mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
216 lines
8.4 KiB
C
216 lines
8.4 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_SSI_H
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#define _HARDWARE_STRUCTS_SSI_H
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/**
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* \file rp2040/ssi.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/ssi.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/ssi.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0
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// Control register 0
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// 0x01000000 [24] SSTE (0) Slave select toggle enable
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// 0x00600000 [22:21] SPI_FRF (0x0) SPI frame format
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// 0x001f0000 [20:16] DFS_32 (0x00) Data frame size in 32b transfer mode +
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// 0x0000f000 [15:12] CFS (0x0) Control frame size +
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// 0x00000800 [11] SRL (0) Shift register loop (test mode)
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// 0x00000400 [10] SLV_OE (0) Slave output enable
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// 0x00000300 [9:8] TMOD (0x0) Transfer mode
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// 0x00000080 [7] SCPOL (0) Serial clock polarity
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// 0x00000040 [6] SCPH (0) Serial clock phase
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// 0x00000030 [5:4] FRF (0x0) Frame format
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// 0x0000000f [3:0] DFS (0x0) Data frame size
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io_rw_32 ctrlr0;
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_REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1
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// Master Control register 1
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// 0x0000ffff [15:0] NDF (0x0000) Number of data frames
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io_rw_32 ctrlr1;
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_REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR
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// SSI Enable
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// 0x00000001 [0] SSI_EN (0) SSI enable
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io_rw_32 ssienr;
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_REG_(SSI_MWCR_OFFSET) // SSI_MWCR
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// Microwire Control
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// 0x00000004 [2] MHS (0) Microwire handshaking
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// 0x00000002 [1] MDD (0) Microwire control
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// 0x00000001 [0] MWMOD (0) Microwire transfer mode
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io_rw_32 mwcr;
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_REG_(SSI_SER_OFFSET) // SSI_SER
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// Slave enable
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// 0x00000001 [0] SER (0) For each bit: +
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io_rw_32 ser;
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_REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR
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// Baud rate
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// 0x0000ffff [15:0] SCKDV (0x0000) SSI clock divider
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io_rw_32 baudr;
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_REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR
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// TX FIFO threshold level
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// 0x000000ff [7:0] TFT (0x00) Transmit FIFO threshold
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io_rw_32 txftlr;
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_REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR
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// RX FIFO threshold level
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// 0x000000ff [7:0] RFT (0x00) Receive FIFO threshold
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io_rw_32 rxftlr;
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_REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR
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// TX FIFO level
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// 0x000000ff [7:0] TFTFL (0x00) Transmit FIFO level
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io_ro_32 txflr;
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_REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR
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// RX FIFO level
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// 0x000000ff [7:0] RXTFL (0x00) Receive FIFO level
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io_ro_32 rxflr;
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_REG_(SSI_SR_OFFSET) // SSI_SR
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// Status register
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// 0x00000040 [6] DCOL (0) Data collision error
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// 0x00000020 [5] TXE (0) Transmission error
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// 0x00000010 [4] RFF (0) Receive FIFO full
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// 0x00000008 [3] RFNE (0) Receive FIFO not empty
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// 0x00000004 [2] TFE (0) Transmit FIFO empty
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// 0x00000002 [1] TFNF (0) Transmit FIFO not full
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// 0x00000001 [0] BUSY (0) SSI busy flag
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io_ro_32 sr;
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_REG_(SSI_IMR_OFFSET) // SSI_IMR
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// Interrupt mask
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// 0x00000020 [5] MSTIM (0) Multi-master contention interrupt mask
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// 0x00000010 [4] RXFIM (0) Receive FIFO full interrupt mask
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// 0x00000008 [3] RXOIM (0) Receive FIFO overflow interrupt mask
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// 0x00000004 [2] RXUIM (0) Receive FIFO underflow interrupt mask
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// 0x00000002 [1] TXOIM (0) Transmit FIFO overflow interrupt mask
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// 0x00000001 [0] TXEIM (0) Transmit FIFO empty interrupt mask
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io_rw_32 imr;
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_REG_(SSI_ISR_OFFSET) // SSI_ISR
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// Interrupt status
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// 0x00000020 [5] MSTIS (0) Multi-master contention interrupt status
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// 0x00000010 [4] RXFIS (0) Receive FIFO full interrupt status
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// 0x00000008 [3] RXOIS (0) Receive FIFO overflow interrupt status
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// 0x00000004 [2] RXUIS (0) Receive FIFO underflow interrupt status
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// 0x00000002 [1] TXOIS (0) Transmit FIFO overflow interrupt status
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// 0x00000001 [0] TXEIS (0) Transmit FIFO empty interrupt status
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io_ro_32 isr;
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_REG_(SSI_RISR_OFFSET) // SSI_RISR
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// Raw interrupt status
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// 0x00000020 [5] MSTIR (0) Multi-master contention raw interrupt status
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// 0x00000010 [4] RXFIR (0) Receive FIFO full raw interrupt status
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// 0x00000008 [3] RXOIR (0) Receive FIFO overflow raw interrupt status
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// 0x00000004 [2] RXUIR (0) Receive FIFO underflow raw interrupt status
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// 0x00000002 [1] TXOIR (0) Transmit FIFO overflow raw interrupt status
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// 0x00000001 [0] TXEIR (0) Transmit FIFO empty raw interrupt status
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io_ro_32 risr;
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_REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR
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// TX FIFO overflow interrupt clear
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// 0x00000001 [0] TXOICR (0) Clear-on-read transmit FIFO overflow interrupt
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io_ro_32 txoicr;
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_REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR
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// RX FIFO overflow interrupt clear
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// 0x00000001 [0] RXOICR (0) Clear-on-read receive FIFO overflow interrupt
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io_ro_32 rxoicr;
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_REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR
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// RX FIFO underflow interrupt clear
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// 0x00000001 [0] RXUICR (0) Clear-on-read receive FIFO underflow interrupt
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io_ro_32 rxuicr;
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_REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR
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// Multi-master interrupt clear
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// 0x00000001 [0] MSTICR (0) Clear-on-read multi-master contention interrupt
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io_ro_32 msticr;
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_REG_(SSI_ICR_OFFSET) // SSI_ICR
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// Interrupt clear
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// 0x00000001 [0] ICR (0) Clear-on-read all active interrupts
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io_ro_32 icr;
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_REG_(SSI_DMACR_OFFSET) // SSI_DMACR
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// DMA control
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// 0x00000002 [1] TDMAE (0) Transmit DMA enable
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// 0x00000001 [0] RDMAE (0) Receive DMA enable
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io_rw_32 dmacr;
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_REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR
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// DMA TX data level
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// 0x000000ff [7:0] DMATDL (0x00) Transmit data watermark level
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io_rw_32 dmatdlr;
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_REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR
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// DMA RX data level
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// 0x000000ff [7:0] DMARDL (0x00) Receive data watermark level (DMARDLR+1)
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io_rw_32 dmardlr;
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_REG_(SSI_IDR_OFFSET) // SSI_IDR
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// Identification register
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// 0xffffffff [31:0] IDCODE (0x51535049) Peripheral dentification code
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io_ro_32 idr;
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_REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID
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// Version ID
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// 0xffffffff [31:0] SSI_COMP_VERSION (0x3430312a) SNPS component version (format X
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io_ro_32 ssi_version_id;
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_REG_(SSI_DR0_OFFSET) // SSI_DR0
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// Data Register 0 (of 36)
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// 0xffffffff [31:0] DR (0x00000000) First data register of 36
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io_rw_32 dr0;
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uint32_t _pad0[35];
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_REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY
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// RX sample delay
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// 0x000000ff [7:0] RSD (0x00) RXD sample delay (in SCLK cycles)
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io_rw_32 rx_sample_dly;
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_REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0
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// SPI control
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// 0xff000000 [31:24] XIP_CMD (0x03) SPI Command to send in XIP mode (INST_L = 8-bit) or to...
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// 0x00040000 [18] SPI_RXDS_EN (0) Read data strobe enable
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// 0x00020000 [17] INST_DDR_EN (0) Instruction DDR transfer enable
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// 0x00010000 [16] SPI_DDR_EN (0) SPI DDR transfer enable
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// 0x0000f800 [15:11] WAIT_CYCLES (0x00) Wait cycles between control frame transmit and data...
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// 0x00000300 [9:8] INST_L (0x0) Instruction length (0/4/8/16b)
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// 0x0000003c [5:2] ADDR_L (0x0) Address length (0b-60b in 4b increments)
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// 0x00000003 [1:0] TRANS_TYPE (0x0) Address and instruction transfer format
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io_rw_32 spi_ctrlr0;
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_REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE
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// TX drive edge
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// 0x000000ff [7:0] TDE (0x00) TXD drive edge
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io_rw_32 txd_drive_edge;
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} ssi_hw_t;
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#define ssi_hw ((ssi_hw_t *)XIP_SSI_BASE)
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static_assert(sizeof (ssi_hw_t) == 0x00fc, "");
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#endif // _HARDWARE_STRUCTS_SSI_H
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