mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
stm32: Add support for flashing stm32h7 boards
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
Eric Callahan
parent
3076dd081c
commit
88e208a083
@ -36,6 +36,9 @@ set_bootup_code(uint64_t code)
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uint64_t *req_code = (void*)&_stack_end;
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*req_code = code;
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barrier();
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#if __CORTEX_M >= 7
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SCB_CleanDCache_by_Addr((void*)req_code, sizeof(*req_code));
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#endif
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}
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#pragma GCC diagnostic pop
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@ -18,5 +18,8 @@ try_request_canboot(void)
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uint64_t *req_sig = (uint64_t *)bl_vectors[0];
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irq_disable();
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*req_sig = REQUEST_CANBOOT;
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#if __CORTEX_M >= 7
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SCB_CleanDCache_by_Addr((void*)req_sig, sizeof(*req_sig));
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#endif
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NVIC_SystemReset();
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}
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@ -76,10 +76,10 @@ choice
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bool "STM32G431" if 0
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select MACH_STM32G4
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config MACH_STM32H723
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bool "STM32H723" if 0
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bool "STM32H723"
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select MACH_STM32H7
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config MACH_STM32H743
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bool "STM32H743" if 0
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bool "STM32H743"
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select MACH_STM32H7
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config MACH_STM32H750
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bool "STM32H750" if 0
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@ -184,6 +184,7 @@ config FLASH_BOOT_ADDRESS
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config RAM_START
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hex
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default 0x24000000 if MACH_STM32H7 # Use "AXI SRAM" to persist reboot flag
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default 0x20000000
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config RAM_SIZE
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@ -478,6 +479,8 @@ config FLASH_START
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choice
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prompt "Application start offset"
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config STM32_APP_START_20000
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bool "128KiB offset" if MACH_STM32H7
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config STM32_APP_START_8000
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bool "32KiB offset" if MACH_STM32F2 || MACH_STM32F4
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config STM32_APP_START_4000
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@ -490,6 +493,7 @@ endchoice
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config LAUNCH_APP_ADDRESS
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hex
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default 0x8020000 if STM32_APP_START_20000
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default 0x8008000 if STM32_APP_START_8000
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default 0x8004000 if STM32_APP_START_4000
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default 0x8002000 if STM32_APP_START_2000
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@ -9,6 +9,7 @@ dirs-$(CONFIG_MACH_STM32F1) += lib/stm32f1
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dirs-$(CONFIG_MACH_STM32F2) += lib/stm32f2
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dirs-$(CONFIG_MACH_STM32F4) += lib/stm32f4
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dirs-$(CONFIG_MACH_STM32G0) += lib/stm32g0
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dirs-$(CONFIG_MACH_STM32H7) += lib/stm32h7
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MCU := $(shell echo $(CONFIG_MCU))
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MCU_UPPER := $(shell echo $(CONFIG_MCU) | tr a-z A-Z | tr X x)
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@ -18,6 +19,7 @@ CFLAGS-$(CONFIG_MACH_STM32F1) += -mcpu=cortex-m3 -Ilib/stm32f1/include
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CFLAGS-$(CONFIG_MACH_STM32F2) += -mcpu=cortex-m3 -Ilib/stm32f2/include
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CFLAGS-$(CONFIG_MACH_STM32F4) += -mcpu=cortex-m4 -Ilib/stm32f4/include
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CFLAGS-$(CONFIG_MACH_STM32G0) += -mcpu=cortex-m0plus -Ilib/stm32g0/include
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CFLAGS-$(CONFIG_MACH_STM32H7) += -mcpu=cortex-m7 -Ilib/stm32h7/include
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CFLAGS += $(CFLAGS-y) -D$(MCU_UPPER) -mthumb -Ilib/cmsis-core -Ilib/fast-hash
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CFLAGS_canboot.elf += --specs=nano.specs --specs=nosys.specs
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@ -45,6 +47,10 @@ mcu-$(CONFIG_MACH_STM32F4) += stm32/gpioperiph.c
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mcu-$(CONFIG_MACH_STM32G0) += stm32/stm32f0_timer.c
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mcu-$(CONFIG_MACH_STM32G0) += stm32/stm32g0.c stm32/gpioperiph.c
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mcu-$(CONFIG_MACH_STM32H7) += ../lib/stm32h7/system_stm32h7xx.c
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mcu-$(CONFIG_MACH_STM32H7) += stm32/stm32h7.c generic/armcm_timer.c
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mcu-$(CONFIG_MACH_STM32H7) += stm32/gpioperiph.c
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src-y += generic/armcm_canboot.c $(mcu-y)
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usb-src-$(CONFIG_HAVE_STM32_USBFS) := stm32/usbfs.c
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usb-src-$(CONFIG_HAVE_STM32_USBOTG) := stm32/usbotg.c
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@ -52,7 +58,7 @@ src-$(CONFIG_USBSERIAL) += $(usb-src-y) stm32/chipid.c generic/usb_cdc.c
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serial-src-y := stm32/serial.c
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serial-src-$(CONFIG_MACH_STM32F0) := stm32/stm32f0_serial.c
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serial-src-$(CONFIG_MACH_STM32G0) := stm32/stm32f0_serial.c
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serial-src-$(CONFIG_MACH_STM32H7) := stm32/stm32h7_serial.c
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serial-src-$(CONFIG_MACH_STM32H7) := stm32/stm32f0_serial.c
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src-$(CONFIG_SERIAL) += $(serial-src-y) generic/serial_irq.c
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canbus-src-y := generic/canserial.c ../lib/fast-hash/fasthash.c
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canbus-src-$(CONFIG_HAVE_STM32_CANBUS) += stm32/can.c
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@ -34,6 +34,8 @@ flash_get_page_size(uint32_t addr)
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return *flash_size <= 64 ? 1024 : 2 * 1024;
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} else if (CONFIG_MACH_STM32G0) {
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return 2 * 1024;
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} else if (CONFIG_MACH_STM32H7) {
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return 128 * 1024;
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}
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}
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@ -48,8 +50,13 @@ check_erased(uint32_t addr, uint32_t count)
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return 1;
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}
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#if CONFIG_MACH_STM32G0 // stm32g0 chip has slightly different bit name
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// Some chips have slightly different register names
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#if CONFIG_MACH_STM32G0
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#define FLASH_SR_BSY (FLASH_SR_BSY1 | FLASH_SR_BSY2)
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#elif CONFIG_MACH_STM32H7
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#define CR CR1
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#define SR SR1
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#define KEYR KEYR1
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#endif
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// Wait for flash hardware to report ready
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@ -114,6 +121,13 @@ erase_page(uint32_t page_address)
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}
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pidx = pidx > 0x3ff ? 0x3ff : pidx;
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FLASH->CR = FLASH_CR_PER | FLASH_CR_STRT | (pidx << FLASH_CR_PNB_Pos);
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#elif CONFIG_MACH_STM32H7
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uint32_t snb = (page_address - 0x08000000) / (128 * 1024);
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snb = snb > 7 ? 7 : snb;
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FLASH->CR = FLASH_CR_SER | FLASH_CR_START | (snb << FLASH_CR_SNB_Pos);
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while (FLASH->SR & FLASH_SR_QW)
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;
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SCB_InvalidateDCache_by_Addr((void*)page_address, 128*1024);
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#endif
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wait_flash();
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}
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@ -144,6 +158,23 @@ write_block(uint32_t block_address, uint32_t *data)
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writel(&page[i*2 + 1], data[i*2 + 1]);
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wait_flash();
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}
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#elif CONFIG_MACH_STM32H7
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uint32_t *page = (void*)block_address;
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FLASH->CR = FLASH_CR_PG;
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for (int i = 0; i < CONFIG_BLOCK_SIZE / 32; i++) {
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writel(&page[i*8], data[i*8]);
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writel(&page[i*8 + 1], data[i*8 + 1]);
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writel(&page[i*8 + 2], data[i*8 + 2]);
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writel(&page[i*8 + 3], data[i*8 + 3]);
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writel(&page[i*8 + 4], data[i*8 + 4]);
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writel(&page[i*8 + 5], data[i*8 + 5]);
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writel(&page[i*8 + 6], data[i*8 + 6]);
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writel(&page[i*8 + 7], data[i*8 + 7]);
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while (FLASH->SR & FLASH_SR_QW)
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;
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wait_flash();
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}
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SCB_InvalidateDCache_by_Addr((void*)block_address, CONFIG_BLOCK_SIZE);
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#endif
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}
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241
src/stm32/stm32h7.c
Normal file
241
src/stm32/stm32h7.c
Normal file
@ -0,0 +1,241 @@
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// Code to setup clocks on stm32h7
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//
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// Copyright (C) 2020 Konstantin Vogel <konstantin.vogel@gmx.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
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#include "board/armcm_boot.h" // VectorTable
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#include "board/armcm_reset.h" // try_request_canboot
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#include "board/irq.h" // irq_disable
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#include "board/misc.h" // bootloader_request
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // get_pclock_frequency
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#include "sched.h" // sched_main
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/****************************************************************
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* Clock setup
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****************************************************************/
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 4)
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// Map a peripheral address to its enable bits
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struct cline
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lookup_clock_line(uint32_t periph_base)
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{
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if (periph_base >= D3_AHB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D3_AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB4ENR, .rst=&RCC->AHB4RSTR, .bit=bit};
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} else if (periph_base >= D3_APB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D3_APB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB4ENR, .rst=&RCC->APB4RSTR, .bit=bit};
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} else if (periph_base >= D1_AHB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D1_AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB3ENR, .rst=&RCC->AHB3RSTR, .bit=bit};
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} else if (periph_base >= D1_APB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D1_APB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB3ENR, .rst=&RCC->APB3RSTR, .bit=bit};
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} else if (periph_base >= D2_AHB2PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D2_AHB2PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB2ENR, .rst=&RCC->AHB2RSTR, .bit=bit};
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} else if (periph_base >= D2_AHB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D2_AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB1ENR, .rst=&RCC->AHB1RSTR, .bit=bit};
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} else if (periph_base >= D2_APB2PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D2_APB2PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit};
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} else {
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uint32_t offset = ((periph_base - D2_APB1PERIPH_BASE) / 0x400);
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if (offset < 32) {
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uint32_t bit = 1 << offset;
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return (struct cline){
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.en=&RCC->APB1LENR, .rst=&RCC->APB1LRSTR, .bit=bit};
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} else {
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uint32_t bit = 1 << (offset - 32);
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return (struct cline){
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.en=&RCC->APB1HENR, .rst=&RCC->APB1HRSTR, .bit=bit};
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}
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}
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}
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// Return the frequency of the given peripheral clock
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uint32_t
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get_pclock_frequency(uint32_t periph_base)
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{
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return FREQ_PERIPH;
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}
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// Enable a GPIO peripheral clock
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void
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gpio_clock_enable(GPIO_TypeDef *regs)
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{
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uint32_t pos = ((uint32_t)regs - D3_AHB1PERIPH_BASE) / 0x400;
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RCC->AHB4ENR |= (1<<pos);
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RCC->AHB4ENR;
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}
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#if !CONFIG_STM32_CLOCK_REF_INTERNAL
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DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
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#endif
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// Main clock and power setup called at chip startup
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static void
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clock_setup(void)
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{
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#if !CONFIG_MACH_STM32H723
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// Ensure USB OTG ULPI is not enabled
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CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);
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CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN);
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#endif
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// Set this despite correct defaults.
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// "The software has to program the supply configuration in PWR control
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// register 3" (pg. 259)
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// Only a single write is allowed (pg. 304)
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PWR->CR3 = (PWR->CR3 | PWR_CR3_LDOEN) & ~(PWR_CR3_BYPASS | PWR_CR3_SCUEN);
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while (!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY))
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;
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// (HSE 25mhz) /DIVM1(5) (pll_base 5Mhz) *DIVN1(192) (pll_freq 960Mhz)
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// /DIVP1(2) (SYSCLK 480Mhz)
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uint32_t pll_base = 5000000;
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// Only even dividers (DIVP1) are allowed
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uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2;
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if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
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// Configure PLL from external crystal (HSE)
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RCC->CR |= RCC_CR_HSEON;
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while(!(RCC->CR & RCC_CR_HSERDY))
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;
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC_Msk,
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RCC_PLLCKSELR_PLLSRC_HSE);
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1_Msk,
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(CONFIG_CLOCK_REF_FREQ/pll_base) << RCC_PLLCKSELR_DIVM1_Pos);
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} else {
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// Configure PLL from internal 64Mhz oscillator (HSI)
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// HSI frequency of 64Mhz is integer divisible with 4Mhz
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pll_base = 4000000;
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC_Msk,
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RCC_PLLCKSELR_PLLSRC_HSI);
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1_Msk,
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(64000000/pll_base) << RCC_PLLCKSELR_DIVM1_Pos);
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}
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// Set input frequency range of PLL1 according to pll_base
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// 3 = 8-16Mhz, 2 = 4-8Mhz
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE_Msk, RCC_PLLCFGR_PLL1RGE_2);
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// Disable unused PLL1 outputs
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN_Msk, 0);
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// Enable PLL1Q and set to 100MHz for SPI 1,2,3
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN, RCC_PLLCFGR_DIVQ1EN);
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MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1,
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(pll_freq / FREQ_PERIPH - 1) << RCC_PLL1DIVR_Q1_Pos);
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// This is necessary, default is not 1!
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN_Msk, RCC_PLLCFGR_DIVP1EN);
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// Set multiplier DIVN1 and post divider DIVP1
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// 001 = /2, 010 = not allowed, 0011 = /4 ...
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MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1_Msk,
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(pll_freq/pll_base - 1) << RCC_PLL1DIVR_N1_Pos);
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MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1_Msk,
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(pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLL1DIVR_P1_Pos);
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// Pwr
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MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS_Msk, PWR_D3CR_VOS);
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while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
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;
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// Enable VOS0 (overdrive)
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if (CONFIG_CLOCK_FREQ > 400000000) {
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RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;
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#if !CONFIG_MACH_STM32H723
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SYSCFG->PWRCR |= SYSCFG_PWRCR_ODEN;
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#else
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PWR->CR3 |= PWR_CR3_BYPASS;
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#endif
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while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
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;
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}
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SCB_EnableICache();
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SCB_EnableDCache();
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// Set flash latency according to clock frequency (pg.159)
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uint32_t flash_acr_latency = (CONFIG_CLOCK_FREQ > 450000000) ?
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FLASH_ACR_LATENCY_4WS : FLASH_ACR_LATENCY_2WS;
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY_Msk, flash_acr_latency);
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MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ_Msk, FLASH_ACR_WRHIGHFREQ_1);
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while (!(FLASH->ACR & flash_acr_latency))
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;
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// Set HPRE, D1PPRE, D2PPRE, D2PPRE2, D3PPRE dividers
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// 480MHz / 2 = 240MHz rcc_hclk3
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MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_D1CFGR_HPRE_3);
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// 240MHz / 2 = 120MHz rcc_pclk3
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MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_D1CFGR_D1PPRE_DIV2);
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// 240MHz / 2 = 120MHz rcc_pclk1
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MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, RCC_D2CFGR_D2PPRE1_DIV2);
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// 240MHz / 2 = 120MHz rcc_pclk2
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MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, RCC_D2CFGR_D2PPRE2_DIV2);
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// 240MHz / 2 = 120MHz rcc_pclk4
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MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, RCC_D3CFGR_D3PPRE_DIV2);
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// Switch on PLL1
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RCC->CR |= RCC_CR_PLL1ON;
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while (!(RCC->CR & RCC_CR_PLL1RDY))
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;
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// Switch system clock source (SYSCLK) to PLL1
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW_Msk, RCC_CFGR_SW_PLL1);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL1)
|
||||
;
|
||||
|
||||
// Set the source of FDCAN clock
|
||||
MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, RCC_D2CCIP1R_FDCANSEL_0);
|
||||
|
||||
// Configure HSI48 clock for USB
|
||||
if (CONFIG_USB) {
|
||||
SET_BIT(RCC->CR, RCC_CR_HSI48ON);
|
||||
while((RCC->CR & RCC_CR_HSI48RDY) == 0);
|
||||
SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);
|
||||
SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_CRSRST);
|
||||
CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_CRSRST);
|
||||
CLEAR_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC);
|
||||
SET_BIT(CRS->CR, CRS_CR_CEN | CRS_CR_AUTOTRIMEN);
|
||||
CLEAR_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL);
|
||||
SET_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Bootloader
|
||||
****************************************************************/
|
||||
|
||||
// Handle reboot requests
|
||||
void
|
||||
bootloader_request(void)
|
||||
{
|
||||
try_request_canboot();
|
||||
dfu_reboot();
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Startup
|
||||
****************************************************************/
|
||||
|
||||
// Main entry point - called from armcm_boot.c:ResetHandler()
|
||||
void
|
||||
armcm_main(void)
|
||||
{
|
||||
// Run SystemInit() and then restore VTOR
|
||||
SystemInit();
|
||||
RCC->D1CCIPR = 0x00000000;
|
||||
RCC->D2CCIP1R = 0x00000000;
|
||||
RCC->D2CCIP2R = 0x00000000;
|
||||
RCC->D3CCIPR = 0x00000000;
|
||||
SCB->VTOR = (uint32_t)VectorTable;
|
||||
|
||||
dfu_reboot_check();
|
||||
|
||||
clock_setup();
|
||||
|
||||
sched_main();
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user