mirror of
https://github.com/andreili/katapult.git
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stm32: sync low level code with klipper
Signed-off-by: Eric Callahan <arksine.code@gmail.com>
This commit is contained in:
Eric Callahan
parent
49e93194a4
commit
3e3ca24beb
@ -60,16 +60,23 @@
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|| CONFIG_STM32_CANBUS_PB5_PB6 ||CONFIG_STM32_CANBUS_PB12_PB13)
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#define SOC_CAN FDCAN1
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#define MSG_RAM (((struct fdcan_ram_layout*)SRAMCAN_BASE)->fdcan1)
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#if CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32G4
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#define CAN_IT0_IRQn FDCAN1_IT0_IRQn
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#endif
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#else
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#define SOC_CAN FDCAN2
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#define MSG_RAM (((struct fdcan_ram_layout*)SRAMCAN_BASE)->fdcan2)
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#if CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32G4
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#define CAN_IT0_IRQn FDCAN2_IT0_IRQn
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#endif
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#endif
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#if CONFIG_MACH_STM32G0
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#define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn
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#define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number
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#elif CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32G4
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#define CAN_IT0_IRQn FDCAN1_IT0_IRQn
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#endif
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#if CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32G4
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#define CAN_FUNCTION GPIO_FUNCTION(9) // Alternative function mapping number
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#endif
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@ -162,10 +169,10 @@ canhw_set_filter(uint32_t id)
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can_filter(1, id);
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can_filter(2, id + 1);
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#if CONFIG_MACH_STM32G0
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#if CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32G4
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SOC_CAN->RXGFC = ((id ? 3 : 1) << FDCAN_RXGFC_LSS_Pos
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| 0x02 << FDCAN_RXGFC_ANFS_Pos);
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#elif CONFIG_MACH_STM32H7 || CONFIG_MAC_STM32G4
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#elif CONFIG_MACH_STM32H7
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uint32_t flssa = (uint32_t)MSG_RAM.FLS - SRAMCAN_BASE;
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SOC_CAN->SIDFC = flssa | ((id ? 3 : 1) << FDCAN_SIDFC_LSS_Pos);
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SOC_CAN->GFC = 0x02 << FDCAN_GFC_ANFS_Pos;
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@ -293,7 +300,7 @@ can_init(void)
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SOC_CAN->NBTP = btr;
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#if CONFIG_MACH_STM32H7 || CONFIG_MAC_STM32G4
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#if CONFIG_MACH_STM32H7
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/* Setup message RAM addresses */
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uint32_t f0sa = (uint32_t)MSG_RAM.RXF0 - SRAMCAN_BASE;
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SOC_CAN->RXF0C = f0sa | (ARRAY_SIZE(MSG_RAM.RXF0) << FDCAN_RXF0C_F0S_Pos);
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@ -68,7 +68,7 @@
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD9,PD8");
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#define GPIO_Rx GPIO('D', 9)
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#define GPIO_Tx GPIO('D', 8)
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#define USARTx_FUNCTION GPIO_FUNCTION(7)
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#define USARTx_FUNCTION GPIO_FUNCTION(CONFIG_MACH_STM32G0 ? 0 : 7)
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#define USARTx USART3
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#define USARTx_IRQn USART3_IRQn
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#elif CONFIG_STM32_SERIAL_UART4
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@ -78,6 +78,13 @@
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#define USARTx_FUNCTION GPIO_FUNCTION(8)
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#define USARTx UART4
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#define USARTx_IRQn UART4_IRQn
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#elif CONFIG_STM32_SERIAL_USART5
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD2,PD3");
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#define GPIO_Rx GPIO('D', 2)
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#define GPIO_Tx GPIO('D', 3)
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#define USARTx_FUNCTION GPIO_FUNCTION(3)
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#define USARTx USART5
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#define USARTx_IRQn USART5_IRQn
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#endif
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#if CONFIG_MACH_STM32F031
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@ -90,6 +97,17 @@
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// Some of the stm32g0 MCUs have slightly different register names
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#if CONFIG_MACH_STM32G0B1
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#define USART2_IRQn USART2_LPUART2_IRQn
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#define USART3_IRQn USART3_4_5_6_LPUART1_IRQn
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#define USART4_IRQn USART3_4_5_6_LPUART1_IRQn
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#define USART5_IRQn USART3_4_5_6_LPUART1_IRQn
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#define USART6_IRQn USART3_4_5_6_LPUART1_IRQn
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#endif
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#if CONFIG_MACH_STM32G0B0
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#define USART2_IRQn USART2_IRQn
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#define USART3_IRQn USART3_4_5_6_IRQn
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#define USART4_IRQn USART3_4_5_6_IRQn
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#define USART5_IRQn USART3_4_5_6_IRQn
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#define USART6_IRQn USART3_4_5_6_IRQn
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#endif
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#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
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#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
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@ -32,18 +32,30 @@ lookup_clock_line(uint32_t periph_base)
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uint32_t bit = 1 << ((periph_base - AHBPERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHBENR, .rst=&RCC->AHBRSTR, .bit=bit};
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}
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#ifdef USART5_BASE
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if (periph_base == USART5_BASE)
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<8};
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#endif
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#ifdef USART6_BASE
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if (periph_base == USART6_BASE)
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<9};
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#endif
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#if defined(FDCAN1_BASE) || defined(FDCAN2_BASE)
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if ((periph_base == FDCAN1_BASE) || (periph_base == FDCAN2_BASE))
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<12};
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#endif
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#ifdef USB_BASE
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if (periph_base == USB_BASE)
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<13};
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#endif
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#ifdef CRS_BASE
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if (periph_base == CRS_BASE)
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<16};
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#endif
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#ifdef I2C3_BASE
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if (periph_base == I2C3_BASE)
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<23};
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#endif
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if (periph_base == TIM1_BASE)
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return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<11};
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if (periph_base == SPI1_BASE)
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@ -106,8 +118,11 @@ clock_setup(void)
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}
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pllcfgr |= (pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos;
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pllcfgr |= (pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLLCFGR_PLLR_Pos;
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pllcfgr |= (pll_freq/FREQ_USB - 1) << RCC_PLLCFGR_PLLQ_Pos;
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RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN;
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#ifdef RCC_PLLCFGR_PLLQ
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pllcfgr |= ((pll_freq/FREQ_USB - 1) << RCC_PLLCFGR_PLLQ_Pos)
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| RCC_PLLCFGR_PLLQEN;
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#endif
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RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN;
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RCC->CR |= RCC_CR_PLLON;
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// Wait for PLL lock
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@ -119,8 +134,10 @@ clock_setup(void)
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != (2 << RCC_CFGR_SWS_Pos))
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;
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#ifdef USB_BASE
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// Use PLLQCLK for USB (setting USBSEL=2 works in practice)
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RCC->CCIPR2 = 2 << RCC_CCIPR2_USBSEL_Pos;
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#endif
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}
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@ -40,6 +40,9 @@ lookup_clock_line(uint32_t periph_base)
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uint32_t bit = 1 << ((periph_base - D2_AHB2PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB2ENR, .rst=&RCC->AHB2RSTR, .bit=bit};
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} else if (periph_base >= D2_AHB1PERIPH_BASE) {
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if (periph_base == ADC12_COMMON_BASE)
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return (struct cline){.en = &RCC->AHB1ENR, .rst = &RCC->AHB1RSTR,
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.bit = RCC_AHB1ENR_ADC12EN};
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uint32_t bit = 1 << ((periph_base - D2_AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB1ENR, .rst=&RCC->AHB1RSTR, .bit=bit};
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} else if (periph_base >= D2_APB2PERIPH_BASE) {
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@ -231,6 +234,12 @@ armcm_main(void)
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RCC->D2CCIP1R = 0x00000000;
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RCC->D2CCIP2R = 0x00000000;
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RCC->D3CCIPR = 0x00000000;
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RCC->APB1LENR = 0x00000000;
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RCC->APB1HENR = 0x00000000;
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RCC->APB2ENR = 0x00000000;
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RCC->APB3ENR = 0x00000000;
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RCC->APB4ENR = 0x00000000;
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SCB->VTOR = (uint32_t)VectorTable;
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dfu_reboot_check();
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@ -1,6 +1,6 @@
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// Hardware interface to "fullspeed USB controller"
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//
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// Copyright (C) 2018-2021 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2018-2023 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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@ -15,7 +15,7 @@
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#include "internal.h" // GPIO
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#include "sched.h" // DECL_INIT
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#if CONFIG_MACH_STM32F103 || CONFIG_MACH_STM32G4
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#if CONFIG_MACH_STM32F1
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// Transfer memory is accessed with 32bits, but contains only 16bits of data
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typedef volatile uint32_t epmword_t;
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#define WSIZE 2
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@ -25,6 +25,11 @@
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typedef volatile uint16_t epmword_t;
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#define WSIZE 2
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#define USBx_IRQn USB_IRQn
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#elif CONFIG_MACH_STM32G4
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// Transfer memory is accessed with 16bits and contains 16bits of data
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typedef volatile uint16_t epmword_t;
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#define WSIZE 2
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#define USBx_IRQn USB_LP_IRQn
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#elif CONFIG_MACH_STM32G0
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// Transfer memory is accessed with 32bits and contains 32bits of data
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typedef volatile uint32_t epmword_t;
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@ -48,6 +53,12 @@
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#define USB_CNTR_FRES USB_CNTR_USBRST
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#endif
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// Some chip variants do not define these fields
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#ifndef USB_EP_DTOG_TX_Pos
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#define USB_EP_DTOG_TX_Pos 6
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#define USB_EP_DTOG_RX_Pos 14
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#endif
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/****************************************************************
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* USB transfer memory
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@ -55,52 +66,50 @@
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// Layout of the USB transfer memory
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#define EPM ((epmword_t*)USB_PMAADDR)
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#define EPM_EP_DESC(ep) (&EPM[(ep) * (8 / WSIZE)])
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#define EPM_EP_DESC(ep, bufnum) (&EPM[((ep)*2 + (bufnum)) * (4 / WSIZE)])
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#define EPM_BUF_OFFSET 0x10
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#define EPM_EP_BUF_SIZE (64 / WSIZE + 1)
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#define EPM_EP_TX_BUF(ep) (&EPM[EPM_BUF_OFFSET + (ep)*2*EPM_EP_BUF_SIZE])
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#define EPM_EP_RX_BUF(ep) (&EPM[EPM_BUF_OFFSET + (1+(ep)*2)*EPM_EP_BUF_SIZE])
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#define EPM_EP_BUF(ep, bufnum) \
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(&EPM[EPM_BUF_OFFSET + ((ep)*2 + (bufnum)) * EPM_EP_BUF_SIZE])
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#define BUFTX 0
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#define BUFRX 1
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// Configure the usb descriptor for an endpoint
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static void
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epm_ep_desc_setup(int ep, int rx_size)
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epm_ep_desc_setup(int ep, int bufnum, int rx_size)
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{
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uint32_t addr_tx = (EPM_EP_TX_BUF(ep) - EPM) * WSIZE, count_tx = 0;
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uint32_t addr_rx = (EPM_EP_RX_BUF(ep) - EPM) * WSIZE;
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uint32_t addr = (EPM_EP_BUF(ep, bufnum) - EPM) * WSIZE;
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uint32_t count_rx = (rx_size <= 30 ? DIV_ROUND_UP(rx_size, 2) << 10
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: ((DIV_ROUND_UP(rx_size, 32) - 1) << 10) | 0x8000);
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epmword_t *desc = EPM_EP_DESC(ep);
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epmword_t *desc = EPM_EP_DESC(ep, bufnum);
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if (WSIZE == 2) {
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desc[0] = addr_tx;
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desc[1] = count_tx;
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desc[2] = addr_rx;
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desc[3] = count_rx;
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desc[0] = addr;
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desc[1] = count_rx;
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} else {
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desc[0] = addr_tx | (count_tx << 16);
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desc[1] = addr_rx | (count_rx << 16);
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*desc = addr | (count_rx << 16);
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}
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}
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// Return number of read bytes on an rx endpoint
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static uint32_t
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epm_get_ep_count_rx(int ep)
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epm_get_ep_count_rx(int ep, int bufnum)
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{
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epmword_t *desc = EPM_EP_DESC(ep);
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epmword_t *desc = EPM_EP_DESC(ep, bufnum);
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if (WSIZE == 2)
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return desc[3] & 0x3ff;
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return (desc[1] >> 16) & 0x3ff;
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return desc[1] & 0x3ff;
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return (*desc >> 16) & 0x3ff;
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}
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// Set number of bytes ready to be transmitted on a tx endpoint
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static void
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epm_set_ep_count_tx(int ep, uint32_t count)
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epm_set_ep_count_tx(int ep, int bufnum, uint32_t count)
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{
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epmword_t *desc = EPM_EP_DESC(ep);
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epmword_t *desc = EPM_EP_DESC(ep, bufnum);
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if (WSIZE == 2) {
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desc[1] = count;
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} else {
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uint32_t addr_tx = (EPM_EP_TX_BUF(ep) - EPM) * WSIZE;
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desc[0] = addr_tx | (count << 16);
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uint32_t addr_tx = (EPM_EP_BUF(ep, bufnum) - EPM) * WSIZE;
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*desc = addr_tx | (count << 16);
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}
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}
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@ -108,18 +117,22 @@ epm_set_ep_count_tx(int ep, uint32_t count)
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static void
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btable_configure(void)
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{
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epm_ep_desc_setup(0, USB_CDC_EP0_SIZE);
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epm_ep_desc_setup(USB_CDC_EP_ACM, 0);
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epm_ep_desc_setup(USB_CDC_EP_BULK_OUT, USB_CDC_EP_BULK_OUT_SIZE);
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epm_ep_desc_setup(USB_CDC_EP_BULK_IN, 0);
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epm_ep_desc_setup(0, BUFTX, 0);
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epm_ep_desc_setup(0, BUFRX, USB_CDC_EP0_SIZE);
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epm_ep_desc_setup(USB_CDC_EP_ACM, BUFTX, 0);
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epm_ep_desc_setup(USB_CDC_EP_ACM, BUFRX, 0);
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epm_ep_desc_setup(USB_CDC_EP_BULK_OUT, 0, USB_CDC_EP_BULK_OUT_SIZE);
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epm_ep_desc_setup(USB_CDC_EP_BULK_OUT, 1, USB_CDC_EP_BULK_OUT_SIZE);
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epm_ep_desc_setup(USB_CDC_EP_BULK_IN, 0, 0);
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epm_ep_desc_setup(USB_CDC_EP_BULK_IN, 1, 0);
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}
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// Read a packet stored in dedicated usb memory
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static uint32_t
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btable_read_packet(int ep, uint8_t *dest, int max_len)
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btable_read_packet(int ep, int bufnum, uint8_t *dest, int max_len)
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{
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epmword_t *src = EPM_EP_RX_BUF(ep);
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uint32_t count = epm_get_ep_count_rx(ep);
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epmword_t *src = EPM_EP_BUF(ep, bufnum);
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uint32_t count = epm_get_ep_count_rx(ep, bufnum);
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if (count > max_len)
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count = max_len;
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int i;
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@ -145,9 +158,9 @@ btable_read_packet(int ep, uint8_t *dest, int max_len)
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// Write a packet to dedicated usb memory
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static void
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btable_write_packet(int ep, const uint8_t *src, int count)
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btable_write_packet(int ep, int bufnum, const uint8_t *src, int count)
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{
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epmword_t *dest = EPM_EP_TX_BUF(ep);
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epmword_t *dest = EPM_EP_BUF(ep, bufnum);
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int i;
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for (i=0; i<count/WSIZE; i++) {
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uint8_t b1 = *src++, b2 = *src++, b3 = 0, b4 = 0;
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@ -165,7 +178,7 @@ btable_write_packet(int ep, const uint8_t *src, int count)
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d |= *src++ << 16;
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*dest = d;
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}
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epm_set_ep_count_tx(ep, count);
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epm_set_ep_count_tx(ep, bufnum, count);
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}
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@ -175,26 +188,27 @@ btable_write_packet(int ep, const uint8_t *src, int count)
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#define USB_EPR ((volatile uint32_t *)USB_BASE)
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#define EPR_TBITS (USB_EP_DTOG_RX | USB_EPRX_STAT \
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| USB_EP_DTOG_TX | USB_EPTX_STAT)
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#define EPR_RWBITS (USB_EPADDR_FIELD | USB_EP_KIND | USB_EP_TYPE_MASK)
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#define EPR_RWCBITS (USB_EP_CTR_RX | USB_EP_CTR_TX)
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// Calculate the memory update needed to set the epr register
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static uint32_t
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set_stat_rx_bits(uint32_t epr, uint32_t bits)
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calc_epr_bits(uint32_t epr, uint32_t mask, uint32_t value)
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{
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return ((epr & (EPR_RWBITS | USB_EPRX_STAT)) ^ bits) | EPR_RWCBITS;
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uint32_t tmask = mask & EPR_TBITS, tvalue = value & tmask;
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uint32_t rwmask = mask & EPR_RWBITS, rwbits = value & rwmask;
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uint32_t cbits = EPR_RWCBITS & ~mask;
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||||
return (((epr & (EPR_RWBITS | tmask)) ^ tvalue) & ~rwmask) | rwbits | cbits;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
set_stat_tx_bits(uint32_t epr, uint32_t bits)
|
||||
// Check if double buffering endpoint hardware can no longer send/receive
|
||||
static int
|
||||
epr_is_dbuf_blocking(uint32_t epr)
|
||||
{
|
||||
return ((epr & (EPR_RWBITS | USB_EPTX_STAT)) ^ bits) | EPR_RWCBITS;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
set_stat_rxtx_bits(uint32_t epr, uint32_t bits)
|
||||
{
|
||||
uint32_t mask = EPR_RWBITS | USB_EPRX_STAT | USB_EPTX_STAT;
|
||||
return ((epr & mask) ^ bits) | EPR_RWCBITS;
|
||||
return !(((epr >> (USB_EP_DTOG_RX_Pos - USB_EP_DTOG_TX_Pos)) ^ epr)
|
||||
& USB_EP_DTOG_TX);
|
||||
}
|
||||
|
||||
|
||||
@ -202,39 +216,77 @@ set_stat_rxtx_bits(uint32_t epr, uint32_t bits)
|
||||
* USB interface
|
||||
****************************************************************/
|
||||
|
||||
static uint32_t bulk_out_pop_count, bulk_out_push_flag;
|
||||
|
||||
int_fast8_t
|
||||
usb_read_bulk_out(void *data, uint_fast8_t max_len)
|
||||
{
|
||||
uint32_t epr = USB_EPR[USB_CDC_EP_BULK_OUT];
|
||||
if ((epr & USB_EPRX_STAT) == USB_EP_RX_VALID)
|
||||
if (readl(&bulk_out_push_flag))
|
||||
// No data ready
|
||||
return -1;
|
||||
uint32_t count = btable_read_packet(USB_CDC_EP_BULK_OUT, data, max_len);
|
||||
USB_EPR[USB_CDC_EP_BULK_OUT] = set_stat_rx_bits(epr, USB_EP_RX_VALID);
|
||||
uint32_t ep = USB_CDC_EP_BULK_OUT;
|
||||
int bufnum = bulk_out_pop_count & 1;
|
||||
bulk_out_pop_count++;
|
||||
uint32_t count = btable_read_packet(ep, bufnum, data, max_len);
|
||||
writel(&bulk_out_push_flag, USB_EP_DTOG_TX);
|
||||
|
||||
// Check if irq handler pulled another packet before push flag update
|
||||
uint32_t epr = USB_EPR[ep];
|
||||
if (epr_is_dbuf_blocking(epr) && readl(&bulk_out_push_flag)) {
|
||||
// Second packet was already read - must notify hardware
|
||||
writel(&bulk_out_push_flag, 0);
|
||||
USB_EPR[ep] = calc_epr_bits(epr, 0, 0) | USB_EP_DTOG_TX;
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static uint32_t bulk_in_push_pos, bulk_in_pop_flag;
|
||||
#define BI_START 2
|
||||
|
||||
int_fast8_t
|
||||
usb_send_bulk_in(void *data, uint_fast8_t len)
|
||||
{
|
||||
uint32_t epr = USB_EPR[USB_CDC_EP_BULK_IN];
|
||||
if ((epr & USB_EPTX_STAT) != USB_EP_TX_NAK)
|
||||
if (readl(&bulk_in_pop_flag))
|
||||
// No buffer space available
|
||||
return -1;
|
||||
btable_write_packet(USB_CDC_EP_BULK_IN, data, len);
|
||||
USB_EPR[USB_CDC_EP_BULK_IN] = set_stat_tx_bits(epr, USB_EP_TX_VALID);
|
||||
uint32_t ep = USB_CDC_EP_BULK_IN;
|
||||
uint32_t bipp = bulk_in_push_pos, bufnum = bipp & 1;
|
||||
bulk_in_push_pos = bipp ^ 1;
|
||||
btable_write_packet(ep, bufnum, data, len);
|
||||
writel(&bulk_in_pop_flag, USB_EP_DTOG_RX);
|
||||
|
||||
// Check if hardware needs to be notified
|
||||
uint32_t epr = USB_EPR[ep];
|
||||
if (epr_is_dbuf_blocking(epr) && readl(&bulk_in_pop_flag)) {
|
||||
writel(&bulk_in_pop_flag, 0);
|
||||
if (unlikely(bipp & BI_START)) {
|
||||
// Two packets are always sent when starting in double
|
||||
// buffering mode, so wait for second packet before starting.
|
||||
if (bipp == (BI_START | 1)) {
|
||||
bulk_in_push_pos = 0;
|
||||
writel(&bulk_in_pop_flag, USB_EP_KIND); // Dummy flag
|
||||
USB_EPR[ep] = calc_epr_bits(epr, USB_EPTX_STAT
|
||||
, USB_EP_TX_VALID);
|
||||
}
|
||||
} else {
|
||||
USB_EPR[ep] = calc_epr_bits(epr, 0, 0) | USB_EP_DTOG_RX;
|
||||
}
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
int_fast8_t
|
||||
usb_read_ep0(void *data, uint_fast8_t max_len)
|
||||
{
|
||||
uint32_t epr = USB_EPR[0];
|
||||
uint32_t ep = 0, epr = USB_EPR[ep];
|
||||
if ((epr & USB_EPRX_STAT) != USB_EP_RX_NAK)
|
||||
// No data ready
|
||||
return -1;
|
||||
uint32_t count = btable_read_packet(0, data, max_len);
|
||||
USB_EPR[0] = set_stat_rxtx_bits(epr, USB_EP_RX_VALID | USB_EP_TX_NAK);
|
||||
uint32_t count = btable_read_packet(ep, BUFRX, data, max_len);
|
||||
USB_EPR[ep] = calc_epr_bits(epr, USB_EPRX_STAT | USB_EPTX_STAT
|
||||
, USB_EP_RX_VALID | USB_EP_TX_NAK);
|
||||
return count;
|
||||
}
|
||||
|
||||
@ -247,22 +299,23 @@ usb_read_ep0_setup(void *data, uint_fast8_t max_len)
|
||||
int_fast8_t
|
||||
usb_send_ep0(const void *data, uint_fast8_t len)
|
||||
{
|
||||
uint32_t epr = USB_EPR[0];
|
||||
uint32_t ep = 0, epr = USB_EPR[ep];
|
||||
if ((epr & USB_EPRX_STAT) != USB_EP_RX_VALID)
|
||||
// Transfer interrupted
|
||||
return -2;
|
||||
if ((epr & USB_EPTX_STAT) != USB_EP_TX_NAK)
|
||||
// No buffer space available
|
||||
return -1;
|
||||
btable_write_packet(0, data, len);
|
||||
USB_EPR[0] = set_stat_tx_bits(epr, USB_EP_TX_VALID);
|
||||
btable_write_packet(ep, BUFTX, data, len);
|
||||
USB_EPR[ep] = calc_epr_bits(epr, USB_EPTX_STAT, USB_EP_TX_VALID);
|
||||
return len;
|
||||
}
|
||||
|
||||
void
|
||||
usb_stall_ep0(void)
|
||||
{
|
||||
USB_EPR[0] = set_stat_rxtx_bits(USB_EPR[0]
|
||||
uint32_t ep = 0, epr = USB_EPR[ep];
|
||||
USB_EPR[ep] = calc_epr_bits(epr, USB_EPRX_STAT | USB_EPTX_STAT
|
||||
, USB_EP_RX_STALL | USB_EP_TX_STALL);
|
||||
}
|
||||
|
||||
@ -278,6 +331,13 @@ usb_set_address(uint_fast8_t addr)
|
||||
void
|
||||
usb_set_configure(void)
|
||||
{
|
||||
uint32_t ep = USB_CDC_EP_BULK_OUT;
|
||||
bulk_out_pop_count = 0;
|
||||
USB_EPR[ep] = calc_epr_bits(USB_EPR[ep], USB_EPRX_STAT, USB_EP_RX_VALID);
|
||||
|
||||
ep = USB_CDC_EP_BULK_IN;
|
||||
bulk_in_push_pos = BI_START;
|
||||
writel(&bulk_in_pop_flag, 0);
|
||||
}
|
||||
|
||||
|
||||
@ -289,14 +349,23 @@ usb_set_configure(void)
|
||||
static void
|
||||
usb_reset(void)
|
||||
{
|
||||
USB_EPR[0] = 0 | USB_EP_CONTROL | USB_EP_RX_VALID | USB_EP_TX_NAK;
|
||||
USB_EPR[USB_CDC_EP_ACM] = (USB_CDC_EP_ACM | USB_EP_INTERRUPT
|
||||
| USB_EP_RX_NAK | USB_EP_TX_NAK);
|
||||
USB_EPR[USB_CDC_EP_BULK_OUT] = (USB_CDC_EP_BULK_OUT | USB_EP_BULK
|
||||
| USB_EP_RX_VALID | USB_EP_TX_NAK);
|
||||
USB_EPR[USB_CDC_EP_BULK_IN] = (USB_CDC_EP_BULK_IN | USB_EP_BULK
|
||||
uint32_t ep = 0;
|
||||
USB_EPR[ep] = 0 | USB_EP_CONTROL | USB_EP_RX_VALID | USB_EP_TX_NAK;
|
||||
|
||||
ep = USB_CDC_EP_ACM;
|
||||
USB_EPR[ep] = (USB_CDC_EP_ACM | USB_EP_INTERRUPT
|
||||
| USB_EP_RX_NAK | USB_EP_TX_NAK);
|
||||
|
||||
ep = USB_CDC_EP_BULK_OUT;
|
||||
USB_EPR[ep] = (USB_CDC_EP_BULK_OUT | USB_EP_BULK | USB_EP_KIND
|
||||
| USB_EP_RX_NAK | USB_EP_DTOG_TX);
|
||||
bulk_out_push_flag = USB_EP_DTOG_TX;
|
||||
|
||||
ep = USB_CDC_EP_BULK_IN;
|
||||
USB_EPR[ep] = (USB_CDC_EP_BULK_IN | USB_EP_BULK | USB_EP_KIND
|
||||
| USB_EP_TX_NAK);
|
||||
bulk_in_pop_flag = USB_EP_DTOG_RX;
|
||||
|
||||
USB->CNTR = USB_CNTR_CTRM | USB_CNTR_RESETM;
|
||||
USB->DADDR = USB_DADDR_EF;
|
||||
}
|
||||
@ -308,20 +377,25 @@ USB_IRQHandler(void)
|
||||
uint32_t istr = USB->ISTR;
|
||||
if (istr & USB_ISTR_CTR) {
|
||||
// Endpoint activity
|
||||
uint32_t ep = istr & USB_ISTR_EP_ID;
|
||||
uint32_t epr = USB_EPR[ep];
|
||||
USB_EPR[ep] = epr & EPR_RWBITS;
|
||||
if (ep == 0) {
|
||||
uint32_t ep = istr & USB_ISTR_EP_ID, epr = USB_EPR[ep];
|
||||
if (ep == USB_CDC_EP_BULK_OUT) {
|
||||
USB_EPR[ep] = (calc_epr_bits(epr, USB_EP_CTR_RX | USB_EP_CTR_TX, 0)
|
||||
| bulk_out_push_flag);
|
||||
bulk_out_push_flag = 0;
|
||||
usb_notify_bulk_out();
|
||||
} else if (ep == USB_CDC_EP_BULK_IN) {
|
||||
USB_EPR[ep] = (calc_epr_bits(epr, USB_EP_CTR_RX | USB_EP_CTR_TX, 0)
|
||||
| bulk_in_pop_flag);
|
||||
bulk_in_pop_flag = 0;
|
||||
usb_notify_bulk_in();
|
||||
} else if (ep == 0) {
|
||||
USB_EPR[ep] = calc_epr_bits(epr, USB_EP_CTR_RX | USB_EP_CTR_TX, 0);
|
||||
usb_notify_ep0();
|
||||
if (epr & USB_EP_CTR_TX && set_address) {
|
||||
// Apply address after last "in" message transmitted
|
||||
USB->DADDR = set_address;
|
||||
set_address = 0;
|
||||
}
|
||||
} else if (ep == USB_CDC_EP_BULK_OUT) {
|
||||
usb_notify_bulk_out();
|
||||
} else if (ep == USB_CDC_EP_BULK_IN) {
|
||||
usb_notify_bulk_in();
|
||||
}
|
||||
}
|
||||
if (istr & USB_ISTR_RESET) {
|
||||
|
||||
@ -397,11 +397,11 @@ OTG_FS_IRQHandler(void)
|
||||
}
|
||||
if (sts & USB_OTG_GINTSTS_IEPINT) {
|
||||
// Can transmit data - disable irq and notify endpoint
|
||||
uint32_t daint = OTGD->DAINT;
|
||||
OTGD->DAINTMSK &= ~daint;
|
||||
if (daint & (1 << 0))
|
||||
uint32_t daint = OTGD->DAINT, msk = OTGD->DAINTMSK, pend = daint & msk;
|
||||
OTGD->DAINTMSK = msk & ~daint;
|
||||
if (pend & (1 << 0))
|
||||
usb_notify_ep0();
|
||||
if (daint & (1 << USB_CDC_EP_BULK_IN))
|
||||
if (pend & (1 << USB_CDC_EP_BULK_IN))
|
||||
usb_notify_bulk_in();
|
||||
}
|
||||
}
|
||||
@ -426,7 +426,7 @@ usb_init(void)
|
||||
OTG->GUSBCFG = (USB_OTG_GUSBCFG_FDMOD | USB_OTG_GUSBCFG_PHYSEL
|
||||
| (6 << USB_OTG_GUSBCFG_TRDT_Pos));
|
||||
OTGD->DCFG |= (3 << USB_OTG_DCFG_DSPD_Pos);
|
||||
#if CONFIG_MACH_STM32F446 || CONFIG_MACH_STM32H7
|
||||
#if CONFIG_MACH_STM32F446 || CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32F7
|
||||
OTG->GOTGCTL = USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
|
||||
#else
|
||||
OTG->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user