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module: stm32, sync fdcan with upstream klipper code

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Syncs the stm32 fdcan and Kconfig to enable BTT U2C and PB12/PB13 FDCAN2 support STM32G0B1 with boards such as the BTT E3EZ.

Signed-off-by: Diana Moore <dmoore@xn4p4lm.com>
This commit is contained in:
Diana 2023-12-13 23:29:02 -08:00 committed by Eric Callahan
parent 0ac72fc2c6
commit 3855b34e94
2 changed files with 13 additions and 4 deletions
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6
src/stm32/Kconfig
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@ -392,7 +392,7 @@ choice
select CANSERIAL select CANSERIAL
config STM32_MMENU_CANBUS_PB12_PB13 config STM32_MMENU_CANBUS_PB12_PB13
bool "CAN bus (on PB12/PB13)" if LOW_LEVEL_OPTIONS bool "CAN bus (on PB12/PB13)" if LOW_LEVEL_OPTIONS
depends on HAVE_STM32_CANBUS && MACH_STM32F4 depends on (HAVE_STM32_CANBUS && MACH_STM32F4) || HAVE_STM32_FDCANBUS
select CANSERIAL select CANSERIAL
config STM32_MMENU_CANBUS_PD0_PD1 config STM32_MMENU_CANBUS_PD0_PD1
bool "CAN bus (on PD0/PD1)" if LOW_LEVEL_OPTIONS bool "CAN bus (on PD0/PD1)" if LOW_LEVEL_OPTIONS
@ -424,10 +424,10 @@ choice
depends on HAVE_STM32_CANBUS && MACH_STM32F4 depends on HAVE_STM32_CANBUS && MACH_STM32F4
config STM32_CMENU_CANBUS_PB5_PB6 config STM32_CMENU_CANBUS_PB5_PB6
bool "CAN bus (on PB5/PB6)" bool "CAN bus (on PB5/PB6)"
depends on HAVE_STM32_CANBUS && MACH_STM32F4 depends on (HAVE_STM32_CANBUS && MACH_STM32F4) || (HAVE_STM32_FDCANBUS && MACH_STM32G0B1)
config STM32_CMENU_CANBUS_PB12_PB13 config STM32_CMENU_CANBUS_PB12_PB13
bool "CAN bus (on PB12/PB13)" bool "CAN bus (on PB12/PB13)"
depends on HAVE_STM32_CANBUS && MACH_STM32F4 depends on (HAVE_STM32_CANBUS && MACH_STM32F4) || HAVE_STM32_FDCANBUS
config STM32_CMENU_CANBUS_PD0_PD1 config STM32_CMENU_CANBUS_PD0_PD1
bool "CAN bus (on PD0/PD1)" bool "CAN bus (on PD0/PD1)"
depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS

11
src/stm32/fdcan.c
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@ -46,9 +46,18 @@
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PC2,PC3"); DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PC2,PC3");
#define GPIO_Rx GPIO('C', 2) #define GPIO_Rx GPIO('C', 2)
#define GPIO_Tx GPIO('C', 3) #define GPIO_Tx GPIO('C', 3)
#elif CONFIG_STM32_CANBUS_PB5_PB6
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB5,PB6");
#define GPIO_Rx GPIO('B', 5)
#define GPIO_Tx GPIO('B', 6)
#elif CONFIG_STM32_CANBUS_PB12_PB13
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB12,PB13");
#define GPIO_Rx GPIO('B', 12)
#define GPIO_Tx GPIO('B', 13)
#endif #endif
#if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3) #if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3 \
|| CONFIG_STM32_CANBUS_PB5_PB6 ||CONFIG_STM32_CANBUS_PB12_PB13)
#define SOC_CAN FDCAN1 #define SOC_CAN FDCAN1
#define MSG_RAM (((struct fdcan_ram_layout*)SRAMCAN_BASE)->fdcan1) #define MSG_RAM (((struct fdcan_ram_layout*)SRAMCAN_BASE)->fdcan1)
#else #else