mirror of
https://github.com/andreili/SBC_builder.git
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124 lines
4.6 KiB
Plaintext
124 lines
4.6 KiB
Plaintext
/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/rk3588-power.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/ata/ahci.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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fragment@0 {
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target-path = "/";
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__overlay__ {
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mpp_srv: mpp-srv {
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compatible = "rockchip,mpp-service";
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rockchip,taskqueue-count = <12>;
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};
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};
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};
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fragment@1 {
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target-path = "/";
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__overlay__ {
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rkvenc_ccu: rkvenc-ccu {
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compatible = "rockchip,rkv-encoder-v2-ccu";
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};
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};
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};
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fragment@2 {
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target-path = "/";
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__overlay__ {
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rkvenc0: rkvenc-core@fdbd0000 {
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compatible = "rockchip,rkv-encoder-v2-core";
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reg = <0x0 0xfdbd0000 0x0 0x6000>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "irq_rkvenc0";
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clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
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clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
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rockchip,normal-rates = <600000000>, <0>, <800000000>;
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assigned-clocks = <&cru ACLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
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assigned-clock-rates = <600000000>, <800000000>;
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resets = <&cru SRST_A_RKVENC0>, <&cru SRST_H_RKVENC0>, <&cru SRST_RKVENC0_CORE>;
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reset-names = "video_a", "video_h", "video_core";
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rockchip,skip-pmu-idle-request;
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iommus = <&rkvenc0_mmu>;
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rockchip,srv = <&mpp_srv>;
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rockchip,ccu = <&rkvenc_ccu>;
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rockchip,taskqueue-node = <7>;
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rockchip,task-capacity = <8>;
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power-domains = <&power RK3588_PD_VENC0>;
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};
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};
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};
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fragment@3 {
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target-path = "/";
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__overlay__ {
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rkvenc0_mmu: iommu@fdbdf000 {
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compatible = "rockchip,rk3568-iommu";
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reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>;
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interrupts = <0 99 4 0>, <0 100 4 0>;
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interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1";
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clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>;
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clock-names = "aclk", "iface";
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rockchip,disable-mmu-reset;
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rockchip,enable-cmd-retry;
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rockchip,shootdown-entire;
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#iommu-cells = <0>;
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power-domains = <&power RK3588_PD_VENC0>;
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};
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};
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};
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fragment@4 {
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target-path = "/";
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__overlay__ {
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rkvenc1: rkvenc-core@fdbe0000 {
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compatible = "rockchip,rkv-encoder-v2-core";
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reg = <0x0 0xfdbe0000 0x0 0x6000>;
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interrupts = <0 104 4 0>;
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interrupt-names = "irq_rkvenc1";
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clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
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clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
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rockchip,normal-rates = <600000000>, <0>, <800000000>;
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assigned-clocks = <&cru ACLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
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assigned-clock-rates = <600000000>, <800000000>;
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resets = <&cru SRST_A_RKVENC1>, <&cru SRST_H_RKVENC1>, <&cru SRST_RKVENC1_CORE>;
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reset-names = "video_a", "video_h", "video_core";
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rockchip,skip-pmu-idle-request;
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iommus = <&rkvenc1_mmu>;
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rockchip,srv = <&mpp_srv>;
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rockchip,ccu = <&rkvenc_ccu>;
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rockchip,taskqueue-node = <7>;
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rockchip,task-capacity = <8>;
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power-domains = <&power RK3588_PD_VENC1>;
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};
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};
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};
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fragment@5 {
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target-path = "/";
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__overlay__ {
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rkvenc1_mmu: iommu@fdbef000 {
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compatible = "rockchip,rk3568-iommu";
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reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>;
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interrupts = <0 102 4 0>, <0 103 4 0>;
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interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1";
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clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>;
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clock-names = "aclk", "iface";
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rockchip,disable-mmu-reset;
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rockchip,enable-cmd-retry;
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rockchip,shootdown-entire;
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#iommu-cells = <0>;
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power-domains = <&power RK3588_PD_VENC1>;
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};
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};
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};
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};
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