mirror of
https://github.com/andreili/SBC_builder.git
synced 2025-08-23 11:04:04 +02:00
29 lines
951 B
Diff
29 lines
951 B
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
|
From: Vasily Khoruzhick <anarsoul@gmail.com>
|
|
Date: Mon, 17 Mar 2025 22:22:46 -0700
|
|
Subject: clk: rockchip: rk3568: Add PLL rate for 33.3MHz
|
|
|
|
Add PLL rate for 33.3 MHz to allow BTT HDMI5 screen to run at its native
|
|
mode of 800x480
|
|
|
|
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
|
|
---
|
|
drivers/clk/rockchip/clk-rk3568.c | 1 +
|
|
1 file changed, 1 insertion(+)
|
|
|
|
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
|
|
index 111111111111..222222222222 100644
|
|
--- a/drivers/clk/rockchip/clk-rk3568.c
|
|
+++ b/drivers/clk/rockchip/clk-rk3568.c
|
|
@@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
|
|
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
|
|
RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
|
|
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
|
|
+ RK3036_PLL_RATE(33300000, 4, 111, 5, 4, 1, 0),
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
--
|
|
Armbian
|
|
|