mirror of
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180 lines
6.5 KiB
Diff
180 lines
6.5 KiB
Diff
From acc83b9c1798eb38d27e8bb273d5fd1f79f8c33a Mon Sep 17 00:00:00 2001
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From: Frank Oltmanns <frank@oltmanns.dev>
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Date: Sun, 10 Mar 2024 14:32:29 +0100
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Subject: drm/sun4i: tcon: Support keeping dclk rate upon ancestor clock
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changes
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Allow the dclk to reset its rate when a rate change is initiated from an
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ancestor clock. This makes it possible to no longer to get an exclusive
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lock. As a consequence, it is now possible to set new rates if
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necessary, e.g. when an external display is connected.
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The first user of this functionality is the A64 because PLL-VIDEO0 is an
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ancestor for both HDMI and TCON0. This allows to select an optimal rate
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for TCON0 as long as there is no external HDMI connection. Once a change
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in PLL-VIDEO0 is performed when an HDMI connection is established, TCON0
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can react gracefully and select an optimal rate based on this the new
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constraint.
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Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
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---
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drivers/gpu/drm/sun4i/sun4i_tcon.c | 70 +++++++++++++++++++++++++++---
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drivers/gpu/drm/sun4i/sun4i_tcon.h | 12 +++++
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2 files changed, 76 insertions(+), 6 deletions(-)
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diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
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index fca95b76e258..0a493142b100 100644
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--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
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+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
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@@ -108,9 +108,11 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
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if (enabled) {
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clk_prepare_enable(clk);
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- clk_rate_exclusive_get(clk);
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+ if (!tcon->quirks->restores_rate)
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+ clk_rate_exclusive_get(clk);
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} else {
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- clk_rate_exclusive_put(clk);
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+ if (!tcon->quirks->restores_rate)
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+ clk_rate_exclusive_put(clk);
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clk_disable_unprepare(clk);
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}
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}
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@@ -343,6 +345,53 @@ static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
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regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
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}
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+static void sun4i_rate_reset_notifier_delayed_update(struct work_struct *work)
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+{
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+ struct sun4i_rate_reset_nb *rate_reset = container_of(work, struct sun4i_rate_reset_nb,
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+ reset_rate_work.work);
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+
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+ clk_set_rate(rate_reset->target_clk, rate_reset->saved_rate);
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+}
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+
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+static int sun4i_rate_reset_notifier_cb(struct notifier_block *nb,
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+ unsigned long event, void *data)
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+{
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+ struct sun4i_rate_reset_nb *rate_reset = to_sun4i_rate_reset_nb(nb);
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+
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+ if (event == POST_RATE_CHANGE)
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+ mod_delayed_work(system_wq, &rate_reset->reset_rate_work, msecs_to_jiffies(100));
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+
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+ return NOTIFY_DONE;
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+}
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+
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+static void sun4i_rate_reset_notifier_register(struct sun4i_rate_reset_nb *rate_reset_nb)
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+{
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+ if (rate_reset_nb->is_registered)
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+ return;
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+
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+ rate_reset_nb->clk_nb.notifier_call = sun4i_rate_reset_notifier_cb;
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+
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+ INIT_DELAYED_WORK(&rate_reset_nb->reset_rate_work,
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+ sun4i_rate_reset_notifier_delayed_update);
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+
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+ if (!clk_notifier_register(rate_reset_nb->target_clk,
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+ &rate_reset_nb->clk_nb))
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+ rate_reset_nb->is_registered = true;
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+}
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+
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+static struct sun4i_rate_reset_nb tcon_rate_reset_tcon0_nb;
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+
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+static void sun4i_tcon0_set_dclk_rate(struct sun4i_tcon *tcon, unsigned long rate)
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+{
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+ clk_set_rate(tcon->dclk, rate);
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+
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+ if (tcon->quirks->restores_rate) {
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+ tcon_rate_reset_tcon0_nb.target_clk = tcon->dclk;
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+ tcon_rate_reset_tcon0_nb.saved_rate = rate;
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+ sun4i_rate_reset_notifier_register(&tcon_rate_reset_tcon0_nb);
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+ }
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+}
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+
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static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
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const struct drm_encoder *encoder,
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const struct drm_display_mode *mode)
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@@ -360,8 +409,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
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*/
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tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
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tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
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- clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes)
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- / SUN6I_DSI_TCON_DIV);
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+ sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000 * (bpp / lanes)
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+ / SUN6I_DSI_TCON_DIV);
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/* Set the resolution */
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
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@@ -434,7 +483,7 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
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tcon->dclk_min_div = 7;
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tcon->dclk_max_div = 7;
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- clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
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+ sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000);
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/* Set the resolution */
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
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@@ -518,7 +567,7 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
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tcon->dclk_min_div = tcon->quirks->dclk_min_div;
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tcon->dclk_max_div = 127;
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- clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
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+ sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000);
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/* Set the resolution */
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
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@@ -1505,6 +1554,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
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.supports_lvds = true,
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};
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+static const struct sun4i_tcon_quirks sun50i_a64_lcd_quirks = {
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+ .supports_lvds = true,
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+ .has_channel_0 = true,
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+ .restores_rate = true,
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+ .dclk_min_div = 1,
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+ .setup_lvds_phy = sun6i_tcon_setup_lvds_phy,
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+};
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+
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static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
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.supports_lvds = true,
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.has_channel_0 = true,
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@@ -1563,6 +1620,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
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{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
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{ .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
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{ .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
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+ { .compatible = "allwinner,sun50i-a64-tcon-lcd", .data = &sun50i_a64_lcd_quirks },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
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diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
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index fa23aa23fe4a..bd4abc90062b 100644
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--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
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+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
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@@ -243,6 +243,7 @@ struct sun4i_tcon_quirks {
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bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
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bool supports_lvds; /* Does the TCON support an LVDS output? */
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bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
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+ bool restores_rate; /* restores the initial rate when rate changes */
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u8 dclk_min_div; /* minimum divider for TCON0 DCLK */
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/* callback to handle tcon muxing options */
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@@ -300,4 +301,15 @@ void sun4i_tcon_set_status(struct sun4i_tcon *crtc,
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extern const struct of_device_id sun4i_tcon_of_table[];
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+struct sun4i_rate_reset_nb {
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+ struct notifier_block clk_nb;
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+ struct delayed_work reset_rate_work;
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+
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+ struct clk *target_clk;
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+ unsigned long saved_rate;
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+ bool is_registered;
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+};
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+
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+#define to_sun4i_rate_reset_nb(_nb) container_of(_nb, struct sun4i_rate_reset_nb, clk_nb)
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+
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#endif /* __SUN4I_TCON_H__ */
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--
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2.35.3
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