/dts-v1/;
/plugin/;
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/ata/ahci.h>
#include <dt-bindings/thermal/thermal.h>

/ {

    fragment@0 {
        target-path = "/";
        __overlay__ {
            mpp_srv: mpp-srv {
                compatible = "rockchip,mpp-service";
                rockchip,taskqueue-count = <12>;
            };
        };
    };

    fragment@1 {
        target-path = "/";
        __overlay__ {
            rkvenc_ccu: rkvenc-ccu {
                compatible = "rockchip,rkv-encoder-v2-ccu";
            };
        };
    };

    fragment@2 {
        target-path = "/";
        __overlay__ {
            rkvenc0: rkvenc-core@fdbd0000 {
                compatible = "rockchip,rkv-encoder-v2-core";
                reg = <0x0 0xfdbd0000 0x0 0x6000>;
                interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupt-names = "irq_rkvenc0";
                clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
                clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
                rockchip,normal-rates = <600000000>, <0>, <800000000>;
                assigned-clocks = <&cru ACLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
                assigned-clock-rates = <600000000>, <800000000>;
                resets = <&cru SRST_A_RKVENC0>, <&cru SRST_H_RKVENC0>, <&cru SRST_RKVENC0_CORE>;
                reset-names = "video_a", "video_h", "video_core";
                rockchip,skip-pmu-idle-request;
                iommus = <&rkvenc0_mmu>;
                rockchip,srv = <&mpp_srv>;
                rockchip,ccu = <&rkvenc_ccu>;
                rockchip,taskqueue-node = <7>;
                rockchip,task-capacity = <8>;
                power-domains = <&power RK3588_PD_VENC0>;
            };
        };
    };

    fragment@3 {
        target-path = "/";
        __overlay__ {
            rkvenc0_mmu: iommu@fdbdf000 {
                compatible = "rockchip,rk3568-iommu";
                reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>;
                interrupts = <0 99 4 0>, <0 100 4 0>;
                interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1";
                clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>;
                clock-names = "aclk", "iface";
                rockchip,disable-mmu-reset;
                rockchip,enable-cmd-retry;
                rockchip,shootdown-entire;
                #iommu-cells = <0>;
                power-domains = <&power RK3588_PD_VENC0>;
            };
        };
    };

    fragment@4 {
        target-path = "/";
        __overlay__ {
            rkvenc1: rkvenc-core@fdbe0000 {
                compatible = "rockchip,rkv-encoder-v2-core";
                reg = <0x0 0xfdbe0000 0x0 0x6000>;
                interrupts = <0 104 4 0>;
                interrupt-names = "irq_rkvenc1";
                clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
                clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
                rockchip,normal-rates = <600000000>, <0>, <800000000>;
                assigned-clocks = <&cru ACLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
                assigned-clock-rates = <600000000>, <800000000>;
                resets = <&cru SRST_A_RKVENC1>, <&cru SRST_H_RKVENC1>, <&cru SRST_RKVENC1_CORE>;
                reset-names = "video_a", "video_h", "video_core";
                rockchip,skip-pmu-idle-request;
                iommus = <&rkvenc1_mmu>;
                rockchip,srv = <&mpp_srv>;
                rockchip,ccu = <&rkvenc_ccu>;
                rockchip,taskqueue-node = <7>;
                rockchip,task-capacity = <8>;
                power-domains = <&power RK3588_PD_VENC1>;
            };
        };
    };

    fragment@5 {
        target-path = "/";
        __overlay__ {
            rkvenc1_mmu: iommu@fdbef000 {
                compatible = "rockchip,rk3568-iommu";
                reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>;
                interrupts = <0 102 4 0>, <0 103 4 0>;
                interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1";
                clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>;
                clock-names = "aclk", "iface";
                rockchip,disable-mmu-reset;
                rockchip,enable-cmd-retry;
                rockchip,shootdown-entire;
                #iommu-cells = <0>;
                power-domains = <&power RK3588_PD_VENC1>;
            };
        };
    };
};