From 4549dc5d132a65e48e93a5ed8f2d02cf5e0ea447 Mon Sep 17 00:00:00 2001 From: AGM1968 Date: Tue, 23 May 2023 16:43:00 +0000 Subject: arm64: dts: add sun50i-h618-cpu-dvfs.dtsi Add sun50i-h616-cpu-opp-test.dtsi for tests only. Its unused production for kernel v6.10. Signed-off-by: AGM1968 Signed-off-by: The-going <48602507+The-going@users.noreply.github.com> --- .../allwinner/sun50i-h616-cpu-opp-test.dtsi | 75 +++++++++++++++++++ .../allwinner/sun50i-h616-orangepi-zero.dtsi | 1 + .../dts/allwinner/sun50i-h618-cpu-dvfs.dtsi | 64 ++++++++++++++++ .../allwinner/sun50i-h618-orangepi-zero3.dts | 57 +------------- 4 files changed, 141 insertions(+), 56 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp-test.dtsi create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp-test.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp-test.dtsi new file mode 100644 index 000000000000..36f2950367c6 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp-test.dtsi @@ -0,0 +1,75 @@ +//SPDX-License-Identifier: (GPL-2.0+ OR MIT) +//Testing Version 1 from: AGM1968 +//Noted: PLL_CPUX = 24 MHz*N/P (WIP) + +/ { + cpu_opp_table: opp-table-cpu { + compatible = "allwinner,sun50i-h616-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + opp-shared; + + opp-480000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <480000000>; + opp-microvolt-speed0 = <820000 820000 1100000>; + opp-microvolt-speed1 = <880000 880000 1100000>; + opp-microvolt-speed2 = <880000 880000 1100000>; + }; + + opp-600000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <600000000>; + opp-microvolt-speed0 = <820000 820000 1100000>; + opp-microvolt-speed1 = <880000 880000 1100000>; + opp-microvolt-speed2 = <880000 880000 1100000>; + }; + + opp-792000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <792000000>; + opp-microvolt-speed0 = <860000 860000 1100000>; + opp-microvolt-speed1 = <940000 940000 1100000>; + opp-microvolt-speed2 = <940000 940000 1100000>; + }; + + opp-1008000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt-speed0 = <900000 900000 1100000>; + opp-microvolt-speed1 = <1020000 1020000 1100000>; + opp-microvolt-speed2 = <1020000 1020000 1100000>; + }; + + opp-1200000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt-speed0 = <960000 960000 1100000>; + opp-microvolt-speed1 = <1100000 1100000 1100000>; + opp-microvolt-speed2 = <1100000 1100000 1100000>; + }; + + opp-1512000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt-speed0 = <1100000 1100000 1100000>; + opp-microvolt-speed1 = <1100000 1100000 1100000>; + opp-microvolt-speed2 = <1100000 1100000 1100000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi index a795087c681f..54dfaf24e75d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi @@ -7,6 +7,7 @@ */ #include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" #include #include diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi new file mode 100644 index 000000000000..0509e3fb22e2 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi @@ -0,0 +1,64 @@ + + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL and DRAM */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-ramp-delay = <200>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts index e1cd7572a14c..222ae63013eb 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts @@ -7,6 +7,7 @@ #include "sun50i-h616-orangepi-zero.dtsi" #include "sun50i-h616-cpu-opp.dtsi" +#include "sun50i-h618-cpu-dvfs.dtsi" / { model = "OrangePi Zero3"; @@ -36,62 +37,6 @@ &mmc0 { vmmc-supply = <®_dldo1>; }; -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&pio>; - interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - /* Supplies VCC-PLL, so needs to be always on. */ - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Supplies VCC-IO, so needs to be always on. */ - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - &pio { vcc-pc-supply = <®_dldo1>; vcc-pf-supply = <®_dldo1>; -- 2.35.3