diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 4bf84622db47..b1a8b52d33c9 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -124,6 +124,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-cb2-manta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pcie.dtso +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-dsi1.dtso +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-hdmi.dtso +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-sfc-nor.dtso +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-w1-gpio4-pb2.dtso dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb @@ -248,3 +253,23 @@ rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-haikou-video-demo.dtb rk3588-tiger-haikou-haikou-video-demo-dtbs := rk3588-tiger-haikou.dtb \ rk3588-tiger-haikou-video-demo.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2-pcie.dtb +rk3566-bigtreetech-pi2-pcie-dtbs := rk3566-bigtreetech-pi2.dtb \ + rk3566-pcie.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2-dsi1.dtb +rk3566-bigtreetech-pi2-dsi1-dtbs := rk3566-bigtreetech-pi2.dtb \ + rk3566-dsi1.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2-hdmi.dtb +rk3566-bigtreetech-pi2-hdmi-dtbs := rk3566-bigtreetech-pi2.dtb \ + rk3566-hdmi.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2-sfc-nor.dtb +rk3566-bigtreetech-pi2-sfc-nor-dtbs := rk3566-bigtreetech-pi2.dtb \ + rk3566-sfc-nor.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2-w1-gpio4-pb2.dtb +rk3566-bigtreetech-pi2-w1-gpio4-pb2-dtbs := rk3566-bigtreetech-pi2.dtb \ + rk3566-w1-gpio4-pb2.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi index e7ba477e75f9..5db1b3ca294d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi @@ -120,7 +120,7 @@ vcc3v3_pcie: regulator-vcc3v3-pcie { compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie"; enable-active-high; - gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie_drv>; regulator-always-on; @@ -251,6 +251,54 @@ &cpu3 { cpu-supply = <&vdd_cpu>; }; +&dsi1 { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dsi1_panel: panel@0 { + compatible = "btt-pitft"; + reg = <0x0>; + status = "disabled"; + vddc-supply = <&bl_dsi>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + + dsi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi1>; + }; + }; + + dsi1_out: port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; @@ -265,6 +313,8 @@ &gmac1m0_rx_bus2 &gmac1m0_rgmii_clk &gmac1m0_clkinout &gmac1m0_rgmii_bus>; + tx_delay = <0x19>; + rx_delay = <0x05>; status = "okay"; }; @@ -280,13 +330,13 @@ rgmii_phy0: phy@0 { &gpu { mali-supply = <&vdd_gpu>; - status = "okay"; + status = "disabled"; }; &hdmi { avdd-0v9-supply = <&vdda0v9_image>; avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; + status = "disabled"; }; &hdmi_in { @@ -302,7 +352,7 @@ hdmi_out_con: endpoint { }; &hdmi_sound { - status = "okay"; + status = "disabled"; }; &i2c0 { @@ -336,6 +386,7 @@ rk809: pmic@20 { #clock-cells = <1>; clock-names = "mclk"; clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset"; pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; @@ -558,11 +609,39 @@ codec { }; &i2c2 { + status = "disabled"; + clock-frequency = <100000>; pinctrl-0 = <&i2c2m1_xfer>; + avdd-1v8-supply = <&vcca1v8_image>; + avdd-0v9-supply = <&vdda0v9_image>; + power-domains = <&power RK3568_PD_VI>; + #address-cells = <1>; + #size-cells = <0>; + #size-cells = <0>; + + bl_dsi: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + status = "disabled"; + }; + + tp_dsi: touchscreen@38 { + compatible = "edt,edt-ft5306"; + reg = <0x38>; + status = "disabled"; + + vcc-supply = <&vcc3v3_sys>; + iovcc-supply = <&vcc_3v3>; + + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; }; &i2c3 { - status = "okay"; + status = "disabled"; tft_tp: touchscreen@48 { compatible = "ti,tsc2007"; @@ -575,10 +654,6 @@ tft_tp: touchscreen@48 { }; }; -&i2s0_8ch { - status = "okay"; -}; - &i2s1_8ch { pinctrl-names = "default"; pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; @@ -614,7 +689,7 @@ &pcie2x1 { pinctrl-0 = <&pcie_reset_h>; reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; + status = "disabled"; }; &pinctrl { @@ -889,11 +964,7 @@ &usb_host1_xhci { &vop { assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; + vop-supply = <&vdd_logic>; }; &vp0 { @@ -902,3 +973,10 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { remote-endpoint = <&hdmi_in_vp0>; }; }; + +&vp1 { + vp1_out_dsi1: endpoint@ROCKCHIP_VOP2_EP_MIPI1 { + reg = ; + remote-endpoint = <&dsi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts index 7cd444caa18b..ff7df921f0f0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts @@ -8,3 +8,28 @@ / { model = "BigTreeTech Pi 2"; compatible = "bigtreetech,pi2", "rockchip,rk3566"; }; + +&scmi_clk { + rockchip,clk-init = <1104000000>; +}; + +/* disable all - default state */ +&display_subsystem { + status = "disabled"; +}; +&dsi_dphy1 { + status = "disabled"; +}; +&vop { + vop-supply = <&vdd_logic>; + status = "disabled"; +}; +&vop_mmu { + status = "disabled"; +}; +&display_subsystem { + status = "disabled"; +}; +&i2s0_8ch { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-dsi1.dtso b/arch/arm64/boot/dts/rockchip/rk3566-dsi1.dtso new file mode 100644 index 000000000000..7c4790908638 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-dsi1.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +/plugin/; + +&vop { + status = "okay"; +}; +&vop_mmu { + status = "okay"; +}; +&display_subsystem { + status = "okay"; +}; +&dsi1 { + status = "okay"; +}; +&dsi1_panel { + status = "okay"; +}; +&dsi1_in_vp1 { + status = "okay"; +}; +&dsi_dphy1 { + status = "okay"; +}; +&tp_dsi { + status = "okay"; +}; +&bl_dsi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-hdmi.dtso b/arch/arm64/boot/dts/rockchip/rk3566-hdmi.dtso new file mode 100644 index 000000000000..08fb4f254955 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-hdmi.dtso @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +/plugin/; + +&vop { + status = "okay"; +}; +&vop_mmu { + status = "okay"; +}; +&display_subsystem { + status = "okay"; +}; +&hdmi_sound { + status = "okay"; +}; +&i2s0_8ch { + status = "okay"; +}; +&hdmi { + status = "okay"; +}; +&hdmi_in_vp0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pcie.dtso b/arch/arm64/boot/dts/rockchip/rk3566-pcie.dtso new file mode 100644 index 000000000000..9cb6e8f03685 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-pcie.dtso @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +/plugin/; + +&pcie2x1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-sfc-nor.dtso b/arch/arm64/boot/dts/rockchip/rk3566-sfc-nor.dtso new file mode 100644 index 000000000000..011850ba18db --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-sfc-nor.dtso @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +/plugin/; + +&sfc { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-w1-gpio4-pb2.dtso b/arch/arm64/boot/dts/rockchip/rk3566-w1-gpio4-pb2.dtso new file mode 100644 index 000000000000..410763276a6b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-w1-gpio4-pb2.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +/plugin/; + +#include +#include + +/ { + onewire: onewire { + compatible = "w1-gpio"; + gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_w1>; + status = "okay"; + }; +}; + +&pinctrl { + gpio-w1 { + gpio_w1:gpio-w1 { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index fd2214b6fad4..9e99309eb9bd 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -616,6 +629,26 @@ vepu_mmu: iommu@fdee0800 { #iommu-cells = <0>; }; + vdec: video-codec@fdf80200 { + compatible = "rockchip,rk3588-vdec"; + reg = <0x0 0xfdf80100 0x0 0x100>, <0x0 0xfdf80200 0x0 0x500>, <0x0 0xfdf80700 0x0 0x100>; + reg-names = "link", "function", "cache"; + interrupts = ; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_CA>, + <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates = <297000000>, <297000000>, + <297000000>, <297000000>; + resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CA>, + <&cru SRST_RKVDEC_CORE>, <&cru SRST_RKVDEC_HEVC_CA>; + reset-names = "rst_axi", "rst_ahb", "rst_cabac", + "rst_core", "rst_hevc_cabac"; + power-domains = <&power RK3568_PD_RKVDEC>; + sram = <&vdec_sram>; + }; + sdmmc2: mmc@fe000000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe000000 0x0 0x4000>; @@ -1057,6 +1090,123 @@ rng: rng@fe388000 { status = "disabled"; }; + otp: otp@fe38c000 { + compatible = "rockchip,rk3568-otp"; + reg = <0x00 0xfe38c000 0x00 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS_USR>, + <&cru CLK_OTPC_NS_SBPI>, + <&cru PCLK_OTPC_NS>, + <&cru PCLK_OTPPHY>; + clock-names = "usr", "sbpi", "apb", "phy"; + resets = <&cru SRST_OTPPHY>; + reset-names = "otp_phy"; + + cpu_code: cpu-code@2 { + reg = <0x02 0x02>; + }; + + specification_serial_number: specification-serial-number@7 { + reg = <0x07 0x01>; + bits = <0x00 0x05>; + }; + + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x01>; + bits = <0x03 0x03>; + }; + + mbist_vmin: mbist-vmin@9 { + reg = <0x09 0x01>; + bits = <0x00 0x04>; + }; + + otp_id: id@a { + reg = <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x01>; + }; + + log_leakage: log-leakage@1b { + reg = <0x1b 0x01>; + }; + + npu_leakage: npu-leakage@1c { + reg = <0x1c 0x01>; + }; + + gpu_leakage: gpu-leakage@1d { + reg = <0x1d 0x01>; + }; + + core_pvtm: core-pvtm@2a { + reg = <0x2a 0x02>; + }; + + cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e { + reg = <0x2e 0x01>; + }; + + cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f { + reg = <0x2f 0x01>; + bits = <0x00 0x04>; + }; + + gpu_tsadc_trim_l: npu-tsadc-trim-l@30 { + reg = <0x30 0x01>; + }; + + gpu_tsadc_trim_h: npu-tsadc-trim-h@31 { + reg = <0x31 0x01>; + bits = <0x00 0x04>; + }; + + tsadc_trim_base_frac: tsadc-trim-base-frac@31 { + reg = <0x31 0x01>; + bits = <0x04 0x04>; + }; + + tsadc_trim_base: tsadc-trim-base@32 { + reg = <0x32 0x01>; + }; + + cpu_opp_info: cpu-opp-info@36 { + reg = <0x36 0x06>; + }; + + gpu_opp_info: gpu-opp-info@3c { + reg = <0x3c 0x06>; + }; + + npu_opp_info: npu-opp-info@42 { + reg = <0x42 0x06>; + }; + + dmc_opp_info: dmc-opp-info@48 { + reg = <0x48 0x06>; + }; + + remark_spec_serial_number: remark-spec-serial-number@56 { + reg = <0x56 1>; + bits = <0 5>; + }; + }; + + crypto: crypto@fe380000 { + compatible = "rockchip,rk3568-crypto"; + reg = <0x0 0xfe380000 0x0 0x2000>; + interrupts = ; + clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, + <&cru CLK_CRYPTO_NS_CORE>; + clock-names = "aclk", "hclk", "core"; + resets = <&cru SRST_CRYPTO_NS_CORE>; + reset-names = "core"; + status = "okay"; + }; + i2s0_8ch: i2s@fe400000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x0 0xfe400000 0x0 0x1000>;