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Migrate H616 to kernel 6.16

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This commit is contained in:
andreili 2025-08-27 10:16:25 +02:00
parent 14200c4e86
commit 38b835c5ed
753 changed files with 2067 additions and 119660 deletions
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218
cfg/kernel_v6.16-rc2
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@ -63,6 +63,7 @@ CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_IRQ_MSI_IOMMU=y
@ -301,7 +302,7 @@ CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_AIROHA is not set
# CONFIG_ARCH_SUNXI is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM is not set
@ -606,6 +607,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPUFREQ_DT=y
# CONFIG_CPUFREQ_VIRT is not set
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management
@ -1252,6 +1254,8 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y
# Bus devices
#
# CONFIG_MOXTET is not set
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
# CONFIG_VEXPRESS_CONFIG is not set
# CONFIG_MHI_BUS is not set
# CONFIG_MHI_BUS_EP is not set
@ -1488,6 +1492,7 @@ CONFIG_RPMB=y
# CONFIG_DW_XDATA_PCIE is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_OPEN_DICE is not set
# CONFIG_NTSYNC is not set
# CONFIG_VCPU_STALL_DETECTOR is not set
@ -1651,6 +1656,9 @@ CONFIG_ETHERNET=y
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
CONFIG_NET_VENDOR_ALLWINNER=y
# CONFIG_SUN4I_EMAC is not set
CONFIG_SUNXI_GMAC=y
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
@ -1716,9 +1724,11 @@ CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
# CONFIG_STMMAC_SELFTESTS is not set
CONFIG_STMMAC_PLATFORM=y
# CONFIG_DWMAC_DWC_QOS_ETH is not set
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_SUNXI=y
CONFIG_DWMAC_SUN8I=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
@ -1745,6 +1755,8 @@ CONFIG_FIXED_PHY=y
#
# CONFIG_AS21XXX_PHY is not set
# CONFIG_AIR_EN8811H_PHY is not set
CONFIG_AC200_PHY=y
CONFIG_AC200_PHY_SUNXI=y
# CONFIG_AMD_PHY is not set
# CONFIG_ADIN_PHY is not set
# CONFIG_ADIN1100_PHY is not set
@ -1853,6 +1865,7 @@ CONFIG_CAN_GS_USB=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
# CONFIG_MDIO_SUN4I is not set
# CONFIG_MDIO_BITBANG is not set
# CONFIG_MDIO_BCM_UNIMAC is not set
# CONFIG_MDIO_HISI_FEMAC is not set
@ -1866,6 +1879,7 @@ CONFIG_OF_MDIO=y
#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=y
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
@ -1971,6 +1985,7 @@ CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
CONFIG_KEYBOARD_SUN4I_LRADC=y
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
@ -2004,6 +2019,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP5 is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
@ -2053,6 +2069,7 @@ CONFIG_TOUCHSCREEN_EDT_FT5X06=m
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SUN4I is not set
# CONFIG_TOUCHSCREEN_SUR40 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
@ -2081,6 +2098,7 @@ CONFIG_INPUT_MISC=y
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
# CONFIG_INPUT_AXP20X_PEK is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_PWM_BEEPER is not set
@ -2112,6 +2130,7 @@ CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_SUN4I_PS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
# CONFIG_GAMEPORT is not set
@ -2196,6 +2215,9 @@ CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
# CONFIG_VIRTIO_CONSOLE is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_SUNXI_SYS_INFO=y
CONFIG_DUMP_REG=y
CONFIG_DUMP_REG_MISC=y
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_HW_RANDOM_BA431 is not set
@ -2270,6 +2292,7 @@ CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_GPIO=y
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_HISI is not set
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
@ -2330,6 +2353,8 @@ CONFIG_SPI_ROCKCHIP_SFC=y
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SN_F_OSPI is not set
# CONFIG_SPI_SUN4I is not set
CONFIG_SPI_SUN6I=y
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_THUNDERX is not set
# CONFIG_SPI_XCOMM is not set
@ -2386,6 +2411,7 @@ CONFIG_PINMUX=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AXP209 is not set
# CONFIG_PINCTRL_AW9523 is not set
# CONFIG_PINCTRL_CY8C95X0 is not set
# CONFIG_PINCTRL_MCP23S08 is not set
@ -2404,6 +2430,33 @@ CONFIG_PINCTRL_ROCKCHIP=y
#
# end of Renesas pinctrl drivers
CONFIG_PINCTRL_SUNXI=y
# CONFIG_PINCTRL_SUN4I_A10 is not set
# CONFIG_PINCTRL_SUN5I is not set
# CONFIG_PINCTRL_SUN6I_A31 is not set
# CONFIG_PINCTRL_SUN6I_A31_R is not set
# CONFIG_PINCTRL_SUN8I_A23 is not set
# CONFIG_PINCTRL_SUN8I_A33 is not set
# CONFIG_PINCTRL_SUN8I_A83T is not set
# CONFIG_PINCTRL_SUN8I_A83T_R is not set
# CONFIG_PINCTRL_SUN8I_A23_R is not set
# CONFIG_PINCTRL_SUN8I_H3 is not set
# CONFIG_PINCTRL_SUN8I_H3_R is not set
# CONFIG_PINCTRL_SUN8I_V3S is not set
# CONFIG_PINCTRL_SUN9I_A80 is not set
# CONFIG_PINCTRL_SUN9I_A80_R is not set
# CONFIG_PINCTRL_SUN20I_D1 is not set
# CONFIG_PINCTRL_SUN50I_A64 is not set
# CONFIG_PINCTRL_SUN50I_A64_R is not set
# CONFIG_PINCTRL_SUN50I_A100 is not set
# CONFIG_PINCTRL_SUN50I_A100_R is not set
# CONFIG_PINCTRL_SUN50I_H5 is not set
# CONFIG_PINCTRL_SUN50I_H6 is not set
# CONFIG_PINCTRL_SUN50I_H6_R is not set
CONFIG_PINCTRL_SUN50I_H616=y
CONFIG_PINCTRL_SUN50I_H616_R=y
# CONFIG_PINCTRL_SUN55I_A523 is not set
# CONFIG_PINCTRL_SUN55I_A523_R is not set
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
@ -2565,10 +2618,14 @@ CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_CHARGER_AXP20X is not set
# CONFIG_BATTERY_AXP20X is not set
CONFIG_AXP20X_POWER=y
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1720X is not set
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
@ -2793,6 +2850,7 @@ CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_THERMAL_MMIO is not set
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
# CONFIG_GENERIC_ADC_THERMAL is not set
CONFIG_WATCHDOG=y
@ -2820,6 +2878,7 @@ CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_ARM_SBSA_WATCHDOG is not set
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=y
CONFIG_SUNXI_WATCHDOG=y
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
@ -2848,6 +2907,7 @@ CONFIG_BCMA_POSSIBLE=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_ADP5585 is not set
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_SUN4I_GPADC is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_SMPRO is not set
# CONFIG_MFD_AS3722 is not set
@ -2857,7 +2917,12 @@ CONFIG_MFD_CORE=y
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_AC100 is not set
# CONFIG_MFD_AC200 is not set
CONFIG_MFD_AC200_SUNXI=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
# CONFIG_MFD_CS42L43_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_MFD_MAX5970 is not set
@ -2922,6 +2987,7 @@ CONFIG_MFD_RK8XX_I2C=y
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_SUN6I_PRCM is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
@ -2982,16 +3048,18 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_NETLINK_EVENTS is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER_OF is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_ADP5055 is not set
# CONFIG_REGULATOR_ARM_SCMI is not set
# CONFIG_REGULATOR_AW37503 is not set
CONFIG_REGULATOR_AXP20X=y
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
# CONFIG_REGULATOR_FAN53555 is not set
CONFIG_REGULATOR_FAN53555=y
# CONFIG_REGULATOR_FAN53880 is not set
# CONFIG_REGULATOR_FAN53200 is not set
CONFIG_REGULATOR_GPIO=y
@ -3029,7 +3097,7 @@ CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_PV88090 is not set
# CONFIG_REGULATOR_PWM is not set
# CONFIG_REGULATOR_RAA215300 is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT4803 is not set
@ -3044,6 +3112,7 @@ CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_RTQ2208 is not set
# CONFIG_REGULATOR_SLG51000 is not set
CONFIG_REGULATOR_SUN20I=y
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
@ -3056,6 +3125,7 @@ CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_REGULATOR_VCTRL is not set
# CONFIG_REGULATOR_TP65185X is not set
# CONFIG_RC_CORE is not set
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y
@ -3232,6 +3302,12 @@ CONFIG_VIDEO_ROCKCHIP_RGA=y
#
# Sunxi media platform drivers
#
# CONFIG_VIDEO_SUN4I_CSI is not set
# CONFIG_VIDEO_SUN6I_CSI is not set
# CONFIG_VIDEO_SUN6I_MIPI_CSI2 is not set
# CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 is not set
# CONFIG_VIDEO_SUN8I_DEINTERLACE is not set
# CONFIG_VIDEO_SUN8I_ROTATE is not set
# CONFIG_VIDEO_SYNOPSYS_HDMIRX is not set
#
@ -3244,6 +3320,7 @@ CONFIG_VIDEO_ROCKCHIP_RGA=y
CONFIG_VIDEO_HANTRO=y
# CONFIG_VIDEO_HANTRO_HEVC_RFC is not set
CONFIG_VIDEO_HANTRO_ROCKCHIP=y
CONFIG_VIDEO_HANTRO_SUNXI=y
#
# VIA media platform drivers
@ -3271,7 +3348,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y
# CONFIG_VIDEO_GC0308 is not set
# CONFIG_VIDEO_GC05A2 is not set
# CONFIG_VIDEO_GC08A3 is not set
# CONFIG_VIDEO_GC2145 is not set
# CONFIG_VIDEO_GC2145_MIPI is not set
# CONFIG_VIDEO_HI556 is not set
# CONFIG_VIDEO_HI846 is not set
# CONFIG_VIDEO_HI847 is not set
@ -3343,6 +3420,8 @@ CONFIG_VIDEO_CAMERA_SENSOR=y
# CONFIG_VIDEO_VGXY61 is not set
# CONFIG_VIDEO_CCS is not set
# CONFIG_VIDEO_ET8EK8 is not set
# CONFIG_VIDEO_HM5065 is not set
# CONFIG_VIDEO_GC2145 is not set
#
# Camera ISPs
@ -3572,6 +3651,11 @@ CONFIG_ROCKCHIP_DW_MIPI_DSI=y
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
CONFIG_DRM_SUN4I=y
CONFIG_DRM_SUN6I_DSI=y
CONFIG_DRM_SUN8I_DW_HDMI=y
CONFIG_DRM_SUN8I_MIXER=y
CONFIG_DRM_SUN8I_TCON_TOP=y
# CONFIG_DRM_QXL is not set
CONFIG_DRM_PANEL=y
@ -3783,6 +3867,7 @@ CONFIG_FB=y
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_SUN5I_EINK is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
@ -4200,7 +4285,8 @@ CONFIG_USB_SERIAL_FTDI_SIO=y
#
# USB Physical Layer drivers
#
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=y
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_ULPI is not set
@ -4208,7 +4294,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y
# CONFIG_USB_GADGET is not set
# CONFIG_TYPEC is not set
# CONFIG_USB_ROLE_SWITCH is not set
CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
CONFIG_PWRSEQ_SIMPLE=y
@ -4247,6 +4333,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_USDHI6ROL0 is not set
CONFIG_MMC_SUNXI=y
CONFIG_MMC_CQHCI=y
# CONFIG_MMC_HSQ is not set
# CONFIG_MMC_TOSHIBA_PCI is not set
@ -4305,6 +4392,7 @@ CONFIG_LEDS_USER=y
# CONFIG_LEDS_SPI_BYTE is not set
# CONFIG_LEDS_LM3697 is not set
# CONFIG_LEDS_ST1202 is not set
CONFIG_LEDS_AXP20X=y
#
# Flash and Torch LED drivers
@ -4313,6 +4401,7 @@ CONFIG_LEDS_USER=y
#
# RGB LED drivers
#
# CONFIG_LEDS_WS2812 is not set
#
# LED Triggers
@ -4451,6 +4540,7 @@ CONFIG_RTC_I2C_AND_SPI=y
#
# CONFIG_RTC_DRV_PL030 is not set
# CONFIG_RTC_DRV_PL031 is not set
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set
@ -4466,10 +4556,12 @@ CONFIG_DMADEVICES=y
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
# CONFIG_AMBA_PL08X is not set
# CONFIG_ARM_DMA350 is not set
CONFIG_DMA_SUN6I=y
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
@ -4523,7 +4615,62 @@ CONFIG_SYNC_FILE=y
# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
# CONFIG_STAGING is not set
CONFIG_STAGING=y
# CONFIG_RTL8723BS is not set
#
# IIO staging drivers
#
#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# end of Accelerometers
#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# end of Analog to digital converters
#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters
#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis
#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters
# end of IIO staging drivers
# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_VIDEO_MAX96712 is not set
# CONFIG_VIDEO_ROCKCHIP_VDEC is not set
CONFIG_VIDEO_ROCKCHIP_VDEC2=y
#
# StarFive media platform drivers
#
CONFIG_VIDEO_SUNXI=y
CONFIG_VIDEO_SUNXI_CEDRUS=y
# CONFIG_VIDEO_SUN6I_ISP is not set
# CONFIG_STAGING_MEDIA_DEPRECATED is not set
# CONFIG_FB_TFT is not set
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_VME_BUS is not set
# CONFIG_GPIB is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
@ -4573,6 +4720,19 @@ CONFIG_CLK_RK3562=y
CONFIG_CLK_RK3568=y
# CONFIG_CLK_RK3576 is not set
# CONFIG_CLK_RK3588 is not set
CONFIG_SUNXI_CCU=y
# CONFIG_SUN50I_A64_CCU is not set
# CONFIG_SUN50I_A100_CCU is not set
# CONFIG_SUN50I_A100_R_CCU is not set
# CONFIG_SUN50I_H6_CCU is not set
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
# CONFIG_SUN55I_A523_CCU is not set
# CONFIG_SUN55I_A523_R_CCU is not set
CONFIG_SUN6I_RTC_CCU=y
# CONFIG_SUN8I_H3_CCU is not set
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
# CONFIG_XILINX_VCU is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
# CONFIG_HWSPINLOCK is not set
@ -4584,12 +4744,14 @@ CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_SUN4I_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
# CONFIG_ARM_TIMER_SP804 is not set
# end of Clock Source drivers
@ -4602,6 +4764,7 @@ CONFIG_MAILBOX=y
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_ALTERA_MBOX is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y
@ -4626,6 +4789,7 @@ CONFIG_IOMMU_DMA=y
# CONFIG_ARM_SMMU_V3 is not set
# CONFIG_IOMMUFD is not set
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_SUN50I_IOMMU=y
#
# Remoteproc drivers
@ -4686,6 +4850,8 @@ CONFIG_ROCKCHIP_IOMMU=y
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_SUNXI_MBUS=y
CONFIG_SUNXI_SRAM=y
# CONFIG_SOC_TI is not set
#
@ -4723,6 +4889,8 @@ CONFIG_ARM_SCPI_POWER_DOMAIN=y
# end of Qualcomm PM Domains
CONFIG_ROCKCHIP_PM_DOMAINS=y
# CONFIG_SUN20I_PPU is not set
CONFIG_SUN50I_H6_PRCM_PPU=y
# end of PM Domains
CONFIG_PM_DEVFREQ=y
@ -4740,6 +4908,7 @@ CONFIG_DEVFREQ_GOV_PASSIVE=y
# DEVFREQ Drivers
#
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
# CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_EXTCON=y
@ -4826,6 +4995,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
#
# Analog to digital converters
#
CONFIG_IIO_ADC_HELPER=y
# CONFIG_AD4000 is not set
# CONFIG_AD4030 is not set
# CONFIG_AD4130 is not set
@ -4859,6 +5029,8 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
# CONFIG_AD7949 is not set
# CONFIG_AD799X is not set
# CONFIG_AD9467 is not set
CONFIG_AXP20X_ADC=y
# CONFIG_AXP288_ADC is not set
# CONFIG_CC10001_ADC is not set
# CONFIG_ENVELOPE_DETECTOR is not set
# CONFIG_GEHC_PMC_ADC is not set
@ -4891,6 +5063,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_ROCKCHIP_SARADC=y
# CONFIG_RICHTEK_RTQ6056 is not set
# CONFIG_SD_ADC_MODULATOR is not set
CONFIG_SUN20I_GPADC=y
# CONFIG_TI_ADC081C is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
@ -5364,6 +5537,8 @@ CONFIG_PWM=y
# CONFIG_PWM_MC33XS2410 is not set
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
# CONFIG_PWM_SUN4I is not set
CONFIG_PWM_SUNXI_ENHANCE=y
# CONFIG_PWM_XILINX is not set
#
@ -5377,6 +5552,8 @@ CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_IRQ_MSI_LIB=y
# CONFIG_AL_FIC is not set
CONFIG_SUN6I_R_INTC=y
CONFIG_SUNXI_NMI_INTC=y
# CONFIG_XILINX_INTC is not set
CONFIG_PARTITION_PERCPU=y
# end of IRQ chip support
@ -5386,7 +5563,8 @@ CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_GPIO is not set
CONFIG_RESET_SCMI=y
# CONFIG_RESET_SIMPLE is not set
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set
@ -5397,6 +5575,10 @@ CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_CAN_TRANSCEIVER is not set
# CONFIG_PHY_NXP_PTN3222 is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=y
# CONFIG_PHY_SUN9I_USB is not set
# CONFIG_PHY_SUN50I_USB3 is not set
#
# PHY drivers for Broadcom platforms
@ -5477,6 +5659,7 @@ CONFIG_NVMEM_LAYOUTS=y
# CONFIG_NVMEM_RMEM is not set
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_SUNXI_SID=y
# CONFIG_NVMEM_U_BOOT_ENV is not set
#
@ -5531,7 +5714,7 @@ CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
# CONFIG_F2FS_FS_SECURITY is not set
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_CHECK_FS=y
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
@ -5792,6 +5975,7 @@ CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_KPP2=y
@ -5831,7 +6015,7 @@ CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SEED is not set
@ -5955,6 +6139,14 @@ CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
# end of Accelerated Cryptographic Algorithms for CPU (arm64)
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
# CONFIG_CRYPTO_DEV_SUN4I_SS is not set
CONFIG_CRYPTO_DEV_SUN8I_CE=y
# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set
CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
# CONFIG_CRYPTO_DEV_SUN8I_SS is not set
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
@ -6009,6 +6201,7 @@ CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=m
CONFIG_CRYPTO_LIB_GF128MUL=m
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
@ -6019,6 +6212,7 @@ CONFIG_CRYPTO_LIB_SM3=y
CONFIG_CRYPTO_SHA256_ARM64=y
# end of Crypto library routines
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_ARCH_HAS_CRC_T10DIF=y
CONFIG_CRC32=y

4
config/board/btt_pi2.json
View File

@ -64,9 +64,9 @@
"parent": "kernel",
"version": "v6.16-rc2",
"version_type": "tag",
"patch_dir": [ "kernel", "kernel/rockchip64-6.16" ],
"patch_dir": [ "kernel", "kernel/sunxi-6.16", "kernel/rockchip64-6.16" ],
"config_def": "printer_defconfig",
"target": [ "clean", "Image", "modules", "dtbs", "modules_install" ],
"target": [ "Image", "modules", "dtbs", "modules_install" ],
"artifacts":
[
{

78
patch/kernel/h616_old
View File

@ -1,78 +0,0 @@
+
+#H616, SoC-specific
+CONFIG_SUN50I_A64_CCU=n
+CONFIG_SUN50I_A100_CCU=n
+CONFIG_SUN50I_A100_R_CCU=n
+CONFIG_SUN50I_H6_CCU=n
+CONFIG_SUN8I_H3_CCU=n
+CONFIG_ARCH_SUNXI=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_SUNXI_CCU=y
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_AC200_PHY=y
+CONFIG_AC200_PHY_SUNXI=y
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_STAGING=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_VIDEO_SUNXI=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MFD_AC200_SUNXI=y
+CONFIG_SUN50I_H616_CCU=y
+CONFIG_SND_SUN4I_CODEC=y
+CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
+CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
+CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
+CONFIG_CRYPTO_DEV_SUN8I_CE=y
+CONFIG_SUN50I_DE2_BUS=y
+CONFIG_SUN8I_DE2_CCU=y
+CONFIG_DRM_SUN8I_MIXER=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DWMAC_SUNXI=y
+CONFIG_DWMAC_SUN8I=y
+CONFIG_MMC_SUNXI=y
+CONFIG_SUN20I_GPADC=y
+CONFIG_DRM_SUN8I_DW_HDMI=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_SUN50I_IOMMU=y
+##CONFIG_IR_SUNXI=y
+CONFIG_KEYBOARD_SUN4I_LRADC=y
+CONFIG_SUNXI_NMI_INTC=y
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
+CONFIG_PINCTRL_SUN50I_H616=y
+CONFIG_SUN50I_H6_PRCM_PPU=y
+CONFIG_PWM_SUNXI_ENHANCE=y
+CONFIG_SUN50I_H6_R_CCU=y
+CONFIG_PINCTRL_SUN50I_H616_R=y
+CONFIG_SUNXI_RSB=y
+CONFIG_SUN6I_RTC_CCU=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_SND_SUN4I_SPDIF=y
+CONFIG_SPI_SUN6I=y
+CONFIG_SUNXI_SYS_INFO=y
+CONFIG_SUNXI_SRAM=y
+CONFIG_SUN8I_THERMAL=y
+CONFIG_VIDEO_SUNXI_CEDRUS=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_DRM_SUN4I=y
+CONFIG_DRM_SUN8I_TCON_TOP=y
+CONFIG_SUNXI_ADDR_MGT=y
+CONFIG_SUNXI_GMAC=y
+##CONFIG_CAN_MCP251X=y
+##CONFIG_FB_TFT_ST7796S=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_REGULATOR_AXP20X=y
+#minimize
+CONFIG_PINCTRL_SUN8I_H3_R=n
+CONFIG_PINCTRL_SUN50I_A64=n
+CONFIG_PINCTRL_SUN50I_A64_R=n
+CONFIG_PINCTRL_SUN50I_A100=n
+CONFIG_PINCTRL_SUN50I_A100_R=n
+CONFIG_PINCTRL_SUN50I_H5=n
+CONFIG_PINCTRL_SUN50I_H6=n
+CONFIG_PINCTRL_SUN50I_H6_R=n
+#sound
+CONFIG_SND_SOC_SUNXI_AHUB=y
+CONFIG_SND_SOC_SUNXI_AHUB_DAM=y

87
patch/kernel/printer_defconfig_1_plat.patch
View File

@ -3,7 +3,7 @@ new file mode 100644
index 000000000000..51de9e95b7d2
--- a/arch/arm64/configs/printer_defconfig
+++ b/arch/arm64/configs/printer_defconfig
@@ -0,4 +124,128 @@
@@ -0,4 +210,214 @@
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SPI_NOR=y
@ -14,6 +14,91 @@ index 000000000000..51de9e95b7d2
+CONFIG_DRM_PANFROST=y
+CONFIG_STMMAC_PLATFORM=y
+
+#H616, SoC-specific
+CONFIG_SUN50I_A64_CCU=n
+CONFIG_SUN50I_A100_CCU=n
+CONFIG_SUN50I_A100_R_CCU=n
+CONFIG_SUN50I_H6_CCU=n
+CONFIG_SUN8I_H3_CCU=n
+CONFIG_SUN55I_A523_CCU=n
+CONFIG_SUN55I_A523_R_CCU=n
+CONFIG_ARCH_SUNXI=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_SUNXI_CCU=y
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_AC200_PHY=y
+CONFIG_AC200_PHY_SUNXI=y
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_STAGING=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_VIDEO_SUNXI=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MFD_AC200_SUNXI=y
+CONFIG_SUN50I_H616_CCU=y
+CONFIG_SND_SUN4I_CODEC=y
+CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
+CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
+CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
+CONFIG_CRYPTO_DEV_SUN8I_CE=y
+CONFIG_SUN50I_DE2_BUS=y
+CONFIG_SUN8I_DE2_CCU=y
+CONFIG_DRM_SUN8I_MIXER=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DWMAC_SUNXI=y
+CONFIG_DWMAC_SUN8I=y
+CONFIG_MMC_SUNXI=y
+CONFIG_SUN20I_GPADC=y
+CONFIG_DRM_SUN8I_DW_HDMI=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_SUN50I_IOMMU=y
+##CONFIG_IR_SUNXI=y
+CONFIG_KEYBOARD_SUN4I_LRADC=y
+CONFIG_SUNXI_NMI_INTC=y
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
+CONFIG_PINCTRL_SUN50I_H616=y
+CONFIG_SUN50I_H6_PRCM_PPU=y
+CONFIG_PWM_SUNXI_ENHANCE=y
+CONFIG_SUN50I_H6_R_CCU=y
+CONFIG_PINCTRL_SUN50I_H616_R=y
+CONFIG_SUNXI_RSB=y
+CONFIG_SUN6I_RTC_CCU=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_SND_SUN4I_SPDIF=y
+CONFIG_SPI_SUN6I=y
+CONFIG_SUNXI_SYS_INFO=y
+CONFIG_SUNXI_SRAM=y
+CONFIG_SUN8I_THERMAL=y
+CONFIG_VIDEO_SUNXI_CEDRUS=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_DRM_SUN4I=y
+CONFIG_DRM_SUN8I_TCON_TOP=y
+CONFIG_SUNXI_ADDR_MGT=y
+CONFIG_SUNXI_GMAC=y
+##CONFIG_CAN_MCP251X=y
+##CONFIG_FB_TFT_ST7796S=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_AXP20X_RSB=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_AXP20X_POWER=y
+CONFIG_AXP20X_ADC=y
+CONFIG_LEDS_AXP20X=y
+#minimize
+CONFIG_PINCTRL_SUN8I_H3_R=n
+CONFIG_PINCTRL_SUN50I_A64=n
+CONFIG_PINCTRL_SUN50I_A64_R=n
+CONFIG_PINCTRL_SUN50I_A100=n
+CONFIG_PINCTRL_SUN50I_A100_R=n
+CONFIG_PINCTRL_SUN50I_H5=n
+CONFIG_PINCTRL_SUN50I_H6=n
+CONFIG_PINCTRL_SUN50I_H6_R=n
+CONFIG_PINCTRL_SUN55I_A523=n
+CONFIG_PINCTRL_SUN55I_A523_R=n
+#sound
+CONFIG_SND_SOC_SUNXI_AHUB=y
+CONFIG_SND_SOC_SUNXI_AHUB_DAM=y
+
+#rk3566/3568, SoC-specific
+CONFIG_CLK_PX30=n
+CONFIG_CLK_RK3576=n

892
patch/kernel/rockchip64-6.14/add-board-fine3399-dts.patch
View File

@ -1,892 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Lemon1151 <smile1151@foxmail.com>
Date: Mon, 3 Jun 2024 12:32:02 +0200
Subject: Adding support for the fine3399 board
> X-Git-Archeology: - Revision 8f64f0508237888dd326018fa9a392346b8ec5ab: https://github.com/armbian/build/commit/8f64f0508237888dd326018fa9a392346b8ec5ab
> X-Git-Archeology: Date: Mon, 03 Jun 2024 12:32:02 +0200
> X-Git-Archeology: From: Lemon1151 <smile1151@foxmail.com>
> X-Git-Archeology: Subject: Adding support for the fine3399 board
---
arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts | 870 ++++++++++
1 file changed, 870 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts b/arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts
@@ -0,0 +1,870 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
+#include "rk3399.dtsi"
+
+
+/ {
+ model = "Rockchip Fine3399";
+ compatible = "rockchip,fine3399", "rockchip,rk3399";
+
+ aliases {
+ mmc0 = &sdio0;
+ mmc1 = &sdmmc;
+ mmc2 = &sdhci;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; // bsp
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v3_sys: vcc3v3_pcie: vcc3v3_bl: vcc3v3-sys { // sch
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc_sys: vcc-sys { // sch
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_phy_h>;
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led2>;
+
+ user_led2 {
+ label = "blue:work_led";
+ gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; // sch
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_key>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; // bsp
+ label = "GPIO Key Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 30 60 90 120 160>;
+ #cooling-cells = <2>;
+ fan-supply = <&vcc_sys>;
+ pwms = <&pwm1 0 40000 0>;
+ };
+
+ // pwm3
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1750000>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>; // ??
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <5>;
+ pwms = <&pwm0 0 1000000 0>;
+ status = "okay";
+ };
+
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&cpu_thermal {
+ trips {
+ cpu_warm: cpu_warm {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_hot: cpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map2 {
+ trip = <&cpu_warm>;
+ cooling-device = <&fan0 THERMAL_NO_LIMIT 1>;
+ };
+
+ map3 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan0 4 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; // bsp
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&gpu_thermal {
+ trips {
+ gpu_warm: gpu_warm {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ gpu_hot: gpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&gpu_warm>;
+ cooling-device = <&fan0 THERMAL_NO_LIMIT 1>;
+ };
+
+ map2 {
+ trip = <&gpu_hot>;
+ cooling-device = <&fan0 4 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
+ system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ vcc10-supply = <&vcc3v3_sys>;
+ vcc11-supply = <&vcc3v3_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc1v8_pmu>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG1 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v0_tp: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc3v0_tp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG3 {
+ regulator-name = "vcc1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sd: LDO_REG4 {
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-name = "vcca3v0_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-name = "vcca1v8_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpu_b_sleep>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpu_sleep>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+// Used for HDMI
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+// HDMI sound
+&i2s2 {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ bt656-supply = <&vcc_3v0>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vcc_sd>;
+ gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmu1830-supply = <&vcc_1v8>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; // sch
+ max-link-speed = <2>;
+ num-lanes = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
+
+&pinctrl {
+ pmic {
+ cpu_b_sleep: cpu-b-sleep {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ gpu_sleep: gpu-sleep {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pmic_dvs2: pmic-dvs2 {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_reg_on_h: wifi-reg-on-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_host_wake_l: wifi-host-wake-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ spi2 {
+ spi2_cs0: spi2-cs0 {
+ rockchip,pins =
+ <2 RK_PB4 2 &pcfg_pull_up>;
+ };
+ };
+
+ display_pin:display-pin {
+ DC_pin: dc-pin {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ reset_pin: reset-pin {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gmac {
+ vcc_phy_h: vcc-phy-h {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ user_led2: user_led2 {
+ rockchip,pins =
+ <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buttons {
+ power_key: power_key {
+ rockchip,pins =
+ <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+// TFT
+&pwm0 {
+ status = "okay";
+};
+
+// FAN
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ clock-frequency = <50000000>;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <50000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wake";
+ brcm,drive-strength = <5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_l>;
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // bsp
+ clock-frequency = <150000000>;
+ disable-wp;
+ sd-uhs-sdr104;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ vqmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ keep-power-in-suspend;
+ non-removable;
+ status = "okay";
+};
+/*
+&spi1 {
+ status = "okay";
+
+ norflash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+*/
+
+&spi2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_cs0>;
+
+ st7735r@0 {
+ status = "okay";
+ compatible = "sitronix,st7735r";
+ reg = <0>;
+ rgb;
+ rotate = <270>;
+ width = <80>;
+ height = <160>;
+ fps = <30>;
+ buswidth = <8>;
+ backlight = <&backlight>;
+ dc-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
+ led-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+ spi-max-frequency = <32000000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ max-speed = <4000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
+// Debug TTL
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+
+&iep_mmu {
+ status = "okay";
+};
--
Armbian

1020
patch/kernel/rockchip64-6.14/add-board-helios64.patch
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File diff suppressed because it is too large Load Diff

320
patch/kernel/rockchip64-6.14/board-firefly-rk3399-dts.patch
View File

@ -1,320 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: chainsx <chainsx@outlook.com>
Date: Fri, 17 May 2024 14:33:21 +0100
Subject: [ARCHEOLOGY] firefly-rk3399: move to rockchip64 family
> X-Git-Archeology: - Revision aa6ed7ce328617cf7eefa21d7e5f0a750d3a3477: https://github.com/armbian/build/commit/aa6ed7ce328617cf7eefa21d7e5f0a750d3a3477
> X-Git-Archeology: Date: Fri, 17 May 2024 14:33:21 +0100
> X-Git-Archeology: From: chainsx <chainsx@outlook.com>
> X-Git-Archeology: Subject: firefly-rk3399: move to rockchip64 family
> X-Git-Archeology:
> X-Git-Archeology: - Revision 7e574bd484de7238f0aba41dea5f3b5fb4e4fe8f: https://github.com/armbian/build/commit/7e574bd484de7238f0aba41dea5f3b5fb4e4fe8f
> X-Git-Archeology: Date: Sat, 18 May 2024 09:47:04 +0100
> X-Git-Archeology: From: chainsx <chainsx@outlook.com>
> X-Git-Archeology: Subject: firefly-rk3399: fix patch
> X-Git-Archeology:
> X-Git-Archeology: - Revision 5fe762e0a344f3487d8ff007f571b2407c817a25: https://github.com/armbian/build/commit/5fe762e0a344f3487d8ff007f571b2407c817a25
> X-Git-Archeology: Date: Sun, 19 May 2024 19:41:24 +0200
> X-Git-Archeology: From: chainsx <chainsx@outlook.com>
> X-Git-Archeology: Subject: Optimize the kernel device tree patch for rk3399-firefly.
> X-Git-Archeology:
> X-Git-Archeology: - Revision 69ca2492628b2aae217c33fde921b3840851eb14: https://github.com/armbian/build/commit/69ca2492628b2aae217c33fde921b3840851eb14
> X-Git-Archeology: Date: Wed, 05 Jun 2024 22:18:24 +0200
> X-Git-Archeology: From: Paolo Sabatino <paolo.sabatino@gmail.com>
> X-Git-Archeology: Subject: rockchip64: bump edge kernel to 6.9
> X-Git-Archeology:
> X-Git-Archeology: - Revision 4ae0a958146810117050d0dbd359b99691a0fa0c: https://github.com/armbian/build/commit/4ae0a958146810117050d0dbd359b99691a0fa0c
> X-Git-Archeology: Date: Mon, 22 Jul 2024 19:17:52 +0200
> X-Git-Archeology: From: Paolo Sabatino <paolo.sabatino@gmail.com>
> X-Git-Archeology: Subject: rockchip64: bump edge kernel to 6.10
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 133 +++++++---
1 file changed, 103 insertions(+), 30 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -216,7 +216,7 @@ vcc5v0_host: regulator-vcc5v0-host {
enable-active-high;
gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
+ pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc_sys>;
@@ -235,8 +235,11 @@ vcc5v0_typec: regulator-vcc5v0-typec {
vcc_sys: regulator-vcc-sys {
compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_sys_en>;
regulator-name = "vcc_sys";
- regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -253,6 +256,27 @@ vdd_log: regulator-vdd-log {
regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
};
+
+ vcca_0v9: vcca-0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcca_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_3g: vcc3v3-3g-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_3g_drv>;
+ regulator-name = "vcc3v3_3g";
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&cpu_l0 {
@@ -305,6 +329,8 @@ &gpu {
};
&hdmi {
+ avdd-0v9-supply = <&vcca0v9_hdmi>;
+ avdd-1v8-supply = <&vcca1v8_hdmi>;
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
@@ -329,18 +355,18 @@ rk808: pmic@1b {
system-power-controller;
wakeup-source;
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc6-supply = <&vcc_sys>;
- vcc7-supply = <&vcc_sys>;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc_sys>;
- vcc10-supply = <&vcc_sys>;
- vcc11-supply = <&vcc_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ vcc10-supply = <&vcc3v3_sys>;
+ vcc11-supply = <&vcc3v3_sys>;
vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc1v8_pmu>;
+ vddio-supply = <&vcc_3v0>;
regulators {
vdd_center: DCDC_REG1 {
@@ -388,8 +414,8 @@ regulator-state-mem {
};
};
- vcc1v8_dvp: LDO_REG1 {
- regulator-name = "vcc1v8_dvp";
+ vcca1v8_codec: LDO_REG1 {
+ regulator-name = "vcca1v8_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@@ -399,12 +425,12 @@ regulator-state-mem {
};
};
- vcc2v8_dvp: LDO_REG2 {
- regulator-name = "vcc2v8_dvp";
+ vcca1v8_hdmi: LDO_REG2 {
+ regulator-name = "vcca1v8_hdmi";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -457,12 +483,12 @@ regulator-state-mem {
};
};
- vcca1v8_codec: LDO_REG7 {
- regulator-name = "vcca1v8_codec";
+ vcca0v9_hdmi: LDO_REG7 {
+ regulator-name = "vcca0v9_hdmi";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -503,14 +529,16 @@ regulator-state-mem {
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
- fcs,suspend-voltage-selector = <0>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel1_pin>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
- vin-supply = <&vcc_sys>;
+ vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -521,13 +549,15 @@ vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel2_pin>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
- vin-supply = <&vcc_sys>;
+ vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -564,7 +594,7 @@ &i2c4 {
status = "okay";
fusb0: typec-portc@22 {
- compatible = "fcs,fusb302";
+ compatible = "fairchild,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
@@ -637,7 +667,7 @@ &i2s2 {
&io_domains {
status = "okay";
- bt656-supply = <&vcc1v8_dvp>;
+ bt656-supply = <&vcc_3v0>;
audio-supply = <&vcca1v8_codec>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
@@ -651,7 +681,10 @@ &pcie0 {
ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn_cpm>;
+ pinctrl-0 = <&pcie_perst>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ vpcie1v8-supply = <&vcc1v8_pmu>;
+ vpcie0v9-supply = <&vcca_0v9>;
status = "okay";
};
@@ -703,6 +736,10 @@ pcie_pwr_en: pcie-pwr-en {
pcie_3g_drv: pcie-3g-drv {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
+
+ pcie_perst: pcie-perst {
+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
pmic {
@@ -741,6 +778,14 @@ usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
+
+ vcc_sys_en: vcc-sys-en {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ hub_rst: hub-rst {
+ rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>;
+ };
};
wifi {
@@ -748,6 +793,20 @@ wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ bt {
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_reg_on_h: bt-reg-on-h {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pwm0 {
@@ -787,7 +846,7 @@ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
@@ -884,8 +943,22 @@ u2phy1_host: host-port {
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ max-speed = <4000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+ };
};
&uart2 {
--
Armbian

72
patch/kernel/rockchip64-6.14/board-helios64-dts-fix-stability-issues.patch
View File

@ -1,72 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Aditya Prayoga <aprayoga@users.noreply.github.com>
Date: Thu, 4 Mar 2021 10:39:40 +0700
Subject: Attempt to improve stability on Helios64 (#2680)
> X-Git-Archeology: > recovered message: > * Adjust the RK808 buck step to improve stability
> X-Git-Archeology: > recovered message: > * Adjust vdd_log and enable vdd_center init voltage
> X-Git-Archeology: > recovered message: > For some reason, regulator-init-microvolt property under PMIC does not applied. Set the voltage on board file.
> X-Git-Archeology: - Revision eefad69215557708b151a5d9244617a4ffd1281c: https://github.com/armbian/build/commit/eefad69215557708b151a5d9244617a4ffd1281c
> X-Git-Archeology: Date: Thu, 04 Mar 2021 10:39:40 +0700
> X-Git-Archeology: From: Aditya Prayoga <aprayoga@users.noreply.github.com>
> X-Git-Archeology: Subject: Attempt to improve stability on Helios64 (#2680)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
@@ -502,6 +502,7 @@ rk808: pmic@1b {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
+ max-buck-steps-per-change = <4>;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
--
Armbian

25
patch/kernel/rockchip64-6.14/board-helios64-remove-pcie-ep-gpios.patch
View File

@ -1,25 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Aditya Prayoga <aditya@kobol.io>
Date: Tue, 15 Sep 2020 13:42:02 +0700
Subject: Remove PCIE ep-gpios from Helios64
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
---
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
@@ -800,7 +800,6 @@ &pcie_phy {
};
&pcie0 {
- ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
max-link-speed = <2>;
num-lanes = <2>;
pinctrl-names = "default";
--
Armbian

147
patch/kernel/rockchip64-6.14/board-nanopc-t4-add-typec-dp.patch
View File

@ -1,147 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: tonymac32 <tonymckahan@gmail.com>
Date: Wed, 17 Feb 2021 00:54:00 -0500
Subject: Patching something
Signed-off-by: tonymac32 <tonymckahan@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts | 96 ++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
@@ -9,6 +9,7 @@
*/
/dts-v1/;
+#include <dt-bindings/usb/pd.h>
#include "rk3399-nanopi4.dtsi"
/ {
@@ -66,6 +67,12 @@ fan: pwm-fan {
};
};
+&cdn_dp {
+ status = "okay";
+ extcon = <&fusb0>;
+ phys = <&tcphy0_dp>;
+};
+
&cpu_thermal {
trips {
cpu_warm: cpu_warm {
@@ -94,6 +101,50 @@ map3 {
};
};
+&fusb0 {
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 1200, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <5000000>;
+
+ extcon-cables = <1 2 5 6 9 10 12 44>;
+ typec-altmodes = <0xff01 1 0x001c0000 1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ usb_con_hs: endpoint {
+ remote-endpoint =
+ <&u2phy0_typec_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+
+ usb_con_ss: endpoint {
+ remote-endpoint =
+ <&tcphy0_typec_ss>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ usb_con_dp: endpoint {
+ remote-endpoint =
+ <&tcphy0_typec_dp>;
+ };
+ };
+ };
+ };
+};
+
&pcie0 {
ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
@@ -114,12 +165,57 @@ &sdhci {
mmc-hs400-enhanced-strobe;
};
+&tcphy0 {
+ extcon = <&fusb0>;
+ status = "okay";
+};
+
+&tcphy0_dp {
+ port {
+ tcphy0_typec_dp: endpoint {
+ remote-endpoint = <&usb_con_dp>;
+ };
+ };
+};
+
+&tcphy0_usb3 {
+ port {
+ tcphy0_typec_ss: endpoint {
+ remote-endpoint = <&usb_con_ss>;
+ };
+ };
+};
+
+&u2phy0 {
+ extcon = <&fusb0>;
+};
+
&u2phy0_host {
phy-supply = <&vcc5v0_host0>;
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+
+ port {
+ u2phy0_typec_hs: endpoint {
+ remote-endpoint = <&usb_con_hs>;
+ };
+ };
};
&u2phy1_host {
phy-supply = <&vcc5v0_host0>;
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ extcon = <&fusb0>;
};
&vcc5v0_sys {
--
Armbian

190
patch/kernel/rockchip64-6.14/board-nanopi-m4v2-dts-add-sound-card.patch
View File

@ -1,190 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Piotr Szczepanik <piter75@gmail.com>
Date: Thu, 28 Nov 2019 22:29:54 +0000
Subject: [ARCHEOLOGY] Initial addition of NanoPi M4V2
> X-Git-Archeology: - Revision c4eecbcef0d4dc499baf0155449e71dc774bc7c4: https://github.com/armbian/build/commit/c4eecbcef0d4dc499baf0155449e71dc774bc7c4
> X-Git-Archeology: Date: Thu, 28 Nov 2019 22:29:54 +0000
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Initial addition of NanoPi M4V2
> X-Git-Archeology:
> X-Git-Archeology: - Revision 40a3d4ecb9a75c17183e2129491b7bc03060a315: https://github.com/armbian/build/commit/40a3d4ecb9a75c17183e2129491b7bc03060a315
> X-Git-Archeology: Date: Sun, 17 May 2020 18:42:24 +0200
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Fixed rt5651 codec probing after its driver was changed to module (#1969)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125)
> X-Git-Archeology:
> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 401fb1fde426c93121c4639b34a450d8ff551c85: https://github.com/armbian/build/commit/401fb1fde426c93121c4639b34a450d8ff551c85
> X-Git-Archeology: Date: Sat, 20 Nov 2021 19:49:22 +0100
> X-Git-Archeology: From: simple <991605149@qq.com>
> X-Git-Archeology: Subject: Fixed rt5651 codec build module (#3270)
> X-Git-Archeology:
> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 51 ++++++++++
sound/soc/rockchip/Kconfig | 9 ++
2 files changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -132,6 +132,27 @@ status_led: led-0 {
};
};
+ rt5651-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "realtek,rt5651-codec";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Mic Jack", "micbias1",
+ "IN1P", "Mic Jack",
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&rt5651>;
+ };
+ };
+
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
@@ -216,6 +237,10 @@ &hdmi_sound {
status = "okay";
};
+&hdmi_sound {
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <160>;
@@ -463,6 +488,16 @@ &i2c1 {
i2c-scl-rising-time-ns = <150>;
i2c-scl-falling-time-ns = <30>;
status = "okay";
+
+ rt5651: rt5651@1a {
+ compatible = "realtek,rt5651";
+ reg = <0x1a>;
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
+ clock-names = "mclk";
+ hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
+ // spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ #sound-dai-cells = <0>;
+ };
};
&i2c2 {
@@ -494,6 +529,16 @@ &i2s2 {
status = "okay";
};
+&i2s1 {
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <8>;
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
&io_domains {
bt656-supply = <&vcc_1v8>;
audio-supply = <&vcca1v8_codec>;
@@ -759,3 +804,9 @@ &vopl {
&vopl_mmu {
status = "okay";
};
+
+&spdif {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index 111111111111..222222222222 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -65,6 +65,15 @@ config SND_SOC_ROCKCHIP_RT5645
Say Y or M here if you want to add support for SoC audio on Rockchip
boards using the RT5645/RT5650 codec, such as Veyron.
+config SND_SOC_ROCKCHIP_RT5651
+ tristate "ASoC support for Rockchip boards using a RT5651 codec"
+ depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK
+ select SND_SOC_ROCKCHIP_I2S
+ select SND_SOC_RT5651
+ help
+ Say Y or M here if you want to add support for SoC audio on Rockchip
+ boards using the RT5651 codec, such as FriendlyARM's Nano{Pi,PC} family.
+
config SND_SOC_RK3288_HDMI_ANALOG
tristate "ASoC support multiple codecs for Rockchip RK3288 boards"
depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK
--
Armbian

30
patch/kernel/rockchip64-6.14/board-nanopi-r2c-plus.patch
View File

@ -1,30 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: amazingfate <liujianfeng1994@gmail.com>
Date: Thu, 31 Aug 2023 11:41:37 +0200
Subject: [ARCHEOLOGY] rockchip64: bump rockchip64-edge kernel to 6.5
> X-Git-Archeology: - Revision 8254411054a99f9750770bb6055facfbdedacbba: https://github.com/armbian/build/commit/8254411054a99f9750770bb6055facfbdedacbba
> X-Git-Archeology: Date: Thu, 31 Aug 2023 11:41:37 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: rockchip64: bump rockchip64-edge kernel to 6.5
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
@@ -28,7 +28,7 @@ &emmc {
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- vmmc-supply = <&vcc_io_33>;
+ vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc18_emmc>;
status = "okay";
};
--
Armbian

720
patch/kernel/rockchip64-6.14/board-nanopi-r2s.patch
View File

@ -1,720 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 7 Jan 2023 11:59:47 +0000
Subject: rockchip64: consolidate nanopi r2s device trees
---
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi | 472 +++++++---
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi | 6 +-
2 files changed, 318 insertions(+), 160 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi
@@ -1,116 +1,155 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
+#include "rk3328-dram-default-timing.dtsi"
#include "rk3328.dtsi"
/ {
+ model = "FriendlyElec boards based on Rockchip RK3328";
+ compatible = "friendlyelec,nanopi-r2",
+ "rockchip,rk3328";
+
aliases {
ethernet0 = &gmac2io;
- ethernet1 = &rtl8153;
- mmc0 = &sdmmc;
+ ethernet1 = &r8153;
};
chosen {
+ bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0";
stdout-path = "serial2:1500000n8";
};
- gmac_clk: gmac-clock {
+ gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&reset_button_pin>;
- pinctrl-names = "default";
-
- key-reset {
- label = "reset";
- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <50>;
- };
+ mach: board {
+ compatible = "friendlyelec,board";
+ machine = "NANOPI-R2";
+ hwrev = <255>;
+ model = "NanoPi R2 Series";
+ nvmem-cells = <&efuse_id>, <&efuse_cpu_version>;
+ nvmem-cell-names = "id", "cpu-version";
};
- leds {
+ leds: gpio-leds {
compatible = "gpio-leds";
- pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
pinctrl-names = "default";
+ pinctrl-0 =<&leds_gpio>;
+ status = "disabled";
- lan_led: led-0 {
- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
- label = "nanopi-r2s:green:lan";
- };
-
- sys_led: led-1 {
+ led@1 {
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
- label = "nanopi-r2s:red:sys";
- default-state = "on";
- };
-
- wan_led: led-2 {
- gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
- label = "nanopi-r2s:green:wan";
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ linux,default-trigger-delay-ms = <0>;
};
};
- vcc_io_sdio: regulator-sdmmcio {
- compatible = "regulator-gpio";
- enable-active-high;
- gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&sdio_vcc_pin>;
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk805 1>;
+ clock-names = "ext_clock";
pinctrl-names = "default";
- regulator-name = "vcc_io_sdio";
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-settling-time-us = <5000>;
- regulator-type = "voltage";
- startup-delay-us = <2000>;
- states = <1800000 0x1>,
- <3300000 0x0>;
- vin-supply = <&vcc_io_33>;
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
};
vcc_sd: regulator-sdmmc {
compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&sdmmc0m1_pin>;
+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
- regulator-name = "vcc_sd";
+ pinctrl-0 = <&sdmmc0m1_pin>;
regulator-boot-on;
+ regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_io_33>;
+ vin-supply = <&vcc_io>;
};
- vdd_5v: regulator-vdd-5v {
+ vccio_sd: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ regulator-name = "vccio_sd";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc_io>;
+ startup-delay-us = <2000>;
+ regulator-settling-time-us = <5000>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ vcc_sys: vcc-sys {
compatible = "regulator-fixed";
- regulator-name = "vdd_5v";
+ regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
- vdd_5v_lan: regulator-vdd-5v-lan {
+ vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&lan_vdd_pin>;
- pinctrl-names = "default";
- regulator-name = "vdd_5v_lan";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_host_vbus: host-vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_host_vbus";
regulator-always-on;
regulator-boot-on;
- vin-supply = <&vdd_5v>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ /delete-node/ dmc-opp-table;
+
+ dmc_opp_table: dmc_opp_table {
+ compatible = "operating-points-v2";
+
+ opp-786000000 {
+ opp-hz = /bits/ 64 <786000000>;
+ opp-microvolt = <1075000 1075000 1200000>;
+ };
+ opp-798000000 {
+ opp-hz = /bits/ 64 <798000000>;
+ opp-microvolt = <1075000 1075000 1200000>;
+ };
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-microvolt = <1075000 1075000 1200000>;
+ };
+ opp-924000000 {
+ opp-hz = /bits/ 64 <924000000>;
+ opp-microvolt = <1100000 1100000 1200000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1175000 1175000 1200000>;
+ };
};
};
@@ -118,30 +157,57 @@ &cpu0 {
cpu-supply = <&vdd_arm>;
};
-&cpu1 {
- cpu-supply = <&vdd_arm>;
+&dfi {
+ status = "okay";
};
-&cpu2 {
- cpu-supply = <&vdd_arm>;
+&dmc {
+ center-supply = <&vdd_logic>;
+ ddr_timing = <&ddr_timing>;
+ status = "okay";
};
-&cpu3 {
- cpu-supply = <&vdd_arm>;
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-hs200-1_8v;
+ no-sd;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
};
-&display_subsystem {
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
status = "disabled";
};
&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
clock_in_out = "input";
- phy-mode = "rgmii";
- phy-supply = <&vcc_io_33>;
- pinctrl-0 = <&rgmiim1_pins>;
pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ phy-handle = <&rtl8211e>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_phy>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,rxpbl = <0x4>;
+ snps,txpbl = <0x4>;
+ tx_delay = <0x24>;
+ rx_delay = <0x18>;
+ status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
@@ -153,36 +219,35 @@ mdio {
&i2c1 {
status = "okay";
- rk805: pmic@18 {
+ rk805: rk805@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
- interrupt-parent = <&gpio1>;
- interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
- pinctrl-0 = <&pmic_int_l>;
pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
- vcc1-supply = <&vdd_5v>;
- vcc2-supply = <&vdd_5v>;
- vcc3-supply = <&vdd_5v>;
- vcc4-supply = <&vdd_5v>;
- vcc5-supply = <&vcc_io_33>;
- vcc6-supply = <&vdd_5v>;
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-init-microvolt = <1075000>;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <12500>;
-
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@@ -191,12 +256,11 @@ regulator-state-mem {
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
+ regulator-init-microvolt = <1225000>;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <12500>;
-
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
@@ -207,19 +271,17 @@ vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
-
regulator-state-mem {
regulator-on-in-suspend;
};
};
- vcc_io_33: DCDC_REG4 {
- regulator-name = "vcc_io_33";
- regulator-always-on;
- regulator-boot-on;
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
-
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
@@ -228,11 +290,10 @@ regulator-state-mem {
vcc_18: LDO_REG1 {
regulator-name = "vcc_18";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
-
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@@ -241,11 +302,10 @@ regulator-state-mem {
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc18_emmc";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
-
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@@ -254,11 +314,10 @@ regulator-state-mem {
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
-
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@@ -269,20 +328,21 @@ regulator-state-mem {
};
&io_domains {
- pmuio-supply = <&vcc_io_33>;
- vccio1-supply = <&vcc_io_33>;
- vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io_sdio>;
- vccio4-supply = <&vcc_18>;
- vccio5-supply = <&vcc_io_33>;
- vccio6-supply = <&vcc_io_33>;
status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_io>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_18>;
+ pmuio-supply = <&vcc_io>;
};
&pinctrl {
- button {
- reset_button_pin: reset-button-pin {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
@@ -292,61 +352,165 @@ eth_phy_reset_pin: eth-phy-reset-pin {
};
};
- leds {
- lan_led_pin: lan-led-pin {
- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ };
- sys_led_pin: sys-led-pin {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ sdmmc0 {
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
};
- wan_led_pin: wan-led-pin {
- rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_dectn: sdmmc0-dectn {
+ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA1 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA2 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA3 1 &pcfg_pull_up_4ma>;
};
};
- lan {
- lan_vdd_pin: lan-vdd-pin {
- rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ sdmmc0ext {
+ sdmmc0ext_clk: sdmmc0ext-clk {
+ rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>;
+ };
+
+ sdmmc0ext_cmd: sdmmc0ext-cmd {
+ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>;
+ };
+
+ sdmmc0ext_bus4: sdmmc0ext-bus4 {
+ rockchip,pins =
+ <3 RK_PA4 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA5 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA6 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA7 3 &pcfg_pull_up_2ma>;
};
};
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ gmac-1 {
+ rgmiim1_pins: rgmiim1-pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <1 RK_PB4 2 &pcfg_pull_none_4ma>,
+ /* mac_rxclk */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* mac_mdio */
+ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
+ /* mac_txen */
+ <1 RK_PD1 2 &pcfg_pull_none_4ma>,
+ /* mac_clk */
+ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
+ /* mac_rxdv */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* mac_mdc */
+ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
+ /* mac_rxd1 */
+ <1 RK_PB2 2 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <1 RK_PB3 2 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <1 RK_PB0 2 &pcfg_pull_none_4ma>,
+ /* mac_txd0 */
+ <1 RK_PB1 2 &pcfg_pull_none_4ma>,
+ /* mac_rxd3 */
+ <1 RK_PB6 2 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <1 RK_PB7 2 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <1 RK_PC0 2 &pcfg_pull_none_4ma>,
+ /* mac_txd2 */
+ <1 RK_PC1 2 &pcfg_pull_none_4ma>,
+
+ /* mac_txclk */
+ <0 RK_PB0 1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 RK_PB4 1 &pcfg_pull_none>,
+ /* mac_clk */
+ <0 RK_PD0 1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 RK_PC0 1 &pcfg_pull_none>,
+ /* mac_txd0 */
+ <0 RK_PC1 1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <0 RK_PC7 1 &pcfg_pull_none>,
+ /* mac_txd2 */
+ <0 RK_PC6 1 &pcfg_pull_none>;
};
};
- sd {
- sdio_vcc_pin: sdio-vcc-pin {
- rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
-&pwm2 {
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ vmmc-supply = <&vcc_sd>;
status = "okay";
};
-&sdmmc {
+&sdmmc_ext {
bus-width = <4>;
cap-sd-highspeed;
+ cap-sdio-irq;
disable-wp;
- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
pinctrl-names = "default";
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
+ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>;
+ rockchip,default-sample-phase = <120>;
+ supports-sdio;
sd-uhs-sdr104;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vcc_io_sdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
};
&tsadc {
- rockchip,hw-tshut-mode = <0>;
- rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
status = "okay";
};
@@ -362,13 +526,16 @@ &u2phy_otg {
status = "okay";
};
-&uart2 {
+&usb20_otg {
status = "okay";
};
-&usb20_otg {
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
status = "okay";
- dr_mode = "host";
};
&usbdrd3 {
@@ -377,17 +544,10 @@ &usbdrd3 {
#address-cells = <1>;
#size-cells = <0>;
- /* Second port is for USB 3.0 */
- rtl8153: device@2 {
+ r8153: device@2 {
compatible = "usbbda,8153";
reg = <2>;
+ realtek,led-data = <0x87>;
+ local-mac-address = [00 00 00 00 00 00];
};
};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi
@@ -19,11 +19,9 @@ &gmac2io {
mdio {
rtl8211e: ethernet-phy@1 {
reg = <1>;
- pinctrl-0 = <&eth_phy_reset_pin>;
- pinctrl-names = "default";
reset-assert-us = <10000>;
- reset-deassert-us = <50000>;
- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ reset-deassert-us = <30000>;
+ /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */
};
};
};
--
Armbian

181
patch/kernel/rockchip64-6.14/board-nanopi-r3s-fix-leds.patch
View File

@ -1,181 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: John Doe <john.doe@somewhere.on.planet>
Date: Tue, 28 Jan 2025 12:13:35 +0800
Subject: Patching NanoPi-R3S LEDs
Signed-off-by: John Doe <john.doe@somewhere.on.planet>
---
arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 41 +++++++---
drivers/net/ethernet/realtek/r8169_main.c | 11 +++
drivers/net/phy/realtek/realtek_main.c | 11 +++
3 files changed, 53 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
@@ -52,19 +52,21 @@ power_led: led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- default-state = "on";
+ linux,default-trigger = "heartbeat";
};
lan_led: led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "r8169-0-100:00:link";
};
wan_led: led-2 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "stmmac-0:01:link";
};
};
@@ -137,18 +139,27 @@ &cpu3 {
};
&gmac1 {
+ phy-mode = "rgmii";
+ clock_in_out = "output";
+
+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 15ms, 50ms for rtl8211f */
+ snps,reset-delays-us = <0 15000 50000>;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
assigned-clock-rates = <0>, <125000000>;
- clock_in_out = "output";
- phy-mode = "rgmii-id";
- phy-handle = <&rgmii_phy1>;
+
pinctrl-names = "default";
pinctrl-0 = <&gmac1m0_miim
&gmac1m0_tx_bus2_level3
&gmac1m0_rx_bus2
&gmac1m0_rgmii_clk_level2
&gmac1m0_rgmii_bus_level3>;
+ tx_delay = <0x3c>;
+ rx_delay = <0x2f>;
+
+ phy-handle = <&rgmii_phy1>;
status = "okay";
};
@@ -409,10 +420,8 @@ rgmii_phy1: ethernet-phy@1 {
interrupt-parent = <&gpio4>;
interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&eth_phy_reset_pin>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&gmac_int>;
+ realtek,ledsel = <0xae00>;
};
};
@@ -421,6 +430,18 @@ &pcie2x1 {
pinctrl-0 = <&pcie_reset_h>;
reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ r8169: pcie@1,0 {
+ reg = <0x000000 0 0 0 0>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ realtek,ledsel = <0x870>;
+ };
+ };
};
&pinctrl {
@@ -439,8 +460,8 @@ wan_led_pin: wan-led-pin {
};
gmac {
- eth_phy_reset_pin: eth-phy-reset-pin {
- rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
+ gmac_int: gmac-int {
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index 111111111111..222222222222 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -21,6 +21,7 @@
#include <linux/in.h>
#include <linux/io.h>
#include <linux/ip.h>
+#include <linux/of.h>
#include <linux/tcp.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
@@ -2436,6 +2437,15 @@ void r8169_apply_firmware(struct rtl8169_private *tp)
}
}
+static void rtl8168_led_of_init(struct rtl8169_private *tp)
+{
+ struct device *d = tp_to_dev(tp);
+ u32 val;
+
+ if (!of_property_read_u32(d->of_node, "realtek,ledsel", &val))
+ RTL_W16(tp, LED_CTRL, val);
+}
+
static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
{
/* Adjust EEE LED frequency */
@@ -3421,6 +3431,7 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
rtl8168_config_eee_mac(tp);
+ rtl8168_led_of_init(tp);
RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c
index 111111111111..222222222222 100644
--- a/drivers/net/phy/realtek/realtek_main.c
+++ b/drivers/net/phy/realtek/realtek_main.c
@@ -125,6 +125,15 @@ static int rtl821x_write_page(struct phy_device *phydev, int page)
return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
}
+static void rtl821x_led_of_init(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ u32 val;
+
+ if (!of_property_read_u32(dev->of_node, "realtek,ledsel", &val))
+ phy_write_paged(phydev, 0xd04, 0x10, val);
+}
+
static int rtl821x_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
@@ -444,6 +453,8 @@ static int rtl8211f_config_init(struct phy_device *phydev)
val_rxdly ? "enabled" : "disabled");
}
+ rtl821x_led_of_init(phydev);
+
if (priv->has_phycr2) {
ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
RTL8211F_CLKOUT_EN, priv->phycr2);
--
Armbian

58
patch/kernel/rockchip64-6.14/board-nanopi-r4s-pwmfan.patch
View File

@ -1,58 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Bochun Bai <bbc@sinofool.net>
Date: Sun, 18 Jun 2023 11:56:34 +0200
Subject: Add pwm-fan support to nanopi r4s
---
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi | 35 ++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi
@@ -60,6 +60,41 @@ vdd_5v: regulator-vdd-5v {
regulator-always-on;
regulator-boot-on;
};
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 18 102 170 255>;
+ fan-supply = <&vdd_5v>;
+ pwms = <&pwm1 0 50000 0>;
+ };
+};
+
+&cpu_thermal {
+ trips {
+ cpu_warm: cpu_warm {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_hot: cpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map2 {
+ trip = <&cpu_warm>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map3 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
};
&emmc_phy {
--
Armbian

57
patch/kernel/rockchip64-6.14/board-odroidm1-add-nodes-for-i2c-pwm-uart-spi.patch
View File

@ -1,57 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Ricardo Pardini <ricardo@pardini.net>
Date: Thu, 9 Jan 2025 19:22:12 +0100
Subject: rk3568-odroid-m1: add nodes for i2c/pwm/spi/uart overlays
- we used to have a bare-dt for odroid-m1 that got removed as it landed upstream
- but mainline doesn't have the nodes we use for the overlays
- at least i2c3 (which is aliased to i2c0) and uart1 breaks without them
---
arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 34 ++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
@@ -739,3 +739,37 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
remote-endpoint = <&hdmi_in_vp0>;
};
};
+
+&i2c3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m1_xfer>;
+};
+
+&pwm1 {
+ status = "disabled";
+ pinctrl-0 = <&pwm1m1_pins>;
+};
+
+&pwm2 {
+ status = "disabled";
+ pinctrl-0 = <&pwm2m1_pins>;
+};
+
+&spi0 {
+ status = "disabled";
+
+ pinctrl-0 = <&spi0m1_pins>;
+ pinctrl-1 = <&spi0m1_pins_hs>;
+ num_chipselect = <1>;
+
+ cs-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
+};
+
+&uart1 {
+ status = "disabled";
+ dma-names = "tx", "rx";
+ /* uart1 uart1-with-ctsrts */
+ pinctrl-0 = <&uart1m1_xfer>;
+ pinctrl-1 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>;
+};
--
Armbian

64
patch/kernel/rockchip64-6.14/board-odroidm2-fix-for-ethernet.patch
View File

@ -1,64 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Milivoje Legenovic <m.legenovic@gmail.com>
Date: Sat, 22 Mar 2025 13:46:35 +0100
Subject: [ARCHEOLOGY] Fix for ethernet warnings in dmesg output
> X-Git-Archeology: - Revision 896a8090c1c194999591326b1dcb55b377e4460c: https://github.com/armbian/build/commit/896a8090c1c194999591326b1dcb55b377e4460c
> X-Git-Archeology: Date: Sat, 22 Mar 2025 13:46:35 +0100
> X-Git-Archeology: From: Milivoje Legenovic <m.legenovic@gmail.com>
> X-Git-Archeology: Subject: Fix for ethernet warnings in dmesg output
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts | 14 ++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts
@@ -229,9 +229,9 @@ &cpu_l3 {
};
&gmac1 {
- clock_in_out = "output";
+ clock_in_out = "input";
phy-handle = <&rgmii_phy1>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii";
phy-supply = <&vcc_3v3_s0>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1_miim
@@ -241,6 +241,8 @@ &gmac1_rgmii_clk
&gmac1_rgmii_bus
&gmac1_clkinout>;
status = "okay";
+ tx_delay = <0x3a>;
+ rx_delay = <0x3e>;
};
&gpu {
@@ -400,6 +402,8 @@ &mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8211f_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
@@ -475,6 +479,12 @@ pcf8563_int: pcf8563-int {
};
};
+ rtl8211f {
+ rtl8211f_rst: rtl8211f-rst {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
usb {
usb2_host_pwren: usb2-host-pwren {
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
--
Armbian

216
patch/kernel/rockchip64-6.14/board-orangepi-r1-plus.patch
View File

@ -1,216 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
Date: Sat, 20 Jun 2020 22:39:57 +0200
Subject: [ARCHEOLOGY] Initial ROCK Pi E support (as WIP) (#2042)
> X-Git-Archeology: > recovered message: > * WIP: Adding RockpiE config
> X-Git-Archeology: > recovered message: > Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: > recovered message: > * Mainline u-boot for ROCK Pi E
> X-Git-Archeology: > recovered message: > * Initial ROCK Pi E device tree in kernel
> X-Git-Archeology: > recovered message: > * Fixed supplies for ROCK Pi E device tree
> X-Git-Archeology: > recovered message: > * Adjusted u-boot load address for rockchip64 boards with 256MB eg. ROCK Pi E
> X-Git-Archeology: > recovered message: > * Blacklisted lima on ROCK Pi E
> X-Git-Archeology: > recovered message: > * Fixed ROCK Pi E patch after merge from master
> X-Git-Archeology: > recovered message: > * Removed mode settings from rk805 regulators
> X-Git-Archeology: > recovered message: > * Fixed issues with offloading for gigabit interface of RockPi E
> X-Git-Archeology: > recovered message: > * Adjusted ROCK Pi E board config
> X-Git-Archeology: > recovered message: > * Added dev branch for ROCK Pi E
> X-Git-Archeology: > recovered message: > * Add build targets
> X-Git-Archeology: > recovered message: > Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: > recovered message: > * Exchange legacy to current in ROCK Pi E build targets
> X-Git-Archeology: > recovered message: > Co-authored-by: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: - Revision e1ecb098330dc372740371dc2386f911833a0529: https://github.com/armbian/build/commit/e1ecb098330dc372740371dc2386f911833a0529
> X-Git-Archeology: Date: Sat, 20 Jun 2020 22:39:57 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Initial ROCK Pi E support (as WIP) (#2042)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 72257bd0648c28fca32962126bb885a4a2c188cc: https://github.com/armbian/build/commit/72257bd0648c28fca32962126bb885a4a2c188cc
> X-Git-Archeology: Date: Tue, 23 Jun 2020 16:37:54 +0200
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Make USB3 support of ROCK Pi E on par with other rk3328 boards (#2050)
> X-Git-Archeology:
> X-Git-Archeology: - Revision e36ce875b025e112127cf8cc2d34825ebfe36569: https://github.com/armbian/build/commit/e36ce875b025e112127cf8cc2d34825ebfe36569
> X-Git-Archeology: Date: Tue, 10 Nov 2020 21:43:13 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switched rockchip64-current to linux 5.9.y (#2309)
> X-Git-Archeology:
> X-Git-Archeology: - Revision ccbc888b3f5731790128684959b55b6552e26190: https://github.com/armbian/build/commit/ccbc888b3f5731790128684959b55b6552e26190
> X-Git-Archeology: Date: Sat, 28 Nov 2020 16:52:34 +0100
> X-Git-Archeology: From: Oleg <balbes-150@yandex.ru>
> X-Git-Archeology: Subject: add dts rk3328-roc-pc, fix WIFI and USB 3.0 rk3328 (#2390)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 25bd76527e1276c4c00829f68c0ca0742ecc94c1: https://github.com/armbian/build/commit/25bd76527e1276c4c00829f68c0ca0742ecc94c1
> X-Git-Archeology: Date: Sat, 28 Nov 2020 18:10:53 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Fix roc-rk3328-pc device tree reference to missing RK_FUNC_1
> X-Git-Archeology:
> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070
> X-Git-Archeology: Date: Sun, 13 Dec 2020 22:13:03 -0500
> X-Git-Archeology: From: tonymac32 <tonymckahan@gmail.com>
> X-Git-Archeology: Subject: [ rockchip64 ] Clean up patchset
> X-Git-Archeology:
> X-Git-Archeology: - Revision 25e0f1633467c020f6ae68d09964a522fbfbe613: https://github.com/armbian/build/commit/25e0f1633467c020f6ae68d09964a522fbfbe613
> X-Git-Archeology: Date: Mon, 18 Jan 2021 23:21:40 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Adjusted power and pmic configuration for Station M1 in current/dev
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision d8dbefd61838e5b0cfc2b93d2d168f3fb2666dfb: https://github.com/armbian/build/commit/d8dbefd61838e5b0cfc2b93d2d168f3fb2666dfb
> X-Git-Archeology: Date: Tue, 27 Jul 2021 00:05:09 -0400
> X-Git-Archeology: From: tonymac32 <tonymckahan@gmail.com>
> X-Git-Archeology: Subject: [ rockchip64 ] rk3328 change to mainline USB3
> X-Git-Archeology:
> X-Git-Archeology: - Revision a16699260fb786a4d89a1c335722e9fed49d19d2: https://github.com/armbian/build/commit/a16699260fb786a4d89a1c335722e9fed49d19d2
> X-Git-Archeology: Date: Fri, 08 Jul 2022 22:35:59 +1200
> X-Git-Archeology: From: schwar3kat <61094841+schwar3kat@users.noreply.github.com>
> X-Git-Archeology: Subject: Refactored orangepi-r1plus-lts dts in kernel add board patch
> X-Git-Archeology:
> X-Git-Archeology: - Revision 8648dde23ff090b5fb704adab036ed14cd944ba3: https://github.com/armbian/build/commit/8648dde23ff090b5fb704adab036ed14cd944ba3
> X-Git-Archeology: Date: Thu, 22 Sep 2022 10:25:28 +0200
> X-Git-Archeology: From: aiamadeus <42570690+aiamadeus@users.noreply.github.com>
> X-Git-Archeology: Subject: rockchip: fixes support for orangepi-r1plus (#4215)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 85bab47bba73e0ef0e4ea5fde60e0aab56f82906: https://github.com/armbian/build/commit/85bab47bba73e0ef0e4ea5fde60e0aab56f82906
> X-Git-Archeology: Date: Sat, 06 May 2023 12:55:10 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
> X-Git-Archeology: - Revision 906ca66430329ab774f5b9d0f62eef1ce5e398fe: https://github.com/armbian/build/commit/906ca66430329ab774f5b9d0f62eef1ce5e398fe
> X-Git-Archeology: Date: Tue, 16 May 2023 08:55:33 +0200
> X-Git-Archeology: From: Ricardo Pardini <ricardo@pardini.net>
> X-Git-Archeology: Subject: `rockchip64`/`edge`/`6.3`: rebase/rewrite patches against `v6.3.1`; do archeology for mbox-less patches; materialize overwrites
> X-Git-Archeology:
> X-Git-Archeology: - Revision 19d532b13cabc1a749f61b9c400d933ba5aeb7e3: https://github.com/armbian/build/commit/19d532b13cabc1a749f61b9c400d933ba5aeb7e3
> X-Git-Archeology: Date: Tue, 13 Jun 2023 12:33:59 +0200
> X-Git-Archeology: From: Ricardo Pardini <ricardo@pardini.net>
> X-Git-Archeology: Subject: `rockchip64` `edge` 6.3: rename most remaining "add-board" patches to "board" (all "add-board"s are now bare .dts in `dt/` folder)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 41ade999f04c26a277cfa1c3c721cbe869d3ad12: https://github.com/armbian/build/commit/41ade999f04c26a277cfa1c3c721cbe869d3ad12
> X-Git-Archeology: Date: Tue, 03 Oct 2023 13:54:03 +0200
> X-Git-Archeology: From: Ricardo Pardini <ricardo@pardini.net>
> X-Git-Archeology: Subject: `rockchip64`/`edge`: bump to `6.6-rc4`; initial copy patches from 6.5
> X-Git-Archeology:
> X-Git-Archeology: - Revision 1f4df4c41fe33f9822ca2f42d14a2a445e27aed7: https://github.com/armbian/build/commit/1f4df4c41fe33f9822ca2f42d14a2a445e27aed7
> X-Git-Archeology: Date: Sun, 14 Jan 2024 14:14:50 +0100
> X-Git-Archeology: From: Paolo Sabatino <paolo.sabatino@gmail.com>
> X-Git-Archeology: Subject: rockchip64: bump edge to 6.7, current to 6.6
> X-Git-Archeology:
> X-Git-Archeology: - Revision e4d413b9166e3633b40fb23382fb1045b9d0e315: https://github.com/armbian/build/commit/e4d413b9166e3633b40fb23382fb1045b9d0e315
> X-Git-Archeology: Date: Tue, 26 Mar 2024 13:46:35 +0100
> X-Git-Archeology: From: Paolo Sabatino <paolo.sabatino@gmail.com>
> X-Git-Archeology: Subject: rockchip64: bump edge kernel to 6.8
> X-Git-Archeology:
> X-Git-Archeology: - Revision fae4549764c548cb65d3cbfe319f1e11bc777505: https://github.com/armbian/build/commit/fae4549764c548cb65d3cbfe319f1e11bc777505
> X-Git-Archeology: Date: Thu, 04 Apr 2024 13:38:18 +0800
> X-Git-Archeology: From: aiamadeus <2789289348@qq.com>
> X-Git-Archeology: Subject: rockchip: update dts patches for orangepi r1-plus
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi | 45 ++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
+#include "rk3328-dram-default-timing.dtsi"
#include "rk3328.dtsi"
/ {
@@ -83,6 +84,33 @@ vdd_5v_lan: regulator-vdd-5v-lan {
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
+
+ /delete-node/ dmc-opp-table;
+
+ dmc_opp_table: dmc_opp_table {
+ compatible = "operating-points-v2";
+
+ opp-786000000 {
+ opp-hz = /bits/ 64 <786000000>;
+ opp-microvolt = <1075000 1075000 1200000>;
+ };
+ opp-798000000 {
+ opp-hz = /bits/ 64 <798000000>;
+ opp-microvolt = <1075000 1075000 1200000>;
+ };
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-microvolt = <1075000 1075000 1200000>;
+ };
+ opp-924000000 {
+ opp-hz = /bits/ 64 <924000000>;
+ opp-microvolt = <1100000 1100000 1200000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1175000 1175000 1200000>;
+ };
+ };
};
&cpu0 {
@@ -105,6 +133,16 @@ &display_subsystem {
status = "disabled";
};
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ center-supply = <&vdd_log>;
+ ddr_timing = <&ddr_timing>;
+ status = "okay";
+};
+
&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
@@ -120,6 +158,10 @@ mdio {
};
};
+&i2c0 {
+ status = "okay";
+};
+
&i2c1 {
status = "okay";
@@ -149,6 +191,7 @@ vdd_log: DCDC_REG1 {
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
+ regulator-init-microvolt = <1075000>;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>;
@@ -163,6 +206,7 @@ vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-always-on;
regulator-boot-on;
+ regulator-init-microvolt = <1225000>;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>;
@@ -344,6 +388,7 @@ &usbdrd3 {
rtl8153: device@2 {
compatible = "usbbda,8153";
reg = <2>;
+ realtek,led-data = <0x87>;
};
};
--
Armbian

68
patch/kernel/rockchip64-6.14/board-orangepi-rk3399-pcie.patch
View File

@ -1,68 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: amazingfate <liujianfeng1994@gmail.com>
Date: Thu, 18 Apr 2024 00:42:13 +0800
Subject: arm64: dts: rockchip: add pcie support to orangepi rk3399 board
---
arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 31 ++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
@@ -123,6 +123,17 @@ vcc3v0_sd: regulator-vcc3v0-sd {
vin-supply = <&vcc3v3_sys>;
};
+ vcc3v3_pcie: regulator-vcc3v3-pcie {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 2 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_drv>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_pcie";
+ };
+
vcc3v3_sys: regulator-vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
@@ -587,6 +598,20 @@ &io_domains {
gpio1830-supply = <&vcc_3v0>;
};
+&pcie_phy {
+ status = "okay";
+ assigned-clocks = <&cru 138>;
+ assigned-clock-parents = <&cru 167>;
+ assigned-clock-rates = <100000000>;
+};
+
+&pcie0 {
+ status = "okay";
+ ep-gpios = <&gpio2 4 0>;
+ num-lanes = <4>;
+ max-link-speed = <1>;
+};
+
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&vcc_3v0>;
@@ -609,6 +634,12 @@ phy_rstb: phy-rstb {
};
};
+ pcie {
+ pcie_drv: pcie-drv {
+ rockchip,pins = <0 2 0 &pcfg_pull_none>;
+ };
+ };
+
pmic {
cpu_b_sleep: cpu-b-sleep {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
--
Armbian

40
patch/kernel/rockchip64-6.14/board-orangepi3b-add-uwe5622-wifi-bt-nodes.patch
View File

@ -1,40 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: amazingfate <liujianfeng1994@gmail.com>
Date: Fri, 25 Oct 2024 14:48:47 +0800
Subject: arch: arm64: dts: add uwe5622 wifi/bt nodes to orangepi3b v1.1
---
arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts | 17 ++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts
@@ -7,6 +7,23 @@
/ {
model = "Xunlong Orange Pi 3B v1.1";
compatible = "xunlong,orangepi-3b-v1.1", "xunlong,orangepi-3b", "rockchip,rk3566";
+
+ sprd-mtty {
+ compatible = "sprd,mtty";
+ sprd,name = "ttyBT";
+ };
+
+ uwe-bsp {
+ compatible = "unisoc,uwe_bsp";
+ wl-reg-on = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ bt-reg-on = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ wl-wake-host-gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+ bt-wake-host-gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ sdio-ext-int-gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ data-irq;
+ blksz-512;
+ keep-power-on;
+ };
};
&pmu_io_domains {
--
Armbian

35
patch/kernel/rockchip64-6.14/board-radxa-e25-sdmmc0-fix.patch
View File

@ -1,35 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: krachlatte <krachlatte1977@gmail.com>
Date: Wed, 17 May 2023 00:55:30 +0200
Subject: [ARCHEOLOGY] Improve SD card compatibility on Radxa E25 (#5165)
> X-Git-Archeology: - Revision 45c85878613108c238e491aa69650fcad1fba4bb: https://github.com/armbian/build/commit/45c85878613108c238e491aa69650fcad1fba4bb
> X-Git-Archeology: Date: Wed, 17 May 2023 00:55:30 +0200
> X-Git-Archeology: From: krachlatte <krachlatte1977@gmail.com>
> X-Git-Archeology: Subject: Improve SD card compatibility on Radxa E25 (#5165)
> X-Git-Archeology:
> X-Git-Archeology: - Revision f6a0c53d08f53aadd0588a571662dc199232825b: https://github.com/armbian/build/commit/f6a0c53d08f53aadd0588a571662dc199232825b
> X-Git-Archeology: Date: Wed, 24 May 2023 10:39:21 +0200
> X-Git-Archeology: From: Ricardo Pardini <ricardo@pardini.net>
> X-Git-Archeology: Subject: manual e25 patch fix
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
@@ -203,7 +203,7 @@ &sdmmc0 {
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
- sd-uhs-sdr104;
+ sd-uhs-sdr50;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
--
Armbian

64
patch/kernel/rockchip64-6.14/board-radxa-e25-usb3-and-emmc-fix.patch
View File

@ -1,64 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: krachlatte <krachlatte1977@gmail.com>
Date: Wed, 17 May 2023 00:55:30 +0200
Subject: [ARCHEOLOGY] Improve SD card compatibility on Radxa E25 (#5165)
> X-Git-Archeology: - Revision 45c85878613108c238e491aa69650fcad1fba4bb: https://github.com/armbian/build/commit/45c85878613108c238e491aa69650fcad1fba4bb
> X-Git-Archeology: Date: Wed, 17 May 2023 00:55:30 +0200
> X-Git-Archeology: From: krachlatte <krachlatte1977@gmail.com>
> X-Git-Archeology: Subject: Improve SD card compatibility on Radxa E25 (#5165)
> X-Git-Archeology:
> X-Git-Archeology: - Revision f6a0c53d08f53aadd0588a571662dc199232825b: https://github.com/armbian/build/commit/f6a0c53d08f53aadd0588a571662dc199232825b
> X-Git-Archeology: Date: Wed, 24 May 2023 10:39:21 +0200
> X-Git-Archeology: From: Ricardo Pardini <ricardo@pardini.net>
> X-Git-Archeology: Subject: manual e25 patch fix
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 12 ++++++++++
arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
@@ -385,6 +385,17 @@ &sdhci {
status = "okay";
};
+&sfc {
+ status = "okay";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+};
+
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
@@ -405,4 +416,5 @@ &usb2phy1 {
&usb_host0_xhci {
extcon = <&usb2phy0>;
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
@@ -218,6 +218,8 @@ &usb_host0_ohci {
};
&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ dr_mode = "host";
status = "okay";
};
--
Armbian

75
patch/kernel/rockchip64-6.14/board-rk3328-roc-cc-dts-enable-dmc.patch
View File

@ -1,75 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Tue, 12 Oct 2021 18:31:28 +0000
Subject: enable roc-cc dmc
---
arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi | 38 ++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
@@ -5,6 +5,7 @@
/dts-v1/;
+#include "rk3328-dram-renegade-timing.dtsi"
#include "rk3328.dtsi"
/ {
@@ -18,6 +19,32 @@ chosen {
stdout-path = "serial2:1500000n8";
};
+ /delete-node/ dmc-opp-table;
+ dmc_opp_table: dmc-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-786000000 {
+ opp-hz = /bits/ 64 <786000000>;
+ opp-microvolt = <1075000 1075000 12000000>;
+ };
+ opp-798000000 {
+ opp-hz = /bits/ 64 <798000000>;
+ opp-microvolt = <1075000 1075000 12000000>;
+ };
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-microvolt = <1075000 1075000 12000000>;
+ };
+ opp-924000000 {
+ opp-hz = /bits/ 64 <924000000>;
+ opp-microvolt = <1100000 1100000 12000000>;
+ };
+ opp-1068000000 {
+ opp-hz = /bits/ 64 <1068000000>;
+ opp-microvolt = <1175000 1175000 12000000>;
+ };
+ };
+
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -111,6 +138,17 @@ &codec {
status = "okay";
};
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ center-supply = <&vdd_logic>;
+ ddr_timing = <&ddr_timing>;
+ status = "okay";
+};
+
+
&cpu0 {
cpu-supply = <&vdd_arm>;
};
--
Armbian

330
patch/kernel/rockchip64-6.14/board-rk3328-roc-cc-dts-ram-profile.patch
View File

@ -1,330 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: tonymac32 <tonymckahan@gmail.com>
Date: Wed, 7 Oct 2020 23:39:54 -0400
Subject: board-rk3328-roc-cc-adjust-DMC-opps
Signed-off-by: tonymac32 <tonymckahan@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi | 311 ++++++++++
1 file changed, 311 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/memory/rk3328-dram.h>
+
+/ {
+ ddr_timing: ddr_timing {
+ compatible = "rockchip,ddr-timing";
+ ddr3_speed_bin = <DDR3_DEFAULT>;
+ ddr4_speed_bin = <DDR4_DEFAULT>;
+ pd_idle = <0>;
+ sr_idle = <0>;
+ sr_mc_gate_idle = <0>;
+ srpd_lite_idle = <0>;
+ standby_idle = <0>;
+
+ auto_pd_dis_freq = <1066>;
+ auto_sr_dis_freq = <800>;
+ ddr3_dll_dis_freq = <300>;
+ ddr4_dll_dis_freq = <625>;
+ phy_dll_dis_freq = <400>;
+
+ ddr3_odt_dis_freq = <100>;
+ phy_ddr3_odt_dis_freq = <100>;
+ ddr3_drv = <DDR3_DS_40ohm>;
+ ddr3_odt = <DDR3_ODT_120ohm>;
+ phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
+ phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
+ phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
+ phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
+
+ lpddr3_odt_dis_freq = <666>;
+ phy_lpddr3_odt_dis_freq = <666>;
+ lpddr3_drv = <LP3_DS_40ohm>;
+ lpddr3_odt = <LP3_ODT_240ohm>;
+ phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
+ phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
+
+ lpddr4_odt_dis_freq = <800>;
+ phy_lpddr4_odt_dis_freq = <800>;
+ lpddr4_drv = <LP4_PDDS_60ohm>;
+ lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
+ lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
+ phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
+ phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
+ phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
+ phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
+
+ ddr4_odt_dis_freq = <666>;
+ phy_ddr4_odt_dis_freq = <666>;
+ ddr4_drv = <DDR4_DS_34ohm>;
+ ddr4_odt = <DDR4_RTT_NOM_240ohm>;
+ phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
+ phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
+
+ /* CA de-skew, one step is 47.8ps, range 0-15 */
+ ddr3a1_ddr4a9_de-skew = <0>;
+ ddr3a0_ddr4a10_de-skew = <0>;
+ ddr3a3_ddr4a6_de-skew = <1>;
+ ddr3a2_ddr4a4_de-skew = <1>;
+ ddr3a5_ddr4a8_de-skew = <0>;
+ ddr3a4_ddr4a5_de-skew = <2>;
+ ddr3a7_ddr4a11_de-skew = <0>;
+ ddr3a6_ddr4a7_de-skew = <2>;
+ ddr3a9_ddr4a0_de-skew = <1>;
+ ddr3a8_ddr4a13_de-skew = <0>;
+ ddr3a11_ddr4a3_de-skew = <2>;
+ ddr3a10_ddr4cs0_de-skew = <0>;
+ ddr3a13_ddr4a2_de-skew = <1>;
+ ddr3a12_ddr4ba1_de-skew = <0>;
+ ddr3a15_ddr4odt0_de-skew = <0>;
+ ddr3a14_ddr4a1_de-skew = <1>;
+ ddr3ba1_ddr4a15_de-skew = <0>;
+ ddr3ba0_ddr4bg0_de-skew = <0>;
+ ddr3ras_ddr4cke_de-skew = <0>;
+ ddr3ba2_ddr4ba0_de-skew = <1>;
+ ddr3we_ddr4bg1_de-skew = <1>;
+ ddr3cas_ddr4a12_de-skew = <0>;
+ ddr3ckn_ddr4ckn_de-skew = <5>;
+ ddr3ckp_ddr4ckp_de-skew = <5>;
+ ddr3cke_ddr4a16_de-skew = <1>;
+ ddr3odt0_ddr4a14_de-skew = <0>;
+ ddr3cs0_ddr4act_de-skew = <1>;
+ ddr3reset_ddr4reset_de-skew = <0>;
+ ddr3cs1_ddr4cs1_de-skew = <0>;
+ ddr3odt1_ddr4odt1_de-skew = <0>;
+
+ /* DATA de-skew
+ * RX one step is 25.1ps, range 0-15
+ * TX one step is 47.8ps, range 0-15
+ */
+ cs0_dm0_rx_de-skew = <7>;
+ cs0_dm0_tx_de-skew = <8>;
+ cs0_dq0_rx_de-skew = <7>;
+ cs0_dq0_tx_de-skew = <8>;
+ cs0_dq1_rx_de-skew = <7>;
+ cs0_dq1_tx_de-skew = <8>;
+ cs0_dq2_rx_de-skew = <7>;
+ cs0_dq2_tx_de-skew = <8>;
+ cs0_dq3_rx_de-skew = <7>;
+ cs0_dq3_tx_de-skew = <8>;
+ cs0_dq4_rx_de-skew = <7>;
+ cs0_dq4_tx_de-skew = <8>;
+ cs0_dq5_rx_de-skew = <7>;
+ cs0_dq5_tx_de-skew = <8>;
+ cs0_dq6_rx_de-skew = <7>;
+ cs0_dq6_tx_de-skew = <8>;
+ cs0_dq7_rx_de-skew = <7>;
+ cs0_dq7_tx_de-skew = <8>;
+ cs0_dqs0_rx_de-skew = <6>;
+ cs0_dqs0p_tx_de-skew = <9>;
+ cs0_dqs0n_tx_de-skew = <9>;
+
+ cs0_dm1_rx_de-skew = <7>;
+ cs0_dm1_tx_de-skew = <7>;
+ cs0_dq8_rx_de-skew = <7>;
+ cs0_dq8_tx_de-skew = <8>;
+ cs0_dq9_rx_de-skew = <7>;
+ cs0_dq9_tx_de-skew = <7>;
+ cs0_dq10_rx_de-skew = <7>;
+ cs0_dq10_tx_de-skew = <8>;
+ cs0_dq11_rx_de-skew = <7>;
+ cs0_dq11_tx_de-skew = <7>;
+ cs0_dq12_rx_de-skew = <7>;
+ cs0_dq12_tx_de-skew = <8>;
+ cs0_dq13_rx_de-skew = <7>;
+ cs0_dq13_tx_de-skew = <7>;
+ cs0_dq14_rx_de-skew = <7>;
+ cs0_dq14_tx_de-skew = <8>;
+ cs0_dq15_rx_de-skew = <7>;
+ cs0_dq15_tx_de-skew = <7>;
+ cs0_dqs1_rx_de-skew = <7>;
+ cs0_dqs1p_tx_de-skew = <9>;
+ cs0_dqs1n_tx_de-skew = <9>;
+
+ cs0_dm2_rx_de-skew = <7>;
+ cs0_dm2_tx_de-skew = <8>;
+ cs0_dq16_rx_de-skew = <7>;
+ cs0_dq16_tx_de-skew = <8>;
+ cs0_dq17_rx_de-skew = <7>;
+ cs0_dq17_tx_de-skew = <8>;
+ cs0_dq18_rx_de-skew = <7>;
+ cs0_dq18_tx_de-skew = <8>;
+ cs0_dq19_rx_de-skew = <7>;
+ cs0_dq19_tx_de-skew = <8>;
+ cs0_dq20_rx_de-skew = <7>;
+ cs0_dq20_tx_de-skew = <8>;
+ cs0_dq21_rx_de-skew = <7>;
+ cs0_dq21_tx_de-skew = <8>;
+ cs0_dq22_rx_de-skew = <7>;
+ cs0_dq22_tx_de-skew = <8>;
+ cs0_dq23_rx_de-skew = <7>;
+ cs0_dq23_tx_de-skew = <8>;
+ cs0_dqs2_rx_de-skew = <6>;
+ cs0_dqs2p_tx_de-skew = <9>;
+ cs0_dqs2n_tx_de-skew = <9>;
+
+ cs0_dm3_rx_de-skew = <7>;
+ cs0_dm3_tx_de-skew = <7>;
+ cs0_dq24_rx_de-skew = <7>;
+ cs0_dq24_tx_de-skew = <8>;
+ cs0_dq25_rx_de-skew = <7>;
+ cs0_dq25_tx_de-skew = <7>;
+ cs0_dq26_rx_de-skew = <7>;
+ cs0_dq26_tx_de-skew = <7>;
+ cs0_dq27_rx_de-skew = <7>;
+ cs0_dq27_tx_de-skew = <7>;
+ cs0_dq28_rx_de-skew = <7>;
+ cs0_dq28_tx_de-skew = <7>;
+ cs0_dq29_rx_de-skew = <7>;
+ cs0_dq29_tx_de-skew = <7>;
+ cs0_dq30_rx_de-skew = <7>;
+ cs0_dq30_tx_de-skew = <7>;
+ cs0_dq31_rx_de-skew = <7>;
+ cs0_dq31_tx_de-skew = <7>;
+ cs0_dqs3_rx_de-skew = <7>;
+ cs0_dqs3p_tx_de-skew = <9>;
+ cs0_dqs3n_tx_de-skew = <9>;
+
+ cs1_dm0_rx_de-skew = <7>;
+ cs1_dm0_tx_de-skew = <8>;
+ cs1_dq0_rx_de-skew = <7>;
+ cs1_dq0_tx_de-skew = <8>;
+ cs1_dq1_rx_de-skew = <7>;
+ cs1_dq1_tx_de-skew = <8>;
+ cs1_dq2_rx_de-skew = <7>;
+ cs1_dq2_tx_de-skew = <8>;
+ cs1_dq3_rx_de-skew = <7>;
+ cs1_dq3_tx_de-skew = <8>;
+ cs1_dq4_rx_de-skew = <7>;
+ cs1_dq4_tx_de-skew = <8>;
+ cs1_dq5_rx_de-skew = <7>;
+ cs1_dq5_tx_de-skew = <8>;
+ cs1_dq6_rx_de-skew = <7>;
+ cs1_dq6_tx_de-skew = <8>;
+ cs1_dq7_rx_de-skew = <7>;
+ cs1_dq7_tx_de-skew = <8>;
+ cs1_dqs0_rx_de-skew = <6>;
+ cs1_dqs0p_tx_de-skew = <9>;
+ cs1_dqs0n_tx_de-skew = <9>;
+
+ cs1_dm1_rx_de-skew = <7>;
+ cs1_dm1_tx_de-skew = <7>;
+ cs1_dq8_rx_de-skew = <7>;
+ cs1_dq8_tx_de-skew = <8>;
+ cs1_dq9_rx_de-skew = <7>;
+ cs1_dq9_tx_de-skew = <7>;
+ cs1_dq10_rx_de-skew = <7>;
+ cs1_dq10_tx_de-skew = <8>;
+ cs1_dq11_rx_de-skew = <7>;
+ cs1_dq11_tx_de-skew = <7>;
+ cs1_dq12_rx_de-skew = <7>;
+ cs1_dq12_tx_de-skew = <8>;
+ cs1_dq13_rx_de-skew = <7>;
+ cs1_dq13_tx_de-skew = <7>;
+ cs1_dq14_rx_de-skew = <7>;
+ cs1_dq14_tx_de-skew = <8>;
+ cs1_dq15_rx_de-skew = <7>;
+ cs1_dq15_tx_de-skew = <7>;
+ cs1_dqs1_rx_de-skew = <7>;
+ cs1_dqs1p_tx_de-skew = <9>;
+ cs1_dqs1n_tx_de-skew = <9>;
+
+ cs1_dm2_rx_de-skew = <7>;
+ cs1_dm2_tx_de-skew = <8>;
+ cs1_dq16_rx_de-skew = <7>;
+ cs1_dq16_tx_de-skew = <8>;
+ cs1_dq17_rx_de-skew = <7>;
+ cs1_dq17_tx_de-skew = <8>;
+ cs1_dq18_rx_de-skew = <7>;
+ cs1_dq18_tx_de-skew = <8>;
+ cs1_dq19_rx_de-skew = <7>;
+ cs1_dq19_tx_de-skew = <8>;
+ cs1_dq20_rx_de-skew = <7>;
+ cs1_dq20_tx_de-skew = <8>;
+ cs1_dq21_rx_de-skew = <7>;
+ cs1_dq21_tx_de-skew = <8>;
+ cs1_dq22_rx_de-skew = <7>;
+ cs1_dq22_tx_de-skew = <8>;
+ cs1_dq23_rx_de-skew = <7>;
+ cs1_dq23_tx_de-skew = <8>;
+ cs1_dqs2_rx_de-skew = <6>;
+ cs1_dqs2p_tx_de-skew = <9>;
+ cs1_dqs2n_tx_de-skew = <9>;
+
+ cs1_dm3_rx_de-skew = <7>;
+ cs1_dm3_tx_de-skew = <7>;
+ cs1_dq24_rx_de-skew = <7>;
+ cs1_dq24_tx_de-skew = <8>;
+ cs1_dq25_rx_de-skew = <7>;
+ cs1_dq25_tx_de-skew = <7>;
+ cs1_dq26_rx_de-skew = <7>;
+ cs1_dq26_tx_de-skew = <7>;
+ cs1_dq27_rx_de-skew = <7>;
+ cs1_dq27_tx_de-skew = <7>;
+ cs1_dq28_rx_de-skew = <7>;
+ cs1_dq28_tx_de-skew = <7>;
+ cs1_dq29_rx_de-skew = <7>;
+ cs1_dq29_tx_de-skew = <7>;
+ cs1_dq30_rx_de-skew = <7>;
+ cs1_dq30_tx_de-skew = <7>;
+ cs1_dq31_rx_de-skew = <7>;
+ cs1_dq31_tx_de-skew = <7>;
+ cs1_dqs3_rx_de-skew = <7>;
+ cs1_dqs3p_tx_de-skew = <9>;
+ cs1_dqs3n_tx_de-skew = <9>;
+ };
+};
--
Armbian

301
patch/kernel/rockchip64-6.14/board-rk3328-roc-pc-dts-ram-profile.patch
View File

@ -1,301 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Tony <tonymckahan@gmail.com>
Date: Thu, 8 Oct 2020 01:56:28 -0400
Subject: [ARCHEOLOGY] Add files via upload
> X-Git-Archeology: - Revision 8fc20a15b12561e76e92d5bd29b5afd1c62f08ac: https://github.com/armbian/build/commit/8fc20a15b12561e76e92d5bd29b5afd1c62f08ac
> X-Git-Archeology: Date: Thu, 08 Oct 2020 01:56:28 -0400
> X-Git-Archeology: From: Tony <tonymckahan@gmail.com>
> X-Git-Archeology: Subject: Add files via upload
> X-Git-Archeology:
> X-Git-Archeology: - Revision 2788adccedc25f12fc9e71e01a92863d97683979: https://github.com/armbian/build/commit/2788adccedc25f12fc9e71e01a92863d97683979
> X-Git-Archeology: Date: Tue, 26 Jan 2021 21:22:04 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Enable DMC for Station M1 in current and dev (#2575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125)
> X-Git-Archeology:
> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi | 223 ++++++++++
1 file changed, 223 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/memory/rk3328-dram.h>
+
+/ {
+ ddr_timing: ddr_timing {
+ /* CA de-skew, one step is 47.8ps, range 0-15 */
+ ddr3a1_ddr4a9_de-skew = <0>;
+ ddr3a0_ddr4a10_de-skew = <0>;
+ ddr3a3_ddr4a6_de-skew = <1>;
+ ddr3a2_ddr4a4_de-skew = <1>;
+ ddr3a5_ddr4a8_de-skew = <0>;
+ ddr3a4_ddr4a5_de-skew = <2>;
+ ddr3a7_ddr4a11_de-skew = <0>;
+ ddr3a6_ddr4a7_de-skew = <2>;
+ ddr3a9_ddr4a0_de-skew = <1>;
+ ddr3a8_ddr4a13_de-skew = <0>;
+ ddr3a11_ddr4a3_de-skew = <2>;
+ ddr3a10_ddr4cs0_de-skew = <0>;
+ ddr3a13_ddr4a2_de-skew = <1>;
+ ddr3a12_ddr4ba1_de-skew = <0>;
+ ddr3a15_ddr4odt0_de-skew = <0>;
+ ddr3a14_ddr4a1_de-skew = <1>;
+ ddr3ba1_ddr4a15_de-skew = <0>;
+ ddr3ba0_ddr4bg0_de-skew = <0>;
+ ddr3ras_ddr4cke_de-skew = <0>;
+ ddr3ba2_ddr4ba0_de-skew = <1>;
+ ddr3we_ddr4bg1_de-skew = <1>;
+ ddr3cas_ddr4a12_de-skew = <0>;
+ ddr3ckn_ddr4ckn_de-skew = <5>;
+ ddr3ckp_ddr4ckp_de-skew = <5>;
+ ddr3cke_ddr4a16_de-skew = <1>;
+ ddr3odt0_ddr4a14_de-skew = <0>;
+ ddr3cs0_ddr4act_de-skew = <1>;
+ ddr3reset_ddr4reset_de-skew = <0>;
+ ddr3cs1_ddr4cs1_de-skew = <0>;
+ ddr3odt1_ddr4odt1_de-skew = <0>;
+
+ /* DATA de-skew
+ * RX one step is 25.1ps, range 0-15
+ * TX one step is 47.8ps, range 0-15
+ */
+ cs0_dm0_rx_de-skew = <7>;
+ cs0_dm0_tx_de-skew = <8>;
+ cs0_dq0_rx_de-skew = <7>;
+ cs0_dq0_tx_de-skew = <8>;
+ cs0_dq1_rx_de-skew = <7>;
+ cs0_dq1_tx_de-skew = <8>;
+ cs0_dq2_rx_de-skew = <7>;
+ cs0_dq2_tx_de-skew = <8>;
+ cs0_dq3_rx_de-skew = <7>;
+ cs0_dq3_tx_de-skew = <8>;
+ cs0_dq4_rx_de-skew = <7>;
+ cs0_dq4_tx_de-skew = <8>;
+ cs0_dq5_rx_de-skew = <7>;
+ cs0_dq5_tx_de-skew = <8>;
+ cs0_dq6_rx_de-skew = <7>;
+ cs0_dq6_tx_de-skew = <8>;
+ cs0_dq7_rx_de-skew = <7>;
+ cs0_dq7_tx_de-skew = <8>;
+ cs0_dqs0_rx_de-skew = <6>;
+ cs0_dqs0p_tx_de-skew = <9>;
+ cs0_dqs0n_tx_de-skew = <9>;
+
+ cs0_dm1_rx_de-skew = <7>;
+ cs0_dm1_tx_de-skew = <7>;
+ cs0_dq8_rx_de-skew = <7>;
+ cs0_dq8_tx_de-skew = <8>;
+ cs0_dq9_rx_de-skew = <7>;
+ cs0_dq9_tx_de-skew = <7>;
+ cs0_dq10_rx_de-skew = <7>;
+ cs0_dq10_tx_de-skew = <8>;
+ cs0_dq11_rx_de-skew = <7>;
+ cs0_dq11_tx_de-skew = <7>;
+ cs0_dq12_rx_de-skew = <7>;
+ cs0_dq12_tx_de-skew = <8>;
+ cs0_dq13_rx_de-skew = <7>;
+ cs0_dq13_tx_de-skew = <7>;
+ cs0_dq14_rx_de-skew = <7>;
+ cs0_dq14_tx_de-skew = <8>;
+ cs0_dq15_rx_de-skew = <7>;
+ cs0_dq15_tx_de-skew = <7>;
+ cs0_dqs1_rx_de-skew = <7>;
+ cs0_dqs1p_tx_de-skew = <9>;
+ cs0_dqs1n_tx_de-skew = <9>;
+
+ cs0_dm2_rx_de-skew = <7>;
+ cs0_dm2_tx_de-skew = <8>;
+ cs0_dq16_rx_de-skew = <7>;
+ cs0_dq16_tx_de-skew = <8>;
+ cs0_dq17_rx_de-skew = <7>;
+ cs0_dq17_tx_de-skew = <8>;
+ cs0_dq18_rx_de-skew = <7>;
+ cs0_dq18_tx_de-skew = <8>;
+ cs0_dq19_rx_de-skew = <7>;
+ cs0_dq19_tx_de-skew = <8>;
+ cs0_dq20_rx_de-skew = <7>;
+ cs0_dq20_tx_de-skew = <8>;
+ cs0_dq21_rx_de-skew = <7>;
+ cs0_dq21_tx_de-skew = <8>;
+ cs0_dq22_rx_de-skew = <7>;
+ cs0_dq22_tx_de-skew = <8>;
+ cs0_dq23_rx_de-skew = <7>;
+ cs0_dq23_tx_de-skew = <8>;
+ cs0_dqs2_rx_de-skew = <6>;
+ cs0_dqs2p_tx_de-skew = <9>;
+ cs0_dqs2n_tx_de-skew = <9>;
+
+ cs0_dm3_rx_de-skew = <7>;
+ cs0_dm3_tx_de-skew = <7>;
+ cs0_dq24_rx_de-skew = <7>;
+ cs0_dq24_tx_de-skew = <8>;
+ cs0_dq25_rx_de-skew = <7>;
+ cs0_dq25_tx_de-skew = <7>;
+ cs0_dq26_rx_de-skew = <7>;
+ cs0_dq26_tx_de-skew = <7>;
+ cs0_dq27_rx_de-skew = <7>;
+ cs0_dq27_tx_de-skew = <7>;
+ cs0_dq28_rx_de-skew = <7>;
+ cs0_dq28_tx_de-skew = <7>;
+ cs0_dq29_rx_de-skew = <7>;
+ cs0_dq29_tx_de-skew = <7>;
+ cs0_dq30_rx_de-skew = <7>;
+ cs0_dq30_tx_de-skew = <7>;
+ cs0_dq31_rx_de-skew = <7>;
+ cs0_dq31_tx_de-skew = <7>;
+ cs0_dqs3_rx_de-skew = <7>;
+ cs0_dqs3p_tx_de-skew = <9>;
+ cs0_dqs3n_tx_de-skew = <9>;
+
+ cs1_dm0_rx_de-skew = <7>;
+ cs1_dm0_tx_de-skew = <8>;
+ cs1_dq0_rx_de-skew = <7>;
+ cs1_dq0_tx_de-skew = <8>;
+ cs1_dq1_rx_de-skew = <7>;
+ cs1_dq1_tx_de-skew = <8>;
+ cs1_dq2_rx_de-skew = <7>;
+ cs1_dq2_tx_de-skew = <8>;
+ cs1_dq3_rx_de-skew = <7>;
+ cs1_dq3_tx_de-skew = <8>;
+ cs1_dq4_rx_de-skew = <7>;
+ cs1_dq4_tx_de-skew = <8>;
+ cs1_dq5_rx_de-skew = <7>;
+ cs1_dq5_tx_de-skew = <8>;
+ cs1_dq6_rx_de-skew = <7>;
+ cs1_dq6_tx_de-skew = <8>;
+ cs1_dq7_rx_de-skew = <7>;
+ cs1_dq7_tx_de-skew = <8>;
+ cs1_dqs0_rx_de-skew = <6>;
+ cs1_dqs0p_tx_de-skew = <9>;
+ cs1_dqs0n_tx_de-skew = <9>;
+
+ cs1_dm1_rx_de-skew = <7>;
+ cs1_dm1_tx_de-skew = <7>;
+ cs1_dq8_rx_de-skew = <7>;
+ cs1_dq8_tx_de-skew = <8>;
+ cs1_dq9_rx_de-skew = <7>;
+ cs1_dq9_tx_de-skew = <7>;
+ cs1_dq10_rx_de-skew = <7>;
+ cs1_dq10_tx_de-skew = <8>;
+ cs1_dq11_rx_de-skew = <7>;
+ cs1_dq11_tx_de-skew = <7>;
+ cs1_dq12_rx_de-skew = <7>;
+ cs1_dq12_tx_de-skew = <8>;
+ cs1_dq13_rx_de-skew = <7>;
+ cs1_dq13_tx_de-skew = <7>;
+ cs1_dq14_rx_de-skew = <7>;
+ cs1_dq14_tx_de-skew = <8>;
+ cs1_dq15_rx_de-skew = <7>;
+ cs1_dq15_tx_de-skew = <7>;
+ cs1_dqs1_rx_de-skew = <7>;
+ cs1_dqs1p_tx_de-skew = <9>;
+ cs1_dqs1n_tx_de-skew = <9>;
+
+ cs1_dm2_rx_de-skew = <7>;
+ cs1_dm2_tx_de-skew = <8>;
+ cs1_dq16_rx_de-skew = <7>;
+ cs1_dq16_tx_de-skew = <8>;
+ cs1_dq17_rx_de-skew = <7>;
+ cs1_dq17_tx_de-skew = <8>;
+ cs1_dq18_rx_de-skew = <7>;
+ cs1_dq18_tx_de-skew = <8>;
+ cs1_dq19_rx_de-skew = <7>;
+ cs1_dq19_tx_de-skew = <8>;
+ cs1_dq20_rx_de-skew = <7>;
+ cs1_dq20_tx_de-skew = <8>;
+ cs1_dq21_rx_de-skew = <7>;
+ cs1_dq21_tx_de-skew = <8>;
+ cs1_dq22_rx_de-skew = <7>;
+ cs1_dq22_tx_de-skew = <8>;
+ cs1_dq23_rx_de-skew = <7>;
+ cs1_dq23_tx_de-skew = <8>;
+ cs1_dqs2_rx_de-skew = <6>;
+ cs1_dqs2p_tx_de-skew = <9>;
+ cs1_dqs2n_tx_de-skew = <9>;
+
+ cs1_dm3_rx_de-skew = <7>;
+ cs1_dm3_tx_de-skew = <7>;
+ cs1_dq24_rx_de-skew = <7>;
+ cs1_dq24_tx_de-skew = <8>;
+ cs1_dq25_rx_de-skew = <7>;
+ cs1_dq25_tx_de-skew = <7>;
+ cs1_dq26_rx_de-skew = <7>;
+ cs1_dq26_tx_de-skew = <7>;
+ cs1_dq27_rx_de-skew = <7>;
+ cs1_dq27_tx_de-skew = <7>;
+ cs1_dq28_rx_de-skew = <7>;
+ cs1_dq28_tx_de-skew = <7>;
+ cs1_dq29_rx_de-skew = <7>;
+ cs1_dq29_tx_de-skew = <7>;
+ cs1_dq30_rx_de-skew = <7>;
+ cs1_dq30_tx_de-skew = <7>;
+ cs1_dq31_rx_de-skew = <7>;
+ cs1_dq31_tx_de-skew = <7>;
+ cs1_dqs3_rx_de-skew = <7>;
+ cs1_dqs3p_tx_de-skew = <9>;
+ cs1_dqs3n_tx_de-skew = <9>;
+ };
+};
--
Armbian

592
patch/kernel/rockchip64-6.14/board-rk3328-roc-pc.patch
View File

@ -1,592 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Tue, 12 Oct 2021 19:34:29 +0000
Subject: enable dmc for rk3328-roc-pc
---
arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 524 +++++++++-
1 file changed, 466 insertions(+), 58 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
@@ -1,109 +1,517 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd
+/*
+ * SPDX-License-Identifier: (GPL-2.0+ or MIT)
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ */
/dts-v1/;
-
+#include "rk3328-roc-pc-dram-timing.dtsi"
+#include "rk3328.dtsi"
#include <dt-bindings/input/input.h>
-#include "rk3328-roc.dtsi"
/ {
- model = "Firefly ROC-RK3328-PC";
+ model = "Firefly roc-rk3328-pc";
compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328";
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1750000>;
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &emmc; /* MMC boot device */
+ };
- /* This button is unpopulated out of the factory. */
- button-recovery {
- label = "Recovery";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <10000>;
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "rockchip,rk3328";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+ };
+
+ hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "rockchip,hdmi";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
};
};
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
- linux,rc-map-name = "rc-khadas";
+ vcc_host_5v: vcc-host-5v-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&ir_int>;
+ pinctrl-0 = <&usb30_host_drv>;
+ regulator-name = "vcc_host_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
};
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&wifi_en>, <&wifi_host_wake>;
- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&usb20_host_drv>;
+ regulator-name = "vcc_host1_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_pin>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power_led: led-0 {
+ label = "firefly:blue:power";
+ linux,default-trigger = "heartbeat";
+ gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ mode = <0x23>;
+ };
+
+ user_led: led-1 {
+ label = "firefly:yellow:user";
+ linux,default-trigger = "mmc1";
+ gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ mode = <0x05>;
+ };
+ };
+
+ /delete-node/ dmc-opp-table;
+ dmc_opp_table: dmc-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-786000000 {
+ opp-hz = /bits/ 64 <786000000>;
+ opp-microvolt = <1075000 1075000 1200000>;
+ };
+ opp-798000000 {
+ opp-hz = /bits/ 64 <798000000>;
+ opp-microvolt = <1075000 1075000 1200000>;
+ };
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-microvolt = <1075000 1075000 1200000>;
+ };
+ opp-924000000 {
+ status = "disabled"; // unstable
+ opp-hz = /bits/ 64 <924000000>;
+ opp-microvolt = <1100000 1100000 1200000>;
+ };
};
};
-&codec {
- mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ center-supply = <&vdd_logic>;
+ ddr_timing = <&ddr_timing>;
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc_18emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_io>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
};
&gpu {
+ status = "okay";
mali-supply = <&vdd_logic>;
};
-&pinctrl {
- ir {
- ir_int: ir-int {
- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ status = "disabled";
+};
+
+&gmac2io {
+ phy-supply = <&vcc_io>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ snps,aal;
+ snps,rxpbl = <0x4>;
+ snps,txpbl = <0x4>;
+ tx_delay = <0x24>;
+ rx_delay = <0x18>;
+ status = "okay";
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&hdmi {
+ #sound-dai-cells = <0>;
+ ddc-i2c-scl-high-time-ns = <9625>;
+ ddc-i2c-scl-low-time-ns = <10000>;
+ status = "okay";
+};
+
+&hdmiphy {
+ status = "okay";
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+/*&h265e {
+ status = "okay";
+};
+
+&vdec {
+ status = "okay";
+};
+
+&vepu {
+ status = "okay";
+};*/
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+/*&vpu_service {
+ status = "okay";
+};*/
+
+&i2s0 {
+ #sound-dai-cells = <0>;
+ rockchip,bclk-fs = <128>;
+ status = "okay";
+};
+
+&i2s1 {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&codec {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ supports-emmc;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ supports-sd;
+ status = "okay";
+ vmmc-supply = <&vcc_sd>;
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ status = "okay";
+ reg = <0x18>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
+
+ rtc {
+ status = "okay";
};
- };
- sdmmcio {
- sdio_per_pin: sdio-per-pin {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
+ pwrkey {
+ status = "okay";
+ };
+
+ gpio {
+ status = "okay";
+ };
+
+ regulators {
+ compatible = "rk805-regulator";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_18: LDO_REG1 {
+ regulator-name = "vdd_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_18emmc: LDO_REG2 {
+ regulator-name = "vcc_18emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_11: LDO_REG3 {
+ regulator-name = "vdd_11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
};
};
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_32k_out>;
+
+ clk_32k {
+ clk_32k_out: clk-32k-out {
+ rockchip,pins =
+ <1 RK_PD4 1 &pcfg_pull_none>;
+ };
+ };
- wifi {
- wifi_en: wifi-en {
- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins =
+ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */
};
+ };
- wifi_host_wake: wifi-host-wake {
- rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>;
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
+ <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>,
+ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ };
- bt_rst: bt-rst {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ usb2 {
+ usb20_host_drv: usb20-host-drv {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ };
- bt_en: bt-en {
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ usb3 {
+ usb30_host_drv: usb30-host-drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
-&pmic_int_l {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+&u2phy {
+ status = "okay";
};
-&rk805 {
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+&u2phy_host {
+ status = "okay";
};
-&saradc {
- vref-supply = <&vcc_18>;
+&u2phy_otg {
status = "okay";
};
-&usb20_host_drv {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+&uart2 {
+ status = "okay";
};
-&vcc_host1_5v {
- gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+&usb20_otg {
+ dr_mode = "host";
+ status = "okay";
};
-&vcc_sdio {
- gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio_per_pin>;
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vdd_18>;
+};
+
+&tsadc {
+ status = "okay";
+ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
};
--
Armbian

54
patch/kernel/rockchip64-6.14/board-rock3a-0001-emmc-sfc.patch
View File

@ -1,54 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jianfeng Liu <liujianfeng1994@gmail.com>
Date: Wed, 3 Aug 2022 22:22:55 +0200
Subject: [ARCHEOLOGY] update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 11 ++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -767,6 +767,17 @@ flash@0 {
};
};
+&sfc {
+ status = "okay";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+};
+
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
--
Armbian

44
patch/kernel/rockchip64-6.14/board-rock3a-0002-usb3.patch
View File

@ -1,44 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jianfeng Liu <liujianfeng1994@gmail.com>
Date: Wed, 3 Aug 2022 22:22:55 +0200
Subject: [ARCHEOLOGY] update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -819,6 +819,7 @@ &usb_host0_ohci {
&usb_host0_xhci {
extcon = <&usb2phy0>;
+ dr_mode = "host";
status = "okay";
};
--
Armbian

84
patch/kernel/rockchip64-6.14/board-rock3a-0003-add-gpio-names.patch
View File

@ -1,84 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Werner <werner@armbian.com>
Date: Wed, 23 Oct 2024 12:27:21 +0200
Subject: add gpio names for rock-3a
Signed-off-by: Werner <werner@armbian.com>
---
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 60 ++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -277,6 +277,66 @@ &gpu {
status = "okay";
};
+&gpio0 {
+ gpio-line-names =
+ /* GPIO0_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_B0 - B7 */
+ "", "", "", "pin-28 [GPIO0_B3]", "pin-27 [GPIO0_B4]", "pin-7 [GPIO0_B5]", "pin-16 [GPIO0_B6]", "",
+ /* GPIO0_C0 - C7 */
+ "", "pin-22 [GPIO0_C1]", "", "", "", "", "", "",
+ /* GPIO0_D0 - D7 */
+ "pin-10 [GPIO0_D0]", "pin-8 [GPIO0_D1]", "", "", "", "", "", "";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /* GPIO1_A0 - A7 */
+ "pin-3 [GPIO1_A0]", "pin-5 [GPIO1_A1]", "", "", "", "", "", "",
+ /* GPIO1_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_C0 - C7 */
+ "pin-15 [GPIO0_C0]", "", "", "", "", "", "", "",
+ /* GPIO1_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ /* GPIO2_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO2_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO2_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO2_D0 - D7 */
+ "", "", "", "", "", "", "", "pin-29 [GPIO2_D7]";
+};
+
+&gpio3 {
+ gpio-line-names =
+ /* GPIO3_A0 - A7 */
+ "pin-31 [GPIO3_A0]", "", "pin-36 [GPIO3_A2]", "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]", "pin-38 [GPIO3_A6]", "",
+ /* GPIO3_B0 - B7 */
+ "", "", "pin-18 [GPIO3_B2]", "", "", "", "", "",
+ /* GPIO3_C0 - C7 */
+ "", "", "pin-32 [GPIO3_C2]", "pin-33 [GPIO3_C3]", "pin-11 [GPIO3_C4]", "pin-13 [GPIO3_C5]", "", "",
+ /* GPIO3_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ /* GPIO4_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO4_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO4_C0 - C7 */
+ "", "", "pin-21 [GPIO4_C2]", "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]", "pin-24 [GPIO4_C6]", "",
+ /* GPIO4_D0 - D7 */
+ "", "pin-26 [GPIO4_D1]", "", "", "", "", "", "";
+};
+
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
--
Armbian

29
patch/kernel/rockchip64-6.14/board-rock64-mail-supply.patch
View File

@ -1,29 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: tonymac32 <tonymckahan@gmail.com>
Date: Sun, 8 Aug 2021 11:49:27 -0400
Subject: board_rock64_mali-usb-supply
Signed-off-by: tonymac32 <tonymckahan@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -136,6 +136,11 @@ &emmc {
status = "okay";
};
+&gpu {
+ status = "okay";
+ mali-supply = <&vdd_logic>;
+};
+
&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
--
Armbian

44
patch/kernel/rockchip64-6.14/board-rockpi3-enable-dmc.patch
View File

@ -1,44 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Wed, 8 Mar 2023 11:12:22 +0100
Subject: [ARCHEOLOGY] rockchip64: enable dmc on Rock PI E board
> X-Git-Archeology: - Revision 4ea9330e5185e1c6e248af035cc615d23408316d: https://github.com/armbian/build/commit/4ea9330e5185e1c6e248af035cc615d23408316d
> X-Git-Archeology: Date: Wed, 08 Mar 2023 11:12:22 +0100
> X-Git-Archeology: From: Paolo Sabatino <paolo.sabatino@gmail.com>
> X-Git-Archeology: Subject: rockchip64: enable dmc on Rock PI E board
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
@@ -15,6 +15,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3328.dtsi"
+#include "rk3328-dram-default-timing.dtsi"
/ {
model = "Radxa ROCK Pi E";
@@ -440,3 +441,9 @@ &usbdrd3 {
&usb_host0_ehci {
status = "okay";
};
+
+&dmc {
+ status = "okay";
+ center-supply = <&vdd_log>;
+ ddr_timing = <&ddr_timing>;
+};
--
Armbian

130
patch/kernel/rockchip64-6.14/board-rockpi4-0003-arm64-dts-pcie.patch
View File

@ -1,130 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Piotr Szczepanik <piter75@gmail.com>
Date: Mon, 18 Nov 2019 18:23:10 +0100
Subject: [ARCHEOLOGY] Rock Pi 4 enable PCIe in device tree for "dev" target
(#1624)
> X-Git-Archeology: > recovered message: > * Rock Pi 4 enabled support for PCIe in device tree
> X-Git-Archeology: > recovered message: > * Rockchip64-dev added possibility to enable PCIe Gen2 speed via overlay
> X-Git-Archeology: - Revision b3bb9345439250d8247f0e24a8e1ef6290b2c279: https://github.com/armbian/build/commit/b3bb9345439250d8247f0e24a8e1ef6290b2c279
> X-Git-Archeology: Date: Mon, 18 Nov 2019 18:23:10 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Rock Pi 4 enable PCIe in device tree for "dev" target (#1624)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3
> X-Git-Archeology: Date: Tue, 19 Nov 2019 23:25:39 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Remove K<4, change branches, new features (#1586)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 812245def37a695bce9e7ece148b2920d82c8b37: https://github.com/armbian/build/commit/812245def37a695bce9e7ece148b2920d82c8b37
> X-Git-Archeology: Date: Sat, 18 Jul 2020 23:07:01 +0200
> X-Git-Archeology: From: Werner <EvilOlaf@users.noreply.github.com>
> X-Git-Archeology: Subject: Move rockchip/64 current to 5.7.y (#2099)
> X-Git-Archeology:
> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070
> X-Git-Archeology: Date: Sun, 13 Dec 2020 22:13:03 -0500
> X-Git-Archeology: From: tonymac32 <tonymckahan@gmail.com>
> X-Git-Archeology: Subject: [ rockchip64 ] Clean up patchset
> X-Git-Archeology:
> X-Git-Archeology: - Revision 091d91468e383c3d12a03a465be36b76112ce798: https://github.com/armbian/build/commit/091d91468e383c3d12a03a465be36b76112ce798
> X-Git-Archeology: Date: Sun, 17 Jan 2021 19:07:59 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switched rockchip64-current to 5.10.y (and synced -dev config/patches) (#2546)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125)
> X-Git-Archeology:
> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
> X-Git-Archeology:
> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 44c4cdf8653104bc395c504d7611d819906ff69b: https://github.com/armbian/build/commit/44c4cdf8653104bc395c504d7611d819906ff69b
> X-Git-Archeology: Date: Fri, 30 Dec 2022 21:17:33 +0100
> X-Git-Archeology: From: Konstantin Litvinov <koftikes@gmail.com>
> X-Git-Archeology: Subject: Fixed issue with NVMe identification in rk3399-rock-pi-4.dts (#4627)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
> X-Git-Archeology: - Revision 44c95b7b0a64486a85f23c5630842ea1b877a695: https://github.com/armbian/build/commit/44c95b7b0a64486a85f23c5630842ea1b877a695
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:01 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: fix unidiff warning from patches of rockchip64-6.3
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
@@ -111,6 +111,8 @@ vcc3v3_pcie: regulator-vcc3v3-pcie {
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
@@ -528,9 +530,11 @@ &pcie0 {
num-lanes = <4>;
pinctrl-0 = <&pcie_clkreqnb_cpm>;
pinctrl-names = "default";
+ vpcie12v-supply = <&vcc12v_dcin>;
vpcie0v9-supply = <&vcc_0v9>;
vpcie1v8-supply = <&vcc_1v8>;
vpcie3v3-supply = <&vcc3v3_pcie>;
+ bus-scan-delay-ms = <1500>;
status = "okay";
};
--
Armbian

25
patch/kernel/rockchip64-6.14/board-rockpie-0001-arm64-dts-rockchip-fix-gmac-PHY-attach-error.patch
View File

@ -1,25 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: FUKAUMI Naoki <naoki@radxa.com>
Date: Tue, 10 Sep 2024 19:33:28 +0000
Subject: arm64: dts: rockchip: fix gmac PHY attach error on ROCK Pi E
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
---
arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
@@ -164,6 +164,7 @@ mdio {
#size-cells = <0>;
rtl8211: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
reg = <1>;
pinctrl-0 = <&eth_phy_int_pin>, <&eth_phy_reset_pin>;
pinctrl-names = "default";
--
Armbian

121
patch/kernel/rockchip64-6.14/board-rockpis-dts-fixes.patch
View File

@ -1,121 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Wed, 27 Nov 2024 19:06:49 +0100
Subject: rk3308: fixes for rock pi s dts
---
arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 73 ++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
@@ -48,6 +48,54 @@ blue-led {
};
};
+ analog_sound: analog-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "analog";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,codec-hp-det;
+ simple-audio-card,widgets =
+ "Headphone", "Headphones";
+
+ simple-audio-card,dai-link@1 {
+ format = "i2s";
+
+ cpu {
+ sound-dai = <&i2s_8ch_2>;
+ };
+
+ codec {
+ sound-dai = <&codec>;
+ };
+
+ };
+
+ };
+
+ pcm5102_sound: pcm5102-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "pcm5102a";
+
+ simple-audio-card,dai-link@1 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&i2s_8ch_0>;
+ };
+
+ codec {
+ sound-dai = <&pcm5102a>;
+ };
+ };
+ };
+
+ pcm5102a: pcm5102a {
+ #sound-dai-cells = <0>;
+ compatible = "ti,pcm5102a";
+ pcm510x,format = "i2s";
+ };
+
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-0 = <&wifi_enable_h>;
@@ -128,6 +176,11 @@ vdd_log: regulator-vdd-log {
};
};
+&codec {
+ status = "okay";
+ #sound-dai-cells = <0>;
+};
+
&cpu0 {
cpu-supply = <&vdd_core>;
};
@@ -242,6 +295,19 @@ &io_domains {
status = "okay";
};
+&i2s_8ch_0 {
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&cru SCLK_I2S0_8CH_RX>;
+ assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>;
+ rockchip,clk-trcm = <1>;
+ status = "okay";
+};
+
+&i2s_8ch_2 {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&rtc_32k>;
@@ -333,10 +399,17 @@ &sdmmc {
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
+ card-detect-delay = <200>;
vmmc-supply = <&vcc_io>;
status = "okay";
};
+&tsadc {
+ rockchip,hw-tshut-mode = <0>; /* 0:CRU */
+ rockchip,hw-tshut-polarity = <1>; /* 1:HIGH */
+ status = "okay";
+};
+
&u2phy {
status = "okay";
--
Armbian

26
patch/kernel/rockchip64-6.14/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch
View File

@ -1,26 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Piotr Szczepanik <piter75@gmail.com>
Date: Mon, 24 Aug 2020 22:47:03 +0200
Subject: Rockpro64 add pcie bus scan delay
- See rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch
- Use 1000ms for rockpro64
---
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
@@ -677,6 +677,7 @@ &pcie0 {
vpcie1v8-supply = <&vcca_1v8>;
vpcie12v-supply = <&vcc12v_dcin>;
vpcie3v3-supply = <&vcc3v3_pcie>;
+ bus-scan-delay-ms = <1000>;
status = "okay";
};
--
Armbian

26
patch/kernel/rockchip64-6.14/board-rockpro64-change-rx_delay-for-gmac.patch
View File

@ -1,26 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Ayufan <ayufan@ayufan.eu>
Date: Sun, 30 Dec 2018 13:32:47 +0100
Subject: ayufan: dts: rockpro64: change rx_delay for gmac
Change-Id: Ib3899f684188aa1ed1545717af004bba53fe0e07
---
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
@@ -317,7 +317,7 @@ &gmac {
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
- rx_delay = <0x11>;
+ rx_delay = <0x20>;
status = "okay";
};
--
Armbian

33
patch/kernel/rockchip64-6.14/board-rockpro64-fix-emmc.patch
View File

@ -1,33 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Martin Ayotte <martinayotte@yahoo.ca>
Date: Wed, 5 Dec 2018 14:09:24 -0500
Subject: rockpro64: sdhci keep-power-in-suspend and set chosen bootargs
mmc_cmdqueue=0 and earlycon
---
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
@@ -17,6 +17,7 @@ aliases {
};
chosen {
+ bootargs = "mmc_cmdqueue=0 earlycon=uart8250,mmio32,0xff1a0000";
stdout-path = "serial2:1500000n8";
};
@@ -829,6 +830,7 @@ &sdmmc {
&sdhci {
bus-width = <8>;
+ keep-power-in-suspend;
mmc-hs200-1_8v;
non-removable;
status = "okay";
--
Armbian

26
patch/kernel/rockchip64-6.14/board-rockpro64-fix-spi1-flash-speed.patch
View File

@ -1,26 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Martin Ayotte <martinayotte@yahoo.ca>
Date: Sat, 5 Jan 2019 09:50:02 -0500
Subject: slow SPIFlash to avoid errors
See Revision ea20f750bfead37ced7b604a44f8f014e317abad
---
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
@@ -852,7 +852,7 @@ &spi1 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <10000000>;
+ spi-max-frequency = <3000000>;
};
};
--
Armbian

25
patch/kernel/rockchip64-6.14/board-rockpro64-work-led-heartbeat.patch
View File

@ -1,25 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Piotr Szczepanik <piter75@gmail.com>
Date: Mon, 24 Aug 2020 22:47:03 +0200
Subject: Switch RockPro64 work led to heartbeat trigger
---
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
@@ -66,7 +66,7 @@ leds {
work_led: led-0 {
label = "work";
- default-state = "on";
+ linux,default-trigger = "heartbeat";
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
};
--
Armbian

64
patch/kernel/rockchip64-6.14/board-rocks0-0001-Revert-arm64-dts-rockchip-Fix-sdmmc-access-on-rk3308.patch
View File

@ -1,64 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Igor Pecovnik <igor@armbian.com>
Date: Sat, 8 Feb 2025 17:54:03 +0100
Subject: Revert "arm64: dts: rockchip: Fix sdmmc access on rk3308-rock-s0 v1.1
boards"
This reverts commit 8810a8368b6075595715c4231322ca906a6b2f6f.
---
arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts | 25 +---------
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
@@ -74,23 +74,6 @@ vcc_io: regulator-3v3-vcc-io {
vin-supply = <&vcc5v0_sys>;
};
- /*
- * HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc.
- * This is modeled as an always-on active low fixed regulator.
- */
- vcc_sd: regulator-3v3-vcc-sd {
- compatible = "regulator-fixed";
- gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_2030>;
- regulator-name = "vcc_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_io>;
- };
-
vcc5v0_sys: regulator-5v0-vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@@ -198,12 +181,6 @@ pwr_led: pwr-led {
};
};
- sdmmc {
- sdmmc_2030: sdmmc-2030 {
- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
wifi {
wifi_reg_on: wifi-reg-on {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -256,7 +233,7 @@ &sdmmc {
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
- vmmc-supply = <&vcc_sd>;
+ vmmc-supply = <&vcc_io>;
status = "okay";
};
--
Armbian

506
patch/kernel/rockchip64-6.14/board-rocks0-0001-deviceTree.patch
View File

@ -1,506 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Brent Roman <genosenosor@gmail.com>
Date: Wed, 7 Feb 2024 18:02:07 -0800
Subject: Added Linux device tree for Rock S0
Signed-off-by: Brent Roman <genosenosor@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts | 346 ++++++----
1 file changed, 200 insertions(+), 146 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
@@ -1,21 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
+ * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
+ * Revised: 2024 Brent Roman <brent@mbari.org>
+ */
/dts-v1/;
-
-#include <dt-bindings/leds/common.h>
#include "rk3308.dtsi"
/ {
model = "Radxa ROCK S0";
compatible = "radxa,rock-s0", "rockchip,rk3308";
- aliases {
- ethernet0 = &gmac;
- mmc0 = &emmc;
- mmc1 = &sdmmc;
- mmc2 = &sdio;
- };
-
chosen {
stdout-path = "serial0:1500000n8";
};
@@ -23,38 +19,70 @@ chosen {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&pwr_led>;
+ pinctrl-0 = <&green_led_gio>;
- led-green {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "on";
- function = LED_FUNCTION_HEARTBEAT;
+ green-led {
+ label = "rock-s0:green:power";
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
+ default-state = "on";
};
};
- vdd_log: regulator-1v04-vdd-log {
- compatible = "regulator-fixed";
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1040000>;
- regulator-max-microvolt = <1040000>;
- vin-supply = <&vcc5v0_sys>;
+ acodec-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "rockchip,rk3308-acodec";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,codec-hp-det;
+ simple-audio-card,widgets =
+ "Headphone", "Headphones";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s_8ch_2>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
};
- vcc_ddr: regulator-1v5-vcc-ddr {
- compatible = "regulator-fixed";
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- vin-supply = <&vcc5v0_sys>;
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "i2s_8ch_0";
+
+ simple-audio-card,dai-link@1 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&i2s_8ch_0>;
+ };
+
+ codec {
+ sound-dai = <&pcm5102a>;
+ };
+ };
+ };
+
+ pcm5102a: pcm5102a {
+ #sound-dai-cells = <0>;
+ compatible = "ti,pcm5102a";
+ pcm510x,format = "i2s";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-0 = <&wifi_enable_h>;
+ pinctrl-names = "default";
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
};
- vcc_1v8: regulator-1v8-vcc {
+ vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
@@ -64,7 +92,7 @@ vcc_1v8: regulator-1v8-vcc {
vin-supply = <&vcc_io>;
};
- vcc_io: regulator-3v3-vcc-io {
+ vcc_io: vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
regulator-always-on;
@@ -74,7 +102,28 @@ vcc_io: regulator-3v3-vcc-io {
vin-supply = <&vcc5v0_sys>;
};
- vcc5v0_sys: regulator-5v0-vcc-sys {
+ vcc_ddr: vcc-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
@@ -83,119 +132,150 @@ vcc5v0_sys: regulator-5v0-vcc-sys {
regulator-max-microvolt = <5000000>;
};
- vdd_core: regulator-vdd-core {
+ vdd_core: vdd-core {
compatible = "pwm-regulator";
pwms = <&pwm0 0 5000 1>;
pwm-supply = <&vcc5v0_sys>;
regulator-name = "vdd_core";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>;
+ regulator-init-microvolt = <1015000>;
regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
};
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
+ vdd_log: vdd-log {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ board_antenna: board-antenna {
+ status = "okay";
+ compatible = "regulator-fixed";
+ enable-active-low;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ regulator-boot-on;
+ pinctrl-0 = <&ant_1>;
pinctrl-names = "default";
- pinctrl-0 = <&wifi_reg_on>;
- reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ regulator-name = "board_antenna";
};
};
+&codec {
+ status = "okay";
+ #sound-dai-cells = <0>;
+};
+
&cpu0 {
cpu-supply = <&vdd_core>;
};
&emmc {
cap-mmc-highspeed;
- no-sd;
- no-sdio;
+ mmc-hs200-1_8v;
non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_pwren>;
- vmmc-supply = <&vcc_io>;
+ vmmc-supply = <&vcc_io>; //was vin-supply
+ status = "okay";
+};
+
+&sdmmc {
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ card-detect-delay = <800>;
status = "okay";
};
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ no-mmc;
+ status = "okay";
+
+ AP6212: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake>;
+ };
+};
+
&gmac {
- clock_in_out = "output";
- phy-handle = <&rtl8201f>;
phy-supply = <&vcc_io>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&cru SCLK_MAC_SRC>;
+ snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 50000 50000>;
status = "okay";
+};
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtl8201f: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&mac_rst>;
- reset-assert-us = <20000>;
- reset-deassert-us = <50000>;
- reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- };
- };
+&i2s_8ch_0 {
+ assigned-clocks = <&cru SCLK_I2S0_8CH_RX>;
+ assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>;
+ rockchip,clk-trcm = <1>;
+ #sound-dai-cells = <0>;
};
-&io_domains {
- vccio0-supply = <&vcc_io>;
- vccio1-supply = <&vcc_io>;
- vccio2-supply = <&vcc_io>;
- vccio3-supply = <&vcc_io>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_io>;
+&i2s_8ch_2 {
status = "okay";
+ #sound-dai-cells = <0>;
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&rtc_32k>;
- bluetooth {
- bt_reg_on: bt-reg-on {
- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_host: bt-wake-host {
- rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- host_wake_bt: host-wake-bt {
- rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ leds {
+ green_led_gio: green-led-gpio {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
- gmac {
- mac_rst: mac-rst {
- rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ usb {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
- leds {
- pwr_led: pwr-led {
- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
- wifi_reg_on: wifi-reg-on {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ wifi_host_wake: wifi-host-wake {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
};
- wifi_wake_host: wifi-wake-host {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ antenna {
+ ant_1: ant-1 {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&pwm0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pin_pull_down>;
status = "okay";
+ pinctrl-0 = <&pwm0_pin_pull_down>;
};
&saradc {
@@ -203,91 +283,65 @@ &saradc {
status = "okay";
};
-&sdio {
- #address-cells = <1>;
- #size-cells = <0>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- max-frequency = <50000000>;
- mmc-pwrseq = <&sdio_pwrseq>;
- no-mmc;
- no-sd;
- non-removable;
- vmmc-supply = <&vcc_io>;
- vqmmc-supply = <&vcc_1v8>;
+&tsadc {
+ rockchip,hw-tshut-mode = <0>; /* 0:CRU */
+ rockchip,hw-tshut-polarity = <1>; /* 1:HIGH */
status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_wake_host>;
- };
};
-&sdmmc {
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- vmmc-supply = <&vcc_io>;
+&i2c1 {
status = "okay";
};
-&u2phy {
- status = "okay";
+&spi2 {
+// status = "okay"; //conflicts with UART2
+ max-freq = <10000000>;
};
-&u2phy_host {
+&uart0 {
status = "okay";
};
-&u2phy_otg {
+&uart2 {
status = "okay";
};
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer>;
+&uart4 {
status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+ };
};
-&uart4 {
- uart-has-rtscts;
+&u2phy {
status = "okay";
- bluetooth {
- compatible = "brcm,bcm43430a1-bt";
- clocks = <&cru SCLK_RTC32K>;
- clock-names = "lpo";
- interrupt-parent = <&gpio4>;
- interrupts = <RK_PB4 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wakeup";
- device-wakeup-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>;
- vbat-supply = <&vcc_io>;
- vddio-supply = <&vcc_1v8>;
+ u2phy_host: host-port {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
};
};
-&usb_host_ehci {
+&usb20_otg {
status = "okay";
};
-&usb_host_ohci {
+&usb_host_ehci {
status = "okay";
};
-&usb20_otg {
- dr_mode = "peripheral";
+&usb_host_ohci{
status = "okay";
};
&wdt {
status = "okay";
};
+
--
Armbian

248
patch/kernel/rockchip64-6.14/board-station-m2.patch
View File

@ -1,248 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: chainsx <chainsx@outlook.com>
Date: Fri, 21 Feb 2025 19:36:41 +0800
Subject: fix rk3566-roc-pc
---
arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 110 +++++++---
1 file changed, 80 insertions(+), 30 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
@@ -52,6 +52,16 @@ led-user {
pinctrl-0 = <&user_led_enable_h>;
retain-state-suspended;
};
+
+ led-firefly {
+ label = "firefly-led";
+ default-state = "off";
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&firefly_led_enable_h>;
+ retain-state-suspended;
+ };
};
rk809-sound {
@@ -70,6 +80,14 @@ simple-audio-card,codec {
};
};
+ rk_headset: rk-headset {
+ compatible = "rockchip_headset";
+ headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det>;
+ io-channels = <&saradc 2>; //HP_HOOK pin
+ };
+
sdio_pwrseq: sdio-pwrseq {
status = "okay";
compatible = "mmc-pwrseq-simple";
@@ -124,7 +142,7 @@ vcc5v0_usb30_host: regulator-vcc5v0-usb30-host {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb30_host";
enable-active-high;
- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
regulator-always-on;
@@ -137,7 +155,7 @@ vcc5v0_usb_otg: regulator-vcc5v0-usb-otg {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb_otg";
enable-active-high;
- gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
regulator-always-on;
@@ -171,6 +189,16 @@ &cpu3 {
cpu-supply = <&vdd_cpu>;
};
+&cpu_thermal {
+ trips {
+ cpu_hot: cpu_hot {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+};
+
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
@@ -465,20 +493,6 @@ vcc3v3_sd: SWITCH_REG2 {
};
};
-&i2c1 {
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3m0_xfer>;
- status = "okay";
-};
-
&i2s0_8ch {
status = "okay";
};
@@ -509,15 +523,15 @@ &pcie2x1 {
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
};
bt_wake_l: bt-wake-l {
- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -525,6 +539,10 @@ leds {
user_led_enable_h: user-led-enable-h {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
+
+ firefly_led_enable_h: firefly-led-enable-h {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
pcie {
@@ -543,7 +561,7 @@ pmic_int: pmic_int {
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
-
+
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -551,12 +569,18 @@ wifi_enable_h: wifi-enable-h {
};
usb {
- vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
- rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en-h {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en-h {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ };
- vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
- rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
@@ -574,6 +598,11 @@ &pmu_io_domains {
vccio7-supply = <&vcc_3v3>;
};
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
@@ -600,28 +629,36 @@ &sdmmc1 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
+ disable-wp;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
vmmc-supply = <&vcc3v3_sys>;
vqmmc-supply = <&vcca1v8_pmu>;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &uart9m1_xfer &uart8m1_xfer>;
status = "okay";
};
-&tsadc {
+&sdmmc2 {
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ bus-width = <4>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+ sd-uhs-sdr104;
status = "okay";
};
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer>;
+&tsadc {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
status = "okay";
uart-has-rtscts;
@@ -653,6 +690,11 @@ &usb2phy0_otg {
status = "okay";
};
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb30_host>;
status = "okay";
@@ -682,6 +724,14 @@ &usb_host0_ohci {
status = "okay";
};
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
--
Armbian

599
patch/kernel/rockchip64-6.14/board-station-p2.patch
View File

@ -1,599 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: chainsx <chainsx@outlook.com>
Date: Thu, 25 Jul 2024 16:40:28 +0200
Subject: [ARCHEOLOGY] fix rk3568-roc-pc
> X-Git-Archeology: - Revision 1c7c5d302dbc52a5c9a16a4e9f12786277e56fac: https://github.com/armbian/build/commit/1c7c5d302dbc52a5c9a16a4e9f12786277e56fac
> X-Git-Archeology: Date: Thu, 25 Jul 2024 16:40:28 +0200
> X-Git-Archeology: From: chainsx <chainsx@outlook.com>
> X-Git-Archeology: Subject: fix rk3568-roc-pc
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts | 380 ++++++++--
1 file changed, 325 insertions(+), 55 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
@@ -48,17 +48,15 @@ gmac1_clkin: external-gmac1-clock {
#clock-cells = <0>;
};
- leds {
+ firefly_leds: leds {
compatible = "gpio-leds";
-
- led-user {
- label = "user-led";
+ power_led: power {
+ label = "firefly:blue:power";
+ linux,default-trigger = "ir-power-click";
default-state = "on";
gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
pinctrl-names = "default";
- pinctrl-0 = <&user_led_enable_h>;
- retain-state-suspended;
+ pinctrl-0 = <&led_power>;
};
};
@@ -126,41 +124,134 @@ vcc5v0_sys: regulator-vcc5v0-sys {
vin-supply = <&dc_12v>;
};
- vcc5v0_usb: regulator-vcc5v0-usb {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
vcc5v0_host: regulator-vcc5v0-host {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
enable-active-high;
- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-always-on;
- vin-supply = <&vcc5v0_usb>;
};
vcc5v0_otg: regulator-vcc5v0-otg {
compatible = "regulator-fixed";
- regulator-name = "vcc5v0_otg";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_otg_en>;
- vin-supply = <&vcc5v0_usb>;
+ regulator-name = "vcc5v0_otg";
};
-};
-&combphy0 {
- /* used for USB3 */
- status = "okay";
+ vcc2v5_sys: vcc2v5-ddr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc2v5-sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc_hub_power: vcc-hub-power-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_hub_power_en>;
+ regulator-name = "vcc_hub_power_en";
+ regulator-always-on;
+ };
+
+ vcc_hub_reset: vcc-hub-reset-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_hub_reset_en>;
+ regulator-name = "vcc_hub_reset_en";
+ regulator-always-on;
+ };
+
+ pcie_pi6c_oe: pcie-pi6c-oe-regulator {
+ compatible = "regulator-fixed";
+ //enable-active-high;
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pi6c_oe_en>;
+ regulator-name = "pcie_pi6c_oe_en";
+ regulator-always-on;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <100>;
+ };
+
+ wireless_wlan: wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "ap6275s";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_irq>;
+ WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ wireless_bluetooth: wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ //wifi-bt-power-toggle;
+ uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "rts_gpio";
+ pinctrl-0 = <&uart8m0_rtsn>;
+ pinctrl-1 = <&uart8_gpios>;
+ BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ flash_led: flash-led {
+ compatible = "led,rgb13h";
+ label = "pwm-flash-led";
+ led-max-microamp = <20000>;
+ flash-max-microamp = <20000>;
+ flash-max-timeout-us = <1000000>;
+ pwms = <&pwm11 0 25000 0>;
+ rockchip,camera-module-index = <1>;
+ rockchip,camera-module-facing = "front";
+ status = "disabled";
+ };
+
+ rk809-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Analog RK809";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&rk809>;
+ };
+ };
+
+ rk_headset: rk-headset {
+ compatible = "rockchip_headset";
+ headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det>;
+ io-channels = <&saradc 2>; //HP_HOOK pin
+ };
};
&combphy1 {
@@ -247,15 +338,59 @@ &hdmi_sound {
&i2c0 {
status = "okay";
+ fusb0: fusb30x@22 {
+ compatible = "fairchild,fusb302";
+ reg = <0x22>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb0_int>;
+ int-n-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ fusb340-switch-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
+ vbus-5v-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "fan53555-reg";
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-ramp-delay = <2300>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-rates = <12288000>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ pinctrl-names = "default", "pmic-sleep",
+ "pmic-power-off", "pmic-reset";
+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+
system-power-controller;
+ #sound-dai-cells = <0>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ //fb-inner-reg-idxs = <2>;
+ /* 1: rst regs (default in codes), 0: rst the pmic */
+ pmic-reset-func = <0>;
+ /* not save the PMIC_POWER_EN register in uboot */
+ not-save-power-en = <1>;
+
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
@@ -283,6 +418,8 @@ regulator-state-mem {
};
vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
regulator-name = "vdd_gpu";
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
@@ -317,19 +454,9 @@ regulator-state-mem {
};
};
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
vdda0v9_image: LDO_REG1 {
+ regulator-boot-on;
+ regulator-always-on;
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
@@ -365,6 +492,8 @@ regulator-state-mem {
};
vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
regulator-name = "vccio_acodec";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -376,6 +505,8 @@ regulator-state-mem {
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@@ -423,6 +554,8 @@ regulator-state-mem {
};
vcca1v8_image: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
regulator-name = "vcca1v8_image";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -432,6 +565,17 @@ regulator-state-mem {
};
};
+ vcc_1v8: DCDC_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
@@ -452,6 +596,10 @@ regulator-state-mem {
};
};
};
+
+ codec {
+ mic-in-differential;
+ };
};
};
@@ -474,7 +622,7 @@ rgmii_phy1: phy@0 {
};
&pcie30phy {
- status = "okay";
+ tatus = "okay";
};
&pcie3x2 {
@@ -487,19 +635,27 @@ &pcie3x2 {
&pinctrl {
leds {
- user_led_enable_h: user-led-enable-h {
- rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ led_power: led-power {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_otg_en: vcc5v0-otg-en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
+
+ vcc_hub_power_en: vcc-hub-power-en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc_hub_reset_en: vcc-hub-reset-en {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
pcie {
@@ -509,21 +665,53 @@ pcie_reset_pin: pcie-reset-pin {
vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ pcie_pi6c_oe_en: pcie-pi6c-oe-en {
+ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
pmic {
- pmic_int: pmic-int {
+ pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-wlan {
+ wifi_host_wake_irq: wifi-host-wake-irq {
+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ wireless-bluetooth {
+ uart8_gpios: uart8-gpios {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ fusb30x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
- vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
@@ -545,25 +733,44 @@ &sdhci {
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ supports-emmc;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
- pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
+ max-frequency = <150000000>;
+ supports-sd;
+ cap-mmc-highspeed;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdmmc2 {
+ max-frequency = <150000000>;
+ supports-sdio;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+ sd-uhs-sdr104;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
status = "okay";
};
&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
@@ -585,6 +792,7 @@ &usb2phy1 {
};
&usb2phy0_otg {
+ vbus-supply = <&vcc5v0_otg>;
status = "okay";
};
@@ -606,6 +814,10 @@ &usb_host0_ohci {
status = "okay";
};
+&usb_host0_xhci {
+ status = "okay";
+};
+
&usb_host1_ehci {
status = "okay";
};
@@ -614,11 +826,13 @@ &usb_host1_ohci {
status = "okay";
};
-&usb_host0_xhci {
+&usb_host1_xhci {
status = "okay";
};
-&usb_host1_xhci {
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
@@ -629,12 +843,68 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
};
};
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+&vop_mmu {
status = "okay";
};
-&vop_mmu {
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclktx
+ &i2s1m0_lrcktx
+ &i2s1m0_sdi0
+ &i2s1m0_sdo0>;
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&gic {
+ status = "okay";
+};
+
+&uart3 {
+// status = "disabled";
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m1_xfer>;
+ status = "okay";
+};
+
+&uart8 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
+};
+
+&rk809 {
+ rtc {
+ status = "disabled";
+ };
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&pwm5 {
+ status = "okay";
+};
+
+&pwm7 {
status = "okay";
};
--
Armbian

337
patch/kernel/rockchip64-6.14/dt/rk3308-sakurapi-rk3308b.dts
View File

@ -1,337 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
* Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
* Copyright (C) 2024 TheSnowfield <thesnowfield@sakurapi.org>
*/
/dts-v1/;
#include "rk3308.dtsi"
#include <dt-bindings/leds/common.h>
/ {
model = "Sakura Pi RK3308B";
compatible = "rockchip,rk3308";
chosen {
stdout-path = "serial2:1500000n8";
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-0 = <&wifi_enable_h>;
pinctrl-names = "default";
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
};
vcc5v0_sys: regulator-vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vdd_core: regulator-vdd-core {
compatible = "pwm-regulator";
pwms = <&pwm0 0 5000 1>;
regulator-name = "vdd_core";
regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>;
regulator-init-microvolt = <1015000>;
regulator-settling-time-up-us = <250>;
regulator-always-on;
regulator-boot-on;
pwm-supply = <&vcc5v0_sys>;
};
vdd_log: regulator-vdd-log {
compatible = "regulator-fixed";
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_ddr: regulator-vcc-ddr {
compatible = "regulator-fixed";
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_io>;
};
vcc_io: regulator-vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_phy: regulator-vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
vcc5v0_otg: regulator-vcc5v0-otg {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_otg";
regulator-always-on;
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
vin-supply = <&vcc5v0_sys>;
};
backlight: backlight {
status = "okay";
compatible = "pwm-backlight";
pwms = <&pwm3 0 25000 0>;
brightness-levels = <0 255>;
default-brightness-level = <255>;
};
display: panel {
compatible = "edt,et070080dh6";
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
enable-delay-ms = <20>;
status = "okay";
panel_in: port {
#address-cells = <1>;
#size-cells = <0>;
panel_in_rgb: endpoint {
reg = <0>;
remote-endpoint = <&vop_out_rgb>;
};
};
};
};
&cpu0 {
cpu-supply = <&vdd_core>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
non-removable;
status = "okay";
};
&i2c1 {
status = "okay";
};
&sdmmc {
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
card-detect-delay = <800>;
status = "okay";
};
&sdio {
#address-cells = <1>;
#size-cells = <0>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
no-mmc;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm43455-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake>;
};
};
&dmac0 {
status = "okay";
};
/* SPI0 for external gpio pin */
&spi0 {
status = "okay";
spi_dev@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <0x2faf080>;
};
};
/* SPI1 for ws2812*/
&spi1 {
status = "okay";
spi_dev@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <0x2faf080>;
};
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&rtc_32k>;
usb {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_host_wake: wifi-host-wake {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
bluetooth {
bt_reg_on: bt-reg-on {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_host: bt-wake-host {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
host_wake_bt: host-wake-bt {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_pin_pull_down>;
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&vop {
status = "okay";
vop_out: port {
#address-cells = <1>;
#size-cells = <0>;
vop_out_rgb: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_rgb>;
};
};
};
&pwm3 {
status = "okay";
};
&display_subsystem {
status = "okay";
};
&i2c1 {
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4345c5";
clocks = <&cru SCLK_RTC32K>;
clock-names = "lpo";
pinctrl-names = "default";
pinctrl-0 = <&host_wake_bt &bt_wake_host &bt_reg_on>;
device-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
max-speed = <1500000>;
};
};
&tsadc{
status = "okay";
};
&usb20_otg {
dr_mode = "peripheral";
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&usb_host_ehci {
status = "okay";
};
&usb_host_ohci{
status = "okay";
};

1009
patch/kernel/rockchip64-6.14/dt/rk3318-box.dts
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288
patch/kernel/rockchip64-6.14/dt/rk3328-heltec.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include "rk3328.dtsi"
/ {
model = "Rockchip RK3328 Heltec";
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
aliases {
mmc0 = &sdmmc;
mmc1 = &sdio;
mmc2 = &emmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0m1_pin>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gmac2phy {
phy-supply = <&vcc_phy>;
clock_in_out = "output";
assigned-clock-rate = <50000000>;
assigned-clocks = <&cru SCLK_MAC2PHY>;
assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
status = "okay";
};
&i2c1 {
status = "okay";
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_io>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_18: LDO_REG1 {
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins =
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <150000000>;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
vmmc-supply = <&vcc_sd>;
status = "okay";
};
&tsadc {
status = "okay";
};
&uart2 {
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};

620
patch/kernel/rockchip64-6.14/dt/rk3328-mksklipad50.dts
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@ -1,620 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Based on rk3328-roc-cc.dtb from original MKS-Klipad50 image
*
* Copyright (c) 2025 Thorsten Maerz
*/
/dts-v1/;
#include "rk3328-dram-renegade-timing.dtsi"
#include "rk3328.dtsi"
/ {
model = "Makerbase MKS-KLIPAD50";
compatible = "mks,rk3328-mksklipad50", "mks,rk3328-mkspi", "rockchip,rk3328";
aliases {
ethernet0 = &gmac2io;
ethernet1 = &gmac2phy;
mmc0 = &sdmmc;
mmc1 = &emmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
/delete-node/ dmc-opp-table;
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
opp-786000000 {
opp-hz = /bits/ 64 <786000000>;
opp-microvolt = <1075000 1075000 12000000>;
status = "disabled";
};
opp-798000000 {
opp-hz = /bits/ 64 <798000000>;
opp-microvolt = <1075000 1075000 12000000>;
status = "disabled";
};
opp-840000000 {
opp-hz = /bits/ 64 <840000000>;
opp-microvolt = <1075000 1075000 12000000>;
};
opp-924000000 {
opp-hz = /bits/ 64 <924000000>;
opp-microvolt = <1100000 1100000 12000000>;
};
opp-1068000000 {
opp-hz = /bits/ 64 <1068000000>;
opp-microvolt = <1175000 1175000 12000000>;
};
};
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0m1_pin>;
regulator-boot-on;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc_sdio: sdmmcio-regulator {
compatible = "regulator-gpio";
gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&sdio_vcc_pin>;
pinctrl-names = "default";
states = <1800000 0x0>,
<3300000 0x1>;
regulator-name = "vcc_sdio";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-settling-time-us = <5000>;
startup-delay-us = <2000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&vcc_io>;
};
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
power_led: led-0 {
label = "firefly:green:power";
linux,default-trigger = "heartbeat";
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
default-state = "on";
mode = <0x23>;
};
user_led: led-1 {
label = "firefly:blue:user";
linux,default-trigger = "activity";
gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
default-state = "off";
mode = <0x05>;
};
};
usb3phy_grf: syscon@ff460000 {
compatible = "rockchip,usb3phy-grf", "syscon";
reg = <0x0 0xff460000 0x0 0x1000>;
};
u3phy: usb3-phy@ff470000 {
compatible = "rockchip,rk3328-u3phy";
reg = <0x0 0xff470000 0x0 0x0>;
rockchip,u3phygrf = <&usb3phy_grf>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
clock-names = "u3phy-otg", "u3phy-pipe";
resets = <&cru SRST_USB3PHY_U2>,
<&cru SRST_USB3PHY_U3>,
<&cru SRST_USB3PHY_PIPE>,
<&cru SRST_USB3OTG_UTMI>,
<&cru SRST_USB3PHY_OTG_P>,
<&cru SRST_USB3PHY_PIPE_P>;
reset-names = "u3phy-u2-por", "u3phy-u3-por",
"u3phy-pipe-mac", "u3phy-utmi-mac",
"u3phy-utmi-apb", "u3phy-pipe-apb";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
u3phy_utmi: utmi@ff470000 {
reg = <0x0 0xff470000 0x0 0x8000>;
#phy-cells = <0>;
status = "okay";
};
u3phy_pipe: pipe@ff478000 {
reg = <0x0 0xff478000 0x0 0x8000>;
#phy-cells = <0>;
status = "okay";
};
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
sdio_vref = <3300>;
status = "okay";
WIFI,host_wake_irq = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
wifi_chip_type = "rtl8723bs";
};
sdio_pwrseq0: sdio_pwrseq0 {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
};
};
&analog_sound {
simple-audio-card,name = "TRS Jack";
status = "okay";
};
&codec {
mute-gpios = <&grf_gpio RK_PA0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gmac2phy {
assigned-clocks = <&cru SCLK_MAC2PHY>;
assigned-clock-rate = <50000000>;
assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
phy-supply = <&vcc_phy>;
status = "disabled";
};
&dfi {
status = "okay";
};
&dmc {
center-supply = <&vdd_logic>;
ddr_timing = <&ddr_timing>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <150000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc18_emmc>;
status = "okay";
};
&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
snps,aal;
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
snps,rxpbl = <0x4>;
snps,txpbl = <0x4>;
tx_delay = <0x24>;
rx_delay = <0x18>;
status = "disabled";
};
&gpu {
mali-supply = <&vdd_logic>;
};
&hdmi {
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI>,
<&cru SCLK_HDMI_SFC>,
<&hdmiphy>,
<&cru SCLK_RTC32K>;
clock-names = "iahb",
"isfr",
"vpll",
"cec";
pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd &hdmi_backlight>;
status = "okay";
};
&hdmiphy {
status = "okay";
};
&hdmi_sound {
status = "disabled";
};
&i2c1 {
status = "okay";
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio1>;
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_io>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1175000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <1400000>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_18: LDO_REG1 {
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&i2s1 {
status = "okay";
};
&pwm3 {
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
vccio3-supply = <&vcc_sdio>;
vccio4-supply = <&vcc_io>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
pmuio-supply = <&vcc_io>;
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&rtc_32k>;
rtc: rtc {
rtc_32k: rtc-32k {
rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
usb20_host_drv: usb20-host-drv {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sd {
sdio_vcc_pin: sdio-vcc-pin {
rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio_pwrseq: sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless_wlan_pin: wireless-wlan {
wifi_wake_host: wifi-wake-host {
rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
hdmi_pin {
hdmi_backlight: hdmi-backlight {
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>;
};
};
spi0_cs2 {
pinctrl_spi0_cs2: pinctrl_spi0_cs2 {
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
&spdif {
pinctrl-0 = <&spdifm0_tx>;
status = "disabled";
};
&spdif_out {
status = "disabled";
};
&spdif_sound {
status = "disabled";
};
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_xfer &uart0_cts>;
status = "okay";
};
&uart2 {
status = "okay";
};
&spi0 {
max-freq = <48000000>;
cs-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx>;
status = "okay";
spi_for_cs2@0 {
reg = <0>;
compatible ="armbian,spi-dev";
pinctrl-names ="default";
pinctrl-0 = <&pinctrl_spi0_cs2>;
spi-max-frequency = <5000000>;
status = "okay";
};
};
&sdio {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
mmc-pwrseq = <&sdio_pwrseq0>;
status = "okay";
non-removable;
bus-width = <0x04>;
cap-sd-highspeed;
cap-sdio-irq;
};
&usb20_otg {
dr_mode = "host";
status = "okay";
};
&usbdrd3 {
dr_mode = "host";
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_LCDC>;
assigned-clock-parents = <&cru HDMIPHY>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vpu {
status = "disabled";
};
&vdec {
status = "disabled";
};
&rga {
status = "disabled";
};

592
patch/kernel/rockchip64-6.14/dt/rk3328-mkspi.dts
View File

@ -1,592 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Based on rk3328-roc-cc.dts
*
* Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
*/
/dts-v1/;
#include "rk3328-dram-renegade-timing.dtsi"
#include "rk3328.dtsi"
/ {
model = "Makerbase MKS-PI";
compatible = "mks,rk3328-mkspi", "rockchip,rk3328";
aliases {
mmc0 = &sdmmc;
mmc1 = &emmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
/delete-node/ dmc-opp-table;
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
opp-786000000 {
opp-hz = /bits/ 64 <786000000>;
opp-microvolt = <1075000 1075000 12000000>;
};
opp-798000000 {
opp-hz = /bits/ 64 <798000000>;
opp-microvolt = <1075000 1075000 12000000>;
};
opp-840000000 {
opp-hz = /bits/ 64 <840000000>;
opp-microvolt = <1075000 1075000 12000000>;
};
opp-924000000 {
opp-hz = /bits/ 64 <924000000>;
opp-microvolt = <1100000 1100000 12000000>;
};
opp-1068000000 {
opp-hz = /bits/ 64 <1068000000>;
opp-microvolt = <1175000 1175000 12000000>;
};
};
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0m1_pin>;
regulator-boot-on;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc_sdio: sdmmcio-regulator {
compatible = "regulator-gpio";
gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&sdio_vcc_pin>;
pinctrl-names = "default";
states = <1800000 0x0>,
<3300000 0x1>;
regulator-name = "vcc_sdio";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&vcc_io>;
};
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
power_led: led-0 {
label = "firefly:blue:power";
linux,default-trigger = "heartbeat";
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
default-state = "on";
mode = <0x23>;
};
user_led: led-1 {
label = "firefly:yellow:user";
linux,default-trigger = "mmc1";
gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
default-state = "off";
mode = <0x05>;
};
};
usb3phy_grf: syscon@ff460000 {
compatible = "rockchip,usb3phy-grf", "syscon";
reg = <0x0 0xff460000 0x0 0x1000>;
};
u3phy: usb3-phy@ff470000 {
compatible = "rockchip,rk3328-u3phy";
reg = <0x0 0xff470000 0x0 0x0>;
rockchip,u3phygrf = <&usb3phy_grf>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
clock-names = "u3phy-otg", "u3phy-pipe";
resets = <&cru SRST_USB3PHY_U2>,
<&cru SRST_USB3PHY_U3>,
<&cru SRST_USB3PHY_PIPE>,
<&cru SRST_USB3OTG_UTMI>,
<&cru SRST_USB3PHY_OTG_P>,
<&cru SRST_USB3PHY_PIPE_P>;
reset-names = "u3phy-u2-por", "u3phy-u3-por",
"u3phy-pipe-mac", "u3phy-utmi-mac",
"u3phy-utmi-apb", "u3phy-pipe-apb";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
u3phy_utmi: utmi@ff470000 {
reg = <0x0 0xff470000 0x0 0x8000>;
#phy-cells = <0>;
status = "okay";
};
u3phy_pipe: pipe@ff478000 {
reg = <0x0 0xff478000 0x0 0x8000>;
#phy-cells = <0>;
status = "okay";
};
};
};
&analog_sound {
status = "disabled";
};
&codec {
status = "okay";
};
&gmac2phy {
assigned-clocks = <&cru SCLK_MAC2PHY>;
assigned-clock-rate = <50000000>;
assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
phy-supply = <&vcc_phy>;
status = "okay";
};
&dfi {
status = "okay";
};
&dmc {
center-supply = <&vdd_logic>;
ddr_timing = <&ddr_timing>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <150000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc18_emmc>;
status = "okay";
};
&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
snps,aal;
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
snps,rxpbl = <0x4>;
snps,txpbl = <0x4>;
tx_delay = <0x24>;
rx_delay = <0x18>;
status = "disabled";
};
&gpu {
mali-supply = <&vdd_logic>;
};
&hdmi {
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI>,
<&cru SCLK_HDMI_SFC>,
<&hdmiphy>, //0x4b
<&cru SCLK_RTC32K>;
clock-names = "iahb",
"isfr",
"vpll",
"cec";
status = "okay";
};
&hdmiphy {
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c1 {
status = "okay";
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_io>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_18: LDO_REG1 {
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
vccio3-supply = <&vcc_sdio>;
vccio4-supply = <&vcc_io>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
pmuio-supply = <&vcc_io>;
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
usb20_host_drv: usb20-host-drv {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sd {
sdio_vcc_pin: sdio-vcc-pin {
rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
touchscreen {
pinctrl_tsc2046_pendown: pinctrl_tsc2046_pendown {
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
pinctrl_tsc2046_cs: pinctrl_tsc2046_cs {
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
lcd {
pinctrl_st7796_cs: pinctrl_st7796_cs {
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
spi0_cs2 {
pinctrl_spi0_cs2: pinctrl_spi0_cs2 {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
&spdif {
pinctrl-0 = <&spdifm0_tx>;
status = "okay";
};
&spdif_out {
status = "okay";
};
&spdif_sound {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_xfer &uart0_cts>;
status = "okay";
};
&uart2 {
status = "okay";
};
&spi0 {
max-freq = <48000000>;
cs-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>,<&gpio3 RK_PA7 GPIO_ACTIVE_LOW>,<&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx>;
status = "okay";
spi_for_lcd@0 {
compatible ="ilitek,st7796";
pinctrl-names ="default";
pinctrl-0 = <&pinctrl_st7796_cs>;
reg = <0>;
spi-max-frequency = <25000000>;
bgr;
fps = <30>;
rotate = <270>;
buswidth = <8>;
dc-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; /* gpio3 A6 */
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; /* gpio3 A4 */
led-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* gpio3 A5 */
status = "okay";
};
spi_for_touch@1 {
reg = <1>;
compatible = "ti,tsc2046";
pinctrl-names ="default";
pinctrl-0 = <&pinctrl_tsc2046_pendown &pinctrl_tsc2046_cs>;
ti,x-max = /bits/ 16 <3776>;
ti,x-min = /bits/ 16 <164>;
ti,y-min = /bits/ 16 <201>;
ti,y-max = /bits/ 16 <3919>;
ti,x-plate-ohms = /bits/ 16 <40>;
ti,pressure-max = /bits/ 16 <255>;
//touchscreen-fuzz-x = <16>;
//touchscreen-fuzz-y = <16>;
//touchscreen-fuzz-pressure = <10>;
ti,swap-xy = <1>;
touchscreen-inverted-y = <1>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PC6 GPIO_ACTIVE_LOW>;
spi-max-frequency = <2000000>;
pendown-gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
vcc-supply = <&vcc_io>;
wakeup-source;
status = "okay";
};
spi_for_cs2@2 {
reg = <2>;
compatible ="armbian,spi-dev";
pinctrl-names ="default";
pinctrl-0 = <&pinctrl_spi0_cs2>;
spi-max-frequency = <5000000>;
status = "okay";
};
};
&usb20_otg {
dr_mode = "host";
status = "okay";
};
&usbdrd3 {
dr_mode = "host";
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_LCDC>;
assigned-clock-parents = <&cru HDMIPHY>;
status = "okay";
};
&vop_mmu {
status = "okay";
};

195
patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-neo3-rev02.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include "rk3328-nanopi-r2s.dts"
/ {
model = "FriendlyElec NanoPi NEO3";
compatible = "friendlyelec,nanopi-neo3", "rockchip,rk3328";
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&gpio_key1>;
button@0 {
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <BTN_1>;
linux,input-type = <1>;
gpio-key,wakeup = <1>;
debounce-interval = <100>;
};
};
i2s-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "I2S Out";
status = "okay";
simple-audio-card,cpu {
sound-dai = <&i2s1>;
};
simple-audio-card,codec {
sound-dai = <&pcm5102>;
};
};
pcm5102: pcm510x {
#sound-dai-cells = <0>;
compatible = "ti,pcm5102a";
pcm510x,format = "i2s";
};
sound-spdif {
compatible = "simple-audio-card";
simple-audio-card,name = "SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
vcc_rtl8153: vcc-rtl8153-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb30_en_drv>;
regulator-always-on;
regulator-name = "vcc_rtl8153";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
off-on-delay-us = <5000>;
enable-active-high;
};
};
&mach {
hwrev = <2>;
model = "NanoPi NEO3";
};
&i2s1 {
rockchip,playback-channels = <2>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_mclk
&i2s1_sclk
&i2s1_lrcktx
&i2s1_lrckrx
&i2s1_sdo
&i2s1_sdi>;
status = "okay";
};
&spdif {
status = "okay";
pinctrl-0 = <&spdifm0_tx>;
};
&emmc {
status = "disabled";
};
&i2c0 {
status = "okay";
};
&leds {
status = "okay";
};
&leds_gpio {
rockchip,pins =
<0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
&pwm2 {
pinctrl-names = "default", "sleep";
pinctrl-1 = <&pwm2_sleep_pin>;
status = "okay";
};
&rk805 {
interrupt-parent = <&gpio1>;
interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
};
&vccio_sd {
status = "okay";
};
&io_domains {
vccio3-supply = <&vccio_sd>;
};
&sdmmc {
vqmmc-supply = <&vccio_sd>;
max-frequency = <150000000>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc_ext {
status = "disabled";
};
&sdio_pwrseq {
status = "disabled";
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pwm {
pwm2_sleep_pin: pwm2-sleep-pin {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
};
};
rockchip-key {
gpio_key1: gpio-key1 {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb30_en_drv: usb30-en-drv {
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&uart1{
status = "okay";
pinctl-0 = <&uart1_xfer>;
};

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patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev00.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include "rk3328-nanopi-r2s.dts"
/ {
model = "FriendlyElec NanoPi R2S";
compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&gpio_key1>;
button@0 {
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <BTN_1>;
linux,input-type = <1>;
gpio-key,wakeup = <1>;
debounce-interval = <100>;
};
};
vcc_rtl8153: vcc-rtl8153-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb30_en_drv>;
regulator-always-on;
regulator-name = "vcc_rtl8153";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
off-on-delay-us = <5000>;
enable-active-high;
};
};
&mach {
hwrev = <0>;
model = "NanoPi R2S";
};
&emmc {
status = "disabled";
};
&i2c0 {
status = "okay";
};
&leds {
status = "okay";
led@2 {
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
label = "lan_led";
};
led@3 {
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
label = "wan_led";
};
};
&rk805 {
interrupt-parent = <&gpio1>;
interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
};
&vccio_sd {
status = "okay";
};
&io_domains {
vccio3-supply = <&vccio_sd>;
};
&sdmmc {
vqmmc-supply = <&vccio_sd>;
max-frequency = <150000000>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc_ext {
status = "disabled";
};
&sdio_pwrseq {
status = "disabled";
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rockchip-key {
gpio_key1: gpio-key1 {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb30_en_drv: usb30-en-drv {
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

92
patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev06.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*/
/dts-v1/;
#include "rk3328-nanopi-r2-rev00.dts"
/ {
model = "FriendlyElec NanoPi R2C";
compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
};
&mach {
hwrev = <6>;
model = "NanoPi R2C";
};
&rgmiim1_pins {
rockchip,pins =
/* mac_txclk */
<1 RK_PB4 2 &pcfg_pull_none_8ma>,
/* mac_rxclk */
<1 RK_PB5 2 &pcfg_pull_none>,
/* mac_mdio */
<1 RK_PC3 2 &pcfg_pull_none_2ma>,
/* mac_txen */
<1 RK_PD1 2 &pcfg_pull_none_8ma>,
/* mac_clk */
<1 RK_PC5 2 &pcfg_pull_none_2ma>,
/* mac_rxdv */
<1 RK_PC6 2 &pcfg_pull_none>,
/* mac_mdc */
<1 RK_PC7 2 &pcfg_pull_none_2ma>,
/* mac_rxd1 */
<1 RK_PB2 2 &pcfg_pull_none>,
/* mac_rxd0 */
<1 RK_PB3 2 &pcfg_pull_none>,
/* mac_txd1 */
<1 RK_PB0 2 &pcfg_pull_none_8ma>,
/* mac_txd0 */
<1 RK_PB1 2 &pcfg_pull_none_8ma>,
/* mac_rxd3 */
<1 RK_PB6 2 &pcfg_pull_none>,
/* mac_rxd2 */
<1 RK_PB7 2 &pcfg_pull_none>,
/* mac_txd3 */
<1 RK_PC0 2 &pcfg_pull_none_8ma>,
/* mac_txd2 */
<1 RK_PC1 2 &pcfg_pull_none_8ma>,
/* mac_txclk */
<0 RK_PB0 1 &pcfg_pull_none>,
/* mac_txen */
<0 RK_PB4 1 &pcfg_pull_none>,
/* mac_clk */
<0 RK_PD0 1 &pcfg_pull_none>,
/* mac_txd1 */
<0 RK_PC0 1 &pcfg_pull_none>,
/* mac_txd0 */
<0 RK_PC1 1 &pcfg_pull_none>,
/* mac_txd3 */
<0 RK_PC7 1 &pcfg_pull_none>,
/* mac_txd2 */
<0 RK_PC6 1 &pcfg_pull_none>;
};
/delete-node/ &rtl8211e;
&gmac2io {
phy-handle = <&ethphy3>;
snps,reset-delays-us = <0 15000 50000>;
tx_delay = <0x22>;
rx_delay = <0x12>;
mdio {
ethphy3: ethernet-phy@3 {
compatible = "ethernet-phy-id0000.011a",
"ethernet-phy-ieee802.3-c22";
reg = <3>;
interrupt-parent = <&gpio2>;
interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
//reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
motorcomm,clk-out-frequency-hz = <125000000>; // enable gmac clock
motorcomm,keep-pll-enabled; // keep pll run without link
motorcomm,auto-sleep-disabled; // disable sleep without link
keep-clkout-on;
};
};
};

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patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev20.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*/
/dts-v1/;
#include "rk3328-nanopi-r2s.dts"
/ {
model = "FriendlyElec NanoPi R2";
compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
};
&mach {
hwrev = <0x20>;
model = "NanoPi R2";
};
&gmac2io {
pinctrl-0 = <&rgmiim1_pins>, <&phy_intb>, <&phy_rstb>;
};
&rtl8211e {
interrupt-parent = <&gpio1>;
interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
};
&pinctrl {
phy {
phy_intb: phy-intb {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
phy_rstb: phy-rstb {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

24
patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2s-plus-rev00.dts
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@ -1,24 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Ian Goodacre
*/
/dts-v1/;
#include "rk3328-nanopi-r2s-plus.dts"
/delete-node/ &rtl8211e;
&gmac2io {
phy-handle = <&rtl8211f>;
snps,reset-delays-us = <0 15000 50000>;
tx_delay = <0x22>;
rx_delay = <0x12>;
mdio {
rtl8211f: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
realtek,ledsel = <0xae00>;
};
};
};

1
patch/kernel/rockchip64-6.14/dt/rk3328-z28pro.dts
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@ -1 +0,0 @@
#include "rk3328-rock64.dts"

776
patch/kernel/rockchip64-6.14/dt/rk3399-am40.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
* Copyright (c) 2025 retro98boy <retro98boy@qq.com>
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
/ {
model = "SMART AM40";
compatible = "smart,am40", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;
mmc0 = &sdhci;
mmc1 = &sdmmc;
rtc0 = &pt7c4563;
/*
* The rk808 circuit design on this board does not have the ability to maintain real-time time after a power outage.
* Registering rk808 as rtc99 (most kernel configurations read time from rtc0) can prevent the kernel from reading the time (2013) from rk808 during startup.
*/
rtc99 = &rk808;
};
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pwr_led>;
pwr-led {
label = "pwr-led";
gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwr_btn>;
pwr-btn {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "pwr-btn";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
button-recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <18000>;
};
};
vcc1v8_s0: regulator-vcc1v8-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_sys: regulator-vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_phy: regulator-vcc-phy {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc_phy_en>;
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
vcc3v3_sys: regulator-vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_sys>;
};
vcc5v0_host: regulator-vcc5v0-host {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc3v3_pcie: regulator-vcc3v3-pcie {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_pcie_en>;
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
front_hdmi_5v: regulator-front-hdmi-5v {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&front_hdmi_5v_en>;
regulator-name = "front_hdmi_5v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
otg_vbus: regulator-otg-vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_en>;
regulator-name = "otg_vbus";
regulator-always-on;
regulator-boot-on;
};
vdd_log: regulator-vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
};
virtual_pd: virtual-pd {
compatible = "linux,extcon-usbc-virtual-pd";
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
det-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
vpd-data-role = "display-port";
vpd-super-speed;
};
dp-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "dp-sound";
simple-audio-card,cpu {
// sound-dai = <&i2s2>;
sound-dai = <&spdif>;
};
simple-audio-card,codec {
// sound-dai = <&cdn_dp 0>;
sound-dai = <&cdn_dp 1>;
};
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clock-parents = <&clkin_gmac>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
clock_in_out = "input";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&phy_rst_l>;
phy-handle = <&rtl8211f>;
phy-mode = "rgmii";
phy-supply = <&vcc_phy>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
rtl8211f: ethernet-phy@0 {
reg = <0>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vcca0v9_hdmi>;
avdd-1v8-supply = <&vcca1v8_hdmi>;
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "disabled";
};
&hdmi_sound {
status = "disabled";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_dvp: LDO_REG1 {
regulator-name = "vcc1v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_hdmi: LDO_REG2 {
regulator-name = "vcca1v8_hdmi";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8: LDO_REG3 {
regulator-name = "vcca1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sd: LDO_REG4 {
regulator-name = "vcc_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v0_sd: LDO_REG5 {
regulator-name = "vcc3v0_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca0v9_hdmi: LDO_REG7 {
regulator-name = "vcca0v9_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s3: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel1_pin>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel2_pin>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c4 {
status = "okay";
i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <300>;
pt7c4563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-output-names = "rtc_xin32k";
wakeup-source;
interrupt-parent = <&gpio0>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&rtc_int>;
pinctrl-names = "default";
};
};
&i2s2 {
status = "okay";
};
&io_domains {
bt656-supply = <&vcc1v8_s0>;
audio-supply = <&vcc1v8_s0>;
sdmmc-supply = <&vcc_sd>;
gpio1830-supply = <&vcc_3v0>;
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-0 = <&pcie_clkreqn>;
pinctrl-names = "default";
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pinctrl {
buttons {
pwr_btn: pwr-btn {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
display {
dp_hpd: dp-hpd {
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_input_pull_up>;
};
front_hdmi_5v_en: front-hdmi-5v-en {
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gmac {
phy_rst_l: phy-rst-l {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc_phy_en: vcc-phy-en {
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
pwr_led: pwr-led {
rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_clkreqn: pci-clkreqn {
rockchip,pins = <2 RK_PD2 2 &pcfg_pull_none>;
};
vcc3v3_pcie_en: vcc3v3-pcie-en {
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
rtc {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-hots-en {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
otg_vbus_en: otg-vbus-en {
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmu1830-supply = <&vcc_1v8>;
status = "okay";
};
&pwm2 {
status = "okay";
};
&saradc {
vref-supply = <&vcca1v8>;
status = "okay";
};
&sdhci {
max-frequency = <150000000>;
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&spdif {
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
vqmmc-supply = <&vcc_sd>;
sd-uhs-sdr104;
status = "okay";
};
&cdn_dp {
phys = <&tcphy0_dp>;
extcon = <&virtual_pd>;
status = "okay";
};
&tcphy0 {
extcon = <&virtual_pd>;
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
dr_mode = "host";
status = "okay";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
&vopl_out_dp {
status = "disabled";
};
&dp_in_vopl {
status = "disabled";
};
&vopb_out_hdmi {
status = "disabled";
};
&hdmi_in_vopb {
status = "disabled";
};

87
patch/kernel/rockchip64-6.14/dt/rk3399-nanopi-m4v2.dts
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@ -1,87 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* FriendlyElec NanoPi M4V2 board device tree source
*
* Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*
* Copyright (c) 2018 Collabora Ltd.
* Copyright (c) 2019 Arm Ltd.
*/
/dts-v1/;
#include "rk3399-nanopi4.dtsi"
/ {
model = "FriendlyElec NanoPi M4 Ver2.0";
compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
vdd_5v: vdd-5v {
compatible = "regulator-fixed";
regulator-name = "vdd_5v";
regulator-always-on;
regulator-boot-on;
};
vcc5v0_core: vcc5v0-core {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_core";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_5v>;
};
vcc5v0_usb1: vcc5v0-usb1 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb1";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb2: vcc5v0-usb2 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb2";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-init-microvolt = <900000>;
vin-supply = <&vcc5v0_core>;
};
};
&gmac {
rx_delay = <0x16>;
};
&rk808 {
max-buck-steps-per-change = <4>;
};
&vcc3v3_sys {
vin-supply = <&vcc5v0_core>;
};
&u2phy0_host {
phy-supply = <&vcc5v0_usb1>;
};
&u2phy1_host {
phy-supply = <&vcc5v0_usb2>;
};
&vbus_typec {
regulator-always-on;
vin-supply = <&vdd_5v>;
};

17
patch/kernel/rockchip64-6.14/dt/rk3399-nanopi-r4se.dts
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@ -1,17 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3399-nanopi-r4s.dts"
/ {
model = "FriendlyElec NanoPi R4SE";
compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
};
&emmc_phy {
status = "okay";
};
&sdhci {
status = "okay";
};

1333
patch/kernel/rockchip64-6.14/dt/rk3399-orangepi-4-lts.dts
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1193
patch/kernel/rockchip64-6.14/dt/rk3399-orangepi-4.dts
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1
patch/kernel/rockchip64-6.14/dt/rk3399-rock-pi-4.dts
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@ -1 +0,0 @@
#include "rk3399-rock-pi-4b.dts"

751
patch/kernel/rockchip64-6.14/dt/rk3399-tinker-2.dts
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@ -1,751 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2021 Thomas McKahan
*/
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "rk3399.dtsi"
#include "rk3399-op1.dtsi"
/ {
model = "Asus Tinker Board 2/2S";
compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
chosen {
stdout-path = "serial2:1500000n8";
};
board_info: board-info {
compatible = "board-info";
hw-id0 = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
hw-id1 = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
hw-id2 = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
pid-id0 = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
pid-id1 = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
pid-id2 = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
ddr-id1 = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
ddr-id2 = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
pmic-reset = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
gpio-leds {
compatible = "gpio-leds";
pwr-led {
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
retain-state-suspended = <1>;
};
act-led {
gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
linux,default-trigger="mmc0";
};
rsv-led {
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
linux,default-trigger="heartbeat";
};
};
vcc_lcd: vcc-lcd {
compatible = "regulator-fixed";
regulator-name = "vcc_lcd";
gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
startup-delay-us = <20000>;
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
vbus_typec: vbus-5vout {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en_pin>;
regulator-name = "vbus_5vout";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
/* for rockchip boot on */
rockchip,pwm_id= <2>;
rockchip,pwm_voltage = <900000>;
};
xin32k: xin32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xin32k";
#clock-cells = <0>;
};
};
&cdn_dp {
status = "okay";
extcon = <&fusb0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&cru SCLK_MAC>;
clock_in_out = "input";
assigned-clock-rates = <125000000>;
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 16000 72000>;
tx_delay = <0x25>;
rx_delay = <0x20>;
wakeup-enable = "0";
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc1v8_pmu>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc3v3_dsi: LDO_REG1 {
regulator-name = "vcc3v3_dsi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_hdmi: LDO_REG2 {
regulator-name = "vcca1v8_hdmi";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG3 {
regulator-name = "vcc1v8_pmu";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vccio_sd: LDO_REG4 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_csi: LDO_REG5 {
regulator-name = "vcc3v3_csi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca0v9_hdmi: LDO_REG7 {
regulator-name = "vcca0v9_hdmi";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: vdd_cpu_b@60 {
compatible = "fcs,fan53200";
reg = <0x60>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "fan53555-regulator";
pinctrl-names = "default";
pinctrl-0 = <&vsel1_gpio>;
vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-ramp-delay = <1000>;
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
status = "okay";
regulator-initial-state = <3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
i2c-scl-rising-time-ns = <475>;
i2c-scl-falling-time-ns = <26>;
fusb0: fusb30x@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
vbus-supply = <&vbus_typec>;
status = "okay";
connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <1000000>;
power-role = "dual";
sink-pdos =
<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
extcon-cables = <1 2 5 6 9 10 12 44>;
typec-altmodes = <0xff01 1 0x001c0000 1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc_hs: endpoint {
remote-endpoint =
<&u2phy0_typec_hs>;
};
};
port@1 {
reg = <1>;
usbc_ss: endpoint {
remote-endpoint =
<&tcphy0_typec_ss>;
};
};
port@2 {
reg = <2>;
usbc_dp: endpoint {
remote-endpoint =
<&tcphy0_typec_dp>;
};
};
};
};
};
vdd_gpu: vdd_gpu@60 {
compatible = "fcs,fan53200";
reg = <0x60>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "fan53555-regulator";
pinctrl-names = "default";
pinctrl-0 = <&vsel2_gpio>;
vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1200000>;
regulator-ramp-delay = <1000>;
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
status = "okay";
regulator-initial-state = <3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c8 {
m24c08: m24c08@50 {
compatible = "atmel,24c08";
reg = <0x50>;
};
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
status = "okay";
};
&i2s2 {
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
};
&pwm0 {
status = "disabled";
};
&pwm2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin_pull_down>;
};
&pwm3 {
status = "disabled";
};
&saradc {
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
supports-emmc;
//mmc-hs400-enhanced-strobe;
non-removable;
keep-power-in-suspend;
status = "okay";
};
&sdmmc {
clock-frequency = <150000000>;
clock-freq-min-max = <100000 150000000>;
supports-sd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
num-slots = <1>;
//sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_s3>;
vqmmc-supply = <&vccio_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
status = "okay";
};
&tcphy0 {
extcon = <&fusb0>;
status = "okay";
};
&tcphy0_dp {
port {
tcphy0_typec_dp: endpoint {
remote-endpoint = <&usbc_dp>;
};
};
};
&tcphy0_usb3 {
port {
tcphy0_typec_ss: endpoint {
remote-endpoint = <&usbc_ss>;
};
};
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
port {
u2phy0_typec_hs: endpoint {
remote-endpoint = <&usbc_hs>;
};
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "host";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 18 RK_FUNC_GPIO &pcfg_pull_up>,
<0 9 RK_FUNC_GPIO &pcfg_pull_none>; /* GPIO0_B1 */
};
vsel1_gpio: vsel1-gpio {
rockchip,pins =
<1 17 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {
rockchip,pins =
<1 14 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins =
<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
fusb30x {
fusb0_int: fusb0-int {
rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};

773
patch/kernel/rockchip64-6.14/dt/rk3399-xiaobao-nas.dts
View File

@ -1,773 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "rk3399.dtsi"
/ {
model = "Codinge Xiaobao NAS";
compatible = "codinge,xiaobao-nas", "rockchip,rk3399";
aliases {
mmc0 = &sdmmc;
mmc1 = &sdhci;
mmc2 = &sdio0;
};
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc_dc: vcc-dc {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
};
vcc_12v: vcc-12v {
compatible = "regulator-fixed";
regulator-name = "vcc_12v";
regulator-always-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
};
vcc_sd: vcc-sd {
compatible = "regulator-fixed";
regulator-name = "vcc_sd";
enable-active-high;
gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc_sd_h>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc5v0_typec: vcc5v0-typec {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vcc5v0_typec";
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_12v>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
enable-active-high;
gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwr_en>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
vcc_lan: vcc3v3-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_lan";
regulator-always-on;
regulator-boot-on;
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
recovery {
label = "Recovery";
linux,code = <0x168>;
press-threshold-microvolt = <18000>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins>;
led1: system-led1 {
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
label = "system_led1";
retain-state-suspended;
default-state = "on";
};
led2: system-led2 {
gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
label = "system_led2";
retain-state-suspended;
default-state = "off";
};
};
pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm1 0 50000 0>;
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
ddc-i2c-scl-high-time-ns = <9625>;
ddc-i2c-scl-low-time-ns = <10000>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_3v0>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_dvp: LDO_REG1 {
regulator-name = "vcc1v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca_1v8: LDO_REG2 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_pmupll: LDO_REG3 {
regulator-name = "vcc1v8_pmupll";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-name = "vcca3v0_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca1v8_codec: LDO_REG7 {
regulator-name = "vcca1v8_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel1_pin>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel2_pin>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <160>;
i2c-scl-falling-time-ns = <30>;
status = "okay";
typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
vbus-supply = <&vcc5v0_typec>;
};
};
&i2s0 {
rockchip,capture-channels = <8>;
rockchip,playback-channels = <8>;
status = "okay";
};
&i2s1 {
rockchip,capture-channels = <2>;
rockchip,playback-channels = <2>;
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
status = "okay";
bt656-supply = <&vcc_3v0>;
audio-supply = <&vcca1v8_codec>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
&pcie_phy {
status = "okay";
drive-impedance-ohm = <50>;
};
&pcie0 {
ep-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqnb_cpm &fn8274_en_h>;
status = "okay";
};
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&vcc_3v0>;
};
&pinctrl {
pcie {
fn8274_en_h: fn8274-en-h {
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>,
<4 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>,
<1 RK_PC7 RK_FUNC_GPIO &pcfg_output_high>;
};
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_typec_en: vcc5v0-typec-en {
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
};
};
vcc_sd {
vcc_sd_h: vcc-sd-h {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
fusb30x {
fusb0_int: fusb0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
leds_pins: leds-pins {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm1 {
status = "okay";
};
&saradc {
status = "okay";
};
&sdio0 {
bus-width = <4>;
clock-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x00>;
spi-max-frequency = <10000000>;
};
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
status = "okay";
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&u2phy0_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_otg {
status = "okay";
};
&u2phy1_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "host";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

796
patch/kernel/rockchip64-6.14/dt/rk3566-h96-tvbox.dts
View File

@ -1,796 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 hqnicolas <hqnicolas@msn.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
/ {
model = "h96 TVbox 3566";
compatible = "h96-TVbox,rk3566", "rockchip,rk3566";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdmmc0;
mmc1 = &sdhci;
mmc2 = &sdmmc1;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
vcc5v0_in: vcc5v0_in {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_in";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac1_clkin";
#clock-cells = <0>;
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_receiver_pin>;
linux,rc-map-name = "rc-h96-max-v56";
};
fddis_dev {
compatible = "fddis_dev";
fddis_gpio_clk = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
fddis_gpio_dat = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&dis_ctl_clk &dis_ctl_dat>;
status = "okay";
};
spdif_dit: spdif-dit {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
spdif_sound: spdif-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_dit>;
};
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: vcc5v0_sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_in>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
enable-active-high;
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_otg: vcc5v0-otg-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_otg";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_otg_en>;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_enable_h>;
regulator-name = "vcc3v3_pcie_p";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3>;
};
leds {
compatible = "gpio-leds";
led_status: led-status {
label = "led-status";
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&led_status_enable_h>;
};
led_power: led-power {
label = "led-power";
gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
pinctrl-names = "default";
pinctrl-0 = <&led_power_enable_h>;
};
};
vbus: vbus-regulator {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
sdio_pwrseq: sdio-pwrseq {
status = "okay";
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
post-power-on-delay-ms = <100>;
};
rk809_sound: rk809-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rk809-codec";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809_codec>;
};
};
rk_headset: rk-headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
io-channels = <&saradc 2>; //HP_HOOK pin
};
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
clock_in_out = "input";
phy-supply = <&vcc_3v3>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m0_miim
&gmac1m0_tx_bus2
&gmac1m0_rx_bus2
&gmac1m0_rgmii_clk
&gmac1m0_clkinout
&gmac1m0_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f, also works well here */
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x41>;
rx_delay = <0x2e>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&hdmi {
assigned-clocks = <&cru CLK_HDMI_CEC>;
assigned-clock-rates = <32768>;
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
#sound-dai-cells = <0>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_npu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
rk809_codec: codec {
mic-in-differential;
};
};
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx
&i2s1m0_sdi0
&i2s1m0_sdo0>;
rockchip,trcm-sync-tx-only;
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
status = "okay";
};
};
&pcie2x1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_h>;
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie_p>;
status = "disabled";
};
&pinctrl {
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_otg_en: vcc5v0-otg-en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_enable_h: pcie-enable-h {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_reset_h: pcie-reset-h {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
ir-receiver {
ir_receiver_pin: ir-receiver-pin {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
led_status_enable_h: led-status-enable-h {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_power_enable_h: led_power_enable_h {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
fddis_ctr {
dis_ctl_clk: dis-ctl-clk {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
dis_ctl_dat: dis-ctl-dat {
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sata2 {
status = "disabled";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sdmmc1 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
disable-wp;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
sd-uhs-sdr50;
supports-sdio;
status = "okay";
vmmc-supply = <&vcc3v3_sys>;
vqmmc-supply = <&vcca1v8_pmu>;
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
};
};
&tsadc {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
dma-names = "tx", "rx";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
status = "okay";
uart-has-rtscts;
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk809 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
max-speed = <3000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcca1v8_pmu>;
};
};
&uart2 {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
status = "okay";
};
&usb2phy0_otg {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
status = "okay";
};
&usb2phy1_otg {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vpu {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

579
patch/kernel/rockchip64-6.14/dt/rk3566-jp-tvbox.dts
View File

@ -1,579 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 tdleiyao <tdleiyao@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
/ {
model = "JP TVbox 3566";
compatible = "JP-TVbox,rk3566", "rockchip,rk3566";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdhci;
mmc1 = &sdmmc1;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac1_clkin";
#clock-cells = <0>;
};
leds {
compatible = "gpio-leds";
led_status: led-status {
label = "led-status";
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&led_status_enable_h>;
};
};
vbus: vbus-regulator {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vbus>;
};
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
sdio_pwrseq: sdio-pwrseq {
status = "okay";
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
post-power-on-delay-ms = <100>;
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6398s";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
clock_in_out = "input";
phy-supply = <&vcc_3v3>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m0_miim
&gmac1m0_tx_bus2
&gmac1m0_rx_bus2
&gmac1m0_rgmii_clk
&gmac1m0_clkinout
&gmac1m0_rgmii_bus>;
snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f, also works well here */
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x41>;
rx_delay = <0x2e>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
status = "okay";
};
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_npu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
led_status_enable_h: led-status-enable-h {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sata2 {
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc1 {
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
non-removable;
mmc-pwrseq = <&sdio_pwrseq>;
status = "okay";
};
&tsadc {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk809 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
max-speed = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcca1v8_pmu>;
};
};
&uart2 {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
status = "okay";
};
&usb2phy0_otg {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
status = "okay";
};
&usb2phy1_otg {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

579
patch/kernel/rockchip64-6.14/dt/rk3566-panther-x2.dts
View File

@ -1,579 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 tdleiyao <tdleiyao@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3566.dtsi"
/ {
model = "Panther X2";
compatible = "panther,x2", "rockchip,rk3566";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdmmc0;
mmc1 = &sdhci;
mmc2 = &sdmmc1;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac1_clkin";
#clock-cells = <0>;
};
leds {
compatible = "gpio-leds";
//Corresponds to the actual order
led_pwr: led-pwr {
label = "led-pwr";
default-state = "on";
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&led_pwr_enable_h>;
retain-state-suspended;
status = "okay";
};
led_wifi: led-wifi {
label = "led-wifi";
default-state = "off";
gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&led_wifi_enable_h>;
retain-state-suspended;
status = "okay";
};
led_eth: led-eth {
label = "led-eth";
default-state = "off";
gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&led_eth_enable_h>;
retain-state-suspended;
status = "okay";
};
led_status: led-status {
label = "led-status";
default-state = "on";
gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&led_status_enable_h>;
retain-state-suspended;
status = "okay";
};
};
vbus: vbus-regulator {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vbus>;
};
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
sdio_pwrseq: sdio-pwrseq {
status = "okay";
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
post-power-on-delay-ms = <100>;
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6236";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
clock_in_out = "input";
phy-supply = <&vcc_3v3>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m0_miim
&gmac1m0_tx_bus2
&gmac1m0_rx_bus2
&gmac1m0_rgmii_clk
&gmac1m0_clkinout
&gmac1m0_rgmii_bus>;
snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f, also works well here */
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x30>;
rx_delay = <0x10>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
status = "okay";
};
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_npu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdda0v9_image: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_image";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdda_0v9: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pmu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_image: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
status = "disabled";
regulator-state-mem {
regulator-on-in-suspend;
};
};
};
};
};
&i2s1_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
&i2s1m1_lrcktx &i2s1m1_lrckrx
&i2s1m1_sdi0 &i2s1m1_sdi1
&i2s1m1_sdi2 &i2s1m1_sdi3
&i2s1m1_sdo0 &i2s1m1_sdo1
&i2s1m1_sdo2 &i2s1m1_sdo3>;
status = "disabled";
};
&pinctrl {
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
led_pwr_enable_h: led-pwr-enable-h {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_wifi_enable_h: led-wifi-enable-h {
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_eth_enable_h: led-eth-enable-h {
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_status_enable_h: led-status-enable-h {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vcc_3v3>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_3v3>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc0 {
broken-cd;
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sdmmc1 {
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
non-removable;
mmc-pwrseq = <&sdio_pwrseq>;
status = "okay";
};
&tsadc {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk809 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
max-speed = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcca1v8_pmu>;
};
};
&uart2 {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
status = "okay";
};
&usb2phy0_otg {
status = "okay";
};

21
patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-h66k.dts
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@ -1,21 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
// Copyright (c) 2022 Flippy <flippy@sina.com>
// Copyright (c) 2023 amazingfate <liujianfeng1994@gmail.com>
/dts-v1/;
#include "rk3568-hinlink-h68k.dts"
/ {
model = "HINLINK H66K";
compatible = "hinlink,h66k", "rockchip,rk3568";
};
&gmac0 {
status = "disabled";
};
&gmac1 {
status = "disabled";
};

882
patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-h68k.dts
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@ -1,882 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
// Copyright (c) 2023 amazingfate <liujianfeng1994@gmail.com>
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
/ {
model = "HINLINK H68K";
compatible = "hinlink,h68k", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
mmc0 = &sdhci;
mmc1 = &sdmmc0;
led-boot = &led_work;
led-failsafe = &led_work;
led-running = &led_work;
led-upgrade = &led_work;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&reset_button_pin>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <50>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_net_en>, <&led_sata_en>, <&led_work_en>;
led_net: net {
label = "blue:net";
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
};
led_sata: sata {
label = "amber:sata";
gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
};
led_work: work {
label = "green:work";
gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
};
};
dc_12v: dc-12v-regulator {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
rfkill-bt {
compatible = "rfkill-gpio";
label = "rfkill-m2-bt";
radio-type = "bluetooth";
shutdown-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
};
rfkill-wifi {
compatible = "rfkill-gpio";
label = "rfkill-pcie-wlan";
radio-type = "wlan";
shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_sys_en>;
vin-supply = <&vcc5v0_sys>;
};
/* eth 2.5g power
for H66K H69K
*/
vcc3v3_pcie3: vcc3v3-pcie3-regulator {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pcie3";
regulator-boot-on;
enable-active-high;
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_pcie3_en>;
vin-supply = <&vcc3v3_sys>;
};
vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_otg_en>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_sd_pwren: vcc3v3-sd-pwren-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sd_pwren";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
enable-active-high;
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; /* SD_PWREN */
vin-supply = <&vcc3v3_sys>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_sd_en>;
};
rk809-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "Analog RK809";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809>;
};
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 127 163 255>;
#cooling-cells = <2>;
fan-supply = <&vcc5v0_sys>;
pwms = <&pwm0 0 50000 0>;
};
};
&combphy0 {
status = "okay";
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&cpu_thermal {
trips {
cpu_cool: cpu_cool {
temperature = <45000>;
hysteresis = <2000>;
type = "active";
};
cpu_warm: cpu_warm {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
cpu_hot: cpu_hot {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&cpu_cool>;
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
};
map2 {
trip = <&cpu_warm>;
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
};
map3 {
trip = <&cpu_hot>;
cooling-device = <&fan 3 THERMAL_NO_LIMIT>;
};
};
};
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "input";
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 200000>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "input";
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 200000>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#sound-dai-cells = <0>;
#clock-cells = <1>;
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
pwrkey {
status = "okay";
};
pinctrl_rk8xx: pinctrl_rk8xx {
gpio-controller;
#gpio-cells = <2>;
rk817_slppin_null: rk817_slppin_null {
pins = "gpio_slp";
function = "pin_fun0";
};
rk817_slppin_slp: rk817_slppin_slp {
pins = "gpio_slp";
function = "pin_fun1";
};
rk817_slppin_pwrdn: rk817_slppin_pwrdn {
pins = "gpio_slp";
function = "pin_fun2";
};
rk817_slppin_rst: rk817_slppin_rst {
pins = "gpio_slp";
function = "pin_fun3";
};
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
rk809_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
clocks = <&cru I2S1_MCLKOUT_TX>;
clock-names = "mclk";
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_mclk>;
hp-volume = <20>;
spk-volume = <3>;
mic-in-differential;
status = "okay";
};
};
};
&i2c5 {
status = "okay";
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
rockchip,trcm-sync-tx-only;
status = "okay";
};
&mdio0 {
rgmii_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
phy-supply = <&vcc3v3_sys>;
reg = <0x0>;
};
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
phy-supply = <&vcc3v3_sys>;
reg = <0x0>;
};
};
&pcie2x1 {
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
};
&pcie30phy {
data-lanes = <1 2>;
status = "okay";
};
&pcie3x1 {
num-lanes = <1>;
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie3>;
status = "okay";
pcie@0,0 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_1: pcie-eth@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x0200>;
};
};
};
&pcie3x2 {
num-lanes = <1>;
rockchip,init-delay-ms = <100>;
reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie3>;
status = "okay";
pcie@0,0 {
reg = <0x00200000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_2: pcie-eth@20,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x0200>;
};
};
};
&pinctrl {
button {
reset_button_pin: reset-button-pin {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
led_work_en: led-work-en {
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_sata_en: led-user-en {
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_net_en: led-net-en {
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
vcc {
vcc3v3_sys_en: vcc3v3-sys-en {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic-int {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sd {
vcc3v3_sd_en: vcc3v3-sd_en {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
vcc3v3_pcie3_en: vcc3v3_pcie3_en {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&pwm0 {
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sata0 {
status = "okay";
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
cap-sd-highspeed;
max-frequency = <50000000>;
disable-wp;
vmmc-supply = <&vcc3v3_sd_pwren>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
status = "disabled";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&usb2phy0_otg {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

228
patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-hnas.dts
View File

@ -1,228 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
// Copyright (c) 2022 Flippy <flippy@sina.com>
// Copyright (c) 2023 amazingfate <liujianfeng1994@gmail.com>
/dts-v1/;
#include "rk3568-hinlink-h68k.dts"
/ {
model = "HINLINK HNAS";
compatible = "hinlink,hnas", "rockchip,rk3568";
fan0: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
cooling-levels = <8 39 70 100 131 162 193 224 255>;
pwms = <&pwm0 0 10000 0>;
};
hdd_leds {
led_hdd1: led-hdd1 {
pinctrl-names = "default";
pinctrl-0 = <&led_hdd1_pin>;
label = "led:hdd1";
gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>;
};
led_hdd2: led-hdd2 {
pinctrl-names = "default";
pinctrl-0 = <&led_hdd2_pin>;
label = "led:hdd2";
gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
};
led_hdd3: led-hdd3 {
pinctrl-names = "default";
pinctrl-0 = <&led_hdd3_pin>;
label = "led:hdd3";
gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
};
led_hdd4: led-hdd4 {
pinctrl-names = "default";
pinctrl-0 = <&led_hdd4_pin>;
label = "led:hdd4";
gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
};
};
sata_pm_power: sata-pm-power {
compatible = "regulator-fixed";
regulator-name = "sata_pm_power";
regulator-enable-ramp-delay = <1000000>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sata_pm_power_en>;
vin-supply = <&vcc3v3_sys>;
};
sata_pm_reset: sata-pm-reset {
compatible = "regulator-fixed";
regulator-name = "sata_pm_reset";
regulator-enable-ramp-delay = <1000000>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sata_pm_reset_en>;
vin-supply = <&vcc3v3_sys>;
};
sata_hdd_power: sata-hdd-power {
compatible = "regulator-fixed";
regulator-name = "sata_hdd_power";
regulator-enable-ramp-delay = <1000000>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sata_hdd_power_en>;
vin-supply = <&vcc5v0_sys>;
};
};
&gmac0 {
status = "disabled";
};
&gmac1 {
status = "disabled";
};
&pinctrl {
hdd-leds {
led_hdd1_pin: led-hdd1-pin {
rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_hdd2_pin: led-hdd2-pin {
rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_hdd3_pin: led-hdd3-pin {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_hdd4_pin: led-hdd4-pin {
rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sata-pm {
sata_pm_power_en: sata-pm-power-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
sata_pm_reset_en: sata-pm-reset-en {
rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
};
sata_hdd_power_en: sata-hdd-power-en {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&pwm0 {
status = "okay";
};
&cpu_thermal {
trips {
trip0: trip-point@0 {
temperature = <45000>;
hysteresis = <5000>;
type = "active";
};
trip1: trip-point@1 {
temperature = <50000>;
hysteresis = <5000>;
type = "active";
};
trip2: trip-point@2 {
temperature = <55000>;
hysteresis = <5000>;
type = "active";
};
trip3: trip-point@3 {
temperature = <60000>;
hysteresis = <5000>;
type = "active";
};
trip4: trip-point@4 {
temperature = <65000>;
hysteresis = <5000>;
type = "active";
};
trip5: trip-point@5 {
temperature = <70000>;
hysteresis = <5000>;
type = "active";
};
trip6: trip-point@6 {
temperature = <75000>;
hysteresis = <5000>;
type = "active";
};
trip7: trip-point@7 {
temperature = <80000>;
hysteresis = <1000>;
type = "active";
};
};
cooling-maps {
map0 {
trip = <&trip0>;
cooling-device = <&fan0 0 1>;
contribution = <1024>;
};
map1 {
trip = <&trip1>;
cooling-device = <&fan0 1 2>;
contribution = <1024>;
};
map2 {
trip = <&trip2>;
cooling-device = <&fan0 2 3>;
contribution = <1024>;
};
map3 {
trip = <&trip3>;
cooling-device = <&fan0 3 4>;
contribution = <1024>;
};
map4 {
trip = <&trip4>;
cooling-device = <&fan0 4 5>;
contribution = <1024>;
};
map5 {
trip = <&trip5>;
cooling-device = <&fan0 5 6>;
contribution = <1024>;
};
map6 {
trip = <&trip6>;
cooling-device = <&fan0 6 7>;
contribution = <1024>;
};
map7 {
trip = <&trip7>;
cooling-device = <&fan0 7 8>;
contribution = <1024>;
};
};
};

767
patch/kernel/rockchip64-6.14/dt/rk3568-mixtile-edge2.dts
View File

@ -1,767 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Focalcrest Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
/ {
model = "Mixtile Edge 2";
compatible = "focalcrest,mixtile-edge2", "rockchip,rk3568";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc2;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
work_led: work {
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
rk809-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "Analog RK809";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809>;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
post-power-on-delay-ms = <200>;
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb_hub: vcc5v0-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb_hub";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_hub_en>;
gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb_host: vcc5v0-usb-host {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_host_en>;
regulator-name = "vcc5v0_usb_host";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc3v3_pcie: vcc3v3-pcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_pcie_en_pin>;
gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
};
vcc3v3_m2: vcc3v3-m2 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_m2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
};
vcc1v8_m2: vcc1v8-m2 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_m2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
pinctrl-names = "default";
pinctrl-0 = <&vcc1v8_m2_pin>;
gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>;
};
vcc3v3_minipcie: vcc3v3-minipcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_minipcie";
regulator-always-on;
regulator-boot-on;
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
};
};
&combphy0 {
status = "okay";
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>,<&cru CLK_MAC1_2TOP>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
system-power-controller;
#sound-dai-cells = <0>;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
wakeup-source;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
codec {
mic-in-differential;
};
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4m1_xfer>;
status = "disabled";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3m0_xfer>;
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
clock-output-names = "rtcic_32kout";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
wakeup-source;
};
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
rockchip,trcm-sync-tx-only;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
&pcie30phy {
status = "okay";
};
&pcie3x2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie30x2m1_pins>;
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pinctrl {
ethernet {
eth_phy_rst: eth_phy_rst {
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
bt {
bt_enable: bt-enable {
rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake: bt-host-wake {
rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
};
bt_wake: bt-wake {
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
vcc1v8-m2-pin {
vcc1v8_m2_pin: vcc1v8-m2-pin {
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
sd-uhs-sdr50;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sdmmc2 {
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
sd-uhs-sdr50;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4m1_xfer>;
};
&uart8 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk809 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
/* vddio comes from regulator on module, use IO bank voltage instead */
};
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
extcon = <&usb2phy0>;
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy0_otg {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

718
patch/kernel/rockchip64-6.14/dt/rk3568-yy3568.dts
View File

@ -1,718 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
/ {
model = "Youyeetoo YY3568";
compatible = "youyeetoo,yy3568", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
mmc2 = &sdmmc2;
mmc1 = &sdmmc0;
mmc0 = &sdhci;
};
gpio-leds {
compatible = "gpio-leds";
led_user: led-0 {
gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&led_user_en>;
};
led_power: led-1 {
gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&led_power_en>;
};
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
rk809-sound {
compatible = "simple-audio-card";
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
hp-det-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
simple-audio-card,format = "i2s";
simple-audio-card,name = "Analog RK809";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809>;
};
};
vcc5v0_otg: regulator-vbus-typec {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_otg_en>;
regulator-name = "vcc5v0_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
/* actually fed by vcc5v0_sys, dependent
* on pi6c clock generator
*/
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_pcie30x1: regulator-vcc3v3-pcie30x1 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie30x1_enable_h>;
regulator-name = "vcc3v3_pcie30x1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_enable_h>;
regulator-name = "vcc3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
pcie30_avdd0v9: regulator-pcie30-avdd0v9 {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc3v3_sys>;
};
pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc3v3_sys>;
};
vcc3v3_sys: regulator-vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc12v_input>;
};
vcc5v0_sys: regulator-vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_input>;
};
/* labeled +12v_input in schematic */
vcc12v_input: regulator-vcc5v-input {
compatible = "regulator-fixed";
regulator-name = "vcc12v_input";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
};
&combphy1 {
phy-supply = <&vcc3v3_pcie30x1>;
status = "okay";
};
&combphy0 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};
&hdmi {
assigned-clocks = <&cru CLK_HDMI_CEC>;
assigned-clock-rates = <32768>;
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&pcie2x1 {
pinctrl-names = "default";
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
status = "okay";
};
&pcie30phy {
data-lanes = <1 2>;
status = "okay";
};
&pcie3x2 {
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pcie30x2_reset_h>;
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc12v_input>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&pinctrl {
leds {
led_user_en: led_user_en {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_power_en: led_power_en {
rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pcie {
pcie30x1_enable_h: pcie30x1-enable-h {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie30x2_reset_h: pcie30x2-reset-h {
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_enable_h: pcie-enable-h {
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_otg_en: vcc5v0_otg_en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&i2s1_8ch {
rockchip,trcm-sync-tx-only;
status = "okay";
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
/* Also used in pcie30x1_clkreqnm0 */
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sdmmc2 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>;
sd-uhs-sdr104;
status = "okay";
};
&mdio0 {
rgmii_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916";
reg = <0x0>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
};
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916";
reg = <0x0>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
};
};
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
status = "okay";
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
extcon = <&usb2phy0>;
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_host>;
status = "okay";
};

10
patch/kernel/rockchip64-6.14/dt/rk3588-bananapi-m7.dts
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@ -1,10 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3588-armsom-sige7.dts"
/ {
model = "Banana Pi M7";
compatible = "bananapi,m7", "rockchip,rk3588";
};

1099
patch/kernel/rockchip64-6.14/dt/rk3588-cyber-aib.dts
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File diff suppressed because it is too large Load Diff

973
patch/kernel/rockchip64-6.14/dt/rk3588-hinlink-h88k.dts
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@ -1,973 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588.dtsi"
/ {
model = "HINLINK H88K";
compatible = "hinlink,h88k", "rockchip,rk3588";
aliases {
ethernet0 = &gmac0;
mmc0 = &sdhci;
mmc1 = &sdmmc;
mmc2 = &sdio;
};
analog-sound {
compatible = "simple-audio-card";
label = "rockchip,es8388-codec";
pinctrl-names = "default";
pinctrl-0 = <&hp_detect>;
simple-audio-card,name = "Analog";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
simple-audio-card,bitclock-master = <&daicpu>;
simple-audio-card,frame-master = <&daicpu>;
simple-audio-card,widgets =
"Microphone", "Onboard Microphone",
"Microphone", "Microphone Jack",
"Speaker", "Speaker",
"Headphone", "Headphones";
simple-audio-card,routing =
"Headphones", "LOUT1",
"Headphones", "ROUT1",
"Speaker", "LOUT2",
"Speaker", "ROUT2",
/* single ended signal to LINPUT1 */
"LINPUT1", "Microphone Jack",
"RINPUT1", "Microphone Jack",
/* differential signal */
"LINPUT2", "Onboard Microphone",
"RINPUT2", "Onboard Microphone";
daicpu: simple-audio-card,cpu {
sound-dai = <&i2s0_8ch>;
system-clock-frequency = <12288000>;
};
daicodec: simple-audio-card,codec {
sound-dai = <&es8388>;
system-clock-frequency = <12288000>;
};
};
chosen {
stdout-path = "serial2:1500000n8";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_net_en>, <&led_sata_en>,
<&led_user_en>, <&led_work_en>;
net {
label = "blue:net";
gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>;
};
sata {
label = "amber:sata";
gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
};
user {
label = "green:user";
gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
};
work {
label = "red:work";
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
hdmi0-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con_in: endpoint {
remote-endpoint = <&hdmi0_out_con>;
};
};
};
hdmi1-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi1_con_in: endpoint {
remote-endpoint = <&hdmi1_out_con>;
};
};
};
rfkilli-wifi {
compatible = "rfkill-gpio";
label = "rfkill-pcie-wlan";
radio-type = "wlan";
shutdown-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
};
rfkill-bt {
compatible = "rfkill-gpio";
label = "rfkill-m2-bt";
radio-type = "bluetooth";
shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-name = "vcc12v_dcin";
};
vcc3v3_pcie30: vcc3v3-pcie30-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc3v3_pcie30";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <5000>;
vin-supply = <&vcc12v_dcin>;
};
/* it's modem reset pin */
modem_enable: modem-enable {
compatible = "regulator-fixed";
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "modem-enable";
vin-supply = <&vcc_3v3_s3>;
startup-delay-us = <500000>;
pinctrl-names = "default";
pintctrl-0 = <&modem_reset_en>;
};
vcc3v3_modem: vcc3v3-modem {
compatible = "regulator-fixed";
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_modem";
pinctrl-names = "default";
pintctrl-0 = <&modem_power_en>;
vin-supply = <&vcc_3v3_s3>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb_hub: vcc5v0-usb-hub {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_hub_en>;
regulator-name = "vcc5v0_usb_hub";
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc5v0_sys>;
};
};
&combphy0_ps {
status = "okay";
};
&combphy1_ps {
status = "okay";
};
&combphy2_psu {
status = "okay";
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy>;
phy-mode = "rgmii-rxid";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
pinctrl-names = "default";
rx_delay = <0x00>;
tx_delay = <0x43>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu_s0>;
status = "okay";
};
&hdmi0 {
status = "okay";
};
&hdptxphy0 {
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
&hdmi0_out {
hdmi0_out_con: endpoint {
remote-endpoint = <&hdmi0_con_in>;
};
};
&hdmi1 {
status = "okay";
};
&hdmi1_in {
hdmi1_in_vp1: endpoint {
remote-endpoint = <&vp1_out_hdmi1>;
};
};
&hdmi1_out {
hdmi1_out_con: endpoint {
remote-endpoint = <&hdmi1_con_in>;
};
};
&hdptxphy1 {
status = "okay";
};
&hdmi_receiver_cma {
status = "okay";
};
&hdmi_receiver {
status = "okay";
hpd-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
pinctrl-names = "default";
memory-region = <&hdmi_receiver_cma>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
status = "okay";
vdd_cpu_big0_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big0_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big1_s0: regulator@43 {
compatible = "rockchip,rk8603", "rockchip,rk8602";
reg = <0x43>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big1_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c2 {
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&i2c7 {
status = "okay";
es8388: audio-codec@11 {
compatible = "everest,es8388";
reg = <0x11>;
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>;
AVDD-supply = <&vcc_3v3_s3>;
clocks = <&cru I2S0_8CH_MCLKOUT>;
DVDD-supply = <&vcc_1v8_s3>;
HPVDD-supply = <&vcc_3v3_s3>;
PVDD-supply = <&vcc_1v8_s3>;
#sound-dai-cells = <0>;
};
};
&i2s0_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s0_lrck
&i2s0_mclk
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
status = "okay";
};
&mdio0 {
rgmii_phy: ethernet-phy@1 {
/* RTL8211F */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
};
};
&pcie2x1l0 {
reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie2x1l1 {
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie2x1l2 {
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie30phy {
status = "okay";
};
&pcie3x4 {
pinctrl-names = "default";
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
status = "okay";
};
&pinctrl {
hdmirx {
hdmirx_hpd: hdmirx-hpd {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
led_net_en: led_net_en {
rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_sata_en: led_sata_en {
rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_user_en: led_user_en {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_work_en: led_work_en {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
modem {
modem_power_en: modem-power-en {
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
modem_reset_en: modem-reset-en {
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
rtl8211f {
rtl8211f_rst: rtl8211f-rst {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sound {
hp_detect: hp-detect {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay";
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
no-sdio;
no-sd;
non-removable;
status = "okay";
};
&sdmmc {
max-frequency = <150000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
sd-uhs-sdr104;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vcc_3v3_s3>;
vqmmc-supply = <&vccio_sd_s0>;
status = "okay";
};
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
num-cs = <1>;
pmic@0 {
compatible = "rockchip,rk806";
spi-max-frequency = <1000000>;
reg = <0x0>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc5v0_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc5v0_sys>;
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
gpio-controller;
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
rk806_dvs2_null: dvs2-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_dvs3_null: dvs3-null-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun0";
};
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_log_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_ddr_s0: dcdc-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
vdd2_ddr_s3: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_2v0_pldo_s3: dcdc-reg7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2000000>;
};
};
vcc_3v3_s3: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vddq_ddr_s0: dcdc-reg9 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s3: dcdc-reg10 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avcc_1v8_s0: pldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s0: pldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avdd_1v2_s0: pldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3_s0: pldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd_s0: pldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
pldo6_s3: pldo-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_0v75_s3: nldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_ddr_pll_s0: nldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
avdd_0v75_s0: nldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "avdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v85_s0: nldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v75_s0: nldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&tsadc {
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_otg {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy2 {
status = "okay";
};
&u2phy2_host {
/* connected to USB hub, which is powered by vcc5v0_sys */
phy-supply = <&vcc5v0_sys>;
status = "okay";
};
&u2phy3 {
status = "okay";
};
&u2phy3_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&usbdp_phy1 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
dr_mode = "host";
status = "okay";
};
&usb_host2_xhci {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi0_in_vp0>;
};
};
&vp1 {
vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
reg = <ROCKCHIP_VOP2_EP_HDMI1>;
remote-endpoint = <&hdmi1_in_vp1>;
};
};

712
patch/kernel/rockchip64-6.14/dt/rk3588-mixtile-blade3.dts
View File

@ -1,712 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3588.dtsi"
/ {
model = "Mixtile Blade 3";
compatible = "mixtile,blade3", "rockchip,rk3588";
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:1500000n8";
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usbdcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usbdcin>;
};
pcie20_avdd0v85: pcie20-avdd0v85-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie20_avdd0v85";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
vin-supply = <&vdd_0v85_s0>;
};
pcie20_avdd1v8: pcie20-avdd1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie20_avdd1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
};
pcie30_avdd0v75: pcie30-avdd0v75-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd0v75";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
vin-supply = <&avdd_0v75_s0>;
};
pcie30_avdd1v8: pcie30-avdd1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
};
vcc3v3_pcie30: vcc3v3-pcie30-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie30";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
startup-delay-us = <5000>;
vin-supply = <&vcc12v_dcin>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3_vcc3v3_en>;
};
vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sd_s0";
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
enable-active-high;
};
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc5v0_sys>;
};
};
&combphy0_ps {
status = "okay";
};
&combphy1_ps {
status = "okay";
};
&combphy2_psu {
status = "okay";
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
mem-supply = <&vdd_cpu_big0_mem_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
mem-supply = <&vdd_cpu_big0_mem_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
mem-supply = <&vdd_cpu_big1_mem_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
mem-supply = <&vdd_cpu_big1_mem_s0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
status = "okay";
vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big0_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 {
compatible = "rockchip,rk8603", "rockchip,rk8602";
reg = <0x43>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big1_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1m2_xfer>;
status = "okay";
vdd_npu_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c4 {
pinctrl-0 = <&i2c4m0_xfer>;
status = "okay";
};
/* exposed on the 30-pin connector; shows up as i2c-3 */
&i2c5 {
pinctrl-0 = <&i2c5m3_xfer>;
status = "okay";
};
&i2s2_2ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s2m1_mclk
&i2s2m1_lrck
&i2s2m1_sclk
&i2s2m1_sdi
&i2s2m1_sdo>;
status = "okay";
};
&pcie2x1l0 {
reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_0_rst>;
status = "okay";
};
&pcie2x1l1 {
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_1_rst>;
status = "okay";
};
&pcie30phy {
status = "okay";
};
&pcie3x4 {
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3_rst>;
status = "okay";
};
&pinctrl {
sdmmc {
sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pcie2 {
pcie2_0_rst: pcie2-0-rst {
rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie2_1_rst: pcie2-1-rst {
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie3 {
pcie3_rst: pcie3-rst {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie3_vcc3v3_en: pcie3-vcc3v3-en {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm8 {
pinctrl-names = "active";
pinctrl-0 = <&pwm8m2_pins>;
status = "okay";
};
&pwm14 {
pinctrl-0 = <&pwm14m2_pins>;
status = "okay";
};
&pwm15 {
pinctrl-0 = <&pwm15m3_pins>;
status = "disabled";
};
&spi4 {
pinctrl-names = "default";
pinctrl-0 = <&spi4m2_cs0 &spi4m2_pins>;
num-cs = <1>;
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcc_1v8_s0>;
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
max-frequency = <200000000>;
// hs400 causes immediate trouble, hs200 works at around 150mb/s
// mmc-hs400-1_8v;
// mmc-hs400-enhanced-strobe;
mmc-hs200-1_8v;
status = "okay";
};
&sdmmc {
max-frequency = <150000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3_s3>;
vqmmc-supply = <&vccio_sd_s0>;
status = "okay";
};
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
num-cs = <1>;
pmic@0 {
compatible = "rockchip,rk806";
spi-max-frequency = <1000000>;
reg = <0x0>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc5v0_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc5v0_sys>;
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
gpio-controller;
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_dvs2_null: dvs2-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_dvs3_null: dvs3-null-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun0";
};
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_log_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_ddr_s0: dcdc-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
vdd2_ddr_s3: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_2v0_pldo_s3: dcdc-reg7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2000000>;
};
};
vcc_3v3_s3: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vddq_ddr_s0: dcdc-reg9 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s3: dcdc-reg10 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avcc_1v8_s0: pldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s0: pldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avdd_1v2_s0: pldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3_s0: pldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd_s0: pldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
pldo6_s3: pldo-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_0v75_s3: nldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_ddr_pll_s0: nldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
avdd_0v75_s0: nldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "avdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v85_s0: nldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v75_s0: nldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&tsadc {
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};

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patch/kernel/rockchip64-6.14/dt/rk3588-rock-5b-plus.dts
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907
patch/kernel/rockchip64-6.14/dt/rk3588s-nanopi-m6.dts
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@ -1,907 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588s.dtsi"
/ {
model = "FriendlyElec NanoPi M6";
compatible = "friendlyelec,nanopi-m6", "rockchip,rk3588s";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
analog-sound {
compatible = "simple-audio-card";
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
simple-audio-card,format = "i2s";
simple-audio-card,hp-det-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "realtek,rt5616-codec";
simple-audio-card,routing =
"Headphones", "HPOL",
"Headphones", "HPOR",
"MIC1", "Microphone Jack",
"Microphone Jack", "micbias1";
simple-audio-card,widgets =
"Headphone", "Headphones",
"Microphone", "Microphone Jack";
simple-audio-card,cpu {
sound-dai = <&i2s0_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rt5616>;
};
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
button-maskrom {
label = "Maskrom";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <1800>;
};
};
adc-keys-1 {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
button-maskrom {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <1800>;
};
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi0_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
sys_led: led-0 {
label = "sys_led";
gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&sys_led_pin>;
};
user_led: led-1 {
label = "user_led";
gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&user_led_pin>;
};
};
vcc5v0_sys: regulator-vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_3v3_s0: regulator-vcc-3v3-s0 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3_s0";
vin-supply = <&vcc_3v3_s3>;
};
vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sd_s0_pwr>;
regulator-name = "vcc_3v3_sd_s0";
regulator-boot-on;
regulator-max-microvolt = <3000000>;
regulator-min-microvolt = <3000000>;
vin-supply = <&vcc_3v3_s3>;
};
vcc_3v3_pcie20: regulator-vcc3v3-pcie20 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_pcie20";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_s3>;
};
vcc_3v3_pcie20_m2: regulator-vcc3v3-pcie20-m2 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_m2_0_pwren>;
regulator-name = "vcc_3v3_pcie20_m2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_s3>;
};
vcc5v0_usb: regulator-vcc5v0-usb {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_host_20: regulator-vcc5v0-host-20 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host20_en>;
regulator-name = "vcc5v0_host_20";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_usb_otg0: regulator-vbus5v0-typec {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&typec5v_pwren>;
regulator-name = "vcc5v0_usb_otg0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
};
&combphy0_ps {
status = "okay";
};
&combphy2_psu {
status = "okay";
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&gmac1 {
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-rxid";
pinctrl-0 = <&gmac1_miim
&gmac1_tx_bus2
&gmac1_rx_bus2
&gmac1_rgmii_clk
&gmac1_rgmii_bus>;
pinctrl-names = "default";
tx_delay = <0x42>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu_s0>;
status = "okay";
};
&hdmi0 {
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
&hdmi0_out {
hdmi0_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdptxphy0 {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
status = "okay";
vdd_cpu_big0_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big0_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big1_s0: regulator@43 {
compatible = "rockchip,rk8603", "rockchip,rk8602";
reg = <0x43>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big1_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c2 {
status = "okay";
vdd_npu_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <2300>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c6 {
clock-frequency = <200000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6m0_xfer>;
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&rtc_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&i2c7 {
clock-frequency = <200000>;
status = "okay";
rt5616: audio-codec@1b {
compatible = "realtek,rt5616";
reg = <0x1b>;
clocks = <&cru I2S0_8CH_MCLKOUT>;
clock-names = "mclk";
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_mclk>;
status = "okay";
#sound-dai-cells = <0>;
};
};
&i2s0_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s0_lrck
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
&pcie2x1l1 {
reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;
status = "okay";
};
&pcie2x1l2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_m2_0_prsnt>;
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie20_m2>;
status = "okay";
};
&pinctrl {
gpio-leds {
sys_led_pin: sys-led-pin {
rockchip,pins =
<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led_pin: lan1-led-pin {
rockchip,pins =
<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_m2_0_pwren: pcie-m20-pwren {
rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_m2_0_prsnt: pcie-m20-prsnt {
rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
hym8563 {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
sd_s0_pwr: sd-s0-pwr {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
typec5v_pwren: typec5v-pwren {
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_host20_en: vcc5v0-host20-en {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
rtl8211f {
rtl8211f_rst: rtl8211f-rst {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay";
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
mmc-hs200-1_8v;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
no-mmc;
no-sdio;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3_sd_s0>;
vqmmc-supply = <&vccio_sd_s0>;
status = "okay";
};
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
num-cs = <1>;
pmic@0 {
compatible = "rockchip,rk806";
spi-max-frequency = <1000000>;
reg = <0x0>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc5v0_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc5v0_sys>;
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
gpio-controller;
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
rk806_dvs2_null: dvs2-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_dvs3_null: dvs3-null-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun0";
};
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_log_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_ddr_s0: dcdc-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
vdd2_ddr_s3: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_2v0_pldo_s3: dcdc-reg7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2000000>;
};
};
vcc_3v3_s3: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vddq_ddr_s0: dcdc-reg9 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s3: dcdc-reg10 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avcc_1v8_s0: pldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_1v8_s0: pldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avdd_1v2_s0: pldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
avcc_3v3_s0: pldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "avcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd_s0: pldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
pldo6_s3: pldo-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_0v75_s3: nldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
avdd_ddr_pll_s0: nldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "avdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
avdd_0v75_s0: nldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "avdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
avdd_0v85_s0: nldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "avdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v75_s0: nldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&tsadc {
status = "okay";
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
phy-supply = <&vcc5v0_usb_otg0>;
status = "okay";
};
&u2phy2 {
status = "okay";
};
&u2phy2_host {
phy-supply = <&vcc5v0_host_20>;
status = "okay";
};
&u2phy3 {
status = "okay";
};
&u2phy3_host {
phy-supply = <&vcc5v0_host_20>;
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
status = "okay";
};
&usbdp_phy0 {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi0_in_vp0>;
};
};

887
patch/kernel/rockchip64-6.14/dt/rk3588s-youyeetoo-r1.dts
View File

@ -1,887 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588s.dtsi"
/ {
model = "Youyeetoo R1";
compatible = "youyeetoo,r1", "rockchip,rk3588s";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdhci;
mmc1 = &sdmmc;
mmc2 = &sdio;
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:1500000n8";
};
leds {
compatible = "gpio-leds";
sys_led: led-0 {
label = "sys_led";
gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&sys_led_pin>;
};
};
/* HDMI 0 CONNECTOR */
hdmi0-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con_in: endpoint {
remote-endpoint = <&hdmi0_out_con>;
};
};
};
/* POWER REGULATOR 12V DC-IN */
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
/* POWER REGULATOR 5V SYS */
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
/* POWER REGULATOR CPU */
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc5v0_sys>;
};
/* POWER REGULATOR 3V (SD) */
vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sd_s0";
enable-active-high;
regulator-boot-on;
gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sd_s0_pwr>;
regulator-max-microvolt = <3000000>;
regulator-min-microvolt = <3000000>;
vin-supply = <&vcc_3v3_s3>;
};
/* POWER REGULATOR 3.3V (PCIE)*/
vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_pcie20";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_s3>;
};
/* POWER REGULATOR 5V (USB2 & USB3) */
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_host_20: vcc5v0-host-20 { // U13 (USB 2.0)
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host20_en>;
regulator-name = "vcc5v0_host_20";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_host_30: vcc5v0-host-30 { // U12 (USB 3.0)
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host30_en>;
regulator-name = "vcc5v0_host_30";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
/* BLUETOOTH */
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
clocks = <&hym8563>;
clock-names = "ext_clock";
status = "okay";
};
/* WIFI */
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
wifi_chip_type = "rtl8852be";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
/* FAN */
fan0: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
cooling-levels = <100 160 190 200 215 235 255>;
pwms = <&pwm6 0 40000 0>;
fan-supply = <&vcc12v_dcin>;
};
};
&combphy0_ps {
status = "okay";
};
&combphy2_psu {
status = "okay";
};
&gmac1 {
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-rxid";
pinctrl-0 = <&gmac1_miim
&gmac1_tx_bus2
&gmac1_rx_bus2
&gmac1_rgmii_clk
&gmac1_rgmii_bus>;
pinctrl-names = "default";
tx_delay = <0x42>;
tx_delay = <0x43>;
status = "okay";
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
mem-supply = <&vdd_cpu_big0_mem_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
mem-supply = <&vdd_cpu_big0_mem_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
mem-supply = <&vdd_cpu_big1_mem_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
mem-supply = <&vdd_cpu_big1_mem_s0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&gpu {
mali-supply = <&vdd_gpu_s0>;
status = "okay";
};
&hdmi0 {
enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
&hdmi0_out {
hdmi0_out_con: endpoint {
remote-endpoint = <&hdmi0_con_in>;
};
};
&hdmi0_sound {
status = "okay";
};
&hdptxphy0 {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
status = "okay";
vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big0_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 {
compatible = "rockchip,rk8603", "rockchip,rk8602";
reg = <0x43>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big1_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c2 {
status = "okay";
vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-compatible = "rk860x-reg";
regulator-name = "vdd_npu_s0";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <2300>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c6m3_xfer>;
/* RTC */
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "hym8563";
status = "okay";
};
};
&i2s5_8ch {
status = "okay";
};
&package_thermal {
polling-delay = <1000>;
trips {
package_fan0: package-fan0 {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
package_fan1: package-fan1 {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&package_fan0>;
cooling-device = <&fan0 THERMAL_NO_LIMIT 1>;
};
map2 {
trip = <&package_fan1>;
cooling-device = <&fan0 2 THERMAL_NO_LIMIT>;
};
};
};
&mdio1 {
rgmii_phy1: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
};
};
&pcie2x1l1 {
reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
rockchip,init-delay-ms = <100>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;
status = "okay";
};
&pcie2x1l2 {
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;
status = "okay";
};
&pinctrl {
/* TODO: SOUND */
sound {
hp_detect: hp-detect {
rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
/* GPIO LEDS */
gpio-leds {
sys_led_pin: sys-led-pin {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
/* RTC */
hym8563 {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
/* SD */
sdmmc {
sd_s0_pwr: sd-s0-pwr {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
/* USB */
usb {
vcc5v0_host20_en: vcc5v0-host20-en { // USB 2.0
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
};
vcc5v0_host30_en: vcc5v0-host30-en { // USB 3.0
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
/* WIRELESS */
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay";
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
/* HS400 doesn't work properly -> https://github.com/torvalds/linux/commit/cee572756aa2cb46e959e9797ad4b730b78a050b */
mmc-hs200-1_8v;
max-frequency = <200000000>;
status = "okay";
};
&sdmmc {
max-frequency = <200000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3_sd_s0>;
vqmmc-supply = <&vccio_sd_s0>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
status = "okay";
};
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
num-cs = <1>;
pmic@0 {
compatible = "rockchip,rk806";
spi-max-frequency = <1000000>;
reg = <0x0>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc5v0_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc5v0_sys>;
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
gpio-controller;
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_dvs2_null: dvs2-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fudr_moden0";
};
rk806_dvs3_null: dvs3-null-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun0";
};
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_log_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-init-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_ddr_s0: dcdc-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
vdd2_ddr_s3: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_2v0_pldo_s3: dcdc-reg7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2000000>;
};
};
vcc_3v3_s3: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vddq_ddr_s0: dcdc-reg9 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s3: dcdc-reg10 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avcc_1v8_s0: pldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_1v8_s0: pldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avdd_1v2_s0: pldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3_s0: pldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd_s0: pldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
pldo6_s3: pldo-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_0v75_s3: nldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_ddr_pll_s0: nldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
avdd_0v75_s0: nldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "avdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v85_s0: nldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v75_s0: nldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&pwm6{
status = "okay";
};
&tsadc {
status = "okay";
};
/* USB */
&u2phy0 {
status = "okay";
};
&u2phy2 {
status = "okay";
};
&u2phy3 {
status = "okay";
};
&u2phy0_otg {
phy-supply = <&vcc5v0_host_30>;
status = "okay";
};
&u2phy2_host {
phy-supply = <&vcc5v0_host_20>;
status = "okay";
};
&u2phy3_host {
phy-supply = <&vcc5v0_host_20>;
status = "okay";
};
&usb_host0_xhci {
status = "okay";
dr_mode = "host";
extcon = <&u2phy0>;
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdp_phy0 {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vop {
status = "okay";
};
&vp0 {
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi0_in_vp0>;
};
};

83
patch/kernel/rockchip64-6.14/general-add-hdmi-mks-ips50-resolutions.patch
View File

@ -1,83 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Maxim Medvedev <redrathnure@gmail.com>
Date: Mon, 1 Jan 2024 21:50:10 +0000
Subject: HDMI EDID records for 800x480 resolution (a MKS IPS50 screen and
similar)
---
drivers/gpu/drm/drm_edid.c | 12 +++++++++-
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 1 +
drivers/video/hdmi.c | 2 ++
include/linux/hdmi.h | 1 +
4 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1550,6 +1550,16 @@ static const struct drm_display_mode edid_cea_modes_193[] = {
4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
.picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
+ /* 220 - 800x480@60Hz 5:3 */
+ { DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30240, 800, 850,
+ 920, 960, 0, 480, 510, 513, 525, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_5_3, },
+ /* 221 - 800x480@60Hz 5:3, MKS IPS50 */
+ { DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30240, 800, 850,
+ 950, 960, 0, 480, 510, 513, 525, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_5_3, },
};
/*
@@ -4215,7 +4225,7 @@ static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
{
BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
- BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
+ BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 221);
if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
return &edid_cea_modes_1[vic - 1];
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 111111111111..222222222222 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -295,6 +295,7 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
{ 25175000, 31468750, 1, 41, 0, 3, 3, 1, 3, 3, 4, 0, 0xf5554f},
{ 27000000, 27000000, 1, 36, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
{ 27000000, 33750000, 1, 45, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
+ { 30240000, 30240000, 5, 504, 3, 2, 2, 20, 4, 2, 2, 0, 0x0}, // Non standard screens like MKS IPS50
{ 31500000, 31500000, 1, 42, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
{ 31500000, 39375000, 1, 105, 1, 3, 3, 10, 0, 3, 4, 0, 0x0},
{ 33750000, 33750000, 1, 45, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 111111111111..222222222222 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1087,6 +1087,8 @@ hdmi_picture_aspect_get_name(enum hdmi_picture_aspect picture_aspect)
return "64:27";
case HDMI_PICTURE_ASPECT_256_135:
return "256:135";
+ case HDMI_PICTURE_ASPECT_5_3:
+ return "5:3";
case HDMI_PICTURE_ASPECT_RESERVED:
return "Reserved";
}
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 111111111111..222222222222 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -108,6 +108,7 @@ enum hdmi_picture_aspect {
HDMI_PICTURE_ASPECT_16_9,
HDMI_PICTURE_ASPECT_64_27,
HDMI_PICTURE_ASPECT_256_135,
+ HDMI_PICTURE_ASPECT_5_3,
HDMI_PICTURE_ASPECT_RESERVED,
};
--
Armbian

133
patch/kernel/rockchip64-6.14/general-add-miniDP-dt-doc.patch
View File

@ -1,133 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Tony <tonymckahan@gmail.com>
Date: Wed, 3 Mar 2021 07:59:25 +0100
Subject: [ARCHEOLOGY] RK3399 Typec DP (#2676)
> X-Git-Archeology: > recovered message: > * RK3399 NanoPC-T4 Add Type-C alt mode DP
> X-Git-Archeology: > recovered message: > * rk3399 rockpi 4C add mini-DP (WIP)
> X-Git-Archeology: > recovered message: > * [ rockchip64 ] revert rockPi 4C DP patch
> X-Git-Archeology: > recovered message: > Add an extension to disable it, but leave for future work.
> X-Git-Archeology: - Revision 4971535c774a1f49a811baebc083ea028ced0300: https://github.com/armbian/build/commit/4971535c774a1f49a811baebc083ea028ced0300
> X-Git-Archeology: Date: Wed, 03 Mar 2021 07:59:25 +0100
> X-Git-Archeology: From: Tony <tonymckahan@gmail.com>
> X-Git-Archeology: Subject: RK3399 Typec DP (#2676)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml | 66 ++++++++++
1 file changed, 66 insertions(+)
diff --git a/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/extcon/extcon-usbc-virtual-pd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Type-C Virtual PD extcon
+
+maintainers:
+ - Jagan Teki <jagan@amarulasolutions.com>
+
+description: |
+ USB Type-C protocol supports various modes of operations includes PD,
+ USB3, and Altmode. If the platform design supports a Type-C connector
+ then configuring these modes can be done via enumeration.
+
+ However, there are some platforms that design these modes as separate
+ protocol connectors like design Display Port from on-chip USB3 controller.
+ So we can access Type-C Altmode Display Port via onboard Display Port
+ connector instead of a Type-C connector. These kinds of platforms require
+ an explicit extcon driver in order to handle Power Delivery and
+ Port Detection.
+
+properties:
+ compatible:
+ const: linux,extcon-usbc-virtual-pd
+
+ det-gpios:
+ description: Detect GPIO pin. Pin can be Display Port Detect or USB ID.
+ maxItems: 1
+
+ vpd-polarity:
+ description: USB Type-C Polarity. false for Normal and true for Flip.
+ type: boolean
+
+ vpd-super-speed:
+ description: USB Super Speed. false for USB2 and true for USB3.
+ type: boolean
+
+ vpd-data-role:
+ description: USB Data roles for Virtual Type-C.
+ $ref: /schemas/types.yaml#definitions/string
+
+ enum:
+ - host
+ - device
+ - display-port
+
+required:
+ - compatible
+ - det-gpios
+ - vpd-data-role
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+
+ virtual_pd: virtual-pd {
+ compatible = "linux,extcon-usbc-virtual-pd";
+ det-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
+ vpd-data-role = "display-port";
+ vpd-super-speed;
+ };
--
Armbian

382
patch/kernel/rockchip64-6.14/general-add-miniDP-virtual-extcon.patch
View File

@ -1,382 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Tony <tonymckahan@gmail.com>
Date: Wed, 3 Mar 2021 07:59:25 +0100
Subject: [ARCHEOLOGY] RK3399 Typec DP (#2676)
> X-Git-Archeology: > recovered message: > * RK3399 NanoPC-T4 Add Type-C alt mode DP
> X-Git-Archeology: > recovered message: > * rk3399 rockpi 4C add mini-DP (WIP)
> X-Git-Archeology: > recovered message: > * [ rockchip64 ] revert rockPi 4C DP patch
> X-Git-Archeology: > recovered message: > Add an extension to disable it, but leave for future work.
> X-Git-Archeology: - Revision 4971535c774a1f49a811baebc083ea028ced0300: https://github.com/armbian/build/commit/4971535c774a1f49a811baebc083ea028ced0300
> X-Git-Archeology: Date: Wed, 03 Mar 2021 07:59:25 +0100
> X-Git-Archeology: From: Tony <tonymckahan@gmail.com>
> X-Git-Archeology: Subject: RK3399 Typec DP (#2676)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
drivers/extcon/Kconfig | 10 +
drivers/extcon/Makefile | 1 +
drivers/extcon/extcon-usbc-virtual-pd.c | 285 ++++++++++
3 files changed, 296 insertions(+)
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
index 111111111111..222222222222 100644
--- a/drivers/extcon/Kconfig
+++ b/drivers/extcon/Kconfig
@@ -214,4 +214,14 @@ config EXTCON_RTK_TYPE_C
The DHC (Digital Home Hub) RTD series SoC contains a type c module.
This driver will detect the status of the type-c port.
+config EXTCON_USBC_VIRTUAL_PD
+ tristate "Virtual Type-C PD EXTCON support"
+ depends on GPIOLIB || COMPILE_TEST
+ help
+ Say Y here to enable Virtual Type-C PD extcon driver support, if
+ hardware platform designed Type-C modes separately.
+
+ Example, of designing Display Port separately from Type-C Altmode
+ instead of accessing Altmode Display Port in Type-C connector.
+
endif
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
index 111111111111..222222222222 100644
--- a/drivers/extcon/Makefile
+++ b/drivers/extcon/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_EXTCON_USB_GPIO) += extcon-usb-gpio.o
obj-$(CONFIG_EXTCON_USBC_CROS_EC) += extcon-usbc-cros-ec.o
obj-$(CONFIG_EXTCON_USBC_TUSB320) += extcon-usbc-tusb320.o
obj-$(CONFIG_EXTCON_RTK_TYPE_C) += extcon-rtk-type-c.o
+obj-$(CONFIG_EXTCON_USBC_VIRTUAL_PD) += extcon-usbc-virtual-pd.o
diff --git a/drivers/extcon/extcon-usbc-virtual-pd.c b/drivers/extcon/extcon-usbc-virtual-pd.c
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/drivers/extcon/extcon-usbc-virtual-pd.c
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Type-C Virtual PD Extcon driver
+ *
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2019 Amarula Solutions(India)
+ */
+
+#include <linux/extcon-provider.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+static const unsigned int vpd_cable[] = {
+ EXTCON_USB,
+ EXTCON_USB_HOST,
+ EXTCON_DISP_DP,
+ EXTCON_NONE,
+};
+
+enum vpd_data_role {
+ DR_NONE,
+ DR_HOST,
+ DR_DEVICE,
+ DR_DISPLAY_PORT,
+};
+
+enum vpd_polarity {
+ POLARITY_NORMAL,
+ POLARITY_FLIP,
+};
+
+enum vpd_usb_ss {
+ USB_SS_USB2,
+ USB_SS_USB3,
+};
+
+struct vpd_extcon {
+ struct device *dev;
+ struct extcon_dev *extcon;
+ struct gpio_desc *det_gpio;
+
+ u8 polarity;
+ u8 usb_ss;
+ enum vpd_data_role data_role;
+
+ int irq;
+ bool enable_irq;
+ struct work_struct work;
+ struct delayed_work irq_work;
+};
+
+static void vpd_extcon_irq_work(struct work_struct *work)
+{
+ struct vpd_extcon *vpd = container_of(work, struct vpd_extcon, irq_work.work);
+ bool host_connected = false, device_connected = false, dp_connected = false;
+ union extcon_property_value property;
+ int det;
+
+ det = vpd->det_gpio ? gpiod_get_raw_value(vpd->det_gpio) : 0;
+ if (det) {
+ device_connected = (vpd->data_role == DR_DEVICE) ? true : false;
+ host_connected = (vpd->data_role == DR_HOST) ? true : false;
+ dp_connected = (vpd->data_role == DR_DISPLAY_PORT) ? true : false;
+ }
+
+ extcon_set_state(vpd->extcon, EXTCON_USB, host_connected);
+ extcon_set_state(vpd->extcon, EXTCON_USB_HOST, device_connected);
+ extcon_set_state(vpd->extcon, EXTCON_DISP_DP, dp_connected);
+
+ property.intval = vpd->polarity;
+ extcon_set_property(vpd->extcon, EXTCON_USB,
+ EXTCON_PROP_USB_TYPEC_POLARITY, property);
+ extcon_set_property(vpd->extcon, EXTCON_USB_HOST,
+ EXTCON_PROP_USB_TYPEC_POLARITY, property);
+ extcon_set_property(vpd->extcon, EXTCON_DISP_DP,
+ EXTCON_PROP_USB_TYPEC_POLARITY, property);
+
+ property.intval = vpd->usb_ss;
+ extcon_set_property(vpd->extcon, EXTCON_USB,
+ EXTCON_PROP_USB_SS, property);
+ extcon_set_property(vpd->extcon, EXTCON_USB_HOST,
+ EXTCON_PROP_USB_SS, property);
+ extcon_set_property(vpd->extcon, EXTCON_DISP_DP,
+ EXTCON_PROP_USB_SS, property);
+
+ extcon_sync(vpd->extcon, EXTCON_USB);
+ extcon_sync(vpd->extcon, EXTCON_USB_HOST);
+ extcon_sync(vpd->extcon, EXTCON_DISP_DP);
+}
+
+static irqreturn_t vpd_extcon_irq_handler(int irq, void *dev_id)
+{
+ struct vpd_extcon *vpd = dev_id;
+
+ schedule_delayed_work(&vpd->irq_work, msecs_to_jiffies(10));
+
+ return IRQ_HANDLED;
+}
+
+static enum vpd_data_role vpd_extcon_data_role(struct vpd_extcon *vpd)
+{
+ const char *const data_roles[] = {
+ [DR_NONE] = "NONE",
+ [DR_HOST] = "host",
+ [DR_DEVICE] = "device",
+ [DR_DISPLAY_PORT] = "display-port",
+ };
+ struct device *dev = vpd->dev;
+ int ret;
+ const char *dr;
+
+ ret = device_property_read_string(dev, "vpd-data-role", &dr);
+ if (ret < 0)
+ return DR_NONE;
+
+ ret = match_string(data_roles, ARRAY_SIZE(data_roles), dr);
+
+ return (ret < 0) ? DR_NONE : ret;
+}
+
+static int vpd_extcon_parse_dts(struct vpd_extcon *vpd)
+{
+ struct device *dev = vpd->dev;
+ bool val = false;
+ int ret;
+
+ val = device_property_read_bool(dev, "vpd-polarity");
+ if (val)
+ vpd->polarity = POLARITY_FLIP;
+ else
+ vpd->polarity = POLARITY_NORMAL;
+
+ val = device_property_read_bool(dev, "vpd-super-speed");
+ if (val)
+ vpd->usb_ss = USB_SS_USB3;
+ else
+ vpd->usb_ss = USB_SS_USB2;
+
+ vpd->data_role = vpd_extcon_data_role(vpd);
+
+ vpd->det_gpio = devm_gpiod_get_optional(dev, "det", GPIOD_ASIS);
+ if (IS_ERR(vpd->det_gpio)) {
+ ret = PTR_ERR(vpd->det_gpio);
+ dev_warn(dev, "failed to get det gpio: %d\n", ret);
+ return ret;
+ }
+
+ vpd->irq = gpiod_to_irq(vpd->det_gpio);
+ if (vpd->irq < 0) {
+ dev_err(dev, "failed to get irq for gpio: %d\n", vpd->irq);
+ return vpd->irq;
+ }
+
+ ret = devm_request_threaded_irq(dev, vpd->irq, NULL,
+ vpd_extcon_irq_handler,
+ IRQF_TRIGGER_FALLING |
+ IRQF_TRIGGER_RISING | IRQF_ONESHOT,
+ NULL, vpd);
+ if (ret)
+ dev_err(dev, "failed to request gpio irq\n");
+
+ return ret;
+}
+
+static int vpd_extcon_probe(struct platform_device *pdev)
+{
+ struct vpd_extcon *vpd;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ vpd = devm_kzalloc(dev, sizeof(*vpd), GFP_KERNEL);
+ if (!vpd)
+ return -ENOMEM;
+
+ vpd->dev = dev;
+ ret = vpd_extcon_parse_dts(vpd);
+ if (ret)
+ return ret;
+
+ INIT_DELAYED_WORK(&vpd->irq_work, vpd_extcon_irq_work);
+
+ vpd->extcon = devm_extcon_dev_allocate(dev, vpd_cable);
+ if (IS_ERR(vpd->extcon)) {
+ dev_err(dev, "allocat extcon failed\n");
+ return PTR_ERR(vpd->extcon);
+ }
+
+ ret = devm_extcon_dev_register(dev, vpd->extcon);
+ if (ret) {
+ dev_err(dev, "register extcon failed: %d\n", ret);
+ return ret;
+ }
+
+ extcon_set_property_capability(vpd->extcon, EXTCON_USB,
+ EXTCON_PROP_USB_VBUS);
+ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST,
+ EXTCON_PROP_USB_VBUS);
+
+ extcon_set_property_capability(vpd->extcon, EXTCON_USB,
+ EXTCON_PROP_USB_TYPEC_POLARITY);
+ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST,
+ EXTCON_PROP_USB_TYPEC_POLARITY);
+ extcon_set_property_capability(vpd->extcon, EXTCON_USB,
+ EXTCON_PROP_USB_SS);
+ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST,
+ EXTCON_PROP_USB_SS);
+
+ extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP,
+ EXTCON_PROP_USB_SS);
+ extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP,
+ EXTCON_PROP_USB_TYPEC_POLARITY);
+
+ platform_set_drvdata(pdev, vpd);
+
+ vpd_extcon_irq_work(&vpd->irq_work.work);
+
+ return 0;
+}
+
+static void vpd_extcon_remove(struct platform_device *pdev)
+{
+ struct vpd_extcon *vpd = platform_get_drvdata(pdev);
+
+ cancel_delayed_work_sync(&vpd->irq_work);
+
+ return;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int vpd_extcon_suspend(struct device *dev)
+{
+ struct vpd_extcon *vpd = dev_get_drvdata(dev);
+
+ if (!vpd->enable_irq) {
+ disable_irq_nosync(vpd->irq);
+ vpd->enable_irq = true;
+ }
+
+ return 0;
+}
+
+static int vpd_extcon_resume(struct device *dev)
+{
+ struct vpd_extcon *vpd = dev_get_drvdata(dev);
+
+ if (vpd->enable_irq) {
+ enable_irq(vpd->irq);
+ vpd->enable_irq = false;
+ }
+
+ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(vpd_extcon_pm_ops,
+ vpd_extcon_suspend, vpd_extcon_resume);
+
+static const struct of_device_id vpd_extcon_dt_match[] = {
+ { .compatible = "linux,extcon-usbc-virtual-pd", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver vpd_extcon_driver = {
+ .probe = vpd_extcon_probe,
+ .remove = vpd_extcon_remove,
+ .driver = {
+ .name = "extcon-usbc-virtual-pd",
+ .pm = &vpd_extcon_pm_ops,
+ .of_match_table = vpd_extcon_dt_match,
+ },
+};
+
+module_platform_driver(vpd_extcon_driver);
+
+MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
+MODULE_DESCRIPTION("Type-C Virtual PD extcon driver");
+MODULE_LICENSE("GPL v2");
--
Armbian

856
patch/kernel/rockchip64-6.14/general-add-panel-simple-dsi.patch
View File

@ -1,856 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: simple <991605149@qq.com>
Date: Sun, 12 Sep 2021 20:06:02 +0200
Subject: [ARCHEOLOGY] general add panel simple dsi (#3140)
> X-Git-Archeology: > recovered message: > * Backporting patch to 5.10 kernel makes sense. Lets do it.
> X-Git-Archeology: > recovered message: > Co-authored-by: iamdrq <iamdrq@qq.com>
> X-Git-Archeology: > recovered message: > Co-authored-by: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: - Revision 15819f00e21238e36ca70f6d8445efd6157fbe66: https://github.com/armbian/build/commit/15819f00e21238e36ca70f6d8445efd6157fbe66
> X-Git-Archeology: Date: Sun, 12 Sep 2021 20:06:02 +0200
> X-Git-Archeology: From: simple <991605149@qq.com>
> X-Git-Archeology: Subject: general add panel simple dsi (#3140)
> X-Git-Archeology:
> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4
> X-Git-Archeology: Date: Tue, 11 Jan 2022 15:26:11 +0100
> X-Git-Archeology: From: Oleg <balbes-150@yandex.ru>
> X-Git-Archeology: Subject: move kernel edge to 5.16 (#3387)
> X-Git-Archeology:
> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 3b78b57fe367e60ad874d9e16ff1cd67957f8382: https://github.com/armbian/build/commit/3b78b57fe367e60ad874d9e16ff1cd67957f8382
> X-Git-Archeology: Date: Sat, 24 Dec 2022 09:43:51 +0100
> X-Git-Archeology: From: simple <991605149@qq.com>
> X-Git-Archeology: Subject: Fix general-add-panel-simple-dsi.patch on linux6.1 (#4607)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-simple-dsi.c | 772 ++++++++++
2 files changed, 773 insertions(+)
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o
obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
+obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple-dsi.o
obj-$(CONFIG_DRM_PANEL_EDP) += panel-edp.o
obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) += panel-ebbg-ft8719.o
obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o
diff --git a/drivers/gpu/drm/panel/panel-simple-dsi.c b/drivers/gpu/drm/panel/panel-simple-dsi.c
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-simple-dsi.c
@@ -0,0 +1,772 @@
+/*
+ * Copyright (C) 2021
+ * This simple dsi driver porting from rock-chip panel-simple.c on linux-4.4
+ */
+
+#include <linux/backlight.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+
+#include <video/display_timing.h>
+#include <video/mipi_display.h>
+#include <linux/of_device.h>
+#include <video/of_display_timing.h>
+#include <linux/of_graph.h>
+#include <video/videomode.h>
+#include <linux/delay.h>
+
+struct cmd_ctrl_hdr {
+ u8 dtype; /* data type */
+ u8 wait; /* ms */
+ u8 dlen; /* payload len */
+} __packed;
+
+struct cmd_desc {
+ struct cmd_ctrl_hdr dchdr;
+ u8 *payload;
+};
+
+struct panel_cmds {
+ u8 *buf;
+ int blen;
+ struct cmd_desc *cmds;
+ int cmd_cnt;
+};
+
+struct panel_desc {
+ const struct drm_display_mode *modes;
+ unsigned int num_modes;
+ const struct display_timing *timings;
+ unsigned int num_timings;
+
+ unsigned int bpc;
+
+ struct {
+ unsigned int width;
+ unsigned int height;
+ } size;
+
+ /**
+ * @reset: the time (in milliseconds) indicates the delay time
+ * after the panel to operate reset gpio
+ * @init: the time (in milliseconds) that it takes for the panel to
+ * power on and dsi host can send command to panel
+ * @prepare: the time (in milliseconds) that it takes for the panel to
+ * become ready and start receiving video data
+ * @enable: the time (in milliseconds) that it takes for the panel to
+ * display the first valid frame after starting to receive
+ * video data
+ * @disable: the time (in milliseconds) that it takes for the panel to
+ * turn the display off (no content is visible)
+ * @unprepare: the time (in milliseconds) that it takes for the panel
+ * to power itself down completely
+ */
+ struct {
+ unsigned int reset;
+ unsigned int init;
+ unsigned int prepare;
+ unsigned int enable;
+ unsigned int disable;
+ unsigned int unprepare;
+ } delay;
+
+ u32 bus_format;
+};
+
+struct panel_simple {
+ struct drm_panel base;
+ struct mipi_dsi_device *dsi;
+ bool prepared;
+ bool enabled;
+ bool power_invert;
+
+ struct device *dev;
+ const struct panel_desc *desc;
+
+ struct regulator *supply;
+
+ struct gpio_desc *enable_gpio;
+ struct gpio_desc *reset_gpio;
+ int cmd_type;
+
+ struct panel_cmds *on_cmds;
+ struct panel_cmds *off_cmds;
+ struct device_node *np_crtc;
+
+ int reset_level;
+ enum drm_panel_orientation orientation;
+};
+
+enum rockchip_cmd_type {
+ CMD_TYPE_DEFAULT,
+ CMD_TYPE_SPI,
+ CMD_TYPE_MCU
+};
+
+static void panel_simple_sleep(unsigned int msec)
+{
+ if (msec > 20)
+ msleep(msec);
+ else
+ usleep_range(msec * 1000, (msec + 1) * 1000);
+}
+
+static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
+{
+ return container_of(panel, struct panel_simple, base);
+}
+
+static void panel_simple_cmds_cleanup(struct panel_simple *p)
+{
+ if (p->on_cmds) {
+ kfree(p->on_cmds->buf);
+ kfree(p->on_cmds->cmds);
+ }
+
+ if (p->off_cmds) {
+ kfree(p->off_cmds->buf);
+ kfree(p->off_cmds->cmds);
+ }
+}
+
+static int panel_simple_parse_cmds(struct device *dev,
+ const u8 *data, int blen,
+ struct panel_cmds *pcmds)
+{
+ unsigned int len;
+ char *buf, *bp;
+ struct cmd_ctrl_hdr *dchdr;
+ int i, cnt;
+
+ if (!pcmds)
+ return -EINVAL;
+
+ buf = kmemdup(data, blen, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ /* scan init commands */
+ bp = buf;
+ len = blen;
+ cnt = 0;
+ while (len > sizeof(*dchdr)) {
+ dchdr = (struct cmd_ctrl_hdr *)bp;
+
+ if (dchdr->dlen > len) {
+ dev_err(dev, "%s: error, len=%d", __func__,
+ dchdr->dlen);
+ return -EINVAL;
+ }
+
+ bp += sizeof(*dchdr);
+ len -= sizeof(*dchdr);
+ bp += dchdr->dlen;
+ len -= dchdr->dlen;
+ cnt++;
+ }
+
+ if (len != 0) {
+ dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
+ __func__, buf[0], blen);
+ kfree(buf);
+ return -EINVAL;
+ }
+
+ pcmds->cmds = kcalloc(cnt, sizeof(struct cmd_desc), GFP_KERNEL);
+ if (!pcmds->cmds) {
+ kfree(buf);
+ return -ENOMEM;
+ }
+
+ pcmds->cmd_cnt = cnt;
+ pcmds->buf = buf;
+ pcmds->blen = blen;
+
+ bp = buf;
+ len = blen;
+ for (i = 0; i < cnt; i++) {
+ dchdr = (struct cmd_ctrl_hdr *)bp;
+ len -= sizeof(*dchdr);
+ bp += sizeof(*dchdr);
+ pcmds->cmds[i].dchdr = *dchdr;
+ pcmds->cmds[i].payload = bp;
+ bp += dchdr->dlen;
+ len -= dchdr->dlen;
+ }
+
+ return 0;
+}
+
+static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
+ struct panel_cmds *cmds)
+{
+ struct mipi_dsi_device *dsi = panel->dsi;
+ int i, err;
+
+ if (!cmds)
+ return -EINVAL;
+
+ for (i = 0; i < cmds->cmd_cnt; i++) {
+ struct cmd_desc *cmd = &cmds->cmds[i];
+
+ switch (cmd->dchdr.dtype) {
+ case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
+ case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
+ case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
+ case MIPI_DSI_GENERIC_LONG_WRITE:
+ err = mipi_dsi_generic_write(dsi, cmd->payload,
+ cmd->dchdr.dlen);
+ break;
+ case MIPI_DSI_DCS_SHORT_WRITE:
+ case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+ case MIPI_DSI_DCS_LONG_WRITE:
+ err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
+ cmd->dchdr.dlen);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (err < 0)
+ dev_err(panel->dev, "failed to write dcs cmd: %d\n",
+ err);
+
+ if (cmd->dchdr.wait)
+ panel_simple_sleep(cmd->dchdr.wait);
+ }
+
+ return 0;
+}
+
+static int panel_simple_get_cmds(struct panel_simple *panel)
+{
+ const void *data;
+ int len;
+ int err;
+
+ data = of_get_property(panel->dev->of_node, "panel-init-sequence",
+ &len);
+ if (data) {
+ panel->on_cmds = devm_kzalloc(panel->dev,
+ sizeof(*panel->on_cmds),
+ GFP_KERNEL);
+ if (!panel->on_cmds)
+ return -ENOMEM;
+
+ err = panel_simple_parse_cmds(panel->dev, data, len,
+ panel->on_cmds);
+ if (err) {
+ dev_err(panel->dev, "failed to parse panel init sequence\n");
+ return err;
+ }
+ }
+
+ data = of_get_property(panel->dev->of_node, "panel-exit-sequence",
+ &len);
+ if (data) {
+ panel->off_cmds = devm_kzalloc(panel->dev,
+ sizeof(*panel->off_cmds),
+ GFP_KERNEL);
+ if (!panel->off_cmds)
+ return -ENOMEM;
+
+ err = panel_simple_parse_cmds(panel->dev, data, len,
+ panel->off_cmds);
+ if (err) {
+ dev_err(panel->dev, "failed to parse panel exit sequence\n");
+ return err;
+ }
+ }
+ return 0;
+}
+
+static int panel_simple_get_modes(struct drm_panel *panel,struct drm_connector *connector)
+{
+ struct panel_simple *p = to_panel_simple(panel);
+ struct drm_device *drm = connector->dev;
+ struct drm_display_mode *mode;
+ struct device_node *timings_np;
+ int ret;
+
+ timings_np = of_get_child_by_name(panel->dev->of_node,
+ "display-timings");
+ if (!timings_np) {
+ dev_dbg(panel->dev, "failed to find display-timings node\n");
+ return 0;
+ }
+
+ of_node_put(timings_np);
+ mode = drm_mode_create(drm);
+ if (!mode)
+ return 0;
+
+ ret = of_get_drm_display_mode(panel->dev->of_node, mode, &p->desc->bus_format,
+ OF_USE_NATIVE_MODE);
+ if (ret) {
+ dev_dbg(panel->dev, "failed to find dts display timings\n");
+ drm_mode_destroy(drm, mode);
+ return 0;
+ }
+
+ drm_mode_set_name(mode);
+ mode->type |= DRM_MODE_TYPE_PREFERRED;
+
+ connector->display_info.width_mm = mode->width_mm;
+ connector->display_info.height_mm = mode->height_mm;
+
+ drm_mode_probed_add(connector, mode);
+
+ /*
+ * TODO: Remove once all drm drivers call
+ * drm_connector_set_orientation_from_panel()
+ */
+ drm_connector_set_panel_orientation(connector, p->orientation);
+
+ return 1;
+}
+
+static int panel_simple_regulator_enable(struct drm_panel *panel)
+{
+ struct panel_simple *p = to_panel_simple(panel);
+ int err = 0;
+
+ if (p->power_invert) {
+ if (regulator_is_enabled(p->supply) > 0)
+ regulator_disable(p->supply);
+ } else {
+ err = regulator_enable(p->supply);
+ if (err < 0) {
+ dev_err(panel->dev, "failed to enable supply: %d\n",
+ err);
+ return err;
+ }
+ }
+
+ return err;
+}
+
+static int panel_simple_regulator_disable(struct drm_panel *panel)
+{
+ struct panel_simple *p = to_panel_simple(panel);
+ int err = 0;
+
+ if (p->power_invert) {
+ if (!regulator_is_enabled(p->supply)) {
+ err = regulator_enable(p->supply);
+ if (err < 0) {
+ dev_err(panel->dev, "failed to enable supply: %d\n",
+ err);
+ return err;
+ }
+ }
+ } else {
+ regulator_disable(p->supply);
+ }
+
+ return err;
+}
+
+static int panel_simple_disable(struct drm_panel *panel)
+{
+ struct panel_simple *p = to_panel_simple(panel);
+ int err = 0;
+
+ if (!p->enabled)
+ return 0;
+
+ if (p->desc && p->desc->delay.disable)
+ panel_simple_sleep(p->desc->delay.disable);
+
+ p->enabled = false;
+
+ return 0;
+}
+
+static int panel_simple_unprepare(struct drm_panel *panel)
+{
+ struct panel_simple *p = to_panel_simple(panel);
+ int err = 0;
+
+ if (!p->prepared)
+ return 0;
+
+ if (p->off_cmds) {
+ if (p->dsi)
+ err = panel_simple_dsi_send_cmds(p, p->off_cmds);
+ if (err)
+ dev_err(p->dev, "failed to send off cmds\n");
+ }
+
+ if (p->reset_gpio)
+ gpiod_direction_output(p->reset_gpio, !p->reset_level);
+
+ if (p->enable_gpio)
+ gpiod_direction_output(p->enable_gpio, 0);
+
+ panel_simple_regulator_disable(panel);
+
+ if (p->desc && p->desc->delay.unprepare)
+ panel_simple_sleep(p->desc->delay.unprepare);
+
+ p->prepared = false;
+
+ return 0;
+}
+
+static int panel_simple_prepare(struct drm_panel *panel)
+{
+ struct panel_simple *p = to_panel_simple(panel);
+ int err;
+
+ if (p->prepared)
+ return 0;
+
+ err = panel_simple_regulator_enable(panel);
+ if (err < 0) {
+ dev_err(panel->dev, "failed to enable supply: %d\n", err);
+ return err;
+ }
+
+ if (p->enable_gpio)
+ gpiod_direction_output(p->enable_gpio, 1);
+
+ if (p->desc && p->desc->delay.prepare)
+ panel_simple_sleep(p->desc->delay.prepare);
+
+ if (p->reset_gpio)
+ gpiod_direction_output(p->reset_gpio, !p->reset_level);
+
+ if (p->desc && p->desc->delay.reset)
+ panel_simple_sleep(p->desc->delay.reset);
+
+ if (p->reset_gpio)
+ gpiod_direction_output(p->reset_gpio, p->reset_level);
+
+ if (p->desc && p->desc->delay.init)
+ panel_simple_sleep(p->desc->delay.init);
+
+ if (p->on_cmds) {
+ if (p->dsi)
+ err = panel_simple_dsi_send_cmds(p, p->on_cmds);
+ if (err)
+ dev_err(p->dev, "failed to send on cmds\n");
+ }
+
+ p->prepared = true;
+
+ return 0;
+}
+
+static int panel_simple_enable(struct drm_panel *panel)
+{
+ struct panel_simple *p = to_panel_simple(panel);
+ int err = 0;
+
+ if (p->enabled)
+ return 0;
+
+ if (p->desc && p->desc->delay.enable)
+ panel_simple_sleep(p->desc->delay.enable);
+
+ p->enabled = true;
+
+ return 0;
+}
+
+static int panel_simple_get_timings(struct drm_panel *panel,
+ unsigned int num_timings,
+ struct display_timing *timings)
+{
+ struct panel_simple *p = to_panel_simple(panel);
+ unsigned int i;
+
+ if (!p->desc)
+ return 0;
+
+ if (p->desc->num_timings < num_timings)
+ num_timings = p->desc->num_timings;
+
+ if (timings)
+ for (i = 0; i < num_timings; i++)
+ timings[i] = p->desc->timings[i];
+
+ return p->desc->num_timings;
+}
+
+static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
+{
+ struct panel_simple *p = to_panel_simple(panel);
+
+ return p->orientation;
+}
+
+
+static const struct drm_panel_funcs panel_simple_funcs = {
+ .disable = panel_simple_disable,
+ .unprepare = panel_simple_unprepare,
+ .prepare = panel_simple_prepare,
+ .enable = panel_simple_enable,
+ .get_modes = panel_simple_get_modes,
+ .get_orientation = panel_simple_get_orientation,
+ .get_timings = panel_simple_get_timings,
+};
+
+static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
+{
+ struct panel_simple *panel;
+ struct panel_desc *of_desc;
+ const char *cmd_type;
+ u32 val;
+ int err;
+
+ panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
+ if (!panel)
+ return -ENOMEM;
+
+ if (!desc)
+ of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
+ else
+ of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
+
+ if (!of_property_read_u32(dev->of_node, "bus-format", &val))
+ of_desc->bus_format = val;
+ if (!of_property_read_u32(dev->of_node, "bpc", &val))
+ of_desc->bpc = val;
+ if (!of_property_read_u32(dev->of_node, "prepare-delay-ms", &val))
+ of_desc->delay.prepare = val;
+ if (!of_property_read_u32(dev->of_node, "enable-delay-ms", &val))
+ of_desc->delay.enable = val;
+ if (!of_property_read_u32(dev->of_node, "disable-delay-ms", &val))
+ of_desc->delay.disable = val;
+ if (!of_property_read_u32(dev->of_node, "unprepare-delay-ms", &val))
+ of_desc->delay.unprepare = val;
+ if (!of_property_read_u32(dev->of_node, "reset-delay-ms", &val))
+ of_desc->delay.reset = val;
+ if (!of_property_read_u32(dev->of_node, "init-delay-ms", &val))
+ of_desc->delay.init = val;
+ if (!of_property_read_u32(dev->of_node, "width-mm", &val))
+ of_desc->size.width = val;
+ if (!of_property_read_u32(dev->of_node, "height-mm", &val))
+ of_desc->size.height = val;
+
+ panel->enabled = false;
+ panel->prepared = false;
+ panel->desc = of_desc;
+ panel->dev = dev;
+
+ err = panel_simple_get_cmds(panel);
+ if (err) {
+ dev_err(dev, "failed to get init cmd: %d\n", err);
+ return err;
+ }
+ panel->supply = devm_regulator_get(dev, "power");
+ if (IS_ERR(panel->supply))
+ return PTR_ERR(panel->supply);
+
+ panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
+ if (IS_ERR(panel->enable_gpio)) {
+ err = PTR_ERR(panel->enable_gpio);
+ dev_err(dev, "failed to request enable GPIO: %d\n", err);
+ return err;
+ }
+
+ panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
+ if (IS_ERR(panel->reset_gpio)) {
+ err = PTR_ERR(panel->reset_gpio);
+ dev_err(dev, "failed to request reset GPIO: %d\n", err);
+ return err;
+ }
+
+ if (!of_property_read_u32(dev->of_node, "reset-level", &val)) {
+ panel->reset_level = val;
+ } else {
+ panel->reset_level = 0;
+ }
+
+ err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
+ if (err) {
+ dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
+ return err;
+ }
+
+ panel->cmd_type = CMD_TYPE_DEFAULT;
+
+ panel->power_invert =
+ of_property_read_bool(dev->of_node, "power-invert");
+
+ drm_panel_init(&panel->base, dev, &panel_simple_funcs,DRM_MODE_CONNECTOR_DSI);
+ panel->base.dev = dev;
+ panel->base.funcs = &panel_simple_funcs;
+
+ err = drm_panel_of_backlight(&panel->base);
+ if (err)
+ return err;
+
+ drm_panel_add(&panel->base);
+
+ dev_set_drvdata(dev, panel);
+
+ return 0;
+}
+
+static int panel_simple_remove(struct device *dev)
+{
+ struct panel_simple *panel = dev_get_drvdata(dev);
+
+ drm_panel_remove(&panel->base);
+
+ panel_simple_disable(&panel->base);
+ panel_simple_unprepare(&panel->base);
+
+ panel_simple_cmds_cleanup(panel);
+
+ return 0;
+}
+
+static void panel_simple_shutdown(struct device *dev)
+{
+ struct panel_simple *panel = dev_get_drvdata(dev);
+
+ panel_simple_disable(&panel->base);
+
+ if (panel->prepared) {
+ if (panel->reset_gpio)
+ gpiod_direction_output(panel->reset_gpio, !panel->reset_level);
+
+ if (panel->enable_gpio)
+ gpiod_direction_output(panel->enable_gpio, 0);
+
+ panel_simple_regulator_disable(&panel->base);
+ }
+}
+
+struct panel_desc_dsi {
+ struct panel_desc desc;
+
+ unsigned long flags;
+ enum mipi_dsi_pixel_format format;
+ unsigned int lanes;
+};
+
+/*
+static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
+ .clock = 157200,
+ .hdisplay = 1920,
+ .hsync_start = 1920 + 154,
+ .hsync_end = 1920 + 154 + 16,
+ .htotal = 1920 + 154 + 16 + 32,
+ .vdisplay = 1200,
+ .vsync_start = 1200 + 17,
+ .vsync_end = 1200 + 17 + 2,
+ .vtotal = 1200 + 17 + 2 + 16,
+ .vrefresh = 60,
+};
+static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
+ .desc = {
+ .modes = &panasonic_vvx10f004b00_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 217,
+ .height = 136,
+ },
+ },
+ .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_CLOCK_NON_CONTINUOUS,
+ .format = MIPI_DSI_FMT_RGB888,
+ .lanes = 4,
+};
+*/
+
+static const struct of_device_id dsi_of_match[] = {
+ {
+ .compatible = "panel-dsi-simple",
+ .data = NULL
+ }, {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(of, dsi_of_match);
+
+static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ struct panel_simple *panel;
+ const struct panel_desc_dsi *desc;
+ const struct of_device_id *id;
+ const struct panel_desc *pdesc;
+ int err;
+ u32 val;
+
+ id = of_match_node(dsi_of_match, dev->of_node);
+ if (!id)
+ return -ENODEV;
+
+ desc = id->data;
+
+ if (desc) {
+ dsi->mode_flags = desc->flags;
+ dsi->format = desc->format;
+ dsi->lanes = desc->lanes;
+ pdesc = &desc->desc;
+ } else {
+ pdesc = NULL;
+ }
+
+ err = panel_simple_probe(dev, pdesc);
+ if (err < 0)
+ return err;
+
+ panel = dev_get_drvdata(dev);
+ panel->dsi = dsi;
+
+ if (!of_property_read_u32(dev->of_node, "dsi,flags", &val))
+ dsi->mode_flags = val;
+
+ if (!of_property_read_u32(dev->of_node, "dsi,format", &val))
+ dsi->format = val;
+
+ if (!of_property_read_u32(dev->of_node, "dsi,lanes", &val))
+ dsi->lanes = val;
+
+ return mipi_dsi_attach(dsi);
+}
+
+static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
+{
+ int err;
+
+ err = mipi_dsi_detach(dsi);
+ if (err < 0)
+ dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
+
+ panel_simple_remove(&dsi->dev);
+}
+
+static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
+{
+ panel_simple_shutdown(&dsi->dev);
+}
+
+static struct mipi_dsi_driver panel_simple_dsi_driver = {
+ .driver = {
+ .name = "panel-dsi-simple",
+ .of_match_table = dsi_of_match,
+ },
+ .probe = panel_simple_dsi_probe,
+ .remove = panel_simple_dsi_remove,
+ .shutdown = panel_simple_dsi_shutdown,
+};
+
+module_mipi_dsi_driver(panel_simple_dsi_driver);
+
+MODULE_AUTHOR("iamdrq <iamdrq@qq.com>");
+MODULE_DESCRIPTION("DRM Driver for DSI Simple Panels");
+MODULE_LICENSE("GPL");
--
Armbian

155
patch/kernel/rockchip64-6.14/general-add-pll-hdmi-timings.patch
View File

@ -1,155 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: paolo <paolo.sabatino@gmail.com>
Date: Sun, 17 Jan 2021 10:20:21 +0000
Subject: [ARCHEOLOGY] Adding pll hdmi timing to rockchip64-dev too
> X-Git-Archeology: > recovered message: > Fixed rk3328 mali node, shortening memory range to 0x30000 as per-stated in official documentation
> X-Git-Archeology: - Revision 3a037e899b06452043e23cd2a17f40fe1a932c5f: https://github.com/armbian/build/commit/3a037e899b06452043e23cd2a17f40fe1a932c5f
> X-Git-Archeology: Date: Sun, 17 Jan 2021 10:20:21 +0000
> X-Git-Archeology: From: paolo <paolo.sabatino@gmail.com>
> X-Git-Archeology: Subject: Adding pll hdmi timing to rockchip64-dev too
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125)
> X-Git-Archeology:
> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
> X-Git-Archeology:
> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 71 ++++++++++
1 file changed, 71 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 111111111111..222222222222 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -465,6 +465,77 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
{594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 1, 1, 0, 0x0},
{594000000, 371250000, 4, 495, 0, 3, 1, 1, 3, 0, 0, 1, 0x0},
{594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0x0},
+ { 25175000, 25175000, 30, 1007, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 31500000, 31500000, 1, 21, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 33750000, 33750000, 1, 45, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 35500000, 35500000, 3, 71, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 36000000, 36000000, 1, 12, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ { 49500000, 49500000, 1, 33, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 50000000, 50000000, 3, 50, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ { 56250000, 56250000, 1, 75, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 65000000, 65000000, 3, 65, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ { 68250000, 68250000, 1, 91, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 71000000, 71000000, 3, 71, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ { 72000000, 72000000, 1, 24, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ { 73250000, 73250000, 3, 293, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 75000000, 75000000, 1, 25, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ { 78750000, 78750000, 1, 105, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 79500000, 79500000, 1, 53, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 83500000, 83500000, 3, 167, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 85500000, 85500000, 1, 57, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 88750000, 88750000, 3, 355, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 94500000, 94500000, 1, 63, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {101000000, 101000000, 3, 101, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {102250000, 102250000, 3, 409, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {106500000, 106500000, 1, 71, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {108000000, 108000000, 1, 36, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {115500000, 115500000, 1, 77, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {117500000, 117500000, 3, 235, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {119000000, 119000000, 3, 119, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {121750000, 121750000, 3, 487, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {122500000, 122500000, 3, 245, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {135000000, 135000000, 1, 45, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {136750000, 136750000, 3, 547, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {140250000, 140250000, 1, 187, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {146250000, 146250000, 1, 195, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {148250000, 148250000, 3, 593, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {154000000, 154000000, 3, 154, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {156000000, 156000000, 1, 52, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {156750000, 156750000, 1, 209, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {157000000, 157000000, 3, 157, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {157500000, 157500000, 1, 105, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {162000000, 162000000, 1, 54, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {175500000, 175500000, 1, 117, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {179500000, 179500000, 3, 359, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {182750000, 182750000, 3, 731, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {187000000, 187000000, 3, 187, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {187250000, 187250000, 3, 749, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {189000000, 189000000, 1, 63, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {193250000, 193250000, 3, 773, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {202500000, 202500000, 1, 135, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {204750000, 204750000, 1, 273, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {208000000, 208000000, 3, 208, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {214750000, 214750000, 3, 859, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {218250000, 218250000, 1, 291, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {229500000, 229500000, 1, 153, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {234000000, 234000000, 1, 78, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {241500000, 241500000, 1, 161, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {245250000, 245250000, 1, 327, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {245500000, 245500000, 3, 491, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {261000000, 261000000, 1, 87, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {268250000, 268250000, 3, 1073, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {268500000, 268500000, 1, 179, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {281250000, 281250000, 1, 375, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {288000000, 288000000, 1, 96, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {312250000, 312250000, 3, 1249, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {317000000, 317000000, 3, 317, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {333250000, 333250000, 3, 1333, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {348500000, 348500000, 3, 697, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {356500000, 356500000, 3, 713, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {380500000, 380500000, 3, 761, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {443250000, 443250000, 1, 591, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {505250000, 505250000, 3, 2021, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {552750000, 552750000, 1, 737, 1, 2, 2, 1, 2, 3, 4, 0, 0},
{ /* sentinel */ }
};
--
Armbian

82
patch/kernel/rockchip64-6.14/general-add-xtx-spi-nor-chips.patch
View File

@ -1,82 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: microcai <microcaicai@gmail.com>
Date: Mon, 29 Jun 2020 23:36:40 +0800
Subject: spi-nor: Add support for xt25f32b/xt25f128b
The RockPi4b dev board ship with xt25f32b solded. add these ids so the
board's spi flash can be accessed within linux.
Signed-off-by: microcai <microcaicai@gmail.com>
---
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/core.c | 1 +
drivers/mtd/spi-nor/core.h | 1 +
drivers/mtd/spi-nor/xtx.c | 21 ++++++++++
4 files changed, 24 insertions(+)
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index 111111111111..222222222222 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -15,6 +15,7 @@ spi-nor-objs += sst.o
spi-nor-objs += winbond.o
spi-nor-objs += xmc.o
spi-nor-$(CONFIG_DEBUG_FS) += debugfs.o
+spi-nor-objs += xtx.o
obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
obj-$(CONFIG_MTD_SPI_NOR) += controllers/
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 111111111111..222222222222 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -1981,6 +1981,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
&spi_nor_sst,
&spi_nor_winbond,
&spi_nor_xmc,
+ &spi_nor_xtx,
};
static const struct flash_info spi_nor_generic_flash = {
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 111111111111..222222222222 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -598,6 +598,7 @@ extern const struct spi_nor_manufacturer spi_nor_spansion;
extern const struct spi_nor_manufacturer spi_nor_sst;
extern const struct spi_nor_manufacturer spi_nor_winbond;
extern const struct spi_nor_manufacturer spi_nor_xmc;
+extern const struct spi_nor_manufacturer spi_nor_xtx;
extern const struct attribute_group *spi_nor_sysfs_groups[];
diff --git a/drivers/mtd/spi-nor/xtx.c b/drivers/mtd/spi-nor/xtx.c
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/drivers/mtd/spi-nor/xtx.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2005, Intec Automation Inc.
+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
+ */
+
+#include <linux/mtd/spi-nor.h>
+
+#include "core.h"
+
+static const struct flash_info xtx_parts[] = {
+ /* XTX (Shenzhen Xin Tian Xia Tech) */
+ { "xt25f32b", SNOR_ID(0x0b, 0x40, 0x16) },
+ { "xt25f128b", SNOR_ID(0x0b, 0x40, 0x18) },
+};
+
+const struct spi_nor_manufacturer spi_nor_xtx = {
+ .name = "xtx",
+ .parts = xtx_parts,
+ .nparts = ARRAY_SIZE(xtx_parts),
+};
--
Armbian

28
patch/kernel/rockchip64-6.14/general-clk-rockchip-rk3568-Add-PLL-rate-for-33.3MHz.patch
View File

@ -1,28 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Vasily Khoruzhick <anarsoul@gmail.com>
Date: Mon, 17 Mar 2025 22:22:46 -0700
Subject: clk: rockchip: rk3568: Add PLL rate for 33.3MHz
Add PLL rate for 33.3 MHz to allow BTT HDMI5 screen to run at its native
mode of 800x480
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
drivers/clk/rockchip/clk-rk3568.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 111111111111..222222222222 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE(33300000, 4, 111, 5, 4, 1, 0),
{ /* sentinel */ },
};
--
Armbian

302
patch/kernel/rockchip64-6.14/general-cryptov1-trng.patch
View File

@ -1,302 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 14 Jan 2024 11:53:20 +0100
Subject: rockchip64: add TRNG to existing crypto v1 driver
original patch source: https://patchwork.kernel.org/project/linux-rockchip/patch/20230707115242.3411259-1-clabbe@baylibre.com/
---
drivers/crypto/Kconfig | 8 +
drivers/crypto/rockchip/Makefile | 1 +
drivers/crypto/rockchip/rk3288_crypto.c | 18 +-
drivers/crypto/rockchip/rk3288_crypto.h | 18 ++
drivers/crypto/rockchip/rk3288_crypto_ahash.c | 2 +
drivers/crypto/rockchip/rk3288_crypto_skcipher.c | 2 +
drivers/crypto/rockchip/rk3288_crypto_trng.c | 92 ++++++++++
7 files changed, 140 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 111111111111..222222222222 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -700,6 +700,14 @@ config CRYPTO_DEV_ROCKCHIP
This driver interfaces with the hardware crypto accelerator.
Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
+config CRYPTO_DEV_ROCKCHIP_TRNG
+ bool "Support for Rockchip TRNG"
+ depends on CRYPTO_DEV_ROCKCHIP
+ select HW_RANDOM
+ help
+ Select this option if you want to provide kernel-side support for
+ the True Random Number Generator found in the Crypto IP.
+
config CRYPTO_DEV_ROCKCHIP_DEBUG
bool "Enable Rockchip crypto stats"
depends on CRYPTO_DEV_ROCKCHIP
diff --git a/drivers/crypto/rockchip/Makefile b/drivers/crypto/rockchip/Makefile
index 111111111111..222222222222 100644
--- a/drivers/crypto/rockchip/Makefile
+++ b/drivers/crypto/rockchip/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o
rk_crypto-objs := rk3288_crypto.o \
rk3288_crypto_skcipher.o \
rk3288_crypto_ahash.o
+rk_crypto-$(CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG) += rk3288_crypto_trng.o
diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c
index 111111111111..222222222222 100644
--- a/drivers/crypto/rockchip/rk3288_crypto.c
+++ b/drivers/crypto/rockchip/rk3288_crypto.c
@@ -47,15 +47,18 @@ static const struct rk_variant rk3288_variant = {
.num_clks = 4,
.rkclks = {
{ "sclk", 150000000},
- }
+ },
+ .trng = false,
};
static const struct rk_variant rk3328_variant = {
.num_clks = 3,
+ .trng = false,
};
static const struct rk_variant rk3399_variant = {
.num_clks = 3,
+ .trng = true,
};
static int rk_crypto_get_clks(struct rk_crypto_info *dev)
@@ -201,6 +204,10 @@ static int rk_crypto_debugfs_show(struct seq_file *seq, void *v)
seq_printf(seq, "%s %s requests: %lu\n",
dev_driver_string(dd->dev), dev_name(dd->dev),
dd->nreq);
+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG
+ seq_printf(seq, "HWRNG: %lu %lu\n",
+ dd->hwrng_stat_req, dd->hwrng_stat_bytes);
+#endif
}
spin_unlock(&rocklist.lock);
@@ -395,6 +402,10 @@ static int rk_crypto_probe(struct platform_device *pdev)
dev_err(dev, "Fail to register crypto algorithms");
goto err_register_alg;
}
+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG
+ if (crypto_info->variant->trng)
+ rk3288_hwrng_register(crypto_info);
+#endif
register_debugfs(crypto_info);
}
@@ -425,6 +436,11 @@ static void rk_crypto_remove(struct platform_device *pdev)
#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG
debugfs_remove_recursive(rocklist.dbgfs_dir);
#endif
+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG
+ if (crypto_tmp->variant->trng)
+ rk3288_hwrng_unregister(crypto_tmp);
+#endif
+
rk_crypto_unregister();
}
rk_crypto_pm_exit(crypto_tmp);
diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h
index 111111111111..222222222222 100644
--- a/drivers/crypto/rockchip/rk3288_crypto.h
+++ b/drivers/crypto/rockchip/rk3288_crypto.h
@@ -11,6 +11,7 @@
#include <crypto/sha1.h>
#include <crypto/sha2.h>
#include <linux/dma-mapping.h>
+#include <linux/hw_random.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/scatterlist.h>
@@ -180,6 +181,16 @@
#define RK_CRYPTO_HASH_DOUT_6 0x01a4
#define RK_CRYPTO_HASH_DOUT_7 0x01a8
+#define RK_CRYPTO_TRNG_CTRL 0x0200
+#define RK_CRYPTO_OSC_ENABLE BIT(16)
+#define RK_CRYPTO_TRNG_DOUT_0 0x0204
+/* sample < 1000 lead to 100% failure on rngtest,
+ * using more than 1200 does not increase success.
+ */
+#define RK_CRYPTO_RNG_SAMPLE 1200
+
+#define RK_CRYPTO_MAX_TRNG_BYTE 32
+
#define CRYPTO_READ(dev, offset) \
readl_relaxed(((dev)->reg + (offset)))
#define CRYPTO_WRITE(dev, offset, val) \
@@ -209,6 +220,7 @@ struct rk_clks {
struct rk_variant {
int num_clks;
struct rk_clks rkclks[RK_MAX_CLKS];
+ bool trng;
};
struct rk_crypto_info {
@@ -219,11 +231,15 @@ struct rk_crypto_info {
struct reset_control *rst;
void __iomem *reg;
int irq;
+ struct mutex lock;
+ struct hwrng hwrng;
const struct rk_variant *variant;
unsigned long nreq;
struct crypto_engine *engine;
struct completion complete;
int status;
+ unsigned long hwrng_stat_req;
+ unsigned long hwrng_stat_bytes;
};
/* the private variable of hash */
@@ -283,3 +299,5 @@ extern struct rk_crypto_tmp rk_ahash_md5;
struct rk_crypto_info *get_rk_crypto(void);
#endif
+int rk3288_hwrng_register(struct rk_crypto_info *rk);
+void rk3288_hwrng_unregister(struct rk_crypto_info *rk);
diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c
index 111111111111..222222222222 100644
--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c
+++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c
@@ -296,6 +296,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq)
goto theend;
}
+ mutex_lock(&rkc->lock);
rk_ahash_reg_init(areq, rkc);
while (sg) {
@@ -330,6 +331,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq)
}
theend:
+ mutex_unlock(&rkc->lock);
pm_runtime_put_autosuspend(rkc->dev);
rk_hash_unprepare(engine, breq);
diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
index 111111111111..222222222222 100644
--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
+++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
@@ -363,6 +363,7 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req)
}
}
err = 0;
+ mutex_unlock(&rkc->lock);
rk_cipher_hw_init(rkc, areq);
if (ivsize) {
if (ivsize == DES_BLOCK_SIZE)
@@ -378,6 +379,7 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req)
crypto_dma_start(rkc, sgs, sgd, todo / 4);
wait_for_completion_interruptible_timeout(&rkc->complete,
msecs_to_jiffies(2000));
+ mutex_unlock(&rkc->lock);
if (!rkc->status) {
dev_err(rkc->dev, "DMA timeout\n");
err = -EFAULT;
diff --git a/drivers/crypto/rockchip/rk3288_crypto_trng.c b/drivers/crypto/rockchip/rk3288_crypto_trng.c
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/drivers/crypto/rockchip/rk3288_crypto_trng.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rk3288_crypto_trng.c - hardware cryptographic offloader for rockchip
+ *
+ * Copyright (C) 2022-2023 Corentin Labbe <clabbe@baylibre.com>
+ *
+ * This file handle the TRNG
+ */
+#include "rk3288_crypto.h"
+#include <linux/hw_random.h>
+#include <linux/iopoll.h>
+#include <linux/pm_runtime.h>
+
+static int rk3288_trng_read(struct hwrng *hwrng, void *data, size_t max, bool wait)
+{
+ struct rk_crypto_info *rk;
+ unsigned int todo;
+ int err = 0;
+ int i;
+ u32 v;
+
+ rk = container_of(hwrng, struct rk_crypto_info, hwrng);
+
+ todo = min_t(size_t, max, RK_CRYPTO_MAX_TRNG_BYTE);
+
+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG
+ rk->hwrng_stat_req++;
+ rk->hwrng_stat_bytes += todo;
+#endif
+
+ err = pm_runtime_resume_and_get(rk->dev);
+ if (err < 0)
+ goto err_pm;
+
+ mutex_lock(&rk->lock);
+
+#define HIWORD_UPDATE(val, mask, shift) \
+ ((val) << (shift) | (mask) << ((shift) + 16))
+ v = RK_CRYPTO_OSC_ENABLE | RK_CRYPTO_RNG_SAMPLE;
+ CRYPTO_WRITE(rk, RK_CRYPTO_TRNG_CTRL, v);
+
+ v = HIWORD_UPDATE(RK_CRYPTO_TRNG_START, RK_CRYPTO_TRNG_START, 0);
+ CRYPTO_WRITE(rk, RK_CRYPTO_CTRL, v);
+ wmb();
+
+ err = readl_poll_timeout(rk->reg + RK_CRYPTO_CTRL, v,
+ !(v & RK_CRYPTO_TRNG_START),
+ 100, 2000);
+ if (err) {
+ dev_err(rk->dev, "HWRNG read timeout");
+ goto readfail;
+ }
+
+ for (i = 0; i < todo / 4; i++) {
+ v = readl(rk->reg + RK_CRYPTO_TRNG_DOUT_0 + i * 4);
+ put_unaligned_le32(v, data + i * 4);
+ }
+
+ err = todo;
+
+ v = HIWORD_UPDATE(0, RK_CRYPTO_TRNG_START, 0);
+ CRYPTO_WRITE(rk, RK_CRYPTO_CTRL, v);
+
+readfail:
+ mutex_unlock(&rk->lock);
+
+ pm_runtime_put(rk->dev);
+
+err_pm:
+ return err;
+}
+
+int rk3288_hwrng_register(struct rk_crypto_info *rk)
+{
+ int ret;
+
+ dev_info(rk->dev, "Register TRNG with sample=%d\n", RK_CRYPTO_RNG_SAMPLE);
+
+ rk->hwrng.name = "Rockchip rk3288 TRNG";
+ rk->hwrng.read = rk3288_trng_read;
+ rk->hwrng.quality = 300;
+
+ ret = hwrng_register(&rk->hwrng);
+ if (ret)
+ dev_err(rk->dev, "Fail to register the TRNG\n");
+ return ret;
+}
+
+void rk3288_hwrng_unregister(struct rk_crypto_info *rk)
+{
+ hwrng_unregister(&rk->hwrng);
+}
--
Armbian

51
patch/kernel/rockchip64-6.14/general-disable-mtu-validation.patch
View File

@ -1,51 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Igor Pecovnik <igor.pecovnik@gmail.com>
Date: Wed, 21 Jul 2021 20:59:39 +0000
Subject: Disable MTU validation
This patch reverts: https://github.com/torvalds/linux/commit/eaf4fac478077d4ed57cbca2c044c4b58a96bd98
It works around following issues:
- no way to change MTU (tx_fifo_size is reported as 0 for Rockchip's dwmac)
Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 ----------
1 file changed, 12 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 111111111111..222222222222 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -5878,27 +5878,15 @@ static void stmmac_set_rx_mode(struct net_device *dev)
static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
{
struct stmmac_priv *priv = netdev_priv(dev);
- int txfifosz = priv->plat->tx_fifo_size;
struct stmmac_dma_conf *dma_conf;
const int mtu = new_mtu;
int ret;
- if (txfifosz == 0)
- txfifosz = priv->dma_cap.tx_fifo_size;
-
- txfifosz /= priv->plat->tx_queues_to_use;
-
if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
return -EINVAL;
}
- new_mtu = STMMAC_ALIGN(new_mtu);
-
- /* If condition true, FIFO is too small or MTU too large */
- if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
- return -EINVAL;
-
if (netif_running(dev)) {
netdev_dbg(priv->dev, "restarting interface to change its MTU\n");
/* Try to allocate the new DMA conf with the new mtu */
--
Armbian

1220
patch/kernel/rockchip64-6.14/general-driver-tm16xx-led-driver.patch
View File

File diff suppressed because it is too large Load Diff

39
patch/kernel/rockchip64-6.14/general-drm-rockchip-Set-dma-mask-to-64-bit.patch
View File

@ -1,39 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: SuperKali <hello@superkali.me>
Date: Fri, 7 Mar 2025 15:06:42 +0000
Subject: drm/rockchip: Set dma mask to 64 bit
The vop mmu support translate physical address upper 4 GB to iova
below 4 GB. So set dma mask to 64 bit to indicate we support address
> 4GB.
This can avoid warnging message like this on some boards with DDR
> 4 GB:
rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 130 (slots)
rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 0 (slots)
rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 130 (slots)
rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 130 (slots)
rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 0 (slots)
---
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -472,7 +472,9 @@ static int rockchip_drm_platform_probe(struct platform_device *pdev)
return ret;
}
- return 0;
+ ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
+
+ return ret;
}
static void rockchip_drm_platform_remove(struct platform_device *pdev)
--
Armbian

105
patch/kernel/rockchip64-6.14/general-fix-es8316-kernel-panic.patch
View File

@ -1,105 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Yannick Adam <yannick.adam@gmail.com>
Date: Tue, 14 Apr 2020 17:15:09 +0200
Subject: [ARCHEOLOGY] Enable es8316 on RockPi4 (#1885)
> X-Git-Archeology: - Revision 454038a50d1d24e636626213ad65b3463d632aa0: https://github.com/armbian/build/commit/454038a50d1d24e636626213ad65b3463d632aa0
> X-Git-Archeology: Date: Tue, 14 Apr 2020 17:15:09 +0200
> X-Git-Archeology: From: Yannick Adam <yannick.adam@gmail.com>
> X-Git-Archeology: Subject: Enable es8316 on RockPi4 (#1885)
> X-Git-Archeology:
> X-Git-Archeology: - Revision bd486c75623e75bdf2bdcaf09dc5a0affe9706c1: https://github.com/armbian/build/commit/bd486c75623e75bdf2bdcaf09dc5a0affe9706c1
> X-Git-Archeology: Date: Tue, 14 Apr 2020 20:14:24 +0200
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: Enable es8316 on RockPi4 for Rockchip64 current too https://github.com/armbian/build/pull/1885
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125)
> X-Git-Archeology:
> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4
> X-Git-Archeology: Date: Tue, 11 Jan 2022 15:26:11 +0100
> X-Git-Archeology: From: Oleg <balbes-150@yandex.ru>
> X-Git-Archeology: Subject: move kernel edge to 5.16 (#3387)
> X-Git-Archeology:
> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489)
> X-Git-Archeology:
> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41
> X-Git-Archeology: Date: Sun, 20 Mar 2022 22:58:21 +0100
> X-Git-Archeology: From: Oleg <balbes-150@yandex.ru>
> X-Git-Archeology: Subject: Adding Pine64 Quartz64a as WIP target (#3539)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c
> X-Git-Archeology: Date: Sun, 24 Apr 2022 22:33:47 +0200
> X-Git-Archeology: From: Oleg <balbes-150@yandex.ru>
> X-Git-Archeology: Subject: move kernel media edge to 5.17 (#3704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200
> X-Git-Archeology: From: Jianfeng Liu <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology:
---
sound/soc/codecs/es8316.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c
index 111111111111..222222222222 100644
--- a/sound/soc/codecs/es8316.c
+++ b/sound/soc/codecs/es8316.c
@@ -732,7 +732,7 @@ static void es8316_disable_jack_detect(struct snd_soc_component *component)
snd_soc_component_update_bits(component, ES8316_GPIO_DEBOUNCE,
ES8316_GPIO_ENABLE_INTERRUPT, 0);
- if (es8316->jack->status & SND_JACK_MICROPHONE) {
+ if (es8316->jack && (es8316->jack->status & SND_JACK_MICROPHONE)) {
es8316_disable_micbias_for_mic_gnd_short_detect(component);
snd_soc_jack_report(es8316->jack, 0, SND_JACK_BTN_0);
}
--
Armbian

28
patch/kernel/rockchip64-6.14/general-fix-inno-usb2-phy-init.patch
View File

@ -1,28 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Mon, 22 Aug 2022 20:51:22 +0000
Subject: remove usb2phy extcon initialization causing kernel oops
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 111111111111..222222222222 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1323,11 +1323,6 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
goto out;
}
- if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
- /* do initial sync of usb state */
- id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
- extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
- }
}
out:
--
Armbian

46
patch/kernel/rockchip64-6.14/general-fix-mmc-signal-voltage-before-reboot.patch
View File

@ -1,46 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 17 Feb 2019 22:14:38 +0000
Subject: mmc: core: set initial signal voltage on power off
Some boards have SD card connectors where the power rail cannot be switched
off by the driver. If the card has not been power cycled, it may still be
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
will fail to boot from a UHS card that continue to use 1.8V signaling.
Set initial signal voltage in mmc_power_off() to allow re-boot to function.
This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
same issue have been seen on some Rockchip RK3399 boards.
I am sending this as a RFC because I have no insights into SD/MMC subsystem,
this change fix a re-boot issue on my boards and does not break emmc/sdio.
Is this an acceptable workaround? Any advice is appreciated.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/mmc/core/core.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 111111111111..222222222222 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -1374,6 +1374,14 @@ void mmc_power_off(struct mmc_host *host)
if (host->ios.power_mode == MMC_POWER_OFF)
return;
+ mmc_set_initial_signal_voltage(host);
+
+ /*
+ * This delay should be sufficient to allow the power supply
+ * to reach the minimum voltage.
+ */
+ mmc_delay(host->ios.power_delay_ms);
+
mmc_pwrseq_power_off(host);
host->ios.clock = 0;
--
Armbian

257
patch/kernel/rockchip64-6.14/general-hdmi-clock-fixes.patch
View File

@ -1,257 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 6 Apr 2024 15:40:30 +0200
Subject: hdmi timing core changes and fixes
---
drivers/clk/rockchip/clk-rk3399.c | 49 ++++++++--
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 12 +--
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 42 ++++++++
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 7 ++
4 files changed, 97 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 111111111111..222222222222 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0, 4194304), /* vco = 1782000000 fout = 594000000 */
+ RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0, 2949838), /* vco = 1780219777 fout = 593406592.36908 */
+ RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640), /* vco = 1918500000 fout = 319750000 */
+ RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0, 4194304), /* vco = 1782000000 fout = 297000000 */
+ RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0, 2949838), /* vco = 1780219777 fout = 296703296.18454 */
+ RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0, 6291456), /* vco = 1449000000 fout = 241500000 */
+ RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0, 8388608), /* vco = 1620000000 fout = 162000000 */
+ RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0, 4194304), /* vco = 1782000000 fout = 148500000*/
+ RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0, 2949838), /* vco = 1780219777 fout = 148351648.09227 */
+ RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0, 6291456), /* vco = 1641000000 fout = 136750000 */
+ RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0, 4194304), /* vco = 1350000000 fout = 135000000 */
+ RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0, 8388608), /* vco = 1428000000 fout = 119000000 */
+ RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1, 0), /* vco = 1512000000 fout = 108000000 */
+ RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0, 2097152), /* vco = 1491000000 fout = 106500000 */
+ RK3036_PLL_RATE( 88750000, 1, 55, 5, 3, 0, 7864320), /* vco = 1331250000 fout = 88750000 */
+ RK3036_PLL_RATE( 85500000, 1, 57, 4, 4, 1, 0), /* vco = 1368000000 fout = 85500000 */
+ RK3036_PLL_RATE( 78750000, 1, 59, 6, 3, 0, 1048576), /* vco = 1417500000 fout = 78750000 */
+ RK3036_PLL_RATE( 74250000, 1, 74, 6, 4, 0, 4194304), /* vco = 1782000000 fout = 74250000 */
+ RK3036_PLL_RATE( 74175824, 1, 74, 6, 4, 0, 2949838), /* vco = 1780219777 fout = 74175824.046135 */
+ RK3036_PLL_RATE( 71000000, 1, 71, 6, 4, 1, 0), /* vco = 1704000000 fout = 71000000 */
+ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 0, 0), /* vco = 1560000000 fout = 65000000 */
+ RK3036_PLL_RATE( 59340659, 1, 59, 6, 4, 0, 5715310), /* vco = 1424175816 fout = 59340659.022331 */
+ RK3036_PLL_RATE( 54000000, 1, 63, 7, 4, 1, 0), /* vco = 1512000000 fout = 54000000 */
+ RK3036_PLL_RATE( 49500000, 1, 72, 5, 7, 0, 3145728), /* vco = 1732500000 fout = 49500000 */
+ RK3036_PLL_RATE( 40000000, 1, 70, 7, 6, 1, 0), /* vco = 1680000000 fout = 40000000 */
+ RK3036_PLL_RATE( 31500000, 1, 55, 7, 6, 0, 2097152), /* vco = 1323000000 fout = 31500000 */
+ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 fout = 27000000 */
+ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173214), /* vco = 1321678296 fout = 26973026.450799 */
+ { /* sentinel */ },
+};
+
/* CRU parents */
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
"gpll_aclk_cci_src",
"npll_aclk_cci_src",
- "vpll_aclk_cci_src" };
+ "prevent:vpll" };
PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
"gpll_cci_trace" };
PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
"ppll", "upll", "xin24m" };
-PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
-PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
+PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "prevent:vpll", "cpll", "gpll" };
+PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "prevent:cpll", "prevent:gpll" };
+
+PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "prevent:vpll", "cpll", "gpll",
"npll" };
-PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
+PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "prevent:vpll", "cpll", "gpll",
"xin24m" };
PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
- RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
+ RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates),
};
static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
- MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
+ MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(28), 0, GFLAGS),
- COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
+ COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3399_CLKGATE_CON(10), 12, GFLAGS),
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -69,15 +69,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
};
static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
- { 0x2591, 0x1322, 0x074b, 0x0000 },
- { 0x6535, 0x2000, 0x7acc, 0x0200 },
- { 0x6acd, 0x7534, 0x2000, 0x0200 }
+ { 0x2040, 0x1080, 0x0640, 0x0040 },
+ { 0xe880, 0x1c00, 0xfb80, 0x0200 },
+ { 0xed80, 0xf680, 0x1c00, 0x0200 }
};
static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
- { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
- { 0x62f0, 0x2000, 0x7d11, 0x0200 },
- { 0x6756, 0x78ab, 0x2000, 0x0200 }
+ { 0x2740, 0x0bc0, 0x0400, 0x0040 },
+ { 0xe680, 0x1c00, 0xfd80, 0x0200 },
+ { 0xea40, 0xf980, 0x1c00, 0x0200 }
};
static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -178,6 +178,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
}
};
+static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = {
+ {
+ 30666000, {
+ { 0x00b7, 0x0000 },
+ { 0x2157, 0x0000 },
+ { 0x40f7, 0x0000 },
+ },
+ }, {
+ 92000000, {
+ { 0x00b7, 0x0000 },
+ { 0x2143, 0x0001 },
+ { 0x40a3, 0x0001 },
+ },
+ }, {
+ 184000000, {
+ { 0x0073, 0x0001 },
+ { 0x2146, 0x0002 },
+ { 0x4062, 0x0002 },
+ },
+ }, {
+ 340000000, {
+ { 0x0052, 0x0003 },
+ { 0x214d, 0x0003 },
+ { 0x4065, 0x0003 },
+ },
+ }, {
+ 600000000, {
+ { 0x0041, 0x0003 },
+ { 0x3b4d, 0x0003 },
+ { 0x5a65, 0x0003 },
+ },
+ }, {
+ ~0UL, {
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ },
+ }
+};
+
static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
/* pixelclk bpp8 bpp10 bpp12 */
{
@@ -343,6 +383,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display);
+ dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display);
+
return phy_power_on(hdmi->phy);
}
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -765,6 +765,7 @@ static const struct vop_intr rk3288_vop_intr = {
static const struct vop_data rk3288_vop = {
.version = VOP_VERSION(3, 1),
.feature = VOP_FEATURE_OUTPUT_RGB10,
+ .max_output = { 3840, 2160 },
.intr = &rk3288_vop_intr,
.common = &rk3288_common,
.modeset = &rk3288_modeset,
@@ -872,6 +873,7 @@ static const struct vop_misc rk3368_misc = {
static const struct vop_data rk3368_vop = {
.version = VOP_VERSION(3, 2),
+ .max_output = { 4096, 2160 },
.intr = &rk3368_vop_intr,
.common = &rk3288_common,
.modeset = &rk3288_modeset,
@@ -894,6 +896,7 @@ static const struct vop_intr rk3366_vop_intr = {
static const struct vop_data rk3366_vop = {
.version = VOP_VERSION(3, 4),
+ .max_output = { 4096, 2160 },
.intr = &rk3366_vop_intr,
.common = &rk3288_common,
.modeset = &rk3288_modeset,
@@ -1047,6 +1050,7 @@ static const struct vop_afbc rk3399_vop_afbc = {
static const struct vop_data rk3399_vop_big = {
.version = VOP_VERSION(3, 5),
.feature = VOP_FEATURE_OUTPUT_RGB10,
+ .max_output = { 4096, 2160 },
.intr = &rk3366_vop_intr,
.common = &rk3399_common,
.modeset = &rk3288_modeset,
@@ -1075,6 +1079,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = {
static const struct vop_data rk3399_vop_lit = {
.version = VOP_VERSION(3, 6),
+ .max_output = { 2560, 1600 },
.intr = &rk3366_vop_intr,
.common = &rk3399_common,
.modeset = &rk3288_modeset,
@@ -1097,6 +1102,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = {
static const struct vop_data rk3228_vop = {
.version = VOP_VERSION(3, 7),
.feature = VOP_FEATURE_OUTPUT_RGB10,
+ .max_output = { 4096, 2160 },
.intr = &rk3366_vop_intr,
.common = &rk3288_common,
.modeset = &rk3288_modeset,
@@ -1169,6 +1175,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = {
static const struct vop_data rk3328_vop = {
.version = VOP_VERSION(3, 8),
.feature = VOP_FEATURE_OUTPUT_RGB10,
+ .max_output = { 4096, 2160 },
.intr = &rk3328_vop_intr,
.common = &rk3328_common,
.modeset = &rk3328_modeset,
--
Armbian

25
patch/kernel/rockchip64-6.14/general-increase-spdif-dma-burst.patch
View File

@ -1,25 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 12 Jan 2025 12:39:03 +0100
Subject: rockchip: increase SPDIF max burst value to maximum
---
sound/soc/rockchip/rockchip_spdif.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c
index 111111111111..222222222222 100644
--- a/sound/soc/rockchip/rockchip_spdif.c
+++ b/sound/soc/rockchip/rockchip_spdif.c
@@ -329,7 +329,7 @@ static int rk_spdif_probe(struct platform_device *pdev)
spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
- spdif->playback_dma_data.maxburst = 4;
+ spdif->playback_dma_data.maxburst = 8;
spdif->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, spdif);
--
Armbian

140
patch/kernel/rockchip64-6.14/general-increasing_DMA_block_memory_allocation_to_2048.patch
View File

@ -1,140 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Igor Pecovnik <igor.pecovnik@gmail.com>
Date: Mon, 21 Aug 2017 08:54:53 +0200
Subject: [ARCHEOLOGY] Increasing DMA block memory allocation to 2048k on all
relevant kernels.
> X-Git-Archeology: > recovered message: > https://forum.armbian.com/index.php?/topic/4811-uas-mainline-kernel-coherent-pool-memory-size
> X-Git-Archeology: - Revision 908bb199ec2defd77f7f05d2016980abf100d627: https://github.com/armbian/build/commit/908bb199ec2defd77f7f05d2016980abf100d627
> X-Git-Archeology: Date: Mon, 21 Aug 2017 08:54:53 +0200
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: Increasing DMA block memory allocation to 2048k on all relevant kernels.
> X-Git-Archeology:
> X-Git-Archeology: - Revision a3cf7b74858e1f862db8ca238bd44f6406be6662: https://github.com/armbian/build/commit/a3cf7b74858e1f862db8ca238bd44f6406be6662
> X-Git-Archeology: Date: Mon, 21 Aug 2017 17:52:29 +0200
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: Revert "Increasing DMA block memory allocation to 2048k on all relevant kernels."
> X-Git-Archeology:
> X-Git-Archeology: - Revision 2be21aad5dc965b3bc67e136a1e1170119d60f74: https://github.com/armbian/build/commit/2be21aad5dc965b3bc67e136a1e1170119d60f74
> X-Git-Archeology: Date: Mon, 21 Aug 2017 17:52:48 +0200
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: Increasing DMA block memory allocation to 2048k on all relevant kernels. https://forum.armbian.com/index.php?/topic/4811-uas-mainline-kernel-coherent-pool-memory-size
> X-Git-Archeology:
> X-Git-Archeology: - Revision b3d2bd4864d89ce032344051e6ced2ba9371084b: https://github.com/armbian/build/commit/b3d2bd4864d89ce032344051e6ced2ba9371084b
> X-Git-Archeology: Date: Wed, 30 Aug 2017 05:42:08 +0000
> X-Git-Archeology: From: Tonymac32 <tonymckahan@gmail.com>
> X-Git-Archeology: Subject: Meson64 Dev increase DMA block memory allocation
> X-Git-Archeology:
> X-Git-Archeology: - Revision 2c59bb9934b749b5df74d4134cd393dc24fd5160: https://github.com/armbian/build/commit/2c59bb9934b749b5df74d4134cd393dc24fd5160
> X-Git-Archeology: Date: Mon, 18 Sep 2017 12:06:30 +0200
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: Lepotato. Added NEXT, added patches from C2 NEXT, au, config update, removed deprecated patches, ...
> X-Git-Archeology:
> X-Git-Archeology: - Revision 13e94e58f04be27db51d18b7dac1d15a1864b79e: https://github.com/armbian/build/commit/13e94e58f04be27db51d18b7dac1d15a1864b79e
> X-Git-Archeology: Date: Fri, 27 Oct 2017 16:14:21 +0300
> X-Git-Archeology: From: zador-blood-stained <zador-blood-stained@users.noreply.github.com>
> X-Git-Archeology: Subject: Remove random executable bits from patch files
> X-Git-Archeology:
> X-Git-Archeology: - Revision 2c08ec8f5a210de35f9482f482ac01ea15381792: https://github.com/armbian/build/commit/2c08ec8f5a210de35f9482f482ac01ea15381792
> X-Git-Archeology: Date: Thu, 24 May 2018 13:32:29 +0200
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: Merge sunxi family into stable
> X-Git-Archeology:
> X-Git-Archeology: - Revision 7d2f3af08f23049c91c88eec5062613bbfbc85d4: https://github.com/armbian/build/commit/7d2f3af08f23049c91c88eec5062613bbfbc85d4
> X-Git-Archeology: Date: Thu, 24 May 2018 15:44:15 +0200
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: Merging Rockchip family
> X-Git-Archeology:
> X-Git-Archeology: - Revision 99a34c7be1e342247a981f99c7930ee73c144f3e: https://github.com/armbian/build/commit/99a34c7be1e342247a981f99c7930ee73c144f3e
> X-Git-Archeology: Date: Tue, 26 Jun 2018 12:47:49 +0000
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: Move Odroid C2 from 4.14.y to 4.16.y, added patch for ethernet, DEV to master, both tested ... not perfect but in a better condition.
> X-Git-Archeology:
> X-Git-Archeology: - Revision fcb85f17675990514d8fadc905e6ccc3bded7138: https://github.com/armbian/build/commit/fcb85f17675990514d8fadc905e6ccc3bded7138
> X-Git-Archeology: Date: Thu, 28 Jun 2018 08:27:08 +0000
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: Major Amlogic RFC and cleanup
> X-Git-Archeology:
> X-Git-Archeology: - Revision c57ebd663cf1b15ad193d4a761f9c044ba3b2acf: https://github.com/armbian/build/commit/c57ebd663cf1b15ad193d4a761f9c044ba3b2acf
> X-Git-Archeology: Date: Tue, 17 Jul 2018 16:11:07 +0200
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: - attach Odroid XU4 4.14.y back to Hardkernel kernel branch
> X-Git-Archeology:
> X-Git-Archeology: - Revision a26ccdee627f1fa27b3285e3840434cddb5aae62: https://github.com/armbian/build/commit/a26ccdee627f1fa27b3285e3840434cddb5aae62
> X-Git-Archeology: Date: Wed, 07 Nov 2018 11:11:51 +0100
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: [odroid xu4] Drop kernel 3.10.y, default -> offical 4.14.y, next = vanilla 4.19.y http://ix.io/1rcZ & dev = n/a
> X-Git-Archeology:
> X-Git-Archeology: - Revision a156fddf8f5bb5a6ac28ffc528ba0ec28ff9df81: https://github.com/armbian/build/commit/a156fddf8f5bb5a6ac28ffc528ba0ec28ff9df81
> X-Git-Archeology: Date: Fri, 18 Jan 2019 20:10:35 +0100
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: [ odroidxu4 ] Reverting NEXT back to stock 4.14.y due to many troubles, DEV = 4.19.y
> X-Git-Archeology:
> X-Git-Archeology: - Revision 79c1c2781915c59bd24576af92b9dbe57da24fac: https://github.com/armbian/build/commit/79c1c2781915c59bd24576af92b9dbe57da24fac
> X-Git-Archeology: Date: Fri, 17 May 2019 10:46:57 +0200
> X-Git-Archeology: From: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: Subject: [ odroidxu4 dev ] Move to 5.1.y
> X-Git-Archeology:
> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3
> X-Git-Archeology: Date: Tue, 19 Nov 2019 23:25:39 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Remove K<4, change branches, new features (#1586)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5: https://github.com/armbian/build/commit/4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5
> X-Git-Archeology: Date: Wed, 02 Sep 2020 23:22:09 +0200
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Switched rockchip64 curent to kernel 5.8.y (#2175)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575)
> X-Git-Archeology:
> X-Git-Archeology: - Revision e4d413b9166e3633b40fb23382fb1045b9d0e315: https://github.com/armbian/build/commit/e4d413b9166e3633b40fb23382fb1045b9d0e315
> X-Git-Archeology: Date: Tue, 26 Mar 2024 13:46:35 +0100
> X-Git-Archeology: From: Paolo Sabatino <paolo.sabatino@gmail.com>
> X-Git-Archeology: Subject: rockchip64: bump edge kernel to 6.8
> X-Git-Archeology:
> X-Git-Archeology: - Revision 69ca2492628b2aae217c33fde921b3840851eb14: https://github.com/armbian/build/commit/69ca2492628b2aae217c33fde921b3840851eb14
> X-Git-Archeology: Date: Wed, 05 Jun 2024 22:18:24 +0200
> X-Git-Archeology: From: Paolo Sabatino <paolo.sabatino@gmail.com>
> X-Git-Archeology: Subject: rockchip64: bump edge kernel to 6.9
> X-Git-Archeology:
> X-Git-Archeology: - Revision 4ae0a958146810117050d0dbd359b99691a0fa0c: https://github.com/armbian/build/commit/4ae0a958146810117050d0dbd359b99691a0fa0c
> X-Git-Archeology: Date: Mon, 22 Jul 2024 19:17:52 +0200
> X-Git-Archeology: From: Paolo Sabatino <paolo.sabatino@gmail.com>
> X-Git-Archeology: Subject: rockchip64: bump edge kernel to 6.10
> X-Git-Archeology:
---
kernel/dma/pool.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/kernel/dma/pool.c b/kernel/dma/pool.c
index 111111111111..222222222222 100644
--- a/kernel/dma/pool.c
+++ b/kernel/dma/pool.c
@@ -189,13 +189,11 @@ static int __init dma_atomic_pool_init(void)
int ret = 0;
/*
- * If coherent_pool was not used on the command line, default the pool
- * sizes to 128KB per 1GB of memory, min 128KB, max MAX_PAGE_ORDER.
+ * Always use 2MiB as default pool size.
+ * See: https://forum.armbian.com/topic/4811-uas-mainline-kernel-coherent-pool-memory-size/
*/
if (!atomic_pool_size) {
- unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
- pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES);
- atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K);
+ atomic_pool_size = SZ_2M;
}
INIT_WORK(&atomic_pool_work, atomic_pool_work_fn);
--
Armbian

421
patch/kernel/rockchip64-6.14/general-pl330-01-fix-periodic-transfers.patch
View File

@ -1,421 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 12 Jan 2025 12:36:50 +0100
Subject: pl330: fix dma engine periodic transfers
---
drivers/dma/pl330.c | 277 +++++++---
1 file changed, 186 insertions(+), 91 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 111111111111..222222222222 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -239,6 +239,7 @@ enum pl330_byteswap {
#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
+#define BYTE_MOD_BURST_LEN(b, ccr) (((b) / BRST_SIZE(ccr)) % BRST_LEN(ccr))
/*
* With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
@@ -455,9 +456,6 @@ struct dma_pl330_chan {
enum dma_data_direction dir;
struct dma_slave_config slave_config;
- /* for cyclic capability */
- bool cyclic;
-
/* for runtime pm tracking */
bool active;
};
@@ -545,6 +543,10 @@ struct dma_pl330_desc {
unsigned peri:5;
/* Hook to attach to DMAC's list of reqs with due callback */
struct list_head rqd;
+
+ /* For cyclic capability */
+ bool cyclic;
+ size_t num_periods;
};
struct _xfer_spec {
@@ -1368,6 +1370,108 @@ static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
return off;
}
+static int _period(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
+ unsigned long bursts, const struct _xfer_spec *pxs, int ev)
+{
+ unsigned int lcnt1, ljmp1;
+ int cyc, off = 0, num_dregs = 0;
+ struct _arg_LPEND lpend;
+ struct pl330_xfer *x = &pxs->desc->px;
+
+ if (bursts > 256) {
+ lcnt1 = 256;
+ cyc = bursts / 256;
+ } else {
+ lcnt1 = bursts;
+ cyc = 1;
+ }
+
+ /* loop1 */
+ off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
+ ljmp1 = off;
+ off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
+ lpend.cond = ALWAYS;
+ lpend.forever = false;
+ lpend.loop = 1;
+ lpend.bjump = off - ljmp1;
+ off += _emit_LPEND(dry_run, &buf[off], &lpend);
+
+ /* remainder */
+ lcnt1 = bursts - (lcnt1 * cyc);
+
+ if (lcnt1) {
+ off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
+ ljmp1 = off;
+ off += _bursts(pl330, dry_run, &buf[off], pxs, 1);
+ lpend.cond = ALWAYS;
+ lpend.forever = false;
+ lpend.loop = 1;
+ lpend.bjump = off - ljmp1;
+ off += _emit_LPEND(dry_run, &buf[off], &lpend);
+ }
+
+ num_dregs = BYTE_MOD_BURST_LEN(x->bytes, pxs->ccr);
+
+ if (num_dregs) {
+ off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
+ off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
+ }
+
+ off += _emit_SEV(dry_run, &buf[off], ev);
+
+ return off;
+}
+
+static inline int _loop_cyclic(struct pl330_dmac *pl330, unsigned int dry_run,
+ u8 buf[], unsigned long bursts,
+ const struct _xfer_spec *pxs, int ev)
+{
+ int off, periods, residue, i;
+ unsigned int lcnt0, ljmp0, ljmpfe;
+ struct _arg_LPEND lpend;
+ struct pl330_xfer *x = &pxs->desc->px;
+
+ off = 0;
+ ljmpfe = off;
+ lcnt0 = pxs->desc->num_periods;
+ periods = 1;
+
+ while (lcnt0 > 256) {
+ periods++;
+ lcnt0 = pxs->desc->num_periods / periods;
+ }
+
+ residue = pxs->desc->num_periods % periods;
+
+ /* forever loop */
+ off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
+ off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
+
+ /* loop0 */
+ off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
+ ljmp0 = off;
+
+ for (i = 0; i < periods; i++)
+ off += _period(pl330, dry_run, &buf[off], bursts, pxs, ev);
+
+ lpend.cond = ALWAYS;
+ lpend.forever = false;
+ lpend.loop = 0;
+ lpend.bjump = off - ljmp0;
+ off += _emit_LPEND(dry_run, &buf[off], &lpend);
+
+ for (i = 0; i < residue; i++)
+ off += _period(pl330, dry_run, &buf[off], bursts, pxs, ev);
+
+ lpend.cond = ALWAYS;
+ lpend.forever = true;
+ lpend.loop = 1;
+ lpend.bjump = off - ljmpfe;
+ off += _emit_LPEND(dry_run, &buf[off], &lpend);
+
+ return off;
+}
+
static inline int _setup_loops(struct pl330_dmac *pl330,
unsigned dry_run, u8 buf[],
const struct _xfer_spec *pxs)
@@ -1407,6 +1511,21 @@ static inline int _setup_xfer(struct pl330_dmac *pl330,
return off;
}
+static inline int _setup_xfer_cyclic(struct pl330_dmac *pl330,
+ unsigned int dry_run, u8 buf[],
+ const struct _xfer_spec *pxs, int ev)
+{
+ struct pl330_xfer *x = &pxs->desc->px;
+ u32 ccr = pxs->ccr;
+ unsigned long bursts = BYTE_TO_BURST(x->bytes, ccr);
+ int off = 0;
+
+ /* Setup Loop(s) */
+ off += _loop_cyclic(pl330, dry_run, &buf[off], bursts, pxs, ev);
+
+ return off;
+}
+
/*
* A req is a sequence of one or more xfer units.
* Returns the number of bytes taken to setup the MC for the req.
@@ -1424,12 +1543,17 @@ static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
/* DMAMOV CCR, ccr */
off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
- off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
+ if (!pxs->desc->cyclic) {
+ off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
- /* DMASEV peripheral/event */
- off += _emit_SEV(dry_run, &buf[off], thrd->ev);
- /* DMAEND */
- off += _emit_END(dry_run, &buf[off]);
+ /* DMASEV peripheral/event */
+ off += _emit_SEV(dry_run, &buf[off], thrd->ev);
+ /* DMAEND */
+ off += _emit_END(dry_run, &buf[off]);
+ } else {
+ off += _setup_xfer_cyclic(pl330, dry_run, &buf[off],
+ pxs, thrd->ev);
+ }
return off;
}
@@ -1703,15 +1827,17 @@ static int pl330_update(struct pl330_dmac *pl330)
/* Detach the req */
descdone = thrd->req[active].desc;
- thrd->req[active].desc = NULL;
-
- thrd->req_running = -1;
-
- /* Get going again ASAP */
- pl330_start_thread(thrd);
-
- /* For now, just make a list of callbacks to be done */
- list_add_tail(&descdone->rqd, &pl330->req_done);
+ if (descdone) {
+ if (!descdone->cyclic) {
+ thrd->req[active].desc = NULL;
+ thrd->req_running = -1;
+ /* Get going again ASAP */
+ pl330_start_thread(thrd);
+ }
+
+ /* For now, just make a list of callbacks to be done */
+ list_add_tail(&descdone->rqd, &pl330->req_done);
+ }
}
}
@@ -2076,12 +2202,25 @@ static void pl330_tasklet(struct tasklet_struct *t)
spin_lock_irqsave(&pch->lock, flags);
/* Pick up ripe tomatoes */
- list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
+ list_for_each_entry_safe(desc, _dt, &pch->work_list, node) {
if (desc->status == DONE) {
- if (!pch->cyclic)
+ if (!desc->cyclic) {
dma_cookie_complete(&desc->txd);
- list_move_tail(&desc->node, &pch->completed_list);
+ list_move_tail(&desc->node, &pch->completed_list);
+ } else {
+ struct dmaengine_desc_callback cb;
+
+ desc->status = BUSY;
+ dmaengine_desc_get_callback(&desc->txd, &cb);
+
+ if (dmaengine_desc_callback_valid(&cb)) {
+ spin_unlock_irqrestore(&pch->lock, flags);
+ dmaengine_desc_callback_invoke(&cb, NULL);
+ spin_lock_irqsave(&pch->lock, flags);
+ }
+ }
}
+ }
/* Try to submit a req imm. next to the last completed cookie */
fill_queue(pch);
@@ -2107,20 +2246,8 @@ static void pl330_tasklet(struct tasklet_struct *t)
dmaengine_desc_get_callback(&desc->txd, &cb);
- if (pch->cyclic) {
- desc->status = PREP;
- list_move_tail(&desc->node, &pch->work_list);
- if (power_down) {
- pch->active = true;
- spin_lock(&pch->thread->dmac->lock);
- pl330_start_thread(pch->thread);
- spin_unlock(&pch->thread->dmac->lock);
- power_down = false;
- }
- } else {
- desc->status = FREE;
- list_move_tail(&desc->node, &pch->dmac->desc_pool);
- }
+ desc->status = FREE;
+ list_move_tail(&desc->node, &pch->dmac->desc_pool);
dma_descriptor_unmap(&desc->txd);
@@ -2168,7 +2295,6 @@ static int pl330_alloc_chan_resources(struct dma_chan *chan)
spin_lock_irqsave(&pl330->lock, flags);
dma_cookie_init(chan);
- pch->cyclic = false;
pch->thread = pl330_request_channel(pl330);
if (!pch->thread) {
@@ -2367,8 +2493,7 @@ static void pl330_free_chan_resources(struct dma_chan *chan)
pl330_release_channel(pch->thread);
pch->thread = NULL;
- if (pch->cyclic)
- list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
+ list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
spin_unlock_irqrestore(&pl330->lock, flags);
pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
@@ -2431,7 +2556,7 @@ pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
/* Check in pending list */
list_for_each_entry(desc, &pch->work_list, node) {
- if (desc->status == DONE)
+ if (desc->status == DONE && !desc->cyclic)
transferred = desc->bytes_requested;
else if (running && desc == running)
transferred =
@@ -2516,10 +2641,7 @@ static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
/* Assign cookies to all nodes */
while (!list_empty(&last->node)) {
desc = list_entry(last->node.next, struct dma_pl330_desc, node);
- if (pch->cyclic) {
- desc->txd.callback = last->txd.callback;
- desc->txd.callback_param = last->txd.callback_param;
- }
+
desc->last = false;
dma_cookie_assign(&desc->txd);
@@ -2622,6 +2744,9 @@ static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
desc->peri = peri_id ? pch->chan.chan_id : 0;
desc->rqcfg.pcfg = &pch->dmac->pcfg;
+ desc->cyclic = false;
+ desc->num_periods = 1;
+
dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
return desc;
@@ -2685,12 +2810,10 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
size_t period_len, enum dma_transfer_direction direction,
unsigned long flags)
{
- struct dma_pl330_desc *desc = NULL, *first = NULL;
+ struct dma_pl330_desc *desc = NULL;
struct dma_pl330_chan *pch = to_pchan(chan);
- struct pl330_dmac *pl330 = pch->dmac;
- unsigned int i;
- dma_addr_t dst;
- dma_addr_t src;
+ dma_addr_t dst = 0;
+ dma_addr_t src = 0;
if (len % period_len != 0)
return NULL;
@@ -2706,33 +2829,14 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
if (!pl330_prep_slave_fifo(pch, direction))
return NULL;
- for (i = 0; i < len / period_len; i++) {
- desc = pl330_get_desc(pch);
- if (!desc) {
- unsigned long iflags;
-
- dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
- __func__, __LINE__);
-
- if (!first)
- return NULL;
-
- spin_lock_irqsave(&pl330->pool_lock, iflags);
-
- while (!list_empty(&first->node)) {
- desc = list_entry(first->node.next,
- struct dma_pl330_desc, node);
- list_move_tail(&desc->node, &pl330->desc_pool);
- }
-
- list_move_tail(&first->node, &pl330->desc_pool);
-
- spin_unlock_irqrestore(&pl330->pool_lock, iflags);
-
- return NULL;
- }
+ desc = pl330_get_desc(pch);
+ if (!desc) {
+ dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
+ __func__, __LINE__);
+ return NULL;
+ }
- switch (direction) {
+ switch (direction) {
case DMA_MEM_TO_DEV:
desc->rqcfg.src_inc = 1;
desc->rqcfg.dst_inc = 0;
@@ -2746,27 +2850,18 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
dst = dma_addr;
break;
default:
- break;
- }
-
- desc->rqtype = direction;
- desc->rqcfg.brst_size = pch->burst_sz;
- desc->rqcfg.brst_len = pch->burst_len;
- desc->bytes_requested = period_len;
- fill_px(&desc->px, dst, src, period_len);
-
- if (!first)
- first = desc;
- else
- list_add_tail(&desc->node, &first->node);
-
- dma_addr += period_len;
+ break;
}
- if (!desc)
- return NULL;
+ desc->rqtype = direction;
+ desc->rqcfg.brst_size = pch->burst_sz;
+ desc->rqcfg.brst_len = pch->burst_len;
+ desc->bytes_requested = len;
+ fill_px(&desc->px, dst, src, period_len);
- pch->cyclic = true;
+ desc->cyclic = true;
+ desc->num_periods = len / period_len;
+ desc->txd.flags = flags;
return &desc->txd;
}
--
Armbian

261
patch/kernel/rockchip64-6.14/general-pl330-02-add-support-for-interleaved-transfers.patch
View File

@ -1,261 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Thu, 23 Jan 2025 20:23:50 +0100
Subject: rockchip/64: pl330 - add support for interleaved transfers
original source: https://patchwork.kernel.org/project/linux-rockchip/cover/1712150304-60832-1-git-send-email-sugar.zhang@rock-chips.com/
---
drivers/dma/pl330.c | 168 +++++++++-
include/linux/dmaengine.h | 1 +
2 files changed, 163 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 111111111111..222222222222 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -543,6 +543,8 @@ struct dma_pl330_desc {
unsigned peri:5;
/* Hook to attach to DMAC's list of reqs with due callback */
struct list_head rqd;
+ /* interleaved size */
+ struct data_chunk sgl;
/* For cyclic capability */
bool cyclic;
@@ -579,6 +581,22 @@ static inline u32 get_revision(u32 periph_id)
return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
}
+static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
+ enum pl330_dst da, u16 val)
+{
+ if (dry_run)
+ return SZ_DMAADDH;
+
+ buf[0] = CMD_DMAADDH;
+ buf[0] |= (da << 1);
+ *((__le16 *)&buf[1]) = cpu_to_le16(val);
+
+ PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
+ da == 1 ? "DA" : "SA", val);
+
+ return SZ_DMAADDH;
+}
+
static inline u32 _emit_END(unsigned dry_run, u8 buf[])
{
if (dry_run)
@@ -1189,7 +1207,7 @@ static inline int _ldst_peripheral(struct pl330_dmac *pl330,
const struct _xfer_spec *pxs, int cyc,
enum pl330_cond cond)
{
- int off = 0;
+ int off = 0, i = 0, burstn = 1;
/*
* do FLUSHP at beginning to clear any stale dma requests before the
@@ -1197,12 +1215,36 @@ static inline int _ldst_peripheral(struct pl330_dmac *pl330,
*/
if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
+
+ if (pxs->desc->sgl.size) {
+ WARN_ON(BYTE_MOD_BURST_LEN(pxs->desc->sgl.size, pxs->ccr));
+ burstn = BYTE_TO_BURST(pxs->desc->sgl.size, pxs->ccr);
+ }
+
while (cyc--) {
- off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
- off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
- pxs->desc->peri);
- off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
- pxs->desc->peri);
+ for (i = 0; i < burstn; i++) {
+ off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
+ off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
+ pxs->desc->peri);
+ off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
+ pxs->desc->peri);
+ }
+
+ switch (pxs->desc->rqtype) {
+ case DMA_DEV_TO_MEM:
+ if (pxs->desc->sgl.dst_icg)
+ off += _emit_ADDH(dry_run, &buf[off], DST,
+ pxs->desc->sgl.dst_icg);
+ break;
+ case DMA_MEM_TO_DEV:
+ if (pxs->desc->sgl.src_icg)
+ off += _emit_ADDH(dry_run, &buf[off], SRC,
+ pxs->desc->sgl.src_icg);
+ break;
+ default:
+ WARN_ON(1);
+ break;
+ }
}
return off;
@@ -1483,6 +1525,9 @@ static inline int _setup_loops(struct pl330_dmac *pl330,
BRST_SIZE(ccr);
int off = 0;
+ if (pxs->desc->sgl.size)
+ bursts = x->bytes / pxs->desc->sgl.size;
+
while (bursts) {
c = bursts;
off += _loop(pl330, dry_run, &buf[off], &c, pxs);
@@ -2743,6 +2788,9 @@ static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
desc->peri = peri_id ? pch->chan.chan_id : 0;
desc->rqcfg.pcfg = &pch->dmac->pcfg;
+ desc->sgl.size = 0;
+ desc->sgl.src_icg = 0;
+ desc->sgl.dst_icg = 0;
desc->cyclic = false;
desc->num_periods = 1;
@@ -2866,6 +2914,110 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
return &desc->txd;
}
+static struct dma_async_tx_descriptor *pl330_prep_interleaved_dma(
+ struct dma_chan *chan, struct dma_interleaved_template *xt,
+ unsigned long flags)
+{
+ struct dma_pl330_desc *desc = NULL, *first = NULL;
+ struct dma_pl330_chan *pch = to_pchan(chan);
+ struct pl330_dmac *pl330 = pch->dmac;
+ unsigned int i;
+ dma_addr_t dst;
+ dma_addr_t src;
+ size_t size, src_icg, dst_icg, period_bytes, buffer_bytes, full_period_bytes;
+ size_t nump = 0, numf = 0;
+
+ if (!xt->numf || !xt->sgl[0].size || xt->frame_size != 1)
+ return NULL;
+ nump = xt->nump;
+ numf = xt->numf;
+ size = xt->sgl[0].size;
+ period_bytes = size * nump;
+ buffer_bytes = size * numf;
+
+ if (flags & DMA_PREP_REPEAT && (!nump || (numf % nump)))
+ return NULL;
+
+ src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]);
+ dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]);
+
+ pl330_config_write(chan, &pch->slave_config, xt->dir);
+
+ if (!pl330_prep_slave_fifo(pch, xt->dir))
+ return NULL;
+
+ for (i = 0; i < numf / nump; i++) {
+ desc = pl330_get_desc(pch);
+ if (!desc) {
+ unsigned long iflags;
+
+ dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
+ __func__, __LINE__);
+
+ if (!first)
+ return NULL;
+
+ spin_lock_irqsave(&pl330->pool_lock, iflags);
+
+ while (!list_empty(&first->node)) {
+ desc = list_entry(first->node.next,
+ struct dma_pl330_desc, node);
+ list_move_tail(&desc->node, &pl330->desc_pool);
+ }
+
+ list_move_tail(&first->node, &pl330->desc_pool);
+
+ spin_unlock_irqrestore(&pl330->pool_lock, iflags);
+
+ return NULL;
+ }
+
+ switch (xt->dir) {
+ case DMA_MEM_TO_DEV:
+ desc->rqcfg.src_inc = 1;
+ desc->rqcfg.dst_inc = 0;
+ src = xt->src_start + period_bytes * i;
+ dst = pch->fifo_dma;
+ full_period_bytes = (size + src_icg) * nump;
+ break;
+ case DMA_DEV_TO_MEM:
+ desc->rqcfg.src_inc = 0;
+ desc->rqcfg.dst_inc = 1;
+ src = pch->fifo_dma;
+ dst = xt->dst_start + period_bytes * i;
+ full_period_bytes = (size + dst_icg) * nump;
+ break;
+ default:
+ break;
+ }
+
+ desc->rqtype = xt->dir;
+ desc->rqcfg.brst_size = pch->burst_sz;
+ desc->rqcfg.brst_len = pch->burst_len;
+ desc->bytes_requested = full_period_bytes;
+ desc->sgl.size = size;
+ desc->sgl.src_icg = src_icg;
+ desc->sgl.dst_icg = dst_icg;
+ fill_px(&desc->px, dst, src, period_bytes);
+
+ if (!first)
+ first = desc;
+ else
+ list_add_tail(&desc->node, &first->node);
+ }
+
+ if (!desc)
+ return NULL;
+
+ if (flags & DMA_PREP_REPEAT)
+ desc->cyclic = true;
+
+ dev_dbg(chan->device->dev, "size: %zu, src_icg: %zu, dst_icg: %zu, nump: %zu, numf: %zu\n",
+ size, src_icg, dst_icg, nump, numf);
+
+ return &desc->txd;
+}
+
static struct dma_async_tx_descriptor *
pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
dma_addr_t src, size_t len, unsigned long flags)
@@ -3221,12 +3373,16 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
dma_cap_set(DMA_SLAVE, pd->cap_mask);
dma_cap_set(DMA_CYCLIC, pd->cap_mask);
dma_cap_set(DMA_PRIVATE, pd->cap_mask);
+ dma_cap_set(DMA_INTERLEAVE, pd->cap_mask);
+ dma_cap_set(DMA_REPEAT, pd->cap_mask);
+ dma_cap_set(DMA_LOAD_EOT, pd->cap_mask);
}
pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
pd->device_free_chan_resources = pl330_free_chan_resources;
pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
+ pd->device_prep_interleaved_dma = pl330_prep_interleaved_dma;
pd->device_tx_status = pl330_tx_status;
pd->device_prep_slave_sg = pl330_prep_slave_sg;
pd->device_config = pl330_config;
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 111111111111..222222222222 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -156,6 +156,7 @@ struct dma_interleaved_template {
bool src_sgl;
bool dst_sgl;
size_t numf;
+ size_t nump;
size_t frame_size;
struct data_chunk sgl[];
};
--
Armbian

27
patch/kernel/rockchip64-6.14/general-pl330-04-bigger-mcode-buffer.patch
View File

@ -1,27 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 26 Jan 2025 14:49:18 +0100
Subject: increase pl330 microcode buffer size
suggestion comes from the scatter/gather functionality as
proposed here: https://github.com/radxa/kernel/commit/ec0b65dbc59793426b6dc7af06ab6675f4a24940
---
drivers/dma/pl330.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 111111111111..222222222222 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -247,7 +247,7 @@ enum pl330_byteswap {
* For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
* should be enough for P<->M and M<->M respectively.
*/
-#define MCODE_BUFF_PER_REQ 256
+#define MCODE_BUFF_PER_REQ 512
/* Use this _only_ to wait on transient states */
#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
--
Armbian

81
patch/kernel/rockchip64-6.14/general-pl330-05-fix-unbalanced-power-down.patch
View File

@ -1,81 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Sat, 26 Mar 2022 18:01:21 +0800
Subject: dmaengine: pl330: Fix unbalanced runtime PM
This driver use runtime PM autosuspend mechanism to manager clk.
pm_runtime_use_autosuspend(&adev->dev);
pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
So, after ref count reached to zero, it will enter suspend
after the delay time elapsed.
The unbalanced PM:
* May cause dmac the next start failed.
* May cause dmac read unexpected state.
* May cause dmac stall if power down happen at the middle of the transfer.
e.g. may lose ack from AXI bus and stall.
Considering the following situation:
DMA TERMINATE TASKLET ROUTINE
| |
| issue_pending
| |
| pch->active = true
| pm_runtime_get
pm_runtime_put(if active) |
pch->active = false |
| work_list empty
| |
| pm_runtime_put(force)
| |
At this point, it's unbalanced(1 get / 2 put).
After this patch:
DMA TERMINATE TASKLET ROUTINE
| |
| issue_pending
| |
| pch->active = true
| pm_runtime_get
pm_runtime_put(if active) |
pch->active = false |
| work_list empty
| |
| pm_runtime_put(if active)
| |
Now, it's balanced(1 get / 1 put).
Fixes:
commit 5c9e6c2b2ba3 ("dmaengine: pl330: Fix runtime PM support for terminated transfers")
commit ae43b3289186 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12")
Change-Id: Ib1feb508c16afb4bc9ced0c3660f2b6b4a19c068
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
---
drivers/dma/pl330.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 111111111111..222222222222 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2274,7 +2274,7 @@ static void pl330_tasklet(struct tasklet_struct *t)
spin_lock(&pch->thread->dmac->lock);
_stop(pch->thread);
spin_unlock(&pch->thread->dmac->lock);
- power_down = true;
+ power_down = pch->active;
pch->active = false;
} else {
/* Make sure the PL330 Channel thread is active */
--
Armbian

70
patch/kernel/rockchip64-6.14/general-pl330-06-fix-buffer-underruns.patch
View File

@ -1,70 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 16 Feb 2025 11:15:55 +0100
Subject: pl330: fix buffer underrun with cyclic dma
userspace applications (notably, pulseaudio) were
suffering frequent buffer underruns when cyclic DMA
was handled by controller itself. This patch fixes
the buffer underruns avoiding to juggle with the
descriptor state, keeping it in BUSY state as long
as it is actual transfer is progressing.
---
drivers/dma/pl330.c | 24 +++++-----
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 111111111111..222222222222 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -1737,11 +1737,11 @@ static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
if (!pch)
return;
- spin_lock_irqsave(&pch->lock, flags);
-
- desc->status = DONE;
-
- spin_unlock_irqrestore(&pch->lock, flags);
+ if (!desc->cyclic) {
+ spin_lock_irqsave(&pch->lock, flags);
+ desc->status = DONE;
+ spin_unlock_irqrestore(&pch->lock, flags);
+ }
tasklet_schedule(&pch->task);
}
@@ -2248,23 +2248,23 @@ static void pl330_tasklet(struct tasklet_struct *t)
/* Pick up ripe tomatoes */
list_for_each_entry_safe(desc, _dt, &pch->work_list, node) {
- if (desc->status == DONE) {
- if (!desc->cyclic) {
- dma_cookie_complete(&desc->txd);
- list_move_tail(&desc->node, &pch->completed_list);
- } else {
- struct dmaengine_desc_callback cb;
+ if (desc->cyclic) {
+ if (desc->status == BUSY || desc->status == DONE) {
+ struct dmaengine_desc_callback cb;
desc->status = BUSY;
dmaengine_desc_get_callback(&desc->txd, &cb);
-
if (dmaengine_desc_callback_valid(&cb)) {
spin_unlock_irqrestore(&pch->lock, flags);
dmaengine_desc_callback_invoke(&cb, NULL);
spin_lock_irqsave(&pch->lock, flags);
}
}
+ } else if (desc->status == DONE) {
+ dma_cookie_complete(&desc->txd);
+ list_move_tail(&desc->node, &pch->completed_list);
}
+
}
/* Try to submit a req imm. next to the last completed cookie */
--
Armbian

51
patch/kernel/rockchip64-6.14/general-possibility-of-disabling-rk808-rtc.patch
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@ -1,51 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Piotr Szczepanik <piter75@gmail.com>
Date: Sun, 24 Jan 2021 16:14:06 +0100
Subject: add possibility of disabling rk808-rtc
To disable rk808-rtc driver from loading for specific board
add the following stanza to rk808 node in device tree:
rtc {
compatible = "rk808-rtc";
status = "disabled";
}
This is needed for roc-rk3399-pc plus (a.k.a. Station P1).
Without the change rk808's rtc is initialised and used for time keeping
although there is another rtc (hym8563) that should be actually used.
Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
---
drivers/mfd/mfd-core.c | 2 +-
drivers/mfd/rk8xx-core.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index 111111111111..222222222222 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -208,7 +208,7 @@ static int mfd_add_device(struct device *parent, int id,
match:
if (!pdev->dev.of_node)
- pr_warn("%s: Failed to locate of_node [id: %d]\n",
+ pr_debug("%s: Failed to locate of_node [id: %d]\n",
cell->name, platform_id);
}
diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c
index 111111111111..222222222222 100644
--- a/drivers/mfd/rk8xx-core.c
+++ b/drivers/mfd/rk8xx-core.c
@@ -133,6 +133,7 @@ static const struct mfd_cell rk818s[] = {
{ .name = "rk808-regulator", },
{
.name = "rk808-rtc",
+ .of_compatible = "rk808-rtc",
.num_resources = ARRAY_SIZE(rtc_resources),
.resources = rtc_resources,
},
--
Armbian

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