From 1fee53d5f5737a8b7f6634f1fc7056769832b82b Mon Sep 17 00:00:00 2001 From: andreili Date: Thu, 24 Jul 2025 23:33:47 +0200 Subject: [PATCH 01/28] Add a temporary RK3566 DT files --- tmp/rk3566-base.dtsi | 35 + tmp/rk3566-bigtreetech-cb2.dtsi | 1498 ++++++++++++++++++++++++ tmp/rk3566-bigtreetech-pi2.dts | 70 ++ tmp/rk3566.dtsi | 107 ++ tmp/rk356x-base.dtsi | 1944 +++++++++++++++++++++++++++++++ 5 files changed, 3654 insertions(+) create mode 100644 tmp/rk3566-base.dtsi create mode 100644 tmp/rk3566-bigtreetech-cb2.dtsi create mode 100644 tmp/rk3566-bigtreetech-pi2.dts create mode 100644 tmp/rk3566.dtsi create mode 100644 tmp/rk356x-base.dtsi diff --git a/tmp/rk3566-base.dtsi b/tmp/rk3566-base.dtsi new file mode 100644 index 0000000..e56e0b6 --- /dev/null +++ b/tmp/rk3566-base.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-base.dtsi" + +/ { + compatible = "rockchip,rk3566"; +}; + +&pipegrf { + compatible = "rockchip,rk3566-pipe-grf", "syscon"; +}; + +&power { + power-domain@RK3568_PD_PIPE { + reg = ; + clocks = <&cru PCLK_PIPE>; + pm_qos = <&qos_pcie2x1>, + <&qos_sata1>, + <&qos_sata2>, + <&qos_usb3_0>, + <&qos_usb3_1>; + #power-domain-cells = <0>; + }; +}; + +&usb_host0_xhci { + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; +}; + +&vop { + compatible = "rockchip,rk3566-vop"; +}; diff --git a/tmp/rk3566-bigtreetech-cb2.dtsi b/tmp/rk3566-bigtreetech-cb2.dtsi new file mode 100644 index 0000000..93b514f --- /dev/null +++ b/tmp/rk3566-bigtreetech-cb2.dtsi @@ -0,0 +1,1498 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + ext_cam_clk: clock-25000000-cam { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "ext_cam_clk"; + #clock-cells = <0>; + }; + + can_mcp2515_osc: clock-8000000-mcp2515 { + compatible = "fixed-clock"; + clock-frequency = <8000000>; + #clock-cells = <0>; + }; + + leds: leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 =<&blue_led>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 =<&heartbeat_led>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 50 100 150 200 255>; + pwms = <&pwm7 0 50000 0>; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host3"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_otg: regulator-vcc5v0-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg3"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc5v0_usb2b: regulator-vcc5v0-usb2b { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb2b_en>; + regulator-name = "vcc5v0_usb2b"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb2t: regulator-vcc5v0-usb2t { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb2t_en>; + regulator-name = "vcc5v0_usb2t"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_5v: regulator-vcc-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_sd: regulator-vcc-sd { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + ddr3_params: ddr3-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x12c>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x21>; + phy_ca_drv_odten = <0x21>; + phy_clk_drv_odten = <0x21>; + dram_dq_drv_odten = <0x22>; + phy_dq_drv_odtoff = <0x21>; + phy_ca_drv_odtoff = <0x21>; + phy_clk_drv_odtoff = <0x21>; + dram_dq_drv_odtoff = <0x22>; + dram_odt = <0x78>; + phy_odt = <0xa7>; + phy_odt_puup_en = <0x01>; + phy_odt_pudn_en = <0x01>; + dram_dq_odt_en_freq = <0x14d>; + phy_odt_en_freq = <0x14d>; + phy_dq_sr_odten = <0x0f>; + phy_ca_sr_odten = <0x03>; + phy_clk_sr_odten = <0x00>; + phy_dq_sr_odtoff = <0x0f>; + phy_ca_sr_odtoff = <0x03>; + phy_clk_sr_odtoff = <0x00>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x15>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + }; + + ddr4_params: ddr4-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x271>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x25>; + phy_ca_drv_odten = <0x25>; + phy_clk_drv_odten = <0x25>; + dram_dq_drv_odten = <0x22>; + phy_dq_drv_odtoff = <0x25>; + phy_ca_drv_odtoff = <0x25>; + phy_clk_drv_odtoff = <0x25>; + dram_dq_drv_odtoff = <0x22>; + dram_odt = <0x78>; + phy_odt = <0x8b>; + phy_odt_puup_en = <0x01>; + phy_odt_pudn_en = <0x01>; + dram_dq_odt_en_freq = <0x1f4>; + phy_odt_en_freq = <0x1f4>; + phy_dq_sr_odten = <0x0e>; + phy_ca_sr_odten = <0x01>; + phy_clk_sr_odten = <0x01>; + phy_dq_sr_odtoff = <0x0e>; + phy_ca_sr_odtoff = <0x01>; + phy_clk_sr_odtoff = <0x01>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x0c>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x22777788>; + dq_map_cs0_dq_h = <0xd7888877>; + dq_map_cs1_dq_l = <0x22777788>; + dq_map_cs1_dq_h = <0xd7888877>; + }; + + lpddr3_params: lpddr3-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x00>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x25>; + phy_ca_drv_odten = <0x25>; + phy_clk_drv_odten = <0x27>; + dram_dq_drv_odten = <0x22>; + phy_dq_drv_odtoff = <0x25>; + phy_ca_drv_odtoff = <0x25>; + phy_clk_drv_odtoff = <0x27>; + dram_dq_drv_odtoff = <0x22>; + dram_odt = <0x78>; + phy_odt = <0x94>; + phy_odt_puup_en = <0x01>; + phy_odt_pudn_en = <0x01>; + dram_dq_odt_en_freq = <0x14d>; + phy_odt_en_freq = <0x14d>; + phy_dq_sr_odten = <0x0f>; + phy_ca_sr_odten = <0x01>; + phy_clk_sr_odten = <0x0f>; + phy_dq_sr_odtoff = <0x0f>; + phy_ca_sr_odtoff = <0x01>; + phy_clk_sr_odtoff = <0x0f>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x00>; + dram_ext_temp = <0x00>; + byte_map = <0x8d>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + }; + + lpddr4_params: lpddr4-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x00>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x1e>; + phy_ca_drv_odten = <0x26>; + phy_clk_drv_odten = <0x26>; + dram_dq_drv_odten = <0x28>; + phy_dq_drv_odtoff = <0x1e>; + phy_ca_drv_odtoff = <0x26>; + phy_clk_drv_odtoff = <0x26>; + dram_dq_drv_odtoff = <0x28>; + dram_odt = <0x50>; + phy_odt = <0x3c>; + phy_odt_puup_en = <0x00>; + phy_odt_pudn_en = <0x00>; + dram_dq_odt_en_freq = <0x320>; + phy_odt_en_freq = <0x320>; + phy_dq_sr_odten = <0x00>; + phy_ca_sr_odten = <0x0f>; + phy_clk_sr_odten = <0x0f>; + phy_dq_sr_odtoff = <0x00>; + phy_ca_sr_odtoff = <0x0f>; + phy_clk_sr_odtoff = <0x0f>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x00>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + lp4_ca_odt = <0x78>; + lp4_drv_pu_cal_odten = <0x01>; + lp4_drv_pu_cal_odtoff = <0x01>; + phy_lp4_drv_pulldown_en_odten = <0x00>; + phy_lp4_drv_pulldown_en_odtoff = <0x00>; + lp4_ca_odt_en_freq = <0x320>; + phy_lp4_cs_drv_odten = <0x00>; + phy_lp4_cs_drv_odtoff = <0x00>; + lp4_odte_ck_en = <0x01>; + lp4_odte_cs_en = <0x01>; + lp4_odtd_ca_en = <0x00>; + phy_lp4_dq_vref_odten = <0xa6>; + lp4_dq_vref_odten = <0x12c>; + lp4_ca_vref_odten = <0x17c>; + phy_lp4_dq_vref_odtoff = <0x1a4>; + lp4_dq_vref_odtoff = <0x1a4>; + lp4_ca_vref_odtoff = <0x1a4>; + }; + + lpddr4x_params: lpddr4x-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x00>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x1d>; + phy_ca_drv_odten = <0x24>; + phy_clk_drv_odten = <0x24>; + dram_dq_drv_odten = <0x28>; + phy_dq_drv_odtoff = <0x1d>; + phy_ca_drv_odtoff = <0x24>; + phy_clk_drv_odtoff = <0x24>; + dram_dq_drv_odtoff = <0x28>; + dram_odt = <0x50>; + phy_odt = <0x3c>; + phy_odt_puup_en = <0x00>; + phy_odt_pudn_en = <0x00>; + dram_dq_odt_en_freq = <0x320>; + phy_odt_en_freq = <0x320>; + phy_dq_sr_odten = <0x00>; + phy_ca_sr_odten = <0x00>; + phy_clk_sr_odten = <0x00>; + phy_dq_sr_odtoff = <0x00>; + phy_ca_sr_odtoff = <0x00>; + phy_clk_sr_odtoff = <0x00>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x00>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + lp4_ca_odt = <0x78>; + lp4_drv_pu_cal_odten = <0x00>; + lp4_drv_pu_cal_odtoff = <0x00>; + phy_lp4_drv_pulldown_en_odten = <0x00>; + phy_lp4_drv_pulldown_en_odtoff = <0x00>; + lp4_ca_odt_en_freq = <0x320>; + phy_lp4_cs_drv_odten = <0x00>; + phy_lp4_cs_drv_odtoff = <0x00>; + lp4_odte_ck_en = <0x00>; + lp4_odte_cs_en = <0x00>; + lp4_odtd_ca_en = <0x00>; + phy_lp4_dq_vref_odten = <0xa6>; + lp4_dq_vref_odten = <0xe4>; + lp4_ca_vref_odten = <0x157>; + phy_lp4_dq_vref_odtoff = <0x1a4>; + lp4_dq_vref_odtoff = <0x1a4>; + lp4_ca_vref_odtoff = <0x157>; + }; + + dmc: dmc { + compatible = "rockchip,rk3568-dmc"; + interrupts = ; + interrupt-names = "complete"; + devfreq-events = <&dfi 0xa2>; + clocks = <&scmi_clk 0x03>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + vop-bw-dmc-freq = <0x00 0x11e 0x4f1a0 0x11f 0x1869f 0x80e80>; + vop-frame-bw-dmc-freq = <0x00 0x26c 0x4f1a0 0x26d 0x1869f 0xbe6e0>; + cpu-bw-dmc-freq = <0x00 0x15e 0x4f1a0 0x15f 0x190 0x80e80 0x191 0x1869f 0xbe6e0>; + upthreshold = <0x28>; + downdifferential = <0x14>; + system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08>; + auto-min-freq = <0x4f1a0>; + auto-freq-en = <1>; + #cooling-cells = <2>; + status = "disabled"; + center-supply = <&vdd_logic>; + }; + + dmc_fsp: dmc-fsp { + compatible = "rockchip,rk3568-dmc-fsp"; + debug_print_level = <0>; + ddr3_params = <&ddr3_params>; + ddr4_params = <&ddr4_params>; + lpddr3_params = <&lpddr3_params>; + lpddr4_params = <&lpddr4_params>; + lpddr4x_params = <&lpddr4x_params>; + status = "disabled"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; + nvmem-cells = <0x70 0x07 0x08 0xa9 0x0a 0x0b>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info", "specification_serial_number", "remark_spec_serial_number"; + rockchip,supported-hw; + rockchip,max-volt = <0xf4240>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x00>; + rockchip,low-temp-adjust-volt = <0x00 0x618 0x124f8>; + rockchip,leakage-voltage-sel = <0x01 0x50 0x00 0x51 0xfe 0x01>; + rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x186a0 0x01>; + rockchip,pvtm-ch = <0x00 0x05>; + + opp-1560000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x5cfbb600>; + opp-microvolt = <0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L0 = <0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240>; + }; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reset-delay-us = <20000>; + reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <100000>; + reg = <0x0>; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "disabled"; + upthreshold = <0x28>; + downdifferential = <0x0a>; + + gpu_power_model: power-model { + compatible = "simple-power-model"; + leakage-range = <0x05 0x0f>; + ls = <0xffffa23e 0x5927 0x00>; + static-coefficient = <0x186a0>; + dynamic-coefficient = <0x3b9>; + ts = <0xfffe56a6 0xf87a 0xfffffab5 0x14>; + thermal-zone = "gpu-thermal"; + }; +}; + +&display_subsystem { + devfreq = <&dmc>; + status = "disabled"; + + route { + route_dsi0: route-dsi0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x11>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x12>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x13>; + }; + + route_hdmi: route-hdmi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x14>; + }; + + route_lvds: route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x15>; + }; + + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x16>; + }; + }; +}; + +&vp0 { + #address-cells = <1>; + #size-cells = <0>; + + vp0_out_dsi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_in_vp0>; + }; + + vp0_out_dsi1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi1_in_vp0>; + }; + + vp0_out_edp: endpoint@2 { + reg = <2>; + remote-endpoint = <&edp_in_vp0>; + }; + + /*vp0_out_hdmi: endpoint@3 { + reg = <3>; + remote-endpoint = <&hdmi_in_vp0>; + };*/ +}; + +&vp1 { + #address-cells = <1>; + #size-cells = <0>; + + vp1_out_dsi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_in_vp1>; + }; + + vp1_out_dsi1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi1_in_vp1>; + }; + + vp1_out_edp: endpoint@2 { + reg = <2>; + remote-endpoint = <&edp_in_vp1>; + }; + + /*vp1_out_hdmi: endpoint@3 { + reg = <3>; + remote-endpoint = <&hdmi_in_vp1>; + };*/ + + vp1_out_lvds: endpoint@4 { + reg = <4>; + remote-endpoint = <&lvds_in_vp1>; + }; +}; + +&vp2 { + #address-cells = <1>; + #size-cells = <0>; + + vp2_out_lvds: endpoint@0 { + reg = <0>; + remote-endpoint = <&lvds_in_vp2>; + }; + + vp2_out_rgb: endpoint@1 { + reg = <1>; + remote-endpoint = <&rgb_in_vp2>; + }; +}; + + +&dsi0_in { + dsi0_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dsi0>; + status = "disabled"; + }; + + dsi0_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dsi0>; + status = "disabled"; + }; +}; + +&dsi1_in { + reg = <0>; + + dsi1_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dsi1>; + status = "disabled"; + }; + + dsi1_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dsi1>; + status = "disabled"; + }; +}; + +&dsi1_out { + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; +}; + +&dsi1 { + dsi1_panel: panel@0 { + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + power-supply = <&vcc3v3_sys>; + compatible = "btt-pitft"; + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; +}; + +&edp_in{ + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_edp>; + status = "disabled"; + }; + + edp_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_edp>; + status = "disabled"; + }; +}; + +&grf { + io_domains: io-domains { + compatible = "rockchip,rk3568-io-voltage-domain"; + status = "disabled"; + }; + + lvds: lvds { + compatible = "rockchip,rk3568-lvds"; + phys = <&dsi_dphy0>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_lvds>; + status = "disabled"; + }; + + lvds_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_lvds>; + status = "disabled"; + }; + }; + }; + }; + + rgb: rgb { + compatible = "rockchip,rk3568-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_ctl>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_rgb>; + status = "disabled"; + }; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-initial-mode = <1>; + regulator-ramp-delay = <2300>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + rockchip,mic-in-differential; + }; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2m1_xfer>; +}; + +&i2c3 { + status = "okay"; + + tft_tp: touchscreen@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + status = "disabled"; + ti,x-plate-ohms = <660>; + ti,rt-thr = <3000>; + ti,fuzzx = <32>; + ti,fuzzy = <16>; + }; +}; + +&i2s0_8ch { + status = "disabled"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "disabled"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + + can_mcp2515: can@0 { + compatible = "microchip,mcp2515"; + reg = <0x00>; + clocks = <&can_mcp2515_osc>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp2515_int_pin>; + spi-max-frequency = <10000000>; + vdd-supply = <&vcc3v3_sys>; + xceiver-supply = <&vcc3v3_sys>; + }; +}; + +&spi3 { + pinctrl-names = "default"; + pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "disabled"; +}; + +&pinctrl { + bt { + bt_enable: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_host_wake: bt-host-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake: bt-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake: wifi-host-wake-l { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb2t_en: vcc5v0-usb2t-en { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb2b_en: vcc5v0-usb2b-en { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + work-led { + heartbeat_led: led-heartbeat { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + blue_led: led-blue { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mcp2515 { + mcp2515_int_pin: mcp2515-int-pin { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0m1_pins>; +}; + +&pwm12 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm12m1_pins>; +}; + +&pwm13 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm13m1_pins>; +}; + +&pwm14 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm14m1_pins>; +}; + +&pwm15 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m1_pins>; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "disabled"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + /* WiFi & BT combo module AMPAK AP6256 */ + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + rockchip,default-sample-phase = <90>; + status = "okay"; + + sdio-wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + brcm,drive-strength = <10>; + }; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&tsadc { + status = "disabled"; +}; + +&uart1 { + dma-names = "tx","rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb2t>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb2b>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "disabled"; +}; + +&vop_mmu { + status = "disabled"; +}; diff --git a/tmp/rk3566-bigtreetech-pi2.dts b/tmp/rk3566-bigtreetech-pi2.dts new file mode 100644 index 0000000..d3cf88a --- /dev/null +++ b/tmp/rk3566-bigtreetech-pi2.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-bigtreetech-cb2.dtsi" + +/ { + model = "BigTreeTech Pi 2"; + compatible = "bigtreetech,pi2", "rockchip,rk3566"; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&i2c2 { + status = "disabled"; + + bl_dsi: regulator@45 { + status = "disabled"; + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + }; + + tp_dsi: ft5406@38 { + status = "disabled"; + compatible = "edt,edt-ft5406"; + reg = <0x38>; + vcc-supply = <&vcc3v3_sys>; + iovcc-supply = <&vcc_3v3>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi1_panel { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi_dphy1 { + status = "disabled"; +}; + +&tp_dsi { + status = "disabled"; +}; + +&bl_dsi { + status = "disabled"; +}; diff --git a/tmp/rk3566.dtsi b/tmp/rk3566.dtsi new file mode 100644 index 0000000..3fcca79 --- /dev/null +++ b/tmp/rk3566.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3566-base.dtsi" + +/ { + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <900000 900000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1025000 1025000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000 1100000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1150000 1150000 1150000>; + clock-latency-ns = <40000>; + }; + }; + + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <850000 850000 1000000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <850000 850000 1000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <850000 850000 1000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1000000>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <950000 950000 1000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000 1000000 1000000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/tmp/rk356x-base.dtsi b/tmp/rk356x-base.dtsi new file mode 100644 index 0000000..51d1b02 --- /dev/null +++ b/tmp/rk356x-base.dtsi @@ -0,0 +1,1944 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&scmi_clk 0>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l3_cache>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l3_cache>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l3_cache>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l3_cache>; + }; + }; + + /* + * There are no private per-core L2 caches, but only the + * L3 cache that appears to the CPU cores as L2 caches + */ + l3_cache: l3-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + rockchip,clk-init = <1104000000>; + }; + }; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + arm,no-tick-in-suspend; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + pinctrl-0 = <&clk32k_out0>; + pinctrl-names = "default"; + #clock-cells = <0>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0010f000 0x100>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + sata1: sata@fc400000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc400000 0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, + <&cru CLK_SATA1_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy1 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + sata2: sata@fc800000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc800000 0 0x1000>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, + <&cru CLK_SATA2_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy2 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + usb_host0_xhci: usb@fcc00000 { + compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfcc00000 0x0 0x400000>; + interrupts = ; + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + dr_mode = "otg"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG0>; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + + usb_host1_xhci: usb@fd000000 { + compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfd000000 0x0 0x400000>; + interrupts = ; + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + dr_mode = "host"; + phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG1>; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ + <0x0 0xfd460000 0 0x80000>; /* GICR */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + mbi-alias = <0x0 0xfd410000>; + mbi-ranges = <296 24>; + msi-controller; + }; + + usb_host0_ehci: usb@fd800000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd800000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>; + phys = <&usb2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fd840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd840000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>; + phys = <&usb2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@fd880000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd880000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>; + phys = <&usb2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@fd8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd8c0000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>; + phys = <&usb2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3568-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + pipegrf: syscon@fdc50000 { + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + + grf: syscon@fdc60000 { + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc60000 0x0 0x10000>; + }; + + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + + usb2phy0_grf: syscon@fdca0000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca0000 0x0 0x8000>; + }; + + usb2phy1_grf: syscon@fdca8000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca8000 0x0 0x8000>; + }; + + sram@fdcc0000 { + compatible = "mmio-sram"; + reg = <0x0 0xfdcc0000 0x0 0xb000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xfdcc0000 0xb000>; + + vdec_sram: rkvdec-sram@0 { + reg = <0x0 0xb000>; + pool; + }; + }; + + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; + rockchip,grf = <&grf>; + }; + + i2c0: i2c@fdd40000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfdd40000 0x0 0x1000>; + interrupts = ; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fdd50000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfdd50000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + pinctrl-0 = <&uart0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pwm0: pwm@fdd70000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70000 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm0m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@fdd70010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70010 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm1m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@fdd70020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70020 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm2m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@fdd70030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70030 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm3_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu: power-management@fdd90000 { + compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfdd90000 0x0 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3568-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* These power domains are grouped by VD_GPU */ + power-domain@RK3568_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU_PRE>, + <&cru PCLK_GPU_PRE>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3568_PD_VI { + reg = ; + clocks = <&cru HCLK_VI>, + <&cru PCLK_VI>; + pm_qos = <&qos_isp>, + <&qos_vicap0>, + <&qos_vicap1>; + #power-domain-cells = <0>; + }; + + power-domain@RK3568_PD_VO { + reg = ; + clocks = <&cru HCLK_VO>, + <&cru PCLK_VO>, + <&cru ACLK_VOP_PRE>; + pm_qos = <&qos_hdcp>, + <&qos_vop_m0>, + <&qos_vop_m1>; + #power-domain-cells = <0>; + }; + + power-domain@RK3568_PD_RGA { + reg = ; + clocks = <&cru HCLK_RGA_PRE>, + <&cru PCLK_RGA_PRE>; + pm_qos = <&qos_ebc>, + <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc>, + <&qos_rga_rd>, + <&qos_rga_wr>; + #power-domain-cells = <0>; + }; + + power-domain@RK3568_PD_VPU { + reg = ; + clocks = <&cru HCLK_VPU_PRE>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3568_PD_RKVDEC { + clocks = <&cru HCLK_RKVDEC_PRE>; + reg = ; + pm_qos = <&qos_rkvdec>; + #power-domain-cells = <0>; + }; + + power-domain@RK3568_PD_RKVENC { + reg = ; + clocks = <&cru HCLK_RKVENC_PRE>; + pm_qos = <&qos_rkvenc_rd_m0>, + <&qos_rkvenc_rd_m1>, + <&qos_rkvenc_wr_m0>; + #power-domain-cells = <0>; + }; + }; + }; + + gpu: gpu@fde60000 { + compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; + reg = <0x0 0xfde60000 0x0 0x4000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scmi_clk 1>, <&cru CLK_GPU>; + clock-names = "gpu", "bus"; + #cooling-cells = <2>; + power-domains = <&power RK3568_PD_GPU>; + status = "disabled"; + }; + + vpu: video-codec@fdea0400 { + compatible = "rockchip,rk3328-vpu"; + reg = <0x0 0xfdea0000 0x0 0x800>; + interrupts = ; + interrupt-names = "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vdpu_mmu>; + power-domains = <&power RK3568_PD_VPU>; + }; + + vdpu_mmu: iommu@fdea0800 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfdea0800 0x0 0x40>; + interrupts = ; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + power-domains = <&power RK3568_PD_VPU>; + #iommu-cells = <0>; + }; + + rga: rga@fdeb0000 { + compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; + reg = <0x0 0xfdeb0000 0x0 0x180>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3568_PD_RGA>; + }; + + vepu: video-codec@fdee0000 { + compatible = "rockchip,rk3568-vepu"; + reg = <0x0 0xfdee0000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; + clock-names = "aclk", "hclk"; + iommus = <&vepu_mmu>; + power-domains = <&power RK3568_PD_RGA>; + }; + + vepu_mmu: iommu@fdee0800 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfdee0800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3568_PD_RGA>; + #iommu-cells = <0>; + }; + + vdec: video-codec@fdf80200 { + compatible = "rockchip,rk3588-vdec"; + reg = <0x0 0xfdf80100 0x0 0x100>, <0x0 0xfdf80200 0x0 0x500>, <0x0 0xfdf80700 0x0 0x100>; + reg-names = "link", "function", "cache"; + interrupts = ; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_CA>, + <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates = <297000000>, <297000000>, + <297000000>, <297000000>; + resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CA>, + <&cru SRST_RKVDEC_CORE>, <&cru SRST_RKVDEC_HEVC_CA>; + reset-names = "rst_axi", "rst_ahb", "rst_cabac", + "rst_core", "rst_hevc_cabac"; + power-domains = <&power RK3568_PD_RKVDEC>; + sram = <&vdec_sram>; + }; + + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, + <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC2>; + reset-names = "reset"; + status = "disabled"; + }; + + gmac1: ethernet@fe010000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe010000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, + <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <8>; + snps,wr_osr_lmt = <4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + vop: vop@fe040000 { + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; + clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; + iommus = <&vop_mmu>; + power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + vp1: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + vp2: port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + vop_mmu: iommu@fe043e00 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3568_PD_VO>; + status = "disabled"; + }; + + dsi0: dsi@fe060000 { + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x00 0xfe060000 0x00 0x10000>; + interrupts = ; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_0>; + phy-names = "dphy"; + phys = <&dsi_dphy0>; + power-domains = <&power RK3568_PD_VO>; + reset-names = "apb"; + resets = <&cru SRST_P_DSITX_0>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in: port@0 { + reg = <0>; + }; + + dsi0_out: port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi@fe070000 { + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xfe070000 0x0 0x10000>; + interrupts = ; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_1>; + phy-names = "dphy"; + phys = <&dsi_dphy1>; + power-domains = <&power RK3568_PD_VO>; + reset-names = "apb"; + resets = <&cru SRST_P_DSITX_1>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + }; + + dsi1_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi: hdmi@fe0a0000 { + compatible = "rockchip,rk3568-dw-hdmi"; + reg = <0x0 0xfe0a0000 0x0 0x20000>; + interrupts = ; + clocks = <&cru PCLK_HDMI_HOST>, + <&cru CLK_HDMI_SFR>, + <&cru CLK_HDMI_CEC>, + <&pmucru CLK_HDMI_REF>, + <&cru HCLK_VO>; + clock-names = "iahb", "isfr", "cec", "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; + power-domains = <&power RK3568_PD_VO>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + edp: edp@fe0c0000 { + compatible = "rockchip,rk3568-edp"; + reg = <0x00 0xfe0c0000 0x00 0x10000>; + interrupts = ; + clocks = <&pmucru XIN_OSC0_EDPPHY_G>, + <&cru PCLK_EDP_CTRL>, + <&cru CLK_EDP_200M>, + <&cru HCLK_VO>; + clock-names = "dp", "pclk", "spdif", "hclk"; + resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>; + reset-names = "dp", "apb"; + phys = <&edp_phy_grf>; + phy-names = "dp"; + power-domains = <&power RK3568_PD_VO>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp_in: port@0 { + reg = <0>; + }; + }; + }; + + edp_phy_grf: syscon@fdcb0000 { + compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd"; + reg = <0x00 0xfdcb0000 0x00 0x100>; + clocks = <&cru PCLK_EDPPHY_GRF>; + + edp_phy: edp-phy { + compatible = "rockchip,rk3568-edp-phy"; + clocks = <&pmucru XIN_OSC0_EDPPHY_G>; + clock-names = "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + qos_gpu: qos@fe128000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe128000 0x0 0x20>; + }; + + qos_rkvenc_rd_m0: qos@fe138080 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe138080 0x0 0x20>; + }; + + qos_rkvenc_rd_m1: qos@fe138100 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe138100 0x0 0x20>; + }; + + qos_rkvenc_wr_m0: qos@fe138180 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe138180 0x0 0x20>; + }; + + qos_isp: qos@fe148000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe148000 0x0 0x20>; + }; + + qos_vicap0: qos@fe148080 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe148080 0x0 0x20>; + }; + + qos_vicap1: qos@fe148100 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe148100 0x0 0x20>; + }; + + qos_vpu: qos@fe150000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe150000 0x0 0x20>; + }; + + qos_ebc: qos@fe158000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158000 0x0 0x20>; + }; + + qos_iep: qos@fe158100 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158100 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fe158180 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158180 0x0 0x20>; + }; + + qos_jpeg_enc: qos@fe158200 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158200 0x0 0x20>; + }; + + qos_rga_rd: qos@fe158280 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158280 0x0 0x20>; + }; + + qos_rga_wr: qos@fe158300 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158300 0x0 0x20>; + }; + + qos_npu: qos@fe180000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe180000 0x0 0x20>; + }; + + qos_pcie2x1: qos@fe190000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190000 0x0 0x20>; + }; + + qos_sata1: qos@fe190280 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190280 0x0 0x20>; + }; + + qos_sata2: qos@fe190300 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190300 0x0 0x20>; + }; + + qos_usb3_0: qos@fe190380 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190380 0x0 0x20>; + }; + + qos_usb3_1: qos@fe190400 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190400 0x0 0x20>; + }; + + qos_rkvdec: qos@fe198000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe198000 0x0 0x20>; + }; + + qos_hdcp: qos@fe1a8000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe1a8000 0x0 0x20>; + }; + + qos_vop_m0: qos@fe1a8080 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe1a8080 0x0 0x20>; + }; + + qos_vop_m1: qos@fe1a8100 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe1a8100 0x0 0x20>; + }; + + dfi: dfi@fe230000 { + compatible = "rockchip,rk3568-dfi"; + reg = <0x00 0xfe230000 0x00 0x400>; + interrupts = ; + rockchip,pmu = <&pmugrf>; + }; + + pcie2x1: pcie@fe260000 { + compatible = "rockchip,rk3568-pcie"; + reg = <0x3 0xc0000000 0x0 0x00400000>, + <0x0 0xfe260000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <6>; + num-ob-windows = <8>; + max-link-speed = <2>; + msi-map = <0x0 &gic 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + sdmmc0: mmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc1: mmc@fe2c0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC1>; + reset-names = "reset"; + status = "disabled"; + }; + + sfc: spi@fe300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe300000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sdhci: mmc@fe310000 { + compatible = "rockchip,rk3568-dwcmshc"; + reg = <0x0 0xfe310000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + rng: rng@fe388000 { + compatible = "rockchip,rk3568-rng"; + reg = <0x0 0xfe388000 0x0 0x4000>; + clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; + clock-names = "core", "ahb"; + resets = <&cru SRST_TRNG_NS>; + status = "disabled"; + }; + + crypto: crypto@fe380000 { + compatible = "rockchip,rk3568-crypto"; + reg = <0x0 0xfe380000 0x0 0x2000>; + interrupts = ; + clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, + <&cru CLK_CRYPTO_NS_CORE>; + clock-names = "aclk", "hclk", "core"; + resets = <&cru SRST_CRYPTO_NS_CORE>; + reset-names = "core"; + status = "okay"; + }; + + i2s0_8ch: i2s@fe400000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe400000 0x0 0x1000>; + interrupts = ; + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; + assigned-clock-rates = <1188000000>, <1188000000>; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 0>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe410000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe410000 0x0 0x1000>; + interrupts = ; + assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; + assigned-clock-rates = <1188000000>, <1188000000>; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, + <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 3>, <&dmac1 2>; + dma-names = "rx", "tx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx + &i2s1m0_lrcktx &i2s1m0_lrckrx + &i2s1m0_sdi0 &i2s1m0_sdi1 + &i2s1m0_sdi2 &i2s1m0_sdi3 + &i2s1m0_sdo0 &i2s1m0_sdo1 + &i2s1m0_sdo2 &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe420000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe420000 0x0 0x1000>; + interrupts = ; + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-rates = <1188000000>; + clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 4>, <&dmac1 5>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S2_2CH>; + reset-names = "tx-m"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m0_sclktx + &i2s2m0_lrcktx + &i2s2m0_sdi + &i2s2m0_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe430000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe430000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, + <&cru HCLK_I2S3_2CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 6>, <&dmac1 7>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm: pdm@fe440000 { + compatible = "rockchip,rk3568-pdm"; + reg = <0x0 0xfe440000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac1 9>; + dma-names = "rx"; + pinctrl-0 = <&pdmm0_clk + &pdmm0_clk1 + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + pinctrl-names = "default"; + resets = <&cru SRST_M_PDM>; + reset-names = "pdm-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif: spdif@fe460000 { + compatible = "rockchip,rk3568-spdif"; + reg = <0x0 0xfe460000 0x0 0x1000>; + interrupts = ; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; + dmas = <&dmac1 1>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + dmac0: dma-controller@fe530000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe530000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dma-controller@fe550000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe550000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + i2c1: i2c@fe5a0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5a0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c1_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe5b0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5b0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c2m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe5c0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5c0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe5d0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5d0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c4m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fe5e0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5e0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@fe600000 { + compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; + reg = <0x0 0xfe600000 0x0 0x100>; + interrupts = ; + clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; + clock-names = "tclk", "pclk"; + }; + + spi0: spi@fe610000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe610000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 20>, <&dmac0 21>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@fe620000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe620000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 22>, <&dmac0 23>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@fe630000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe630000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 24>, <&dmac0 25>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@fe640000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe640000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 26>, <&dmac0 27>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + pinctrl-0 = <&uart1m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@fe660000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe660000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 4>, <&dmac0 5>; + pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@fe670000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe670000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 6>, <&dmac0 7>; + pinctrl-0 = <&uart3m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@fe680000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe680000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 8>, <&dmac0 9>; + pinctrl-0 = <&uart4m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@fe690000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe690000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 10>, <&dmac0 11>; + pinctrl-0 = <&uart5m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart6: serial@fe6a0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 12>, <&dmac0 13>; + pinctrl-0 = <&uart6m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart7: serial@fe6b0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + pinctrl-0 = <&uart7m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart8: serial@fe6c0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + pinctrl-0 = <&uart8m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart9: serial@fe6d0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 18>, <&dmac0 19>; + pinctrl-0 = <&uart9m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + thermal_zones: thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + gpu_threshold: gpu-threshold { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_target: gpu-target { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: gpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@fe710000 { + compatible = "rockchip,rk3568-tsadc"; + reg = <0x0 0xfe710000 0x0 0x100>; + interrupts = ; + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; + assigned-clock-rates = <17000000>, <700000>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, + <&cru SRST_TSADCPHY>; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tsadc_shutorg>; + pinctrl-1 = <&tsadc_pin>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + saradc: saradc@fe720000 { + compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xfe720000 0x0 0x100>; + interrupts = ; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + pwm4: pwm@fe6e0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0000 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm4_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@fe6e0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0010 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm5_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@fe6e0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0020 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm6_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@fe6e0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0030 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm7_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@fe6f0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0000 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm8m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@fe6f0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0010 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm9m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@fe6f0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0020 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm10m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@fe6f0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0030 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@fe700000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700000 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm12m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@fe700010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700010 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm13m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@fe700020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700020 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm14m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@fe700030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700030 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm15m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + combphy1: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, + <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; + reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; + status = "disabled"; + }; + + combphy2: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, + <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; + reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>; + status = "disabled"; + }; + + csi_dphy: phy@fe870000 { + compatible = "rockchip,rk3568-csi-dphy"; + reg = <0x0 0xfe870000 0x0 0x10000>; + clocks = <&cru PCLK_MIPICSIPHY>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_MIPICSIPHY>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + dsi_dphy0: mipi-dphy@fe850000 { + compatible = "rockchip,rk3568-dsi-dphy"; + reg = <0x0 0xfe850000 0x0 0x10000>; + clock-names = "ref", "pclk"; + clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; + #phy-cells = <0>; + power-domains = <&power RK3568_PD_VO>; + reset-names = "apb"; + resets = <&cru SRST_P_MIPIDSIPHY0>; + status = "disabled"; + }; + + dsi_dphy1: mipi-dphy@fe860000 { + compatible = "rockchip,rk3568-dsi-dphy"; + reg = <0x0 0xfe860000 0x0 0x10000>; + clock-names = "ref", "pclk"; + clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; + #phy-cells = <0>; + power-domains = <&power RK3568_PD_VO>; + reset-names = "apb"; + resets = <&cru SRST_P_MIPIDSIPHY1>; + status = "disabled"; + }; + + usb2phy0: usb2phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8a0000 0x0 0x10000>; + clocks = <&pmucru CLK_USBPHY0_REF>; + clock-names = "phyclk"; + clock-output-names = "clk_usbphy0_480m"; + interrupts = ; + rockchip,usbgrf = <&usb2phy0_grf>; + #clock-cells = <0>; + status = "disabled"; + + usb2phy0_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + usb2phy1: usb2phy@fe8b0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8b0000 0x0 0x10000>; + clocks = <&pmucru CLK_USBPHY1_REF>; + clock-names = "phyclk"; + clock-output-names = "clk_usbphy1_480m"; + interrupts = ; + rockchip,usbgrf = <&usb2phy1_grf>; + #clock-cells = <0>; + status = "disabled"; + + usb2phy1_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfdd60000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fe740000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe740000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fe750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe750000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe760000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fe770000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe770000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3568-pinctrl.dtsi" From 0240e880f9bf222952e4733b5e1a22dc2ab24667 Mon Sep 17 00:00:00 2001 From: andreili Date: Fri, 25 Jul 2025 23:12:30 +0200 Subject: [PATCH 02/28] Reset tro default state. --- tmp/rk3566-bigtreetech-cb2.dtsi | 679 ++------------------------------ tmp/rk3566-bigtreetech-pi2.dts | 60 --- tmp/rk356x-base.dtsi | 41 -- 3 files changed, 43 insertions(+), 737 deletions(-) diff --git a/tmp/rk3566-bigtreetech-cb2.dtsi b/tmp/rk3566-bigtreetech-cb2.dtsi index 93b514f..7eb11ef 100644 --- a/tmp/rk3566-bigtreetech-cb2.dtsi +++ b/tmp/rk3566-bigtreetech-cb2.dtsi @@ -33,6 +33,17 @@ #clock-cells = <0>; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -109,7 +120,7 @@ compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie"; enable-active-high; - gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie_drv>; regulator-always-on; @@ -214,355 +225,6 @@ regulator-name = "vcc_sd"; vin-supply = <&vcc3v3_sys>; }; - - ddr3_params: ddr3-params { - version = <0x100>; - expanded_version = <0x00>; - reserved = <0x00>; - freq_0 = <0x420>; - freq_1 = <0x144>; - freq_2 = <0x210>; - freq_3 = <0x30c>; - freq_4 = <0x00>; - freq_5 = <0x00>; - pd_idle = <0x0d>; - sr_idle = <0x5d>; - sr_mc_gate_idle = <0x00>; - srpd_lite_idle = <0x00>; - standby_idle = <0x00>; - pd_dis_freq = <0x42a>; - sr_dis_freq = <0x320>; - dram_dll_dis_freq = <0x12c>; - phy_dll_dis_freq = <0x00>; - phy_dq_drv_odten = <0x21>; - phy_ca_drv_odten = <0x21>; - phy_clk_drv_odten = <0x21>; - dram_dq_drv_odten = <0x22>; - phy_dq_drv_odtoff = <0x21>; - phy_ca_drv_odtoff = <0x21>; - phy_clk_drv_odtoff = <0x21>; - dram_dq_drv_odtoff = <0x22>; - dram_odt = <0x78>; - phy_odt = <0xa7>; - phy_odt_puup_en = <0x01>; - phy_odt_pudn_en = <0x01>; - dram_dq_odt_en_freq = <0x14d>; - phy_odt_en_freq = <0x14d>; - phy_dq_sr_odten = <0x0f>; - phy_ca_sr_odten = <0x03>; - phy_clk_sr_odten = <0x00>; - phy_dq_sr_odtoff = <0x0f>; - phy_ca_sr_odtoff = <0x03>; - phy_clk_sr_odtoff = <0x00>; - ssmod_downspread = <0x00>; - ssmod_div = <0x00>; - ssmod_spread = <0x00>; - mode_2t = <0x00>; - speed_bin = <0x15>; - dram_ext_temp = <0x00>; - byte_map = <0xe4>; - dq_map_cs0_dq_l = <0x00>; - dq_map_cs0_dq_h = <0x00>; - dq_map_cs1_dq_l = <0x00>; - dq_map_cs1_dq_h = <0x00>; - }; - - ddr4_params: ddr4-params { - version = <0x100>; - expanded_version = <0x00>; - reserved = <0x00>; - freq_0 = <0x420>; - freq_1 = <0x144>; - freq_2 = <0x210>; - freq_3 = <0x30c>; - freq_4 = <0x00>; - freq_5 = <0x00>; - pd_idle = <0x0d>; - sr_idle = <0x5d>; - sr_mc_gate_idle = <0x00>; - srpd_lite_idle = <0x00>; - standby_idle = <0x00>; - pd_dis_freq = <0x42a>; - sr_dis_freq = <0x320>; - dram_dll_dis_freq = <0x271>; - phy_dll_dis_freq = <0x00>; - phy_dq_drv_odten = <0x25>; - phy_ca_drv_odten = <0x25>; - phy_clk_drv_odten = <0x25>; - dram_dq_drv_odten = <0x22>; - phy_dq_drv_odtoff = <0x25>; - phy_ca_drv_odtoff = <0x25>; - phy_clk_drv_odtoff = <0x25>; - dram_dq_drv_odtoff = <0x22>; - dram_odt = <0x78>; - phy_odt = <0x8b>; - phy_odt_puup_en = <0x01>; - phy_odt_pudn_en = <0x01>; - dram_dq_odt_en_freq = <0x1f4>; - phy_odt_en_freq = <0x1f4>; - phy_dq_sr_odten = <0x0e>; - phy_ca_sr_odten = <0x01>; - phy_clk_sr_odten = <0x01>; - phy_dq_sr_odtoff = <0x0e>; - phy_ca_sr_odtoff = <0x01>; - phy_clk_sr_odtoff = <0x01>; - ssmod_downspread = <0x00>; - ssmod_div = <0x00>; - ssmod_spread = <0x00>; - mode_2t = <0x00>; - speed_bin = <0x0c>; - dram_ext_temp = <0x00>; - byte_map = <0xe4>; - dq_map_cs0_dq_l = <0x22777788>; - dq_map_cs0_dq_h = <0xd7888877>; - dq_map_cs1_dq_l = <0x22777788>; - dq_map_cs1_dq_h = <0xd7888877>; - }; - - lpddr3_params: lpddr3-params { - version = <0x100>; - expanded_version = <0x00>; - reserved = <0x00>; - freq_0 = <0x420>; - freq_1 = <0x144>; - freq_2 = <0x210>; - freq_3 = <0x30c>; - freq_4 = <0x00>; - freq_5 = <0x00>; - pd_idle = <0x0d>; - sr_idle = <0x5d>; - sr_mc_gate_idle = <0x00>; - srpd_lite_idle = <0x00>; - standby_idle = <0x00>; - pd_dis_freq = <0x42a>; - sr_dis_freq = <0x320>; - dram_dll_dis_freq = <0x00>; - phy_dll_dis_freq = <0x00>; - phy_dq_drv_odten = <0x25>; - phy_ca_drv_odten = <0x25>; - phy_clk_drv_odten = <0x27>; - dram_dq_drv_odten = <0x22>; - phy_dq_drv_odtoff = <0x25>; - phy_ca_drv_odtoff = <0x25>; - phy_clk_drv_odtoff = <0x27>; - dram_dq_drv_odtoff = <0x22>; - dram_odt = <0x78>; - phy_odt = <0x94>; - phy_odt_puup_en = <0x01>; - phy_odt_pudn_en = <0x01>; - dram_dq_odt_en_freq = <0x14d>; - phy_odt_en_freq = <0x14d>; - phy_dq_sr_odten = <0x0f>; - phy_ca_sr_odten = <0x01>; - phy_clk_sr_odten = <0x0f>; - phy_dq_sr_odtoff = <0x0f>; - phy_ca_sr_odtoff = <0x01>; - phy_clk_sr_odtoff = <0x0f>; - ssmod_downspread = <0x00>; - ssmod_div = <0x00>; - ssmod_spread = <0x00>; - mode_2t = <0x00>; - speed_bin = <0x00>; - dram_ext_temp = <0x00>; - byte_map = <0x8d>; - dq_map_cs0_dq_l = <0x00>; - dq_map_cs0_dq_h = <0x00>; - dq_map_cs1_dq_l = <0x00>; - dq_map_cs1_dq_h = <0x00>; - }; - - lpddr4_params: lpddr4-params { - version = <0x100>; - expanded_version = <0x00>; - reserved = <0x00>; - freq_0 = <0x420>; - freq_1 = <0x144>; - freq_2 = <0x210>; - freq_3 = <0x30c>; - freq_4 = <0x00>; - freq_5 = <0x00>; - pd_idle = <0x0d>; - sr_idle = <0x5d>; - sr_mc_gate_idle = <0x00>; - srpd_lite_idle = <0x00>; - standby_idle = <0x00>; - pd_dis_freq = <0x42a>; - sr_dis_freq = <0x320>; - dram_dll_dis_freq = <0x00>; - phy_dll_dis_freq = <0x00>; - phy_dq_drv_odten = <0x1e>; - phy_ca_drv_odten = <0x26>; - phy_clk_drv_odten = <0x26>; - dram_dq_drv_odten = <0x28>; - phy_dq_drv_odtoff = <0x1e>; - phy_ca_drv_odtoff = <0x26>; - phy_clk_drv_odtoff = <0x26>; - dram_dq_drv_odtoff = <0x28>; - dram_odt = <0x50>; - phy_odt = <0x3c>; - phy_odt_puup_en = <0x00>; - phy_odt_pudn_en = <0x00>; - dram_dq_odt_en_freq = <0x320>; - phy_odt_en_freq = <0x320>; - phy_dq_sr_odten = <0x00>; - phy_ca_sr_odten = <0x0f>; - phy_clk_sr_odten = <0x0f>; - phy_dq_sr_odtoff = <0x00>; - phy_ca_sr_odtoff = <0x0f>; - phy_clk_sr_odtoff = <0x0f>; - ssmod_downspread = <0x00>; - ssmod_div = <0x00>; - ssmod_spread = <0x00>; - mode_2t = <0x00>; - speed_bin = <0x00>; - dram_ext_temp = <0x00>; - byte_map = <0xe4>; - dq_map_cs0_dq_l = <0x00>; - dq_map_cs0_dq_h = <0x00>; - dq_map_cs1_dq_l = <0x00>; - dq_map_cs1_dq_h = <0x00>; - lp4_ca_odt = <0x78>; - lp4_drv_pu_cal_odten = <0x01>; - lp4_drv_pu_cal_odtoff = <0x01>; - phy_lp4_drv_pulldown_en_odten = <0x00>; - phy_lp4_drv_pulldown_en_odtoff = <0x00>; - lp4_ca_odt_en_freq = <0x320>; - phy_lp4_cs_drv_odten = <0x00>; - phy_lp4_cs_drv_odtoff = <0x00>; - lp4_odte_ck_en = <0x01>; - lp4_odte_cs_en = <0x01>; - lp4_odtd_ca_en = <0x00>; - phy_lp4_dq_vref_odten = <0xa6>; - lp4_dq_vref_odten = <0x12c>; - lp4_ca_vref_odten = <0x17c>; - phy_lp4_dq_vref_odtoff = <0x1a4>; - lp4_dq_vref_odtoff = <0x1a4>; - lp4_ca_vref_odtoff = <0x1a4>; - }; - - lpddr4x_params: lpddr4x-params { - version = <0x100>; - expanded_version = <0x00>; - reserved = <0x00>; - freq_0 = <0x420>; - freq_1 = <0x144>; - freq_2 = <0x210>; - freq_3 = <0x30c>; - freq_4 = <0x00>; - freq_5 = <0x00>; - pd_idle = <0x0d>; - sr_idle = <0x5d>; - sr_mc_gate_idle = <0x00>; - srpd_lite_idle = <0x00>; - standby_idle = <0x00>; - pd_dis_freq = <0x42a>; - sr_dis_freq = <0x320>; - dram_dll_dis_freq = <0x00>; - phy_dll_dis_freq = <0x00>; - phy_dq_drv_odten = <0x1d>; - phy_ca_drv_odten = <0x24>; - phy_clk_drv_odten = <0x24>; - dram_dq_drv_odten = <0x28>; - phy_dq_drv_odtoff = <0x1d>; - phy_ca_drv_odtoff = <0x24>; - phy_clk_drv_odtoff = <0x24>; - dram_dq_drv_odtoff = <0x28>; - dram_odt = <0x50>; - phy_odt = <0x3c>; - phy_odt_puup_en = <0x00>; - phy_odt_pudn_en = <0x00>; - dram_dq_odt_en_freq = <0x320>; - phy_odt_en_freq = <0x320>; - phy_dq_sr_odten = <0x00>; - phy_ca_sr_odten = <0x00>; - phy_clk_sr_odten = <0x00>; - phy_dq_sr_odtoff = <0x00>; - phy_ca_sr_odtoff = <0x00>; - phy_clk_sr_odtoff = <0x00>; - ssmod_downspread = <0x00>; - ssmod_div = <0x00>; - ssmod_spread = <0x00>; - mode_2t = <0x00>; - speed_bin = <0x00>; - dram_ext_temp = <0x00>; - byte_map = <0xe4>; - dq_map_cs0_dq_l = <0x00>; - dq_map_cs0_dq_h = <0x00>; - dq_map_cs1_dq_l = <0x00>; - dq_map_cs1_dq_h = <0x00>; - lp4_ca_odt = <0x78>; - lp4_drv_pu_cal_odten = <0x00>; - lp4_drv_pu_cal_odtoff = <0x00>; - phy_lp4_drv_pulldown_en_odten = <0x00>; - phy_lp4_drv_pulldown_en_odtoff = <0x00>; - lp4_ca_odt_en_freq = <0x320>; - phy_lp4_cs_drv_odten = <0x00>; - phy_lp4_cs_drv_odtoff = <0x00>; - lp4_odte_ck_en = <0x00>; - lp4_odte_cs_en = <0x00>; - lp4_odtd_ca_en = <0x00>; - phy_lp4_dq_vref_odten = <0xa6>; - lp4_dq_vref_odten = <0xe4>; - lp4_ca_vref_odten = <0x157>; - phy_lp4_dq_vref_odtoff = <0x1a4>; - lp4_dq_vref_odtoff = <0x1a4>; - lp4_ca_vref_odtoff = <0x157>; - }; - - dmc: dmc { - compatible = "rockchip,rk3568-dmc"; - interrupts = ; - interrupt-names = "complete"; - devfreq-events = <&dfi 0xa2>; - clocks = <&scmi_clk 0x03>; - clock-names = "dmc_clk"; - operating-points-v2 = <&dmc_opp_table>; - vop-bw-dmc-freq = <0x00 0x11e 0x4f1a0 0x11f 0x1869f 0x80e80>; - vop-frame-bw-dmc-freq = <0x00 0x26c 0x4f1a0 0x26d 0x1869f 0xbe6e0>; - cpu-bw-dmc-freq = <0x00 0x15e 0x4f1a0 0x15f 0x190 0x80e80 0x191 0x1869f 0xbe6e0>; - upthreshold = <0x28>; - downdifferential = <0x14>; - system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08>; - auto-min-freq = <0x4f1a0>; - auto-freq-en = <1>; - #cooling-cells = <2>; - status = "disabled"; - center-supply = <&vdd_logic>; - }; - - dmc_fsp: dmc-fsp { - compatible = "rockchip,rk3568-dmc-fsp"; - debug_print_level = <0>; - ddr3_params = <&ddr3_params>; - ddr4_params = <&ddr4_params>; - lpddr3_params = <&lpddr3_params>; - lpddr4_params = <&lpddr4_params>; - lpddr4x_params = <&lpddr4x_params>; - status = "disabled"; - }; - - dmc_opp_table: dmc-opp-table { - compatible = "operating-points-v2"; - mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; - nvmem-cells = <0x70 0x07 0x08 0xa9 0x0a 0x0b>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info", "specification_serial_number", "remark_spec_serial_number"; - rockchip,supported-hw; - rockchip,max-volt = <0xf4240>; - rockchip,temp-hysteresis = <0x1388>; - rockchip,low-temp = <0x00>; - rockchip,low-temp-adjust-volt = <0x00 0x618 0x124f8>; - rockchip,leakage-voltage-sel = <0x01 0x50 0x00 0x51 0xfe 0x01>; - rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x186a0 0x01>; - rockchip,pvtm-ch = <0x00 0x05>; - - opp-1560000000 { - opp-supported-hw = <0xf9 0xffff>; - opp-hz = <0x00 0x5cfbb600>; - opp-microvolt = <0xdbba0 0xdbba0 0xf4240>; - opp-microvolt-L0 = <0xdbba0 0xdbba0 0xf4240>; - opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240>; - }; - }; }; &combphy1 { @@ -603,8 +265,6 @@ &gmac1m0_rgmii_clk &gmac1m0_clkinout &gmac1m0_rgmii_bus>; - tx_delay = <0x30>; - rx_delay = <0x10>; status = "okay"; }; @@ -620,289 +280,29 @@ &gpu { mali-supply = <&vdd_gpu>; - status = "disabled"; - upthreshold = <0x28>; - downdifferential = <0x0a>; + status = "okay"; +}; - gpu_power_model: power-model { - compatible = "simple-power-model"; - leakage-range = <0x05 0x0f>; - ls = <0xffffa23e 0x5927 0x00>; - static-coefficient = <0x186a0>; - dynamic-coefficient = <0x3b9>; - ts = <0xfffe56a6 0xf87a 0xfffffab5 0x14>; - thermal-zone = "gpu-thermal"; +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; }; }; -&display_subsystem { - devfreq = <&dmc>; - status = "disabled"; - - route { - route_dsi0: route-dsi0 { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <0x11>; - }; - - route_dsi1: route-dsi1 { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <0x12>; - }; - - route_edp: route-edp { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <0x13>; - }; - - route_hdmi: route-hdmi { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <0x14>; - }; - - route_lvds: route-lvds { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <0x15>; - }; - - route_rgb: route-rgb { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <0x16>; - }; +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; }; }; -&vp0 { - #address-cells = <1>; - #size-cells = <0>; - - vp0_out_dsi0: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi0_in_vp0>; - }; - - vp0_out_dsi1: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi1_in_vp0>; - }; - - vp0_out_edp: endpoint@2 { - reg = <2>; - remote-endpoint = <&edp_in_vp0>; - }; - - /*vp0_out_hdmi: endpoint@3 { - reg = <3>; - remote-endpoint = <&hdmi_in_vp0>; - };*/ -}; - -&vp1 { - #address-cells = <1>; - #size-cells = <0>; - - vp1_out_dsi0: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi0_in_vp1>; - }; - - vp1_out_dsi1: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi1_in_vp1>; - }; - - vp1_out_edp: endpoint@2 { - reg = <2>; - remote-endpoint = <&edp_in_vp1>; - }; - - /*vp1_out_hdmi: endpoint@3 { - reg = <3>; - remote-endpoint = <&hdmi_in_vp1>; - };*/ - - vp1_out_lvds: endpoint@4 { - reg = <4>; - remote-endpoint = <&lvds_in_vp1>; - }; -}; - -&vp2 { - #address-cells = <1>; - #size-cells = <0>; - - vp2_out_lvds: endpoint@0 { - reg = <0>; - remote-endpoint = <&lvds_in_vp2>; - }; - - vp2_out_rgb: endpoint@1 { - reg = <1>; - remote-endpoint = <&rgb_in_vp2>; - }; -}; - - -&dsi0_in { - dsi0_in_vp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vp0_out_dsi0>; - status = "disabled"; - }; - - dsi0_in_vp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vp1_out_dsi0>; - status = "disabled"; - }; -}; - -&dsi1_in { - reg = <0>; - - dsi1_in_vp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vp0_out_dsi1>; - status = "disabled"; - }; - - dsi1_in_vp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vp1_out_dsi1>; - status = "disabled"; - }; -}; - -&dsi1_out { - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; -}; - -&dsi1 { - dsi1_panel: panel@0 { - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - power-supply = <&vcc3v3_sys>; - compatible = "btt-pitft"; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; -}; - -&edp_in{ - #address-cells = <1>; - #size-cells = <0>; - - edp_in_vp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vp0_out_edp>; - status = "disabled"; - }; - - edp_in_vp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vp1_out_edp>; - status = "disabled"; - }; -}; - -&grf { - io_domains: io-domains { - compatible = "rockchip,rk3568-io-voltage-domain"; - status = "disabled"; - }; - - lvds: lvds { - compatible = "rockchip,rk3568-lvds"; - phys = <&dsi_dphy0>; - phy-names = "phy"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - lvds_in_vp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vp1_out_lvds>; - status = "disabled"; - }; - - lvds_in_vp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vp2_out_lvds>; - status = "disabled"; - }; - }; - }; - }; - - rgb: rgb { - compatible = "rockchip,rk3568-rgb"; - pinctrl-names = "default"; - pinctrl-0 = <&lcdc_ctl>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - rgb_in_vp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vp2_out_rgb>; - status = "disabled"; - }; - }; - }; - }; +&hdmi_sound { + status = "okay"; }; &i2c0 { @@ -1168,7 +568,7 @@ tft_tp: touchscreen@48 { compatible = "ti,tsc2007"; reg = <0x48>; - status = "disabled"; + status = "okay"; ti,x-plate-ohms = <660>; ti,rt-thr = <3000>; ti,fuzzx = <32>; @@ -1177,14 +577,14 @@ }; &i2s0_8ch { - status = "disabled"; + status = "okay"; }; &i2s1_8ch { pinctrl-names = "default"; pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; rockchip,trcm-sync-tx-only; - status = "disabled"; + status = "okay"; }; &spi1 { @@ -1215,7 +615,7 @@ pinctrl-0 = <&pcie_reset_h>; reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; - status = "disabled"; + status = "okay"; }; &pinctrl { @@ -1334,7 +734,7 @@ &saradc { vref-supply = <&vcca_1v8>; - status = "disabled"; + status = "okay"; }; &sdhci { @@ -1395,7 +795,7 @@ }; &tsadc { - status = "disabled"; + status = "okay"; }; &uart1 { @@ -1490,9 +890,16 @@ &vop { assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "disabled"; + status = "okay"; }; &vop_mmu { - status = "disabled"; + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; }; diff --git a/tmp/rk3566-bigtreetech-pi2.dts b/tmp/rk3566-bigtreetech-pi2.dts index d3cf88a..7cd444c 100644 --- a/tmp/rk3566-bigtreetech-pi2.dts +++ b/tmp/rk3566-bigtreetech-pi2.dts @@ -8,63 +8,3 @@ model = "BigTreeTech Pi 2"; compatible = "bigtreetech,pi2", "rockchip,rk3566"; }; - -&sfc { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -&i2c2 { - status = "disabled"; - - bl_dsi: regulator@45 { - status = "disabled"; - compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; - reg = <0x45>; - }; - - tp_dsi: ft5406@38 { - status = "disabled"; - compatible = "edt,edt-ft5406"; - reg = <0x38>; - vcc-supply = <&vcc3v3_sys>; - iovcc-supply = <&vcc_3v3>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-inverted-y; - }; -}; - -&dsi1 { - status = "disabled"; -}; - -&dsi1_panel { - status = "disabled"; -}; - -&dsi1_in_vp1 { - status = "disabled"; -}; - -&dsi_dphy1 { - status = "disabled"; -}; - -&tp_dsi { - status = "disabled"; -}; - -&bl_dsi { - status = "disabled"; -}; diff --git a/tmp/rk356x-base.dtsi b/tmp/rk356x-base.dtsi index 51d1b02..a3b0f2c 100644 --- a/tmp/rk356x-base.dtsi +++ b/tmp/rk356x-base.dtsi @@ -140,7 +140,6 @@ scmi_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; - rockchip,clk-init = <1104000000>; }; }; }; @@ -835,46 +834,6 @@ }; }; - edp: edp@fe0c0000 { - compatible = "rockchip,rk3568-edp"; - reg = <0x00 0xfe0c0000 0x00 0x10000>; - interrupts = ; - clocks = <&pmucru XIN_OSC0_EDPPHY_G>, - <&cru PCLK_EDP_CTRL>, - <&cru CLK_EDP_200M>, - <&cru HCLK_VO>; - clock-names = "dp", "pclk", "spdif", "hclk"; - resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>; - reset-names = "dp", "apb"; - phys = <&edp_phy_grf>; - phy-names = "dp"; - power-domains = <&power RK3568_PD_VO>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - edp_in: port@0 { - reg = <0>; - }; - }; - }; - - edp_phy_grf: syscon@fdcb0000 { - compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd"; - reg = <0x00 0xfdcb0000 0x00 0x100>; - clocks = <&cru PCLK_EDPPHY_GRF>; - - edp_phy: edp-phy { - compatible = "rockchip,rk3568-edp-phy"; - clocks = <&pmucru XIN_OSC0_EDPPHY_G>; - clock-names = "refclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - qos_gpu: qos@fe128000 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe128000 0x0 0x20>; From df9cb17d298082c163ecdb59e2d50da0e23b7b7b Mon Sep 17 00:00:00 2001 From: andreili Date: Fri, 25 Jul 2025 23:21:19 +0200 Subject: [PATCH 03/28] BTT Pi2 - fix PCIe regulator enable pin. --- tmp/rk3566-bigtreetech-cb2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tmp/rk3566-bigtreetech-cb2.dtsi b/tmp/rk3566-bigtreetech-cb2.dtsi index 7eb11ef..bcfa60b 100644 --- a/tmp/rk3566-bigtreetech-cb2.dtsi +++ b/tmp/rk3566-bigtreetech-cb2.dtsi @@ -120,7 +120,7 @@ compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie"; enable-active-high; - gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie_drv>; regulator-always-on; From 637e6d9fd898040bdd99289c217057df40714f9b Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 27 Jul 2025 01:04:12 +0200 Subject: [PATCH 04/28] Add SQH modules support --- config/board/btt_cb1.json | 7 +++- config/board/btt_pi2.json | 7 +++- config/board/opi_zero2.json | 7 +++- config/os_aarch64.json | 55 ++++++++++++++++++++++++++--- files/initramfs/init | 69 +++++++++++++++++-------------------- scripts/os.py | 16 +++++++++ scripts/sources.py | 7 ++++ scripts/target.py | 1 + 8 files changed, 124 insertions(+), 45 deletions(-) diff --git a/config/board/btt_cb1.json b/config/board/btt_cb1.json index a6e53ea..3f0714f 100644 --- a/config/board/btt_cb1.json +++ b/config/board/btt_cb1.json @@ -69,9 +69,14 @@ "file": "arch/arm64/boot/dts/allwinner/overlay/sun50i-h616*.dtbo", "store_type": "boot", "subdir": "dtb/allwinner/overlay" + }, + { + "file": "", + "store_type": "boot", + "kmods": true } ], - "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods" + "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods/usr" }, { "parent": "rtl8189ES_linux", diff --git a/config/board/btt_pi2.json b/config/board/btt_pi2.json index a43b7b4..fa5c553 100644 --- a/config/board/btt_pi2.json +++ b/config/board/btt_pi2.json @@ -71,9 +71,14 @@ "file": "arch/arm64/boot/dts/%{DTB_FILE}%", "store_type": "boot", "subdir": "dtb/rockchip" + }, + { + "file": "", + "store_type": "boot", + "kmods": true } ], - "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods" + "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods/usr" } ], "install": diff --git a/config/board/opi_zero2.json b/config/board/opi_zero2.json index a5debb3..21cbdcb 100644 --- a/config/board/opi_zero2.json +++ b/config/board/opi_zero2.json @@ -70,9 +70,14 @@ "file": "arch/arm64/boot/dts/allwinner/overlay/sun50i-h616*.dtbo", "store_type": "boot", "subdir": "dtb/allwinner/overlay" + }, + { + "file": "", + "store_type": "boot", + "kmods": true } ], - "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods" + "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods/usr" } ], "install": diff --git a/config/os_aarch64.json b/config/os_aarch64.json index 0677ad6..4241bf3 100644 --- a/config/os_aarch64.json +++ b/config/os_aarch64.json @@ -1,7 +1,9 @@ { "variables": [ - "USER_LOGIN:klipper" + "USER_LOGIN:klipper", + "USER_ID:1010", + "TIME_ZONE:Europe/Warsaw" ], "stage3_info": { @@ -198,17 +200,60 @@ { "steps": [ - { "chroot": "systemctl enable NetworkManager ntpdate sshd" }, + { + "file": "/etc/systemd/system/prepare_shutdown.service", + "append": false, + "lines": [ + "[Unit]", + "Description=Prepare a shutdown script to correctly unmount all filesystems", + "[Install]", + "WantedBy=multi-user.target", + "[Service]", + "Type=oneshot", + "ExecStart=sh -c \"mkdir -p /run/initramfs && cd /run/initramfs && tar xf /usr/shutdown.tar.xz\"" + ] + }, + { + "file": "/etc/systemd/system/sync.service", + "append": false, + "lines": [ + "[Unit]", + "Description=Sync all data", + "StartLimitIntervalSec=0", + "[Service]", + "Type=simple", + "Restart=always", + "RestartSec=10", + "User=root", + "ExecStart=/usr/local/bin/sync.sh", + "[Install]", + "WantedBy=multi-user.target" + ] + }, + { + "file": "/usr/local/bin/sync.sh", + "append": false, + "lines": [ + "#!/bin/bash", + "# regular sync to prevent data loss when direct power outage", + "while [ 1 ]; do", + " sync", + " sleep 60", + "done" + ], + "chmod": "+x" + }, + { "chroot": "systemctl enable NetworkManager ntpdate sshd prepare_shutdown sync" }, { "sudo": "sed -i -E 's/^# (%wheel ALL)/\\1/' ./etc/sudoers" }, { "sudo": "sed -i -E 's/^#(\\S+MaxUse)=$/\\1=10M/' ./etc/systemd/journald.conf" }, { "sudo": "sed -i -E 's/^#(\\S+MaxFileSize)=$/\\1=10M/' ./etc/systemd/journald.conf" }, { "copy": [ "%{ROOT_DIR}%/files/firmware/usr", "."] }, { "sudo": "chmod u+s ./usr/bin/Xorg" }, - { "sudo": "ln -sf /usr/share/zoneinfo/Europe/Warsaw ./etc/localtime" }, - { "chroot": "useradd -m -G wheel,video,audio,disk,usb %{USER_LOGIN}% --password %{USER_LOGIN}%" }, + { "sudo": "ln -sf /usr/share/zoneinfo/%{TIME_ZONE}% ./etc/localtime" }, + { "chroot": "useradd -m -G wheel,video,audio,disk,usb -g %{USER_ID}% -u %{USER_ID}% %{USER_LOGIN}% --password %{USER_LOGIN}%" }, { "chroot": "echo '%{USER_LOGIN}%:%{USER_LOGIN}%' | chpasswd" }, { "chroot": "echo 'root:root' | chpasswd" }, - { "chroot": "sudo -i -u klipper python -m venv /home/%{USER_LOGIN}%/venv" }, + { "chroot": "sudo -i -u %{USER_LOGIN}% python -m venv /home/%{USER_LOGIN}%/venv" }, { "soft_clean": "bdeps" } ] } diff --git a/files/initramfs/init b/files/initramfs/init index 7f36d6a..10f1cce 100644 --- a/files/initramfs/init +++ b/files/initramfs/init @@ -71,48 +71,43 @@ done # [ ! -d "${i}" ] && run mkdir -p "${i}" #done run mount -t squashfs -o loop,ro "${CDROOT_PATH}/${LOOP}" "${STATIC}" || run_emergency_shell -#if [ -d ${CDROOT_PATH}/modules ] -#then -# warn_msg "Adding all modules in ${CDROOT_PATH}/modules" -# for module in "${CDROOT_PATH}/modules/"*.lzm; do -# mod=${module##*/} -# mod=${mod//-/_} -# mod=${mod%.*} -# if [ ! -d "${OVERLAY}/.${mod}" ] -# then -# run mkdir -p "${OVERLAY}/.${mod}" || return -# fi -# run mount -o loop,ro "${module}" "${OVERLAY}/.${mod}" -# mod_path="${mod_path}:${OVERLAY}/.${mod}" -# # Assign variable with paths to modules mount point -# # TODO: Stop using eval -# eval ${mod}="${OVERLAY}/.${mod}" -# mods="${mods} ${mod}" -# done -#fi +if [ -d ${CDROOT_PATH}/modules ] +then + warn_msg "Adding all modules in ${CDROOT_PATH}/modules" + for module in "${CDROOT_PATH}/modules/"*.lzm; do + mod=${module##*/} + mod=${mod//-/_} + mod=${mod%.*} + if [ ! -d "${OVERLAY}/.${mod}" ] + then + run mkdir -p "${OVERLAY}/.${mod}" || return + fi + run mount -o loop,ro "${module}" "${OVERLAY}/.${mod}" + mod_path="${mod_path}:${OVERLAY}/.${mod}" + # Assign variable with paths to modules mount point + # TODO: Stop using eval + eval ${mod}="${OVERLAY}/.${mod}" + mods="${mods} ${mod}" + done +fi run mount -t overlay overlay -o lowerdir="${STATIC}${mod_path}",upperdir="${upperdir}",workdir="${workdir}" "${NEW_ROOT}" || run_emergency_shell for i in "${RW_MNT}" "${STATIC}" "${CDROOT_PATH}" do [ ! -d "${NEW_ROOT}${i}" ] && run mkdir -p "${NEW_ROOT}${i}" + run mount --move "${i}" "${NEW_ROOT}${i}" || run_emergency_shell done -#echo "overlay / overlay defaults 0 0" > "${NEW_ROOT}"/etc/fstab -#run mkdir -p "${NEW_ROOT}${OVERLAY}" -#run chmod 755 "${NEW_ROOT}${OVERLAY}" -#run mount --bind "${OVERLAY}" "${NEW_ROOT}${OVERLAY}" -#run mount --bind "${STATIC}" "${NEW_ROOT}${STATIC}" -#if [ -n "${mods}" ] -#then -# for i in ${mods} -# do -# run mount --bind "${OVERLAY}/.${i}" "${NEW_ROOT}/${OVERLAY}/.${i}" -# done -#fi -#[ ! -d "${NEW_ROOT}${CDROOT_PATH}" ] && mkdir -p "${NEW_ROOT}${CDROOT_PATH}" -#run mount --bind "${CDROOT_PATH}" "${NEW_ROOT}${CDROOT_PATH}" -#run mount --bind "${RW_MNT}" "${NEW_ROOT}${RW_MNT}" -run mount --move "${CDROOT_PATH}" "${NEW_ROOT}${CDROOT_PATH}" || run_emergency_shell -run mount --move "${RW_MNT}" "${NEW_ROOT}${RW_MNT}" || run_emergency_shell -run mount --move "${STATIC}" "${NEW_ROOT}${STATIC}" || run_emergency_shell + +#run mount --move "${CDROOT_PATH}" "${NEW_ROOT}${CDROOT_PATH}" || run_emergency_shell +#run mount --move "${RW_MNT}" "${NEW_ROOT}${RW_MNT}" || run_emergency_shell +#run mount --move "${STATIC}" "${NEW_ROOT}${STATIC}" || run_emergency_shell +if [ -n "${mods}" ] +then + for i in ${mods} + do + [ ! -d "${NEW_ROOT}${OVERLAY}/.${i}" ] && run mkdir -p "${NEW_ROOT}${OVERLAY}/.${i}" + run mount --bind "${OVERLAY}/.${i}" "${NEW_ROOT}/${OVERLAY}/.${i}" + done +fi #for m in ${MODULES}; do # run insmod "${NEW_ROOT}${m}" diff --git a/scripts/os.py b/scripts/os.py index 5615a9b..931482a 100644 --- a/scripts/os.py +++ b/scripts/os.py @@ -92,6 +92,9 @@ class OS: cmd += f" | sudo tee {is_append} {self.root_dir}{path} > /dev/null" Logger.os(f"\tCreate file {path}...") self.__sudo(cmd, shell=True, cwd=dir) + if ("chmod" in step): + mode = step["chmod"] + self.__sudo(f"chmod {mode} {dir}{path}", shell=True, cwd=dir) if ("chroot" in step): cmd = self.board.parse_variables(step["chroot"]) self.__chroot(cmd, dir=dir) @@ -239,8 +242,20 @@ class OS: def __finalize(self, dir): self.__stage3_steps(self.finalize, "Finalize system installation...", dir=dir) + def make_sqh_kmod(self): + mod_path = f"{ROOT_DIR}/out/modules" + os.makedirs(mod_path, exist_ok=True) + kmod_fn = self.board.parse_variables("%{out_dir}%/kmods/usr/lib/modules") + kmod = Path(kmod_fn) + for f in kmod.iterdir(): + sqh_name = f.name + self.__make_sqh(f"{kmod_fn}/../../..", f"{mod_path}/{sqh_name}.lzm") + break + def sqh(self): self.__relaunch_as_sudo() + self.make_sqh_kmod() + exit(0) date = datetime.datetime.today().strftime('%Y_%m_%d') temp_dir = f"{ROOT_DIR}/build/tmp" # pack full system via tar @@ -410,6 +425,7 @@ class OS: self.__copy_file(f"{self.board.out_sh}/uInitrd", f"{out_dir}/") Logger.install(f"\tCopy root.sqh") self.__sudo(["cp", "-H", f"{self.board.out_sh}/root.sqh", f"{out_dir}/"]) + self.__sudo(["cp", "-H", f"{self.board.out_sh}/modules", f"{out_dir}/"]) def __install_rw(self, out_dir): self.__sudo(["touch", f"{out_dir}/rw_part"], stdout=subprocess.DEVNULL) diff --git a/scripts/sources.py b/scripts/sources.py index 04fbbf8..c708f09 100644 --- a/scripts/sources.py +++ b/scripts/sources.py @@ -264,8 +264,15 @@ class Sources: # copy new configurtion, if exists shutil.copyfile(work_cfg_name, cfg_name) + def prepare_artifacts(self, artifacts, out_dir): + for art in artifacts: + if ("kmods" in art): + shutil.rmtree(f"{out_dir}/kmods") + def copy_artifacts(self, artifacts, out_dir): for art in artifacts: + if ("kmods" in art): + continue file_name = self.work_dir + "/" + art["file"] if ("subdir" in art): dir_o = out_dir + "/" + art["subdir"] + "/" diff --git a/scripts/target.py b/scripts/target.py index 049f811..1f98772 100644 --- a/scripts/target.py +++ b/scripts/target.py @@ -72,6 +72,7 @@ class Target: def build(self, sub_target, out_dir): self.source_sync() + self.sources.prepare_artifacts(self.artifacts, out_dir) if (not self.no_build): opts = self.makeopts.split(" ") config = "" From 470cd88dfa593835d197a9c952fdf24f6d2261e8 Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 27 Jul 2025 12:11:35 +0200 Subject: [PATCH 05/28] Update init script --- files/initramfs/init | 30 ++++++------------------------ files/initramfs/init.script | 2 +- 2 files changed, 7 insertions(+), 25 deletions(-) diff --git a/files/initramfs/init b/files/initramfs/init index 10f1cce..8eb59de 100644 --- a/files/initramfs/init +++ b/files/initramfs/init @@ -62,53 +62,35 @@ run cd "${CHROOT}" good_msg 'Mounting squashfs filesystem' upperdir="${RW_MNT}/.upper" workdir="${RW_MNT}/.work" -for i in "${RW_MNT}" "${STATIC}" "${OVERLAY}" +for i in "${RW_MNT}" "${STATIC}" "${OVERLAY}" "${upperdir}" "${workdir}" do [ ! -d "${i}" ] && run mkdir -p "${i}" done -#for i in "${upperdir}" "${workdir}" -#do -# [ ! -d "${i}" ] && run mkdir -p "${i}" -#done run mount -t squashfs -o loop,ro "${CDROOT_PATH}/${LOOP}" "${STATIC}" || run_emergency_shell if [ -d ${CDROOT_PATH}/modules ] then - warn_msg "Adding all modules in ${CDROOT_PATH}/modules" + good_msg "Adding all modules in ${CDROOT_PATH}/modules" for module in "${CDROOT_PATH}/modules/"*.lzm; do mod=${module##*/} mod=${mod//-/_} mod=${mod%.*} if [ ! -d "${OVERLAY}/.${mod}" ] then - run mkdir -p "${OVERLAY}/.${mod}" || return + run mkdir -p "${OVERLAY}/.${mod}" || run_emergency_shell fi - run mount -o loop,ro "${module}" "${OVERLAY}/.${mod}" + run mount -o loop,ro "${module}" "${OVERLAY}/.${mod}" || run_emergency_shell mod_path="${mod_path}:${OVERLAY}/.${mod}" # Assign variable with paths to modules mount point - # TODO: Stop using eval - eval ${mod}="${OVERLAY}/.${mod}" - mods="${mods} ${mod}" + mods="${mods} ${OVERLAY}/.${mod}" done fi run mount -t overlay overlay -o lowerdir="${STATIC}${mod_path}",upperdir="${upperdir}",workdir="${workdir}" "${NEW_ROOT}" || run_emergency_shell -for i in "${RW_MNT}" "${STATIC}" "${CDROOT_PATH}" +for i in "${RW_MNT}" "${STATIC}" "${CDROOT_PATH}" ${mods} do [ ! -d "${NEW_ROOT}${i}" ] && run mkdir -p "${NEW_ROOT}${i}" run mount --move "${i}" "${NEW_ROOT}${i}" || run_emergency_shell done -#run mount --move "${CDROOT_PATH}" "${NEW_ROOT}${CDROOT_PATH}" || run_emergency_shell -#run mount --move "${RW_MNT}" "${NEW_ROOT}${RW_MNT}" || run_emergency_shell -#run mount --move "${STATIC}" "${NEW_ROOT}${STATIC}" || run_emergency_shell -if [ -n "${mods}" ] -then - for i in ${mods} - do - [ ! -d "${NEW_ROOT}${OVERLAY}/.${i}" ] && run mkdir -p "${NEW_ROOT}${OVERLAY}/.${i}" - run mount --bind "${OVERLAY}/.${i}" "${NEW_ROOT}/${OVERLAY}/.${i}" - done -fi - #for m in ${MODULES}; do # run insmod "${NEW_ROOT}${m}" #done diff --git a/files/initramfs/init.script b/files/initramfs/init.script index 86212aa..7d7bb32 100644 --- a/files/initramfs/init.script +++ b/files/initramfs/init.script @@ -101,7 +101,7 @@ devicelist() { # iSeries devices DEVICES="${DEVICES} /dev/iseries/vcd*" # builtin mmc/sd card reader devices - DEVICES="${DEVICES} /dev/mmcblk* /dev/mmcblk*/*" + DEVICES="${DEVICES} /dev/mmcblk*p*/*" # fallback scanning, this might scan something twice, but it's better than # failing to boot. [ -e /proc/partitions ] && DEVICES="${DEVICES} $(awk '/([0-9]+[[:space:]]+)/{print "/dev/" $4}' /proc/partitions)" From ac22cd5440eace892e68420b7b8fe7159a58725a Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 27 Jul 2025 12:11:47 +0200 Subject: [PATCH 06/28] Fix remove modules dir issue --- scripts/sources.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/sources.py b/scripts/sources.py index c708f09..cbede6a 100644 --- a/scripts/sources.py +++ b/scripts/sources.py @@ -267,7 +267,7 @@ class Sources: def prepare_artifacts(self, artifacts, out_dir): for art in artifacts: if ("kmods" in art): - shutil.rmtree(f"{out_dir}/kmods") + shutil.rmtree(f"{out_dir}/kmods", ignore_errors=True) def copy_artifacts(self, artifacts, out_dir): for art in artifacts: From cd4e03082c43a38c995a8be023f2d265ccaac14f Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 27 Jul 2025 12:12:11 +0200 Subject: [PATCH 07/28] Add kernel support for panel "btt-pitft" --- patch/kernel/printer_btt_tft_support.patch | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 patch/kernel/printer_btt_tft_support.patch diff --git a/patch/kernel/printer_btt_tft_support.patch b/patch/kernel/printer_btt_tft_support.patch new file mode 100644 index 0000000..9f0951a --- /dev/null +++ b/patch/kernel/printer_btt_tft_support.patch @@ -0,0 +1,51 @@ +diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c +index 9b2f128fd309..ae3b28cbe31f 100644 +--- a/drivers/gpu/drm/panel/panel-simple.c ++++ b/drivers/gpu/drm/panel/panel-simple.c +@@ -5470,6 +5470,36 @@ static const struct panel_desc_dsi osd101t2045_53ts = { + .lanes = 4, + }; + ++static const struct drm_display_mode btt_pitft_mode = { ++ .clock = 26101800 / 1000, ++ .hdisplay = 800, ++ .hsync_start = 800 + 59, ++ .hsync_end = 800 + 59 + 2, ++ .htotal = 800 + 59 + 2 + 52, ++ .vdisplay = 1200, ++ .vsync_start = 480 + 7, ++ .vsync_end = 480 + 7 + 2, ++ .vtotal = 480 + 7 + 2 + 21, ++ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, ++}; ++ ++static const struct panel_desc_dsi btt_pitft = { ++ .desc = { ++ .modes = &btt_pitft_mode, ++ .num_modes = 1, ++ .bpc = 8, ++ .size = { ++ .width = 217, ++ .height = 136, ++ }, ++ .connector_type = DRM_MODE_CONNECTOR_DSI, ++ }, ++ .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | ++ MIPI_DSI_MODE_LPM, ++ .format = MIPI_DSI_FMT_RGB888, ++ .lanes = 1, ++}; ++ + static const struct of_device_id dsi_of_match[] = { + { + .compatible = "auo,b080uan01", +@@ -5492,6 +5522,9 @@ static const struct of_device_id dsi_of_match[] = { + }, { + .compatible = "osddisplays,osd101t2045-53ts", + .data = &osd101t2045_53ts ++ }, { ++ .compatible = "btt-pitft", ++ .data = &btt_pitft + }, { + /* sentinel */ + } From 933a2c3d1cba1eb4af8c1d493889bfb6e520a149 Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 27 Jul 2025 12:12:32 +0200 Subject: [PATCH 08/28] Add no-IRQ mode support for EDT touch. --- .../printer_edt_ft5x06_noIRQ_support.patch | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 patch/kernel/printer_edt_ft5x06_noIRQ_support.patch diff --git a/patch/kernel/printer_edt_ft5x06_noIRQ_support.patch b/patch/kernel/printer_edt_ft5x06_noIRQ_support.patch new file mode 100644 index 0000000..aaecf35 --- /dev/null +++ b/patch/kernel/printer_edt_ft5x06_noIRQ_support.patch @@ -0,0 +1,161 @@ +diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c +index 0d7bf18e2508..535e84de038e 100644 +--- a/drivers/input/touchscreen/edt-ft5x06.c ++++ b/drivers/input/touchscreen/edt-ft5x06.c +@@ -77,6 +77,10 @@ + #define EDT_DEFAULT_NUM_X 1024 + #define EDT_DEFAULT_NUM_Y 1024 + ++#define RESET_DELAY_MS 300 /* reset deassert to I2C */ ++#define FIRST_POLL_DELAY_MS 300 /* in addition to the above */ ++#define POLL_INTERVAL_MS 17 /* 17ms = 60fps */ ++ + #define M06_REG_CMD(factory) ((factory) ? 0xf3 : 0xfc) + #define M06_REG_ADDR(factory, addr) ((factory) ? (addr) & 0x7f : (addr) & 0x3f) + +@@ -135,6 +139,7 @@ struct edt_ft5x06_ts_data { + int offset_y; + int report_rate; + int max_support_points; ++ unsigned int known_ids; + int point_len; + u8 tdata_cmd; + int tdata_len; +@@ -147,6 +152,9 @@ struct edt_ft5x06_ts_data { + enum edt_ver version; + unsigned int crc_errors; + unsigned int header_errors; ++ ++ struct timer_list timer; ++ struct work_struct work_i2c_poll; + }; + + struct edt_i2c_chip_data { +@@ -303,6 +311,10 @@ static irqreturn_t edt_ft5x06_ts_isr(int irq, void *dev_id) + u8 rdbuf[63]; + int i, type, x, y, id; + int error; ++ unsigned int active_ids = 0, known_ids = tsdata->known_ids; ++ long released_ids; ++ int b = 0; ++ unsigned int num_points; + + memset(rdbuf, 0, sizeof(rdbuf)); + error = regmap_bulk_read(tsdata->regmap, tsdata->tdata_cmd, rdbuf, +@@ -313,7 +325,16 @@ static irqreturn_t edt_ft5x06_ts_isr(int irq, void *dev_id) + goto out; + } + +- for (i = 0; i < tsdata->max_support_points; i++) { ++ /* M09/M12 does not send header or CRC */ ++ if (tsdata->version == EDT_M06) { ++ num_points = tsdata->max_support_points; ++ } else { ++ /* Register 2 is TD_STATUS, containing the number of touch ++ * points. ++ */ ++ num_points = min(rdbuf[2] & 0xf, tsdata->max_support_points); ++ } ++ for (i = 0; i < num_points; i++) { + u8 *buf = &rdbuf[i * tsdata->point_len + tsdata->tdata_offset]; + + type = buf[0] >> 6; +@@ -335,11 +356,26 @@ static irqreturn_t edt_ft5x06_ts_isr(int irq, void *dev_id) + + input_mt_slot(tsdata->input, id); + if (input_mt_report_slot_state(tsdata->input, MT_TOOL_FINGER, +- type != TOUCH_EVENT_UP)) ++ type != TOUCH_EVENT_UP)) { + touchscreen_report_pos(tsdata->input, &tsdata->prop, + x, y, true); ++ active_ids |= BIT(id); ++ } else { ++ known_ids &= ~BIT(id); ++ } + } + ++ /* One issue with the device is the TOUCH_UP message is not always ++ * returned. Instead track which ids we know about and report when they ++ * are no longer updated ++ */ ++ released_ids = known_ids & ~active_ids; ++ for_each_set_bit_from(b, &released_ids, tsdata->max_support_points) { ++ input_mt_slot(tsdata->input, b); ++ input_mt_report_slot_inactive(tsdata->input); ++ } ++ tsdata->known_ids = active_ids; ++ + input_mt_report_pointer_emulation(tsdata->input, true); + input_sync(tsdata->input); + +@@ -347,6 +383,22 @@ static irqreturn_t edt_ft5x06_ts_isr(int irq, void *dev_id) + return IRQ_HANDLED; + } + ++static void edt_ft5x06_ts_irq_poll_timer(struct timer_list *t) ++{ ++ struct edt_ft5x06_ts_data *tsdata = from_timer(tsdata, t, timer); ++ ++ schedule_work(&tsdata->work_i2c_poll); ++ mod_timer(&tsdata->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS)); ++} ++ ++static void edt_ft5x06_ts_work_i2c_poll(struct work_struct *work) ++{ ++ struct edt_ft5x06_ts_data *tsdata = container_of(work, ++ struct edt_ft5x06_ts_data, work_i2c_poll); ++ ++ edt_ft5x06_ts_isr(0, tsdata); ++} ++ + struct edt_ft5x06_attribute { + struct device_attribute dattr; + size_t field_offset; +@@ -1332,17 +1384,26 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client) + return error; + } + +- irq_flags = irq_get_trigger_type(client->irq); +- if (irq_flags == IRQF_TRIGGER_NONE) +- irq_flags = IRQF_TRIGGER_FALLING; +- irq_flags |= IRQF_ONESHOT; ++ if (client->irq) { ++ irq_flags = irq_get_trigger_type(client->irq); ++ if (irq_flags == IRQF_TRIGGER_NONE) ++ irq_flags = IRQF_TRIGGER_FALLING; ++ irq_flags |= IRQF_ONESHOT; + +- error = devm_request_threaded_irq(&client->dev, client->irq, +- NULL, edt_ft5x06_ts_isr, irq_flags, +- client->name, tsdata); +- if (error) { +- dev_err(&client->dev, "Unable to request touchscreen IRQ.\n"); +- return error; ++ error = devm_request_threaded_irq(&client->dev, client->irq, ++ NULL, edt_ft5x06_ts_isr, irq_flags, ++ client->name, tsdata); ++ if (error) { ++ dev_err(&client->dev, "Unable to request touchscreen IRQ.\n"); ++ return error; ++ } ++ } else { ++ INIT_WORK(&tsdata->work_i2c_poll, ++ edt_ft5x06_ts_work_i2c_poll); ++ timer_setup(&tsdata->timer, edt_ft5x06_ts_irq_poll_timer, 0); ++ tsdata->timer.expires = ++ jiffies + msecs_to_jiffies(FIRST_POLL_DELAY_MS); ++ add_timer(&tsdata->timer); + } + + error = input_register_device(input); +@@ -1364,6 +1425,10 @@ static void edt_ft5x06_ts_remove(struct i2c_client *client) + { + struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client); + ++ if (!client->irq) { ++ del_timer(&tsdata->timer); ++ cancel_work_sync(&tsdata->work_i2c_poll); ++ } + edt_ft5x06_ts_teardown_debugfs(tsdata); + } + From c7247c4cb13bc2054d73e4e2cf14a687b15c17f8 Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 27 Jul 2025 12:13:02 +0200 Subject: [PATCH 09/28] Update kernel config --- cfg/kernel_v6.14-rc7 | 115 +++++++++++++++++++- patch/kernel/printer_defconfig_1_plat.patch | 5 +- 2 files changed, 116 insertions(+), 4 deletions(-) diff --git a/cfg/kernel_v6.14-rc7 b/cfg/kernel_v6.14-rc7 index dcad18d..9078a78 100644 --- a/cfg/kernel_v6.14-rc7 +++ b/cfg/kernel_v6.14-rc7 @@ -3043,6 +3043,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_PV88090 is not set # CONFIG_REGULATOR_PWM is not set # CONFIG_REGULATOR_RAA215300 is not set +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT4803 is not set @@ -3538,9 +3539,11 @@ CONFIG_DRM_CLIENT_DEFAULT="fbdev" # end of Supported DRM clients # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +CONFIG_DRM_DISPLAY_DP_AUX_BUS=m CONFIG_DRM_DISPLAY_HELPER=y # CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set # CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set +CONFIG_DRM_DISPLAY_DP_HELPER=y CONFIG_DRM_DISPLAY_HDMI_HELPER=y CONFIG_DRM_GEM_DMA_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=y @@ -3577,7 +3580,7 @@ CONFIG_ROCKCHIP_VOP2=y CONFIG_ROCKCHIP_DW_HDMI=y # CONFIG_ROCKCHIP_DW_HDMI_QP is not set CONFIG_ROCKCHIP_DW_MIPI_DSI=y -# CONFIG_ROCKCHIP_DW_MIPI_DSI2 is not set +CONFIG_ROCKCHIP_DW_MIPI_DSI2=y # CONFIG_ROCKCHIP_INNO_HDMI is not set # CONFIG_ROCKCHIP_LVDS is not set # CONFIG_ROCKCHIP_RGB is not set @@ -3599,21 +3602,107 @@ CONFIG_DRM_PANEL=y # # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set +# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +CONFIG_DRM_PANEL_DSI_CM=y +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set +# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_JDI_R63452 is not set +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set -# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set +# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set +# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +CONFIG_DRM_PANEL_EDP=m +CONFIG_DRM_PANEL_SIMPLE=m +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -3664,6 +3753,7 @@ CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_DW_HDMI=y CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_DW_MIPI_DSI=y +CONFIG_DRM_DW_MIPI_DSI2=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set @@ -3734,6 +3824,7 @@ CONFIG_FB=y # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set +# CONFIG_FB_SSD1307 is not set # CONFIG_FB_SM712 is not set CONFIG_FB_CORE=y CONFIG_FB_NOTIFY=y @@ -3757,7 +3848,24 @@ CONFIG_FB_MODE_HELPERS=y # Backlight & LCD device support # # CONFIG_LCD_CLASS_DEVICE is not set -# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set +# CONFIG_BACKLIGHT_KTZ8866 is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_QCOM_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3509 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_MP3309C is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_LED is not set # end of Backlight & LCD device support CONFIG_VIDEOMODE_HELPERS=y @@ -4500,6 +4608,7 @@ CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_VIDEO_SUN6I_ISP is not set # CONFIG_STAGING_MEDIA_DEPRECATED is not set +# CONFIG_FB_TFT is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_VME_BUS is not set # CONFIG_GPIB is not set diff --git a/patch/kernel/printer_defconfig_1_plat.patch b/patch/kernel/printer_defconfig_1_plat.patch index 839d409..a988326 100644 --- a/patch/kernel/printer_defconfig_1_plat.patch +++ b/patch/kernel/printer_defconfig_1_plat.patch @@ -3,7 +3,7 @@ new file mode 100644 index 000000000000..51de9e95b7d2 --- a/arch/arm64/configs/printer_defconfig +++ b/arch/arm64/configs/printer_defconfig -@@ -0,4 +200,204 @@ +@@ -0,4 +203,207 @@ CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_SPI_NOR=y @@ -208,3 +208,6 @@ index 000000000000..51de9e95b7d2 +#CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +#CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_BACKLIGHT_CLASS_DEVICE=y ++CONFIG_BACKLIGHT_PWM=y ++CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTIMY=y From be1bd381c27fcfa31d2bbfada52ae476cc635406 Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 27 Jul 2025 12:13:14 +0200 Subject: [PATCH 10/28] Add OTP definition --- tmp/rk356x-base.dtsi | 105 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/tmp/rk356x-base.dtsi b/tmp/rk356x-base.dtsi index a3b0f2c..ab2b701 100644 --- a/tmp/rk356x-base.dtsi +++ b/tmp/rk356x-base.dtsi @@ -1074,6 +1074,111 @@ status = "disabled"; }; + otp: otp@fe38c000 { + compatible = "rockchip,rk3568-otp"; + reg = <0x00 0xfe38c000 0x00 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS_USR>, + <&cru CLK_OTPC_NS_SBPI>, + <&cru PCLK_OTPC_NS>, + <&cru PCLK_OTPPHY>; + clock-names = "usr", "sbpi", "apb", "phy"; + resets = <&cru SRST_OTPPHY>; + reset-names = "otp_phy"; + + cpu_code: cpu-code@2 { + reg = <0x02 0x02>; + }; + + specification_serial_number: specification-serial-number@7 { + reg = <0x07 0x01>; + bits = <0x00 0x05>; + }; + + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x01>; + bits = <0x03 0x03>; + }; + + mbist_vmin: mbist-vmin@9 { + reg = <0x09 0x01>; + bits = <0x00 0x04>; + }; + + otp_id: id@a { + reg = <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x01>; + }; + + log_leakage: log-leakage@1b { + reg = <0x1b 0x01>; + }; + + npu_leakage: npu-leakage@1c { + reg = <0x1c 0x01>; + }; + + gpu_leakage: gpu-leakage@1d { + reg = <0x1d 0x01>; + }; + + core_pvtm: core-pvtm@2a { + reg = <0x2a 0x02>; + }; + + cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e { + reg = <0x2e 0x01>; + }; + + cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f { + reg = <0x2f 0x01>; + bits = <0x00 0x04>; + }; + + gpu_tsadc_trim_l: npu-tsadc-trim-l@30 { + reg = <0x30 0x01>; + }; + + gpu_tsadc_trim_h: npu-tsadc-trim-h@31 { + reg = <0x31 0x01>; + bits = <0x00 0x04>; + }; + + tsadc_trim_base_frac: tsadc-trim-base-frac@31 { + reg = <0x31 0x01>; + bits = <0x04 0x04>; + }; + + tsadc_trim_base: tsadc-trim-base@32 { + reg = <0x32 0x01>; + }; + + cpu_opp_info: cpu-opp-info@36 { + reg = <0x36 0x06>; + }; + + gpu_opp_info: gpu-opp-info@3c { + reg = <0x3c 0x06>; + }; + + npu_opp_info: npu-opp-info@42 { + reg = <0x42 0x06>; + }; + + dmc_opp_info: dmc-opp-info@48 { + reg = <0x48 0x06>; + }; + + remark_spec_serial_number: remark-spec-serial-number@56 { + reg = <0x56 1>; + bits = <0 5>; + }; + }; + crypto: crypto@fe380000 { compatible = "rockchip,rk3568-crypto"; reg = <0x0 0xfe380000 0x0 0x2000>; From 2843aaf1cde8c3ec3e1e79f1b78b6610f62c775e Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 27 Jul 2025 12:13:39 +0200 Subject: [PATCH 11/28] Add optional HDMI/DSI output for BTT-Pi2 --- tmp/rk3566-bigtreetech-cb2.dtsi | 119 ++++++++++++++++++++++++-------- tmp/rk3566-bigtreetech-pi2.dts | 52 ++++++++++++++ 2 files changed, 143 insertions(+), 28 deletions(-) diff --git a/tmp/rk3566-bigtreetech-cb2.dtsi b/tmp/rk3566-bigtreetech-cb2.dtsi index bcfa60b..0fed7da 100644 --- a/tmp/rk3566-bigtreetech-cb2.dtsi +++ b/tmp/rk3566-bigtreetech-cb2.dtsi @@ -251,6 +251,58 @@ cpu-supply = <&vdd_cpu>; }; +&dsi_dphy1 { + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_panel: panel@0 { + compatible = "btt-pitft"; + reg = <0x0>; + status = "disabled"; + vddc-supply = <&bl_dsi>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + + dsi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi1>; + }; + }; + + dsi1_out: port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; @@ -265,6 +317,8 @@ &gmac1m0_rgmii_clk &gmac1m0_clkinout &gmac1m0_rgmii_bus>; + tx_delay = <0x19>; + rx_delay = <0x05>; status = "okay"; }; @@ -286,7 +340,7 @@ &hdmi { avdd-0v9-supply = <&vdda0v9_image>; avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; + status = "disabled"; }; &hdmi_in { @@ -301,10 +355,6 @@ }; }; -&hdmi_sound { - status = "okay"; -}; - &i2c0 { status = "okay"; @@ -559,25 +609,36 @@ }; &i2c2 { + status = "okay"; + pinctrl-names = "default"; + clock-frequency = <100000>; pinctrl-0 = <&i2c2m1_xfer>; -}; + avdd-1v8-supply = <&vcca1v8_image>; + avdd-0v9-supply = <&vdda0v9_image>; + power-domains = <&power RK3568_PD_VI>; + #address-cells = <1>; + #size-cells = <0>; + #size-cells = <0>; -&i2c3 { - status = "okay"; - - tft_tp: touchscreen@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - status = "okay"; - ti,x-plate-ohms = <660>; - ti,rt-thr = <3000>; - ti,fuzzx = <32>; - ti,fuzzy = <16>; + bl_dsi: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + status = "disabled"; }; -}; -&i2s0_8ch { - status = "okay"; + tp_dsi: touchscreen@38 { + compatible = "edt,edt-ft5306"; + reg = <0x38>; + status = "disabled"; + + vcc-supply = <&vcc3v3_sys>; + iovcc-supply = <&vcc_3v3>; + + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; }; &i2s1_8ch { @@ -615,7 +676,6 @@ pinctrl-0 = <&pcie_reset_h>; reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; }; &pinctrl { @@ -794,10 +854,6 @@ status = "okay"; }; -&tsadc { - status = "okay"; -}; - &uart1 { dma-names = "tx","rx"; pinctrl-names = "default"; @@ -890,11 +946,11 @@ &vop { assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; + vop-supply = <&vdd_logic>; }; -&vop_mmu { - status = "okay"; +&scmi_clk { + rockchip,clk-init = <1104000000>; }; &vp0 { @@ -903,3 +959,10 @@ remote-endpoint = <&hdmi_in_vp0>; }; }; + +&vp1 { + vp1_out_dsi1: endpoint@ROCKCHIP_VOP2_EP_MIPI1 { + reg = ; + remote-endpoint = <&dsi1_in_vp1>; + }; +}; diff --git a/tmp/rk3566-bigtreetech-pi2.dts b/tmp/rk3566-bigtreetech-pi2.dts index 7cd444c..150da85 100644 --- a/tmp/rk3566-bigtreetech-pi2.dts +++ b/tmp/rk3566-bigtreetech-pi2.dts @@ -8,3 +8,55 @@ model = "BigTreeTech Pi 2"; compatible = "bigtreetech,pi2", "rockchip,rk3566"; }; + +/* HDMI output */ +/*&vop { + status = "okay"; +}; +&vop_mmu { + status = "okay"; +}; +&display_subsystem { + status = "okay"; +}; +&hdmi_sound { + status = "okay"; +}; +&i2s0_8ch { + status = "okay"; +}; +&hdmi { + status = "okay"; +}; +&hdmi_in_vp0 { + status = "okay"; +};*/ + +/* DSI1 output */ +&vop { + status = "okay"; +}; +&vop_mmu { + status = "okay"; +}; +&display_subsystem { + status = "okay"; +}; +&dsi1 { + status = "okay"; +}; +&dsi1_panel { + status = "okay"; +}; +&dsi1_in_vp1 { + status = "okay"; +}; +&dsi_dphy1 { + status = "okay"; +}; +&tp_dsi { + status = "okay"; +}; +&bl_dsi { + status = "okay"; +}; From 48e64951f9d5bb39b674c44ac8a5eec20f1f9053 Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 27 Jul 2025 21:52:53 +0200 Subject: [PATCH 12/28] Fix EIX initial --- config/os_aarch64.json | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/config/os_aarch64.json b/config/os_aarch64.json index 4241bf3..3d94e2d 100644 --- a/config/os_aarch64.json +++ b/config/os_aarch64.json @@ -191,8 +191,17 @@ ], "oneshot": false }, + { + "file": "/etc/eixrc/00-eixrc", + "append": false, + "lines": [ + "PORTDIR_CACHE_METHOD='sqlite'", + "OVERLAY_CACHE_METHOD='sqlite'" + ] + }, { "chroot": "crossdev -s4 arm-none-eabi" }, { "chroot": "eselect news read" }, + { "chroot": "eix-update" }, { "soft_clean": "default" } ] }, From 214876120141f8db9885315b3101e40d29fb0bc9 Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 27 Jul 2025 21:53:46 +0200 Subject: [PATCH 13/28] Fix CPU temperature sensor. Some optimizations. --- cfg/kernel_v6.14-rc7 | 43 ++++++------------- patch/kernel/printer_defconfig_0_common.patch | 16 ++++--- patch/kernel/printer_defconfig_1_plat.patch | 9 ++-- tmp/rk3566-bigtreetech-cb2.dtsi | 4 ++ 4 files changed, 31 insertions(+), 41 deletions(-) diff --git a/cfg/kernel_v6.14-rc7 b/cfg/kernel_v6.14-rc7 index 9078a78..b164b12 100644 --- a/cfg/kernel_v6.14-rc7 +++ b/cfg/kernel_v6.14-rc7 @@ -1462,7 +1462,7 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_PHANTOM is not set -# CONFIG_RPMB is not set +CONFIG_RPMB=y # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1492,9 +1492,9 @@ CONFIG_BLK_DEV_NVME=y # EEPROM support # CONFIG_EEPROM_AT24=y -CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_AT25 is not set # CONFIG_EEPROM_MAX6875 is not set -CONFIG_EEPROM_93CX6=y +# CONFIG_EEPROM_93CX6 is not set # CONFIG_EEPROM_93XX46 is not set # CONFIG_EEPROM_IDT_89HPESX is not set # CONFIG_EEPROM_EE1004 is not set @@ -2151,9 +2151,8 @@ CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y -CONFIG_SERIAL_8250_PCILIB=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_EXAR=y +# CONFIG_SERIAL_8250_PCI is not set +# CONFIG_SERIAL_8250_EXAR is not set CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y @@ -2166,7 +2165,7 @@ CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_RT288X is not set -CONFIG_SERIAL_8250_PERICOM=y +# CONFIG_SERIAL_8250_PERICOM is not set CONFIG_SERIAL_OF_PLATFORM=y # @@ -2463,7 +2462,6 @@ CONFIG_GPIO_CDEV_V1=y # CONFIG_GPIO_ALTERA is not set # CONFIG_GPIO_CADENCE is not set # CONFIG_GPIO_DWAPB is not set -# CONFIG_GPIO_EXAR is not set # CONFIG_GPIO_FTGPIO010 is not set # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_GRGPIO is not set @@ -3539,11 +3537,9 @@ CONFIG_DRM_CLIENT_DEFAULT="fbdev" # end of Supported DRM clients # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set -CONFIG_DRM_DISPLAY_DP_AUX_BUS=m CONFIG_DRM_DISPLAY_HELPER=y # CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set # CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set -CONFIG_DRM_DISPLAY_DP_HELPER=y CONFIG_DRM_DISPLAY_HDMI_HELPER=y CONFIG_DRM_GEM_DMA_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=y @@ -3580,7 +3576,7 @@ CONFIG_ROCKCHIP_VOP2=y CONFIG_ROCKCHIP_DW_HDMI=y # CONFIG_ROCKCHIP_DW_HDMI_QP is not set CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_DW_MIPI_DSI2=y +# CONFIG_ROCKCHIP_DW_MIPI_DSI2 is not set # CONFIG_ROCKCHIP_INNO_HDMI is not set # CONFIG_ROCKCHIP_LVDS is not set # CONFIG_ROCKCHIP_RGB is not set @@ -3613,7 +3609,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set -CONFIG_DRM_PANEL_DSI_CM=y +CONFIG_DRM_PANEL_DSI_CM=m # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set @@ -3690,7 +3686,7 @@ CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m # CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set # CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set -CONFIG_DRM_PANEL_EDP=m +# CONFIG_DRM_PANEL_EDP is not set CONFIG_DRM_PANEL_SIMPLE=m # CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set @@ -3753,7 +3749,6 @@ CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_DW_HDMI=y CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_DW_MIPI_DSI=y -CONFIG_DRM_DW_MIPI_DSI2=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set @@ -4112,18 +4107,7 @@ CONFIG_USB_STORAGE=y # USB dual-mode controller drivers # # CONFIG_USB_CDNS_SUPPORT is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_HOST=y - -# -# Platform Glue Layer -# -CONFIG_USB_MUSB_SUNXI=y - -# -# MUSB DMA mode -# -# CONFIG_MUSB_PIO_ONLY is not set +# CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y CONFIG_USB_DWC3_HOST=y @@ -6261,10 +6245,7 @@ CONFIG_FRAME_POINTER=y # # Generic Kernel Debugging Instruments # -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +# CONFIG_MAGIC_SYSRQ is not set CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set @@ -6349,7 +6330,7 @@ CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y # # Scheduler Debugging # -CONFIG_SCHED_DEBUG=y +# CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set # end of Scheduler Debugging diff --git a/patch/kernel/printer_defconfig_0_common.patch b/patch/kernel/printer_defconfig_0_common.patch index 81579ee..ab7134a 100644 --- a/patch/kernel/printer_defconfig_0_common.patch +++ b/patch/kernel/printer_defconfig_0_common.patch @@ -3,7 +3,7 @@ new file mode 100644 index 000000000000..51de9e95b7d2 --- /dev/null +++ b/arch/arm64/configs/printer_defconfig -@@ -0,0 +1,507 @@ +@@ -0,0 +1,513 @@ +CONFIG_DEFAULT_HOSTNAME="Printer" +CONFIG_LOCALVERSION="-arm64" +CONFIG_LOCALVERSION_AUTO=n @@ -43,6 +43,7 @@ index 000000000000..51de9e95b7d2 +CONFIG_PWM=y +CONFIG_ETHERNET=y +CONFIG_MMC=y ++CONFIG_RPMB=y +CONFIG_RESET_CONTROLLER=y +CONFIG_ARM64=y +CONFIG_WATCHDOG=y @@ -123,10 +124,8 @@ index 000000000000..51de9e95b7d2 +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_DEBUG_MISC=n -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -+CONFIG_MAGIC_SYSRQ_SERIAL=y -+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" ++CONFIG_MAGIC_SYSRQ=n ++CONFIG_SCHED_DEBUG=n + +#minimize +CONFIG_NR_CPUS=8 @@ -290,6 +289,10 @@ index 000000000000..51de9e95b7d2 +CONFIG_ARM64_ERRATUM_2051678=n +CONFIG_ARM64_ERRATUM_2077057=n +CONFIG_ARM64_ERRATUM_2658417=n ++CONFIG_SERIAL_8250_PCILIB=n ++CONFIG_SERIAL_8250_PCI=n ++CONFIG_SERIAL_8250_EXAR=n ++CONFIG_SERIAL_8250_PERICOM=n + +#system +CONFIG_VALIDATE_FS_PARSER=y @@ -489,6 +492,9 @@ index 000000000000..51de9e95b7d2 +CONFIG_DRM_DW_HDMI_I2S_AUDIO=y +CONFIG_DRM_DW_HDMI_CEC=y +CONFIG_DRM_DW_MIPI_DSI=y ++CONFIG_DRM_PANEL_SIMPLE=m ++CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m ++CONFIG_DRM_PANEL_DSI_CM=m +#network +CONFIG_PACKET=y +CONFIG_INET=y diff --git a/patch/kernel/printer_defconfig_1_plat.patch b/patch/kernel/printer_defconfig_1_plat.patch index a988326..40fbcdc 100644 --- a/patch/kernel/printer_defconfig_1_plat.patch +++ b/patch/kernel/printer_defconfig_1_plat.patch @@ -3,7 +3,7 @@ new file mode 100644 index 000000000000..51de9e95b7d2 --- a/arch/arm64/configs/printer_defconfig +++ b/arch/arm64/configs/printer_defconfig -@@ -0,4 +203,207 @@ +@@ -0,4 +202,206 @@ CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_SPI_NOR=y @@ -26,7 +26,6 @@ index 000000000000..51de9e95b7d2 +CONFIG_NET_VENDOR_ALLWINNER=y +CONFIG_AC200_PHY=y +CONFIG_AC200_PHY_SUNXI=y -+CONFIG_USB_MUSB_HDRC=y +CONFIG_PHY_SUN4I_USB=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y @@ -52,7 +51,6 @@ index 000000000000..51de9e95b7d2 +CONFIG_SUN50I_IOMMU=y +##CONFIG_IR_SUNXI=y +CONFIG_KEYBOARD_SUN4I_LRADC=y -+CONFIG_USB_MUSB_SUNXI=y +CONFIG_SUNXI_NMI_INTC=y +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y +CONFIG_PINCTRL_SUN50I_H616=y @@ -170,7 +168,8 @@ index 000000000000..51de9e95b7d2 +CONFIG_BLK_DEV_NVME=y +#EEPROM +CONFIG_EEPROM_AT24=y -+CONFIG_EEPROM_AT25=y ++CONFIG_EEPROM_AT25=n ++CONFIG_EEPROM_93CX6=n +#FB +CONFIG_DRM_SIMPLEDRM=y +CONFIG_FB=y @@ -210,4 +209,4 @@ index 000000000000..51de9e95b7d2 +#CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y -+CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTIMY=y ++CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y diff --git a/tmp/rk3566-bigtreetech-cb2.dtsi b/tmp/rk3566-bigtreetech-cb2.dtsi index 0fed7da..85fb75d 100644 --- a/tmp/rk3566-bigtreetech-cb2.dtsi +++ b/tmp/rk3566-bigtreetech-cb2.dtsi @@ -251,6 +251,10 @@ cpu-supply = <&vdd_cpu>; }; +&tsadc { + status = "okay"; +}; + &dsi_dphy1 { status = "disabled"; }; From 1383d18ecceaf3c469993a2ae5424c0f5d2f2436 Mon Sep 17 00:00:00 2001 From: andreili Date: Sun, 17 Aug 2025 18:28:11 +0200 Subject: [PATCH 14/28] Add one wire support. --- cfg/kernel_v6.14-rc7 | 43 +++++++++++++++++-- patch/kernel/printer_defconfig_0_common.patch | 6 ++- tmp/rk3566-bigtreetech-cb2.dtsi | 16 +++++++ 3 files changed, 61 insertions(+), 4 deletions(-) diff --git a/cfg/kernel_v6.14-rc7 b/cfg/kernel_v6.14-rc7 index b164b12..eacc9c0 100644 --- a/cfg/kernel_v6.14-rc7 +++ b/cfg/kernel_v6.14-rc7 @@ -11,8 +11,8 @@ CONFIG_AS_VERSION=24400 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=24400 CONFIG_LLD_VERSION=0 -CONFIG_RUSTC_VERSION=108800 -CONFIG_RUSTC_LLVM_VERSION=200105 +CONFIG_RUSTC_VERSION=108900 +CONFIG_RUSTC_LLVM_VERSION=200107 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y @@ -2540,7 +2540,42 @@ CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_VIRTUSER is not set # end of GPIO Debugging utilities -# CONFIG_W1 is not set +CONFIG_W1=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_AMD_AXI is not set +# CONFIG_W1_MASTER_MATROX is not set +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_DS2482 is not set +CONFIG_W1_MASTER_GPIO=y +# CONFIG_W1_MASTER_SGI is not set +# CONFIG_W1_MASTER_UART is not set +# end of 1-wire Bus Masters + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=y +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2405 is not set +# CONFIG_W1_SLAVE_DS2408 is not set +# CONFIG_W1_SLAVE_DS2413 is not set +# CONFIG_W1_SLAVE_DS2406 is not set +# CONFIG_W1_SLAVE_DS2423 is not set +# CONFIG_W1_SLAVE_DS2805 is not set +# CONFIG_W1_SLAVE_DS2430 is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2438 is not set +# CONFIG_W1_SLAVE_DS250X is not set +# CONFIG_W1_SLAVE_DS2780 is not set +# CONFIG_W1_SLAVE_DS2781 is not set +# CONFIG_W1_SLAVE_DS28E04 is not set +# CONFIG_W1_SLAVE_DS28E17 is not set +# end of 1-wire Slaves + CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_GPIO is not set # CONFIG_POWER_RESET_GPIO_RESTART is not set @@ -2561,6 +2596,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set # CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2760 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set @@ -2573,6 +2609,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set # CONFIG_BATTERY_MAX1720X is not set +# CONFIG_BATTERY_MAX1721X is not set # CONFIG_CHARGER_ISP1704 is not set # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_LP8727 is not set diff --git a/patch/kernel/printer_defconfig_0_common.patch b/patch/kernel/printer_defconfig_0_common.patch index ab7134a..e3a9560 100644 --- a/patch/kernel/printer_defconfig_0_common.patch +++ b/patch/kernel/printer_defconfig_0_common.patch @@ -3,7 +3,7 @@ new file mode 100644 index 000000000000..51de9e95b7d2 --- /dev/null +++ b/arch/arm64/configs/printer_defconfig -@@ -0,0 +1,513 @@ +@@ -0,0 +1,517 @@ +CONFIG_DEFAULT_HOSTNAME="Printer" +CONFIG_LOCALVERSION="-arm64" +CONFIG_LOCALVERSION_AUTO=n @@ -454,6 +454,10 @@ index 000000000000..51de9e95b7d2 +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y +CONFIG_HW_RANDOM=y ++#sensors ++CONFIG_W1=y ++CONFIG_W1_MASTER_GPIO=y ++CONFIG_W1_SLAVE_THERM=y +#systemd +CONFIG_BPF_SYSCALL=y +CONFIG_CGROUP_BPF=y diff --git a/tmp/rk3566-bigtreetech-cb2.dtsi b/tmp/rk3566-bigtreetech-cb2.dtsi index 85fb75d..61c3f1f 100644 --- a/tmp/rk3566-bigtreetech-cb2.dtsi +++ b/tmp/rk3566-bigtreetech-cb2.dtsi @@ -225,6 +225,22 @@ regulator-name = "vcc_sd"; vin-supply = <&vcc3v3_sys>; }; + + onewire: onewire { + compatible = "w1-gpio"; + gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_w1>; + status = "okay"; + }; +}; + +&pinctrl { + gpio-w1 { + gpio_w1:gpio-w1 { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &combphy1 { From ee2dc421bc2452fee7888a7a17bfb7acf1f90213 Mon Sep 17 00:00:00 2001 From: andreili Date: Mon, 18 Aug 2025 22:11:19 +0200 Subject: [PATCH 15/28] Installation fixes. --- config/board/btt_pi2.json | 13 ++++++------- scripts/os.py | 10 ++++++---- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/config/board/btt_pi2.json b/config/board/btt_pi2.json index fa5c553..683441a 100644 --- a/config/board/btt_pi2.json +++ b/config/board/btt_pi2.json @@ -49,6 +49,10 @@ "store_type": "dd", "block_size": "512b", "img_offset": 16384 + }, + { + "file": "u-boot-rockchip-spi.bin", + "store_type": "temp" } ], "target": [ "" ], @@ -71,11 +75,6 @@ "file": "arch/arm64/boot/dts/%{DTB_FILE}%", "store_type": "boot", "subdir": "dtb/rockchip" - }, - { - "file": "", - "store_type": "boot", - "kmods": true } ], "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods/usr" @@ -90,12 +89,12 @@ [ { "name": "boot", - "size": "1g", + "size": "1G", "first_sector": "32768" }, { "name": "rw", - "size": "2g" + "size": "2G" } ] } diff --git a/scripts/os.py b/scripts/os.py index 931482a..f67abd3 100644 --- a/scripts/os.py +++ b/scripts/os.py @@ -155,6 +155,8 @@ class OS: else: args.insert(0, "sudo") err_n = args[1] + else: + err_n = args p = subprocess.Popen(args, cwd=cwd, env=env, stdout=stdout, stderr=stdout, shell=shell) p.wait() if (p.returncode != 0): @@ -270,6 +272,7 @@ class OS: # remove temp directory self.__tmp_clean(temp_dir) self.__extract_tar(arch_path, temp_dir) + self.__sudo(f"rm {temp_dir}/usr/bin/qemu-{self.arch}") sqh_fn = f"{ROOT_DIR}/out/root_{date}.sqh" self.__make_sqh(temp_dir, sqh_fn) os.symlink(sqh_fn, f"{ROOT_DIR}/out/root.sqh.tmp") @@ -374,9 +377,8 @@ class OS: if (part_size > (90 * 1024 * 1024)) and (i == idx): # required partition #print(f"\tIdx:{i} Size:{part_size}") - self.__sudo(["losetup", "-o", str(offset), "--sizelimit", - str(part_size), "/dev/loop0", img_or_blk], - cwd=ROOT_DIR)#, stdout=subprocess.DEVNULL) + self.__sudo(f"losetup -o {offset} --sizelimit {part_size} /dev/loop0 {img_or_blk}", + cwd=ROOT_DIR, shell=True)#, stdout=subprocess.DEVNULL) return True i += 1 offset += part_size @@ -425,7 +427,7 @@ class OS: self.__copy_file(f"{self.board.out_sh}/uInitrd", f"{out_dir}/") Logger.install(f"\tCopy root.sqh") self.__sudo(["cp", "-H", f"{self.board.out_sh}/root.sqh", f"{out_dir}/"]) - self.__sudo(["cp", "-H", f"{self.board.out_sh}/modules", f"{out_dir}/"]) + self.__sudo(["cp", "-Hr", f"{self.board.out_sh}/modules", f"{out_dir}/"]) def __install_rw(self, out_dir): self.__sudo(["touch", f"{out_dir}/rw_part"], stdout=subprocess.DEVNULL) From f5089c22693d879703db194b2e81807416e8b0e8 Mon Sep 17 00:00:00 2001 From: andreili Date: Tue, 19 Aug 2025 15:29:11 +0200 Subject: [PATCH 16/28] Move 1w ti board file. --- tmp/rk3566-bigtreetech-cb2.dtsi | 16 ---------------- tmp/rk3566-bigtreetech-pi2.dts | 28 ++++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 16 deletions(-) diff --git a/tmp/rk3566-bigtreetech-cb2.dtsi b/tmp/rk3566-bigtreetech-cb2.dtsi index 61c3f1f..85fb75d 100644 --- a/tmp/rk3566-bigtreetech-cb2.dtsi +++ b/tmp/rk3566-bigtreetech-cb2.dtsi @@ -225,22 +225,6 @@ regulator-name = "vcc_sd"; vin-supply = <&vcc3v3_sys>; }; - - onewire: onewire { - compatible = "w1-gpio"; - gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_w1>; - status = "okay"; - }; -}; - -&pinctrl { - gpio-w1 { - gpio_w1:gpio-w1 { - rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; }; &combphy1 { diff --git a/tmp/rk3566-bigtreetech-pi2.dts b/tmp/rk3566-bigtreetech-pi2.dts index 150da85..07af961 100644 --- a/tmp/rk3566-bigtreetech-pi2.dts +++ b/tmp/rk3566-bigtreetech-pi2.dts @@ -7,6 +7,22 @@ / { model = "BigTreeTech Pi 2"; compatible = "bigtreetech,pi2", "rockchip,rk3566"; + + onewire: onewire { + compatible = "w1-gpio"; + gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_w1>; + status = "disabled"; + }; +}; + +&pinctrl { + gpio-w1 { + gpio_w1:gpio-w1 { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; /* HDMI output */ @@ -60,3 +76,15 @@ &bl_dsi { status = "okay"; }; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; From 66365d91a8fdb5dd72784cd2c60a92377bb6500a Mon Sep 17 00:00:00 2001 From: andreili Date: Tue, 19 Aug 2025 15:29:25 +0200 Subject: [PATCH 17/28] Fix user create sequence --- config/os_aarch64.json | 1 + 1 file changed, 1 insertion(+) diff --git a/config/os_aarch64.json b/config/os_aarch64.json index 3d94e2d..58eb94c 100644 --- a/config/os_aarch64.json +++ b/config/os_aarch64.json @@ -259,6 +259,7 @@ { "copy": [ "%{ROOT_DIR}%/files/firmware/usr", "."] }, { "sudo": "chmod u+s ./usr/bin/Xorg" }, { "sudo": "ln -sf /usr/share/zoneinfo/%{TIME_ZONE}% ./etc/localtime" }, + { "chroot": "groupadd -g %{USER_ID}% %{USER_LOGIN}%" }, { "chroot": "useradd -m -G wheel,video,audio,disk,usb -g %{USER_ID}% -u %{USER_ID}% %{USER_LOGIN}% --password %{USER_LOGIN}%" }, { "chroot": "echo '%{USER_LOGIN}%:%{USER_LOGIN}%' | chpasswd" }, { "chroot": "echo 'root:root' | chpasswd" }, From 94ed8d5f0c47ddf52d7642ee8c68d8fae415ecb4 Mon Sep 17 00:00:00 2001 From: andreili Date: Tue, 19 Aug 2025 15:29:46 +0200 Subject: [PATCH 18/28] Fix cleanup --- scripts/os.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/os.py b/scripts/os.py index f67abd3..ebbec74 100644 --- a/scripts/os.py +++ b/scripts/os.py @@ -272,7 +272,7 @@ class OS: # remove temp directory self.__tmp_clean(temp_dir) self.__extract_tar(arch_path, temp_dir) - self.__sudo(f"rm {temp_dir}/usr/bin/qemu-{self.arch}") + self.__sudo(f"rm {temp_dir}/usr/bin/qemu-{self.arch}", shell=True) sqh_fn = f"{ROOT_DIR}/out/root_{date}.sqh" self.__make_sqh(temp_dir, sqh_fn) os.symlink(sqh_fn, f"{ROOT_DIR}/out/root.sqh.tmp") From b2f118ebf21c414cb0f89480461402a87ee8d845 Mon Sep 17 00:00:00 2001 From: andreili Date: Tue, 19 Aug 2025 21:29:05 +0200 Subject: [PATCH 19/28] Fix initial script. --- files/initramfs/init | 3 +++ files/initramfs/init.script | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/files/initramfs/init b/files/initramfs/init index 8eb59de..f005b48 100644 --- a/files/initramfs/init +++ b/files/initramfs/init @@ -3,6 +3,9 @@ . /etc/init.def . /etc/init.script +CONSOLE="/dev/$(get_active_console)" +exec 0<>${CONSOLE} 1<>${CONSOLE} 2<>${CONSOLE} + run mount -t sysfs sysfs /sys -o noexec,nosuid,nodev >/dev/null run mount -t devtmpfs -o exec,nosuid,mode=0755,size=10M udev /dev run mkdir -m 0755 /dev/pts diff --git a/files/initramfs/init.script b/files/initramfs/init.script index 7d7bb32..5f23ac9 100644 --- a/files/initramfs/init.script +++ b/files/initramfs/init.script @@ -130,6 +130,21 @@ determine_fs() { echo "${_fs}" } +get_active_console() { + local active_console=console + + while [ -f /sys/class/tty/${active_console}/active ] + do + active_console=$(cat /sys/class/tty/${active_console}/active) + + # last console will be the active one, + # see https://www.kernel.org/doc/html/latest/admin-guide/serial-console.html + active_console=${active_console##* } + done + + echo ${active_console} +} + findmediamount() { # $1 = mount dir name / media name # $2 = recognition file From 55d84e71f0ac6904f0f8d81897eabf4d5fbe6a35 Mon Sep 17 00:00:00 2001 From: andreili Date: Thu, 21 Aug 2025 23:20:43 +0200 Subject: [PATCH 20/28] Update kernel to 6.16-rc2 --- cfg/btt_pi2/uboot | 98 +- cfg/{kernel_v6.14-rc7 => kernel_v6.16-rc2} | 408 +- config/board/btt_pi2.json | 4 +- files/backups/excl_min.lst | 7 - patch/kernel/h616_old | 78 + patch/kernel/printer_defconfig_1_plat.patch | 79 +- .../printer_edt_ft5x06_noIRQ_support.patch | 4 +- ...neral-add-hdmi-mks-ips50-resolutions.patch | 83 + .../general-add-miniDP-dt-doc.patch | 133 + .../general-add-miniDP-virtual-extcon.patch | 382 ++ ...eral-add-overlay-compilation-support.patch | 66 + .../general-add-overlay-configfs.patch | 419 ++ .../general-add-panel-simple-dsi.patch | 856 ++++ .../general-add-pll-hdmi-timings.patch | 155 + .../general-add-xtx-spi-nor-chips.patch | 82 + .../general-cryptov1-trng.patch | 302 ++ .../general-disable-mtu-validation.patch | 51 + .../general-driver-tm16xx-led-driver.patch | 1397 ++++++ ...al-drm-panel-add-yixian-yx0345-panel.patch | 378 ++ ...-drm-rockchip-Set-dma-mask-to-64-bit.patch | 39 + .../general-fix-es8316-kernel-panic.patch | 105 + ...fix-mmc-signal-voltage-before-reboot.patch | 46 + .../general-hdmi-clock-fixes.patch | 257 ++ .../general-increase-spdif-dma-burst.patch | 25 + ..._DMA_block_memory_allocation_to_2048.patch | 140 + ...eral-pl330-01-fix-periodic-transfers.patch | 421 ++ ...dd-support-for-interleaved-transfers.patch | 261 ++ ...general-pl330-04-bigger-mcode-buffer.patch | 27 + ...l-pl330-05-fix-unbalanced-power-down.patch | 81 + ...eneral-pl330-06-fix-buffer-underruns.patch | 70 + ...l-possibility-of-disabling-rk808-rtc.patch | 51 + ...08-configurable-switch-voltage-steps.patch | 104 + .../general-rockchip-overlays.patch | 30 + .../general-st7796-driver.patch | 203 + .../general-v4l2-iep-driver.patch | 1808 ++++++++ .../general-v4l2-rkvdec-01-vp9.patch | 491 +++ .../media-0001-Add-rkvdec2-Support-v3.patch | 3748 +++++++++++++++++ ...Initialize-h264-frame_mbs_only_flag-.patch | 43 + ...edia-0003-rk3568-disable-hantro-h264.patch | 97 + ...-r8152-add-LED-configuration-from-OF.patch | 79 + .../regulator-add-fan53200-driver.patch | 597 +++ .../rk356x-add-rkvdec2-support.patch | 77 + .../rk3588-0010-fix-clk-divisions.patch | 142 + .../rk35xx-montjoie-crypto-v2-rk35xx.patch | 2328 ++++++++++ .../temporary-workaround-dma-reset.patch | 21 + .../wifi-4003-add-bcm43342-chip.patch | 45 + patch/uboot/btt/btt_pi2_support.patch | 102 +- tmp/rk3566-bigtreetech-cb2.dtsi | 43 +- tmp/rk3566-bigtreetech-pi2.dts | 79 +- tmp/rk356x-base.dtsi | 46 +- 50 files changed, 16014 insertions(+), 574 deletions(-) rename cfg/{kernel_v6.14-rc7 => kernel_v6.16-rc2} (95%) create mode 100644 patch/kernel/h616_old create mode 100644 patch/kernel/rockchip64-6.16/general-add-hdmi-mks-ips50-resolutions.patch create mode 100644 patch/kernel/rockchip64-6.16/general-add-miniDP-dt-doc.patch create mode 100644 patch/kernel/rockchip64-6.16/general-add-miniDP-virtual-extcon.patch create mode 100644 patch/kernel/rockchip64-6.16/general-add-overlay-compilation-support.patch create mode 100644 patch/kernel/rockchip64-6.16/general-add-overlay-configfs.patch create mode 100644 patch/kernel/rockchip64-6.16/general-add-panel-simple-dsi.patch create mode 100644 patch/kernel/rockchip64-6.16/general-add-pll-hdmi-timings.patch create mode 100644 patch/kernel/rockchip64-6.16/general-add-xtx-spi-nor-chips.patch create mode 100644 patch/kernel/rockchip64-6.16/general-cryptov1-trng.patch create mode 100644 patch/kernel/rockchip64-6.16/general-disable-mtu-validation.patch create mode 100644 patch/kernel/rockchip64-6.16/general-driver-tm16xx-led-driver.patch create mode 100644 patch/kernel/rockchip64-6.16/general-drm-panel-add-yixian-yx0345-panel.patch create mode 100644 patch/kernel/rockchip64-6.16/general-drm-rockchip-Set-dma-mask-to-64-bit.patch create mode 100644 patch/kernel/rockchip64-6.16/general-fix-es8316-kernel-panic.patch create mode 100644 patch/kernel/rockchip64-6.16/general-fix-mmc-signal-voltage-before-reboot.patch create mode 100644 patch/kernel/rockchip64-6.16/general-hdmi-clock-fixes.patch create mode 100644 patch/kernel/rockchip64-6.16/general-increase-spdif-dma-burst.patch create mode 100644 patch/kernel/rockchip64-6.16/general-increasing_DMA_block_memory_allocation_to_2048.patch create mode 100644 patch/kernel/rockchip64-6.16/general-pl330-01-fix-periodic-transfers.patch create mode 100644 patch/kernel/rockchip64-6.16/general-pl330-02-add-support-for-interleaved-transfers.patch create mode 100644 patch/kernel/rockchip64-6.16/general-pl330-04-bigger-mcode-buffer.patch create mode 100644 patch/kernel/rockchip64-6.16/general-pl330-05-fix-unbalanced-power-down.patch create mode 100644 patch/kernel/rockchip64-6.16/general-pl330-06-fix-buffer-underruns.patch create mode 100644 patch/kernel/rockchip64-6.16/general-possibility-of-disabling-rk808-rtc.patch create mode 100644 patch/kernel/rockchip64-6.16/general-rk808-configurable-switch-voltage-steps.patch create mode 100644 patch/kernel/rockchip64-6.16/general-rockchip-overlays.patch create mode 100644 patch/kernel/rockchip64-6.16/general-st7796-driver.patch create mode 100644 patch/kernel/rockchip64-6.16/general-v4l2-iep-driver.patch create mode 100644 patch/kernel/rockchip64-6.16/general-v4l2-rkvdec-01-vp9.patch create mode 100644 patch/kernel/rockchip64-6.16/media-0001-Add-rkvdec2-Support-v3.patch create mode 100644 patch/kernel/rockchip64-6.16/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch create mode 100644 patch/kernel/rockchip64-6.16/media-0003-rk3568-disable-hantro-h264.patch create mode 100644 patch/kernel/rockchip64-6.16/net-usb-r8152-add-LED-configuration-from-OF.patch create mode 100644 patch/kernel/rockchip64-6.16/regulator-add-fan53200-driver.patch create mode 100644 patch/kernel/rockchip64-6.16/rk356x-add-rkvdec2-support.patch create mode 100644 patch/kernel/rockchip64-6.16/rk3588-0010-fix-clk-divisions.patch create mode 100644 patch/kernel/rockchip64-6.16/rk35xx-montjoie-crypto-v2-rk35xx.patch create mode 100644 patch/kernel/rockchip64-6.16/temporary-workaround-dma-reset.patch create mode 100644 patch/kernel/rockchip64-6.16/wifi-4003-add-bcm43342-chip.patch diff --git a/cfg/btt_pi2/uboot b/cfg/btt_pi2/uboot index 06de31c..372f6df 100644 --- a/cfg/btt_pi2/uboot +++ b/cfg/btt_pi2/uboot @@ -1,10 +1,10 @@ # # Automatically generated file; DO NOT EDIT. -# U-Boot 2025.07-rc5 Configuration +# U-Boot 2025.10-rc2 Configuration # # -# Compiler: aarch64-linux-gnu-gcc (Gentoo 15.1.0 p1) 15.1.0 +# Compiler: aarch64-linux-gnu-gcc (Gentoo 15.1.1_p20250705-r1 p2) 15.1.1 20250705 # CONFIG_CREATE_ARCH_SYMLINK=y CONFIG_HAVE_SETJMP=y @@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_SHIFT_6=y CONFIG_64BIT=y CONFIG_SPL_64BIT=y CONFIG_SYS_CACHELINE_SIZE=64 +CONFIG_SYS_DTC_PAD_BYTES=4096 CONFIG_LINKER_LIST_ALIGN=8 # CONFIG_ARC is not set CONFIG_ARM=y @@ -56,6 +57,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 # CONFIG_POSITION_INDEPENDENT is not set # CONFIG_INIT_SP_RELATIVE is not set CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE=0x00a00000 +# CONFIG_KVM_VIRT_INS is not set # CONFIG_DRIVER_GICV2 is not set # CONFIG_GIC_V3_ITS is not set # CONFIG_GICV3_SUPPORT_GIC600 is not set @@ -113,7 +115,6 @@ CONFIG_ARM64_SUPPORT_AARCH32=y # CONFIG_ARCH_IMXRT is not set # CONFIG_ARCH_MX23 is not set # CONFIG_ARCH_MX28 is not set -# CONFIG_ARCH_MX31 is not set # CONFIG_ARCH_MX7ULP is not set # CONFIG_ARCH_MX7 is not set # CONFIG_ARCH_MX6 is not set @@ -322,11 +323,12 @@ CONFIG_SYS_LITTLE_ENDIAN=y # # General setup # +# CONFIG_COMPILE_TEST is not set # CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=150100 +CONFIG_GCC_VERSION=150101 CONFIG_CLANG_VERSION=0 CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_CC_OPTIMIZE_FOR_SPEED is not set @@ -376,6 +378,7 @@ CONFIG_SYS_UBOOT_START=0x00a00000 # Boot images # # CONFIG_ANDROID_BOOT_IMAGE is not set +# CONFIG_ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR is not set # CONFIG_TIMESTAMP is not set CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x0 @@ -420,6 +423,7 @@ CONFIG_BOOTMETH_VBE_SIMPLE=y # CONFIG_BOOTMETH_VBE_ABREC is not set CONFIG_BOOTMETH_VBE_SIMPLE_OS=y # CONFIG_SPL_BOOTMETH_VBE_SIMPLE is not set +# CONFIG_BOOTMETH_RAUC is not set CONFIG_BOOTMETH_SCRIPT=y # CONFIG_UPL is not set CONFIG_LEGACY_IMAGE_FORMAT=y @@ -466,6 +470,7 @@ CONFIG_BOOTDELAY=2 # # CONFIG_OF_ENV_SETUP is not set # CONFIG_OF_BOARD_SETUP is not set +# CONFIG_OF_BOARD_SETUP_EXTENDED is not set # CONFIG_OF_SYSTEM_SETUP is not set # CONFIG_OF_STDOUT_VIA_ALIAS is not set # CONFIG_FDT_FIXUP_PARTITIONS is not set @@ -526,9 +531,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_CYCLIC is not set CONFIG_EVENT=y # CONFIG_EVENT_DEBUG is not set -# CONFIG_ARCH_MISC_INIT is not set # CONFIG_BOARD_EARLY_INIT_F is not set # CONFIG_BOARD_EARLY_INIT_R is not set +CONFIG_BOARD_INIT=y # CONFIG_BOARD_POSTCLK_INIT is not set CONFIG_BOARD_LATE_INIT=y # CONFIG_CLOCKS is not set @@ -614,7 +619,7 @@ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=1 # CONFIG_SPL_MMC_TINY is not set # CONFIG_SPL_MMC_WRITE is not set # CONFIG_SPL_MPC8XXX_INIT_DDR is not set -# CONFIG_SPL_MTD is not set +CONFIG_SPL_MTD=y # CONFIG_SPL_MUSB_NEW is not set # CONFIG_SPL_NAND_SUPPORT is not set # CONFIG_SPL_NAND_DRIVERS is not set @@ -640,7 +645,7 @@ CONFIG_SPL_DM_SPI_FLASH=y # CONFIG_SPL_SATA is not set # CONFIG_SPL_NVME is not set CONFIG_SPL_SPI_FLASH_TINY=y -# CONFIG_SPL_SPI_FLASH_MTD is not set +CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 # CONFIG_SPL_THERMAL is not set @@ -683,6 +688,7 @@ CONFIG_CMD_BDI=y # CONFIG_CMD_CONFIG is not set CONFIG_CMD_CONSOLE=y # CONFIG_CMD_UFETCH is not set +CONFIG_CMD_HELP=y # CONFIG_CMD_HISTORY is not set # CONFIG_CMD_LICENSE is not set # CONFIG_CMD_PMC is not set @@ -875,7 +881,6 @@ CONFIG_CMD_REGULATOR=y # Security commands # # CONFIG_CMD_AES is not set -# CONFIG_CMD_BLOB is not set # CONFIG_CMD_HASH is not set # CONFIG_CMD_HVC is not set # CONFIG_CMD_SMC is not set @@ -970,7 +975,7 @@ CONFIG_ENV_SUPPORT=y CONFIG_ENV_CALLBACK_LIST_STATIC="" CONFIG_SAVEENV=y # CONFIG_ENV_OVERWRITE is not set -# CONFIG_OVERWRITE_ETHADDR_ONCE is not set +# CONFIG_ENV_OVERWRITE_ETHADDR_ONCE is not set CONFIG_ENV_MIN_ENTRIES=64 CONFIG_ENV_MAX_ENTRIES=512 CONFIG_ENV_IS_DEFAULT=y @@ -981,13 +986,14 @@ CONFIG_ENV_IS_NOWHERE=y # CONFIG_ENV_IS_IN_FLASH is not set # CONFIG_ENV_IS_IN_MMC is not set # CONFIG_ENV_IS_IN_NAND is not set +# CONFIG_ENV_IS_IN_SCSI is not set # CONFIG_ENV_IS_IN_NVRAM is not set # CONFIG_ENV_IS_IN_REMOTE is not set # CONFIG_ENV_IS_IN_SPI_FLASH is not set # CONFIG_ENV_IS_IN_MTD is not set -# CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_USE_DEFAULT_ENV_FILE is not set +# CONFIG_ENV_REDUNDANT is not set +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +# CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE is not set # CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set # CONFIG_ENV_IMPORT_FDT is not set # CONFIG_ENV_APPEND is not set @@ -1043,7 +1049,6 @@ CONFIG_OFNODE_MULTI_TREE_MAX=4 CONFIG_BOUNCE_BUFFER=y CONFIG_ADC=y # CONFIG_SPL_ADC is not set -# CONFIG_ADC_EXYNOS is not set # CONFIG_ADC_SANDBOX is not set # CONFIG_SARADC_MESON is not set CONFIG_SARADC_ROCKCHIP=y @@ -1082,7 +1087,6 @@ CONFIG_BLOCK_CACHE=y # # CONFIG_CACHE is not set # CONFIG_L2X0_CACHE is not set -# CONFIG_ANDES_L2_CACHE is not set # CONFIG_NCORE_CACHE is not set # CONFIG_SIFIVE_CCACHE is not set # CONFIG_SIFIVE_PL2 is not set @@ -1091,6 +1095,7 @@ CONFIG_BLOCK_CACHE=y # Clock # CONFIG_CLK=y +# CONFIG_CLK_AUTO_ID is not set CONFIG_SPL_CLK=y # CONFIG_SPL_CLK_CCF is not set # CONFIG_CLK_CCF is not set @@ -1120,12 +1125,12 @@ CONFIG_SPL_CLK=y # Hardware crypto devices # # CONFIG_DM_HASH is not set +# CONFIG_DM_AES is not set # CONFIG_FSL_CAAM is not set CONFIG_CAAM_64BIT=y # CONFIG_SYS_FSL_SEC_BE is not set # CONFIG_SYS_FSL_SEC_LE is not set # CONFIG_FSL_DCP_RNG is not set -# CONFIG_NPCM_AES is not set # CONFIG_NPCM_SHA is not set # CONFIG_DDR_SPD is not set # CONFIG_IMX_SNPS_DDR_PHY is not set @@ -1143,8 +1148,6 @@ CONFIG_CAAM_64BIT=y # DMA Support # # CONFIG_DMA is not set -# CONFIG_DMA_LPC32XX is not set -# CONFIG_TI_EDMA3 is not set # CONFIG_DMA_LEGACY is not set # @@ -1158,7 +1161,6 @@ CONFIG_CAAM_64BIT=y CONFIG_FIRMWARE=y # CONFIG_SPL_FIRMWARE is not set CONFIG_ARM_PSCI_FW=y -# CONFIG_ZYNQMP_FIRMWARE is not set # CONFIG_ARM_SMCCC_FEATURES is not set # CONFIG_ARM_FFA_TRANSPORT is not set # CONFIG_SCMI_FIRMWARE is not set @@ -1168,7 +1170,6 @@ CONFIG_ARM_PSCI_FW=y # FPGA support # # CONFIG_FPGA_ALTERA is not set -# CONFIG_FPGA_SOCFPGA is not set # CONFIG_FPGA_LATTICE is not set # CONFIG_FPGA_XILINX is not set # CONFIG_DM_FPGA is not set @@ -1180,53 +1181,32 @@ CONFIG_SPL_DM_GPIO=y # CONFIG_DM_GPIO_LOOKUP_LABEL is not set # CONFIG_SPL_DM_GPIO_LOOKUP_LABEL is not set # CONFIG_ALTERA_PIO is not set -# CONFIG_BCM2835_GPIO is not set # CONFIG_DWAPB_GPIO is not set -# CONFIG_AT91_GPIO is not set -# CONFIG_ATMEL_PIO4 is not set # CONFIG_ASPEED_GPIO is not set # CONFIG_ASPEED_SGPIO is not set # CONFIG_ASPEED_G7_GPIO is not set # CONFIG_DA8XX_GPIO is not set # CONFIG_FXL6408_GPIO is not set -# CONFIG_HIKEY_GPIO is not set -# CONFIG_INTEL_BROADWELL_GPIO is not set -# CONFIG_INTEL_GPIO is not set -# CONFIG_INTEL_ICH6_GPIO is not set -# CONFIG_IMX_RGPIO2P is not set # CONFIG_IPROC_GPIO is not set # CONFIG_HSDK_CREG_GPIO is not set -# CONFIG_KIRKWOOD_GPIO is not set -# CONFIG_LPC32XX_GPIO is not set # CONFIG_MAX7320_GPIO is not set # CONFIG_MCP230XX_GPIO is not set -# CONFIG_MSM_GPIO is not set -# CONFIG_MXC_GPIO is not set -# CONFIG_MXS_GPIO is not set -# CONFIG_NPCM_GPIO is not set -# CONFIG_NPCM_SGPIO is not set # CONFIG_CMD_PCA953X is not set # CONFIG_PCF8575_GPIO is not set CONFIG_ROCKCHIP_GPIO=y # CONFIG_XILINX_GPIO is not set -# CONFIG_TCA642X is not set -# CONFIG_TEGRA_GPIO is not set # CONFIG_TEGRA186_GPIO is not set -# CONFIG_VYBRID_GPIO is not set -# CONFIG_SIFIVE_GPIO is not set # CONFIG_ZYNQ_GPIO is not set # CONFIG_DM_74X164 is not set # CONFIG_DM_PCA953X is not set # CONFIG_ADP5588_GPIO is not set # CONFIG_SPL_DM_PCA953X is not set # CONFIG_PCA953X is not set -# CONFIG_MPC8XXX_GPIO is not set -# CONFIG_MPC8XX_GPIO is not set # CONFIG_NX_GPIO is not set # CONFIG_NOMADIK_GPIO is not set -# CONFIG_SLG7XL45106_I2C_GPO is not set # CONFIG_FTGPIO010 is not set # CONFIG_ADP5585_GPIO is not set +# CONFIG_MPFS_GPIO is not set # # Hardware Spinlock Support @@ -1238,31 +1218,26 @@ CONFIG_SPL_DM_I2C=y # CONFIG_I2C_SET_DEFAULT_BUS_NUM is not set # CONFIG_DM_I2C_GPIO is not set # CONFIG_SYS_I2C_IPROC is not set -# CONFIG_SYS_I2C_FSL is not set # CONFIG_SYS_I2C_CADENCE is not set # CONFIG_SYS_I2C_DW is not set # CONFIG_SYS_I2C_INTEL is not set -# CONFIG_SYS_I2C_IMX_LPI2C is not set # CONFIG_SYS_I2C_MTK is not set # CONFIG_SYS_I2C_MICROCHIP is not set -# CONFIG_SYS_I2C_MXC is not set -# CONFIG_SYS_I2C_NEXELL is not set -# CONFIG_SYS_I2C_NPCM is not set # CONFIG_SYS_I2C_OCORES is not set CONFIG_SYS_I2C_ROCKCHIP=y # CONFIG_SYS_I2C_SOFT is not set # CONFIG_SYS_I2C_S3C24X0 is not set # CONFIG_SYS_I2C_MV is not set -# CONFIG_SYS_I2C_MVTWSI is not set # CONFIG_SYS_I2C_XILINX_XIIC is not set # CONFIG_SYS_I2C_IHS is not set # CONFIG_I2C_MUX is not set +# CONFIG_I3C is not set +# CONFIG_I3C_SANDBOX is not set CONFIG_INPUT=y # CONFIG_SPL_INPUT is not set # CONFIG_DM_KEYBOARD is not set # CONFIG_SPL_DM_KEYBOARD is not set # CONFIG_CROS_EC_KEYB is not set -# CONFIG_TEGRA_KEYBOARD is not set # CONFIG_TWL4030_INPUT is not set # @@ -1315,13 +1290,10 @@ CONFIG_ROCKCHIP_IODOMAIN=y # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_CROS_EC is not set # CONFIG_SPL_CROS_EC is not set -# CONFIG_DS4510 is not set -# CONFIG_FSL_SEC_MON is not set # CONFIG_IRQ is not set # CONFIG_NPCM_HOST is not set # CONFIG_NUVOTON_NCT6102D is not set # CONFIG_PWRSEQ is not set -# CONFIG_PCA9551_LED is not set # CONFIG_TEST_DRV is not set # CONFIG_TURRIS_OMNIA_MCU is not set # CONFIG_USB_HUB_USB251XB is not set @@ -1335,7 +1307,6 @@ CONFIG_ROCKCHIP_IODOMAIN=y # CONFIG_FS_LOADER is not set # CONFIG_SPL_FS_LOADER is not set # CONFIG_GDSYS_SOC is not set -# CONFIG_IHS_FPGA is not set # CONFIG_MICROCHIP_FLEXCOM is not set # CONFIG_ESM_PMIC is not set # CONFIG_SL28CPLD is not set @@ -1373,34 +1344,23 @@ CONFIG_MMC_DW=y # CONFIG_MMC_DW_K3 is not set CONFIG_MMC_DW_ROCKCHIP=y # CONFIG_MMC_DW_SNPS is not set -# CONFIG_MMC_MXC is not set # CONFIG_MMC_PCI is not set -# CONFIG_MMC_OMAP_HS is not set CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_SPL_MMC_SDHCI_SDMA=y # CONFIG_MMC_SDHCI_ADMA is not set # CONFIG_SPL_MMC_SDHCI_ADMA is not set -# CONFIG_MMC_SDHCI_BCMSTB is not set CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC_SDHCI_CV1800B=y # CONFIG_MMC_SDHCI_IPROC is not set # CONFIG_MMC_SDHCI_F_SDH30 is not set -# CONFIG_MMC_SDHCI_KONA is not set -# CONFIG_MMC_SDHCI_MSM is not set # CONFIG_MMC_SDHCI_NPCM is not set CONFIG_MMC_SDHCI_ROCKCHIP=y -# CONFIG_MMC_SDHCI_S5P is not set # CONFIG_MMC_SDHCI_SNPS is not set -# CONFIG_MMC_SDHCI_STI is not set # CONFIG_MMC_SDHCI_XENON is not set # CONFIG_MMC_SDHCI_TANGIER is not set -# CONFIG_MMC_SDHCI_ZYNQ is not set # CONFIG_MMC_PITON is not set -# CONFIG_STM32_SDMMC2 is not set # CONFIG_FTSDC010 is not set -# CONFIG_FSL_ESDHC is not set -# CONFIG_FSL_ESDHC_IMX is not set # # MTD Support @@ -1465,7 +1425,6 @@ CONFIG_SPI_FLASH_MTD=y # CONFIG_MV88E6352_SWITCH is not set # CONFIG_FSL_MEMAC is not set CONFIG_PHY_RESET_DELAY=0 -# CONFIG_FSL_PFE is not set CONFIG_ETH=y CONFIG_DM_ETH_PHY=y CONFIG_NVME=y @@ -1502,6 +1461,7 @@ CONFIG_PCIE_DW_ROCKCHIP=y # PCI Endpoint # # CONFIG_PCI_ENDPOINT is not set +# CONFIG_PCIE_CDNS_TI_EP is not set # CONFIG_X86_PCH7 is not set # CONFIG_X86_PCH9 is not set @@ -1557,10 +1517,13 @@ CONFIG_SPL_PINCONF_RECURSIVE=y # CONFIG_PINCTRL_INTEL is not set # CONFIG_PINCTRL_QE is not set # CONFIG_PINCTRL_ROCKCHIP_RV1108 is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_SPL_PINCTRL_SX150X is not set # CONFIG_PINCTRL_SINGLE is not set # CONFIG_PINCTRL_STM32 is not set # CONFIG_PINCTRL_STMFX is not set # CONFIG_SPL_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_TH1520 is not set # CONFIG_PINCTRL_K210 is not set CONFIG_PINCTRL_ROCKCHIP=y CONFIG_SPL_PINCTRL_ROCKCHIP=y @@ -1657,7 +1620,10 @@ CONFIG_DM_PWM=y # CONFIG_PWM_SIFIVE is not set # CONFIG_PWM_TEGRA is not set # CONFIG_PWM_SUNXI is not set -# CONFIG_U_QE is not set + +# +# RAM drivers using Driver Model +# CONFIG_RAM=y CONFIG_SPL_RAM=y # CONFIG_STM32_SDRAM is not set @@ -1808,7 +1774,6 @@ CONFIG_SPI_MEM=y # CONFIG_MTK_SNOR is not set # CONFIG_MTK_SNFI_SPI is not set # CONFIG_MTK_SPIM is not set -# CONFIG_MVEBU_A3700_SPI is not set # CONFIG_SPI_MXIC is not set # CONFIG_NPCM_FIU_SPI is not set # CONFIG_NPCM_PSPI is not set @@ -1948,6 +1913,7 @@ CONFIG_STRTO=y CONFIG_SPL_STRTO=y CONFIG_SYS_HZ=1000 CONFIG_SPL_USE_TINY_PRINTF=y +# CONFIG_SPL_USE_TINY_PRINTF_POINTER_SUPPORT is not set # CONFIG_PANIC_HANG is not set CONFIG_REGEX=y CONFIG_LIB_RAND=y diff --git a/cfg/kernel_v6.14-rc7 b/cfg/kernel_v6.16-rc2 similarity index 95% rename from cfg/kernel_v6.14-rc7 rename to cfg/kernel_v6.16-rc2 index eacc9c0..4d9795f 100644 --- a/cfg/kernel_v6.14-rc7 +++ b/cfg/kernel_v6.16-rc2 @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.14.0-rc7 Kernel Configuration +# Linux/arm64 6.16.0-rc2 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Gentoo 15.1.1_p20250705-r1 p2) 15.1.1 20250705" CONFIG_CC_IS_GCC=y @@ -14,14 +14,17 @@ CONFIG_LLD_VERSION=0 CONFIG_RUSTC_VERSION=108900 CONFIG_RUSTC_LLVM_VERSION=200107 CONFIG_CC_CAN_LINK=y -CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y CONFIG_TOOLS_SUPPORT_RELR=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_CC_HAS_COUNTED_BY=y +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING=y +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY=y CONFIG_RUSTC_HAS_COERCE_POINTEE=y +CONFIG_RUSTC_HAS_SPAN_FILE=y +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES=y CONFIG_PAHOLE_VERSION=130 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y @@ -45,7 +48,6 @@ CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y -# CONFIG_USELIB is not set # CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y @@ -61,7 +63,6 @@ CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y CONFIG_GENERIC_IRQ_IPI=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_IRQ_MSI_IOMMU=y @@ -104,9 +105,11 @@ CONFIG_BPF_UNPRIV_DEFAULT_OFF=y # end of BPF subsystem CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_ARCH_HAS_PREEMPT_LAZY=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set +# CONFIG_PREEMPT_LAZY is not set # CONFIG_PREEMPT_RT is not set # CONFIG_PREEMPT_DYNAMIC is not set @@ -211,11 +214,11 @@ CONFIG_LD_ORPHAN_WARN_LEVEL="warn" CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_SYSFS_SYSCALL is not set CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y # CONFIG_SGETMASK_SYSCALL is not set -CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y @@ -223,6 +226,7 @@ CONFIG_BUG=y # CONFIG_BASE_SMALL is not set CONFIG_FUTEX=y CONFIG_FUTEX_PI=y +CONFIG_FUTEX_PRIVATE_HASH=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -239,6 +243,7 @@ CONFIG_CACHESTAT_SYSCALL=y # CONFIG_PC104 is not set # CONFIG_KALLSYMS is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS=y CONFIG_HAVE_PERF_EVENTS=y # @@ -259,6 +264,7 @@ CONFIG_KEXEC_CORE=y CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y # CONFIG_KEXEC_SIG is not set +# CONFIG_KEXEC_HANDOVER is not set CONFIG_CRASH_DUMP=y # end of Kexec and crash features # end of General setup @@ -295,7 +301,7 @@ CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y # # CONFIG_ARCH_ACTIONS is not set # CONFIG_ARCH_AIROHA is not set -CONFIG_ARCH_SUNXI=y +# CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_APPLE is not set # CONFIG_ARCH_BCM is not set @@ -342,6 +348,7 @@ CONFIG_ARCH_ROCKCHIP=y # ARM errata workarounds via the alternatives framework # # CONFIG_AMPERE_ERRATUM_AC03_CPU_38 is not set +CONFIG_AMPERE_ERRATUM_AC04_CPU_23=y CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y CONFIG_ARM64_ERRATUM_826319=y CONFIG_ARM64_ERRATUM_827319=y @@ -351,7 +358,6 @@ CONFIG_ARM64_ERRATUM_832075=y CONFIG_ARM64_ERRATUM_1742098=y CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y CONFIG_ARM64_ERRATUM_1024718=y CONFIG_ARM64_ERRATUM_1418040=y CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y @@ -388,6 +394,7 @@ CONFIG_ARM64_ERRATUM_2441009=y # CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set # CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set # CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set +CONFIG_ROCKCHIP_ERRATUM_3568002=y CONFIG_ROCKCHIP_ERRATUM_3588001=y # CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set # end of ARM errata workarounds via the alternatives framework @@ -425,6 +432,7 @@ CONFIG_ARCH_SELECTS_KEXEC_FILE=y CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_SUPPORTS_KEXEC_HANDOVER=y CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y CONFIG_ARCH_DEFAULT_CRASH_DUMP=y CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION=y @@ -446,7 +454,6 @@ CONFIG_KUSER_HELPERS=y # CONFIG_ARM64_HW_AFDBM=y CONFIG_ARM64_PAN=y -CONFIG_AS_HAS_LSE_ATOMICS=y CONFIG_ARM64_LSE_ATOMICS=y CONFIG_ARM64_USE_LSE_ATOMICS=y # end of ARMv8.1 architectural features @@ -454,8 +461,6 @@ CONFIG_ARM64_USE_LSE_ATOMICS=y # # ARMv8.2 architectural features # -CONFIG_AS_HAS_ARMV8_2=y -CONFIG_AS_HAS_SHA3=y # CONFIG_ARM64_PMEM is not set CONFIG_ARM64_RAS_EXTN=y CONFIG_ARM64_CNP=y @@ -467,17 +472,13 @@ CONFIG_ARM64_CNP=y CONFIG_ARM64_PTR_AUTH=y CONFIG_ARM64_PTR_AUTH_KERNEL=y CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y -CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y -CONFIG_AS_HAS_ARMV8_3=y CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y -CONFIG_AS_HAS_LDAPR=y # end of ARMv8.3 architectural features # # ARMv8.4 architectural features # CONFIG_ARM64_AMU_EXTN=y -CONFIG_AS_HAS_ARMV8_4=y CONFIG_ARM64_TLB_RANGE=y # end of ARMv8.4 architectural features @@ -515,6 +516,7 @@ CONFIG_ARM64_GCS=y # end of v9.4 architectural features CONFIG_ARM64_SVE=y +CONFIG_ARM64_SME=y # CONFIG_ARM64_PSEUDO_NMI is not set CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set @@ -604,7 +606,6 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPUFREQ_DT=y # CONFIG_CPUFREQ_VIRT is not set CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y CONFIG_ARM_SCMI_CPUFREQ=y # end of CPU Frequency scaling # end of CPU Power Management @@ -616,6 +617,7 @@ CONFIG_CPU_MITIGATIONS=y # General architecture-dependent options # CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y +CONFIG_HOTPLUG_SMT=y CONFIG_HOTPLUG_CORE_SYNC=y CONFIG_HOTPLUG_CORE_SYNC_DEAD=y # CONFIG_KPROBES is not set @@ -780,7 +782,6 @@ CONFIG_MSDOS_PARTITION=y CONFIG_EFI_PARTITION=y # end of Partition Types -CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y # @@ -879,6 +880,7 @@ CONFIG_SWAP=y # Slab allocator options # CONFIG_SLUB=y +CONFIG_KVFREE_RCU_BATCHED=y # CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set @@ -917,7 +919,9 @@ CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y # CONFIG_MEMORY_FAILURE is not set CONFIG_ARCH_WANTS_THP_SWAP=y # CONFIG_TRANSPARENT_HUGEPAGE is not set +CONFIG_PAGE_MAPCOUNT=y # CONFIG_CMA is not set +CONFIG_PAGE_BLOCK_ORDER=10 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set @@ -1002,7 +1006,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_NET_PTP_CLASSIFY=y # CONFIG_NETWORK_PHY_TIMESTAMPING is not set # CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set # CONFIG_TIPC is not set @@ -1123,6 +1126,7 @@ CONFIG_PCI_MSI=y CONFIG_PCI_QUIRKS=y # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set +# CONFIG_PCI_DOE is not set # CONFIG_PCI_IOV is not set # CONFIG_PCI_NPEM is not set # CONFIG_PCI_PRI is not set @@ -1160,8 +1164,10 @@ CONFIG_VGA_ARB_MAX_GPUS=16 # DesignWare-based PCIe controllers # CONFIG_PCIE_DW=y +# CONFIG_PCIE_DW_DEBUGFS is not set CONFIG_PCIE_DW_HOST=y # CONFIG_PCIE_AL is not set +# CONFIG_PCIE_AMD_MDB is not set # CONFIG_PCI_MESON is not set # CONFIG_PCI_HISI is not set # CONFIG_PCIE_KIRIN is not set @@ -1194,6 +1200,7 @@ CONFIG_PCIE_ROCKCHIP_DW_HOST=y # CONFIG_PCI_SW_SWITCHTEC is not set # end of PCI switch controller drivers +# CONFIG_PCI_PWRCTRL_SLOT is not set # CONFIG_CXL_BUS is not set # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set @@ -1245,8 +1252,6 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # Bus devices # # CONFIG_MOXTET is not set -CONFIG_SUN50I_DE2_BUS=y -CONFIG_SUNXI_RSB=y # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_MHI_BUS is not set # CONFIG_MHI_BUS_EP is not set @@ -1290,6 +1295,7 @@ CONFIG_ARM_SCMI_TRANSPORT_SMC=y # end of ARM System Control and Management Interface Protocol CONFIG_ARM_SCPI_PROTOCOL=y +# CONFIG_ARM_SDE_INTERFACE is not set # CONFIG_FIRMWARE_MEMMAP is not set # CONFIG_FW_CFG_SYSFS is not set # CONFIG_ARM_FFA_TRANSPORT is not set @@ -1312,6 +1318,7 @@ CONFIG_ARM_SMCCC_SOC_ID=y # end of Tegra firmware driver # end of Firmware Drivers +# CONFIG_FWCTL is not set # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -1463,6 +1470,7 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_DUMMY_IRQ is not set # CONFIG_PHANTOM is not set CONFIG_RPMB=y +# CONFIG_TI_FPC202 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1480,12 +1488,10 @@ CONFIG_RPMB=y # CONFIG_DW_XDATA_PCIE is not set # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set -# CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set # CONFIG_NTSYNC is not set # CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_MCHP_LAN966X_PCI is not set -# CONFIG_MODEM_POWER is not set # CONFIG_C2PORT is not set # @@ -1506,7 +1512,6 @@ CONFIG_EEPROM_AT24=y # CONFIG_ALTERA_STAPL is not set # CONFIG_VMWARE_VMCI is not set # CONFIG_GENWQE is not set -# CONFIG_ECHO is not set # CONFIG_BCM_VK is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set @@ -1515,7 +1520,7 @@ CONFIG_EEPROM_AT24=y # CONFIG_PVPANIC is not set # CONFIG_GP_PCI1XXXX is not set # CONFIG_KEBA_CP500 is not set -CONFIG_SUNXI_ADDR_MGT=y +# CONFIG_AMD_SBRMI_I2C is not set # end of Misc devices # @@ -1622,6 +1627,7 @@ CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set # CONFIG_WIREGUARD is not set +# CONFIG_OVPN is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_FC is not set # CONFIG_NET_TEAM is not set @@ -1645,9 +1651,6 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_ADAPTEC is not set # CONFIG_NET_VENDOR_AGERE is not set # CONFIG_NET_VENDOR_ALACRITECH is not set -CONFIG_NET_VENDOR_ALLWINNER=y -# CONFIG_SUN4I_EMAC is not set -CONFIG_SUNXI_GMAC=y # CONFIG_NET_VENDOR_ALTEON is not set # CONFIG_ALTERA_TSE is not set # CONFIG_NET_VENDOR_AMAZON is not set @@ -1713,11 +1716,9 @@ CONFIG_NET_VENDOR_STMICRO=y CONFIG_STMMAC_ETH=y # CONFIG_STMMAC_SELFTESTS is not set CONFIG_STMMAC_PLATFORM=y -CONFIG_DWMAC_DWC_QOS_ETH=y +# CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=y CONFIG_DWMAC_ROCKCHIP=y -CONFIG_DWMAC_SUNXI=y -CONFIG_DWMAC_SUN8I=y # CONFIG_DWMAC_INTEL_PLAT is not set # CONFIG_STMMAC_PCI is not set # CONFIG_NET_VENDOR_SUN is not set @@ -1742,9 +1743,8 @@ CONFIG_FIXED_PHY=y # # MII PHY device drivers # +# CONFIG_AS21XXX_PHY is not set # CONFIG_AIR_EN8811H_PHY is not set -CONFIG_AC200_PHY=y -CONFIG_AC200_PHY_SUNXI=y # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_ADIN1100_PHY is not set @@ -1767,6 +1767,7 @@ CONFIG_AC200_PHY_SUNXI=y # CONFIG_MARVELL_88Q2XXX_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set # CONFIG_MAXLINEAR_GPHY is not set +# CONFIG_MAXLINEAR_86110_PHY is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set # CONFIG_MICROCHIP_T1S_PHY is not set @@ -1849,12 +1850,9 @@ CONFIG_CAN_GS_USB=y # end of CAN USB interfaces # CONFIG_CAN_DEBUG_DEVICES is not set -CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_SUN4I is not set # CONFIG_MDIO_BITBANG is not set # CONFIG_MDIO_BCM_UNIMAC is not set # CONFIG_MDIO_HISI_FEMAC is not set @@ -1868,7 +1866,6 @@ CONFIG_MDIO_DEVRES=y # # MDIO Multiplexers # -CONFIG_MDIO_BUS_MUX=y # CONFIG_MDIO_BUS_MUX_GPIO is not set # CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set # CONFIG_MDIO_BUS_MUX_MMIOREG is not set @@ -1883,7 +1880,6 @@ CONFIG_PCS_XPCS=y # CONFIG_SLIP is not set # CONFIG_USB_NET_DRIVERS is not set CONFIG_WLAN=y -# CONFIG_SSV6051 is not set # CONFIG_WLAN_VENDOR_ADMTEK is not set # CONFIG_WLAN_VENDOR_ATH is not set # CONFIG_WLAN_VENDOR_ATMEL is not set @@ -1975,7 +1971,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_KEYBOARD_SAMSUNG is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set -CONFIG_KEYBOARD_SUN4I_LRADC=y # CONFIG_KEYBOARD_OMAP4 is not set # CONFIG_KEYBOARD_TM2_TOUCHKEY is not set # CONFIG_KEYBOARD_XTKBD is not set @@ -2009,7 +2004,6 @@ CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_CY8CTMA140 is not set # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set # CONFIG_TOUCHSCREEN_CYTTSP5 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set @@ -2059,7 +2053,6 @@ CONFIG_TOUCHSCREEN_EDT_FT5X06=m # CONFIG_TOUCHSCREEN_SIS_I2C is not set # CONFIG_TOUCHSCREEN_ST1232 is not set # CONFIG_TOUCHSCREEN_STMFTS is not set -# CONFIG_TOUCHSCREEN_SUN4I is not set # CONFIG_TOUCHSCREEN_SUR40 is not set # CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set # CONFIG_TOUCHSCREEN_SX8654 is not set @@ -2088,7 +2081,6 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set -# CONFIG_INPUT_AXP20X_PEK is not set # CONFIG_INPUT_UINPUT is not set # CONFIG_INPUT_PCF8574 is not set # CONFIG_INPUT_PWM_BEEPER is not set @@ -2120,7 +2112,6 @@ CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_PS2MULT is not set # CONFIG_SERIO_ARC_PS2 is not set # CONFIG_SERIO_APBPS2 is not set -# CONFIG_SERIO_SUN4I_PS2 is not set # CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set # CONFIG_GAMEPORT is not set @@ -2205,9 +2196,6 @@ CONFIG_SERIAL_DEV_CTRL_TTYPORT=y # CONFIG_TTY_PRINTK is not set # CONFIG_VIRTIO_CONSOLE is not set # CONFIG_IPMI_HANDLER is not set -CONFIG_SUNXI_SYS_INFO=y -CONFIG_DUMP_REG=y -CONFIG_DUMP_REG_MISC=y CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_HW_RANDOM_BA431 is not set @@ -2264,7 +2252,6 @@ CONFIG_I2C_ALGOBIT=y # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set -# CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_NFORCE2 is not set # CONFIG_I2C_NVIDIA_GPU is not set # CONFIG_I2C_SIS5595 is not set @@ -2283,7 +2270,6 @@ CONFIG_I2C_ALGOBIT=y CONFIG_I2C_GPIO=y # CONFIG_I2C_GPIO_FAULT_INJECTOR is not set # CONFIG_I2C_HISI is not set -CONFIG_I2C_MV64XXX=y # CONFIG_I2C_NOMADIK is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set @@ -2344,8 +2330,6 @@ CONFIG_SPI_ROCKCHIP_SFC=y # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set # CONFIG_SPI_SN_F_OSPI is not set -# CONFIG_SPI_SUN4I is not set -CONFIG_SPI_SUN6I=y # CONFIG_SPI_MXIC is not set # CONFIG_SPI_THUNDERX is not set # CONFIG_SPI_XCOMM is not set @@ -2402,7 +2386,6 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set -# CONFIG_PINCTRL_AXP209 is not set # CONFIG_PINCTRL_AW9523 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set @@ -2421,31 +2404,6 @@ CONFIG_PINCTRL_ROCKCHIP=y # # end of Renesas pinctrl drivers -CONFIG_PINCTRL_SUNXI=y -# CONFIG_PINCTRL_SUN4I_A10 is not set -# CONFIG_PINCTRL_SUN5I is not set -# CONFIG_PINCTRL_SUN6I_A31 is not set -# CONFIG_PINCTRL_SUN6I_A31_R is not set -# CONFIG_PINCTRL_SUN8I_A23 is not set -# CONFIG_PINCTRL_SUN8I_A33 is not set -# CONFIG_PINCTRL_SUN8I_A83T is not set -# CONFIG_PINCTRL_SUN8I_A83T_R is not set -# CONFIG_PINCTRL_SUN8I_A23_R is not set -# CONFIG_PINCTRL_SUN8I_H3 is not set -# CONFIG_PINCTRL_SUN8I_H3_R is not set -# CONFIG_PINCTRL_SUN8I_V3S is not set -# CONFIG_PINCTRL_SUN9I_A80 is not set -# CONFIG_PINCTRL_SUN9I_A80_R is not set -# CONFIG_PINCTRL_SUN20I_D1 is not set -# CONFIG_PINCTRL_SUN50I_A64 is not set -# CONFIG_PINCTRL_SUN50I_A64_R is not set -# CONFIG_PINCTRL_SUN50I_A100 is not set -# CONFIG_PINCTRL_SUN50I_A100_R is not set -# CONFIG_PINCTRL_SUN50I_H5 is not set -# CONFIG_PINCTRL_SUN50I_H6 is not set -# CONFIG_PINCTRL_SUN50I_H6_R is not set -CONFIG_PINCTRL_SUN50I_H616=y -CONFIG_PINCTRL_SUN50I_H616_R=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y @@ -2582,6 +2540,7 @@ CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_LTC2952 is not set CONFIG_POWER_RESET_REGULATOR=y CONFIG_POWER_RESET_RESTART=y +# CONFIG_POWER_RESET_TORADEX_EC is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y @@ -2595,6 +2554,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_IP5XXX_POWER is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CHAGALL is not set # CONFIG_BATTERY_CW2015 is not set # CONFIG_BATTERY_DS2760 is not set # CONFIG_BATTERY_DS2780 is not set @@ -2605,12 +2565,10 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_SBS is not set # CONFIG_MANAGER_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_AXP20X_POWER is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set # CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_MAX1721X is not set -# CONFIG_CHARGER_ISP1704 is not set # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_LP8727 is not set # CONFIG_CHARGER_GPIO is not set @@ -2619,6 +2577,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_MAX77976 is not set +# CONFIG_CHARGER_MAX8971 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -2687,6 +2646,7 @@ CONFIG_SENSORS_ARM_SCPI=y CONFIG_SENSORS_GPIO_FAN=y # CONFIG_SENSORS_HIH6130 is not set # CONFIG_SENSORS_HS3001 is not set +# CONFIG_SENSORS_HTU31 is not set # CONFIG_SENSORS_IIO_HWMON is not set # CONFIG_SENSORS_ISL28022 is not set # CONFIG_SENSORS_IT87 is not set @@ -2764,7 +2724,6 @@ CONFIG_SENSORS_GPIO_FAN=y # CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=y # CONFIG_SENSORS_SBTSI is not set -# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -2834,7 +2793,6 @@ CONFIG_CPU_FREQ_THERMAL=y CONFIG_DEVFREQ_THERMAL=y # CONFIG_THERMAL_EMULATION is not set # CONFIG_THERMAL_MMIO is not set -CONFIG_SUN8I_THERMAL=y CONFIG_ROCKCHIP_THERMAL=y # CONFIG_GENERIC_ADC_THERMAL is not set CONFIG_WATCHDOG=y @@ -2862,7 +2820,6 @@ CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_ARM_SBSA_WATCHDOG is not set # CONFIG_CADENCE_WATCHDOG is not set CONFIG_DW_WATCHDOG=y -CONFIG_SUNXI_WATCHDOG=y # CONFIG_MAX63XX_WATCHDOG is not set # CONFIG_ARM_SMC_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set @@ -2891,7 +2848,6 @@ CONFIG_BCMA_POSSIBLE=y CONFIG_MFD_CORE=y # CONFIG_MFD_ADP5585 is not set # CONFIG_MFD_ACT8945A is not set -# CONFIG_MFD_SUN4I_GPADC is not set # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_SMPRO is not set # CONFIG_MFD_AS3722 is not set @@ -2901,12 +2857,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_ATMEL_HLCDC is not set # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set -# CONFIG_MFD_AC100 is not set -# CONFIG_MFD_AC200 is not set -CONFIG_MFD_AC200_SUNXI=y -CONFIG_MFD_AXP20X=y -CONFIG_MFD_AXP20X_I2C=y -# CONFIG_MFD_AXP20X_RSB is not set +# CONFIG_MFD_AXP20X_I2C is not set # CONFIG_MFD_CS42L43_I2C is not set # CONFIG_MFD_MADERA is not set # CONFIG_MFD_MAX5970 is not set @@ -2938,7 +2889,9 @@ CONFIG_MFD_AXP20X_I2C=y # CONFIG_MFD_MAX77650 is not set # CONFIG_MFD_MAX77686 is not set # CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77705 is not set # CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77759 is not set # CONFIG_MFD_MAX77843 is not set # CONFIG_MFD_MAX8907 is not set # CONFIG_MFD_MAX8925 is not set @@ -2954,7 +2907,6 @@ CONFIG_MFD_AXP20X_I2C=y # CONFIG_MFD_VIPERBOARD is not set # CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set -# CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_SY7636A is not set # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_RT4831 is not set @@ -2965,12 +2917,11 @@ CONFIG_MFD_RK8XX=y CONFIG_MFD_RK8XX_I2C=y # CONFIG_MFD_RK8XX_SPI is not set # CONFIG_MFD_RN5T618 is not set -# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SEC_I2C is not set # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set # CONFIG_MFD_STMPE is not set -# CONFIG_MFD_SUN6I_PRCM is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_LP3943 is not set # CONFIG_MFD_LP8788 is not set @@ -3031,17 +2982,16 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER_OF is not set # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ADP5055 is not set # CONFIG_REGULATOR_ARM_SCMI is not set # CONFIG_REGULATOR_AW37503 is not set -CONFIG_REGULATOR_AXP20X=y # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set -CONFIG_REGULATOR_FAN53555=y +# CONFIG_REGULATOR_FAN53555 is not set # CONFIG_REGULATOR_FAN53880 is not set # CONFIG_REGULATOR_FAN53200 is not set CONFIG_REGULATOR_GPIO=y @@ -3071,6 +3021,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF9453 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -3078,7 +3029,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_PV88090 is not set # CONFIG_REGULATOR_PWM is not set # CONFIG_REGULATOR_RAA215300 is not set -CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT4803 is not set @@ -3093,7 +3044,6 @@ CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_RTQ2208 is not set # CONFIG_REGULATOR_SLG51000 is not set -CONFIG_REGULATOR_SUN20I=y # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set # CONFIG_REGULATOR_SY8827N is not set @@ -3106,7 +3056,6 @@ CONFIG_REGULATOR_SUN20I=y # CONFIG_REGULATOR_TPS65132 is not set # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_REGULATOR_VCTRL is not set -# CONFIG_REGULATOR_TP65185X is not set # CONFIG_RC_CORE is not set CONFIG_CEC_CORE=y CONFIG_CEC_NOTIFIER=y @@ -3116,6 +3065,7 @@ CONFIG_CEC_NOTIFIER=y # CONFIG_MEDIA_CEC_SUPPORT=y # CONFIG_CEC_CH7322 is not set +# CONFIG_CEC_NXP_TDA9950 is not set # CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC is not set # CONFIG_USB_PULSE8_CEC is not set # CONFIG_USB_RAINSHADOW_CEC is not set @@ -3282,12 +3232,6 @@ CONFIG_VIDEO_ROCKCHIP_RGA=y # # Sunxi media platform drivers # -# CONFIG_VIDEO_SUN4I_CSI is not set -# CONFIG_VIDEO_SUN6I_CSI is not set -# CONFIG_VIDEO_SUN6I_MIPI_CSI2 is not set -# CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 is not set -# CONFIG_VIDEO_SUN8I_DEINTERLACE is not set -# CONFIG_VIDEO_SUN8I_ROTATE is not set # CONFIG_VIDEO_SYNOPSYS_HDMIRX is not set # @@ -3300,7 +3244,6 @@ CONFIG_VIDEO_ROCKCHIP_RGA=y CONFIG_VIDEO_HANTRO=y # CONFIG_VIDEO_HANTRO_HEVC_RFC is not set CONFIG_VIDEO_HANTRO_ROCKCHIP=y -CONFIG_VIDEO_HANTRO_SUNXI=y # # VIA media platform drivers @@ -3328,7 +3271,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_GC0308 is not set # CONFIG_VIDEO_GC05A2 is not set # CONFIG_VIDEO_GC08A3 is not set -# CONFIG_VIDEO_GC2145_MIPI is not set +# CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set @@ -3357,6 +3300,8 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_OG01A1B is not set # CONFIG_VIDEO_OV01A10 is not set # CONFIG_VIDEO_OV02A10 is not set +# CONFIG_VIDEO_OV02E10 is not set +# CONFIG_VIDEO_OV02C10 is not set # CONFIG_VIDEO_OV08D10 is not set # CONFIG_VIDEO_OV08X40 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3393,11 +3338,11 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_S5C73M3 is not set # CONFIG_VIDEO_S5K5BAF is not set # CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_VD55G1 is not set +# CONFIG_VIDEO_VD56G3 is not set # CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set -# CONFIG_VIDEO_HM5065 is not set -# CONFIG_VIDEO_GC2145 is not set # # Camera ISPs @@ -3551,8 +3496,15 @@ CONFIG_APERTURE_HELPERS=y CONFIG_VIDEO=y # CONFIG_AUXDISPLAY is not set CONFIG_DRM=y -CONFIG_DRM_MIPI_DSI=y + +# +# DRM debugging options +# +# CONFIG_DRM_WERROR is not set # CONFIG_DRM_DEBUG_MM is not set +# end of DRM debugging options + +CONFIG_DRM_MIPI_DSI=y CONFIG_DRM_KMS_HELPER=y # CONFIG_DRM_PANIC is not set # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set @@ -3583,13 +3535,11 @@ CONFIG_DRM_GEM_SHMEM_HELPER=y CONFIG_DRM_SCHED=y # -# I2C encoder or helper chips +# Drivers for system framebuffers # -# CONFIG_DRM_I2C_CH7006 is not set -# CONFIG_DRM_I2C_SIL164 is not set -# CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_I2C_NXP_TDA9950 is not set -# end of I2C encoder or helper chips +CONFIG_DRM_SYSFB_HELPER=y +CONFIG_DRM_SIMPLEDRM=y +# end of Drivers for system framebuffers # # ARM devices @@ -3622,11 +3572,6 @@ CONFIG_ROCKCHIP_DW_MIPI_DSI=y # CONFIG_DRM_UDL is not set # CONFIG_DRM_AST is not set # CONFIG_DRM_MGAG200 is not set -CONFIG_DRM_SUN4I=y -CONFIG_DRM_SUN6I_DSI=y -CONFIG_DRM_SUN8I_DW_HDMI=y -CONFIG_DRM_SUN8I_MIXER=y -CONFIG_DRM_SUN8I_TCON_TOP=y # CONFIG_DRM_QXL is not set CONFIG_DRM_PANEL=y @@ -3639,6 +3584,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set # CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TD4320 is not set # CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set @@ -3648,6 +3594,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set CONFIG_DRM_PANEL_DSI_CM=m # CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_HIMAX_HX8279 is not set # CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set @@ -3682,6 +3629,7 @@ CONFIG_DRM_PANEL_DSI_CM=m # CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set +# CONFIG_DRM_PANEL_NOVATEK_NT37801 is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set @@ -3690,6 +3638,7 @@ CONFIG_DRM_PANEL_DSI_CM=m # CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67200 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set @@ -3725,16 +3674,20 @@ CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m # CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set # CONFIG_DRM_PANEL_EDP is not set CONFIG_DRM_PANEL_SIMPLE=m +# CONFIG_DRM_PANEL_SUMMIT is not set # CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_G2647FB105 is not set # CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_VISIONOX_RM692E5 is not set # CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set # CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# CONFIG_DRM_PANEL_YIXIAN_YX0345 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # end of Display Panels @@ -3747,6 +3700,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set CONFIG_DRM_DISPLAY_CONNECTOR=y +# CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_ITE_IT6263 is not set # CONFIG_DRM_ITE_IT6505 is not set # CONFIG_DRM_LONTIUM_LT8912B is not set @@ -3797,7 +3751,6 @@ CONFIG_DRM_DW_MIPI_DSI=y # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_PANEL_MIPI_DBI is not set -CONFIG_DRM_SIMPLEDRM=y # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set @@ -3806,17 +3759,17 @@ CONFIG_DRM_SIMPLEDRM=y # CONFIG_TINYDRM_MI0283QT is not set # CONFIG_TINYDRM_REPAPER is not set # CONFIG_TINYDRM_SHARP_MEMORY is not set -# CONFIG_TINYDRM_ST7586 is not set -# CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_PL111 is not set # CONFIG_DRM_LIMA is not set CONFIG_DRM_PANFROST=y # CONFIG_DRM_PANTHOR is not set # CONFIG_DRM_TIDSS is not set # CONFIG_DRM_GUD is not set +# CONFIG_DRM_ST7571_I2C is not set +# CONFIG_DRM_ST7586 is not set +# CONFIG_DRM_ST7735R is not set # CONFIG_DRM_SSD130X is not set # CONFIG_DRM_POWERVR is not set -# CONFIG_DRM_WERROR is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # @@ -3830,7 +3783,6 @@ CONFIG_FB=y # CONFIG_FB_IMSTT is not set # CONFIG_FB_OPENCORES is not set # CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_SUN5I_EINK is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_I740 is not set @@ -3981,7 +3933,6 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_LCPOWER is not set # CONFIG_HID_LED is not set # CONFIG_HID_LETSKETCH is not set -# CONFIG_HID_LOGITECH is not set # CONFIG_HID_MAGICMOUSE is not set # CONFIG_HID_MALTRON is not set # CONFIG_HID_MAYFLASH is not set @@ -4088,6 +4039,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y # CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y +# CONFIG_USB_XHCI_SIDEBAND is not set CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_ROOT_HUB_TT is not set CONFIG_USB_EHCI_TT_NEWSCHED=y @@ -4248,8 +4200,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y # # USB Physical Layer drivers # -CONFIG_USB_PHY=y -CONFIG_NOP_USB_XCEIV=y +# CONFIG_NOP_USB_XCEIV is not set # CONFIG_USB_GPIO_VBUS is not set # CONFIG_USB_ISP1301 is not set # CONFIG_USB_ULPI is not set @@ -4257,7 +4208,7 @@ CONFIG_NOP_USB_XCEIV=y # CONFIG_USB_GADGET is not set # CONFIG_TYPEC is not set -CONFIG_USB_ROLE_SWITCH=y +# CONFIG_USB_ROLE_SWITCH is not set CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=y CONFIG_PWRSEQ_SIMPLE=y @@ -4296,7 +4247,6 @@ CONFIG_MMC_DW_ROCKCHIP=y # CONFIG_MMC_VUB300 is not set # CONFIG_MMC_USHC is not set # CONFIG_MMC_USDHI6ROL0 is not set -CONFIG_MMC_SUNXI=y CONFIG_MMC_CQHCI=y # CONFIG_MMC_HSQ is not set # CONFIG_MMC_TOSHIBA_PCI is not set @@ -4355,7 +4305,6 @@ CONFIG_LEDS_USER=y # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_LM3697 is not set # CONFIG_LEDS_ST1202 is not set -# CONFIG_LEDS_AXP20X is not set # # Flash and Torch LED drivers @@ -4364,7 +4313,6 @@ CONFIG_LEDS_USER=y # # RGB LED drivers # -# CONFIG_LEDS_WS2812 is not set # # LED Triggers @@ -4392,7 +4340,7 @@ CONFIG_LEDS_TRIGGER_NETDEV=y # CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # -# Simple LED drivers +# Simatic LED drivers # # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set @@ -4503,7 +4451,6 @@ CONFIG_RTC_I2C_AND_SPI=y # # CONFIG_RTC_DRV_PL030 is not set # CONFIG_RTC_DRV_PL031 is not set -CONFIG_RTC_DRV_SUN6I=y # CONFIG_RTC_DRV_CADENCE is not set # CONFIG_RTC_DRV_FTRTC010 is not set # CONFIG_RTC_DRV_R7301 is not set @@ -4519,11 +4466,10 @@ CONFIG_DMADEVICES=y # DMA Devices # CONFIG_DMA_ENGINE=y -CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DMA_OF=y # CONFIG_ALTERA_MSGDMA is not set # CONFIG_AMBA_PL08X is not set -CONFIG_DMA_SUN6I=y +# CONFIG_ARM_DMA350 is not set # CONFIG_DW_AXI_DMAC is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_QDMA is not set @@ -4572,67 +4518,12 @@ CONFIG_SYNC_FILE=y # # Microsoft Hyper-V guest support # +# CONFIG_HYPERV is not set # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set # CONFIG_COMEDI is not set -CONFIG_STAGING=y -# CONFIG_RTL8723BS is not set - -# -# IIO staging drivers -# - -# -# Accelerometers -# -# CONFIG_ADIS16203 is not set -# CONFIG_ADIS16240 is not set -# end of Accelerometers - -# -# Analog to digital converters -# -# CONFIG_AD7816 is not set -# end of Analog to digital converters - -# -# Analog digital bi-direction converters -# -# CONFIG_ADT7316 is not set -# end of Analog digital bi-direction converters - -# -# Direct Digital Synthesis -# -# CONFIG_AD9832 is not set -# CONFIG_AD9834 is not set -# end of Direct Digital Synthesis - -# -# Network Analyzer, Impedance Converters -# -# CONFIG_AD5933 is not set -# end of Network Analyzer, Impedance Converters -# end of IIO staging drivers - -# CONFIG_FB_SM750 is not set -CONFIG_STAGING_MEDIA=y -# CONFIG_VIDEO_MAX96712 is not set -# CONFIG_VIDEO_ROCKCHIP_VDEC is not set -CONFIG_VIDEO_ROCKCHIP_VDEC2=y - -# -# StarFive media platform drivers -# -CONFIG_VIDEO_SUNXI=y -CONFIG_VIDEO_SUNXI_CEDRUS=y -# CONFIG_VIDEO_SUN6I_ISP is not set -# CONFIG_STAGING_MEDIA_DEPRECATED is not set -# CONFIG_FB_TFT is not set -# CONFIG_XIL_AXIS_FIFO is not set -# CONFIG_VME_BUS is not set -# CONFIG_GPIB is not set +# CONFIG_STAGING is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set @@ -4677,20 +4568,11 @@ CONFIG_COMMON_CLK_ROCKCHIP=y # CONFIG_CLK_RK3328 is not set # CONFIG_CLK_RK3368 is not set # CONFIG_CLK_RK3399 is not set +CONFIG_CLK_RK3528=y +CONFIG_CLK_RK3562=y CONFIG_CLK_RK3568=y # CONFIG_CLK_RK3576 is not set # CONFIG_CLK_RK3588 is not set -CONFIG_SUNXI_CCU=y -# CONFIG_SUN50I_A64_CCU is not set -# CONFIG_SUN50I_A100_CCU is not set -# CONFIG_SUN50I_A100_R_CCU is not set -# CONFIG_SUN50I_H6_CCU is not set -CONFIG_SUN50I_H616_CCU=y -CONFIG_SUN50I_H6_R_CCU=y -CONFIG_SUN6I_RTC_CCU=y -# CONFIG_SUN8I_H3_CCU is not set -CONFIG_SUN8I_DE2_CCU=y -CONFIG_SUN8I_R_CCU=y # CONFIG_XILINX_VCU is not set # CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set # CONFIG_HWSPINLOCK is not set @@ -4702,14 +4584,12 @@ CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_MMIO=y CONFIG_ROCKCHIP_TIMER=y -CONFIG_SUN4I_TIMER=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y CONFIG_FSL_ERRATUM_A008585=y CONFIG_HISILICON_ERRATUM_161010101=y CONFIG_ARM64_ERRATUM_858921=y -CONFIG_SUN50I_ERRATUM_UNKNOWN1=y # CONFIG_ARM_TIMER_SP804 is not set # end of Clock Source drivers @@ -4722,7 +4602,6 @@ CONFIG_MAILBOX=y CONFIG_ROCKCHIP_MBOX=y # CONFIG_ALTERA_MBOX is not set # CONFIG_MAILBOX_TEST is not set -CONFIG_SUN6I_MSGBOX=y CONFIG_IOMMU_IOVA=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y @@ -4743,11 +4622,10 @@ CONFIG_IOMMU_DEFAULT_DMA_STRICT=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y -# CONFIG_IOMMUFD is not set -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_SUN50I_IOMMU=y # CONFIG_ARM_SMMU is not set # CONFIG_ARM_SMMU_V3 is not set +# CONFIG_IOMMUFD is not set +CONFIG_ROCKCHIP_IOMMU=y # # Remoteproc drivers @@ -4808,8 +4686,6 @@ CONFIG_SUN50I_IOMMU=y CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_SUNXI_MBUS=y -CONFIG_SUNXI_SRAM=y # CONFIG_SOC_TI is not set # @@ -4847,8 +4723,6 @@ CONFIG_ARM_SCPI_POWER_DOMAIN=y # end of Qualcomm PM Domains CONFIG_ROCKCHIP_PM_DOMAINS=y -# CONFIG_SUN20I_PPU is not set -CONFIG_SUN50I_H6_PRCM_PPU=y # end of PM Domains CONFIG_PM_DEVFREQ=y @@ -4865,9 +4739,7 @@ CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # -CONFIG_ARM_RK3328_DMC_DEVFREQ=y # CONFIG_ARM_RK3399_DMC_DEVFREQ is not set -# CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set CONFIG_PM_DEVFREQ_EVENT=y CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y CONFIG_EXTCON=y @@ -4955,12 +4827,15 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # Analog to digital converters # # CONFIG_AD4000 is not set +# CONFIG_AD4030 is not set # CONFIG_AD4130 is not set # CONFIG_AD4695 is not set +# CONFIG_AD4851 is not set # CONFIG_AD7091R5 is not set # CONFIG_AD7091R8 is not set # CONFIG_AD7124 is not set # CONFIG_AD7173 is not set +# CONFIG_AD7191 is not set # CONFIG_AD7192 is not set # CONFIG_AD7266 is not set # CONFIG_AD7280 is not set @@ -4984,8 +4859,6 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD7949 is not set # CONFIG_AD799X is not set # CONFIG_AD9467 is not set -# CONFIG_AXP20X_ADC is not set -# CONFIG_AXP288_ADC is not set # CONFIG_CC10001_ADC is not set # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_GEHC_PMC_ADC is not set @@ -5011,29 +4884,31 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MCP3564 is not set # CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set +# CONFIG_NCT7201 is not set # CONFIG_PAC1921 is not set # CONFIG_PAC1934 is not set +# CONFIG_ROHM_BD79124 is not set CONFIG_ROCKCHIP_SARADC=y # CONFIG_RICHTEK_RTQ6056 is not set # CONFIG_SD_ADC_MODULATOR is not set -CONFIG_SUN20I_GPADC=y # CONFIG_TI_ADC081C is not set # CONFIG_TI_ADC0832 is not set # CONFIG_TI_ADC084S021 is not set -# CONFIG_TI_ADC12138 is not set # CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC12138 is not set # CONFIG_TI_ADC128S052 is not set # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set -# CONFIG_TI_ADS1119 is not set -# CONFIG_TI_ADS7924 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set +# CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set +# CONFIG_TI_ADS131E08 is not set +# CONFIG_TI_ADS7138 is not set +# CONFIG_TI_ADS7924 is not set # CONFIG_TI_ADS7950 is not set # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set -# CONFIG_TI_ADS124S08 is not set -# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_LMP92064 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_TI_TSC2046 is not set @@ -5079,9 +4954,11 @@ CONFIG_SUN20I_GPADC=y # CONFIG_CCS811 is not set # CONFIG_ENS160 is not set # CONFIG_IAQCORE is not set +# CONFIG_MHZ19B is not set # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SCD4X is not set +# CONFIG_SEN0322 is not set # CONFIG_SENSIRION_SGP30 is not set # CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set @@ -5110,6 +4987,7 @@ CONFIG_SUN20I_GPADC=y # # Digital to analog converters # +# CONFIG_AD3530R is not set # CONFIG_AD3552R_HS is not set # CONFIG_AD3552R is not set # CONFIG_AD5064 is not set @@ -5245,6 +5123,7 @@ CONFIG_SUN20I_GPADC=y # CONFIG_ADIS16460 is not set # CONFIG_ADIS16475 is not set # CONFIG_ADIS16480 is not set +# CONFIG_ADIS16550 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set # CONFIG_BMI270_I2C is not set @@ -5270,8 +5149,10 @@ CONFIG_SUN20I_GPADC=y # # CONFIG_ADJD_S311 is not set # CONFIG_ADUX1020 is not set +# CONFIG_AL3000A is not set # CONFIG_AL3010 is not set # CONFIG_AL3320A is not set +# CONFIG_APDS9160 is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9306 is not set # CONFIG_APDS9960 is not set @@ -5344,6 +5225,7 @@ CONFIG_SUN20I_GPADC=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_SI7210 is not set # CONFIG_TI_TMAG5273 is not set # CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors @@ -5479,10 +5361,9 @@ CONFIG_PWM=y # CONFIG_PWM_CLK is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_MC33XS2410 is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_ROCKCHIP=y -# CONFIG_PWM_SUN4I is not set -CONFIG_PWM_SUNXI_ENHANCE=y # CONFIG_PWM_XILINX is not set # @@ -5496,8 +5377,6 @@ CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_IRQ_MSI_LIB=y # CONFIG_AL_FIC is not set -CONFIG_SUN6I_R_INTC=y -CONFIG_SUNXI_NMI_INTC=y # CONFIG_XILINX_INTC is not set CONFIG_PARTITION_PERCPU=y # end of IRQ chip support @@ -5507,8 +5386,7 @@ CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set CONFIG_RESET_SCMI=y -CONFIG_RESET_SIMPLE=y -CONFIG_RESET_SUNXI=y +# CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RESET_TI_TPS380X is not set @@ -5519,10 +5397,6 @@ CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y # CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_PHY_NXP_PTN3222 is not set -CONFIG_PHY_SUN4I_USB=y -CONFIG_PHY_SUN6I_MIPI_DPHY=y -# CONFIG_PHY_SUN9I_USB is not set -# CONFIG_PHY_SUN50I_USB3 is not set # # PHY drivers for Broadcom platforms @@ -5537,7 +5411,6 @@ CONFIG_PHY_SUN6I_MIPI_DPHY=y # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -5550,6 +5423,7 @@ CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y # CONFIG_PHY_ROCKCHIP_PCIE is not set +# CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY is not set # CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX is not set # CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set # CONFIG_PHY_ROCKCHIP_TYPEC is not set @@ -5603,7 +5477,6 @@ CONFIG_NVMEM_LAYOUTS=y # CONFIG_NVMEM_RMEM is not set CONFIG_NVMEM_ROCKCHIP_EFUSE=y CONFIG_NVMEM_ROCKCHIP_OTP=y -CONFIG_NVMEM_SUNXI_SID=y # CONFIG_NVMEM_U_BOOT_ENV is not set # @@ -5754,6 +5627,7 @@ CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y # CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU=y CONFIG_SQUASHFS_XATTR=y +# CONFIG_SQUASHFS_COMP_CACHE_FULL is not set CONFIG_SQUASHFS_ZLIB=y CONFIG_SQUASHFS_LZ4=y CONFIG_SQUASHFS_LZO=y @@ -5770,7 +5644,6 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_PSTORE is not set -# CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y @@ -5834,7 +5707,6 @@ CONFIG_NLS_ASCII=y CONFIG_NLS_UTF8=y # CONFIG_DLM is not set CONFIG_UNICODE=y -# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set CONFIG_IO_WQ=y # end of File systems @@ -5846,10 +5718,9 @@ CONFIG_IO_WQ=y CONFIG_PROC_MEM_ALWAYS_FORCE=y # CONFIG_PROC_MEM_FORCE_PTRACE is not set # CONFIG_PROC_MEM_NO_FORCE is not set +# CONFIG_MSEAL_SYSTEM_MAPPINGS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_HARDENED_USERCOPY is not set -# CONFIG_FORTIFY_SOURCE is not set # CONFIG_STATIC_USERMODEHELPER is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,ipe,bpf" @@ -5874,6 +5745,13 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # CONFIG_ZERO_CALL_USED_REGS is not set # end of Memory initialization +# +# Bounds checking +# +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_HARDENED_USERCOPY is not set +# end of Bounds checking + # # Hardening of kernel data structures # @@ -5901,7 +5779,6 @@ CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_KPP2=y @@ -5909,13 +5786,13 @@ CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_USER is not set -CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_NULL2=m +# CONFIG_CRYPTO_SELFTESTS is not set +# CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_PCRYPT is not set # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_KRB5ENC is not set +# CONFIG_CRYPTO_BENCHMARK is not set CONFIG_CRYPTO_ENGINE=y # end of Crypto core or helper @@ -5941,7 +5818,7 @@ CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SEED is not set @@ -5989,13 +5866,11 @@ CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_POLY1305 is not set # CONFIG_CRYPTO_RMD160 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set -CONFIG_CRYPTO_SM3=y CONFIG_CRYPTO_SM3_GENERIC=y # CONFIG_CRYPTO_STREEBOG is not set # CONFIG_CRYPTO_WP512 is not set @@ -6008,7 +5883,6 @@ CONFIG_CRYPTO_SM3_GENERIC=y # # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_CRC32 is not set -# CONFIG_CRYPTO_CRCT10DIF is not set # end of CRCs (cyclic redundancy checks) # @@ -6042,16 +5916,12 @@ CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y # end of Userspace interface # CONFIG_CRYPTO_NHPOLY1305_NEON is not set -# CONFIG_CRYPTO_CHACHA20_NEON is not set # # Accelerated Cryptographic Algorithms for CPU (arm64) # # CONFIG_CRYPTO_GHASH_ARM64_CE is not set -# CONFIG_CRYPTO_POLY1305_NEON is not set # CONFIG_CRYPTO_SHA1_ARM64_CE is not set -# CONFIG_CRYPTO_SHA256_ARM64 is not set -# CONFIG_CRYPTO_SHA2_ARM64_CE is not set # CONFIG_CRYPTO_SHA512_ARM64 is not set # CONFIG_CRYPTO_SHA512_ARM64_CE is not set # CONFIG_CRYPTO_SHA3_ARM64 is not set @@ -6072,14 +5942,6 @@ CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y # end of Accelerated Cryptographic Algorithms for CPU (arm64) CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_DEV_ALLWINNER=y -# CONFIG_CRYPTO_DEV_SUN4I_SS is not set -CONFIG_CRYPTO_DEV_SUN8I_CE=y -# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set -CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y -CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y -CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y -# CONFIG_CRYPTO_DEV_SUN8I_SS is not set # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_CCP is not set @@ -6092,7 +5954,6 @@ CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y # CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set # CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set # CONFIG_CRYPTO_DEV_QAT_C62XVF is not set -# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set # CONFIG_CRYPTO_DEV_ROCKCHIP is not set CONFIG_CRYPTO_DEV_ROCKCHIP2=y # CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set @@ -6106,6 +5967,7 @@ CONFIG_CRYPTO_DEV_ROCKCHIP2=y # # end of Certificates for signature checking +# CONFIG_CRYPTO_KRB5 is not set CONFIG_BINARY_PRINTF=y # @@ -6134,30 +5996,21 @@ CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_LIB_GF128MUL=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -# CONFIG_CRYPTO_LIB_CHACHA is not set -# CONFIG_CRYPTO_LIB_CURVE25519 is not set -CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -# CONFIG_CRYPTO_LIB_POLY1305 is not set -# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_SHA256=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_SHA256_SIMD=y +CONFIG_CRYPTO_LIB_SHA256_GENERIC=y +CONFIG_CRYPTO_LIB_SM3=y +CONFIG_CRYPTO_SHA256_ARM64=y # end of Crypto library routines -CONFIG_CRC_CCITT=y CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set CONFIG_ARCH_HAS_CRC_T10DIF=y -# CONFIG_CRC64_ROCKSOFT is not set -# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y CONFIG_ARCH_HAS_CRC32=y CONFIG_CRC32_ARCH=y -# CONFIG_CRC64 is not set -# CONFIG_CRC4 is not set -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -# CONFIG_CRC8 is not set CONFIG_CRC_OPTIMIZATIONS=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y # CONFIG_RANDOM32_SELFTEST is not set @@ -6220,6 +6073,7 @@ CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_VDSO_GETRANDOM=y +CONFIG_GENERIC_VDSO_DATA_STORE=y CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y @@ -6318,7 +6172,7 @@ CONFIG_SLUB_DEBUG=y # CONFIG_DEBUG_RODATA_TEST is not set CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set -CONFIG_GENERIC_PTDUMP=y +CONFIG_ARCH_HAS_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set @@ -6328,6 +6182,7 @@ CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_SCHED_STACK_END_CHECK is not set CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VFS is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_VM_PGTABLE is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y @@ -6367,7 +6222,6 @@ CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y # # Scheduler Debugging # -# CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set # end of Scheduler Debugging @@ -6432,6 +6286,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACE_CLOCK=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set @@ -6456,7 +6311,6 @@ CONFIG_STRICT_DEVMEM=y # CONFIG_NOTIFIER_ERROR_INJECTION is not set # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_ARCH_USE_MEMTEST=y @@ -6468,3 +6322,5 @@ CONFIG_ARCH_USE_MEMTEST=y # # end of Rust hacking # end of Kernel hacking + +CONFIG_IO_URING_ZCRX=y diff --git a/config/board/btt_pi2.json b/config/board/btt_pi2.json index 683441a..8d5dc6b 100644 --- a/config/board/btt_pi2.json +++ b/config/board/btt_pi2.json @@ -60,9 +60,9 @@ }, { "parent": "kernel", - "version": "v6.14-rc7", + "version": "v6.16-rc2", "version_type": "tag", - "patch_dir": [ "kernel", "kernel/sunxi-6.14", "kernel/rockchip64-6.14" ], + "patch_dir": [ "kernel", "kernel/rockchip64-6.16" ], "config_def": "printer_defconfig", "target": [ "clean", "Image", "modules", "dtbs", "modules_install" ], "artifacts": diff --git a/files/backups/excl_min.lst b/files/backups/excl_min.lst index 0a55625..6df37ee 100644 --- a/files/backups/excl_min.lst +++ b/files/backups/excl_min.lst @@ -1,12 +1,5 @@ -#home/biqu/* boot/* media/* -usr/lib/python3.13/test* -usr/lib64/perl5* -#usr/src/* var/cache/binpkgs/* var/cache/distfiles/* -#var/cache/edb/* -var/cache/eix/* var/log/*.log -#var/db/repos/* diff --git a/patch/kernel/h616_old b/patch/kernel/h616_old new file mode 100644 index 0000000..363dc54 --- /dev/null +++ b/patch/kernel/h616_old @@ -0,0 +1,78 @@ + ++ ++#H616, SoC-specific ++CONFIG_SUN50I_A64_CCU=n ++CONFIG_SUN50I_A100_CCU=n ++CONFIG_SUN50I_A100_R_CCU=n ++CONFIG_SUN50I_H6_CCU=n ++CONFIG_SUN8I_H3_CCU=n ++CONFIG_ARCH_SUNXI=y ++CONFIG_DWMAC_DWC_QOS_ETH=y ++CONFIG_SUNXI_CCU=y ++CONFIG_NET_VENDOR_ALLWINNER=y ++CONFIG_AC200_PHY=y ++CONFIG_AC200_PHY_SUNXI=y ++CONFIG_PHY_SUN4I_USB=y ++CONFIG_STAGING=y ++CONFIG_STAGING_MEDIA=y ++CONFIG_VIDEO_SUNXI=y ++CONFIG_NOP_USB_XCEIV=y ++CONFIG_MFD_AC200_SUNXI=y ++CONFIG_SUN50I_H616_CCU=y ++CONFIG_SND_SUN4I_CODEC=y ++CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y ++CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y ++CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y ++CONFIG_CRYPTO_DEV_SUN8I_CE=y ++CONFIG_SUN50I_DE2_BUS=y ++CONFIG_SUN8I_DE2_CCU=y ++CONFIG_DRM_SUN8I_MIXER=y ++CONFIG_DMA_SUN6I=y ++CONFIG_DWMAC_SUNXI=y ++CONFIG_DWMAC_SUN8I=y ++CONFIG_MMC_SUNXI=y ++CONFIG_SUN20I_GPADC=y ++CONFIG_DRM_SUN8I_DW_HDMI=y ++CONFIG_I2C_MV64XXX=y ++CONFIG_SUN50I_IOMMU=y ++##CONFIG_IR_SUNXI=y ++CONFIG_KEYBOARD_SUN4I_LRADC=y ++CONFIG_SUNXI_NMI_INTC=y ++CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y ++CONFIG_PINCTRL_SUN50I_H616=y ++CONFIG_SUN50I_H6_PRCM_PPU=y ++CONFIG_PWM_SUNXI_ENHANCE=y ++CONFIG_SUN50I_H6_R_CCU=y ++CONFIG_PINCTRL_SUN50I_H616_R=y ++CONFIG_SUNXI_RSB=y ++CONFIG_SUN6I_RTC_CCU=y ++CONFIG_RTC_DRV_SUN6I=y ++CONFIG_NVMEM_SUNXI_SID=y ++CONFIG_SND_SUN4I_SPDIF=y ++CONFIG_SPI_SUN6I=y ++CONFIG_SUNXI_SYS_INFO=y ++CONFIG_SUNXI_SRAM=y ++CONFIG_SUN8I_THERMAL=y ++CONFIG_VIDEO_SUNXI_CEDRUS=y ++CONFIG_SUNXI_WATCHDOG=y ++CONFIG_DRM_SUN4I=y ++CONFIG_DRM_SUN8I_TCON_TOP=y ++CONFIG_SUNXI_ADDR_MGT=y ++CONFIG_SUNXI_GMAC=y ++##CONFIG_CAN_MCP251X=y ++##CONFIG_FB_TFT_ST7796S=y ++CONFIG_REGULATOR_FAN53555=y ++CONFIG_MFD_AXP20X_I2C=y ++CONFIG_REGULATOR_AXP20X=y ++#minimize ++CONFIG_PINCTRL_SUN8I_H3_R=n ++CONFIG_PINCTRL_SUN50I_A64=n ++CONFIG_PINCTRL_SUN50I_A64_R=n ++CONFIG_PINCTRL_SUN50I_A100=n ++CONFIG_PINCTRL_SUN50I_A100_R=n ++CONFIG_PINCTRL_SUN50I_H5=n ++CONFIG_PINCTRL_SUN50I_H6=n ++CONFIG_PINCTRL_SUN50I_H6_R=n ++#sound ++CONFIG_SND_SOC_SUNXI_AHUB=y ++CONFIG_SND_SOC_SUNXI_AHUB_DAM=y diff --git a/patch/kernel/printer_defconfig_1_plat.patch b/patch/kernel/printer_defconfig_1_plat.patch index 40fbcdc..ed95cac 100644 --- a/patch/kernel/printer_defconfig_1_plat.patch +++ b/patch/kernel/printer_defconfig_1_plat.patch @@ -3,7 +3,7 @@ new file mode 100644 index 000000000000..51de9e95b7d2 --- a/arch/arm64/configs/printer_defconfig +++ b/arch/arm64/configs/printer_defconfig -@@ -0,4 +202,206 @@ +@@ -0,4 +124,128 @@ CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_SPI_NOR=y @@ -14,83 +14,6 @@ index 000000000000..51de9e95b7d2 +CONFIG_DRM_PANFROST=y +CONFIG_STMMAC_PLATFORM=y + -+#H616, SoC-specific -+CONFIG_SUN50I_A64_CCU=n -+CONFIG_SUN50I_A100_CCU=n -+CONFIG_SUN50I_A100_R_CCU=n -+CONFIG_SUN50I_H6_CCU=n -+CONFIG_SUN8I_H3_CCU=n -+CONFIG_ARCH_SUNXI=y -+CONFIG_DWMAC_DWC_QOS_ETH=y -+CONFIG_SUNXI_CCU=y -+CONFIG_NET_VENDOR_ALLWINNER=y -+CONFIG_AC200_PHY=y -+CONFIG_AC200_PHY_SUNXI=y -+CONFIG_PHY_SUN4I_USB=y -+CONFIG_STAGING=y -+CONFIG_STAGING_MEDIA=y -+CONFIG_VIDEO_SUNXI=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_MFD_AC200_SUNXI=y -+CONFIG_SUN50I_H616_CCU=y -+CONFIG_SND_SUN4I_CODEC=y -+CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y -+CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y -+CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y -+CONFIG_CRYPTO_DEV_SUN8I_CE=y -+CONFIG_SUN50I_DE2_BUS=y -+CONFIG_SUN8I_DE2_CCU=y -+CONFIG_DRM_SUN8I_MIXER=y -+CONFIG_DMA_SUN6I=y -+CONFIG_DWMAC_SUNXI=y -+CONFIG_DWMAC_SUN8I=y -+CONFIG_MMC_SUNXI=y -+CONFIG_SUN20I_GPADC=y -+CONFIG_DRM_SUN8I_DW_HDMI=y -+CONFIG_I2C_MV64XXX=y -+CONFIG_SUN50I_IOMMU=y -+##CONFIG_IR_SUNXI=y -+CONFIG_KEYBOARD_SUN4I_LRADC=y -+CONFIG_SUNXI_NMI_INTC=y -+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y -+CONFIG_PINCTRL_SUN50I_H616=y -+CONFIG_SUN50I_H6_PRCM_PPU=y -+CONFIG_PWM_SUNXI_ENHANCE=y -+CONFIG_SUN50I_H6_R_CCU=y -+CONFIG_PINCTRL_SUN50I_H616_R=y -+CONFIG_SUNXI_RSB=y -+CONFIG_SUN6I_RTC_CCU=y -+CONFIG_RTC_DRV_SUN6I=y -+CONFIG_NVMEM_SUNXI_SID=y -+CONFIG_SND_SUN4I_SPDIF=y -+CONFIG_SPI_SUN6I=y -+CONFIG_SUNXI_SYS_INFO=y -+CONFIG_SUNXI_SRAM=y -+CONFIG_SUN8I_THERMAL=y -+CONFIG_VIDEO_SUNXI_CEDRUS=y -+CONFIG_SUNXI_WATCHDOG=y -+CONFIG_DRM_SUN4I=y -+CONFIG_DRM_SUN8I_TCON_TOP=y -+CONFIG_SUNXI_ADDR_MGT=y -+CONFIG_SUNXI_GMAC=y -+##CONFIG_CAN_MCP251X=y -+##CONFIG_FB_TFT_ST7796S=y -+CONFIG_REGULATOR_FAN53555=y -+CONFIG_MFD_AXP20X_I2C=y -+CONFIG_REGULATOR_AXP20X=y -+#minimize -+CONFIG_PINCTRL_SUN8I_H3_R=n -+CONFIG_PINCTRL_SUN50I_A64=n -+CONFIG_PINCTRL_SUN50I_A64_R=n -+CONFIG_PINCTRL_SUN50I_A100=n -+CONFIG_PINCTRL_SUN50I_A100_R=n -+CONFIG_PINCTRL_SUN50I_H5=n -+CONFIG_PINCTRL_SUN50I_H6=n -+CONFIG_PINCTRL_SUN50I_H6_R=n -+#sound -+CONFIG_SND_SOC_SUNXI_AHUB=y -+CONFIG_SND_SOC_SUNXI_AHUB_DAM=y -+ +#rk3566/3568, SoC-specific +CONFIG_CLK_PX30=n +CONFIG_CLK_RK3576=n diff --git a/patch/kernel/printer_edt_ft5x06_noIRQ_support.patch b/patch/kernel/printer_edt_ft5x06_noIRQ_support.patch index aaecf35..6814c34 100644 --- a/patch/kernel/printer_edt_ft5x06_noIRQ_support.patch +++ b/patch/kernel/printer_edt_ft5x06_noIRQ_support.patch @@ -94,7 +94,7 @@ index 0d7bf18e2508..535e84de038e 100644 +static void edt_ft5x06_ts_irq_poll_timer(struct timer_list *t) +{ -+ struct edt_ft5x06_ts_data *tsdata = from_timer(tsdata, t, timer); ++ struct edt_ft5x06_ts_data *tsdata = timer_container_of(tsdata, t, timer); + + schedule_work(&tsdata->work_i2c_poll); + mod_timer(&tsdata->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS)); @@ -153,7 +153,7 @@ index 0d7bf18e2508..535e84de038e 100644 struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client); + if (!client->irq) { -+ del_timer(&tsdata->timer); ++ timer_delete(&tsdata->timer); + cancel_work_sync(&tsdata->work_i2c_poll); + } edt_ft5x06_ts_teardown_debugfs(tsdata); diff --git a/patch/kernel/rockchip64-6.16/general-add-hdmi-mks-ips50-resolutions.patch b/patch/kernel/rockchip64-6.16/general-add-hdmi-mks-ips50-resolutions.patch new file mode 100644 index 0000000..a0339c3 --- /dev/null +++ b/patch/kernel/rockchip64-6.16/general-add-hdmi-mks-ips50-resolutions.patch @@ -0,0 +1,83 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Maxim Medvedev +Date: Mon, 1 Jan 2024 21:50:10 +0000 +Subject: HDMI EDID records for 800x480 resolution (a MKS IPS50 screen and + similar) + +--- + drivers/gpu/drm/drm_edid.c | 12 +++++++++- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 1 + + drivers/video/hdmi.c | 2 ++ + include/linux/hdmi.h | 1 + + 4 files changed, 15 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -1550,6 +1550,16 @@ static const struct drm_display_mode edid_cea_modes_193[] = { + 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, ++ /* 220 - 800x480@60Hz 5:3 */ ++ { DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30240, 800, 850, ++ 920, 960, 0, 480, 510, 513, 525, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), ++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_5_3, }, ++ /* 221 - 800x480@60Hz 5:3, MKS IPS50 */ ++ { DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30240, 800, 850, ++ 950, 960, 0, 480, 510, 513, 525, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), ++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_5_3, }, + }; + + /* +@@ -4215,7 +4225,7 @@ static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) + static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) + { + BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); +- BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); ++ BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 221); + + if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) + return &edid_cea_modes_1[vic - 1]; +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 111111111111..222222222222 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -295,6 +295,7 @@ static const struct pre_pll_config pre_pll_cfg_table[] = { + { 25175000, 31468750, 1, 41, 0, 3, 3, 1, 3, 3, 4, 0, 0xf5554f}, + { 27000000, 27000000, 1, 36, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 27000000, 33750000, 1, 45, 0, 3, 3, 1, 3, 3, 4, 0, 0x0}, ++ { 30240000, 30240000, 5, 504, 3, 2, 2, 20, 4, 2, 2, 0, 0x0}, // Non standard screens like MKS IPS50 + { 31500000, 31500000, 1, 42, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, + { 31500000, 39375000, 1, 105, 1, 3, 3, 10, 0, 3, 4, 0, 0x0}, + { 33750000, 33750000, 1, 45, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, +diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c +index 111111111111..222222222222 100644 +--- a/drivers/video/hdmi.c ++++ b/drivers/video/hdmi.c +@@ -1087,6 +1087,8 @@ hdmi_picture_aspect_get_name(enum hdmi_picture_aspect picture_aspect) + return "64:27"; + case HDMI_PICTURE_ASPECT_256_135: + return "256:135"; ++ case HDMI_PICTURE_ASPECT_5_3: ++ return "5:3"; + case HDMI_PICTURE_ASPECT_RESERVED: + return "Reserved"; + } +diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h +index 111111111111..222222222222 100644 +--- a/include/linux/hdmi.h ++++ b/include/linux/hdmi.h +@@ -108,6 +108,7 @@ enum hdmi_picture_aspect { + HDMI_PICTURE_ASPECT_16_9, + HDMI_PICTURE_ASPECT_64_27, + HDMI_PICTURE_ASPECT_256_135, ++ HDMI_PICTURE_ASPECT_5_3, + HDMI_PICTURE_ASPECT_RESERVED, + }; + +-- +Armbian + diff --git a/patch/kernel/rockchip64-6.16/general-add-miniDP-dt-doc.patch b/patch/kernel/rockchip64-6.16/general-add-miniDP-dt-doc.patch new file mode 100644 index 0000000..4729ab0 --- /dev/null +++ b/patch/kernel/rockchip64-6.16/general-add-miniDP-dt-doc.patch @@ -0,0 +1,133 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tony +Date: Wed, 3 Mar 2021 07:59:25 +0100 +Subject: [ARCHEOLOGY] RK3399 Typec DP (#2676) + +> X-Git-Archeology: > recovered message: > * RK3399 NanoPC-T4 Add Type-C alt mode DP +> X-Git-Archeology: > recovered message: > * rk3399 rockpi 4C add mini-DP (WIP) +> X-Git-Archeology: > recovered message: > * [ rockchip64 ] revert rockPi 4C DP patch +> X-Git-Archeology: > recovered message: > Add an extension to disable it, but leave for future work. +> X-Git-Archeology: - Revision 4971535c774a1f49a811baebc083ea028ced0300: https://github.com/armbian/build/commit/4971535c774a1f49a811baebc083ea028ced0300 +> X-Git-Archeology: Date: Wed, 03 Mar 2021 07:59:25 +0100 +> X-Git-Archeology: From: Tony +> X-Git-Archeology: Subject: RK3399 Typec DP (#2676) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml | 66 ++++++++++ + 1 file changed, 66 insertions(+) + +diff --git a/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml +@@ -0,0 +1,66 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/extcon/extcon-usbc-virtual-pd.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Type-C Virtual PD extcon ++ ++maintainers: ++ - Jagan Teki ++ ++description: | ++ USB Type-C protocol supports various modes of operations includes PD, ++ USB3, and Altmode. If the platform design supports a Type-C connector ++ then configuring these modes can be done via enumeration. ++ ++ However, there are some platforms that design these modes as separate ++ protocol connectors like design Display Port from on-chip USB3 controller. ++ So we can access Type-C Altmode Display Port via onboard Display Port ++ connector instead of a Type-C connector. These kinds of platforms require ++ an explicit extcon driver in order to handle Power Delivery and ++ Port Detection. ++ ++properties: ++ compatible: ++ const: linux,extcon-usbc-virtual-pd ++ ++ det-gpios: ++ description: Detect GPIO pin. Pin can be Display Port Detect or USB ID. ++ maxItems: 1 ++ ++ vpd-polarity: ++ description: USB Type-C Polarity. false for Normal and true for Flip. ++ type: boolean ++ ++ vpd-super-speed: ++ description: USB Super Speed. false for USB2 and true for USB3. ++ type: boolean ++ ++ vpd-data-role: ++ description: USB Data roles for Virtual Type-C. ++ $ref: /schemas/types.yaml#definitions/string ++ ++ enum: ++ - host ++ - device ++ - display-port ++ ++required: ++ - compatible ++ - det-gpios ++ - vpd-data-role ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ virtual_pd: virtual-pd { ++ compatible = "linux,extcon-usbc-virtual-pd"; ++ det-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; ++ vpd-data-role = "display-port"; ++ vpd-super-speed; ++ }; +-- +Armbian + diff --git a/patch/kernel/rockchip64-6.16/general-add-miniDP-virtual-extcon.patch b/patch/kernel/rockchip64-6.16/general-add-miniDP-virtual-extcon.patch new file mode 100644 index 0000000..6fb6ea1 --- /dev/null +++ b/patch/kernel/rockchip64-6.16/general-add-miniDP-virtual-extcon.patch @@ -0,0 +1,382 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tony +Date: Wed, 3 Mar 2021 07:59:25 +0100 +Subject: [ARCHEOLOGY] RK3399 Typec DP (#2676) + +> X-Git-Archeology: > recovered message: > * RK3399 NanoPC-T4 Add Type-C alt mode DP +> X-Git-Archeology: > recovered message: > * rk3399 rockpi 4C add mini-DP (WIP) +> X-Git-Archeology: > recovered message: > * [ rockchip64 ] revert rockPi 4C DP patch +> X-Git-Archeology: > recovered message: > Add an extension to disable it, but leave for future work. +> X-Git-Archeology: - Revision 4971535c774a1f49a811baebc083ea028ced0300: https://github.com/armbian/build/commit/4971535c774a1f49a811baebc083ea028ced0300 +> X-Git-Archeology: Date: Wed, 03 Mar 2021 07:59:25 +0100 +> X-Git-Archeology: From: Tony +> X-Git-Archeology: Subject: RK3399 Typec DP (#2676) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + drivers/extcon/Kconfig | 10 + + drivers/extcon/Makefile | 1 + + drivers/extcon/extcon-usbc-virtual-pd.c | 285 ++++++++++ + 3 files changed, 296 insertions(+) + +diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig +index 111111111111..222222222222 100644 +--- a/drivers/extcon/Kconfig ++++ b/drivers/extcon/Kconfig +@@ -214,4 +214,14 @@ config EXTCON_RTK_TYPE_C + The DHC (Digital Home Hub) RTD series SoC contains a type c module. + This driver will detect the status of the type-c port. + ++config EXTCON_USBC_VIRTUAL_PD ++ tristate "Virtual Type-C PD EXTCON support" ++ depends on GPIOLIB || COMPILE_TEST ++ help ++ Say Y here to enable Virtual Type-C PD extcon driver support, if ++ hardware platform designed Type-C modes separately. ++ ++ Example, of designing Display Port separately from Type-C Altmode ++ instead of accessing Altmode Display Port in Type-C connector. ++ + endif +diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/extcon/Makefile ++++ b/drivers/extcon/Makefile +@@ -27,3 +27,4 @@ obj-$(CONFIG_EXTCON_USB_GPIO) += extcon-usb-gpio.o + obj-$(CONFIG_EXTCON_USBC_CROS_EC) += extcon-usbc-cros-ec.o + obj-$(CONFIG_EXTCON_USBC_TUSB320) += extcon-usbc-tusb320.o + obj-$(CONFIG_EXTCON_RTK_TYPE_C) += extcon-rtk-type-c.o ++obj-$(CONFIG_EXTCON_USBC_VIRTUAL_PD) += extcon-usbc-virtual-pd.o +diff --git a/drivers/extcon/extcon-usbc-virtual-pd.c b/drivers/extcon/extcon-usbc-virtual-pd.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/extcon/extcon-usbc-virtual-pd.c +@@ -0,0 +1,285 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Type-C Virtual PD Extcon driver ++ * ++ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (c) 2019 Radxa Limited ++ * Copyright (c) 2019 Amarula Solutions(India) ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const unsigned int vpd_cable[] = { ++ EXTCON_USB, ++ EXTCON_USB_HOST, ++ EXTCON_DISP_DP, ++ EXTCON_NONE, ++}; ++ ++enum vpd_data_role { ++ DR_NONE, ++ DR_HOST, ++ DR_DEVICE, ++ DR_DISPLAY_PORT, ++}; ++ ++enum vpd_polarity { ++ POLARITY_NORMAL, ++ POLARITY_FLIP, ++}; ++ ++enum vpd_usb_ss { ++ USB_SS_USB2, ++ USB_SS_USB3, ++}; ++ ++struct vpd_extcon { ++ struct device *dev; ++ struct extcon_dev *extcon; ++ struct gpio_desc *det_gpio; ++ ++ u8 polarity; ++ u8 usb_ss; ++ enum vpd_data_role data_role; ++ ++ int irq; ++ bool enable_irq; ++ struct work_struct work; ++ struct delayed_work irq_work; ++}; ++ ++static void vpd_extcon_irq_work(struct work_struct *work) ++{ ++ struct vpd_extcon *vpd = container_of(work, struct vpd_extcon, irq_work.work); ++ bool host_connected = false, device_connected = false, dp_connected = false; ++ union extcon_property_value property; ++ int det; ++ ++ det = vpd->det_gpio ? gpiod_get_raw_value(vpd->det_gpio) : 0; ++ if (det) { ++ device_connected = (vpd->data_role == DR_DEVICE) ? true : false; ++ host_connected = (vpd->data_role == DR_HOST) ? true : false; ++ dp_connected = (vpd->data_role == DR_DISPLAY_PORT) ? true : false; ++ } ++ ++ extcon_set_state(vpd->extcon, EXTCON_USB, host_connected); ++ extcon_set_state(vpd->extcon, EXTCON_USB_HOST, device_connected); ++ extcon_set_state(vpd->extcon, EXTCON_DISP_DP, dp_connected); ++ ++ property.intval = vpd->polarity; ++ extcon_set_property(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ extcon_set_property(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ extcon_set_property(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ ++ property.intval = vpd->usb_ss; ++ extcon_set_property(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_SS, property); ++ extcon_set_property(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_SS, property); ++ extcon_set_property(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_SS, property); ++ ++ extcon_sync(vpd->extcon, EXTCON_USB); ++ extcon_sync(vpd->extcon, EXTCON_USB_HOST); ++ extcon_sync(vpd->extcon, EXTCON_DISP_DP); ++} ++ ++static irqreturn_t vpd_extcon_irq_handler(int irq, void *dev_id) ++{ ++ struct vpd_extcon *vpd = dev_id; ++ ++ schedule_delayed_work(&vpd->irq_work, msecs_to_jiffies(10)); ++ ++ return IRQ_HANDLED; ++} ++ ++static enum vpd_data_role vpd_extcon_data_role(struct vpd_extcon *vpd) ++{ ++ const char *const data_roles[] = { ++ [DR_NONE] = "NONE", ++ [DR_HOST] = "host", ++ [DR_DEVICE] = "device", ++ [DR_DISPLAY_PORT] = "display-port", ++ }; ++ struct device *dev = vpd->dev; ++ int ret; ++ const char *dr; ++ ++ ret = device_property_read_string(dev, "vpd-data-role", &dr); ++ if (ret < 0) ++ return DR_NONE; ++ ++ ret = match_string(data_roles, ARRAY_SIZE(data_roles), dr); ++ ++ return (ret < 0) ? DR_NONE : ret; ++} ++ ++static int vpd_extcon_parse_dts(struct vpd_extcon *vpd) ++{ ++ struct device *dev = vpd->dev; ++ bool val = false; ++ int ret; ++ ++ val = device_property_read_bool(dev, "vpd-polarity"); ++ if (val) ++ vpd->polarity = POLARITY_FLIP; ++ else ++ vpd->polarity = POLARITY_NORMAL; ++ ++ val = device_property_read_bool(dev, "vpd-super-speed"); ++ if (val) ++ vpd->usb_ss = USB_SS_USB3; ++ else ++ vpd->usb_ss = USB_SS_USB2; ++ ++ vpd->data_role = vpd_extcon_data_role(vpd); ++ ++ vpd->det_gpio = devm_gpiod_get_optional(dev, "det", GPIOD_ASIS); ++ if (IS_ERR(vpd->det_gpio)) { ++ ret = PTR_ERR(vpd->det_gpio); ++ dev_warn(dev, "failed to get det gpio: %d\n", ret); ++ return ret; ++ } ++ ++ vpd->irq = gpiod_to_irq(vpd->det_gpio); ++ if (vpd->irq < 0) { ++ dev_err(dev, "failed to get irq for gpio: %d\n", vpd->irq); ++ return vpd->irq; ++ } ++ ++ ret = devm_request_threaded_irq(dev, vpd->irq, NULL, ++ vpd_extcon_irq_handler, ++ IRQF_TRIGGER_FALLING | ++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, ++ NULL, vpd); ++ if (ret) ++ dev_err(dev, "failed to request gpio irq\n"); ++ ++ return ret; ++} ++ ++static int vpd_extcon_probe(struct platform_device *pdev) ++{ ++ struct vpd_extcon *vpd; ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ vpd = devm_kzalloc(dev, sizeof(*vpd), GFP_KERNEL); ++ if (!vpd) ++ return -ENOMEM; ++ ++ vpd->dev = dev; ++ ret = vpd_extcon_parse_dts(vpd); ++ if (ret) ++ return ret; ++ ++ INIT_DELAYED_WORK(&vpd->irq_work, vpd_extcon_irq_work); ++ ++ vpd->extcon = devm_extcon_dev_allocate(dev, vpd_cable); ++ if (IS_ERR(vpd->extcon)) { ++ dev_err(dev, "allocat extcon failed\n"); ++ return PTR_ERR(vpd->extcon); ++ } ++ ++ ret = devm_extcon_dev_register(dev, vpd->extcon); ++ if (ret) { ++ dev_err(dev, "register extcon failed: %d\n", ret); ++ return ret; ++ } ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_VBUS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_VBUS); ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_SS); ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ ++ platform_set_drvdata(pdev, vpd); ++ ++ vpd_extcon_irq_work(&vpd->irq_work.work); ++ ++ return 0; ++} ++ ++static void vpd_extcon_remove(struct platform_device *pdev) ++{ ++ struct vpd_extcon *vpd = platform_get_drvdata(pdev); ++ ++ cancel_delayed_work_sync(&vpd->irq_work); ++ ++ return; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int vpd_extcon_suspend(struct device *dev) ++{ ++ struct vpd_extcon *vpd = dev_get_drvdata(dev); ++ ++ if (!vpd->enable_irq) { ++ disable_irq_nosync(vpd->irq); ++ vpd->enable_irq = true; ++ } ++ ++ return 0; ++} ++ ++static int vpd_extcon_resume(struct device *dev) ++{ ++ struct vpd_extcon *vpd = dev_get_drvdata(dev); ++ ++ if (vpd->enable_irq) { ++ enable_irq(vpd->irq); ++ vpd->enable_irq = false; ++ } ++ ++ return 0; ++} ++#endif ++ ++static SIMPLE_DEV_PM_OPS(vpd_extcon_pm_ops, ++ vpd_extcon_suspend, vpd_extcon_resume); ++ ++static const struct of_device_id vpd_extcon_dt_match[] = { ++ { .compatible = "linux,extcon-usbc-virtual-pd", }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver vpd_extcon_driver = { ++ .probe = vpd_extcon_probe, ++ .remove = vpd_extcon_remove, ++ .driver = { ++ .name = "extcon-usbc-virtual-pd", ++ .pm = &vpd_extcon_pm_ops, ++ .of_match_table = vpd_extcon_dt_match, ++ }, ++}; ++ ++module_platform_driver(vpd_extcon_driver); ++ ++MODULE_AUTHOR("Jagan Teki "); ++MODULE_DESCRIPTION("Type-C Virtual PD extcon driver"); ++MODULE_LICENSE("GPL v2"); +-- +Armbian + diff --git a/patch/kernel/rockchip64-6.16/general-add-overlay-compilation-support.patch b/patch/kernel/rockchip64-6.16/general-add-overlay-compilation-support.patch new file mode 100644 index 0000000..267fd37 --- /dev/null +++ b/patch/kernel/rockchip64-6.16/general-add-overlay-compilation-support.patch @@ -0,0 +1,66 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Wed, 2 Oct 2024 19:30:34 +0300 +Subject: compile .scr and install overlays in right path + +--- + scripts/Makefile.dtbinst | 13 +++++++++- + scripts/Makefile.dtbs | 8 +++++- + 2 files changed, 19 insertions(+), 2 deletions(-) + +diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst +index 111111111111..222222222222 100644 +--- a/scripts/Makefile.dtbinst ++++ b/scripts/Makefile.dtbinst +@@ -33,7 +33,18 @@ endef + + $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d)))) + +-dtbs := $(notdir $(dtbs)) ++# Very convoluted way to flatten all the device tree ++# directories, but keep the "/overlay/" directory ++ ++# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip) ++topmost_dir = $(firstword $(subst /, ,$(dtbs))) ++# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir" ++dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs))) ++# collect the non-overlay dtbs ++dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs)) ++# compose the dtbs variable flattening all the non-overlays entries ++# and appending the overlays entries ++dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays) + + endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL + +diff --git a/scripts/Makefile.dtbs b/scripts/Makefile.dtbs +index 111111111111..222222222222 100644 +--- a/scripts/Makefile.dtbs ++++ b/scripts/Makefile.dtbs +@@ -122,17 +122,23 @@ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + quiet_cmd_dtc = DTC $(quiet_dtb_check_tag) $@ + cmd_dtc = \ + $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ +- $(DTC) -o $@ -b 0 $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) \ ++ $(DTC) -@ -o $@ -b 0 $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) \ + $(DTC_FLAGS) -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) \ + $(cmd_dtb_check) + ++quiet_cmd_scr = MKIMAGE $@ ++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ ++ + $(obj)/%.dtb: $(obj)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(call if_changed_dep,dtc) + + $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE + $(call if_changed_dep,dtc) + ++$(obj)/%.scr: $(src)/%.scr-cmd FORCE ++ $(call if_changed,scr) ++ + # targets + # --------------------------------------------------------------------------- + +-- +Armbian + diff --git a/patch/kernel/rockchip64-6.16/general-add-overlay-configfs.patch b/patch/kernel/rockchip64-6.16/general-add-overlay-configfs.patch new file mode 100644 index 0000000..3f75a5c --- /dev/null +++ b/patch/kernel/rockchip64-6.16/general-add-overlay-configfs.patch @@ -0,0 +1,419 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Pantelis Antoniou +Date: Wed, 3 Dec 2014 13:23:28 +0200 +Subject: OF: DT-Overlay configfs interface + +This is a port of Pantelis Antoniou's v3 port that makes use of the +new upstreamed configfs support for binary attributes. + +Original commit message: + +Add a runtime interface to using configfs for generic device tree overlay +usage. With it its possible to use device tree overlays without having +to use a per-platform overlay manager. + +Please see Documentation/devicetree/configfs-overlays.txt for more info. + +Changes since v2: +- Removed ifdef CONFIG_OF_OVERLAY (since for now it's required) +- Created a documentation entry +- Slight rewording in Kconfig + +Changes since v1: +- of_resolve() -> of_resolve_phandles(). + +Originally-signed-off-by: Pantelis Antoniou +Signed-off-by: Phil Elwell + +DT configfs: Fix build errors on other platforms + +Signed-off-by: Phil Elwell + +DT configfs: fix build error + +There is an error when compiling rpi-4.6.y branch: + CC drivers/of/configfs.o +drivers/of/configfs.c:291:21: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types] + .default_groups = of_cfs_def_groups, + ^ +drivers/of/configfs.c:291:21: note: (near initialization for 'of_cfs_subsys.su_group.default_groups.next') + +The .default_groups is linked list since commit +1ae1602de028acaa42a0f6ff18d19756f8e825c6. +This commit uses configfs_add_default_group to fix this problem. + +Signed-off-by: Slawomir Stepien + +configfs: New of_overlay API + +of: configfs: Use of_overlay_fdt_apply API call + +The published API to the dynamic overlay application mechanism now +takes a Flattened Device Tree blob as input so that it can manage the +lifetime of the unflattened tree. Conveniently, the new API call - +of_overlay_fdt_apply - is virtually a drop-in replacement for +create_overlay, which can now be deleted. + +Signed-off-by: Phil Elwell +--- + Documentation/devicetree/configfs-overlays.txt | 31 ++ + drivers/of/Kconfig | 11 + + drivers/of/Makefile | 1 + + drivers/of/configfs.c | 277 ++++++++++ + 4 files changed, 320 insertions(+) + +diff --git a/Documentation/devicetree/configfs-overlays.txt b/Documentation/devicetree/configfs-overlays.txt +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/Documentation/devicetree/configfs-overlays.txt +@@ -0,0 +1,31 @@ ++Howto use the configfs overlay interface. ++ ++A device-tree configfs entry is created in /config/device-tree/overlays ++and and it is manipulated using standard file system I/O. ++Note that this is a debug level interface, for use by developers and ++not necessarily something accessed by normal users due to the ++security implications of having direct access to the kernel's device tree. ++ ++* To create an overlay you mkdir the directory: ++ ++ # mkdir /config/device-tree/overlays/foo ++ ++* Either you echo the overlay firmware file to the path property file. ++ ++ # echo foo.dtbo >/config/device-tree/overlays/foo/path ++ ++* Or you cat the contents of the overlay to the dtbo file ++ ++ # cat foo.dtbo >/config/device-tree/overlays/foo/dtbo ++ ++The overlay file will be applied, and devices will be created/destroyed ++as required. ++ ++To remove it simply rmdir the directory. ++ ++ # rmdir /config/device-tree/overlays/foo ++ ++The rationalle of the dual interface (firmware & direct copy) is that each is ++better suited to different use patterns. The firmware interface is what's ++intended to be used by hardware managers in the kernel, while the copy interface ++make sense for developers (since it avoids problems with namespaces). +diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig +index 111111111111..222222222222 100644 +--- a/drivers/of/Kconfig ++++ b/drivers/of/Kconfig +@@ -126,4 +126,15 @@ config OF_OVERLAY_KUNIT_TEST + config OF_NUMA + bool + ++config OF_DMA_DEFAULT_COHERENT ++ # arches should select this if DMA is coherent by default for OF devices ++ bool ++ ++config OF_CONFIGFS ++ bool "Device Tree Overlay ConfigFS interface" ++ select CONFIGFS_FS ++ select OF_OVERLAY ++ help ++ Enable a simple user-space driven DT overlay interface. ++ + endif # OF +diff --git a/drivers/of/Makefile b/drivers/of/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/of/Makefile ++++ b/drivers/of/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-y = base.o cpu.o device.o module.o platform.o property.o + obj-$(CONFIG_OF_KOBJ) += kobj.o ++obj-$(CONFIG_OF_CONFIGFS) += configfs.o + obj-$(CONFIG_OF_DYNAMIC) += dynamic.o + obj-$(CONFIG_OF_FLATTREE) += fdt.o empty_root.dtb.o + obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o +diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/of/configfs.c +@@ -0,0 +1,277 @@ ++/* ++ * Configfs entries for device-tree ++ * ++ * Copyright (C) 2013 - Pantelis Antoniou ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "of_private.h" ++ ++struct cfs_overlay_item { ++ struct config_item item; ++ ++ char path[PATH_MAX]; ++ ++ const struct firmware *fw; ++ struct device_node *overlay; ++ int ov_id; ++ ++ void *dtbo; ++ int dtbo_size; ++}; ++ ++static inline struct cfs_overlay_item *to_cfs_overlay_item( ++ struct config_item *item) ++{ ++ return item ? container_of(item, struct cfs_overlay_item, item) : NULL; ++} ++ ++static ssize_t cfs_overlay_item_path_show(struct config_item *item, ++ char *page) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ return sprintf(page, "%s\n", overlay->path); ++} ++ ++static ssize_t cfs_overlay_item_path_store(struct config_item *item, ++ const char *page, size_t count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ const char *p = page; ++ char *s; ++ int err; ++ ++ /* if it's set do not allow changes */ ++ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) ++ return -EPERM; ++ ++ /* copy to path buffer (and make sure it's always zero terminated */ ++ count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p); ++ overlay->path[sizeof(overlay->path) - 1] = '\0'; ++ ++ /* strip trailing newlines */ ++ s = overlay->path + strlen(overlay->path); ++ while (s > overlay->path && *--s == '\n') ++ *s = '\0'; ++ ++ pr_debug("%s: path is '%s'\n", __func__, overlay->path); ++ ++ err = request_firmware(&overlay->fw, overlay->path, NULL); ++ if (err != 0) ++ goto out_err; ++ ++ err = of_overlay_fdt_apply((void *)overlay->fw->data, ++ (u32)overlay->fw->size, &overlay->ov_id, NULL); ++ if (err != 0) ++ goto out_err; ++ ++ return count; ++ ++out_err: ++ ++ release_firmware(overlay->fw); ++ overlay->fw = NULL; ++ ++ overlay->path[0] = '\0'; ++ return err; ++} ++ ++static ssize_t cfs_overlay_item_status_show(struct config_item *item, ++ char *page) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ return sprintf(page, "%s\n", ++ overlay->ov_id > 0 ? "applied" : "unapplied"); ++} ++ ++CONFIGFS_ATTR(cfs_overlay_item_, path); ++CONFIGFS_ATTR_RO(cfs_overlay_item_, status); ++ ++static struct configfs_attribute *cfs_overlay_attrs[] = { ++ &cfs_overlay_item_attr_path, ++ &cfs_overlay_item_attr_status, ++ NULL, ++}; ++ ++ssize_t cfs_overlay_item_dtbo_read(struct config_item *item, ++ void *buf, size_t max_count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ pr_debug("%s: buf=%p max_count=%zu\n", __func__, ++ buf, max_count); ++ ++ if (overlay->dtbo == NULL) ++ return 0; ++ ++ /* copy if buffer provided */ ++ if (buf != NULL) { ++ /* the buffer must be large enough */ ++ if (overlay->dtbo_size > max_count) ++ return -ENOSPC; ++ ++ memcpy(buf, overlay->dtbo, overlay->dtbo_size); ++ } ++ ++ return overlay->dtbo_size; ++} ++ ++ssize_t cfs_overlay_item_dtbo_write(struct config_item *item, ++ const void *buf, size_t count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ int err; ++ ++ /* if it's set do not allow changes */ ++ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) ++ return -EPERM; ++ ++ /* copy the contents */ ++ overlay->dtbo = kmemdup(buf, count, GFP_KERNEL); ++ if (overlay->dtbo == NULL) ++ return -ENOMEM; ++ ++ overlay->dtbo_size = count; ++ ++ err = of_overlay_fdt_apply(overlay->dtbo, overlay->dtbo_size, ++ &overlay->ov_id, NULL); ++ if (err != 0) ++ goto out_err; ++ ++ return count; ++ ++out_err: ++ kfree(overlay->dtbo); ++ overlay->dtbo = NULL; ++ overlay->dtbo_size = 0; ++ overlay->ov_id = 0; ++ ++ return err; ++} ++ ++CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M); ++ ++static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = { ++ &cfs_overlay_item_attr_dtbo, ++ NULL, ++}; ++ ++static void cfs_overlay_release(struct config_item *item) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ if (overlay->ov_id > 0) ++ of_overlay_remove(&overlay->ov_id); ++ if (overlay->fw) ++ release_firmware(overlay->fw); ++ /* kfree with NULL is safe */ ++ kfree(overlay->dtbo); ++ kfree(overlay); ++} ++ ++static struct configfs_item_operations cfs_overlay_item_ops = { ++ .release = cfs_overlay_release, ++}; ++ ++static struct config_item_type cfs_overlay_type = { ++ .ct_item_ops = &cfs_overlay_item_ops, ++ .ct_attrs = cfs_overlay_attrs, ++ .ct_bin_attrs = cfs_overlay_bin_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_item *cfs_overlay_group_make_item( ++ struct config_group *group, const char *name) ++{ ++ struct cfs_overlay_item *overlay; ++ ++ overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); ++ if (!overlay) ++ return ERR_PTR(-ENOMEM); ++ ++ config_item_init_type_name(&overlay->item, name, &cfs_overlay_type); ++ return &overlay->item; ++} ++ ++static void cfs_overlay_group_drop_item(struct config_group *group, ++ struct config_item *item) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ config_item_put(&overlay->item); ++} ++ ++static struct configfs_group_operations overlays_ops = { ++ .make_item = cfs_overlay_group_make_item, ++ .drop_item = cfs_overlay_group_drop_item, ++}; ++ ++static struct config_item_type overlays_type = { ++ .ct_group_ops = &overlays_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct configfs_group_operations of_cfs_ops = { ++ /* empty - we don't allow anything to be created */ ++}; ++ ++static struct config_item_type of_cfs_type = { ++ .ct_group_ops = &of_cfs_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++struct config_group of_cfs_overlay_group; ++ ++static struct configfs_subsystem of_cfs_subsys = { ++ .su_group = { ++ .cg_item = { ++ .ci_namebuf = "device-tree", ++ .ci_type = &of_cfs_type, ++ }, ++ }, ++ .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex), ++}; ++ ++static int __init of_cfs_init(void) ++{ ++ int ret; ++ ++ pr_info("%s\n", __func__); ++ ++ config_group_init(&of_cfs_subsys.su_group); ++ config_group_init_type_name(&of_cfs_overlay_group, "overlays", ++ &overlays_type); ++ configfs_add_default_group(&of_cfs_overlay_group, ++ &of_cfs_subsys.su_group); ++ ++ ret = configfs_register_subsystem(&of_cfs_subsys); ++ if (ret != 0) { ++ pr_err("%s: failed to register subsys\n", __func__); ++ goto out; ++ } ++ pr_info("%s: OK\n", __func__); ++out: ++ return ret; ++} ++late_initcall(of_cfs_init); +-- +Armbian + diff --git a/patch/kernel/rockchip64-6.16/general-add-panel-simple-dsi.patch b/patch/kernel/rockchip64-6.16/general-add-panel-simple-dsi.patch new file mode 100644 index 0000000..c048e45 --- /dev/null +++ b/patch/kernel/rockchip64-6.16/general-add-panel-simple-dsi.patch @@ -0,0 +1,856 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: simple <991605149@qq.com> +Date: Sun, 12 Sep 2021 20:06:02 +0200 +Subject: [ARCHEOLOGY] general add panel simple dsi (#3140) + +> X-Git-Archeology: > recovered message: > * Backporting patch to 5.10 kernel makes sense. Lets do it. +> X-Git-Archeology: > recovered message: > Co-authored-by: iamdrq +> X-Git-Archeology: > recovered message: > Co-authored-by: Igor Pecovnik +> X-Git-Archeology: - Revision 15819f00e21238e36ca70f6d8445efd6157fbe66: https://github.com/armbian/build/commit/15819f00e21238e36ca70f6d8445efd6157fbe66 +> X-Git-Archeology: Date: Sun, 12 Sep 2021 20:06:02 +0200 +> X-Git-Archeology: From: simple <991605149@qq.com> +> X-Git-Archeology: Subject: general add panel simple dsi (#3140) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4 +> X-Git-Archeology: Date: Tue, 11 Jan 2022 15:26:11 +0100 +> X-Git-Archeology: From: Oleg +> X-Git-Archeology: Subject: move kernel edge to 5.16 (#3387) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 3b78b57fe367e60ad874d9e16ff1cd67957f8382: https://github.com/armbian/build/commit/3b78b57fe367e60ad874d9e16ff1cd67957f8382 +> X-Git-Archeology: Date: Sat, 24 Dec 2022 09:43:51 +0100 +> X-Git-Archeology: From: simple <991605149@qq.com> +> X-Git-Archeology: Subject: Fix general-add-panel-simple-dsi.patch on linux6.1 (#4607) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + drivers/gpu/drm/panel/Makefile | 1 + + drivers/gpu/drm/panel/panel-simple-dsi.c | 772 ++++++++++ + 2 files changed, 773 insertions(+) + +diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/panel/Makefile ++++ b/drivers/gpu/drm/panel/Makefile +@@ -12,6 +12,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o + obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o + obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o + obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o ++obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple-dsi.o + obj-$(CONFIG_DRM_PANEL_EDP) += panel-edp.o + obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) += panel-ebbg-ft8719.o + obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o +diff --git a/drivers/gpu/drm/panel/panel-simple-dsi.c b/drivers/gpu/drm/panel/panel-simple-dsi.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/gpu/drm/panel/panel-simple-dsi.c +@@ -0,0 +1,772 @@ ++/* ++ * Copyright (C) 2021 ++ * This simple dsi driver porting from rock-chip panel-simple.c on linux-4.4 ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include