diff --git a/cfg/btt_pi2/uboot b/cfg/btt_pi2/uboot index 06de31c..372f6df 100644 --- a/cfg/btt_pi2/uboot +++ b/cfg/btt_pi2/uboot @@ -1,10 +1,10 @@ # # Automatically generated file; DO NOT EDIT. -# U-Boot 2025.07-rc5 Configuration +# U-Boot 2025.10-rc2 Configuration # # -# Compiler: aarch64-linux-gnu-gcc (Gentoo 15.1.0 p1) 15.1.0 +# Compiler: aarch64-linux-gnu-gcc (Gentoo 15.1.1_p20250705-r1 p2) 15.1.1 20250705 # CONFIG_CREATE_ARCH_SYMLINK=y CONFIG_HAVE_SETJMP=y @@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_SHIFT_6=y CONFIG_64BIT=y CONFIG_SPL_64BIT=y CONFIG_SYS_CACHELINE_SIZE=64 +CONFIG_SYS_DTC_PAD_BYTES=4096 CONFIG_LINKER_LIST_ALIGN=8 # CONFIG_ARC is not set CONFIG_ARM=y @@ -56,6 +57,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 # CONFIG_POSITION_INDEPENDENT is not set # CONFIG_INIT_SP_RELATIVE is not set CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE=0x00a00000 +# CONFIG_KVM_VIRT_INS is not set # CONFIG_DRIVER_GICV2 is not set # CONFIG_GIC_V3_ITS is not set # CONFIG_GICV3_SUPPORT_GIC600 is not set @@ -113,7 +115,6 @@ CONFIG_ARM64_SUPPORT_AARCH32=y # CONFIG_ARCH_IMXRT is not set # CONFIG_ARCH_MX23 is not set # CONFIG_ARCH_MX28 is not set -# CONFIG_ARCH_MX31 is not set # CONFIG_ARCH_MX7ULP is not set # CONFIG_ARCH_MX7 is not set # CONFIG_ARCH_MX6 is not set @@ -322,11 +323,12 @@ CONFIG_SYS_LITTLE_ENDIAN=y # # General setup # +# CONFIG_COMPILE_TEST is not set # CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=150100 +CONFIG_GCC_VERSION=150101 CONFIG_CLANG_VERSION=0 CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_CC_OPTIMIZE_FOR_SPEED is not set @@ -376,6 +378,7 @@ CONFIG_SYS_UBOOT_START=0x00a00000 # Boot images # # CONFIG_ANDROID_BOOT_IMAGE is not set +# CONFIG_ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR is not set # CONFIG_TIMESTAMP is not set CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x0 @@ -420,6 +423,7 @@ CONFIG_BOOTMETH_VBE_SIMPLE=y # CONFIG_BOOTMETH_VBE_ABREC is not set CONFIG_BOOTMETH_VBE_SIMPLE_OS=y # CONFIG_SPL_BOOTMETH_VBE_SIMPLE is not set +# CONFIG_BOOTMETH_RAUC is not set CONFIG_BOOTMETH_SCRIPT=y # CONFIG_UPL is not set CONFIG_LEGACY_IMAGE_FORMAT=y @@ -466,6 +470,7 @@ CONFIG_BOOTDELAY=2 # # CONFIG_OF_ENV_SETUP is not set # CONFIG_OF_BOARD_SETUP is not set +# CONFIG_OF_BOARD_SETUP_EXTENDED is not set # CONFIG_OF_SYSTEM_SETUP is not set # CONFIG_OF_STDOUT_VIA_ALIAS is not set # CONFIG_FDT_FIXUP_PARTITIONS is not set @@ -526,9 +531,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_CYCLIC is not set CONFIG_EVENT=y # CONFIG_EVENT_DEBUG is not set -# CONFIG_ARCH_MISC_INIT is not set # CONFIG_BOARD_EARLY_INIT_F is not set # CONFIG_BOARD_EARLY_INIT_R is not set +CONFIG_BOARD_INIT=y # CONFIG_BOARD_POSTCLK_INIT is not set CONFIG_BOARD_LATE_INIT=y # CONFIG_CLOCKS is not set @@ -614,7 +619,7 @@ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=1 # CONFIG_SPL_MMC_TINY is not set # CONFIG_SPL_MMC_WRITE is not set # CONFIG_SPL_MPC8XXX_INIT_DDR is not set -# CONFIG_SPL_MTD is not set +CONFIG_SPL_MTD=y # CONFIG_SPL_MUSB_NEW is not set # CONFIG_SPL_NAND_SUPPORT is not set # CONFIG_SPL_NAND_DRIVERS is not set @@ -640,7 +645,7 @@ CONFIG_SPL_DM_SPI_FLASH=y # CONFIG_SPL_SATA is not set # CONFIG_SPL_NVME is not set CONFIG_SPL_SPI_FLASH_TINY=y -# CONFIG_SPL_SPI_FLASH_MTD is not set +CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 # CONFIG_SPL_THERMAL is not set @@ -683,6 +688,7 @@ CONFIG_CMD_BDI=y # CONFIG_CMD_CONFIG is not set CONFIG_CMD_CONSOLE=y # CONFIG_CMD_UFETCH is not set +CONFIG_CMD_HELP=y # CONFIG_CMD_HISTORY is not set # CONFIG_CMD_LICENSE is not set # CONFIG_CMD_PMC is not set @@ -875,7 +881,6 @@ CONFIG_CMD_REGULATOR=y # Security commands # # CONFIG_CMD_AES is not set -# CONFIG_CMD_BLOB is not set # CONFIG_CMD_HASH is not set # CONFIG_CMD_HVC is not set # CONFIG_CMD_SMC is not set @@ -970,7 +975,7 @@ CONFIG_ENV_SUPPORT=y CONFIG_ENV_CALLBACK_LIST_STATIC="" CONFIG_SAVEENV=y # CONFIG_ENV_OVERWRITE is not set -# CONFIG_OVERWRITE_ETHADDR_ONCE is not set +# CONFIG_ENV_OVERWRITE_ETHADDR_ONCE is not set CONFIG_ENV_MIN_ENTRIES=64 CONFIG_ENV_MAX_ENTRIES=512 CONFIG_ENV_IS_DEFAULT=y @@ -981,13 +986,14 @@ CONFIG_ENV_IS_NOWHERE=y # CONFIG_ENV_IS_IN_FLASH is not set # CONFIG_ENV_IS_IN_MMC is not set # CONFIG_ENV_IS_IN_NAND is not set +# CONFIG_ENV_IS_IN_SCSI is not set # CONFIG_ENV_IS_IN_NVRAM is not set # CONFIG_ENV_IS_IN_REMOTE is not set # CONFIG_ENV_IS_IN_SPI_FLASH is not set # CONFIG_ENV_IS_IN_MTD is not set -# CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_USE_DEFAULT_ENV_FILE is not set +# CONFIG_ENV_REDUNDANT is not set +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +# CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE is not set # CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set # CONFIG_ENV_IMPORT_FDT is not set # CONFIG_ENV_APPEND is not set @@ -1043,7 +1049,6 @@ CONFIG_OFNODE_MULTI_TREE_MAX=4 CONFIG_BOUNCE_BUFFER=y CONFIG_ADC=y # CONFIG_SPL_ADC is not set -# CONFIG_ADC_EXYNOS is not set # CONFIG_ADC_SANDBOX is not set # CONFIG_SARADC_MESON is not set CONFIG_SARADC_ROCKCHIP=y @@ -1082,7 +1087,6 @@ CONFIG_BLOCK_CACHE=y # # CONFIG_CACHE is not set # CONFIG_L2X0_CACHE is not set -# CONFIG_ANDES_L2_CACHE is not set # CONFIG_NCORE_CACHE is not set # CONFIG_SIFIVE_CCACHE is not set # CONFIG_SIFIVE_PL2 is not set @@ -1091,6 +1095,7 @@ CONFIG_BLOCK_CACHE=y # Clock # CONFIG_CLK=y +# CONFIG_CLK_AUTO_ID is not set CONFIG_SPL_CLK=y # CONFIG_SPL_CLK_CCF is not set # CONFIG_CLK_CCF is not set @@ -1120,12 +1125,12 @@ CONFIG_SPL_CLK=y # Hardware crypto devices # # CONFIG_DM_HASH is not set +# CONFIG_DM_AES is not set # CONFIG_FSL_CAAM is not set CONFIG_CAAM_64BIT=y # CONFIG_SYS_FSL_SEC_BE is not set # CONFIG_SYS_FSL_SEC_LE is not set # CONFIG_FSL_DCP_RNG is not set -# CONFIG_NPCM_AES is not set # CONFIG_NPCM_SHA is not set # CONFIG_DDR_SPD is not set # CONFIG_IMX_SNPS_DDR_PHY is not set @@ -1143,8 +1148,6 @@ CONFIG_CAAM_64BIT=y # DMA Support # # CONFIG_DMA is not set -# CONFIG_DMA_LPC32XX is not set -# CONFIG_TI_EDMA3 is not set # CONFIG_DMA_LEGACY is not set # @@ -1158,7 +1161,6 @@ CONFIG_CAAM_64BIT=y CONFIG_FIRMWARE=y # CONFIG_SPL_FIRMWARE is not set CONFIG_ARM_PSCI_FW=y -# CONFIG_ZYNQMP_FIRMWARE is not set # CONFIG_ARM_SMCCC_FEATURES is not set # CONFIG_ARM_FFA_TRANSPORT is not set # CONFIG_SCMI_FIRMWARE is not set @@ -1168,7 +1170,6 @@ CONFIG_ARM_PSCI_FW=y # FPGA support # # CONFIG_FPGA_ALTERA is not set -# CONFIG_FPGA_SOCFPGA is not set # CONFIG_FPGA_LATTICE is not set # CONFIG_FPGA_XILINX is not set # CONFIG_DM_FPGA is not set @@ -1180,53 +1181,32 @@ CONFIG_SPL_DM_GPIO=y # CONFIG_DM_GPIO_LOOKUP_LABEL is not set # CONFIG_SPL_DM_GPIO_LOOKUP_LABEL is not set # CONFIG_ALTERA_PIO is not set -# CONFIG_BCM2835_GPIO is not set # CONFIG_DWAPB_GPIO is not set -# CONFIG_AT91_GPIO is not set -# CONFIG_ATMEL_PIO4 is not set # CONFIG_ASPEED_GPIO is not set # CONFIG_ASPEED_SGPIO is not set # CONFIG_ASPEED_G7_GPIO is not set # CONFIG_DA8XX_GPIO is not set # CONFIG_FXL6408_GPIO is not set -# CONFIG_HIKEY_GPIO is not set -# CONFIG_INTEL_BROADWELL_GPIO is not set -# CONFIG_INTEL_GPIO is not set -# CONFIG_INTEL_ICH6_GPIO is not set -# CONFIG_IMX_RGPIO2P is not set # CONFIG_IPROC_GPIO is not set # CONFIG_HSDK_CREG_GPIO is not set -# CONFIG_KIRKWOOD_GPIO is not set -# CONFIG_LPC32XX_GPIO is not set # CONFIG_MAX7320_GPIO is not set # CONFIG_MCP230XX_GPIO is not set -# CONFIG_MSM_GPIO is not set -# CONFIG_MXC_GPIO is not set -# CONFIG_MXS_GPIO is not set -# CONFIG_NPCM_GPIO is not set -# CONFIG_NPCM_SGPIO is not set # CONFIG_CMD_PCA953X is not set # CONFIG_PCF8575_GPIO is not set CONFIG_ROCKCHIP_GPIO=y # CONFIG_XILINX_GPIO is not set -# CONFIG_TCA642X is not set -# CONFIG_TEGRA_GPIO is not set # CONFIG_TEGRA186_GPIO is not set -# CONFIG_VYBRID_GPIO is not set -# CONFIG_SIFIVE_GPIO is not set # CONFIG_ZYNQ_GPIO is not set # CONFIG_DM_74X164 is not set # CONFIG_DM_PCA953X is not set # CONFIG_ADP5588_GPIO is not set # CONFIG_SPL_DM_PCA953X is not set # CONFIG_PCA953X is not set -# CONFIG_MPC8XXX_GPIO is not set -# CONFIG_MPC8XX_GPIO is not set # CONFIG_NX_GPIO is not set # CONFIG_NOMADIK_GPIO is not set -# CONFIG_SLG7XL45106_I2C_GPO is not set # CONFIG_FTGPIO010 is not set # CONFIG_ADP5585_GPIO is not set +# CONFIG_MPFS_GPIO is not set # # Hardware Spinlock Support @@ -1238,31 +1218,26 @@ CONFIG_SPL_DM_I2C=y # CONFIG_I2C_SET_DEFAULT_BUS_NUM is not set # CONFIG_DM_I2C_GPIO is not set # CONFIG_SYS_I2C_IPROC is not set -# CONFIG_SYS_I2C_FSL is not set # CONFIG_SYS_I2C_CADENCE is not set # CONFIG_SYS_I2C_DW is not set # CONFIG_SYS_I2C_INTEL is not set -# CONFIG_SYS_I2C_IMX_LPI2C is not set # CONFIG_SYS_I2C_MTK is not set # CONFIG_SYS_I2C_MICROCHIP is not set -# CONFIG_SYS_I2C_MXC is not set -# CONFIG_SYS_I2C_NEXELL is not set -# CONFIG_SYS_I2C_NPCM is not set # CONFIG_SYS_I2C_OCORES is not set CONFIG_SYS_I2C_ROCKCHIP=y # CONFIG_SYS_I2C_SOFT is not set # CONFIG_SYS_I2C_S3C24X0 is not set # CONFIG_SYS_I2C_MV is not set -# CONFIG_SYS_I2C_MVTWSI is not set # CONFIG_SYS_I2C_XILINX_XIIC is not set # CONFIG_SYS_I2C_IHS is not set # CONFIG_I2C_MUX is not set +# CONFIG_I3C is not set +# CONFIG_I3C_SANDBOX is not set CONFIG_INPUT=y # CONFIG_SPL_INPUT is not set # CONFIG_DM_KEYBOARD is not set # CONFIG_SPL_DM_KEYBOARD is not set # CONFIG_CROS_EC_KEYB is not set -# CONFIG_TEGRA_KEYBOARD is not set # CONFIG_TWL4030_INPUT is not set # @@ -1315,13 +1290,10 @@ CONFIG_ROCKCHIP_IODOMAIN=y # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_CROS_EC is not set # CONFIG_SPL_CROS_EC is not set -# CONFIG_DS4510 is not set -# CONFIG_FSL_SEC_MON is not set # CONFIG_IRQ is not set # CONFIG_NPCM_HOST is not set # CONFIG_NUVOTON_NCT6102D is not set # CONFIG_PWRSEQ is not set -# CONFIG_PCA9551_LED is not set # CONFIG_TEST_DRV is not set # CONFIG_TURRIS_OMNIA_MCU is not set # CONFIG_USB_HUB_USB251XB is not set @@ -1335,7 +1307,6 @@ CONFIG_ROCKCHIP_IODOMAIN=y # CONFIG_FS_LOADER is not set # CONFIG_SPL_FS_LOADER is not set # CONFIG_GDSYS_SOC is not set -# CONFIG_IHS_FPGA is not set # CONFIG_MICROCHIP_FLEXCOM is not set # CONFIG_ESM_PMIC is not set # CONFIG_SL28CPLD is not set @@ -1373,34 +1344,23 @@ CONFIG_MMC_DW=y # CONFIG_MMC_DW_K3 is not set CONFIG_MMC_DW_ROCKCHIP=y # CONFIG_MMC_DW_SNPS is not set -# CONFIG_MMC_MXC is not set # CONFIG_MMC_PCI is not set -# CONFIG_MMC_OMAP_HS is not set CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_SPL_MMC_SDHCI_SDMA=y # CONFIG_MMC_SDHCI_ADMA is not set # CONFIG_SPL_MMC_SDHCI_ADMA is not set -# CONFIG_MMC_SDHCI_BCMSTB is not set CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC_SDHCI_CV1800B=y # CONFIG_MMC_SDHCI_IPROC is not set # CONFIG_MMC_SDHCI_F_SDH30 is not set -# CONFIG_MMC_SDHCI_KONA is not set -# CONFIG_MMC_SDHCI_MSM is not set # CONFIG_MMC_SDHCI_NPCM is not set CONFIG_MMC_SDHCI_ROCKCHIP=y -# CONFIG_MMC_SDHCI_S5P is not set # CONFIG_MMC_SDHCI_SNPS is not set -# CONFIG_MMC_SDHCI_STI is not set # CONFIG_MMC_SDHCI_XENON is not set # CONFIG_MMC_SDHCI_TANGIER is not set -# CONFIG_MMC_SDHCI_ZYNQ is not set # CONFIG_MMC_PITON is not set -# CONFIG_STM32_SDMMC2 is not set # CONFIG_FTSDC010 is not set -# CONFIG_FSL_ESDHC is not set -# CONFIG_FSL_ESDHC_IMX is not set # # MTD Support @@ -1465,7 +1425,6 @@ CONFIG_SPI_FLASH_MTD=y # CONFIG_MV88E6352_SWITCH is not set # CONFIG_FSL_MEMAC is not set CONFIG_PHY_RESET_DELAY=0 -# CONFIG_FSL_PFE is not set CONFIG_ETH=y CONFIG_DM_ETH_PHY=y CONFIG_NVME=y @@ -1502,6 +1461,7 @@ CONFIG_PCIE_DW_ROCKCHIP=y # PCI Endpoint # # CONFIG_PCI_ENDPOINT is not set +# CONFIG_PCIE_CDNS_TI_EP is not set # CONFIG_X86_PCH7 is not set # CONFIG_X86_PCH9 is not set @@ -1557,10 +1517,13 @@ CONFIG_SPL_PINCONF_RECURSIVE=y # CONFIG_PINCTRL_INTEL is not set # CONFIG_PINCTRL_QE is not set # CONFIG_PINCTRL_ROCKCHIP_RV1108 is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_SPL_PINCTRL_SX150X is not set # CONFIG_PINCTRL_SINGLE is not set # CONFIG_PINCTRL_STM32 is not set # CONFIG_PINCTRL_STMFX is not set # CONFIG_SPL_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_TH1520 is not set # CONFIG_PINCTRL_K210 is not set CONFIG_PINCTRL_ROCKCHIP=y CONFIG_SPL_PINCTRL_ROCKCHIP=y @@ -1657,7 +1620,10 @@ CONFIG_DM_PWM=y # CONFIG_PWM_SIFIVE is not set # CONFIG_PWM_TEGRA is not set # CONFIG_PWM_SUNXI is not set -# CONFIG_U_QE is not set + +# +# RAM drivers using Driver Model +# CONFIG_RAM=y CONFIG_SPL_RAM=y # CONFIG_STM32_SDRAM is not set @@ -1808,7 +1774,6 @@ CONFIG_SPI_MEM=y # CONFIG_MTK_SNOR is not set # CONFIG_MTK_SNFI_SPI is not set # CONFIG_MTK_SPIM is not set -# CONFIG_MVEBU_A3700_SPI is not set # CONFIG_SPI_MXIC is not set # CONFIG_NPCM_FIU_SPI is not set # CONFIG_NPCM_PSPI is not set @@ -1948,6 +1913,7 @@ CONFIG_STRTO=y CONFIG_SPL_STRTO=y CONFIG_SYS_HZ=1000 CONFIG_SPL_USE_TINY_PRINTF=y +# CONFIG_SPL_USE_TINY_PRINTF_POINTER_SUPPORT is not set # CONFIG_PANIC_HANG is not set CONFIG_REGEX=y CONFIG_LIB_RAND=y diff --git a/cfg/kernel_v6.14-rc7 b/cfg/kernel_v6.16-rc2 similarity index 94% rename from cfg/kernel_v6.14-rc7 rename to cfg/kernel_v6.16-rc2 index dcad18d..4efa7b2 100644 --- a/cfg/kernel_v6.14-rc7 +++ b/cfg/kernel_v6.16-rc2 @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.14.0-rc7 Kernel Configuration +# Linux/arm64 6.16.0-rc2 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Gentoo 15.1.1_p20250705-r1 p2) 15.1.1 20250705" CONFIG_CC_IS_GCC=y @@ -11,17 +11,20 @@ CONFIG_AS_VERSION=24400 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=24400 CONFIG_LLD_VERSION=0 -CONFIG_RUSTC_VERSION=108800 -CONFIG_RUSTC_LLVM_VERSION=200105 +CONFIG_RUSTC_VERSION=108900 +CONFIG_RUSTC_LLVM_VERSION=200107 CONFIG_CC_CAN_LINK=y -CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y CONFIG_TOOLS_SUPPORT_RELR=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_CC_HAS_COUNTED_BY=y +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING=y +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY=y CONFIG_RUSTC_HAS_COERCE_POINTEE=y +CONFIG_RUSTC_HAS_SPAN_FILE=y +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES=y CONFIG_PAHOLE_VERSION=130 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y @@ -45,7 +48,6 @@ CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y -# CONFIG_USELIB is not set # CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y @@ -104,9 +106,11 @@ CONFIG_BPF_UNPRIV_DEFAULT_OFF=y # end of BPF subsystem CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_ARCH_HAS_PREEMPT_LAZY=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set +# CONFIG_PREEMPT_LAZY is not set # CONFIG_PREEMPT_RT is not set # CONFIG_PREEMPT_DYNAMIC is not set @@ -211,11 +215,11 @@ CONFIG_LD_ORPHAN_WARN_LEVEL="warn" CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_SYSFS_SYSCALL is not set CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y # CONFIG_SGETMASK_SYSCALL is not set -CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y @@ -223,6 +227,7 @@ CONFIG_BUG=y # CONFIG_BASE_SMALL is not set CONFIG_FUTEX=y CONFIG_FUTEX_PI=y +CONFIG_FUTEX_PRIVATE_HASH=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -239,6 +244,7 @@ CONFIG_CACHESTAT_SYSCALL=y # CONFIG_PC104 is not set # CONFIG_KALLSYMS is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS=y CONFIG_HAVE_PERF_EVENTS=y # @@ -259,6 +265,7 @@ CONFIG_KEXEC_CORE=y CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y # CONFIG_KEXEC_SIG is not set +# CONFIG_KEXEC_HANDOVER is not set CONFIG_CRASH_DUMP=y # end of Kexec and crash features # end of General setup @@ -342,6 +349,7 @@ CONFIG_ARCH_ROCKCHIP=y # ARM errata workarounds via the alternatives framework # # CONFIG_AMPERE_ERRATUM_AC03_CPU_38 is not set +CONFIG_AMPERE_ERRATUM_AC04_CPU_23=y CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y CONFIG_ARM64_ERRATUM_826319=y CONFIG_ARM64_ERRATUM_827319=y @@ -351,7 +359,6 @@ CONFIG_ARM64_ERRATUM_832075=y CONFIG_ARM64_ERRATUM_1742098=y CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y CONFIG_ARM64_ERRATUM_1024718=y CONFIG_ARM64_ERRATUM_1418040=y CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y @@ -388,6 +395,7 @@ CONFIG_ARM64_ERRATUM_2441009=y # CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set # CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set # CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set +CONFIG_ROCKCHIP_ERRATUM_3568002=y CONFIG_ROCKCHIP_ERRATUM_3588001=y # CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set # end of ARM errata workarounds via the alternatives framework @@ -425,6 +433,7 @@ CONFIG_ARCH_SELECTS_KEXEC_FILE=y CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_SUPPORTS_KEXEC_HANDOVER=y CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y CONFIG_ARCH_DEFAULT_CRASH_DUMP=y CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION=y @@ -446,7 +455,6 @@ CONFIG_KUSER_HELPERS=y # CONFIG_ARM64_HW_AFDBM=y CONFIG_ARM64_PAN=y -CONFIG_AS_HAS_LSE_ATOMICS=y CONFIG_ARM64_LSE_ATOMICS=y CONFIG_ARM64_USE_LSE_ATOMICS=y # end of ARMv8.1 architectural features @@ -454,8 +462,6 @@ CONFIG_ARM64_USE_LSE_ATOMICS=y # # ARMv8.2 architectural features # -CONFIG_AS_HAS_ARMV8_2=y -CONFIG_AS_HAS_SHA3=y # CONFIG_ARM64_PMEM is not set CONFIG_ARM64_RAS_EXTN=y CONFIG_ARM64_CNP=y @@ -467,17 +473,13 @@ CONFIG_ARM64_CNP=y CONFIG_ARM64_PTR_AUTH=y CONFIG_ARM64_PTR_AUTH_KERNEL=y CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y -CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y -CONFIG_AS_HAS_ARMV8_3=y CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y -CONFIG_AS_HAS_LDAPR=y # end of ARMv8.3 architectural features # # ARMv8.4 architectural features # CONFIG_ARM64_AMU_EXTN=y -CONFIG_AS_HAS_ARMV8_4=y CONFIG_ARM64_TLB_RANGE=y # end of ARMv8.4 architectural features @@ -515,6 +517,7 @@ CONFIG_ARM64_GCS=y # end of v9.4 architectural features CONFIG_ARM64_SVE=y +CONFIG_ARM64_SME=y # CONFIG_ARM64_PSEUDO_NMI is not set CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set @@ -616,6 +619,7 @@ CONFIG_CPU_MITIGATIONS=y # General architecture-dependent options # CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y +CONFIG_HOTPLUG_SMT=y CONFIG_HOTPLUG_CORE_SYNC=y CONFIG_HOTPLUG_CORE_SYNC_DEAD=y # CONFIG_KPROBES is not set @@ -780,7 +784,6 @@ CONFIG_MSDOS_PARTITION=y CONFIG_EFI_PARTITION=y # end of Partition Types -CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y # @@ -879,6 +882,7 @@ CONFIG_SWAP=y # Slab allocator options # CONFIG_SLUB=y +CONFIG_KVFREE_RCU_BATCHED=y # CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set @@ -917,7 +921,9 @@ CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y # CONFIG_MEMORY_FAILURE is not set CONFIG_ARCH_WANTS_THP_SWAP=y # CONFIG_TRANSPARENT_HUGEPAGE is not set +CONFIG_PAGE_MAPCOUNT=y # CONFIG_CMA is not set +CONFIG_PAGE_BLOCK_ORDER=10 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set @@ -1002,7 +1008,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_NET_PTP_CLASSIFY=y # CONFIG_NETWORK_PHY_TIMESTAMPING is not set # CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set # CONFIG_TIPC is not set @@ -1123,6 +1128,7 @@ CONFIG_PCI_MSI=y CONFIG_PCI_QUIRKS=y # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set +# CONFIG_PCI_DOE is not set # CONFIG_PCI_IOV is not set # CONFIG_PCI_NPEM is not set # CONFIG_PCI_PRI is not set @@ -1160,8 +1166,10 @@ CONFIG_VGA_ARB_MAX_GPUS=16 # DesignWare-based PCIe controllers # CONFIG_PCIE_DW=y +# CONFIG_PCIE_DW_DEBUGFS is not set CONFIG_PCIE_DW_HOST=y # CONFIG_PCIE_AL is not set +# CONFIG_PCIE_AMD_MDB is not set # CONFIG_PCI_MESON is not set # CONFIG_PCI_HISI is not set # CONFIG_PCIE_KIRIN is not set @@ -1194,6 +1202,7 @@ CONFIG_PCIE_ROCKCHIP_DW_HOST=y # CONFIG_PCI_SW_SWITCHTEC is not set # end of PCI switch controller drivers +# CONFIG_PCI_PWRCTRL_SLOT is not set # CONFIG_CXL_BUS is not set # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set @@ -1290,6 +1299,7 @@ CONFIG_ARM_SCMI_TRANSPORT_SMC=y # end of ARM System Control and Management Interface Protocol CONFIG_ARM_SCPI_PROTOCOL=y +# CONFIG_ARM_SDE_INTERFACE is not set # CONFIG_FIRMWARE_MEMMAP is not set # CONFIG_FW_CFG_SYSFS is not set # CONFIG_ARM_FFA_TRANSPORT is not set @@ -1312,6 +1322,7 @@ CONFIG_ARM_SMCCC_SOC_ID=y # end of Tegra firmware driver # end of Firmware Drivers +# CONFIG_FWCTL is not set # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -1462,7 +1473,8 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_PHANTOM is not set -# CONFIG_RPMB is not set +CONFIG_RPMB=y +# CONFIG_TI_FPC202 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1485,16 +1497,15 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_NTSYNC is not set # CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_MCHP_LAN966X_PCI is not set -# CONFIG_MODEM_POWER is not set # CONFIG_C2PORT is not set # # EEPROM support # CONFIG_EEPROM_AT24=y -CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_AT25 is not set # CONFIG_EEPROM_MAX6875 is not set -CONFIG_EEPROM_93CX6=y +# CONFIG_EEPROM_93CX6 is not set # CONFIG_EEPROM_93XX46 is not set # CONFIG_EEPROM_IDT_89HPESX is not set # CONFIG_EEPROM_EE1004 is not set @@ -1506,7 +1517,6 @@ CONFIG_EEPROM_93CX6=y # CONFIG_ALTERA_STAPL is not set # CONFIG_VMWARE_VMCI is not set # CONFIG_GENWQE is not set -# CONFIG_ECHO is not set # CONFIG_BCM_VK is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set @@ -1515,7 +1525,7 @@ CONFIG_EEPROM_93CX6=y # CONFIG_PVPANIC is not set # CONFIG_GP_PCI1XXXX is not set # CONFIG_KEBA_CP500 is not set -CONFIG_SUNXI_ADDR_MGT=y +# CONFIG_AMD_SBRMI_I2C is not set # end of Misc devices # @@ -1622,6 +1632,7 @@ CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set # CONFIG_WIREGUARD is not set +# CONFIG_OVPN is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_FC is not set # CONFIG_NET_TEAM is not set @@ -1742,6 +1753,7 @@ CONFIG_FIXED_PHY=y # # MII PHY device drivers # +# CONFIG_AS21XXX_PHY is not set # CONFIG_AIR_EN8811H_PHY is not set CONFIG_AC200_PHY=y CONFIG_AC200_PHY_SUNXI=y @@ -1767,6 +1779,7 @@ CONFIG_AC200_PHY_SUNXI=y # CONFIG_MARVELL_88Q2XXX_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set # CONFIG_MAXLINEAR_GPHY is not set +# CONFIG_MAXLINEAR_86110_PHY is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set # CONFIG_MICROCHIP_T1S_PHY is not set @@ -1849,11 +1862,9 @@ CONFIG_CAN_GS_USB=y # end of CAN USB interfaces # CONFIG_CAN_DEBUG_DEVICES is not set -CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y -CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_SUN4I is not set # CONFIG_MDIO_BITBANG is not set # CONFIG_MDIO_BCM_UNIMAC is not set @@ -1883,7 +1894,6 @@ CONFIG_PCS_XPCS=y # CONFIG_SLIP is not set # CONFIG_USB_NET_DRIVERS is not set CONFIG_WLAN=y -# CONFIG_SSV6051 is not set # CONFIG_WLAN_VENDOR_ADMTEK is not set # CONFIG_WLAN_VENDOR_ATH is not set # CONFIG_WLAN_VENDOR_ATMEL is not set @@ -2151,9 +2161,8 @@ CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y -CONFIG_SERIAL_8250_PCILIB=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_EXAR=y +# CONFIG_SERIAL_8250_PCI is not set +# CONFIG_SERIAL_8250_EXAR is not set CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y @@ -2166,7 +2175,7 @@ CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_RT288X is not set -CONFIG_SERIAL_8250_PERICOM=y +# CONFIG_SERIAL_8250_PERICOM is not set CONFIG_SERIAL_OF_PLATFORM=y # @@ -2265,7 +2274,6 @@ CONFIG_I2C_ALGOBIT=y # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set -# CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_NFORCE2 is not set # CONFIG_I2C_NVIDIA_GPU is not set # CONFIG_I2C_SIS5595 is not set @@ -2447,6 +2455,8 @@ CONFIG_PINCTRL_SUNXI=y # CONFIG_PINCTRL_SUN50I_H6_R is not set CONFIG_PINCTRL_SUN50I_H616=y CONFIG_PINCTRL_SUN50I_H616_R=y +# CONFIG_PINCTRL_SUN55I_A523 is not set +# CONFIG_PINCTRL_SUN55I_A523_R is not set CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y @@ -2463,7 +2473,6 @@ CONFIG_GPIO_CDEV_V1=y # CONFIG_GPIO_ALTERA is not set # CONFIG_GPIO_CADENCE is not set # CONFIG_GPIO_DWAPB is not set -# CONFIG_GPIO_EXAR is not set # CONFIG_GPIO_FTGPIO010 is not set # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_GRGPIO is not set @@ -2542,13 +2551,49 @@ CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_VIRTUSER is not set # end of GPIO Debugging utilities -# CONFIG_W1 is not set +CONFIG_W1=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_AMD_AXI is not set +# CONFIG_W1_MASTER_MATROX is not set +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_DS2482 is not set +CONFIG_W1_MASTER_GPIO=y +# CONFIG_W1_MASTER_SGI is not set +# CONFIG_W1_MASTER_UART is not set +# end of 1-wire Bus Masters + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=y +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2405 is not set +# CONFIG_W1_SLAVE_DS2408 is not set +# CONFIG_W1_SLAVE_DS2413 is not set +# CONFIG_W1_SLAVE_DS2406 is not set +# CONFIG_W1_SLAVE_DS2423 is not set +# CONFIG_W1_SLAVE_DS2805 is not set +# CONFIG_W1_SLAVE_DS2430 is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2438 is not set +# CONFIG_W1_SLAVE_DS250X is not set +# CONFIG_W1_SLAVE_DS2780 is not set +# CONFIG_W1_SLAVE_DS2781 is not set +# CONFIG_W1_SLAVE_DS28E04 is not set +# CONFIG_W1_SLAVE_DS28E17 is not set +# end of 1-wire Slaves + CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_GPIO is not set # CONFIG_POWER_RESET_GPIO_RESTART is not set # CONFIG_POWER_RESET_LTC2952 is not set CONFIG_POWER_RESET_REGULATOR=y CONFIG_POWER_RESET_RESTART=y +# CONFIG_POWER_RESET_TORADEX_EC is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y @@ -2562,7 +2607,9 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_IP5XXX_POWER is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CHAGALL is not set # CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2760 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set @@ -2571,10 +2618,13 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_SBS is not set # CONFIG_MANAGER_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_AXP20X_POWER is not set +# CONFIG_CHARGER_AXP20X is not set +# CONFIG_BATTERY_AXP20X is not set +CONFIG_AXP20X_POWER=y # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set # CONFIG_BATTERY_MAX1720X is not set +# CONFIG_BATTERY_MAX1721X is not set # CONFIG_CHARGER_ISP1704 is not set # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_LP8727 is not set @@ -2584,6 +2634,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_MAX77976 is not set +# CONFIG_CHARGER_MAX8971 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -2652,6 +2703,7 @@ CONFIG_SENSORS_ARM_SCPI=y CONFIG_SENSORS_GPIO_FAN=y # CONFIG_SENSORS_HIH6130 is not set # CONFIG_SENSORS_HS3001 is not set +# CONFIG_SENSORS_HTU31 is not set # CONFIG_SENSORS_IIO_HWMON is not set # CONFIG_SENSORS_ISL28022 is not set # CONFIG_SENSORS_IT87 is not set @@ -2729,7 +2781,6 @@ CONFIG_SENSORS_GPIO_FAN=y # CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=y # CONFIG_SENSORS_SBTSI is not set -# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -2871,7 +2922,7 @@ CONFIG_MFD_CORE=y CONFIG_MFD_AC200_SUNXI=y CONFIG_MFD_AXP20X=y CONFIG_MFD_AXP20X_I2C=y -# CONFIG_MFD_AXP20X_RSB is not set +CONFIG_MFD_AXP20X_RSB=y # CONFIG_MFD_CS42L43_I2C is not set # CONFIG_MFD_MADERA is not set # CONFIG_MFD_MAX5970 is not set @@ -2903,7 +2954,9 @@ CONFIG_MFD_AXP20X_I2C=y # CONFIG_MFD_MAX77650 is not set # CONFIG_MFD_MAX77686 is not set # CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77705 is not set # CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77759 is not set # CONFIG_MFD_MAX77843 is not set # CONFIG_MFD_MAX8907 is not set # CONFIG_MFD_MAX8925 is not set @@ -2919,7 +2972,6 @@ CONFIG_MFD_AXP20X_I2C=y # CONFIG_MFD_VIPERBOARD is not set # CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set -# CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_SY7636A is not set # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_RT4831 is not set @@ -2930,7 +2982,7 @@ CONFIG_MFD_RK8XX=y CONFIG_MFD_RK8XX_I2C=y # CONFIG_MFD_RK8XX_SPI is not set # CONFIG_MFD_RN5T618 is not set -# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SEC_I2C is not set # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set @@ -3000,6 +3052,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ADP5055 is not set # CONFIG_REGULATOR_ARM_SCMI is not set # CONFIG_REGULATOR_AW37503 is not set CONFIG_REGULATOR_AXP20X=y @@ -3036,6 +3089,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF9453 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -3043,6 +3097,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_PV88090 is not set # CONFIG_REGULATOR_PWM is not set # CONFIG_REGULATOR_RAA215300 is not set +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT4803 is not set @@ -3080,6 +3135,7 @@ CONFIG_CEC_NOTIFIER=y # CONFIG_MEDIA_CEC_SUPPORT=y # CONFIG_CEC_CH7322 is not set +# CONFIG_CEC_NXP_TDA9950 is not set # CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC is not set # CONFIG_USB_PULSE8_CEC is not set # CONFIG_USB_RAINSHADOW_CEC is not set @@ -3321,6 +3377,8 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_OG01A1B is not set # CONFIG_VIDEO_OV01A10 is not set # CONFIG_VIDEO_OV02A10 is not set +# CONFIG_VIDEO_OV02E10 is not set +# CONFIG_VIDEO_OV02C10 is not set # CONFIG_VIDEO_OV08D10 is not set # CONFIG_VIDEO_OV08X40 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3357,6 +3415,8 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_S5C73M3 is not set # CONFIG_VIDEO_S5K5BAF is not set # CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_VD55G1 is not set +# CONFIG_VIDEO_VD56G3 is not set # CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set @@ -3515,8 +3575,15 @@ CONFIG_APERTURE_HELPERS=y CONFIG_VIDEO=y # CONFIG_AUXDISPLAY is not set CONFIG_DRM=y -CONFIG_DRM_MIPI_DSI=y + +# +# DRM debugging options +# +# CONFIG_DRM_WERROR is not set # CONFIG_DRM_DEBUG_MM is not set +# end of DRM debugging options + +CONFIG_DRM_MIPI_DSI=y CONFIG_DRM_KMS_HELPER=y # CONFIG_DRM_PANIC is not set # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set @@ -3547,13 +3614,11 @@ CONFIG_DRM_GEM_SHMEM_HELPER=y CONFIG_DRM_SCHED=y # -# I2C encoder or helper chips +# Drivers for system framebuffers # -# CONFIG_DRM_I2C_CH7006 is not set -# CONFIG_DRM_I2C_SIL164 is not set -# CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_I2C_NXP_TDA9950 is not set -# end of I2C encoder or helper chips +CONFIG_DRM_SYSFB_HELPER=y +CONFIG_DRM_SIMPLEDRM=y +# end of Drivers for system framebuffers # # ARM devices @@ -3599,21 +3664,115 @@ CONFIG_DRM_PANEL=y # # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set +# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TD4320 is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +CONFIG_DRM_PANEL_DSI_CM=m +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_HIMAX_HX8279 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set +# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_JDI_R63452 is not set +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set -# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set +# CONFIG_DRM_PANEL_NOVATEK_NT37801 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set +# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set +# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_EDP is not set +CONFIG_DRM_PANEL_SIMPLE=m +# CONFIG_DRM_PANEL_SUMMIT is not set +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_G2647FB105 is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_VISIONOX_RM692E5 is not set +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# CONFIG_DRM_PANEL_YIXIAN_YX0345 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -3625,6 +3784,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set CONFIG_DRM_DISPLAY_CONNECTOR=y +# CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_ITE_IT6263 is not set # CONFIG_DRM_ITE_IT6505 is not set # CONFIG_DRM_LONTIUM_LT8912B is not set @@ -3675,7 +3835,6 @@ CONFIG_DRM_DW_MIPI_DSI=y # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_PANEL_MIPI_DBI is not set -CONFIG_DRM_SIMPLEDRM=y # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set @@ -3684,17 +3843,17 @@ CONFIG_DRM_SIMPLEDRM=y # CONFIG_TINYDRM_MI0283QT is not set # CONFIG_TINYDRM_REPAPER is not set # CONFIG_TINYDRM_SHARP_MEMORY is not set -# CONFIG_TINYDRM_ST7586 is not set -# CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_PL111 is not set # CONFIG_DRM_LIMA is not set CONFIG_DRM_PANFROST=y # CONFIG_DRM_PANTHOR is not set # CONFIG_DRM_TIDSS is not set # CONFIG_DRM_GUD is not set +# CONFIG_DRM_ST7571_I2C is not set +# CONFIG_DRM_ST7586 is not set +# CONFIG_DRM_ST7735R is not set # CONFIG_DRM_SSD130X is not set # CONFIG_DRM_POWERVR is not set -# CONFIG_DRM_WERROR is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # @@ -3734,6 +3893,7 @@ CONFIG_FB=y # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set +# CONFIG_FB_SSD1307 is not set # CONFIG_FB_SM712 is not set CONFIG_FB_CORE=y CONFIG_FB_NOTIFY=y @@ -3757,7 +3917,24 @@ CONFIG_FB_MODE_HELPERS=y # Backlight & LCD device support # # CONFIG_LCD_CLASS_DEVICE is not set -# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set +# CONFIG_BACKLIGHT_KTZ8866 is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_QCOM_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3509 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_MP3309C is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_LED is not set # end of Backlight & LCD device support CONFIG_VIDEOMODE_HELPERS=y @@ -3841,7 +4018,6 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_LCPOWER is not set # CONFIG_HID_LED is not set # CONFIG_HID_LETSKETCH is not set -# CONFIG_HID_LOGITECH is not set # CONFIG_HID_MAGICMOUSE is not set # CONFIG_HID_MALTRON is not set # CONFIG_HID_MAYFLASH is not set @@ -3948,6 +4124,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y # CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y +# CONFIG_USB_XHCI_SIDEBAND is not set CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_ROOT_HUB_TT is not set CONFIG_USB_EHCI_TT_NEWSCHED=y @@ -4004,18 +4181,7 @@ CONFIG_USB_STORAGE=y # USB dual-mode controller drivers # # CONFIG_USB_CDNS_SUPPORT is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_HOST=y - -# -# Platform Glue Layer -# -CONFIG_USB_MUSB_SUNXI=y - -# -# MUSB DMA mode -# -# CONFIG_MUSB_PIO_ONLY is not set +# CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y CONFIG_USB_DWC3_HOST=y @@ -4226,7 +4392,7 @@ CONFIG_LEDS_USER=y # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_LM3697 is not set # CONFIG_LEDS_ST1202 is not set -# CONFIG_LEDS_AXP20X is not set +CONFIG_LEDS_AXP20X=y # # Flash and Torch LED drivers @@ -4263,7 +4429,7 @@ CONFIG_LEDS_TRIGGER_NETDEV=y # CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # -# Simple LED drivers +# Simatic LED drivers # # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set @@ -4394,6 +4560,7 @@ CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DMA_OF=y # CONFIG_ALTERA_MSGDMA is not set # CONFIG_AMBA_PL08X is not set +# CONFIG_ARM_DMA350 is not set CONFIG_DMA_SUN6I=y # CONFIG_DW_AXI_DMAC is not set # CONFIG_FSL_EDMA is not set @@ -4443,6 +4610,7 @@ CONFIG_SYNC_FILE=y # # Microsoft Hyper-V guest support # +# CONFIG_HYPERV is not set # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set @@ -4458,7 +4626,6 @@ CONFIG_STAGING=y # Accelerometers # # CONFIG_ADIS16203 is not set -# CONFIG_ADIS16240 is not set # end of Accelerometers # @@ -4500,6 +4667,7 @@ CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_VIDEO_SUN6I_ISP is not set # CONFIG_STAGING_MEDIA_DEPRECATED is not set +# CONFIG_FB_TFT is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_VME_BUS is not set # CONFIG_GPIB is not set @@ -4547,6 +4715,8 @@ CONFIG_COMMON_CLK_ROCKCHIP=y # CONFIG_CLK_RK3328 is not set # CONFIG_CLK_RK3368 is not set # CONFIG_CLK_RK3399 is not set +CONFIG_CLK_RK3528=y +CONFIG_CLK_RK3562=y CONFIG_CLK_RK3568=y # CONFIG_CLK_RK3576 is not set # CONFIG_CLK_RK3588 is not set @@ -4557,6 +4727,8 @@ CONFIG_SUNXI_CCU=y # CONFIG_SUN50I_H6_CCU is not set CONFIG_SUN50I_H616_CCU=y CONFIG_SUN50I_H6_R_CCU=y +# CONFIG_SUN55I_A523_CCU is not set +# CONFIG_SUN55I_A523_R_CCU is not set CONFIG_SUN6I_RTC_CCU=y # CONFIG_SUN8I_H3_CCU is not set CONFIG_SUN8I_DE2_CCU=y @@ -4613,11 +4785,11 @@ CONFIG_IOMMU_DEFAULT_DMA_STRICT=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y +# CONFIG_ARM_SMMU is not set +# CONFIG_ARM_SMMU_V3 is not set # CONFIG_IOMMUFD is not set CONFIG_ROCKCHIP_IOMMU=y CONFIG_SUN50I_IOMMU=y -# CONFIG_ARM_SMMU is not set -# CONFIG_ARM_SMMU_V3 is not set # # Remoteproc drivers @@ -4735,7 +4907,6 @@ CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # -CONFIG_ARM_RK3328_DMC_DEVFREQ=y # CONFIG_ARM_RK3399_DMC_DEVFREQ is not set # CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set CONFIG_PM_DEVFREQ_EVENT=y @@ -4824,13 +4995,17 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # Analog to digital converters # +CONFIG_IIO_ADC_HELPER=y # CONFIG_AD4000 is not set +# CONFIG_AD4030 is not set # CONFIG_AD4130 is not set # CONFIG_AD4695 is not set +# CONFIG_AD4851 is not set # CONFIG_AD7091R5 is not set # CONFIG_AD7091R8 is not set # CONFIG_AD7124 is not set # CONFIG_AD7173 is not set +# CONFIG_AD7191 is not set # CONFIG_AD7192 is not set # CONFIG_AD7266 is not set # CONFIG_AD7280 is not set @@ -4854,7 +5029,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD7949 is not set # CONFIG_AD799X is not set # CONFIG_AD9467 is not set -# CONFIG_AXP20X_ADC is not set +CONFIG_AXP20X_ADC=y # CONFIG_AXP288_ADC is not set # CONFIG_CC10001_ADC is not set # CONFIG_ENVELOPE_DETECTOR is not set @@ -4881,8 +5056,10 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MCP3564 is not set # CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set +# CONFIG_NCT7201 is not set # CONFIG_PAC1921 is not set # CONFIG_PAC1934 is not set +# CONFIG_ROHM_BD79124 is not set CONFIG_ROCKCHIP_SARADC=y # CONFIG_RICHTEK_RTQ6056 is not set # CONFIG_SD_ADC_MODULATOR is not set @@ -4890,20 +5067,21 @@ CONFIG_SUN20I_GPADC=y # CONFIG_TI_ADC081C is not set # CONFIG_TI_ADC0832 is not set # CONFIG_TI_ADC084S021 is not set -# CONFIG_TI_ADC12138 is not set # CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC12138 is not set # CONFIG_TI_ADC128S052 is not set # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set -# CONFIG_TI_ADS1119 is not set -# CONFIG_TI_ADS7924 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set +# CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set +# CONFIG_TI_ADS131E08 is not set +# CONFIG_TI_ADS7138 is not set +# CONFIG_TI_ADS7924 is not set # CONFIG_TI_ADS7950 is not set # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set -# CONFIG_TI_ADS124S08 is not set -# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_LMP92064 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_TI_TSC2046 is not set @@ -4949,9 +5127,11 @@ CONFIG_SUN20I_GPADC=y # CONFIG_CCS811 is not set # CONFIG_ENS160 is not set # CONFIG_IAQCORE is not set +# CONFIG_MHZ19B is not set # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SCD4X is not set +# CONFIG_SEN0322 is not set # CONFIG_SENSIRION_SGP30 is not set # CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set @@ -4980,6 +5160,7 @@ CONFIG_SUN20I_GPADC=y # # Digital to analog converters # +# CONFIG_AD3530R is not set # CONFIG_AD3552R_HS is not set # CONFIG_AD3552R is not set # CONFIG_AD5064 is not set @@ -5115,6 +5296,7 @@ CONFIG_SUN20I_GPADC=y # CONFIG_ADIS16460 is not set # CONFIG_ADIS16475 is not set # CONFIG_ADIS16480 is not set +# CONFIG_ADIS16550 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set # CONFIG_BMI270_I2C is not set @@ -5140,8 +5322,10 @@ CONFIG_SUN20I_GPADC=y # # CONFIG_ADJD_S311 is not set # CONFIG_ADUX1020 is not set +# CONFIG_AL3000A is not set # CONFIG_AL3010 is not set # CONFIG_AL3320A is not set +# CONFIG_APDS9160 is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9306 is not set # CONFIG_APDS9960 is not set @@ -5214,6 +5398,7 @@ CONFIG_SUN20I_GPADC=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_SI7210 is not set # CONFIG_TI_TMAG5273 is not set # CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors @@ -5349,6 +5534,7 @@ CONFIG_PWM=y # CONFIG_PWM_CLK is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_MC33XS2410 is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_ROCKCHIP=y # CONFIG_PWM_SUN4I is not set @@ -5407,7 +5593,6 @@ CONFIG_PHY_SUN6I_MIPI_DPHY=y # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -5420,6 +5605,7 @@ CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y # CONFIG_PHY_ROCKCHIP_PCIE is not set +# CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY is not set # CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX is not set # CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set # CONFIG_PHY_ROCKCHIP_TYPEC is not set @@ -5523,7 +5709,20 @@ CONFIG_FS_MBCACHE=y # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set -# CONFIG_F2FS_FS is not set +CONFIG_F2FS_FS=y +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +# CONFIG_F2FS_FS_SECURITY is not set +CONFIG_F2FS_CHECK_FS=y +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y +# CONFIG_F2FS_FS_ZSTD is not set +CONFIG_F2FS_IOSTAT=y # CONFIG_BCACHEFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y @@ -5624,6 +5823,7 @@ CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y # CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU=y CONFIG_SQUASHFS_XATTR=y +# CONFIG_SQUASHFS_COMP_CACHE_FULL is not set CONFIG_SQUASHFS_ZLIB=y CONFIG_SQUASHFS_LZ4=y CONFIG_SQUASHFS_LZO=y @@ -5640,7 +5840,6 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_PSTORE is not set -# CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y @@ -5704,7 +5903,6 @@ CONFIG_NLS_ASCII=y CONFIG_NLS_UTF8=y # CONFIG_DLM is not set CONFIG_UNICODE=y -# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set CONFIG_IO_WQ=y # end of File systems @@ -5716,10 +5914,9 @@ CONFIG_IO_WQ=y CONFIG_PROC_MEM_ALWAYS_FORCE=y # CONFIG_PROC_MEM_FORCE_PTRACE is not set # CONFIG_PROC_MEM_NO_FORCE is not set +# CONFIG_MSEAL_SYSTEM_MAPPINGS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_HARDENED_USERCOPY is not set -# CONFIG_FORTIFY_SOURCE is not set # CONFIG_STATIC_USERMODEHELPER is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,ipe,bpf" @@ -5744,6 +5941,13 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # CONFIG_ZERO_CALL_USED_REGS is not set # end of Memory initialization +# +# Bounds checking +# +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_HARDENED_USERCOPY is not set +# end of Bounds checking + # # Hardening of kernel data structures # @@ -5779,13 +5983,13 @@ CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_USER is not set -CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_NULL2=m +# CONFIG_CRYPTO_SELFTESTS is not set +# CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_PCRYPT is not set # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_KRB5ENC is not set +# CONFIG_CRYPTO_BENCHMARK is not set CONFIG_CRYPTO_ENGINE=y # end of Crypto core or helper @@ -5859,13 +6063,11 @@ CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_POLY1305 is not set # CONFIG_CRYPTO_RMD160 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set -CONFIG_CRYPTO_SM3=y CONFIG_CRYPTO_SM3_GENERIC=y # CONFIG_CRYPTO_STREEBOG is not set # CONFIG_CRYPTO_WP512 is not set @@ -5878,7 +6080,6 @@ CONFIG_CRYPTO_SM3_GENERIC=y # # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_CRC32 is not set -# CONFIG_CRYPTO_CRCT10DIF is not set # end of CRCs (cyclic redundancy checks) # @@ -5912,16 +6113,12 @@ CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y # end of Userspace interface # CONFIG_CRYPTO_NHPOLY1305_NEON is not set -# CONFIG_CRYPTO_CHACHA20_NEON is not set # # Accelerated Cryptographic Algorithms for CPU (arm64) # # CONFIG_CRYPTO_GHASH_ARM64_CE is not set -# CONFIG_CRYPTO_POLY1305_NEON is not set # CONFIG_CRYPTO_SHA1_ARM64_CE is not set -# CONFIG_CRYPTO_SHA256_ARM64 is not set -# CONFIG_CRYPTO_SHA2_ARM64_CE is not set # CONFIG_CRYPTO_SHA512_ARM64 is not set # CONFIG_CRYPTO_SHA512_ARM64_CE is not set # CONFIG_CRYPTO_SHA3_ARM64 is not set @@ -5962,7 +6159,6 @@ CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y # CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set # CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set # CONFIG_CRYPTO_DEV_QAT_C62XVF is not set -# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set # CONFIG_CRYPTO_DEV_ROCKCHIP is not set CONFIG_CRYPTO_DEV_ROCKCHIP2=y # CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set @@ -5976,6 +6172,7 @@ CONFIG_CRYPTO_DEV_ROCKCHIP2=y # # end of Certificates for signature checking +# CONFIG_CRYPTO_KRB5 is not set CONFIG_BINARY_PRINTF=y # @@ -6004,35 +6201,31 @@ CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_LIB_GF128MUL=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -# CONFIG_CRYPTO_LIB_CHACHA is not set -# CONFIG_CRYPTO_LIB_CURVE25519 is not set CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -# CONFIG_CRYPTO_LIB_POLY1305 is not set -# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_SHA256=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_SHA256_SIMD=y +CONFIG_CRYPTO_LIB_SHA256_GENERIC=y +CONFIG_CRYPTO_LIB_SM3=y +CONFIG_CRYPTO_SHA256_ARM64=y # end of Crypto library routines CONFIG_CRC_CCITT=y CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set CONFIG_ARCH_HAS_CRC_T10DIF=y -# CONFIG_CRC64_ROCKSOFT is not set -# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y CONFIG_ARCH_HAS_CRC32=y CONFIG_CRC32_ARCH=y -# CONFIG_CRC64 is not set -# CONFIG_CRC4 is not set -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -# CONFIG_CRC8 is not set CONFIG_CRC_OPTIMIZATIONS=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=y +CONFIG_LZ4HC_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y CONFIG_XZ_DEC=y # CONFIG_XZ_DEC_X86 is not set @@ -6090,6 +6283,7 @@ CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_VDSO_GETRANDOM=y +CONFIG_GENERIC_VDSO_DATA_STORE=y CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y @@ -6152,10 +6346,7 @@ CONFIG_FRAME_POINTER=y # # Generic Kernel Debugging Instruments # -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +# CONFIG_MAGIC_SYSRQ is not set CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set @@ -6191,7 +6382,7 @@ CONFIG_SLUB_DEBUG=y # CONFIG_DEBUG_RODATA_TEST is not set CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set -CONFIG_GENERIC_PTDUMP=y +CONFIG_ARCH_HAS_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set @@ -6201,6 +6392,7 @@ CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_SCHED_STACK_END_CHECK is not set CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VFS is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_VM_PGTABLE is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y @@ -6240,7 +6432,6 @@ CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y # # Scheduler Debugging # -CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # end of Scheduler Debugging @@ -6305,6 +6496,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACE_CLOCK=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set @@ -6329,7 +6521,6 @@ CONFIG_STRICT_DEVMEM=y # CONFIG_NOTIFIER_ERROR_INJECTION is not set # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_ARCH_USE_MEMTEST=y @@ -6341,3 +6532,5 @@ CONFIG_ARCH_USE_MEMTEST=y # # end of Rust hacking # end of Kernel hacking + +CONFIG_IO_URING_ZCRX=y diff --git a/config/board/btt_cb1.json b/config/board/btt_cb1.json index a6e53ea..3339ee9 100644 --- a/config/board/btt_cb1.json +++ b/config/board/btt_cb1.json @@ -7,7 +7,10 @@ [ "CROSS_C:aarch64-linux-gnu-", "ATF_PLATFORM:sun50i_h616", - "ARCH:aarch64" + "ARCH:aarch64", + "DTB_FILE:allwinner/sun50i-h616-bigtreetech-cb1-manta.dtb", + "DTO_FILES:sun50i-h616*.dtbo", + "DTO_DIR:allwinner/overlays" ], "targets": [ @@ -49,9 +52,9 @@ }, { "parent": "kernel", - "version": "v6.14-rc7", + "version": "v6.16-rc2", "version_type": "tag", - "patch_dir": [ "kernel", "kernel/sunxi-6.14", "kernel/rockchip64-6.14" ], + "patch_dir": [ "kernel", "kernel/sunxi-6.16", "kernel/rockchip64-6.16" ], "config_def": "printer_defconfig", "target": [ "clean", "Image", "modules", "dtbs", "modules_install" ], "artifacts": @@ -61,32 +64,27 @@ "store_type": "boot" }, { - "file": "arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1*.dtb", + "file": "arch/arm64/boot/dts/%{DTB_FILE}%", "store_type": "boot", - "subdir": "dtb/allwinner" + "subdir": "dtb/allwinner", + "destdir": "dtb" }, { - "file": "arch/arm64/boot/dts/allwinner/overlay/sun50i-h616*.dtbo", - "store_type": "boot", + "file": "arch/arm64/boot/dts/allwinner/overlay/%{DTO_FILES}%", + "store_type": "none", "subdir": "dtb/allwinner/overlay" } ], - "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods" + "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods/usr" }, { "parent": "rtl8189ES_linux", "version": "rtl8189fs", "version_type": "branch", - "target": [ "modules" ], - "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods KSRC=%{common_dir}%/kernel", + "target": [ "modules", "install" ], + "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 MODDESTDIR=%{out_dir}%/kmods/usr/lib/modules/*/kernel/drivers/net/wireless KSRC=%{common_dir}%/kernel", "artifacts": - [ - { - "file": "8189fs.ko", - "store_type": "boot", - "subdir": "modules" - } - ] + [] } ], "install": diff --git a/config/board/btt_pi2.json b/config/board/btt_pi2.json index a43b7b4..f879a96 100644 --- a/config/board/btt_pi2.json +++ b/config/board/btt_pi2.json @@ -9,7 +9,9 @@ "TPL_BIN:rk3566_ddr_1056MHz_v1.23.bin", "BL31_BIN:rk3568_bl31_v1.44.elf", "ARCH:aarch64", - "DTB_FILE:rockchip/rk3566-bigtreetech-pi2.dtb" + "DTB_FILE:rockchip/rk3566-bigtreetech-pi2.dtb", + "DTO_FILES:rockchip/rk3566-*.dtbo", + "DTO_DIR:rockchip/overlays" ], "targets": [ @@ -49,6 +51,10 @@ "store_type": "dd", "block_size": "512b", "img_offset": 16384 + }, + { + "file": "u-boot-rockchip-spi.bin", + "store_type": "boot" } ], "target": [ "" ], @@ -56,11 +62,11 @@ }, { "parent": "kernel", - "version": "v6.14-rc7", + "version": "v6.16-rc2", "version_type": "tag", - "patch_dir": [ "kernel", "kernel/sunxi-6.14", "kernel/rockchip64-6.14" ], + "patch_dir": [ "kernel", "kernel/sunxi-6.16", "kernel/rockchip64-6.16" ], "config_def": "printer_defconfig", - "target": [ "clean", "Image", "modules", "dtbs", "modules_install" ], + "target": [ "Image", "modules", "dtbs", "modules_install" ], "artifacts": [ { @@ -70,10 +76,16 @@ { "file": "arch/arm64/boot/dts/%{DTB_FILE}%", "store_type": "boot", - "subdir": "dtb/rockchip" + "subdir": "dtb/rockchip", + "destdir": "dtb" + }, + { + "file": "arch/arm64/boot/dts/%{DTO_FILES}%", + "store_type": "none", + "subdir": "dtb/rockchip/overlays" } ], - "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods" + "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods/usr" } ], "install": @@ -85,13 +97,20 @@ [ { "name": "boot", - "size": "1g", + "size": "1G", "first_sector": "32768" }, { "name": "rw", - "size": "2g" + "size": "2G" } + ], + "overlays": + [ + "/dtb/%{DTO_DIR}%/rk3566-sfc-nor.dtbo", + "/dtb/%{DTO_DIR}%/rk3566-w1-gpio4-pb2.dtbo", + "/dtb/%{DTO_DIR}%/rk3566-dsi1.dtbo", + "/dtb/%{DTO_DIR}%/rk3566-pcie.dtbo" ] } } diff --git a/config/board/opi_zero2.json b/config/board/opi_zero2.json index a5debb3..21cbdcb 100644 --- a/config/board/opi_zero2.json +++ b/config/board/opi_zero2.json @@ -70,9 +70,14 @@ "file": "arch/arm64/boot/dts/allwinner/overlay/sun50i-h616*.dtbo", "store_type": "boot", "subdir": "dtb/allwinner/overlay" + }, + { + "file": "", + "store_type": "boot", + "kmods": true } ], - "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods" + "makeopts": "CROSS_COMPILE=%{CROSS_C}% ARCH=arm64 INSTALL_MOD_PATH=%{out_dir}%/kmods/usr" } ], "install": diff --git a/config/os_aarch64.json b/config/os_aarch64.json index 0677ad6..60de9d9 100644 --- a/config/os_aarch64.json +++ b/config/os_aarch64.json @@ -1,7 +1,9 @@ { "variables": [ - "USER_LOGIN:klipper" + "USER_LOGIN:klipper", + "USER_ID:1010", + "TIME_ZONE:Europe/Warsaw" ], "stage3_info": { @@ -82,15 +84,6 @@ "append": false, "lines": [ "regulatory.db" ] }, - { - "file": "/etc/portage/package.use/test", - "append": false, - "lines": - [ - "net-misc/networkmanager -bluetooth -modemmanager", - "net-misc/networkmanager -ppp" - ] - }, { "file": "/etc/portage/package.use/system", "append": false, @@ -111,7 +104,8 @@ "app-admin/sudo -sendmail", "sys-apps/systemd -dns-over-tls -gcrypt -kernel-install", "media-libs/mesa -llvm", - "sys-process/htop lm-sensors" + "sys-process/htop lm-sensors", + "net-misc/networkmanager -bluetooth -modemmanager -ppp" ] }, { @@ -134,7 +128,7 @@ "#x11-base/xorg-server suid", "cross-arm-none-eabi/newlib nano", "media-libs/libepoxy egl", - "net-misc/networkmanager -tools", + "#net-misc/networkmanager -tools", "media-libs/libglvnd X", "media-libs/libv4l bpf", "media-video/ffmpeg x264 x265", @@ -189,8 +183,17 @@ ], "oneshot": false }, + { + "file": "/etc/eixrc/00-eixrc", + "append": false, + "lines": [ + "PORTDIR_CACHE_METHOD='sqlite'", + "OVERLAY_CACHE_METHOD='sqlite'" + ] + }, { "chroot": "crossdev -s4 arm-none-eabi" }, { "chroot": "eselect news read" }, + { "chroot": "eix-update" }, { "soft_clean": "default" } ] }, @@ -198,17 +201,74 @@ { "steps": [ - { "chroot": "systemctl enable NetworkManager ntpdate sshd" }, + { + "file": "/etc/systemd/system/prepare_shutdown.service", + "append": false, + "lines": [ + "[Unit]", + "Description=Prepare a shutdown script to correctly unmount all filesystems", + "[Install]", + "WantedBy=multi-user.target", + "[Service]", + "Type=oneshot", + "ExecStart=sh -c \"mkdir -p /run/initramfs && cd /run/initramfs && tar xf /usr/shutdown.tar.xz\"" + ] + }, + { + "file": "/etc/systemd/system/sync.service", + "append": false, + "lines": [ + "[Unit]", + "Description=Sync all data", + "StartLimitIntervalSec=0", + "[Service]", + "Type=simple", + "Restart=always", + "RestartSec=10", + "User=root", + "ExecStart=/usr/local/bin/sync.sh", + "[Install]", + "WantedBy=multi-user.target" + ] + }, + { + "file": "/usr/local/bin/sync.sh", + "append": false, + "lines": [ + "#!/bin/bash", + "# regular sync to prevent data loss when direct power outage", + "while [ 1 ]; do", + " sync", + " sleep 60", + "done" + ], + "chmod": "+x" + }, + { + "file": "/etc/NetworkManager/conf.d/00-leave-original-mac.conf", + "append": false, + "lines": [ + "[device-mac-randomization]", + "wifi.scan-rand-mac-address=no", + "", + "[connection-mac-randomization]", + "ethernet.cloned-mac-address=permanent", + "wifi.cloned-mac-address=permanent" + ], + "chmod": "+x" + }, + { "chroot": "systemctl enable NetworkManager ntpdate sshd prepare_shutdown sync" }, { "sudo": "sed -i -E 's/^# (%wheel ALL)/\\1/' ./etc/sudoers" }, { "sudo": "sed -i -E 's/^#(\\S+MaxUse)=$/\\1=10M/' ./etc/systemd/journald.conf" }, { "sudo": "sed -i -E 's/^#(\\S+MaxFileSize)=$/\\1=10M/' ./etc/systemd/journald.conf" }, { "copy": [ "%{ROOT_DIR}%/files/firmware/usr", "."] }, { "sudo": "chmod u+s ./usr/bin/Xorg" }, - { "sudo": "ln -sf /usr/share/zoneinfo/Europe/Warsaw ./etc/localtime" }, - { "chroot": "useradd -m -G wheel,video,audio,disk,usb %{USER_LOGIN}% --password %{USER_LOGIN}%" }, + { "sudo": "ln -sf /usr/share/zoneinfo/%{TIME_ZONE}% ./etc/localtime" }, + { "chroot": "groupadd -g %{USER_ID}% %{USER_LOGIN}%" }, + { "chroot": "useradd -m -G wheel,video,audio,disk,usb -g %{USER_ID}% -u %{USER_ID}% %{USER_LOGIN}% --password %{USER_LOGIN}%" }, { "chroot": "echo '%{USER_LOGIN}%:%{USER_LOGIN}%' | chpasswd" }, { "chroot": "echo 'root:root' | chpasswd" }, - { "chroot": "sudo -i -u klipper python -m venv /home/%{USER_LOGIN}%/venv" }, + { "chroot": "sudo -i -u %{USER_LOGIN}% python -m venv /home/%{USER_LOGIN}%/venv" }, { "soft_clean": "bdeps" } ] } diff --git a/files/backups/excl_min.lst b/files/backups/excl_min.lst index 0a55625..6df37ee 100644 --- a/files/backups/excl_min.lst +++ b/files/backups/excl_min.lst @@ -1,12 +1,5 @@ -#home/biqu/* boot/* media/* -usr/lib/python3.13/test* -usr/lib64/perl5* -#usr/src/* var/cache/binpkgs/* var/cache/distfiles/* -#var/cache/edb/* -var/cache/eix/* var/log/*.log -#var/db/repos/* diff --git a/files/initramfs/init b/files/initramfs/init index 7f36d6a..f005b48 100644 --- a/files/initramfs/init +++ b/files/initramfs/init @@ -3,6 +3,9 @@ . /etc/init.def . /etc/init.script +CONSOLE="/dev/$(get_active_console)" +exec 0<>${CONSOLE} 1<>${CONSOLE} 2<>${CONSOLE} + run mount -t sysfs sysfs /sys -o noexec,nosuid,nodev >/dev/null run mount -t devtmpfs -o exec,nosuid,mode=0755,size=10M udev /dev run mkdir -m 0755 /dev/pts @@ -62,57 +65,34 @@ run cd "${CHROOT}" good_msg 'Mounting squashfs filesystem' upperdir="${RW_MNT}/.upper" workdir="${RW_MNT}/.work" -for i in "${RW_MNT}" "${STATIC}" "${OVERLAY}" +for i in "${RW_MNT}" "${STATIC}" "${OVERLAY}" "${upperdir}" "${workdir}" do [ ! -d "${i}" ] && run mkdir -p "${i}" done -#for i in "${upperdir}" "${workdir}" -#do -# [ ! -d "${i}" ] && run mkdir -p "${i}" -#done run mount -t squashfs -o loop,ro "${CDROOT_PATH}/${LOOP}" "${STATIC}" || run_emergency_shell -#if [ -d ${CDROOT_PATH}/modules ] -#then -# warn_msg "Adding all modules in ${CDROOT_PATH}/modules" -# for module in "${CDROOT_PATH}/modules/"*.lzm; do -# mod=${module##*/} -# mod=${mod//-/_} -# mod=${mod%.*} -# if [ ! -d "${OVERLAY}/.${mod}" ] -# then -# run mkdir -p "${OVERLAY}/.${mod}" || return -# fi -# run mount -o loop,ro "${module}" "${OVERLAY}/.${mod}" -# mod_path="${mod_path}:${OVERLAY}/.${mod}" -# # Assign variable with paths to modules mount point -# # TODO: Stop using eval -# eval ${mod}="${OVERLAY}/.${mod}" -# mods="${mods} ${mod}" -# done -#fi +if [ -d ${CDROOT_PATH}/modules ] +then + good_msg "Adding all modules in ${CDROOT_PATH}/modules" + for module in "${CDROOT_PATH}/modules/"*.lzm; do + mod=${module##*/} + mod=${mod//-/_} + mod=${mod%.*} + if [ ! -d "${OVERLAY}/.${mod}" ] + then + run mkdir -p "${OVERLAY}/.${mod}" || run_emergency_shell + fi + run mount -o loop,ro "${module}" "${OVERLAY}/.${mod}" || run_emergency_shell + mod_path="${mod_path}:${OVERLAY}/.${mod}" + # Assign variable with paths to modules mount point + mods="${mods} ${OVERLAY}/.${mod}" + done +fi run mount -t overlay overlay -o lowerdir="${STATIC}${mod_path}",upperdir="${upperdir}",workdir="${workdir}" "${NEW_ROOT}" || run_emergency_shell -for i in "${RW_MNT}" "${STATIC}" "${CDROOT_PATH}" +for i in "${RW_MNT}" "${STATIC}" "${CDROOT_PATH}" ${mods} do [ ! -d "${NEW_ROOT}${i}" ] && run mkdir -p "${NEW_ROOT}${i}" + run mount --move "${i}" "${NEW_ROOT}${i}" || run_emergency_shell done -#echo "overlay / overlay defaults 0 0" > "${NEW_ROOT}"/etc/fstab -#run mkdir -p "${NEW_ROOT}${OVERLAY}" -#run chmod 755 "${NEW_ROOT}${OVERLAY}" -#run mount --bind "${OVERLAY}" "${NEW_ROOT}${OVERLAY}" -#run mount --bind "${STATIC}" "${NEW_ROOT}${STATIC}" -#if [ -n "${mods}" ] -#then -# for i in ${mods} -# do -# run mount --bind "${OVERLAY}/.${i}" "${NEW_ROOT}/${OVERLAY}/.${i}" -# done -#fi -#[ ! -d "${NEW_ROOT}${CDROOT_PATH}" ] && mkdir -p "${NEW_ROOT}${CDROOT_PATH}" -#run mount --bind "${CDROOT_PATH}" "${NEW_ROOT}${CDROOT_PATH}" -#run mount --bind "${RW_MNT}" "${NEW_ROOT}${RW_MNT}" -run mount --move "${CDROOT_PATH}" "${NEW_ROOT}${CDROOT_PATH}" || run_emergency_shell -run mount --move "${RW_MNT}" "${NEW_ROOT}${RW_MNT}" || run_emergency_shell -run mount --move "${STATIC}" "${NEW_ROOT}${STATIC}" || run_emergency_shell #for m in ${MODULES}; do # run insmod "${NEW_ROOT}${m}" diff --git a/files/initramfs/init.script b/files/initramfs/init.script index 86212aa..5f23ac9 100644 --- a/files/initramfs/init.script +++ b/files/initramfs/init.script @@ -101,7 +101,7 @@ devicelist() { # iSeries devices DEVICES="${DEVICES} /dev/iseries/vcd*" # builtin mmc/sd card reader devices - DEVICES="${DEVICES} /dev/mmcblk* /dev/mmcblk*/*" + DEVICES="${DEVICES} /dev/mmcblk*p*/*" # fallback scanning, this might scan something twice, but it's better than # failing to boot. [ -e /proc/partitions ] && DEVICES="${DEVICES} $(awk '/([0-9]+[[:space:]]+)/{print "/dev/" $4}' /proc/partitions)" @@ -130,6 +130,21 @@ determine_fs() { echo "${_fs}" } +get_active_console() { + local active_console=console + + while [ -f /sys/class/tty/${active_console}/active ] + do + active_console=$(cat /sys/class/tty/${active_console}/active) + + # last console will be the active one, + # see https://www.kernel.org/doc/html/latest/admin-guide/serial-console.html + active_console=${active_console##* } + done + + echo ${active_console} +} + findmediamount() { # $1 = mount dir name / media name # $2 = recognition file diff --git a/files/portage/andreil/virtual/klipper/Manifest b/files/portage/andreil/virtual/klipper/Manifest index b04bdc5..3194e90 100644 --- a/files/portage/andreil/virtual/klipper/Manifest +++ b/files/portage/andreil/virtual/klipper/Manifest @@ -1 +1 @@ -EBUILD klipper-11.ebuild 656 BLAKE2B 0f9fcd5dc3939e6dc2288f6ca740457f422a2cee5d9849188cd9d823872e4712c799d56545547cec548dc7bb079ae35a1f7d586aa78860a13b349ccc2cffaa79 SHA512 ac11acfa93008f791b385bdc19dc411434c14d91560825f0b6bb77a88c7452ddbbba62a8d30cb63dca75df62eac53678e0c666c92e2d7ae0345b17fd21500915 +EBUILD klipper-11.ebuild 675 BLAKE2B afa7fe5a57391a1d7b9e1674b859e9c79d3605a5f01a986fa8464a354db0c15603d8bea67c197f38bdd1a6fd2a5c8f37713baeb5a727e99886976689a9ef3071 SHA512 5250dfb61df6d74e350543b9f0379c9807ad703b09ca84319a46a568fdcc9d52adbda2ddd41fc25a873535589631a857ab77dc993731e2b24943a16934314d49 diff --git a/files/portage/andreil/virtual/klipper/klipper-11.ebuild b/files/portage/andreil/virtual/klipper/klipper-11.ebuild index 68a85d6..3719cf3 100644 --- a/files/portage/andreil/virtual/klipper/klipper-11.ebuild +++ b/files/portage/andreil/virtual/klipper/klipper-11.ebuild @@ -29,4 +29,5 @@ RDEPEND=" media-libs/libv4l net-misc/ntp sys-apps/i2c-tools + sys-fs/f2fs-tools " diff --git a/patch/kernel/printer_btt_tft_support.patch b/patch/kernel/printer_btt_tft_support.patch new file mode 100644 index 0000000..9f0951a --- /dev/null +++ b/patch/kernel/printer_btt_tft_support.patch @@ -0,0 +1,51 @@ +diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c +index 9b2f128fd309..ae3b28cbe31f 100644 +--- a/drivers/gpu/drm/panel/panel-simple.c ++++ b/drivers/gpu/drm/panel/panel-simple.c +@@ -5470,6 +5470,36 @@ static const struct panel_desc_dsi osd101t2045_53ts = { + .lanes = 4, + }; + ++static const struct drm_display_mode btt_pitft_mode = { ++ .clock = 26101800 / 1000, ++ .hdisplay = 800, ++ .hsync_start = 800 + 59, ++ .hsync_end = 800 + 59 + 2, ++ .htotal = 800 + 59 + 2 + 52, ++ .vdisplay = 1200, ++ .vsync_start = 480 + 7, ++ .vsync_end = 480 + 7 + 2, ++ .vtotal = 480 + 7 + 2 + 21, ++ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, ++}; ++ ++static const struct panel_desc_dsi btt_pitft = { ++ .desc = { ++ .modes = &btt_pitft_mode, ++ .num_modes = 1, ++ .bpc = 8, ++ .size = { ++ .width = 217, ++ .height = 136, ++ }, ++ .connector_type = DRM_MODE_CONNECTOR_DSI, ++ }, ++ .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | ++ MIPI_DSI_MODE_LPM, ++ .format = MIPI_DSI_FMT_RGB888, ++ .lanes = 1, ++}; ++ + static const struct of_device_id dsi_of_match[] = { + { + .compatible = "auo,b080uan01", +@@ -5492,6 +5522,9 @@ static const struct of_device_id dsi_of_match[] = { + }, { + .compatible = "osddisplays,osd101t2045-53ts", + .data = &osd101t2045_53ts ++ }, { ++ .compatible = "btt-pitft", ++ .data = &btt_pitft + }, { + /* sentinel */ + } diff --git a/patch/kernel/printer_defconfig_0_common.patch b/patch/kernel/printer_defconfig_0_common.patch index 81579ee..8b08bdf 100644 --- a/patch/kernel/printer_defconfig_0_common.patch +++ b/patch/kernel/printer_defconfig_0_common.patch @@ -3,7 +3,7 @@ new file mode 100644 index 000000000000..51de9e95b7d2 --- /dev/null +++ b/arch/arm64/configs/printer_defconfig -@@ -0,0 +1,507 @@ +@@ -0,0 +1,521 @@ +CONFIG_DEFAULT_HOSTNAME="Printer" +CONFIG_LOCALVERSION="-arm64" +CONFIG_LOCALVERSION_AUTO=n @@ -43,6 +43,7 @@ index 000000000000..51de9e95b7d2 +CONFIG_PWM=y +CONFIG_ETHERNET=y +CONFIG_MMC=y ++CONFIG_RPMB=y +CONFIG_RESET_CONTROLLER=y +CONFIG_ARM64=y +CONFIG_WATCHDOG=y @@ -123,10 +124,8 @@ index 000000000000..51de9e95b7d2 +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_DEBUG_MISC=n -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -+CONFIG_MAGIC_SYSRQ_SERIAL=y -+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" ++CONFIG_MAGIC_SYSRQ=n ++CONFIG_SCHED_DEBUG=n + +#minimize +CONFIG_NR_CPUS=8 @@ -290,6 +289,10 @@ index 000000000000..51de9e95b7d2 +CONFIG_ARM64_ERRATUM_2051678=n +CONFIG_ARM64_ERRATUM_2077057=n +CONFIG_ARM64_ERRATUM_2658417=n ++CONFIG_SERIAL_8250_PCILIB=n ++CONFIG_SERIAL_8250_PCI=n ++CONFIG_SERIAL_8250_EXAR=n ++CONFIG_SERIAL_8250_PERICOM=n + +#system +CONFIG_VALIDATE_FS_PARSER=y @@ -340,6 +343,10 @@ index 000000000000..51de9e95b7d2 +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=n +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++CONFIG_F2FS_FS=y ++CONFIG_F2FS_FS_COMPRESSION=y ++CONFIG_F2FS_FS_ZSTD=n ++CONFIG_F2FS_CHECK_FS=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_ARM_ARCH_TIMER=y @@ -451,6 +458,10 @@ index 000000000000..51de9e95b7d2 +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y +CONFIG_HW_RANDOM=y ++#sensors ++CONFIG_W1=y ++CONFIG_W1_MASTER_GPIO=y ++CONFIG_W1_SLAVE_THERM=y +#systemd +CONFIG_BPF_SYSCALL=y +CONFIG_CGROUP_BPF=y @@ -489,6 +500,9 @@ index 000000000000..51de9e95b7d2 +CONFIG_DRM_DW_HDMI_I2S_AUDIO=y +CONFIG_DRM_DW_HDMI_CEC=y +CONFIG_DRM_DW_MIPI_DSI=y ++CONFIG_DRM_PANEL_SIMPLE=m ++CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m ++CONFIG_DRM_PANEL_DSI_CM=m +#network +CONFIG_PACKET=y +CONFIG_INET=y diff --git a/patch/kernel/printer_defconfig_1_plat.patch b/patch/kernel/printer_defconfig_1_plat.patch index 839d409..4014d32 100644 --- a/patch/kernel/printer_defconfig_1_plat.patch +++ b/patch/kernel/printer_defconfig_1_plat.patch @@ -3,7 +3,7 @@ new file mode 100644 index 000000000000..51de9e95b7d2 --- a/arch/arm64/configs/printer_defconfig +++ b/arch/arm64/configs/printer_defconfig -@@ -0,4 +200,204 @@ +@@ -0,4 +210,214 @@ CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_SPI_NOR=y @@ -20,13 +20,14 @@ index 000000000000..51de9e95b7d2 +CONFIG_SUN50I_A100_R_CCU=n +CONFIG_SUN50I_H6_CCU=n +CONFIG_SUN8I_H3_CCU=n ++CONFIG_SUN55I_A523_CCU=n ++CONFIG_SUN55I_A523_R_CCU=n +CONFIG_ARCH_SUNXI=y +CONFIG_DWMAC_DWC_QOS_ETH=y +CONFIG_SUNXI_CCU=y +CONFIG_NET_VENDOR_ALLWINNER=y +CONFIG_AC200_PHY=y +CONFIG_AC200_PHY_SUNXI=y -+CONFIG_USB_MUSB_HDRC=y +CONFIG_PHY_SUN4I_USB=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y @@ -52,7 +53,6 @@ index 000000000000..51de9e95b7d2 +CONFIG_SUN50I_IOMMU=y +##CONFIG_IR_SUNXI=y +CONFIG_KEYBOARD_SUN4I_LRADC=y -+CONFIG_USB_MUSB_SUNXI=y +CONFIG_SUNXI_NMI_INTC=y +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y +CONFIG_PINCTRL_SUN50I_H616=y @@ -79,7 +79,11 @@ index 000000000000..51de9e95b7d2 +##CONFIG_FB_TFT_ST7796S=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_MFD_AXP20X_I2C=y ++CONFIG_MFD_AXP20X_RSB=y +CONFIG_REGULATOR_AXP20X=y ++CONFIG_AXP20X_POWER=y ++CONFIG_AXP20X_ADC=y ++CONFIG_LEDS_AXP20X=y +#minimize +CONFIG_PINCTRL_SUN8I_H3_R=n +CONFIG_PINCTRL_SUN50I_A64=n @@ -89,6 +93,8 @@ index 000000000000..51de9e95b7d2 +CONFIG_PINCTRL_SUN50I_H5=n +CONFIG_PINCTRL_SUN50I_H6=n +CONFIG_PINCTRL_SUN50I_H6_R=n ++CONFIG_PINCTRL_SUN55I_A523=n ++CONFIG_PINCTRL_SUN55I_A523_R=n +#sound +CONFIG_SND_SOC_SUNXI_AHUB=y +CONFIG_SND_SOC_SUNXI_AHUB_DAM=y @@ -170,7 +176,8 @@ index 000000000000..51de9e95b7d2 +CONFIG_BLK_DEV_NVME=y +#EEPROM +CONFIG_EEPROM_AT24=y -+CONFIG_EEPROM_AT25=y ++CONFIG_EEPROM_AT25=n ++CONFIG_EEPROM_93CX6=n +#FB +CONFIG_DRM_SIMPLEDRM=y +CONFIG_FB=y @@ -208,3 +215,6 @@ index 000000000000..51de9e95b7d2 +#CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +#CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_BACKLIGHT_CLASS_DEVICE=y ++CONFIG_BACKLIGHT_PWM=y ++CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y diff --git a/patch/kernel/printer_dts_1_fix_pcie_enable.patch b/patch/kernel/printer_dts_1_fix_pcie_enable.patch new file mode 100644 index 0000000..003484e --- /dev/null +++ b/patch/kernel/printer_dts_1_fix_pcie_enable.patch @@ -0,0 +1,13 @@ +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +index e7ba477e75f9..5db1b3ca294d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +@@ -120,7 +120,7 @@ vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; +- gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-always-on; diff --git a/patch/kernel/printer_dts_2_fix_gmac_delays.patch b/patch/kernel/printer_dts_2_fix_gmac_delays.patch new file mode 100644 index 0000000..3f49ef9 --- /dev/null +++ b/patch/kernel/printer_dts_2_fix_gmac_delays.patch @@ -0,0 +1,13 @@ +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +index e7ba477e75f9..5db1b3ca294d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +@@ -265,6 +313,8 @@ &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; ++ tx_delay = <0x19>; ++ rx_delay = <0x05>; + status = "okay"; + }; + diff --git a/patch/kernel/printer_dts_3_fix_rk808_clkout_names.patch b/patch/kernel/printer_dts_3_fix_rk808_clkout_names.patch new file mode 100644 index 0000000..00eff78 --- /dev/null +++ b/patch/kernel/printer_dts_3_fix_rk808_clkout_names.patch @@ -0,0 +1,12 @@ +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +index e7ba477e75f9..5db1b3ca294d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +@@ -336,6 +386,7 @@ rk809: pmic@20 { + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; diff --git a/patch/kernel/printer_dts_4_disable_all_gpu_default.patch b/patch/kernel/printer_dts_4_disable_all_gpu_default.patch new file mode 100644 index 0000000..2ae4852 --- /dev/null +++ b/patch/kernel/printer_dts_4_disable_all_gpu_default.patch @@ -0,0 +1,62 @@ +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +index e7ba477e75f9..5db1b3ca294d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +@@ -280,13 +330,13 @@ rgmii_phy0: phy@0 { + + &gpu { + mali-supply = <&vdd_gpu>; +- status = "okay"; ++ status = "disabled"; + }; + + &hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; +- status = "okay"; ++ status = "disabled"; + }; + + &hdmi_in { +@@ -302,7 +352,7 @@ hdmi_out_con: endpoint { + }; + + &hdmi_sound { +- status = "okay"; ++ status = "disabled"; + }; + + &i2c0 { +@@ -575,10 +654,6 @@ tft_tp: touchscreen@48 { + }; + }; + +-&i2s0_8ch { +- status = "okay"; +-}; +- + &i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; +@@ -614,7 +689,7 @@ &pcie2x1 { + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; +- status = "okay"; ++ status = "disabled"; + }; + + &pinctrl { +@@ -889,11 +964,7 @@ &usb_host1_xhci { + &vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; ++ vop-supply = <&vdd_logic>; + }; + + &vp0 { diff --git a/patch/kernel/printer_dts_5_add_dsi1_output.patch b/patch/kernel/printer_dts_5_add_dsi1_output.patch new file mode 100644 index 0000000..adbfef3 --- /dev/null +++ b/patch/kernel/printer_dts_5_add_dsi1_output.patch @@ -0,0 +1,111 @@ +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +index e7ba477e75f9..5db1b3ca294d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +@@ -251,6 +251,54 @@ &cpu3 { + cpu-supply = <&vdd_cpu>; + }; + ++&dsi1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ dsi1_panel: panel@0 { ++ compatible = "btt-pitft"; ++ reg = <0x0>; ++ status = "disabled"; ++ vddc-supply = <&bl_dsi>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ panel_in: endpoint { ++ remote-endpoint = <&mipi_dsi_out>; ++ }; ++ }; ++ }; ++ }; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dsi1_in: port@0 { ++ reg = <0>; ++ ++ dsi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_dsi1>; ++ }; ++ }; ++ ++ dsi1_out: port@1 { ++ reg = <1>; ++ ++ mipi_dsi_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ }; ++}; ++ + &gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; +@@ -558,11 +609,39 @@ codec { + }; + + &i2c2 { ++ status = "disabled"; ++ clock-frequency = <100000>; + pinctrl-0 = <&i2c2m1_xfer>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ avdd-0v9-supply = <&vdda0v9_image>; ++ power-domains = <&power RK3568_PD_VI>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #size-cells = <0>; ++ ++ bl_dsi: regulator@45 { ++ compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; ++ reg = <0x45>; ++ status = "disabled"; ++ }; ++ ++ tp_dsi: touchscreen@38 { ++ compatible = "edt,edt-ft5306"; ++ reg = <0x38>; ++ status = "disabled"; ++ ++ vcc-supply = <&vcc3v3_sys>; ++ iovcc-supply = <&vcc_3v3>; ++ ++ touchscreen-size-x = <800>; ++ touchscreen-size-y = <480>; ++ touchscreen-inverted-x; ++ touchscreen-inverted-y; ++ }; + }; + + &i2c3 { +- status = "okay"; ++ status = "disabled"; + + tft_tp: touchscreen@48 { + compatible = "ti,tsc2007"; +@@ -902,3 +973,10 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + remote-endpoint = <&hdmi_in_vp0>; + }; + }; ++ ++&vp1 { ++ vp1_out_dsi1: endpoint@ROCKCHIP_VOP2_EP_MIPI1 { ++ reg = ; ++ remote-endpoint = <&dsi1_in_vp1>; ++ }; ++}; diff --git a/patch/kernel/printer_dts_6_fix_pi2_defaults.patch b/patch/kernel/printer_dts_6_fix_pi2_defaults.patch new file mode 100644 index 0000000..4674af7 --- /dev/null +++ b/patch/kernel/printer_dts_6_fix_pi2_defaults.patch @@ -0,0 +1,17 @@ +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts +index 7cd444caa18b..ff7df921f0f0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts +@@ -8,3 +8,12 @@ / { + model = "BigTreeTech Pi 2"; + compatible = "bigtreetech,pi2", "rockchip,rk3566"; + }; ++ ++&scmi_clk { ++ rockchip,clk-init = <1104000000>; ++}; ++ ++/* disable all - default state */ ++&fan { ++ status = "disabled"; ++}; diff --git a/patch/kernel/printer_dts_7_rk356x_add_otp.patch b/patch/kernel/printer_dts_7_rk356x_add_otp.patch new file mode 100644 index 0000000..b46a684 --- /dev/null +++ b/patch/kernel/printer_dts_7_rk356x_add_otp.patch @@ -0,0 +1,116 @@ +diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +index fd2214b6fad4..9e99309eb9bd 100644 +--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +@@ -1057,6 +1090,111 @@ rng: rng@fe388000 { + status = "disabled"; + }; + ++ otp: otp@fe38c000 { ++ compatible = "rockchip,rk3568-otp"; ++ reg = <0x00 0xfe38c000 0x00 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&cru CLK_OTPC_NS_USR>, ++ <&cru CLK_OTPC_NS_SBPI>, ++ <&cru PCLK_OTPC_NS>, ++ <&cru PCLK_OTPPHY>; ++ clock-names = "usr", "sbpi", "apb", "phy"; ++ resets = <&cru SRST_OTPPHY>; ++ reset-names = "otp_phy"; ++ ++ cpu_code: cpu-code@2 { ++ reg = <0x02 0x02>; ++ }; ++ ++ specification_serial_number: specification-serial-number@7 { ++ reg = <0x07 0x01>; ++ bits = <0x00 0x05>; ++ }; ++ ++ otp_cpu_version: cpu-version@8 { ++ reg = <0x08 0x01>; ++ bits = <0x03 0x03>; ++ }; ++ ++ mbist_vmin: mbist-vmin@9 { ++ reg = <0x09 0x01>; ++ bits = <0x00 0x04>; ++ }; ++ ++ otp_id: id@a { ++ reg = <0x0a 0x10>; ++ }; ++ ++ cpu_leakage: cpu-leakage@1a { ++ reg = <0x1a 0x01>; ++ }; ++ ++ log_leakage: log-leakage@1b { ++ reg = <0x1b 0x01>; ++ }; ++ ++ npu_leakage: npu-leakage@1c { ++ reg = <0x1c 0x01>; ++ }; ++ ++ gpu_leakage: gpu-leakage@1d { ++ reg = <0x1d 0x01>; ++ }; ++ ++ core_pvtm: core-pvtm@2a { ++ reg = <0x2a 0x02>; ++ }; ++ ++ cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e { ++ reg = <0x2e 0x01>; ++ }; ++ ++ cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f { ++ reg = <0x2f 0x01>; ++ bits = <0x00 0x04>; ++ }; ++ ++ gpu_tsadc_trim_l: npu-tsadc-trim-l@30 { ++ reg = <0x30 0x01>; ++ }; ++ ++ gpu_tsadc_trim_h: npu-tsadc-trim-h@31 { ++ reg = <0x31 0x01>; ++ bits = <0x00 0x04>; ++ }; ++ ++ tsadc_trim_base_frac: tsadc-trim-base-frac@31 { ++ reg = <0x31 0x01>; ++ bits = <0x04 0x04>; ++ }; ++ ++ tsadc_trim_base: tsadc-trim-base@32 { ++ reg = <0x32 0x01>; ++ }; ++ ++ cpu_opp_info: cpu-opp-info@36 { ++ reg = <0x36 0x06>; ++ }; ++ ++ gpu_opp_info: gpu-opp-info@3c { ++ reg = <0x3c 0x06>; ++ }; ++ ++ npu_opp_info: npu-opp-info@42 { ++ reg = <0x42 0x06>; ++ }; ++ ++ dmc_opp_info: dmc-opp-info@48 { ++ reg = <0x48 0x06>; ++ }; ++ ++ remark_spec_serial_number: remark-spec-serial-number@56 { ++ reg = <0x56 1>; ++ bits = <0 5>; ++ }; ++ }; ++ + i2s0_8ch: i2s@fe400000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe400000 0x0 0x1000>; diff --git a/patch/kernel/printer_dts_8_overlays.patch b/patch/kernel/printer_dts_8_overlays.patch new file mode 100644 index 0000000..24336db --- /dev/null +++ b/patch/kernel/printer_dts_8_overlays.patch @@ -0,0 +1,181 @@ +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 4bf84622db47..b1a8b52d33c9 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -124,6 +124,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-cb2-manta.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pcie.dtso ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-dsi1.dtso ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-hdmi.dtso ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-sfc-nor.dtso ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-w1-gpio4-pb2.dtso + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb +@@ -248,3 +253,23 @@ rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \ + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-haikou-video-demo.dtb + rk3588-tiger-haikou-haikou-video-demo-dtbs := rk3588-tiger-haikou.dtb \ + rk3588-tiger-haikou-video-demo.dtbo ++ ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2-pcie.dtb ++rk3566-bigtreetech-pi2-pcie-dtbs := rk3566-bigtreetech-pi2.dtb \ ++ rk3566-pcie.dtbo ++ ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2-dsi1.dtb ++rk3566-bigtreetech-pi2-dsi1-dtbs := rk3566-bigtreetech-pi2.dtb \ ++ rk3566-dsi1.dtbo ++ ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2-hdmi.dtb ++rk3566-bigtreetech-pi2-hdmi-dtbs := rk3566-bigtreetech-pi2.dtb \ ++ rk3566-hdmi.dtbo ++ ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2-sfc-nor.dtb ++rk3566-bigtreetech-pi2-sfc-nor-dtbs := rk3566-bigtreetech-pi2.dtb \ ++ rk3566-sfc-nor.dtbo ++ ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2-w1-gpio4-pb2.dtb ++rk3566-bigtreetech-pi2-w1-gpio4-pb2-dtbs := rk3566-bigtreetech-pi2.dtb \ ++ rk3566-w1-gpio4-pb2.dtbo +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-dsi1.dtso b/arch/arm64/boot/dts/rockchip/rk3566-dsi1.dtso +new file mode 100644 +index 000000000000..7c4790908638 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-dsi1.dtso +@@ -0,0 +1,32 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++/plugin/; ++ ++&vop { ++ status = "okay"; ++}; ++&vop_mmu { ++ status = "okay"; ++}; ++&display_subsystem { ++ status = "okay"; ++}; ++&dsi1 { ++ status = "okay"; ++}; ++&dsi1_panel { ++ status = "okay"; ++}; ++&dsi1_in_vp1 { ++ status = "okay"; ++}; ++&dsi_dphy1 { ++ status = "okay"; ++}; ++&tp_dsi { ++ status = "okay"; ++}; ++&bl_dsi { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-hdmi.dtso b/arch/arm64/boot/dts/rockchip/rk3566-hdmi.dtso +new file mode 100644 +index 000000000000..08fb4f254955 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-hdmi.dtso +@@ -0,0 +1,26 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++/plugin/; ++ ++&vop { ++ status = "okay"; ++}; ++&vop_mmu { ++ status = "okay"; ++}; ++&display_subsystem { ++ status = "okay"; ++}; ++&hdmi_sound { ++ status = "okay"; ++}; ++&i2s0_8ch { ++ status = "okay"; ++}; ++&hdmi { ++ status = "okay"; ++}; ++&hdmi_in_vp0 { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pcie.dtso b/arch/arm64/boot/dts/rockchip/rk3566-pcie.dtso +new file mode 100644 +index 000000000000..9cb6e8f03685 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-pcie.dtso +@@ -0,0 +1,8 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++/plugin/; ++ ++&pcie2x1 { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-sfc-nor.dtso b/arch/arm64/boot/dts/rockchip/rk3566-sfc-nor.dtso +new file mode 100644 +index 000000000000..011850ba18db +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-sfc-nor.dtso +@@ -0,0 +1,20 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++/plugin/; ++ ++&sfc { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ flash@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <100000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-w1-gpio4-pb2.dtso b/arch/arm64/boot/dts/rockchip/rk3566-w1-gpio4-pb2.dtso +new file mode 100644 +index 000000000000..410763276a6b +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-w1-gpio4-pb2.dtso +@@ -0,0 +1,25 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++#include ++ ++&{/} { ++ onewire: onewire { ++ compatible = "w1-gpio"; ++ gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio_w1>; ++ status = "okay"; ++ }; ++}; ++ ++&pinctrl { ++ gpio-w1 { ++ gpio_w1:gpio-w1 { ++ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; diff --git a/patch/kernel/printer_edt_ft5x06_noIRQ_support.patch b/patch/kernel/printer_edt_ft5x06_noIRQ_support.patch new file mode 100644 index 0000000..6814c34 --- /dev/null +++ b/patch/kernel/printer_edt_ft5x06_noIRQ_support.patch @@ -0,0 +1,161 @@ +diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c +index 0d7bf18e2508..535e84de038e 100644 +--- a/drivers/input/touchscreen/edt-ft5x06.c ++++ b/drivers/input/touchscreen/edt-ft5x06.c +@@ -77,6 +77,10 @@ + #define EDT_DEFAULT_NUM_X 1024 + #define EDT_DEFAULT_NUM_Y 1024 + ++#define RESET_DELAY_MS 300 /* reset deassert to I2C */ ++#define FIRST_POLL_DELAY_MS 300 /* in addition to the above */ ++#define POLL_INTERVAL_MS 17 /* 17ms = 60fps */ ++ + #define M06_REG_CMD(factory) ((factory) ? 0xf3 : 0xfc) + #define M06_REG_ADDR(factory, addr) ((factory) ? (addr) & 0x7f : (addr) & 0x3f) + +@@ -135,6 +139,7 @@ struct edt_ft5x06_ts_data { + int offset_y; + int report_rate; + int max_support_points; ++ unsigned int known_ids; + int point_len; + u8 tdata_cmd; + int tdata_len; +@@ -147,6 +152,9 @@ struct edt_ft5x06_ts_data { + enum edt_ver version; + unsigned int crc_errors; + unsigned int header_errors; ++ ++ struct timer_list timer; ++ struct work_struct work_i2c_poll; + }; + + struct edt_i2c_chip_data { +@@ -303,6 +311,10 @@ static irqreturn_t edt_ft5x06_ts_isr(int irq, void *dev_id) + u8 rdbuf[63]; + int i, type, x, y, id; + int error; ++ unsigned int active_ids = 0, known_ids = tsdata->known_ids; ++ long released_ids; ++ int b = 0; ++ unsigned int num_points; + + memset(rdbuf, 0, sizeof(rdbuf)); + error = regmap_bulk_read(tsdata->regmap, tsdata->tdata_cmd, rdbuf, +@@ -313,7 +325,16 @@ static irqreturn_t edt_ft5x06_ts_isr(int irq, void *dev_id) + goto out; + } + +- for (i = 0; i < tsdata->max_support_points; i++) { ++ /* M09/M12 does not send header or CRC */ ++ if (tsdata->version == EDT_M06) { ++ num_points = tsdata->max_support_points; ++ } else { ++ /* Register 2 is TD_STATUS, containing the number of touch ++ * points. ++ */ ++ num_points = min(rdbuf[2] & 0xf, tsdata->max_support_points); ++ } ++ for (i = 0; i < num_points; i++) { + u8 *buf = &rdbuf[i * tsdata->point_len + tsdata->tdata_offset]; + + type = buf[0] >> 6; +@@ -335,11 +356,26 @@ static irqreturn_t edt_ft5x06_ts_isr(int irq, void *dev_id) + + input_mt_slot(tsdata->input, id); + if (input_mt_report_slot_state(tsdata->input, MT_TOOL_FINGER, +- type != TOUCH_EVENT_UP)) ++ type != TOUCH_EVENT_UP)) { + touchscreen_report_pos(tsdata->input, &tsdata->prop, + x, y, true); ++ active_ids |= BIT(id); ++ } else { ++ known_ids &= ~BIT(id); ++ } + } + ++ /* One issue with the device is the TOUCH_UP message is not always ++ * returned. Instead track which ids we know about and report when they ++ * are no longer updated ++ */ ++ released_ids = known_ids & ~active_ids; ++ for_each_set_bit_from(b, &released_ids, tsdata->max_support_points) { ++ input_mt_slot(tsdata->input, b); ++ input_mt_report_slot_inactive(tsdata->input); ++ } ++ tsdata->known_ids = active_ids; ++ + input_mt_report_pointer_emulation(tsdata->input, true); + input_sync(tsdata->input); + +@@ -347,6 +383,22 @@ static irqreturn_t edt_ft5x06_ts_isr(int irq, void *dev_id) + return IRQ_HANDLED; + } + ++static void edt_ft5x06_ts_irq_poll_timer(struct timer_list *t) ++{ ++ struct edt_ft5x06_ts_data *tsdata = timer_container_of(tsdata, t, timer); ++ ++ schedule_work(&tsdata->work_i2c_poll); ++ mod_timer(&tsdata->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS)); ++} ++ ++static void edt_ft5x06_ts_work_i2c_poll(struct work_struct *work) ++{ ++ struct edt_ft5x06_ts_data *tsdata = container_of(work, ++ struct edt_ft5x06_ts_data, work_i2c_poll); ++ ++ edt_ft5x06_ts_isr(0, tsdata); ++} ++ + struct edt_ft5x06_attribute { + struct device_attribute dattr; + size_t field_offset; +@@ -1332,17 +1384,26 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client) + return error; + } + +- irq_flags = irq_get_trigger_type(client->irq); +- if (irq_flags == IRQF_TRIGGER_NONE) +- irq_flags = IRQF_TRIGGER_FALLING; +- irq_flags |= IRQF_ONESHOT; ++ if (client->irq) { ++ irq_flags = irq_get_trigger_type(client->irq); ++ if (irq_flags == IRQF_TRIGGER_NONE) ++ irq_flags = IRQF_TRIGGER_FALLING; ++ irq_flags |= IRQF_ONESHOT; + +- error = devm_request_threaded_irq(&client->dev, client->irq, +- NULL, edt_ft5x06_ts_isr, irq_flags, +- client->name, tsdata); +- if (error) { +- dev_err(&client->dev, "Unable to request touchscreen IRQ.\n"); +- return error; ++ error = devm_request_threaded_irq(&client->dev, client->irq, ++ NULL, edt_ft5x06_ts_isr, irq_flags, ++ client->name, tsdata); ++ if (error) { ++ dev_err(&client->dev, "Unable to request touchscreen IRQ.\n"); ++ return error; ++ } ++ } else { ++ INIT_WORK(&tsdata->work_i2c_poll, ++ edt_ft5x06_ts_work_i2c_poll); ++ timer_setup(&tsdata->timer, edt_ft5x06_ts_irq_poll_timer, 0); ++ tsdata->timer.expires = ++ jiffies + msecs_to_jiffies(FIRST_POLL_DELAY_MS); ++ add_timer(&tsdata->timer); + } + + error = input_register_device(input); +@@ -1364,6 +1425,10 @@ static void edt_ft5x06_ts_remove(struct i2c_client *client) + { + struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client); + ++ if (!client->irq) { ++ timer_delete(&tsdata->timer); ++ cancel_work_sync(&tsdata->work_i2c_poll); ++ } + edt_ft5x06_ts_teardown_debugfs(tsdata); + } + diff --git a/patch/kernel/rockchip64-6.14/add-board-fine3399-dts.patch b/patch/kernel/rockchip64-6.14/add-board-fine3399-dts.patch deleted file mode 100644 index fc513ff..0000000 --- a/patch/kernel/rockchip64-6.14/add-board-fine3399-dts.patch +++ /dev/null @@ -1,892 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lemon1151 -Date: Mon, 3 Jun 2024 12:32:02 +0200 -Subject: Adding support for the fine3399 board - -> X-Git-Archeology: - Revision 8f64f0508237888dd326018fa9a392346b8ec5ab: https://github.com/armbian/build/commit/8f64f0508237888dd326018fa9a392346b8ec5ab -> X-Git-Archeology: Date: Mon, 03 Jun 2024 12:32:02 +0200 -> X-Git-Archeology: From: Lemon1151 -> X-Git-Archeology: Subject: Adding support for the fine3399 board ---- - arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts | 870 ++++++++++ - 1 file changed, 870 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts b/arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-fine3399.dts -@@ -0,0 +1,870 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include -+#include -+#include -+#include "rk3399.dtsi" -+ -+ -+/ { -+ model = "Rockchip Fine3399"; -+ compatible = "rockchip,fine3399", "rockchip,rk3399"; -+ -+ aliases { -+ mmc0 = &sdio0; -+ mmc1 = &sdmmc; -+ mmc2 = &sdhci; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ dc_12v: dc-12v { -+ compatible = "regulator-fixed"; -+ regulator-name = "dc_12v"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk808 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on_h>; -+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; // bsp -+ }; -+ -+ /* switched by pmic_sleep */ -+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc1v8_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc_1v8>; -+ }; -+ -+ vcc3v3_sys: vcc3v3_pcie: vcc3v3_bl: vcc3v3-sys { // sch -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&dc_12v>; -+ }; -+ -+ vcc_sys: vcc-sys { // sch -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&dc_12v>; -+ }; -+ -+ vcc_phy: vcc-phy-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_phy_h>; -+ regulator-name = "vcc_phy"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vdd_log: vdd-log { -+ compatible = "pwm-regulator"; -+ pwms = <&pwm2 0 25000 1>; -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ leds: gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&user_led2>; -+ -+ user_led2 { -+ label = "blue:work_led"; -+ gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; // sch -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&power_key>; -+ -+ power { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; // bsp -+ label = "GPIO Key Power"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ fan0: pwm-fan { -+ compatible = "pwm-fan"; -+ cooling-levels = <0 30 60 90 120 160>; -+ #cooling-cells = <2>; -+ fan-supply = <&vcc_sys>; -+ pwms = <&pwm1 0 40000 0>; -+ }; -+ -+ // pwm3 -+ ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ir_int>; -+ }; -+ -+ adc-keys { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 1>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1750000>; -+ poll-interval = <100>; -+ -+ recovery { -+ label = "Recovery"; -+ linux,code = ; // ?? -+ press-threshold-microvolt = <0>; -+ }; -+ }; -+ -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ brightness-levels = <0 4 8 16 32 64 128 255>; -+ default-brightness-level = <5>; -+ pwms = <&pwm0 0 1000000 0>; -+ status = "okay"; -+ }; -+ -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&cpu_thermal { -+ trips { -+ cpu_warm: cpu_warm { -+ temperature = <50000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_hot: cpu_hot { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map2 { -+ trip = <&cpu_warm>; -+ cooling-device = <&fan0 THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map3 { -+ trip = <&cpu_hot>; -+ cooling-device = <&fan0 4 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ assigned-clock-parents = <&clkin_gmac>; -+ clock_in_out = "input"; -+ phy-supply = <&vcc_phy>; -+ phy-mode = "rgmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; // bsp -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ tx_delay = <0x28>; -+ rx_delay = <0x11>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&gpu_thermal { -+ trips { -+ gpu_warm: gpu_warm { -+ temperature = <50000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ gpu_hot: gpu_hot { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map1 { -+ trip = <&gpu_warm>; -+ cooling-device = <&fan0 THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map2 { -+ trip = <&gpu_hot>; -+ cooling-device = <&fan0 4 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ -+&hdmi { -+ ddc-i2c-bus = <&i2c3>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmi_cec>; -+ status = "okay"; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <168>; -+ i2c-scl-falling-time-ns = <4>; -+ status = "okay"; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk808-clkout2"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l &pmic_dvs2>; -+ system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ vcc10-supply = <&vcc3v3_sys>; -+ vcc11-supply = <&vcc3v3_sys>; -+ vcc12-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc1v8_pmu>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-name = "vdd_center"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG1 { -+ regulator-name = "vcc1v8_dvp"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v0_tp: LDO_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_tp"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_pmu: LDO_REG3 { -+ regulator-name = "vcc1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sd: LDO_REG4 { -+ regulator-name = "vcc_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG5 { -+ regulator-name = "vcca3v0_codec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-name = "vcc_1v5"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-name = "vcca1v8_codec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-name = "vcc_3v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_s3: SWITCH_REG1 { -+ regulator-name = "vcc3v3_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-name = "vcc3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&cpu_b_sleep>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpu_sleep>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+// Used for HDMI -+&i2c3 { -+ i2c-scl-rising-time-ns = <450>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; -+ -+// HDMI sound -+&i2s2 { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ -+&io_domains { -+ status = "okay"; -+ -+ bt656-supply = <&vcc_3v0>; -+ audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vcc_sd>; -+ gpio1830-supply = <&vcc_3v0>; -+}; -+ -+&pmu_io_domains { -+ status = "okay"; -+ pmu1830-supply = <&vcc_1v8>; -+}; -+ -+&pcie_phy { -+ status = "okay"; -+}; -+ -+&pcie0 { -+ ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; // sch -+ max-link-speed = <2>; -+ num-lanes = <2>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_clkreqn_cpm>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ pmic { -+ cpu_b_sleep: cpu-b-sleep { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ gpu_sleep: gpu-sleep { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ pmic_dvs2: pmic-dvs2 { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; // bsp -+ }; -+ }; -+ -+ sdio-pwrseq { -+ wifi_reg_on_h: wifi-reg-on-h { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ wifi { -+ wifi_host_wake_l: wifi-host-wake-l { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ spi2 { -+ spi2_cs0: spi2-cs0 { -+ rockchip,pins = -+ <2 RK_PB4 2 &pcfg_pull_up>; -+ }; -+ }; -+ -+ display_pin:display-pin { -+ DC_pin: dc-pin { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ reset_pin: reset-pin { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ gmac { -+ vcc_phy_h: vcc-phy-h { -+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ leds { -+ user_led2: user_led2 { -+ rockchip,pins = -+ <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ ir { -+ ir_int: ir-int { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ buttons { -+ power_key: power_key { -+ rockchip,pins = -+ <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+// TFT -+&pwm0 { -+ status = "okay"; -+}; -+ -+// FAN -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdio0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ clock-frequency = <50000000>; -+ disable-wp; -+ keep-power-in-suspend; -+ max-frequency = <50000000>; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ brcmf: wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ interrupt-names = "host-wake"; -+ brcm,drive-strength = <5>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_host_wake_l>; -+ }; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // bsp -+ clock-frequency = <150000000>; -+ disable-wp; -+ sd-uhs-sdr104; -+ max-frequency = <150000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; -+ vqmmc-supply = <&vcc_sd>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ keep-power-in-suspend; -+ non-removable; -+ status = "okay"; -+}; -+/* -+&spi1 { -+ status = "okay"; -+ -+ norflash: flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <50000000>; -+ }; -+}; -+*/ -+ -+&spi2 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_cs0>; -+ -+ st7735r@0 { -+ status = "okay"; -+ compatible = "sitronix,st7735r"; -+ reg = <0>; -+ rgb; -+ rotate = <270>; -+ width = <80>; -+ height = <160>; -+ fps = <30>; -+ buswidth = <8>; -+ backlight = <&backlight>; -+ dc-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; -+ led-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; -+ spi-max-frequency = <32000000>; -+ spi-cpol; -+ spi-cpha; -+ }; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+ -+ u2phy0_otg: otg-port { -+ status = "okay"; -+ }; -+ -+ u2phy0_host: host-port { -+ status = "okay"; -+ }; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+ -+ u2phy1_otg: otg-port { -+ status = "okay"; -+ }; -+ -+ u2phy1_host: host-port { -+ status = "okay"; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ clocks = <&rk808 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; -+ max-speed = <4000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; -+ vbat-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_1v8>; -+ }; -+}; -+ -+// Debug TTL -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; -+ -+&iep_mmu { -+ status = "okay"; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/add-board-helios64.patch b/patch/kernel/rockchip64-6.14/add-board-helios64.patch deleted file mode 100644 index ae7e582..0000000 --- a/patch/kernel/rockchip64-6.14/add-board-helios64.patch +++ /dev/null @@ -1,1020 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Aditya Prayoga -Date: Tue, 15 Sep 2020 20:04:22 +0700 -Subject: Add board Helios64 - -note: rpardini: this patch was rebased on top of 6.3.1, finally admitting -that it used to blindly overwrite the mainline dts (it was added when helios64 -was not in the tree, and thus a "file addition"). the resulting patch -is the complete set of changes actually done. - -Signed-off-by: Aditya Prayoga ---- - arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 716 ++++++++-- - 1 file changed, 635 insertions(+), 81 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -11,6 +11,10 @@ - */ - - /dts-v1/; -+#include -+#include -+#include -+#include - #include "rk3399.dtsi" - - / { -@@ -47,6 +51,25 @@ chosen { - stdout-path = "serial2:1500000n8"; - }; - -+ adc-keys { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 1>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ poll-interval = <100>; -+ -+ user2-button { -+ label = "User Button 2"; -+ linux,code = ; -+ press-threshold-microvolt = <100000>; -+ }; -+ }; -+ -+ beeper: beeper { -+ compatible = "gpio-beeper"; -+ gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; -+ }; -+ - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; -@@ -54,35 +77,119 @@ clkin_gmac: external-gmac-clock { - #clock-cells = <0>; - }; - -- fan1 { -+ fan1: p7-fan { - /* fan connected to P7 */ - compatible = "pwm-fan"; - pwms = <&pwm0 0 40000 0>; -+ cooling-min-state = <0>; -+ cooling-max-state = <3>; -+ #cooling-cells = <2>; - cooling-levels = <0 80 170 255>; - }; - -- fan2 { -+ fan2: p6-fan { - /* fan connected to P6 */ - compatible = "pwm-fan"; - pwms = <&pwm1 0 40000 0>; -+ cooling-min-state = <0>; -+ cooling-max-state = <3>; -+ #cooling-cells = <2>; - cooling-levels = <0 80 170 255>; - }; - -- leds { -+ io_leds: io-gpio-leds { -+ status = "okay"; - compatible = "gpio-leds"; - pinctrl-names = "default"; -- pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>; -+ pinctrl-0 = <&network_act>, <&usb3_act>, -+ <&sata_act>, <&sata_err_led>; -+ -+ network { -+ label = "helios64:blue:net"; -+ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "netdev"; -+ default-state = "off"; -+ }; - -- led-0 { -- label = "helios64:green:status"; -+ sata { -+ label = "helios64:blue:hdd-status"; -+ gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "disk-activity"; -+ default-state = "off"; -+ }; -+ -+ sata_err1 { -+ label = "helios64:red:ata1-err"; -+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ -+ sata_err2 { -+ label = "helios64:red:ata2-err"; -+ gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ -+ sata_err3 { -+ label = "helios64:red:ata3-err"; -+ gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ -+ sata_err4 { -+ label = "helios64:red:ata4-err"; -+ gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ -+ sata_err5 { -+ label = "helios64:red:ata5-err"; -+ gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ -+ usb3 { -+ label = "helios64:blue:usb3"; -+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; -+ trigger-sources = <&int_hub_port1>, -+ <&int_hub_port2>, -+ <&int_hub_port3>; -+ linux,default-trigger = "usbport"; -+ default-state = "off"; -+ }; -+ }; -+ -+ pwmleds { -+ compatible = "pwm-leds"; -+ status = "okay"; -+ -+ power-led { -+ label = "helios64:blue:power-status"; -+ pwms = <&pwm3 0 2000000000 0>; -+ max-brightness = <255>; -+ }; -+ }; -+ -+ system_leds: system-gpio-leds { -+ status = "okay"; -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&system_led>; -+ -+ status-led { -+ label = "helios64::status"; - gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "none"; - default-state = "on"; -+ mode = <0x23>; - }; - -- led-1 { -+ fault-led { - label = "helios64:red:fault"; - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "panic"; - default-state = "keep"; -+ mode = <0x23>; - }; - }; - -@@ -114,7 +221,7 @@ pcie_power: regulator-pcie-power { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; -- pinctrl-0 = <&pcie_pwr>; -+ pinctrl-0 = <&pcie_pwr_en>; - pinctrl-names = "default"; - regulator-boot-on; - regulator-name = "pcie_power"; -@@ -134,6 +241,7 @@ usblan_power: regulator-usblan-power { - vin-supply = <&vcc5v0_usb>; - }; - -+ /* switched by pmic_sleep */ - vcc1v8_sys_s0: regulator-vcc1v8-sys-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_sys_s0"; -@@ -144,6 +252,16 @@ vcc1v8_sys_s0: regulator-vcc1v8-sys-s0 { - vin-supply = <&vcc1v8_sys_s3>; - }; - -+ vcc0v9_s3: vcc0v9-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc0v9_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vcc3v3_sys_s3>; -+ }; -+ - vcc3v0_sd: regulator-vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; -@@ -209,6 +327,36 @@ vcc5v0_usb: regulator-vcc5v0-usb { - vin-supply = <&vcc5v0_perdev>; - }; - -+ vcc5v0_typec: vcc5v0-typec-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_vbus_en>; -+ regulator-name = "vcc5v0_typec"; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc5v0_hdd: vcc5v0-hdd { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_hdd"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin_bkup>; -+ }; -+ -+ vcc12v_hdd: vcc12v-hdd { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_hdd"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ vin-supply = <&vcc12v_dcin_bkup>; -+ }; -+ - vcc12v_dcin: regulator-vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; -@@ -227,36 +375,60 @@ vcc12v_dcin_bkup: regulator-vcc12v-dcin-bkup { - regulator-max-microvolt = <12000000>; - vin-supply = <&vcc12v_dcin>; - }; --}; - --/* -- * The system doesn't run stable with cpu freq enabled, so disallow the lower -- * frequencies until this problem is properly understood and resolved. -- */ --&cluster0_opp { -- /delete-node/ opp00; -- /delete-node/ opp01; -- /delete-node/ opp02; -- /delete-node/ opp03; -- /delete-node/ opp04; --}; -+ vdd_log: vdd-log { -+ compatible = "pwm-regulator"; -+ pwms = <&pwm2 0 25000 1>; -+ pwm-supply = <&vcc5v0_sys>; -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <830000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; - --&cluster1_opp { -- /delete-node/ opp00; -- /delete-node/ opp01; -- /delete-node/ opp02; -- /delete-node/ opp03; -- /delete-node/ opp04; -- /delete-node/ opp05; -- /delete-node/ opp06; --}; -+ gpio-charger { -+ compatible = "gpio-charger"; -+ charger-type = "mains"; -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ charge-status-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ac_present_ap>, <&charger_status>; -+ }; - --&cpu_b0 { -- cpu-supply = <&vdd_cpu_b>; --}; -+ gpio-keys { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwrbtn>, <&user1btn>, <&wake_on_lan>; -+ -+ power { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "Power"; -+ linux,code = ; -+ wakeup-source; -+ }; - --&cpu_b1 { -- cpu-supply = <&vdd_cpu_b>; -+ user1-button { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; -+ label = "User Button 1"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ hdmi_dp_sound: hdmi-dp-sound { -+ status = "okay"; -+ compatible = "rockchip,rk3399-hdmi-dp"; -+ rockchip,cpu = <&i2s2>; -+ rockchip,codec = <&cdn_dp>; -+ }; - }; - - &cpu_l0 { -@@ -275,7 +447,22 @@ &cpu_l3 { - cpu-supply = <&vdd_cpu_l>; - }; - -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cdn_dp { -+ status = "okay"; -+ extcon = <&fusb0>; -+ phys = <&tcphy0_dp>; -+}; -+ - &emmc_phy { -+ rockchip,enable-strobe-pulldown; - status = "okay"; - }; - -@@ -295,6 +482,11 @@ &gmac { - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ - &i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; -@@ -310,6 +502,7 @@ rk808: pmic@1b { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; -+ - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; -@@ -326,6 +519,19 @@ rk808: pmic@1b { - #clock-cells = <1>; - - regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-name = "vdd_center"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1000000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; -@@ -333,19 +539,48 @@ vdd_cpu_l: DCDC_REG2 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; -- - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - -+ vcc_ddr_s3: DCDC_REG3 { -+ regulator-name = "vcc_ddr_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ - vcc1v8_sys_s3: DCDC_REG4 { - regulator-name = "vcc1v8_sys_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ /* not used */ -+ vcc1v8_dvp: LDO_REG1 { -+ regulator-name = "vcc1v8_dvp"; -+ }; -+ -+ /* not used */ -+ vcc3v0_touch: LDO_REG2 { -+ regulator-name = "vcc3v0_touch"; -+ }; - -+ vcc1v8_s3: LDO_REG3 { -+ regulator-name = "vcc1v8_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; -@@ -358,25 +593,61 @@ vcc_sdio_s0: LDO_REG4 { - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; -- - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - -+ /* not used */ -+ vcca3v0_codec: LDO_REG5 { -+ regulator-name = "vcca3v0_codec"; -+ }; -+ -+ vcc1v5_s3: LDO_REG6 { -+ regulator-name = "vcc1v5_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ /* not used */ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-name = "vcca1v8_codec"; -+ }; -+ - vcc3v0_s3: LDO_REG8 { - regulator-name = "vcc3v0_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -- - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; -+ -+ vcc3v3_sys_s0: SWITCH_REG1 { -+ regulator-name = "vcc3v3_sys_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ /* not used */ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-name = "vcc3v3_s0"; -+ }; - }; - }; - -@@ -384,12 +655,33 @@ vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel1_gpio>; - regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <40000>; - regulator-always-on; - regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel2_gpio>; -+ regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { -@@ -404,17 +696,101 @@ &i2c2 { - i2c-scl-falling-time-ns = <30>; - status = "okay"; - -+ gpio-expander@20 { -+ compatible = "nxp,pca9555"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pca0_pins>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ vcc-supply = <&vcc3v3_sys_s3>; -+ }; -+ - temp@4c { - compatible = "national,lm75"; - reg = <0x4c>; - }; - }; - -+&i2c4 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ fusb0: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_int>; -+ vbus-supply = <&vcc5v0_typec>; -+ -+ connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ data-role = "dual"; -+ try-power-role = "sink"; -+ source-pdos = ; -+ sink-pdos = ; -+ op-sink-microwatt = <5000000>; -+ -+ extcon-cables = <1 2 5 6 9 10 12 44>; -+ typec-altmodes = <0xff01 1 0x001c0000 1>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usb_con_hs: endpoint { -+ remote-endpoint = <&u2phy0_typec_hs>; -+ }; -+ }; -+ port@1 { -+ reg = <1>; -+ usb_con_ss: endpoint { -+ remote-endpoint = <&tcphy0_typec_ss>; -+ }; -+ }; -+ port@2 { -+ reg = <2>; -+ usb_con_sbu: endpoint { -+ remote-endpoint = <&tcphy0_typec_dp>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+/* I2C on UEXT */ -+&i2c7 { -+ status = "okay"; -+}; -+ -+/* External I2C */ -+&i2c8 { -+ status = "okay"; -+}; -+ -+&i2s2 { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ - &io_domains { -- audio-supply = <&vcc1v8_sys_s0>; - bt656-supply = <&vcc1v8_sys_s0>; -- gpio1830-supply = <&vcc3v0_s3>; -+ audio-supply = <&vcc1v8_sys_s0>; - sdmmc-supply = <&vcc_sdio_s0>; -+ gpio1830-supply = <&vcc3v0_s3>; - status = "okay"; - }; - -@@ -427,6 +803,7 @@ &pcie0 { - max-link-speed = <2>; - num-lanes = <2>; - pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_prst &pcie_clkreqn_cpm>; - status = "okay"; - - vpcie12v-supply = <&vcc12v_dcin>; -@@ -436,36 +813,116 @@ &pcie0 { - }; - - &pinctrl { -+ buttons { -+ pwrbtn: pwrbtn { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ user1btn: usr1btn { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ charger { -+ ac_present_ap: ac-present-ap { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ charger_status: charger-status { -+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ fan { -+ fan1_sense: fan1-sense { -+ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ fan2_sense: fan2-sense { -+ rockchip,pins = <4 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ fusb30x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ fusb0_vbus_en: fusb0-vbus-en { -+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ - gmac { - gphy_reset: gphy-reset { -- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; -+ rockchip,pins = -+ <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - leds { -- sys_grn_led_on: sys-grn-led-on { -- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; -+ network_act: network-act { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ usb3_act: usb3-act { -+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ sata_act: sata-act { -+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ system_led: sys-led { -+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>, -+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - -- sys_red_led_on: sys-red-led-on { -- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; -+ sata_err_led: sata-err-led { -+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>, -+ <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>, -+ <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, -+ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>, -+ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ misc { -+ pca0_pins: pca0-pins { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wake_on_lan: wake-on-lan { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { -- pcie_pwr: pcie-pwr { -+ pcie_pwr_en: pcie-pwr-en { - rockchip,pins = - <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ -+ pcie_prst: pcie-prst { -+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; - }; - - pmic { - pmic_int_l: pmic-int-l { -- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ vsel1_gpio: vsel1-gpio { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ vsel2_gpio: vsel2-gpio { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - -- power { -+ power { - hdd_a_power_en: hdd-a-power-en { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; -@@ -485,7 +942,7 @@ usb_lan_en: usb-lan-en { - - vcc3v0-sd { - sdmmc0_pwr_h: sdmmc0-pwr-h { -- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - }; -@@ -505,10 +962,28 @@ &pwm1 { - status = "okay"; - }; - -+&pwm2 { -+ status = "okay"; -+}; -+ -+&pwm3 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcc1v8_s3>; -+ status = "okay"; -+}; -+ - &sdhci { -+ assigned-clock-rates = <150000000>; - bus-width = <8>; - mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ supports-emmc; - non-removable; -+ disable-wp; - vqmmc-supply = <&vcc1v8_sys_s0>; - status = "okay"; - }; -@@ -516,8 +991,9 @@ &sdhci { - &sdmmc { - bus-width = <4>; - cap-sd-highspeed; -- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // TODO: verify what needs to be done to use implicit CD definition - disable-wp; -+ sd-uhs-sdr104; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc3v0_sd>; -@@ -546,6 +1022,27 @@ &spi5 { - status = "okay"; - }; - -+&tcphy0 { -+ extcon = <&fusb0>; -+ status = "okay"; -+}; -+ -+&tcphy0_dp { -+ port { -+ tcphy0_typec_dp: endpoint { -+ remote-endpoint = <&usb_con_sbu>; -+ }; -+ }; -+}; -+ -+&tcphy0_usb3 { -+ port { -+ tcphy0_typec_ss: endpoint { -+ remote-endpoint = <&usb_con_ss>; -+ }; -+ }; -+}; -+ - &tcphy1 { - /* phy for &usbdrd_dwc3_1 */ - status = "okay"; -@@ -559,61 +1056,118 @@ &tsadc { - status = "okay"; - }; - --&u2phy1 { -+&u2phy0 { - status = "okay"; - -- otg-port { -- /* phy for &usbdrd_dwc3_1 */ -+ u2phy0_otg: otg-port { -+ status = "okay"; -+ }; -+ -+ u2phy0_host: host-port { - phy-supply = <&vcc5v0_usb>; - status = "okay"; - }; -+ -+ port { -+ u2phy0_typec_hs: endpoint { -+ remote-endpoint = <&usb_con_hs>; -+ }; -+ }; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+ -+ u2phy1_otg: otg-port { -+ status = "okay"; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer>; -+ status = "okay"; - }; - - &uart2 { - status = "okay"; - }; - -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ status = "okay"; -+ dr_mode = "otg"; -+}; -+ - &usbdrd3_1 { - status = "okay"; -+}; - -- usb@fe900000 { -- dr_mode = "host"; -- status = "okay"; -+&usbdrd_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ int_hub: hub@1 { -+ compatible = "usb2109,0815"; -+ reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - -- hub@1 { -- compatible = "usb2109,0815"; -+ int_hub_port1: port@1 { - reg = <1>; -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@1 { -- reg = <1>; -- #trigger-source-cells = <0>; -- }; -+ #trigger-source-cells = <0>; -+ }; - -- port@2 { -- reg = <2>; -- #trigger-source-cells = <0>; -- }; -+ int_hub_port2: port@2 { -+ reg = <2>; -+ #trigger-source-cells = <0>; -+ }; - -- port@3 { -- reg = <3>; -- #trigger-source-cells = <0>; -- }; -+ int_hub_port3: port@3 { -+ reg = <3>; -+ #trigger-source-cells = <0>; -+ }; - -- device@4 { -- compatible = "usbbda,8156"; -- reg = <4>; -- #address-cells = <2>; -- #size-cells = <0>; -+ usb_lan: device@4 { -+ compatible = "usbbda,8156"; -+ reg = <4>; -+ #address-cells = <2>; -+ #size-cells = <0>; - -- interface@0 { /* interface 0 of configuration 1 */ -- compatible = "usbifbda,8156.config1.0"; -- reg = <0 1>; -- }; -+ interface@0 { /* interface 0 of configuration 1 */ -+ compatible = "usbifbda,8156.config1.0"; -+ reg = <0 1>; - }; - }; - }; - }; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-firefly-rk3399-dts.patch b/patch/kernel/rockchip64-6.14/board-firefly-rk3399-dts.patch deleted file mode 100644 index 1213ad5..0000000 --- a/patch/kernel/rockchip64-6.14/board-firefly-rk3399-dts.patch +++ /dev/null @@ -1,320 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: chainsx -Date: Fri, 17 May 2024 14:33:21 +0100 -Subject: [ARCHEOLOGY] firefly-rk3399: move to rockchip64 family - -> X-Git-Archeology: - Revision aa6ed7ce328617cf7eefa21d7e5f0a750d3a3477: https://github.com/armbian/build/commit/aa6ed7ce328617cf7eefa21d7e5f0a750d3a3477 -> X-Git-Archeology: Date: Fri, 17 May 2024 14:33:21 +0100 -> X-Git-Archeology: From: chainsx -> X-Git-Archeology: Subject: firefly-rk3399: move to rockchip64 family -> X-Git-Archeology: -> X-Git-Archeology: - Revision 7e574bd484de7238f0aba41dea5f3b5fb4e4fe8f: https://github.com/armbian/build/commit/7e574bd484de7238f0aba41dea5f3b5fb4e4fe8f -> X-Git-Archeology: Date: Sat, 18 May 2024 09:47:04 +0100 -> X-Git-Archeology: From: chainsx -> X-Git-Archeology: Subject: firefly-rk3399: fix patch -> X-Git-Archeology: -> X-Git-Archeology: - Revision 5fe762e0a344f3487d8ff007f571b2407c817a25: https://github.com/armbian/build/commit/5fe762e0a344f3487d8ff007f571b2407c817a25 -> X-Git-Archeology: Date: Sun, 19 May 2024 19:41:24 +0200 -> X-Git-Archeology: From: chainsx -> X-Git-Archeology: Subject: Optimize the kernel device tree patch for rk3399-firefly. -> X-Git-Archeology: -> X-Git-Archeology: - Revision 69ca2492628b2aae217c33fde921b3840851eb14: https://github.com/armbian/build/commit/69ca2492628b2aae217c33fde921b3840851eb14 -> X-Git-Archeology: Date: Wed, 05 Jun 2024 22:18:24 +0200 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip64: bump edge kernel to 6.9 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 4ae0a958146810117050d0dbd359b99691a0fa0c: https://github.com/armbian/build/commit/4ae0a958146810117050d0dbd359b99691a0fa0c -> X-Git-Archeology: Date: Mon, 22 Jul 2024 19:17:52 +0200 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip64: bump edge kernel to 6.10 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 133 +++++++--- - 1 file changed, 103 insertions(+), 30 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts -@@ -216,7 +216,7 @@ vcc5v0_host: regulator-vcc5v0-host { - enable-active-high; - gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; -- pinctrl-0 = <&vcc5v0_host_en>; -+ pinctrl-0 = <&vcc5v0_host_en &hub_rst>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc_sys>; -@@ -235,8 +235,11 @@ vcc5v0_typec: regulator-vcc5v0-typec { - - vcc_sys: regulator-vcc-sys { - compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_sys_en>; - regulator-name = "vcc_sys"; -- regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -@@ -253,6 +256,27 @@ vdd_log: regulator-vdd-log { - regulator-min-microvolt = <430000>; - regulator-max-microvolt = <1400000>; - }; -+ -+ vcca_0v9: vcca-0v9 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vcc3v3_3g: vcc3v3-3g-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_3g_drv>; -+ regulator-name = "vcc3v3_3g"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; - }; - - &cpu_l0 { -@@ -305,6 +329,8 @@ &gpu { - }; - - &hdmi { -+ avdd-0v9-supply = <&vcca0v9_hdmi>; -+ avdd-1v8-supply = <&vcca1v8_hdmi>; - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; -@@ -329,18 +355,18 @@ rk808: pmic@1b { - system-power-controller; - wakeup-source; - -- vcc1-supply = <&vcc_sys>; -- vcc2-supply = <&vcc_sys>; -- vcc3-supply = <&vcc_sys>; -- vcc4-supply = <&vcc_sys>; -- vcc6-supply = <&vcc_sys>; -- vcc7-supply = <&vcc_sys>; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; -- vcc9-supply = <&vcc_sys>; -- vcc10-supply = <&vcc_sys>; -- vcc11-supply = <&vcc_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ vcc10-supply = <&vcc3v3_sys>; -+ vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; -- vddio-supply = <&vcc1v8_pmu>; -+ vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { -@@ -388,8 +414,8 @@ regulator-state-mem { - }; - }; - -- vcc1v8_dvp: LDO_REG1 { -- regulator-name = "vcc1v8_dvp"; -+ vcca1v8_codec: LDO_REG1 { -+ regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; -@@ -399,12 +425,12 @@ regulator-state-mem { - }; - }; - -- vcc2v8_dvp: LDO_REG2 { -- regulator-name = "vcc2v8_dvp"; -+ vcca1v8_hdmi: LDO_REG2 { -+ regulator-name = "vcca1v8_hdmi"; - regulator-always-on; - regulator-boot-on; -- regulator-min-microvolt = <2800000>; -- regulator-max-microvolt = <2800000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; -@@ -457,12 +483,12 @@ regulator-state-mem { - }; - }; - -- vcca1v8_codec: LDO_REG7 { -- regulator-name = "vcca1v8_codec"; -+ vcca0v9_hdmi: LDO_REG7 { -+ regulator-name = "vcca0v9_hdmi"; - regulator-always-on; - regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; -@@ -503,14 +529,16 @@ regulator-state-mem { - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; -- fcs,suspend-voltage-selector = <0>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel1_pin>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; -- vin-supply = <&vcc_sys>; -+ vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; -@@ -521,13 +549,15 @@ vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel2_pin>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; -- vin-supply = <&vcc_sys>; -+ vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; -@@ -564,7 +594,7 @@ &i2c4 { - status = "okay"; - - fusb0: typec-portc@22 { -- compatible = "fcs,fusb302"; -+ compatible = "fairchild,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; -@@ -637,7 +667,7 @@ &i2s2 { - &io_domains { - status = "okay"; - -- bt656-supply = <&vcc1v8_dvp>; -+ bt656-supply = <&vcc_3v0>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -@@ -651,7 +681,10 @@ &pcie0 { - ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; -- pinctrl-0 = <&pcie_clkreqn_cpm>; -+ pinctrl-0 = <&pcie_perst>; -+ vpcie3v3-supply = <&vcc3v3_pcie>; -+ vpcie1v8-supply = <&vcc1v8_pmu>; -+ vpcie0v9-supply = <&vcca_0v9>; - status = "okay"; - }; - -@@ -703,6 +736,10 @@ pcie_pwr_en: pcie-pwr-en { - pcie_3g_drv: pcie-3g-drv { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; -+ -+ pcie_perst: pcie-perst { -+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; - }; - - pmic { -@@ -741,6 +778,14 @@ usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ -+ vcc_sys_en: vcc-sys-en { -+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ hub_rst: hub-rst { -+ rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; -+ }; - }; - - wifi { -@@ -748,6 +793,20 @@ wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -+ -+ bt { -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_reg_on_h: bt-reg-on-h { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; - }; - - &pwm0 { -@@ -787,7 +846,7 @@ brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio0>; -- interrupts = ; -+ interrupts = ; - interrupt-names = "host-wake"; - brcm,drive-strength = <5>; - pinctrl-names = "default"; -@@ -884,8 +943,22 @@ u2phy1_host: host-port { - - &uart0 { - pinctrl-names = "default"; -- pinctrl-0 = <&uart0_xfer &uart0_cts>; -+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; - status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ clocks = <&rk808 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; -+ max-speed = <4000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; -+ vbat-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_1v8>; -+ }; - }; - - &uart2 { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-helios64-dts-fix-stability-issues.patch b/patch/kernel/rockchip64-6.14/board-helios64-dts-fix-stability-issues.patch deleted file mode 100644 index b1f2aca..0000000 --- a/patch/kernel/rockchip64-6.14/board-helios64-dts-fix-stability-issues.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Aditya Prayoga -Date: Thu, 4 Mar 2021 10:39:40 +0700 -Subject: Attempt to improve stability on Helios64 (#2680) - -> X-Git-Archeology: > recovered message: > * Adjust the RK808 buck step to improve stability -> X-Git-Archeology: > recovered message: > * Adjust vdd_log and enable vdd_center init voltage -> X-Git-Archeology: > recovered message: > For some reason, regulator-init-microvolt property under PMIC does not applied. Set the voltage on board file. -> X-Git-Archeology: - Revision eefad69215557708b151a5d9244617a4ffd1281c: https://github.com/armbian/build/commit/eefad69215557708b151a5d9244617a4ffd1281c -> X-Git-Archeology: Date: Thu, 04 Mar 2021 10:39:40 +0700 -> X-Git-Archeology: From: Aditya Prayoga -> X-Git-Archeology: Subject: Attempt to improve stability on Helios64 (#2680) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -502,6 +502,7 @@ rk808: pmic@1b { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; -+ max-buck-steps-per-change = <4>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-helios64-remove-pcie-ep-gpios.patch b/patch/kernel/rockchip64-6.14/board-helios64-remove-pcie-ep-gpios.patch deleted file mode 100644 index 0882459..0000000 --- a/patch/kernel/rockchip64-6.14/board-helios64-remove-pcie-ep-gpios.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Aditya Prayoga -Date: Tue, 15 Sep 2020 13:42:02 +0700 -Subject: Remove PCIE ep-gpios from Helios64 - -Signed-off-by: Aditya Prayoga ---- - arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -800,7 +800,6 @@ &pcie_phy { - }; - - &pcie0 { -- ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; - num-lanes = <2>; - pinctrl-names = "default"; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-nanopc-t4-add-typec-dp.patch b/patch/kernel/rockchip64-6.14/board-nanopc-t4-add-typec-dp.patch deleted file mode 100644 index 7a8a520..0000000 --- a/patch/kernel/rockchip64-6.14/board-nanopc-t4-add-typec-dp.patch +++ /dev/null @@ -1,147 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: tonymac32 -Date: Wed, 17 Feb 2021 00:54:00 -0500 -Subject: Patching something - -Signed-off-by: tonymac32 ---- - arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts | 96 ++++++++++ - 1 file changed, 96 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -@@ -9,6 +9,7 @@ - */ - - /dts-v1/; -+#include - #include "rk3399-nanopi4.dtsi" - - / { -@@ -66,6 +67,12 @@ fan: pwm-fan { - }; - }; - -+&cdn_dp { -+ status = "okay"; -+ extcon = <&fusb0>; -+ phys = <&tcphy0_dp>; -+}; -+ - &cpu_thermal { - trips { - cpu_warm: cpu_warm { -@@ -94,6 +101,50 @@ map3 { - }; - }; - -+&fusb0 { -+ -+ connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ data-role = "dual"; -+ try-power-role = "sink"; -+ source-pdos = ; -+ sink-pdos = ; -+ op-sink-microwatt = <5000000>; -+ -+ extcon-cables = <1 2 5 6 9 10 12 44>; -+ typec-altmodes = <0xff01 1 0x001c0000 1>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ port@0 { -+ reg = <0>; -+ usb_con_hs: endpoint { -+ remote-endpoint = -+ <&u2phy0_typec_hs>; -+ }; -+ }; -+ port@1 { -+ reg = <1>; -+ -+ usb_con_ss: endpoint { -+ remote-endpoint = -+ <&tcphy0_typec_ss>; -+ }; -+ }; -+ port@2 { -+ reg = <2>; -+ usb_con_dp: endpoint { -+ remote-endpoint = -+ <&tcphy0_typec_dp>; -+ }; -+ }; -+ }; -+ }; -+}; -+ - &pcie0 { - ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; -@@ -114,12 +165,57 @@ &sdhci { - mmc-hs400-enhanced-strobe; - }; - -+&tcphy0 { -+ extcon = <&fusb0>; -+ status = "okay"; -+}; -+ -+&tcphy0_dp { -+ port { -+ tcphy0_typec_dp: endpoint { -+ remote-endpoint = <&usb_con_dp>; -+ }; -+ }; -+}; -+ -+&tcphy0_usb3 { -+ port { -+ tcphy0_typec_ss: endpoint { -+ remote-endpoint = <&usb_con_ss>; -+ }; -+ }; -+}; -+ -+&u2phy0 { -+ extcon = <&fusb0>; -+}; -+ - &u2phy0_host { - phy-supply = <&vcc5v0_host0>; -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+ -+ port { -+ u2phy0_typec_hs: endpoint { -+ remote-endpoint = <&usb_con_hs>; -+ }; -+ }; - }; - - &u2phy1_host { - phy-supply = <&vcc5v0_host0>; -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ extcon = <&fusb0>; - }; - - &vcc5v0_sys { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-nanopi-m4v2-dts-add-sound-card.patch b/patch/kernel/rockchip64-6.14/board-nanopi-m4v2-dts-add-sound-card.patch deleted file mode 100644 index 0479354..0000000 --- a/patch/kernel/rockchip64-6.14/board-nanopi-m4v2-dts-add-sound-card.patch +++ /dev/null @@ -1,190 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Piotr Szczepanik -Date: Thu, 28 Nov 2019 22:29:54 +0000 -Subject: [ARCHEOLOGY] Initial addition of NanoPi M4V2 - -> X-Git-Archeology: - Revision c4eecbcef0d4dc499baf0155449e71dc774bc7c4: https://github.com/armbian/build/commit/c4eecbcef0d4dc499baf0155449e71dc774bc7c4 -> X-Git-Archeology: Date: Thu, 28 Nov 2019 22:29:54 +0000 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Initial addition of NanoPi M4V2 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 40a3d4ecb9a75c17183e2129491b7bc03060a315: https://github.com/armbian/build/commit/40a3d4ecb9a75c17183e2129491b7bc03060a315 -> X-Git-Archeology: Date: Sun, 17 May 2020 18:42:24 +0200 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Fixed rt5651 codec probing after its driver was changed to module (#1969) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 -> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 -> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) -> X-Git-Archeology: -> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e -> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 401fb1fde426c93121c4639b34a450d8ff551c85: https://github.com/armbian/build/commit/401fb1fde426c93121c4639b34a450d8ff551c85 -> X-Git-Archeology: Date: Sat, 20 Nov 2021 19:49:22 +0100 -> X-Git-Archeology: From: simple <991605149@qq.com> -> X-Git-Archeology: Subject: Fixed rt5651 codec build module (#3270) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 51 ++++++++++ - sound/soc/rockchip/Kconfig | 9 ++ - 2 files changed, 60 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi -@@ -132,6 +132,27 @@ status_led: led-0 { - }; - }; - -+ rt5651-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "realtek,rt5651-codec"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,widgets = -+ "Microphone", "Mic Jack", -+ "Headphone", "Headphone Jack"; -+ simple-audio-card,routing = -+ "Mic Jack", "micbias1", -+ "IN1P", "Mic Jack", -+ "Headphone Jack", "HPOL", -+ "Headphone Jack", "HPOR"; -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1>; -+ }; -+ simple-audio-card,codec { -+ sound-dai = <&rt5651>; -+ }; -+ }; -+ - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; -@@ -216,6 +237,10 @@ &hdmi_sound { - status = "okay"; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; -@@ -463,6 +488,16 @@ &i2c1 { - i2c-scl-rising-time-ns = <150>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; -+ -+ rt5651: rt5651@1a { -+ compatible = "realtek,rt5651"; -+ reg = <0x1a>; -+ clocks = <&cru SCLK_I2S_8CH_OUT>; -+ clock-names = "mclk"; -+ hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; -+ // spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; -+ #sound-dai-cells = <0>; -+ }; - }; - - &i2c2 { -@@ -494,6 +529,16 @@ &i2s2 { - status = "okay"; - }; - -+&i2s1 { -+ rockchip,playback-channels = <8>; -+ rockchip,capture-channels = <8>; -+ status = "okay"; -+}; -+ -+&i2s2 { -+ status = "okay"; -+}; -+ - &io_domains { - bt656-supply = <&vcc_1v8>; - audio-supply = <&vcca1v8_codec>; -@@ -759,3 +804,9 @@ &vopl { - &vopl_mmu { - status = "okay"; - }; -+ -+&spdif { -+ i2c-scl-rising-time-ns = <450>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; -diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig -index 111111111111..222222222222 100644 ---- a/sound/soc/rockchip/Kconfig -+++ b/sound/soc/rockchip/Kconfig -@@ -65,6 +65,15 @@ config SND_SOC_ROCKCHIP_RT5645 - Say Y or M here if you want to add support for SoC audio on Rockchip - boards using the RT5645/RT5650 codec, such as Veyron. - -+config SND_SOC_ROCKCHIP_RT5651 -+ tristate "ASoC support for Rockchip boards using a RT5651 codec" -+ depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK -+ select SND_SOC_ROCKCHIP_I2S -+ select SND_SOC_RT5651 -+ help -+ Say Y or M here if you want to add support for SoC audio on Rockchip -+ boards using the RT5651 codec, such as FriendlyARM's Nano{Pi,PC} family. -+ - config SND_SOC_RK3288_HDMI_ANALOG - tristate "ASoC support multiple codecs for Rockchip RK3288 boards" - depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-nanopi-r2c-plus.patch b/patch/kernel/rockchip64-6.14/board-nanopi-r2c-plus.patch deleted file mode 100644 index cadf9eb..0000000 --- a/patch/kernel/rockchip64-6.14/board-nanopi-r2c-plus.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Thu, 31 Aug 2023 11:41:37 +0200 -Subject: [ARCHEOLOGY] rockchip64: bump rockchip64-edge kernel to 6.5 - -> X-Git-Archeology: - Revision 8254411054a99f9750770bb6055facfbdedacbba: https://github.com/armbian/build/commit/8254411054a99f9750770bb6055facfbdedacbba -> X-Git-Archeology: Date: Thu, 31 Aug 2023 11:41:37 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: rockchip64: bump rockchip64-edge kernel to 6.5 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts -@@ -28,7 +28,7 @@ &emmc { - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -- vmmc-supply = <&vcc_io_33>; -+ vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; - }; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-nanopi-r2s.patch b/patch/kernel/rockchip64-6.14/board-nanopi-r2s.patch deleted file mode 100644 index 7dd1992..0000000 --- a/patch/kernel/rockchip64-6.14/board-nanopi-r2s.patch +++ /dev/null @@ -1,720 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Sat, 7 Jan 2023 11:59:47 +0000 -Subject: rockchip64: consolidate nanopi r2s device trees - ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi | 472 +++++++--- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi | 6 +- - 2 files changed, 318 insertions(+), 160 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi -@@ -1,116 +1,155 @@ - // SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* -- * Copyright (c) 2020 David Bauer -+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - - /dts-v1/; -- --#include --#include -+#include "rk3328-dram-default-timing.dtsi" - #include "rk3328.dtsi" - - / { -+ model = "FriendlyElec boards based on Rockchip RK3328"; -+ compatible = "friendlyelec,nanopi-r2", -+ "rockchip,rk3328"; -+ - aliases { - ethernet0 = &gmac2io; -- ethernet1 = &rtl8153; -- mmc0 = &sdmmc; -+ ethernet1 = &r8153; - }; - - chosen { -+ bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0"; - stdout-path = "serial2:1500000n8"; - }; - -- gmac_clk: gmac-clock { -+ gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - -- keys { -- compatible = "gpio-keys"; -- pinctrl-0 = <&reset_button_pin>; -- pinctrl-names = "default"; -- -- key-reset { -- label = "reset"; -- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; -- linux,code = ; -- debounce-interval = <50>; -- }; -+ mach: board { -+ compatible = "friendlyelec,board"; -+ machine = "NANOPI-R2"; -+ hwrev = <255>; -+ model = "NanoPi R2 Series"; -+ nvmem-cells = <&efuse_id>, <&efuse_cpu_version>; -+ nvmem-cell-names = "id", "cpu-version"; - }; - -- leds { -+ leds: gpio-leds { - compatible = "gpio-leds"; -- pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - pinctrl-names = "default"; -+ pinctrl-0 =<&leds_gpio>; -+ status = "disabled"; - -- lan_led: led-0 { -- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:lan"; -- }; -- -- sys_led: led-1 { -+ led@1 { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:red:sys"; -- default-state = "on"; -- }; -- -- wan_led: led-2 { -- gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:wan"; -+ label = "status_led"; -+ linux,default-trigger = "heartbeat"; -+ linux,default-trigger-delay-ms = <0>; - }; - }; - -- vcc_io_sdio: regulator-sdmmcio { -- compatible = "regulator-gpio"; -- enable-active-high; -- gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; -- pinctrl-0 = <&sdio_vcc_pin>; -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk805 1>; -+ clock-names = "ext_clock"; - pinctrl-names = "default"; -- regulator-name = "vcc_io_sdio"; -- regulator-always-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <3300000>; -- regulator-settling-time-us = <5000>; -- regulator-type = "voltage"; -- startup-delay-us = <2000>; -- states = <1800000 0x1>, -- <3300000 0x0>; -- vin-supply = <&vcc_io_33>; -+ pinctrl-0 = <&wifi_enable_h>; -+ -+ /* -+ * On the module itself this is one of these (depending -+ * on the actual card populated): -+ * - SDIO_RESET_L_WL_REG_ON -+ * - PDN (power down when low) -+ */ -+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - }; - - vcc_sd: regulator-sdmmc { - compatible = "regulator-fixed"; -- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -- pinctrl-0 = <&sdmmc0m1_pin>; -+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; -- regulator-name = "vcc_sd"; -+ pinctrl-0 = <&sdmmc0m1_pin>; - regulator-boot-on; -+ regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc_io_33>; -+ vin-supply = <&vcc_io>; - }; - -- vdd_5v: regulator-vdd-5v { -+ vccio_sd: sdmmcio-regulator { -+ compatible = "regulator-gpio"; -+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; -+ states = <1800000 0x1 -+ 3300000 0x0>; -+ regulator-name = "vccio_sd"; -+ regulator-type = "voltage"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ vin-supply = <&vcc_io>; -+ startup-delay-us = <2000>; -+ regulator-settling-time-us = <5000>; -+ enable-active-high; -+ status = "disabled"; -+ }; -+ -+ vcc_sys: vcc-sys { - compatible = "regulator-fixed"; -- regulator-name = "vdd_5v"; -+ regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - -- vdd_5v_lan: regulator-vdd-5v-lan { -+ vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; -- pinctrl-0 = <&lan_vdd_pin>; -- pinctrl-names = "default"; -- regulator-name = "vdd_5v_lan"; -+ regulator-name = "vcc_phy"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vcc_host_vbus: host-vbus-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_host_vbus"; - regulator-always-on; - regulator-boot-on; -- vin-supply = <&vdd_5v>; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ /delete-node/ dmc-opp-table; -+ -+ dmc_opp_table: dmc_opp_table { -+ compatible = "operating-points-v2"; -+ -+ opp-786000000 { -+ opp-hz = /bits/ 64 <786000000>; -+ opp-microvolt = <1075000 1075000 1200000>; -+ }; -+ opp-798000000 { -+ opp-hz = /bits/ 64 <798000000>; -+ opp-microvolt = <1075000 1075000 1200000>; -+ }; -+ opp-840000000 { -+ opp-hz = /bits/ 64 <840000000>; -+ opp-microvolt = <1075000 1075000 1200000>; -+ }; -+ opp-924000000 { -+ opp-hz = /bits/ 64 <924000000>; -+ opp-microvolt = <1100000 1100000 1200000>; -+ }; -+ opp-1056000000 { -+ opp-hz = /bits/ 64 <1056000000>; -+ opp-microvolt = <1175000 1175000 1200000>; -+ }; - }; - }; - -@@ -118,30 +157,57 @@ &cpu0 { - cpu-supply = <&vdd_arm>; - }; - --&cpu1 { -- cpu-supply = <&vdd_arm>; -+&dfi { -+ status = "okay"; - }; - --&cpu2 { -- cpu-supply = <&vdd_arm>; -+&dmc { -+ center-supply = <&vdd_logic>; -+ ddr_timing = <&ddr_timing>; -+ status = "okay"; - }; - --&cpu3 { -- cpu-supply = <&vdd_arm>; -+&emmc { -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ max-frequency = <150000000>; -+ mmc-hs200-1_8v; -+ no-sd; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -+ vmmc-supply = <&vcc_io>; -+ vqmmc-supply = <&vcc18_emmc>; -+ status = "okay"; - }; - --&display_subsystem { -+&gmac2phy { -+ phy-supply = <&vcc_phy>; -+ clock_in_out = "output"; -+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; -+ assigned-clock-rate = <50000000>; -+ assigned-clocks = <&cru SCLK_MAC2PHY>; -+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - status = "disabled"; - }; - - &gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -- assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; -- phy-mode = "rgmii"; -- phy-supply = <&vcc_io_33>; -- pinctrl-0 = <&rgmiim1_pins>; - pinctrl-names = "default"; -+ pinctrl-0 = <&rgmiim1_pins>; -+ phy-handle = <&rtl8211e>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_phy>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 30000>; -+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,rxpbl = <0x4>; -+ snps,txpbl = <0x4>; -+ tx_delay = <0x24>; -+ rx_delay = <0x18>; -+ status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; -@@ -153,36 +219,35 @@ mdio { - &i2c1 { - status = "okay"; - -- rk805: pmic@18 { -+ rk805: rk805@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; -- interrupt-parent = <&gpio1>; -- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-parent = <&gpio2>; -+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; -- pinctrl-0 = <&pmic_int_l>; - pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - -- vcc1-supply = <&vdd_5v>; -- vcc2-supply = <&vdd_5v>; -- vcc3-supply = <&vdd_5v>; -- vcc4-supply = <&vdd_5v>; -- vcc5-supply = <&vcc_io_33>; -- vcc6-supply = <&vdd_5v>; -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_io>; -+ vcc6-supply = <&vcc_io>; - - regulators { -- vdd_log: DCDC_REG1 { -- regulator-name = "vdd_log"; -- regulator-always-on; -- regulator-boot-on; -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-init-microvolt = <1075000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; -- regulator-ramp-delay = <12500>; -- -+ regulator-always-on; -+ regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; -@@ -191,12 +256,11 @@ regulator-state-mem { - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; -- regulator-always-on; -- regulator-boot-on; -+ regulator-init-microvolt = <1225000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; -- regulator-ramp-delay = <12500>; -- -+ regulator-always-on; -+ regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; -@@ -207,19 +271,17 @@ vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; -- - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - -- vcc_io_33: DCDC_REG4 { -- regulator-name = "vcc_io_33"; -- regulator-always-on; -- regulator-boot-on; -+ vcc_io: DCDC_REG4 { -+ regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -- -+ regulator-always-on; -+ regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; -@@ -228,11 +290,10 @@ regulator-state-mem { - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; -- regulator-always-on; -- regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -- -+ regulator-always-on; -+ regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; -@@ -241,11 +302,10 @@ regulator-state-mem { - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; -- regulator-always-on; -- regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -- -+ regulator-always-on; -+ regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; -@@ -254,11 +314,10 @@ regulator-state-mem { - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; -- regulator-always-on; -- regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; -- -+ regulator-always-on; -+ regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; -@@ -269,20 +328,21 @@ regulator-state-mem { - }; - - &io_domains { -- pmuio-supply = <&vcc_io_33>; -- vccio1-supply = <&vcc_io_33>; -- vccio2-supply = <&vcc18_emmc>; -- vccio3-supply = <&vcc_io_sdio>; -- vccio4-supply = <&vcc_18>; -- vccio5-supply = <&vcc_io_33>; -- vccio6-supply = <&vcc_io_33>; - status = "okay"; -+ -+ vccio1-supply = <&vcc_io>; -+ vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_io>; -+ vccio4-supply = <&vcc_io>; -+ vccio5-supply = <&vcc_io>; -+ vccio6-supply = <&vcc_18>; -+ pmuio-supply = <&vcc_io>; - }; - - &pinctrl { -- button { -- reset_button_pin: reset-button-pin { -- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - -@@ -292,61 +352,165 @@ eth_phy_reset_pin: eth-phy-reset-pin { - }; - }; - -- leds { -- lan_led_pin: lan-led-pin { -- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ }; - -- sys_led_pin: sys-led-pin { -- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ sdmmc0 { -+ sdmmc0_clk: sdmmc0-clk { -+ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>; - }; - -- wan_led_pin: wan-led-pin { -- rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ sdmmc0_cmd: sdmmc0-cmd { -+ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>; -+ }; -+ -+ sdmmc0_dectn: sdmmc0-dectn { -+ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; -+ }; -+ -+ sdmmc0_bus4: sdmmc0-bus4 { -+ rockchip,pins = -+ <1 RK_PA0 1 &pcfg_pull_up_4ma>, -+ <1 RK_PA1 1 &pcfg_pull_up_4ma>, -+ <1 RK_PA2 1 &pcfg_pull_up_4ma>, -+ <1 RK_PA3 1 &pcfg_pull_up_4ma>; - }; - }; - -- lan { -- lan_vdd_pin: lan-vdd-pin { -- rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ sdmmc0ext { -+ sdmmc0ext_clk: sdmmc0ext-clk { -+ rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>; -+ }; -+ -+ sdmmc0ext_cmd: sdmmc0ext-cmd { -+ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>; -+ }; -+ -+ sdmmc0ext_bus4: sdmmc0ext-bus4 { -+ rockchip,pins = -+ <3 RK_PA4 3 &pcfg_pull_up_2ma>, -+ <3 RK_PA5 3 &pcfg_pull_up_2ma>, -+ <3 RK_PA6 3 &pcfg_pull_up_2ma>, -+ <3 RK_PA7 3 &pcfg_pull_up_2ma>; - }; - }; - -- pmic { -- pmic_int_l: pmic-int-l { -- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ gmac-1 { -+ rgmiim1_pins: rgmiim1-pins { -+ rockchip,pins = -+ /* mac_txclk */ -+ <1 RK_PB4 2 &pcfg_pull_none_4ma>, -+ /* mac_rxclk */ -+ <1 RK_PB5 2 &pcfg_pull_none>, -+ /* mac_mdio */ -+ <1 RK_PC3 2 &pcfg_pull_none_2ma>, -+ /* mac_txen */ -+ <1 RK_PD1 2 &pcfg_pull_none_4ma>, -+ /* mac_clk */ -+ <1 RK_PC5 2 &pcfg_pull_none_2ma>, -+ /* mac_rxdv */ -+ <1 RK_PC6 2 &pcfg_pull_none>, -+ /* mac_mdc */ -+ <1 RK_PC7 2 &pcfg_pull_none_2ma>, -+ /* mac_rxd1 */ -+ <1 RK_PB2 2 &pcfg_pull_none>, -+ /* mac_rxd0 */ -+ <1 RK_PB3 2 &pcfg_pull_none>, -+ /* mac_txd1 */ -+ <1 RK_PB0 2 &pcfg_pull_none_4ma>, -+ /* mac_txd0 */ -+ <1 RK_PB1 2 &pcfg_pull_none_4ma>, -+ /* mac_rxd3 */ -+ <1 RK_PB6 2 &pcfg_pull_none>, -+ /* mac_rxd2 */ -+ <1 RK_PB7 2 &pcfg_pull_none>, -+ /* mac_txd3 */ -+ <1 RK_PC0 2 &pcfg_pull_none_4ma>, -+ /* mac_txd2 */ -+ <1 RK_PC1 2 &pcfg_pull_none_4ma>, -+ -+ /* mac_txclk */ -+ <0 RK_PB0 1 &pcfg_pull_none>, -+ /* mac_txen */ -+ <0 RK_PB4 1 &pcfg_pull_none>, -+ /* mac_clk */ -+ <0 RK_PD0 1 &pcfg_pull_none>, -+ /* mac_txd1 */ -+ <0 RK_PC0 1 &pcfg_pull_none>, -+ /* mac_txd0 */ -+ <0 RK_PC1 1 &pcfg_pull_none>, -+ /* mac_txd3 */ -+ <0 RK_PC7 1 &pcfg_pull_none>, -+ /* mac_txd2 */ -+ <0 RK_PC6 1 &pcfg_pull_none>; - }; - }; - -- sd { -- sdio_vcc_pin: sdio-vcc-pin { -- rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; -+ usb { -+ host_vbus_drv: host-vbus-drv { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ otg_vbus_drv: otg-vbus-drv { -+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -+ -+ gpio-leds { -+ leds_gpio: leds-gpio { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; - }; - --&pwm2 { -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ max-frequency = <150000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; -+ vmmc-supply = <&vcc_sd>; - status = "okay"; - }; - --&sdmmc { -+&sdmmc_ext { - bus-width = <4>; - cap-sd-highspeed; -+ cap-sdio-irq; - disable-wp; -- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; -+ keep-power-in-suspend; -+ max-frequency = <100000000>; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ num-slots = <1>; - pinctrl-names = "default"; -- sd-uhs-sdr12; -- sd-uhs-sdr25; -- sd-uhs-sdr50; -+ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>; -+ rockchip,default-sample-phase = <120>; -+ supports-sdio; - sd-uhs-sdr104; -- vmmc-supply = <&vcc_sd>; -- vqmmc-supply = <&vcc_io_sdio>; -+ #address-cells = <1>; -+ #size-cells = <0>; - status = "okay"; -+ -+ brcmf: bcrmf@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ interrupt-names = "host-wake"; -+ }; - }; - - &tsadc { -- rockchip,hw-tshut-mode = <0>; -- rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&uart2 { - status = "okay"; - }; - -@@ -362,13 +526,16 @@ &u2phy_otg { - status = "okay"; - }; - --&uart2 { -+&usb20_otg { - status = "okay"; - }; - --&usb20_otg { -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { - status = "okay"; -- dr_mode = "host"; - }; - - &usbdrd3 { -@@ -377,17 +544,10 @@ &usbdrd3 { - #address-cells = <1>; - #size-cells = <0>; - -- /* Second port is for USB 3.0 */ -- rtl8153: device@2 { -+ r8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; -+ realtek,led-data = <0x87>; -+ local-mac-address = [00 00 00 00 00 00]; - }; - }; -- --&usb_host0_ehci { -- status = "okay"; --}; -- --&usb_host0_ohci { -- status = "okay"; --}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi -@@ -19,11 +19,9 @@ &gmac2io { - mdio { - rtl8211e: ethernet-phy@1 { - reg = <1>; -- pinctrl-0 = <ð_phy_reset_pin>; -- pinctrl-names = "default"; - reset-assert-us = <10000>; -- reset-deassert-us = <50000>; -- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ reset-deassert-us = <30000>; -+ /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */ - }; - }; - }; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-nanopi-r3s-fix-leds.patch b/patch/kernel/rockchip64-6.14/board-nanopi-r3s-fix-leds.patch deleted file mode 100644 index f7639fe..0000000 --- a/patch/kernel/rockchip64-6.14/board-nanopi-r3s-fix-leds.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: John Doe -Date: Tue, 28 Jan 2025 12:13:35 +0800 -Subject: Patching NanoPi-R3S LEDs - -Signed-off-by: John Doe ---- - arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 41 +++++++--- - drivers/net/ethernet/realtek/r8169_main.c | 11 +++ - drivers/net/phy/realtek/realtek_main.c | 11 +++ - 3 files changed, 53 insertions(+), 10 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts -@@ -52,19 +52,21 @@ power_led: led-0 { - color = ; - function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -- default-state = "on"; -+ linux,default-trigger = "heartbeat"; - }; - - lan_led: led-1 { - color = ; - function = LED_FUNCTION_LAN; - gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "r8169-0-100:00:link"; - }; - - wan_led: led-2 { - color = ; - function = LED_FUNCTION_WAN; - gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "stmmac-0:01:link"; - }; - }; - -@@ -137,18 +139,27 @@ &cpu3 { - }; - - &gmac1 { -+ phy-mode = "rgmii"; -+ clock_in_out = "output"; -+ -+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ /* Reset time is 15ms, 50ms for rtl8211f */ -+ snps,reset-delays-us = <0 15000 50000>; - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; - assigned-clock-rates = <0>, <125000000>; -- clock_in_out = "output"; -- phy-mode = "rgmii-id"; -- phy-handle = <&rgmii_phy1>; -+ - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m0_miim - &gmac1m0_tx_bus2_level3 - &gmac1m0_rx_bus2 - &gmac1m0_rgmii_clk_level2 - &gmac1m0_rgmii_bus_level3>; -+ tx_delay = <0x3c>; -+ rx_delay = <0x2f>; -+ -+ phy-handle = <&rgmii_phy1>; - status = "okay"; - }; - -@@ -409,10 +420,8 @@ rgmii_phy1: ethernet-phy@1 { - interrupt-parent = <&gpio4>; - interrupts = ; - pinctrl-names = "default"; -- pinctrl-0 = <ð_phy_reset_pin>; -- reset-assert-us = <20000>; -- reset-deassert-us = <100000>; -- reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&gmac_int>; -+ realtek,ledsel = <0xae00>; - }; - }; - -@@ -421,6 +430,18 @@ &pcie2x1 { - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00000000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ r8169: pcie@1,0 { -+ reg = <0x000000 0 0 0 0>; -+ local-mac-address = [ 00 00 00 00 00 00 ]; -+ realtek,ledsel = <0x870>; -+ }; -+ }; - }; - - &pinctrl { -@@ -439,8 +460,8 @@ wan_led_pin: wan-led-pin { - }; - - gmac { -- eth_phy_reset_pin: eth-phy-reset-pin { -- rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; -+ gmac_int: gmac-int { -+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - -diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c -index 111111111111..222222222222 100644 ---- a/drivers/net/ethernet/realtek/r8169_main.c -+++ b/drivers/net/ethernet/realtek/r8169_main.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -2436,6 +2437,15 @@ void r8169_apply_firmware(struct rtl8169_private *tp) - } - } - -+static void rtl8168_led_of_init(struct rtl8169_private *tp) -+{ -+ struct device *d = tp_to_dev(tp); -+ u32 val; -+ -+ if (!of_property_read_u32(d->of_node, "realtek,ledsel", &val)) -+ RTL_W16(tp, LED_CTRL, val); -+} -+ - static void rtl8168_config_eee_mac(struct rtl8169_private *tp) - { - /* Adjust EEE LED frequency */ -@@ -3421,6 +3431,7 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) - rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); - - rtl8168_config_eee_mac(tp); -+ rtl8168_led_of_init(tp); - - RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); - RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); -diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c -index 111111111111..222222222222 100644 ---- a/drivers/net/phy/realtek/realtek_main.c -+++ b/drivers/net/phy/realtek/realtek_main.c -@@ -125,6 +125,15 @@ static int rtl821x_write_page(struct phy_device *phydev, int page) - return __phy_write(phydev, RTL821x_PAGE_SELECT, page); - } - -+static void rtl821x_led_of_init(struct phy_device *phydev) -+{ -+ struct device *dev = &phydev->mdio.dev; -+ u32 val; -+ -+ if (!of_property_read_u32(dev->of_node, "realtek,ledsel", &val)) -+ phy_write_paged(phydev, 0xd04, 0x10, val); -+} -+ - static int rtl821x_probe(struct phy_device *phydev) - { - struct device *dev = &phydev->mdio.dev; -@@ -444,6 +453,8 @@ static int rtl8211f_config_init(struct phy_device *phydev) - val_rxdly ? "enabled" : "disabled"); - } - -+ rtl821x_led_of_init(phydev); -+ - if (priv->has_phycr2) { - ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2, - RTL8211F_CLKOUT_EN, priv->phycr2); --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-nanopi-r4s-pwmfan.patch b/patch/kernel/rockchip64-6.14/board-nanopi-r4s-pwmfan.patch deleted file mode 100644 index 3d5c72f..0000000 --- a/patch/kernel/rockchip64-6.14/board-nanopi-r4s-pwmfan.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Bochun Bai -Date: Sun, 18 Jun 2023 11:56:34 +0200 -Subject: Add pwm-fan support to nanopi r4s - ---- - arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi | 35 ++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi -@@ -60,6 +60,41 @@ vdd_5v: regulator-vdd-5v { - regulator-always-on; - regulator-boot-on; - }; -+ -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ cooling-levels = <0 18 102 170 255>; -+ fan-supply = <&vdd_5v>; -+ pwms = <&pwm1 0 50000 0>; -+ }; -+}; -+ -+&cpu_thermal { -+ trips { -+ cpu_warm: cpu_warm { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_hot: cpu_hot { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map2 { -+ trip = <&cpu_warm>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map3 { -+ trip = <&cpu_hot>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; - }; - - &emmc_phy { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-odroidm1-add-nodes-for-i2c-pwm-uart-spi.patch b/patch/kernel/rockchip64-6.14/board-odroidm1-add-nodes-for-i2c-pwm-uart-spi.patch deleted file mode 100644 index 7f412fa..0000000 --- a/patch/kernel/rockchip64-6.14/board-odroidm1-add-nodes-for-i2c-pwm-uart-spi.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ricardo Pardini -Date: Thu, 9 Jan 2025 19:22:12 +0100 -Subject: rk3568-odroid-m1: add nodes for i2c/pwm/spi/uart overlays - -- we used to have a bare-dt for odroid-m1 that got removed as it landed upstream -- but mainline doesn't have the nodes we use for the overlays -- at least i2c3 (which is aliased to i2c0) and uart1 breaks without them ---- - arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 34 ++++++++++ - 1 file changed, 34 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts -@@ -739,3 +739,37 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - remote-endpoint = <&hdmi_in_vp0>; - }; - }; -+ -+&i2c3 { -+ status = "disabled"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3m1_xfer>; -+}; -+ -+&pwm1 { -+ status = "disabled"; -+ pinctrl-0 = <&pwm1m1_pins>; -+}; -+ -+&pwm2 { -+ status = "disabled"; -+ pinctrl-0 = <&pwm2m1_pins>; -+}; -+ -+&spi0 { -+ status = "disabled"; -+ -+ pinctrl-0 = <&spi0m1_pins>; -+ pinctrl-1 = <&spi0m1_pins_hs>; -+ num_chipselect = <1>; -+ -+ cs-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>; -+}; -+ -+&uart1 { -+ status = "disabled"; -+ dma-names = "tx", "rx"; -+ /* uart1 uart1-with-ctsrts */ -+ pinctrl-0 = <&uart1m1_xfer>; -+ pinctrl-1 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-odroidm2-fix-for-ethernet.patch b/patch/kernel/rockchip64-6.14/board-odroidm2-fix-for-ethernet.patch deleted file mode 100644 index eab9a25..0000000 --- a/patch/kernel/rockchip64-6.14/board-odroidm2-fix-for-ethernet.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Milivoje Legenovic -Date: Sat, 22 Mar 2025 13:46:35 +0100 -Subject: [ARCHEOLOGY] Fix for ethernet warnings in dmesg output - -> X-Git-Archeology: - Revision 896a8090c1c194999591326b1dcb55b377e4460c: https://github.com/armbian/build/commit/896a8090c1c194999591326b1dcb55b377e4460c -> X-Git-Archeology: Date: Sat, 22 Mar 2025 13:46:35 +0100 -> X-Git-Archeology: From: Milivoje Legenovic -> X-Git-Archeology: Subject: Fix for ethernet warnings in dmesg output -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts | 14 ++++++++-- - 1 file changed, 12 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts -@@ -229,9 +229,9 @@ &cpu_l3 { - }; - - &gmac1 { -- clock_in_out = "output"; -+ clock_in_out = "input"; - phy-handle = <&rgmii_phy1>; -- phy-mode = "rgmii-id"; -+ phy-mode = "rgmii"; - phy-supply = <&vcc_3v3_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim -@@ -241,6 +241,8 @@ &gmac1_rgmii_clk - &gmac1_rgmii_bus - &gmac1_clkinout>; - status = "okay"; -+ tx_delay = <0x3a>; -+ rx_delay = <0x3e>; - }; - - &gpu { -@@ -400,6 +402,8 @@ &mdio1 { - rgmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id001c.c916"; - reg = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -@@ -475,6 +479,12 @@ pcf8563_int: pcf8563-int { - }; - }; - -+ rtl8211f { -+ rtl8211f_rst: rtl8211f-rst { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - usb { - usb2_host_pwren: usb2-host-pwren { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-orangepi-r1-plus.patch b/patch/kernel/rockchip64-6.14/board-orangepi-r1-plus.patch deleted file mode 100644 index 33f951f..0000000 --- a/patch/kernel/rockchip64-6.14/board-orangepi-r1-plus.patch +++ /dev/null @@ -1,216 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Igor Pecovnik -Date: Sat, 20 Jun 2020 22:39:57 +0200 -Subject: [ARCHEOLOGY] Initial ROCK Pi E support (as WIP) (#2042) - -> X-Git-Archeology: > recovered message: > * WIP: Adding RockpiE config -> X-Git-Archeology: > recovered message: > Signed-off-by: Igor Pecovnik -> X-Git-Archeology: > recovered message: > * Mainline u-boot for ROCK Pi E -> X-Git-Archeology: > recovered message: > * Initial ROCK Pi E device tree in kernel -> X-Git-Archeology: > recovered message: > * Fixed supplies for ROCK Pi E device tree -> X-Git-Archeology: > recovered message: > * Adjusted u-boot load address for rockchip64 boards with 256MB eg. ROCK Pi E -> X-Git-Archeology: > recovered message: > * Blacklisted lima on ROCK Pi E -> X-Git-Archeology: > recovered message: > * Fixed ROCK Pi E patch after merge from master -> X-Git-Archeology: > recovered message: > * Removed mode settings from rk805 regulators -> X-Git-Archeology: > recovered message: > * Fixed issues with offloading for gigabit interface of RockPi E -> X-Git-Archeology: > recovered message: > * Adjusted ROCK Pi E board config -> X-Git-Archeology: > recovered message: > * Added dev branch for ROCK Pi E -> X-Git-Archeology: > recovered message: > * Add build targets -> X-Git-Archeology: > recovered message: > Signed-off-by: Igor Pecovnik -> X-Git-Archeology: > recovered message: > * Exchange legacy to current in ROCK Pi E build targets -> X-Git-Archeology: > recovered message: > Co-authored-by: Piotr Szczepanik -> X-Git-Archeology: - Revision e1ecb098330dc372740371dc2386f911833a0529: https://github.com/armbian/build/commit/e1ecb098330dc372740371dc2386f911833a0529 -> X-Git-Archeology: Date: Sat, 20 Jun 2020 22:39:57 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Initial ROCK Pi E support (as WIP) (#2042) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 72257bd0648c28fca32962126bb885a4a2c188cc: https://github.com/armbian/build/commit/72257bd0648c28fca32962126bb885a4a2c188cc -> X-Git-Archeology: Date: Tue, 23 Jun 2020 16:37:54 +0200 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Make USB3 support of ROCK Pi E on par with other rk3328 boards (#2050) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e36ce875b025e112127cf8cc2d34825ebfe36569: https://github.com/armbian/build/commit/e36ce875b025e112127cf8cc2d34825ebfe36569 -> X-Git-Archeology: Date: Tue, 10 Nov 2020 21:43:13 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switched rockchip64-current to linux 5.9.y (#2309) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ccbc888b3f5731790128684959b55b6552e26190: https://github.com/armbian/build/commit/ccbc888b3f5731790128684959b55b6552e26190 -> X-Git-Archeology: Date: Sat, 28 Nov 2020 16:52:34 +0100 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: add dts rk3328-roc-pc, fix WIFI and USB 3.0 rk3328 (#2390) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 25bd76527e1276c4c00829f68c0ca0742ecc94c1: https://github.com/armbian/build/commit/25bd76527e1276c4c00829f68c0ca0742ecc94c1 -> X-Git-Archeology: Date: Sat, 28 Nov 2020 18:10:53 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Fix roc-rk3328-pc device tree reference to missing RK_FUNC_1 -> X-Git-Archeology: -> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070 -> X-Git-Archeology: Date: Sun, 13 Dec 2020 22:13:03 -0500 -> X-Git-Archeology: From: tonymac32 -> X-Git-Archeology: Subject: [ rockchip64 ] Clean up patchset -> X-Git-Archeology: -> X-Git-Archeology: - Revision 25e0f1633467c020f6ae68d09964a522fbfbe613: https://github.com/armbian/build/commit/25e0f1633467c020f6ae68d09964a522fbfbe613 -> X-Git-Archeology: Date: Mon, 18 Jan 2021 23:21:40 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Adjusted power and pmic configuration for Station M1 in current/dev -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision d8dbefd61838e5b0cfc2b93d2d168f3fb2666dfb: https://github.com/armbian/build/commit/d8dbefd61838e5b0cfc2b93d2d168f3fb2666dfb -> X-Git-Archeology: Date: Tue, 27 Jul 2021 00:05:09 -0400 -> X-Git-Archeology: From: tonymac32 -> X-Git-Archeology: Subject: [ rockchip64 ] rk3328 change to mainline USB3 -> X-Git-Archeology: -> X-Git-Archeology: - Revision a16699260fb786a4d89a1c335722e9fed49d19d2: https://github.com/armbian/build/commit/a16699260fb786a4d89a1c335722e9fed49d19d2 -> X-Git-Archeology: Date: Fri, 08 Jul 2022 22:35:59 +1200 -> X-Git-Archeology: From: schwar3kat <61094841+schwar3kat@users.noreply.github.com> -> X-Git-Archeology: Subject: Refactored orangepi-r1plus-lts dts in kernel add board patch -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8648dde23ff090b5fb704adab036ed14cd944ba3: https://github.com/armbian/build/commit/8648dde23ff090b5fb704adab036ed14cd944ba3 -> X-Git-Archeology: Date: Thu, 22 Sep 2022 10:25:28 +0200 -> X-Git-Archeology: From: aiamadeus <42570690+aiamadeus@users.noreply.github.com> -> X-Git-Archeology: Subject: rockchip: fixes support for orangepi-r1plus (#4215) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 85bab47bba73e0ef0e4ea5fde60e0aab56f82906: https://github.com/armbian/build/commit/85bab47bba73e0ef0e4ea5fde60e0aab56f82906 -> X-Git-Archeology: Date: Sat, 06 May 2023 12:55:10 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 906ca66430329ab774f5b9d0f62eef1ce5e398fe: https://github.com/armbian/build/commit/906ca66430329ab774f5b9d0f62eef1ce5e398fe -> X-Git-Archeology: Date: Tue, 16 May 2023 08:55:33 +0200 -> X-Git-Archeology: From: Ricardo Pardini -> X-Git-Archeology: Subject: `rockchip64`/`edge`/`6.3`: rebase/rewrite patches against `v6.3.1`; do archeology for mbox-less patches; materialize overwrites -> X-Git-Archeology: -> X-Git-Archeology: - Revision 19d532b13cabc1a749f61b9c400d933ba5aeb7e3: https://github.com/armbian/build/commit/19d532b13cabc1a749f61b9c400d933ba5aeb7e3 -> X-Git-Archeology: Date: Tue, 13 Jun 2023 12:33:59 +0200 -> X-Git-Archeology: From: Ricardo Pardini -> X-Git-Archeology: Subject: `rockchip64` `edge` 6.3: rename most remaining "add-board" patches to "board" (all "add-board"s are now bare .dts in `dt/` folder) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 41ade999f04c26a277cfa1c3c721cbe869d3ad12: https://github.com/armbian/build/commit/41ade999f04c26a277cfa1c3c721cbe869d3ad12 -> X-Git-Archeology: Date: Tue, 03 Oct 2023 13:54:03 +0200 -> X-Git-Archeology: From: Ricardo Pardini -> X-Git-Archeology: Subject: `rockchip64`/`edge`: bump to `6.6-rc4`; initial copy patches from 6.5 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 1f4df4c41fe33f9822ca2f42d14a2a445e27aed7: https://github.com/armbian/build/commit/1f4df4c41fe33f9822ca2f42d14a2a445e27aed7 -> X-Git-Archeology: Date: Sun, 14 Jan 2024 14:14:50 +0100 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip64: bump edge to 6.7, current to 6.6 -> X-Git-Archeology: -> X-Git-Archeology: - Revision e4d413b9166e3633b40fb23382fb1045b9d0e315: https://github.com/armbian/build/commit/e4d413b9166e3633b40fb23382fb1045b9d0e315 -> X-Git-Archeology: Date: Tue, 26 Mar 2024 13:46:35 +0100 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip64: bump edge kernel to 6.8 -> X-Git-Archeology: -> X-Git-Archeology: - Revision fae4549764c548cb65d3cbfe319f1e11bc777505: https://github.com/armbian/build/commit/fae4549764c548cb65d3cbfe319f1e11bc777505 -> X-Git-Archeology: Date: Thu, 04 Apr 2024 13:38:18 +0800 -> X-Git-Archeology: From: aiamadeus <2789289348@qq.com> -> X-Git-Archeology: Subject: rockchip: update dts patches for orangepi r1-plus -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi | 45 ++++++++++ - 1 file changed, 45 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi -@@ -8,6 +8,7 @@ - - #include - #include -+#include "rk3328-dram-default-timing.dtsi" - #include "rk3328.dtsi" - - / { -@@ -83,6 +84,33 @@ vdd_5v_lan: regulator-vdd-5v-lan { - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; -+ -+ /delete-node/ dmc-opp-table; -+ -+ dmc_opp_table: dmc_opp_table { -+ compatible = "operating-points-v2"; -+ -+ opp-786000000 { -+ opp-hz = /bits/ 64 <786000000>; -+ opp-microvolt = <1075000 1075000 1200000>; -+ }; -+ opp-798000000 { -+ opp-hz = /bits/ 64 <798000000>; -+ opp-microvolt = <1075000 1075000 1200000>; -+ }; -+ opp-840000000 { -+ opp-hz = /bits/ 64 <840000000>; -+ opp-microvolt = <1075000 1075000 1200000>; -+ }; -+ opp-924000000 { -+ opp-hz = /bits/ 64 <924000000>; -+ opp-microvolt = <1100000 1100000 1200000>; -+ }; -+ opp-1056000000 { -+ opp-hz = /bits/ 64 <1056000000>; -+ opp-microvolt = <1175000 1175000 1200000>; -+ }; -+ }; - }; - - &cpu0 { -@@ -105,6 +133,16 @@ &display_subsystem { - status = "disabled"; - }; - -+&dfi { -+ status = "okay"; -+}; -+ -+&dmc { -+ center-supply = <&vdd_log>; -+ ddr_timing = <&ddr_timing>; -+ status = "okay"; -+}; -+ - &gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -@@ -120,6 +158,10 @@ mdio { - }; - }; - -+&i2c0 { -+ status = "okay"; -+}; -+ - &i2c1 { - status = "okay"; - -@@ -149,6 +191,7 @@ vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1075000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; -@@ -163,6 +206,7 @@ vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1225000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; -@@ -344,6 +388,7 @@ &usbdrd3 { - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; -+ realtek,led-data = <0x87>; - }; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-orangepi-rk3399-pcie.patch b/patch/kernel/rockchip64-6.14/board-orangepi-rk3399-pcie.patch deleted file mode 100644 index e7c2548..0000000 --- a/patch/kernel/rockchip64-6.14/board-orangepi-rk3399-pcie.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Thu, 18 Apr 2024 00:42:13 +0800 -Subject: arm64: dts: rockchip: add pcie support to orangepi rk3399 board - ---- - arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 31 ++++++++++ - 1 file changed, 31 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -@@ -123,6 +123,17 @@ vcc3v0_sd: regulator-vcc3v0-sd { - vin-supply = <&vcc3v3_sys>; - }; - -+ vcc3v3_pcie: regulator-vcc3v3-pcie { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 2 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_drv>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_pcie"; -+ }; -+ - vcc3v3_sys: regulator-vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; -@@ -587,6 +598,20 @@ &io_domains { - gpio1830-supply = <&vcc_3v0>; - }; - -+&pcie_phy { -+ status = "okay"; -+ assigned-clocks = <&cru 138>; -+ assigned-clock-parents = <&cru 167>; -+ assigned-clock-rates = <100000000>; -+}; -+ -+&pcie0 { -+ status = "okay"; -+ ep-gpios = <&gpio2 4 0>; -+ num-lanes = <4>; -+ max-link-speed = <1>; -+}; -+ - &pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_3v0>; -@@ -609,6 +634,12 @@ phy_rstb: phy-rstb { - }; - }; - -+ pcie { -+ pcie_drv: pcie-drv { -+ rockchip,pins = <0 2 0 &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - cpu_b_sleep: cpu-b-sleep { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-orangepi3b-add-uwe5622-wifi-bt-nodes.patch b/patch/kernel/rockchip64-6.14/board-orangepi3b-add-uwe5622-wifi-bt-nodes.patch deleted file mode 100644 index 4e1b160..0000000 --- a/patch/kernel/rockchip64-6.14/board-orangepi3b-add-uwe5622-wifi-bt-nodes.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Fri, 25 Oct 2024 14:48:47 +0800 -Subject: arch: arm64: dts: add uwe5622 wifi/bt nodes to orangepi3b v1.1 - ---- - arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts | 17 ++++++++++ - 1 file changed, 17 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts -@@ -7,6 +7,23 @@ - / { - model = "Xunlong Orange Pi 3B v1.1"; - compatible = "xunlong,orangepi-3b-v1.1", "xunlong,orangepi-3b", "rockchip,rk3566"; -+ -+ sprd-mtty { -+ compatible = "sprd,mtty"; -+ sprd,name = "ttyBT"; -+ }; -+ -+ uwe-bsp { -+ compatible = "unisoc,uwe_bsp"; -+ wl-reg-on = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; -+ bt-reg-on = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ wl-wake-host-gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; -+ bt-wake-host-gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; -+ sdio-ext-int-gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; -+ data-irq; -+ blksz-512; -+ keep-power-on; -+ }; - }; - - &pmu_io_domains { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-radxa-e25-sdmmc0-fix.patch b/patch/kernel/rockchip64-6.14/board-radxa-e25-sdmmc0-fix.patch deleted file mode 100644 index 5565210..0000000 --- a/patch/kernel/rockchip64-6.14/board-radxa-e25-sdmmc0-fix.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: krachlatte -Date: Wed, 17 May 2023 00:55:30 +0200 -Subject: [ARCHEOLOGY] Improve SD card compatibility on Radxa E25 (#5165) - -> X-Git-Archeology: - Revision 45c85878613108c238e491aa69650fcad1fba4bb: https://github.com/armbian/build/commit/45c85878613108c238e491aa69650fcad1fba4bb -> X-Git-Archeology: Date: Wed, 17 May 2023 00:55:30 +0200 -> X-Git-Archeology: From: krachlatte -> X-Git-Archeology: Subject: Improve SD card compatibility on Radxa E25 (#5165) -> X-Git-Archeology: -> X-Git-Archeology: - Revision f6a0c53d08f53aadd0588a571662dc199232825b: https://github.com/armbian/build/commit/f6a0c53d08f53aadd0588a571662dc199232825b -> X-Git-Archeology: Date: Wed, 24 May 2023 10:39:21 +0200 -> X-Git-Archeology: From: Ricardo Pardini -> X-Git-Archeology: Subject: manual e25 patch fix -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -@@ -203,7 +203,7 @@ &sdmmc0 { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; -- sd-uhs-sdr104; -+ sd-uhs-sdr50; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-radxa-e25-usb3-and-emmc-fix.patch b/patch/kernel/rockchip64-6.14/board-radxa-e25-usb3-and-emmc-fix.patch deleted file mode 100644 index 83cad5d..0000000 --- a/patch/kernel/rockchip64-6.14/board-radxa-e25-usb3-and-emmc-fix.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: krachlatte -Date: Wed, 17 May 2023 00:55:30 +0200 -Subject: [ARCHEOLOGY] Improve SD card compatibility on Radxa E25 (#5165) - -> X-Git-Archeology: - Revision 45c85878613108c238e491aa69650fcad1fba4bb: https://github.com/armbian/build/commit/45c85878613108c238e491aa69650fcad1fba4bb -> X-Git-Archeology: Date: Wed, 17 May 2023 00:55:30 +0200 -> X-Git-Archeology: From: krachlatte -> X-Git-Archeology: Subject: Improve SD card compatibility on Radxa E25 (#5165) -> X-Git-Archeology: -> X-Git-Archeology: - Revision f6a0c53d08f53aadd0588a571662dc199232825b: https://github.com/armbian/build/commit/f6a0c53d08f53aadd0588a571662dc199232825b -> X-Git-Archeology: Date: Wed, 24 May 2023 10:39:21 +0200 -> X-Git-Archeology: From: Ricardo Pardini -> X-Git-Archeology: Subject: manual e25 patch fix -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 12 ++++++++++ - arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 ++ - 2 files changed, 14 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi -@@ -385,6 +385,17 @@ &sdhci { - status = "okay"; - }; - -+&sfc { -+ status = "okay"; -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <108000000>; -+ spi-rx-bus-width = <2>; -+ spi-tx-bus-width = <2>; -+ }; -+}; -+ - &tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; -@@ -405,4 +416,5 @@ &usb2phy1 { - - &usb_host0_xhci { - extcon = <&usb2phy0>; -+ dr_mode = "host"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -@@ -218,6 +218,8 @@ &usb_host0_ohci { - }; - - &usb_host0_xhci { -+ extcon = <&usb2phy0>; -+ dr_mode = "host"; - status = "okay"; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rk3328-roc-cc-dts-enable-dmc.patch b/patch/kernel/rockchip64-6.14/board-rk3328-roc-cc-dts-enable-dmc.patch deleted file mode 100644 index dfc1790..0000000 --- a/patch/kernel/rockchip64-6.14/board-rk3328-roc-cc-dts-enable-dmc.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Tue, 12 Oct 2021 18:31:28 +0000 -Subject: enable roc-cc dmc - ---- - arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi | 38 ++++++++++ - 1 file changed, 38 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi -@@ -5,6 +5,7 @@ - - /dts-v1/; - -+#include "rk3328-dram-renegade-timing.dtsi" - #include "rk3328.dtsi" - - / { -@@ -18,6 +19,32 @@ chosen { - stdout-path = "serial2:1500000n8"; - }; - -+ /delete-node/ dmc-opp-table; -+ dmc_opp_table: dmc-opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-786000000 { -+ opp-hz = /bits/ 64 <786000000>; -+ opp-microvolt = <1075000 1075000 12000000>; -+ }; -+ opp-798000000 { -+ opp-hz = /bits/ 64 <798000000>; -+ opp-microvolt = <1075000 1075000 12000000>; -+ }; -+ opp-840000000 { -+ opp-hz = /bits/ 64 <840000000>; -+ opp-microvolt = <1075000 1075000 12000000>; -+ }; -+ opp-924000000 { -+ opp-hz = /bits/ 64 <924000000>; -+ opp-microvolt = <1100000 1100000 12000000>; -+ }; -+ opp-1068000000 { -+ opp-hz = /bits/ 64 <1068000000>; -+ opp-microvolt = <1175000 1175000 12000000>; -+ }; -+ }; -+ - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; -@@ -111,6 +138,17 @@ &codec { - status = "okay"; - }; - -+&dfi { -+ status = "okay"; -+}; -+ -+&dmc { -+ center-supply = <&vdd_logic>; -+ ddr_timing = <&ddr_timing>; -+ status = "okay"; -+}; -+ -+ - &cpu0 { - cpu-supply = <&vdd_arm>; - }; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rk3328-roc-cc-dts-ram-profile.patch b/patch/kernel/rockchip64-6.14/board-rk3328-roc-cc-dts-ram-profile.patch deleted file mode 100644 index dc5e811..0000000 --- a/patch/kernel/rockchip64-6.14/board-rk3328-roc-cc-dts-ram-profile.patch +++ /dev/null @@ -1,330 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: tonymac32 -Date: Wed, 7 Oct 2020 23:39:54 -0400 -Subject: board-rk3328-roc-cc-adjust-DMC-opps - -Signed-off-by: tonymac32 ---- - arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi | 311 ++++++++++ - 1 file changed, 311 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi -@@ -0,0 +1,311 @@ -+/* -+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+#include -+#include -+ -+/ { -+ ddr_timing: ddr_timing { -+ compatible = "rockchip,ddr-timing"; -+ ddr3_speed_bin = ; -+ ddr4_speed_bin = ; -+ pd_idle = <0>; -+ sr_idle = <0>; -+ sr_mc_gate_idle = <0>; -+ srpd_lite_idle = <0>; -+ standby_idle = <0>; -+ -+ auto_pd_dis_freq = <1066>; -+ auto_sr_dis_freq = <800>; -+ ddr3_dll_dis_freq = <300>; -+ ddr4_dll_dis_freq = <625>; -+ phy_dll_dis_freq = <400>; -+ -+ ddr3_odt_dis_freq = <100>; -+ phy_ddr3_odt_dis_freq = <100>; -+ ddr3_drv = ; -+ ddr3_odt = ; -+ phy_ddr3_ca_drv = ; -+ phy_ddr3_ck_drv = ; -+ phy_ddr3_dq_drv = ; -+ phy_ddr3_odt = ; -+ -+ lpddr3_odt_dis_freq = <666>; -+ phy_lpddr3_odt_dis_freq = <666>; -+ lpddr3_drv = ; -+ lpddr3_odt = ; -+ phy_lpddr3_ca_drv = ; -+ phy_lpddr3_ck_drv = ; -+ phy_lpddr3_dq_drv = ; -+ phy_lpddr3_odt = ; -+ -+ lpddr4_odt_dis_freq = <800>; -+ phy_lpddr4_odt_dis_freq = <800>; -+ lpddr4_drv = ; -+ lpddr4_dq_odt = ; -+ lpddr4_ca_odt = ; -+ phy_lpddr4_ca_drv = ; -+ phy_lpddr4_ck_cs_drv = ; -+ phy_lpddr4_dq_drv = ; -+ phy_lpddr4_odt = ; -+ -+ ddr4_odt_dis_freq = <666>; -+ phy_ddr4_odt_dis_freq = <666>; -+ ddr4_drv = ; -+ ddr4_odt = ; -+ phy_ddr4_ca_drv = ; -+ phy_ddr4_ck_drv = ; -+ phy_ddr4_dq_drv = ; -+ phy_ddr4_odt = ; -+ -+ /* CA de-skew, one step is 47.8ps, range 0-15 */ -+ ddr3a1_ddr4a9_de-skew = <0>; -+ ddr3a0_ddr4a10_de-skew = <0>; -+ ddr3a3_ddr4a6_de-skew = <1>; -+ ddr3a2_ddr4a4_de-skew = <1>; -+ ddr3a5_ddr4a8_de-skew = <0>; -+ ddr3a4_ddr4a5_de-skew = <2>; -+ ddr3a7_ddr4a11_de-skew = <0>; -+ ddr3a6_ddr4a7_de-skew = <2>; -+ ddr3a9_ddr4a0_de-skew = <1>; -+ ddr3a8_ddr4a13_de-skew = <0>; -+ ddr3a11_ddr4a3_de-skew = <2>; -+ ddr3a10_ddr4cs0_de-skew = <0>; -+ ddr3a13_ddr4a2_de-skew = <1>; -+ ddr3a12_ddr4ba1_de-skew = <0>; -+ ddr3a15_ddr4odt0_de-skew = <0>; -+ ddr3a14_ddr4a1_de-skew = <1>; -+ ddr3ba1_ddr4a15_de-skew = <0>; -+ ddr3ba0_ddr4bg0_de-skew = <0>; -+ ddr3ras_ddr4cke_de-skew = <0>; -+ ddr3ba2_ddr4ba0_de-skew = <1>; -+ ddr3we_ddr4bg1_de-skew = <1>; -+ ddr3cas_ddr4a12_de-skew = <0>; -+ ddr3ckn_ddr4ckn_de-skew = <5>; -+ ddr3ckp_ddr4ckp_de-skew = <5>; -+ ddr3cke_ddr4a16_de-skew = <1>; -+ ddr3odt0_ddr4a14_de-skew = <0>; -+ ddr3cs0_ddr4act_de-skew = <1>; -+ ddr3reset_ddr4reset_de-skew = <0>; -+ ddr3cs1_ddr4cs1_de-skew = <0>; -+ ddr3odt1_ddr4odt1_de-skew = <0>; -+ -+ /* DATA de-skew -+ * RX one step is 25.1ps, range 0-15 -+ * TX one step is 47.8ps, range 0-15 -+ */ -+ cs0_dm0_rx_de-skew = <7>; -+ cs0_dm0_tx_de-skew = <8>; -+ cs0_dq0_rx_de-skew = <7>; -+ cs0_dq0_tx_de-skew = <8>; -+ cs0_dq1_rx_de-skew = <7>; -+ cs0_dq1_tx_de-skew = <8>; -+ cs0_dq2_rx_de-skew = <7>; -+ cs0_dq2_tx_de-skew = <8>; -+ cs0_dq3_rx_de-skew = <7>; -+ cs0_dq3_tx_de-skew = <8>; -+ cs0_dq4_rx_de-skew = <7>; -+ cs0_dq4_tx_de-skew = <8>; -+ cs0_dq5_rx_de-skew = <7>; -+ cs0_dq5_tx_de-skew = <8>; -+ cs0_dq6_rx_de-skew = <7>; -+ cs0_dq6_tx_de-skew = <8>; -+ cs0_dq7_rx_de-skew = <7>; -+ cs0_dq7_tx_de-skew = <8>; -+ cs0_dqs0_rx_de-skew = <6>; -+ cs0_dqs0p_tx_de-skew = <9>; -+ cs0_dqs0n_tx_de-skew = <9>; -+ -+ cs0_dm1_rx_de-skew = <7>; -+ cs0_dm1_tx_de-skew = <7>; -+ cs0_dq8_rx_de-skew = <7>; -+ cs0_dq8_tx_de-skew = <8>; -+ cs0_dq9_rx_de-skew = <7>; -+ cs0_dq9_tx_de-skew = <7>; -+ cs0_dq10_rx_de-skew = <7>; -+ cs0_dq10_tx_de-skew = <8>; -+ cs0_dq11_rx_de-skew = <7>; -+ cs0_dq11_tx_de-skew = <7>; -+ cs0_dq12_rx_de-skew = <7>; -+ cs0_dq12_tx_de-skew = <8>; -+ cs0_dq13_rx_de-skew = <7>; -+ cs0_dq13_tx_de-skew = <7>; -+ cs0_dq14_rx_de-skew = <7>; -+ cs0_dq14_tx_de-skew = <8>; -+ cs0_dq15_rx_de-skew = <7>; -+ cs0_dq15_tx_de-skew = <7>; -+ cs0_dqs1_rx_de-skew = <7>; -+ cs0_dqs1p_tx_de-skew = <9>; -+ cs0_dqs1n_tx_de-skew = <9>; -+ -+ cs0_dm2_rx_de-skew = <7>; -+ cs0_dm2_tx_de-skew = <8>; -+ cs0_dq16_rx_de-skew = <7>; -+ cs0_dq16_tx_de-skew = <8>; -+ cs0_dq17_rx_de-skew = <7>; -+ cs0_dq17_tx_de-skew = <8>; -+ cs0_dq18_rx_de-skew = <7>; -+ cs0_dq18_tx_de-skew = <8>; -+ cs0_dq19_rx_de-skew = <7>; -+ cs0_dq19_tx_de-skew = <8>; -+ cs0_dq20_rx_de-skew = <7>; -+ cs0_dq20_tx_de-skew = <8>; -+ cs0_dq21_rx_de-skew = <7>; -+ cs0_dq21_tx_de-skew = <8>; -+ cs0_dq22_rx_de-skew = <7>; -+ cs0_dq22_tx_de-skew = <8>; -+ cs0_dq23_rx_de-skew = <7>; -+ cs0_dq23_tx_de-skew = <8>; -+ cs0_dqs2_rx_de-skew = <6>; -+ cs0_dqs2p_tx_de-skew = <9>; -+ cs0_dqs2n_tx_de-skew = <9>; -+ -+ cs0_dm3_rx_de-skew = <7>; -+ cs0_dm3_tx_de-skew = <7>; -+ cs0_dq24_rx_de-skew = <7>; -+ cs0_dq24_tx_de-skew = <8>; -+ cs0_dq25_rx_de-skew = <7>; -+ cs0_dq25_tx_de-skew = <7>; -+ cs0_dq26_rx_de-skew = <7>; -+ cs0_dq26_tx_de-skew = <7>; -+ cs0_dq27_rx_de-skew = <7>; -+ cs0_dq27_tx_de-skew = <7>; -+ cs0_dq28_rx_de-skew = <7>; -+ cs0_dq28_tx_de-skew = <7>; -+ cs0_dq29_rx_de-skew = <7>; -+ cs0_dq29_tx_de-skew = <7>; -+ cs0_dq30_rx_de-skew = <7>; -+ cs0_dq30_tx_de-skew = <7>; -+ cs0_dq31_rx_de-skew = <7>; -+ cs0_dq31_tx_de-skew = <7>; -+ cs0_dqs3_rx_de-skew = <7>; -+ cs0_dqs3p_tx_de-skew = <9>; -+ cs0_dqs3n_tx_de-skew = <9>; -+ -+ cs1_dm0_rx_de-skew = <7>; -+ cs1_dm0_tx_de-skew = <8>; -+ cs1_dq0_rx_de-skew = <7>; -+ cs1_dq0_tx_de-skew = <8>; -+ cs1_dq1_rx_de-skew = <7>; -+ cs1_dq1_tx_de-skew = <8>; -+ cs1_dq2_rx_de-skew = <7>; -+ cs1_dq2_tx_de-skew = <8>; -+ cs1_dq3_rx_de-skew = <7>; -+ cs1_dq3_tx_de-skew = <8>; -+ cs1_dq4_rx_de-skew = <7>; -+ cs1_dq4_tx_de-skew = <8>; -+ cs1_dq5_rx_de-skew = <7>; -+ cs1_dq5_tx_de-skew = <8>; -+ cs1_dq6_rx_de-skew = <7>; -+ cs1_dq6_tx_de-skew = <8>; -+ cs1_dq7_rx_de-skew = <7>; -+ cs1_dq7_tx_de-skew = <8>; -+ cs1_dqs0_rx_de-skew = <6>; -+ cs1_dqs0p_tx_de-skew = <9>; -+ cs1_dqs0n_tx_de-skew = <9>; -+ -+ cs1_dm1_rx_de-skew = <7>; -+ cs1_dm1_tx_de-skew = <7>; -+ cs1_dq8_rx_de-skew = <7>; -+ cs1_dq8_tx_de-skew = <8>; -+ cs1_dq9_rx_de-skew = <7>; -+ cs1_dq9_tx_de-skew = <7>; -+ cs1_dq10_rx_de-skew = <7>; -+ cs1_dq10_tx_de-skew = <8>; -+ cs1_dq11_rx_de-skew = <7>; -+ cs1_dq11_tx_de-skew = <7>; -+ cs1_dq12_rx_de-skew = <7>; -+ cs1_dq12_tx_de-skew = <8>; -+ cs1_dq13_rx_de-skew = <7>; -+ cs1_dq13_tx_de-skew = <7>; -+ cs1_dq14_rx_de-skew = <7>; -+ cs1_dq14_tx_de-skew = <8>; -+ cs1_dq15_rx_de-skew = <7>; -+ cs1_dq15_tx_de-skew = <7>; -+ cs1_dqs1_rx_de-skew = <7>; -+ cs1_dqs1p_tx_de-skew = <9>; -+ cs1_dqs1n_tx_de-skew = <9>; -+ -+ cs1_dm2_rx_de-skew = <7>; -+ cs1_dm2_tx_de-skew = <8>; -+ cs1_dq16_rx_de-skew = <7>; -+ cs1_dq16_tx_de-skew = <8>; -+ cs1_dq17_rx_de-skew = <7>; -+ cs1_dq17_tx_de-skew = <8>; -+ cs1_dq18_rx_de-skew = <7>; -+ cs1_dq18_tx_de-skew = <8>; -+ cs1_dq19_rx_de-skew = <7>; -+ cs1_dq19_tx_de-skew = <8>; -+ cs1_dq20_rx_de-skew = <7>; -+ cs1_dq20_tx_de-skew = <8>; -+ cs1_dq21_rx_de-skew = <7>; -+ cs1_dq21_tx_de-skew = <8>; -+ cs1_dq22_rx_de-skew = <7>; -+ cs1_dq22_tx_de-skew = <8>; -+ cs1_dq23_rx_de-skew = <7>; -+ cs1_dq23_tx_de-skew = <8>; -+ cs1_dqs2_rx_de-skew = <6>; -+ cs1_dqs2p_tx_de-skew = <9>; -+ cs1_dqs2n_tx_de-skew = <9>; -+ -+ cs1_dm3_rx_de-skew = <7>; -+ cs1_dm3_tx_de-skew = <7>; -+ cs1_dq24_rx_de-skew = <7>; -+ cs1_dq24_tx_de-skew = <8>; -+ cs1_dq25_rx_de-skew = <7>; -+ cs1_dq25_tx_de-skew = <7>; -+ cs1_dq26_rx_de-skew = <7>; -+ cs1_dq26_tx_de-skew = <7>; -+ cs1_dq27_rx_de-skew = <7>; -+ cs1_dq27_tx_de-skew = <7>; -+ cs1_dq28_rx_de-skew = <7>; -+ cs1_dq28_tx_de-skew = <7>; -+ cs1_dq29_rx_de-skew = <7>; -+ cs1_dq29_tx_de-skew = <7>; -+ cs1_dq30_rx_de-skew = <7>; -+ cs1_dq30_tx_de-skew = <7>; -+ cs1_dq31_rx_de-skew = <7>; -+ cs1_dq31_tx_de-skew = <7>; -+ cs1_dqs3_rx_de-skew = <7>; -+ cs1_dqs3p_tx_de-skew = <9>; -+ cs1_dqs3n_tx_de-skew = <9>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rk3328-roc-pc-dts-ram-profile.patch b/patch/kernel/rockchip64-6.14/board-rk3328-roc-pc-dts-ram-profile.patch deleted file mode 100644 index 226ffb3..0000000 --- a/patch/kernel/rockchip64-6.14/board-rk3328-roc-pc-dts-ram-profile.patch +++ /dev/null @@ -1,301 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Tony -Date: Thu, 8 Oct 2020 01:56:28 -0400 -Subject: [ARCHEOLOGY] Add files via upload - -> X-Git-Archeology: - Revision 8fc20a15b12561e76e92d5bd29b5afd1c62f08ac: https://github.com/armbian/build/commit/8fc20a15b12561e76e92d5bd29b5afd1c62f08ac -> X-Git-Archeology: Date: Thu, 08 Oct 2020 01:56:28 -0400 -> X-Git-Archeology: From: Tony -> X-Git-Archeology: Subject: Add files via upload -> X-Git-Archeology: -> X-Git-Archeology: - Revision 2788adccedc25f12fc9e71e01a92863d97683979: https://github.com/armbian/build/commit/2788adccedc25f12fc9e71e01a92863d97683979 -> X-Git-Archeology: Date: Tue, 26 Jan 2021 21:22:04 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Enable DMC for Station M1 in current and dev (#2575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 -> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 -> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi | 223 ++++++++++ - 1 file changed, 223 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi -@@ -0,0 +1,223 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd -+ * -+ */ -+#include -+#include -+ -+/ { -+ ddr_timing: ddr_timing { -+ /* CA de-skew, one step is 47.8ps, range 0-15 */ -+ ddr3a1_ddr4a9_de-skew = <0>; -+ ddr3a0_ddr4a10_de-skew = <0>; -+ ddr3a3_ddr4a6_de-skew = <1>; -+ ddr3a2_ddr4a4_de-skew = <1>; -+ ddr3a5_ddr4a8_de-skew = <0>; -+ ddr3a4_ddr4a5_de-skew = <2>; -+ ddr3a7_ddr4a11_de-skew = <0>; -+ ddr3a6_ddr4a7_de-skew = <2>; -+ ddr3a9_ddr4a0_de-skew = <1>; -+ ddr3a8_ddr4a13_de-skew = <0>; -+ ddr3a11_ddr4a3_de-skew = <2>; -+ ddr3a10_ddr4cs0_de-skew = <0>; -+ ddr3a13_ddr4a2_de-skew = <1>; -+ ddr3a12_ddr4ba1_de-skew = <0>; -+ ddr3a15_ddr4odt0_de-skew = <0>; -+ ddr3a14_ddr4a1_de-skew = <1>; -+ ddr3ba1_ddr4a15_de-skew = <0>; -+ ddr3ba0_ddr4bg0_de-skew = <0>; -+ ddr3ras_ddr4cke_de-skew = <0>; -+ ddr3ba2_ddr4ba0_de-skew = <1>; -+ ddr3we_ddr4bg1_de-skew = <1>; -+ ddr3cas_ddr4a12_de-skew = <0>; -+ ddr3ckn_ddr4ckn_de-skew = <5>; -+ ddr3ckp_ddr4ckp_de-skew = <5>; -+ ddr3cke_ddr4a16_de-skew = <1>; -+ ddr3odt0_ddr4a14_de-skew = <0>; -+ ddr3cs0_ddr4act_de-skew = <1>; -+ ddr3reset_ddr4reset_de-skew = <0>; -+ ddr3cs1_ddr4cs1_de-skew = <0>; -+ ddr3odt1_ddr4odt1_de-skew = <0>; -+ -+ /* DATA de-skew -+ * RX one step is 25.1ps, range 0-15 -+ * TX one step is 47.8ps, range 0-15 -+ */ -+ cs0_dm0_rx_de-skew = <7>; -+ cs0_dm0_tx_de-skew = <8>; -+ cs0_dq0_rx_de-skew = <7>; -+ cs0_dq0_tx_de-skew = <8>; -+ cs0_dq1_rx_de-skew = <7>; -+ cs0_dq1_tx_de-skew = <8>; -+ cs0_dq2_rx_de-skew = <7>; -+ cs0_dq2_tx_de-skew = <8>; -+ cs0_dq3_rx_de-skew = <7>; -+ cs0_dq3_tx_de-skew = <8>; -+ cs0_dq4_rx_de-skew = <7>; -+ cs0_dq4_tx_de-skew = <8>; -+ cs0_dq5_rx_de-skew = <7>; -+ cs0_dq5_tx_de-skew = <8>; -+ cs0_dq6_rx_de-skew = <7>; -+ cs0_dq6_tx_de-skew = <8>; -+ cs0_dq7_rx_de-skew = <7>; -+ cs0_dq7_tx_de-skew = <8>; -+ cs0_dqs0_rx_de-skew = <6>; -+ cs0_dqs0p_tx_de-skew = <9>; -+ cs0_dqs0n_tx_de-skew = <9>; -+ -+ cs0_dm1_rx_de-skew = <7>; -+ cs0_dm1_tx_de-skew = <7>; -+ cs0_dq8_rx_de-skew = <7>; -+ cs0_dq8_tx_de-skew = <8>; -+ cs0_dq9_rx_de-skew = <7>; -+ cs0_dq9_tx_de-skew = <7>; -+ cs0_dq10_rx_de-skew = <7>; -+ cs0_dq10_tx_de-skew = <8>; -+ cs0_dq11_rx_de-skew = <7>; -+ cs0_dq11_tx_de-skew = <7>; -+ cs0_dq12_rx_de-skew = <7>; -+ cs0_dq12_tx_de-skew = <8>; -+ cs0_dq13_rx_de-skew = <7>; -+ cs0_dq13_tx_de-skew = <7>; -+ cs0_dq14_rx_de-skew = <7>; -+ cs0_dq14_tx_de-skew = <8>; -+ cs0_dq15_rx_de-skew = <7>; -+ cs0_dq15_tx_de-skew = <7>; -+ cs0_dqs1_rx_de-skew = <7>; -+ cs0_dqs1p_tx_de-skew = <9>; -+ cs0_dqs1n_tx_de-skew = <9>; -+ -+ cs0_dm2_rx_de-skew = <7>; -+ cs0_dm2_tx_de-skew = <8>; -+ cs0_dq16_rx_de-skew = <7>; -+ cs0_dq16_tx_de-skew = <8>; -+ cs0_dq17_rx_de-skew = <7>; -+ cs0_dq17_tx_de-skew = <8>; -+ cs0_dq18_rx_de-skew = <7>; -+ cs0_dq18_tx_de-skew = <8>; -+ cs0_dq19_rx_de-skew = <7>; -+ cs0_dq19_tx_de-skew = <8>; -+ cs0_dq20_rx_de-skew = <7>; -+ cs0_dq20_tx_de-skew = <8>; -+ cs0_dq21_rx_de-skew = <7>; -+ cs0_dq21_tx_de-skew = <8>; -+ cs0_dq22_rx_de-skew = <7>; -+ cs0_dq22_tx_de-skew = <8>; -+ cs0_dq23_rx_de-skew = <7>; -+ cs0_dq23_tx_de-skew = <8>; -+ cs0_dqs2_rx_de-skew = <6>; -+ cs0_dqs2p_tx_de-skew = <9>; -+ cs0_dqs2n_tx_de-skew = <9>; -+ -+ cs0_dm3_rx_de-skew = <7>; -+ cs0_dm3_tx_de-skew = <7>; -+ cs0_dq24_rx_de-skew = <7>; -+ cs0_dq24_tx_de-skew = <8>; -+ cs0_dq25_rx_de-skew = <7>; -+ cs0_dq25_tx_de-skew = <7>; -+ cs0_dq26_rx_de-skew = <7>; -+ cs0_dq26_tx_de-skew = <7>; -+ cs0_dq27_rx_de-skew = <7>; -+ cs0_dq27_tx_de-skew = <7>; -+ cs0_dq28_rx_de-skew = <7>; -+ cs0_dq28_tx_de-skew = <7>; -+ cs0_dq29_rx_de-skew = <7>; -+ cs0_dq29_tx_de-skew = <7>; -+ cs0_dq30_rx_de-skew = <7>; -+ cs0_dq30_tx_de-skew = <7>; -+ cs0_dq31_rx_de-skew = <7>; -+ cs0_dq31_tx_de-skew = <7>; -+ cs0_dqs3_rx_de-skew = <7>; -+ cs0_dqs3p_tx_de-skew = <9>; -+ cs0_dqs3n_tx_de-skew = <9>; -+ -+ cs1_dm0_rx_de-skew = <7>; -+ cs1_dm0_tx_de-skew = <8>; -+ cs1_dq0_rx_de-skew = <7>; -+ cs1_dq0_tx_de-skew = <8>; -+ cs1_dq1_rx_de-skew = <7>; -+ cs1_dq1_tx_de-skew = <8>; -+ cs1_dq2_rx_de-skew = <7>; -+ cs1_dq2_tx_de-skew = <8>; -+ cs1_dq3_rx_de-skew = <7>; -+ cs1_dq3_tx_de-skew = <8>; -+ cs1_dq4_rx_de-skew = <7>; -+ cs1_dq4_tx_de-skew = <8>; -+ cs1_dq5_rx_de-skew = <7>; -+ cs1_dq5_tx_de-skew = <8>; -+ cs1_dq6_rx_de-skew = <7>; -+ cs1_dq6_tx_de-skew = <8>; -+ cs1_dq7_rx_de-skew = <7>; -+ cs1_dq7_tx_de-skew = <8>; -+ cs1_dqs0_rx_de-skew = <6>; -+ cs1_dqs0p_tx_de-skew = <9>; -+ cs1_dqs0n_tx_de-skew = <9>; -+ -+ cs1_dm1_rx_de-skew = <7>; -+ cs1_dm1_tx_de-skew = <7>; -+ cs1_dq8_rx_de-skew = <7>; -+ cs1_dq8_tx_de-skew = <8>; -+ cs1_dq9_rx_de-skew = <7>; -+ cs1_dq9_tx_de-skew = <7>; -+ cs1_dq10_rx_de-skew = <7>; -+ cs1_dq10_tx_de-skew = <8>; -+ cs1_dq11_rx_de-skew = <7>; -+ cs1_dq11_tx_de-skew = <7>; -+ cs1_dq12_rx_de-skew = <7>; -+ cs1_dq12_tx_de-skew = <8>; -+ cs1_dq13_rx_de-skew = <7>; -+ cs1_dq13_tx_de-skew = <7>; -+ cs1_dq14_rx_de-skew = <7>; -+ cs1_dq14_tx_de-skew = <8>; -+ cs1_dq15_rx_de-skew = <7>; -+ cs1_dq15_tx_de-skew = <7>; -+ cs1_dqs1_rx_de-skew = <7>; -+ cs1_dqs1p_tx_de-skew = <9>; -+ cs1_dqs1n_tx_de-skew = <9>; -+ -+ cs1_dm2_rx_de-skew = <7>; -+ cs1_dm2_tx_de-skew = <8>; -+ cs1_dq16_rx_de-skew = <7>; -+ cs1_dq16_tx_de-skew = <8>; -+ cs1_dq17_rx_de-skew = <7>; -+ cs1_dq17_tx_de-skew = <8>; -+ cs1_dq18_rx_de-skew = <7>; -+ cs1_dq18_tx_de-skew = <8>; -+ cs1_dq19_rx_de-skew = <7>; -+ cs1_dq19_tx_de-skew = <8>; -+ cs1_dq20_rx_de-skew = <7>; -+ cs1_dq20_tx_de-skew = <8>; -+ cs1_dq21_rx_de-skew = <7>; -+ cs1_dq21_tx_de-skew = <8>; -+ cs1_dq22_rx_de-skew = <7>; -+ cs1_dq22_tx_de-skew = <8>; -+ cs1_dq23_rx_de-skew = <7>; -+ cs1_dq23_tx_de-skew = <8>; -+ cs1_dqs2_rx_de-skew = <6>; -+ cs1_dqs2p_tx_de-skew = <9>; -+ cs1_dqs2n_tx_de-skew = <9>; -+ -+ cs1_dm3_rx_de-skew = <7>; -+ cs1_dm3_tx_de-skew = <7>; -+ cs1_dq24_rx_de-skew = <7>; -+ cs1_dq24_tx_de-skew = <8>; -+ cs1_dq25_rx_de-skew = <7>; -+ cs1_dq25_tx_de-skew = <7>; -+ cs1_dq26_rx_de-skew = <7>; -+ cs1_dq26_tx_de-skew = <7>; -+ cs1_dq27_rx_de-skew = <7>; -+ cs1_dq27_tx_de-skew = <7>; -+ cs1_dq28_rx_de-skew = <7>; -+ cs1_dq28_tx_de-skew = <7>; -+ cs1_dq29_rx_de-skew = <7>; -+ cs1_dq29_tx_de-skew = <7>; -+ cs1_dq30_rx_de-skew = <7>; -+ cs1_dq30_tx_de-skew = <7>; -+ cs1_dq31_rx_de-skew = <7>; -+ cs1_dq31_tx_de-skew = <7>; -+ cs1_dqs3_rx_de-skew = <7>; -+ cs1_dqs3p_tx_de-skew = <9>; -+ cs1_dqs3n_tx_de-skew = <9>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rk3328-roc-pc.patch b/patch/kernel/rockchip64-6.14/board-rk3328-roc-pc.patch deleted file mode 100644 index 8d37eb6..0000000 --- a/patch/kernel/rockchip64-6.14/board-rk3328-roc-pc.patch +++ /dev/null @@ -1,592 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Tue, 12 Oct 2021 19:34:29 +0000 -Subject: enable dmc for rk3328-roc-pc - ---- - arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 524 +++++++++- - 1 file changed, 466 insertions(+), 58 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts -@@ -1,109 +1,517 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR MIT) --// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd -+/* -+ * SPDX-License-Identifier: (GPL-2.0+ or MIT) -+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd -+ */ - - /dts-v1/; -- -+#include "rk3328-roc-pc-dram-timing.dtsi" -+#include "rk3328.dtsi" - #include --#include "rk3328-roc.dtsi" - - / { -- model = "Firefly ROC-RK3328-PC"; -+ model = "Firefly roc-rk3328-pc"; - compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328"; - -- adc-keys { -- compatible = "adc-keys"; -- io-channels = <&saradc 0>; -- io-channel-names = "buttons"; -- keyup-threshold-microvolt = <1750000>; -+ aliases { -+ mmc0 = &sdmmc; -+ mmc1 = &emmc; /* MMC boot device */ -+ }; - -- /* This button is unpopulated out of the factory. */ -- button-recovery { -- label = "Recovery"; -- linux,code = ; -- press-threshold-microvolt = <10000>; -+ gmac_clkin: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,name = "rockchip,rk3328"; -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1>; -+ }; -+ simple-audio-card,codec { -+ sound-dai = <&codec>; -+ }; -+ }; -+ -+ hdmi-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <128>; -+ simple-audio-card,name = "rockchip,hdmi"; -+ simple-audio-card,cpu { -+ sound-dai = <&i2s0>; -+ }; -+ simple-audio-card,codec { -+ sound-dai = <&hdmi>; - }; - }; - -- ir-receiver { -- compatible = "gpio-ir-receiver"; -- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; -- linux,rc-map-name = "rc-khadas"; -+ vcc_host_5v: vcc-host-5v-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; -- pinctrl-0 = <&ir_int>; -+ pinctrl-0 = <&usb30_host_drv>; -+ regulator-name = "vcc_host_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_phy"; -+ regulator-always-on; -+ regulator-boot-on; - }; - -- sdio_pwrseq: sdio-pwrseq { -- compatible = "mmc-pwrseq-simple"; -+ vcc_phy: vcc-phy-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; -- pinctrl-0 = <&wifi_en>, <&wifi_host_wake>; -- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&usb20_host_drv>; -+ regulator-name = "vcc_host1_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0m1_pin>; -+ regulator-name = "vcc_sd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_io>; -+ }; -+ -+ vcc_sys: vcc-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ xin32k: xin32k { -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+ clock-output-names = "xin32k"; -+ #clock-cells = <0>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ power_led: led-0 { -+ label = "firefly:blue:power"; -+ linux,default-trigger = "heartbeat"; -+ gpios = <&rk805 1 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ mode = <0x23>; -+ }; -+ -+ user_led: led-1 { -+ label = "firefly:yellow:user"; -+ linux,default-trigger = "mmc1"; -+ gpios = <&rk805 0 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ mode = <0x05>; -+ }; -+ }; -+ -+ /delete-node/ dmc-opp-table; -+ dmc_opp_table: dmc-opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-786000000 { -+ opp-hz = /bits/ 64 <786000000>; -+ opp-microvolt = <1075000 1075000 1200000>; -+ }; -+ opp-798000000 { -+ opp-hz = /bits/ 64 <798000000>; -+ opp-microvolt = <1075000 1075000 1200000>; -+ }; -+ opp-840000000 { -+ opp-hz = /bits/ 64 <840000000>; -+ opp-microvolt = <1075000 1075000 1200000>; -+ }; -+ opp-924000000 { -+ status = "disabled"; // unstable -+ opp-hz = /bits/ 64 <924000000>; -+ opp-microvolt = <1100000 1100000 1200000>; -+ }; - }; - }; - --&codec { -- mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; -+&dfi { -+ status = "okay"; -+}; -+ -+&dmc { -+ center-supply = <&vdd_logic>; -+ ddr_timing = <&ddr_timing>; -+ status = "okay"; -+}; -+ -+&io_domains { -+ status = "okay"; -+ -+ vccio1-supply = <&vcc_io>; -+ vccio2-supply = <&vcc_18emmc>; -+ vccio3-supply = <&vcc_io>; -+ vccio4-supply = <&vcc_io>; -+ vccio5-supply = <&vcc_io>; -+ vccio6-supply = <&vcc_io>; -+ pmuio-supply = <&vcc_io>; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; - }; - - &gpu { -+ status = "okay"; - mali-supply = <&vdd_logic>; - }; - --&pinctrl { -- ir { -- ir_int: ir-int { -- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+&gmac2phy { -+ phy-supply = <&vcc_phy>; -+ clock_in_out = "output"; -+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; -+ assigned-clock-rate = <50000000>; -+ assigned-clocks = <&cru SCLK_MAC2PHY>; -+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; -+ status = "disabled"; -+}; -+ -+&gmac2io { -+ phy-supply = <&vcc_io>; -+ phy-mode = "rgmii"; -+ clock_in_out = "input"; -+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmiim1_pins>; -+ snps,aal; -+ snps,rxpbl = <0x4>; -+ snps,txpbl = <0x4>; -+ tx_delay = <0x24>; -+ rx_delay = <0x18>; -+ status = "okay"; -+}; -+ -+&display_subsystem { -+ status = "okay"; -+}; -+ -+&hdmi { -+ #sound-dai-cells = <0>; -+ ddc-i2c-scl-high-time-ns = <9625>; -+ ddc-i2c-scl-low-time-ns = <10000>; -+ status = "okay"; -+}; -+ -+&hdmiphy { -+ status = "okay"; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+/*&h265e { -+ status = "okay"; -+}; -+ -+&vdec { -+ status = "okay"; -+}; -+ -+&vepu { -+ status = "okay"; -+};*/ -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+/*&vpu_service { -+ status = "okay"; -+};*/ -+ -+&i2s0 { -+ #sound-dai-cells = <0>; -+ rockchip,bclk-fs = <128>; -+ status = "okay"; -+}; -+ -+&i2s1 { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ -+&codec { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ -+&emmc { -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ supports-emmc; -+ disable-wp; -+ non-removable; -+ num-slots = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ max-frequency = <150000000>; -+ num-slots = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; -+ supports-sd; -+ status = "okay"; -+ vmmc-supply = <&vcc_sd>; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ rk805: rk805@18 { -+ compatible = "rockchip,rk805"; -+ status = "okay"; -+ reg = <0x18>; -+ interrupt-parent = <&gpio2>; -+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ gpio-controller; -+ #gpio-cells = <2>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk805-clkout2"; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_io>; -+ vcc6-supply = <&vcc_io>; -+ -+ rtc { -+ status = "okay"; - }; -- }; - -- sdmmcio { -- sdio_per_pin: sdio-per-pin { -- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; -+ pwrkey { -+ status = "okay"; -+ }; -+ -+ gpio { -+ status = "okay"; -+ }; -+ -+ regulators { -+ compatible = "rk805-regulator"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_io: DCDC_REG4 { -+ regulator-name = "vcc_io"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vdd_18: LDO_REG1 { -+ regulator-name = "vdd_18"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_18emmc: LDO_REG2 { -+ regulator-name = "vcc_18emmc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_11: LDO_REG3 { -+ regulator-name = "vdd_11"; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1100000>; -+ }; -+ }; - }; - }; -+}; -+ -+&pinctrl { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&clk_32k_out>; -+ -+ clk_32k { -+ clk_32k_out: clk-32k-out { -+ rockchip,pins = -+ <1 RK_PD4 1 &pcfg_pull_none>; -+ }; -+ }; - -- wifi { -- wifi_en: wifi-en { -- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = -+ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */ - }; -+ }; - -- wifi_host_wake: wifi-host-wake { -- rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>; -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, -+ <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>, -+ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, -+ <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ }; - -- bt_rst: bt-rst { -- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; -+ usb2 { -+ usb20_host_drv: usb20-host-drv { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ }; - -- bt_en: bt-en { -- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ usb3 { -+ usb30_host_drv: usb30-host-drv { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - }; - --&pmic_int_l { -- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+&u2phy { -+ status = "okay"; - }; - --&rk805 { -- interrupt-parent = <&gpio0>; -- interrupts = ; -+&u2phy_host { -+ status = "okay"; - }; - --&saradc { -- vref-supply = <&vcc_18>; -+&u2phy_otg { - status = "okay"; - }; - --&usb20_host_drv { -- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; -+&uart2 { -+ status = "okay"; - }; - --&vcc_host1_5v { -- gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -+&usb20_otg { -+ dr_mode = "host"; -+ status = "okay"; - }; - --&vcc_sdio { -- gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&sdio_per_pin>; -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usbdrd3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&wdt { -+ status = "okay"; -+}; -+ -+&saradc { -+ status = "okay"; -+ vref-supply = <&vdd_18>; -+}; -+ -+&tsadc { -+ status = "okay"; -+ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - }; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rock3a-0001-emmc-sfc.patch b/patch/kernel/rockchip64-6.14/board-rock3a-0001-emmc-sfc.patch deleted file mode 100644 index 8ce6fd5..0000000 --- a/patch/kernel/rockchip64-6.14/board-rock3a-0001-emmc-sfc.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Wed, 3 Aug 2022 22:22:55 +0200 -Subject: [ARCHEOLOGY] update rockchip64 edge to 5.19 (#4039) - -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 11 ++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -767,6 +767,17 @@ flash@0 { - }; - }; - -+&sfc { -+ status = "okay"; -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <108000000>; -+ spi-rx-bus-width = <2>; -+ spi-tx-bus-width = <2>; -+ }; -+}; -+ - &tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rock3a-0002-usb3.patch b/patch/kernel/rockchip64-6.14/board-rock3a-0002-usb3.patch deleted file mode 100644 index a49f809..0000000 --- a/patch/kernel/rockchip64-6.14/board-rock3a-0002-usb3.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Wed, 3 Aug 2022 22:22:55 +0200 -Subject: [ARCHEOLOGY] update rockchip64 edge to 5.19 (#4039) - -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -819,6 +819,7 @@ &usb_host0_ohci { - - &usb_host0_xhci { - extcon = <&usb2phy0>; -+ dr_mode = "host"; - status = "okay"; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rock3a-0003-add-gpio-names.patch b/patch/kernel/rockchip64-6.14/board-rock3a-0003-add-gpio-names.patch deleted file mode 100644 index 956e0f1..0000000 --- a/patch/kernel/rockchip64-6.14/board-rock3a-0003-add-gpio-names.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Werner -Date: Wed, 23 Oct 2024 12:27:21 +0200 -Subject: add gpio names for rock-3a - -Signed-off-by: Werner ---- - arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 60 ++++++++++ - 1 file changed, 60 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -277,6 +277,66 @@ &gpu { - status = "okay"; - }; - -+&gpio0 { -+ gpio-line-names = -+ /* GPIO0_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO0_B0 - B7 */ -+ "", "", "", "pin-28 [GPIO0_B3]", "pin-27 [GPIO0_B4]", "pin-7 [GPIO0_B5]", "pin-16 [GPIO0_B6]", "", -+ /* GPIO0_C0 - C7 */ -+ "", "pin-22 [GPIO0_C1]", "", "", "", "", "", "", -+ /* GPIO0_D0 - D7 */ -+ "pin-10 [GPIO0_D0]", "pin-8 [GPIO0_D1]", "", "", "", "", "", ""; -+}; -+ -+&gpio1 { -+ gpio-line-names = -+ /* GPIO1_A0 - A7 */ -+ "pin-3 [GPIO1_A0]", "pin-5 [GPIO1_A1]", "", "", "", "", "", "", -+ /* GPIO1_B0 - B7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO1_C0 - C7 */ -+ "pin-15 [GPIO0_C0]", "", "", "", "", "", "", "", -+ /* GPIO1_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio2 { -+ gpio-line-names = -+ /* GPIO2_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO2_B0 - B7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO2_C0 - C7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO2_D0 - D7 */ -+ "", "", "", "", "", "", "", "pin-29 [GPIO2_D7]"; -+}; -+ -+&gpio3 { -+ gpio-line-names = -+ /* GPIO3_A0 - A7 */ -+ "pin-31 [GPIO3_A0]", "", "pin-36 [GPIO3_A2]", "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]", "pin-38 [GPIO3_A6]", "", -+ /* GPIO3_B0 - B7 */ -+ "", "", "pin-18 [GPIO3_B2]", "", "", "", "", "", -+ /* GPIO3_C0 - C7 */ -+ "", "", "pin-32 [GPIO3_C2]", "pin-33 [GPIO3_C3]", "pin-11 [GPIO3_C4]", "pin-13 [GPIO3_C5]", "", "", -+ /* GPIO3_D0 - D7 */ -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = -+ /* GPIO4_A0 - A7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO4_B0 - B7 */ -+ "", "", "", "", "", "", "", "", -+ /* GPIO4_C0 - C7 */ -+ "", "", "pin-21 [GPIO4_C2]", "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]", "pin-24 [GPIO4_C6]", "", -+ /* GPIO4_D0 - D7 */ -+ "", "pin-26 [GPIO4_D1]", "", "", "", "", "", ""; -+}; -+ - &hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rock64-mail-supply.patch b/patch/kernel/rockchip64-6.14/board-rock64-mail-supply.patch deleted file mode 100644 index d285e99..0000000 --- a/patch/kernel/rockchip64-6.14/board-rock64-mail-supply.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: tonymac32 -Date: Sun, 8 Aug 2021 11:49:27 -0400 -Subject: board_rock64_mali-usb-supply - -Signed-off-by: tonymac32 ---- - arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -@@ -136,6 +136,11 @@ &emmc { - status = "okay"; - }; - -+&gpu { -+ status = "okay"; -+ mali-supply = <&vdd_logic>; -+}; -+ - &gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rockpi3-enable-dmc.patch b/patch/kernel/rockchip64-6.14/board-rockpi3-enable-dmc.patch deleted file mode 100644 index 1b1b0a0..0000000 --- a/patch/kernel/rockchip64-6.14/board-rockpi3-enable-dmc.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Wed, 8 Mar 2023 11:12:22 +0100 -Subject: [ARCHEOLOGY] rockchip64: enable dmc on Rock PI E board - -> X-Git-Archeology: - Revision 4ea9330e5185e1c6e248af035cc615d23408316d: https://github.com/armbian/build/commit/4ea9330e5185e1c6e248af035cc615d23408316d -> X-Git-Archeology: Date: Wed, 08 Mar 2023 11:12:22 +0100 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip64: enable dmc on Rock PI E board -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts -@@ -15,6 +15,7 @@ - #include - - #include "rk3328.dtsi" -+#include "rk3328-dram-default-timing.dtsi" - - / { - model = "Radxa ROCK Pi E"; -@@ -440,3 +441,9 @@ &usbdrd3 { - &usb_host0_ehci { - status = "okay"; - }; -+ -+&dmc { -+ status = "okay"; -+ center-supply = <&vdd_log>; -+ ddr_timing = <&ddr_timing>; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rockpi4-0003-arm64-dts-pcie.patch b/patch/kernel/rockchip64-6.14/board-rockpi4-0003-arm64-dts-pcie.patch deleted file mode 100644 index ab7b03f..0000000 --- a/patch/kernel/rockchip64-6.14/board-rockpi4-0003-arm64-dts-pcie.patch +++ /dev/null @@ -1,130 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Piotr Szczepanik -Date: Mon, 18 Nov 2019 18:23:10 +0100 -Subject: [ARCHEOLOGY] Rock Pi 4 enable PCIe in device tree for "dev" target - (#1624) - -> X-Git-Archeology: > recovered message: > * Rock Pi 4 enabled support for PCIe in device tree -> X-Git-Archeology: > recovered message: > * Rockchip64-dev added possibility to enable PCIe Gen2 speed via overlay -> X-Git-Archeology: - Revision b3bb9345439250d8247f0e24a8e1ef6290b2c279: https://github.com/armbian/build/commit/b3bb9345439250d8247f0e24a8e1ef6290b2c279 -> X-Git-Archeology: Date: Mon, 18 Nov 2019 18:23:10 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Rock Pi 4 enable PCIe in device tree for "dev" target (#1624) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3 -> X-Git-Archeology: Date: Tue, 19 Nov 2019 23:25:39 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Remove K<4, change branches, new features (#1586) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 812245def37a695bce9e7ece148b2920d82c8b37: https://github.com/armbian/build/commit/812245def37a695bce9e7ece148b2920d82c8b37 -> X-Git-Archeology: Date: Sat, 18 Jul 2020 23:07:01 +0200 -> X-Git-Archeology: From: Werner -> X-Git-Archeology: Subject: Move rockchip/64 current to 5.7.y (#2099) -> X-Git-Archeology: -> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070 -> X-Git-Archeology: Date: Sun, 13 Dec 2020 22:13:03 -0500 -> X-Git-Archeology: From: tonymac32 -> X-Git-Archeology: Subject: [ rockchip64 ] Clean up patchset -> X-Git-Archeology: -> X-Git-Archeology: - Revision 091d91468e383c3d12a03a465be36b76112ce798: https://github.com/armbian/build/commit/091d91468e383c3d12a03a465be36b76112ce798 -> X-Git-Archeology: Date: Sun, 17 Jan 2021 19:07:59 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switched rockchip64-current to 5.10.y (and synced -dev config/patches) (#2546) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 -> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 -> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) -> X-Git-Archeology: -> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e -> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 44c4cdf8653104bc395c504d7611d819906ff69b: https://github.com/armbian/build/commit/44c4cdf8653104bc395c504d7611d819906ff69b -> X-Git-Archeology: Date: Fri, 30 Dec 2022 21:17:33 +0100 -> X-Git-Archeology: From: Konstantin Litvinov -> X-Git-Archeology: Subject: Fixed issue with NVMe identification in rk3399-rock-pi-4.dts (#4627) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 44c95b7b0a64486a85f23c5630842ea1b877a695: https://github.com/armbian/build/commit/44c95b7b0a64486a85f23c5630842ea1b877a695 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:01 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: fix unidiff warning from patches of rockchip64-6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -111,6 +111,8 @@ vcc3v3_pcie: regulator-vcc3v3-pcie { - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - -@@ -528,9 +530,11 @@ &pcie0 { - num-lanes = <4>; - pinctrl-0 = <&pcie_clkreqnb_cpm>; - pinctrl-names = "default"; -+ vpcie12v-supply = <&vcc12v_dcin>; - vpcie0v9-supply = <&vcc_0v9>; - vpcie1v8-supply = <&vcc_1v8>; - vpcie3v3-supply = <&vcc3v3_pcie>; -+ bus-scan-delay-ms = <1500>; - status = "okay"; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rockpie-0001-arm64-dts-rockchip-fix-gmac-PHY-attach-error.patch b/patch/kernel/rockchip64-6.14/board-rockpie-0001-arm64-dts-rockchip-fix-gmac-PHY-attach-error.patch deleted file mode 100644 index e87394b..0000000 --- a/patch/kernel/rockchip64-6.14/board-rockpie-0001-arm64-dts-rockchip-fix-gmac-PHY-attach-error.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Tue, 10 Sep 2024 19:33:28 +0000 -Subject: arm64: dts: rockchip: fix gmac PHY attach error on ROCK Pi E - -Signed-off-by: FUKAUMI Naoki ---- - arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts -@@ -164,6 +164,7 @@ mdio { - #size-cells = <0>; - - rtl8211: ethernet-phy@1 { -+ compatible = "ethernet-phy-id001c.c916"; - reg = <1>; - pinctrl-0 = <ð_phy_int_pin>, <ð_phy_reset_pin>; - pinctrl-names = "default"; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rockpis-dts-fixes.patch b/patch/kernel/rockchip64-6.14/board-rockpis-dts-fixes.patch deleted file mode 100644 index 2121d5f..0000000 --- a/patch/kernel/rockchip64-6.14/board-rockpis-dts-fixes.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Wed, 27 Nov 2024 19:06:49 +0100 -Subject: rk3308: fixes for rock pi s dts - ---- - arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 73 ++++++++++ - 1 file changed, 73 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts -@@ -48,6 +48,54 @@ blue-led { - }; - }; - -+ analog_sound: analog-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "analog"; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,codec-hp-det; -+ simple-audio-card,widgets = -+ "Headphone", "Headphones"; -+ -+ simple-audio-card,dai-link@1 { -+ format = "i2s"; -+ -+ cpu { -+ sound-dai = <&i2s_8ch_2>; -+ }; -+ -+ codec { -+ sound-dai = <&codec>; -+ }; -+ -+ }; -+ -+ }; -+ -+ pcm5102_sound: pcm5102-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,name = "pcm5102a"; -+ -+ simple-audio-card,dai-link@1 { -+ format = "i2s"; -+ cpu { -+ sound-dai = <&i2s_8ch_0>; -+ }; -+ -+ codec { -+ sound-dai = <&pcm5102a>; -+ }; -+ }; -+ }; -+ -+ pcm5102a: pcm5102a { -+ #sound-dai-cells = <0>; -+ compatible = "ti,pcm5102a"; -+ pcm510x,format = "i2s"; -+ }; -+ - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-0 = <&wifi_enable_h>; -@@ -128,6 +176,11 @@ vdd_log: regulator-vdd-log { - }; - }; - -+&codec { -+ status = "okay"; -+ #sound-dai-cells = <0>; -+}; -+ - &cpu0 { - cpu-supply = <&vdd_core>; - }; -@@ -242,6 +295,19 @@ &io_domains { - status = "okay"; - }; - -+&i2s_8ch_0 { -+ #sound-dai-cells = <0>; -+ assigned-clocks = <&cru SCLK_I2S0_8CH_RX>; -+ assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>; -+ rockchip,clk-trcm = <1>; -+ status = "okay"; -+}; -+ -+&i2s_8ch_2 { -+ #sound-dai-cells = <0>; -+ status = "okay"; -+}; -+ - &pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; -@@ -333,10 +399,17 @@ &sdmmc { - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -+ card-detect-delay = <200>; - vmmc-supply = <&vcc_io>; - status = "okay"; - }; - -+&tsadc { -+ rockchip,hw-tshut-mode = <0>; /* 0:CRU */ -+ rockchip,hw-tshut-polarity = <1>; /* 1:HIGH */ -+ status = "okay"; -+}; -+ - &u2phy { - status = "okay"; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch b/patch/kernel/rockchip64-6.14/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch deleted file mode 100644 index 2c7b06e..0000000 --- a/patch/kernel/rockchip64-6.14/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Piotr Szczepanik -Date: Mon, 24 Aug 2020 22:47:03 +0200 -Subject: Rockpro64 add pcie bus scan delay - -- See rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch -- Use 1000ms for rockpro64 ---- - arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -677,6 +677,7 @@ &pcie0 { - vpcie1v8-supply = <&vcca_1v8>; - vpcie12v-supply = <&vcc12v_dcin>; - vpcie3v3-supply = <&vcc3v3_pcie>; -+ bus-scan-delay-ms = <1000>; - status = "okay"; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rockpro64-change-rx_delay-for-gmac.patch b/patch/kernel/rockchip64-6.14/board-rockpro64-change-rx_delay-for-gmac.patch deleted file mode 100644 index 5ab1edb..0000000 --- a/patch/kernel/rockchip64-6.14/board-rockpro64-change-rx_delay-for-gmac.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ayufan -Date: Sun, 30 Dec 2018 13:32:47 +0100 -Subject: ayufan: dts: rockpro64: change rx_delay for gmac - -Change-Id: Ib3899f684188aa1ed1545717af004bba53fe0e07 ---- - arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -317,7 +317,7 @@ &gmac { - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; -- rx_delay = <0x11>; -+ rx_delay = <0x20>; - status = "okay"; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rockpro64-fix-emmc.patch b/patch/kernel/rockchip64-6.14/board-rockpro64-fix-emmc.patch deleted file mode 100644 index 96fdbdc..0000000 --- a/patch/kernel/rockchip64-6.14/board-rockpro64-fix-emmc.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Martin Ayotte -Date: Wed, 5 Dec 2018 14:09:24 -0500 -Subject: rockpro64: sdhci keep-power-in-suspend and set chosen bootargs - mmc_cmdqueue=0 and earlycon - ---- - arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -17,6 +17,7 @@ aliases { - }; - - chosen { -+ bootargs = "mmc_cmdqueue=0 earlycon=uart8250,mmio32,0xff1a0000"; - stdout-path = "serial2:1500000n8"; - }; - -@@ -829,6 +830,7 @@ &sdmmc { - - &sdhci { - bus-width = <8>; -+ keep-power-in-suspend; - mmc-hs200-1_8v; - non-removable; - status = "okay"; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rockpro64-fix-spi1-flash-speed.patch b/patch/kernel/rockchip64-6.14/board-rockpro64-fix-spi1-flash-speed.patch deleted file mode 100644 index 675fb66..0000000 --- a/patch/kernel/rockchip64-6.14/board-rockpro64-fix-spi1-flash-speed.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Martin Ayotte -Date: Sat, 5 Jan 2019 09:50:02 -0500 -Subject: slow SPIFlash to avoid errors - -See Revision ea20f750bfead37ced7b604a44f8f014e317abad ---- - arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -852,7 +852,7 @@ &spi1 { - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; -- spi-max-frequency = <10000000>; -+ spi-max-frequency = <3000000>; - }; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rockpro64-work-led-heartbeat.patch b/patch/kernel/rockchip64-6.14/board-rockpro64-work-led-heartbeat.patch deleted file mode 100644 index 40d526a..0000000 --- a/patch/kernel/rockchip64-6.14/board-rockpro64-work-led-heartbeat.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Piotr Szczepanik -Date: Mon, 24 Aug 2020 22:47:03 +0200 -Subject: Switch RockPro64 work led to heartbeat trigger - ---- - arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -66,7 +66,7 @@ leds { - - work_led: led-0 { - label = "work"; -- default-state = "on"; -+ linux,default-trigger = "heartbeat"; - gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rocks0-0001-Revert-arm64-dts-rockchip-Fix-sdmmc-access-on-rk3308.patch b/patch/kernel/rockchip64-6.14/board-rocks0-0001-Revert-arm64-dts-rockchip-Fix-sdmmc-access-on-rk3308.patch deleted file mode 100644 index b3c97e8..0000000 --- a/patch/kernel/rockchip64-6.14/board-rocks0-0001-Revert-arm64-dts-rockchip-Fix-sdmmc-access-on-rk3308.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Igor Pecovnik -Date: Sat, 8 Feb 2025 17:54:03 +0100 -Subject: Revert "arm64: dts: rockchip: Fix sdmmc access on rk3308-rock-s0 v1.1 - boards" - -This reverts commit 8810a8368b6075595715c4231322ca906a6b2f6f. ---- - arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts | 25 +--------- - 1 file changed, 1 insertion(+), 24 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts -@@ -74,23 +74,6 @@ vcc_io: regulator-3v3-vcc-io { - vin-supply = <&vcc5v0_sys>; - }; - -- /* -- * HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. -- * This is modeled as an always-on active low fixed regulator. -- */ -- vcc_sd: regulator-3v3-vcc-sd { -- compatible = "regulator-fixed"; -- gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; -- pinctrl-names = "default"; -- pinctrl-0 = <&sdmmc_2030>; -- regulator-name = "vcc_sd"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc_io>; -- }; -- - vcc5v0_sys: regulator-5v0-vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; -@@ -198,12 +181,6 @@ pwr_led: pwr-led { - }; - }; - -- sdmmc { -- sdmmc_2030: sdmmc-2030 { -- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- - wifi { - wifi_reg_on: wifi-reg-on { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -256,7 +233,7 @@ &sdmmc { - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -- vmmc-supply = <&vcc_sd>; -+ vmmc-supply = <&vcc_io>; - status = "okay"; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-rocks0-0001-deviceTree.patch b/patch/kernel/rockchip64-6.14/board-rocks0-0001-deviceTree.patch deleted file mode 100644 index 3e4ae0b..0000000 --- a/patch/kernel/rockchip64-6.14/board-rocks0-0001-deviceTree.patch +++ /dev/null @@ -1,506 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Brent Roman -Date: Wed, 7 Feb 2024 18:02:07 -0800 -Subject: Added Linux device tree for Rock S0 - -Signed-off-by: Brent Roman ---- - arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts | 346 ++++++---- - 1 file changed, 200 insertions(+), 146 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts -@@ -1,21 +1,17 @@ - // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2019 Akash Gajjar -+ * Copyright (c) 2019 Jagan Teki -+ * Revised: 2024 Brent Roman -+ */ - - /dts-v1/; -- --#include - #include "rk3308.dtsi" - - / { - model = "Radxa ROCK S0"; - compatible = "radxa,rock-s0", "rockchip,rk3308"; - -- aliases { -- ethernet0 = &gmac; -- mmc0 = &emmc; -- mmc1 = &sdmmc; -- mmc2 = &sdio; -- }; -- - chosen { - stdout-path = "serial0:1500000n8"; - }; -@@ -23,38 +19,70 @@ chosen { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; -- pinctrl-0 = <&pwr_led>; -+ pinctrl-0 = <&green_led_gio>; - -- led-green { -- color = ; -- default-state = "on"; -- function = LED_FUNCTION_HEARTBEAT; -+ green-led { -+ label = "rock-s0:green:power"; - gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; -+ default-state = "on"; - }; - }; - -- vdd_log: regulator-1v04-vdd-log { -- compatible = "regulator-fixed"; -- regulator-name = "vdd_log"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1040000>; -- regulator-max-microvolt = <1040000>; -- vin-supply = <&vcc5v0_sys>; -+ acodec-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "rockchip,rk3308-acodec"; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,codec-hp-det; -+ simple-audio-card,widgets = -+ "Headphone", "Headphones"; -+ simple-audio-card,cpu { -+ sound-dai = <&i2s_8ch_2>; -+ }; -+ simple-audio-card,codec { -+ sound-dai = <&codec>; -+ }; - }; - -- vcc_ddr: regulator-1v5-vcc-ddr { -- compatible = "regulator-fixed"; -- regulator-name = "vcc_ddr"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1500000>; -- regulator-max-microvolt = <1500000>; -- vin-supply = <&vcc5v0_sys>; -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,name = "i2s_8ch_0"; -+ -+ simple-audio-card,dai-link@1 { -+ format = "i2s"; -+ cpu { -+ sound-dai = <&i2s_8ch_0>; -+ }; -+ -+ codec { -+ sound-dai = <&pcm5102a>; -+ }; -+ }; -+ }; -+ -+ pcm5102a: pcm5102a { -+ #sound-dai-cells = <0>; -+ compatible = "ti,pcm5102a"; -+ pcm510x,format = "i2s"; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-0 = <&wifi_enable_h>; -+ pinctrl-names = "default"; -+ /* -+ * On the module itself this is one of these (depending -+ * on the actual card populated): -+ * - SDIO_RESET_L_WL_REG_ON -+ * - PDN (power down when low) -+ */ -+ reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - }; - -- vcc_1v8: regulator-1v8-vcc { -+ vcc_1v8: vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-always-on; -@@ -64,7 +92,7 @@ vcc_1v8: regulator-1v8-vcc { - vin-supply = <&vcc_io>; - }; - -- vcc_io: regulator-3v3-vcc-io { -+ vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-always-on; -@@ -74,7 +102,28 @@ vcc_io: regulator-3v3-vcc-io { - vin-supply = <&vcc5v0_sys>; - }; - -- vcc5v0_sys: regulator-5v0-vcc-sys { -+ vcc_ddr: vcc-ddr { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_otg: vcc5v0-otg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&otg_vbus_drv>; -+ regulator-name = "vcc5v0_otg"; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; -@@ -83,119 +132,150 @@ vcc5v0_sys: regulator-5v0-vcc-sys { - regulator-max-microvolt = <5000000>; - }; - -- vdd_core: regulator-vdd-core { -+ vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - pwm-supply = <&vcc5v0_sys>; - regulator-name = "vdd_core"; -- regulator-always-on; -- regulator-boot-on; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; -+ regulator-init-microvolt = <1015000>; - regulator-settling-time-up-us = <250>; -+ regulator-always-on; -+ regulator-boot-on; - }; - -- sdio_pwrseq: sdio-pwrseq { -- compatible = "mmc-pwrseq-simple"; -+ vdd_log: vdd-log { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ board_antenna: board-antenna { -+ status = "okay"; -+ compatible = "regulator-fixed"; -+ enable-active-low; -+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ regulator-always-on; -+ regulator-boot-on; -+ pinctrl-0 = <&ant_1>; - pinctrl-names = "default"; -- pinctrl-0 = <&wifi_reg_on>; -- reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; -+ regulator-name = "board_antenna"; - }; - }; - -+&codec { -+ status = "okay"; -+ #sound-dai-cells = <0>; -+}; -+ - &cpu0 { - cpu-supply = <&vdd_core>; - }; - - &emmc { - cap-mmc-highspeed; -- no-sd; -- no-sdio; -+ mmc-hs200-1_8v; - non-removable; -- pinctrl-names = "default"; -- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_pwren>; -- vmmc-supply = <&vcc_io>; -+ vmmc-supply = <&vcc_io>; //was vin-supply -+ status = "okay"; -+}; -+ -+&sdmmc { -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ card-detect-delay = <800>; - status = "okay"; - }; - -+&sdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ no-mmc; -+ status = "okay"; -+ -+ AP6212: wifi@1 { -+ compatible = "brcm,bcm4329-fmac"; -+ reg = <1>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ interrupt-names = "host-wake"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_host_wake>; -+ }; -+}; -+ - &gmac { -- clock_in_out = "output"; -- phy-handle = <&rtl8201f>; - phy-supply = <&vcc_io>; -+ clock_in_out = "output"; -+ assigned-clocks = <&cru SCLK_MAC>; -+ assigned-clock-parents = <&cru SCLK_MAC_SRC>; -+ snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 50000 50000>; - status = "okay"; -+}; - -- mdio { -- compatible = "snps,dwmac-mdio"; -- #address-cells = <1>; -- #size-cells = <0>; -- -- rtl8201f: ethernet-phy@1 { -- compatible = "ethernet-phy-ieee802.3-c22"; -- reg = <1>; -- pinctrl-names = "default"; -- pinctrl-0 = <&mac_rst>; -- reset-assert-us = <20000>; -- reset-deassert-us = <50000>; -- reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -- }; -- }; -+&i2s_8ch_0 { -+ assigned-clocks = <&cru SCLK_I2S0_8CH_RX>; -+ assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>; -+ rockchip,clk-trcm = <1>; -+ #sound-dai-cells = <0>; - }; - --&io_domains { -- vccio0-supply = <&vcc_io>; -- vccio1-supply = <&vcc_io>; -- vccio2-supply = <&vcc_io>; -- vccio3-supply = <&vcc_io>; -- vccio4-supply = <&vcc_1v8>; -- vccio5-supply = <&vcc_io>; -+&i2s_8ch_2 { - status = "okay"; -+ #sound-dai-cells = <0>; - }; - - &pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - -- bluetooth { -- bt_reg_on: bt-reg-on { -- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- bt_wake_host: bt-wake-host { -- rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; -- }; -- -- host_wake_bt: host-wake-bt { -- rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ leds { -+ green_led_gio: green-led-gpio { -+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - -- gmac { -- mac_rst: mac-rst { -- rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; -+ usb { -+ otg_vbus_drv: otg-vbus-drv { -+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - -- leds { -- pwr_led: pwr-led { -- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { -- wifi_reg_on: wifi-reg-on { -- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ wifi_host_wake: wifi-host-wake { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - -- wifi_wake_host: wifi-wake-host { -- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ antenna { -+ ant_1: ant-1 { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - }; - - &pwm0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pwm0_pin_pull_down>; - status = "okay"; -+ pinctrl-0 = <&pwm0_pin_pull_down>; - }; - - &saradc { -@@ -203,91 +283,65 @@ &saradc { - status = "okay"; - }; - --&sdio { -- #address-cells = <1>; -- #size-cells = <0>; -- cap-sd-highspeed; -- cap-sdio-irq; -- keep-power-in-suspend; -- max-frequency = <50000000>; -- mmc-pwrseq = <&sdio_pwrseq>; -- no-mmc; -- no-sd; -- non-removable; -- vmmc-supply = <&vcc_io>; -- vqmmc-supply = <&vcc_1v8>; -+&tsadc { -+ rockchip,hw-tshut-mode = <0>; /* 0:CRU */ -+ rockchip,hw-tshut-polarity = <1>; /* 1:HIGH */ - status = "okay"; -- -- brcmf: wifi@1 { -- compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; -- reg = <1>; -- interrupt-parent = <&gpio0>; -- interrupts = ; -- interrupt-names = "host-wake"; -- pinctrl-names = "default"; -- pinctrl-0 = <&wifi_wake_host>; -- }; - }; - --&sdmmc { -- cap-mmc-highspeed; -- cap-sd-highspeed; -- disable-wp; -- vmmc-supply = <&vcc_io>; -+&i2c1 { - status = "okay"; - }; - --&u2phy { -- status = "okay"; -+&spi2 { -+// status = "okay"; //conflicts with UART2 -+ max-freq = <10000000>; - }; - --&u2phy_host { -+&uart0 { - status = "okay"; - }; - --&u2phy_otg { -+&uart2 { - status = "okay"; - }; - --&uart0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart0_xfer>; -+&uart4 { - status = "okay"; -+ -+ bluetooth { -+ compatible = "realtek,rtl8723bs-bt"; -+ device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; -+ host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; -+ }; - }; - --&uart4 { -- uart-has-rtscts; -+&u2phy { - status = "okay"; - -- bluetooth { -- compatible = "brcm,bcm43430a1-bt"; -- clocks = <&cru SCLK_RTC32K>; -- clock-names = "lpo"; -- interrupt-parent = <&gpio4>; -- interrupts = ; -- interrupt-names = "host-wakeup"; -- device-wakeup-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; -- shutdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; -- vbat-supply = <&vcc_io>; -- vddio-supply = <&vcc_1v8>; -+ u2phy_host: host-port { -+ phy-supply = <&vcc5v0_otg>; -+ status = "okay"; -+ }; -+ -+ u2phy_otg: otg-port { -+ status = "okay"; - }; - }; - --&usb_host_ehci { -+&usb20_otg { - status = "okay"; - }; - --&usb_host_ohci { -+&usb_host_ehci { - status = "okay"; - }; - --&usb20_otg { -- dr_mode = "peripheral"; -+&usb_host_ohci{ - status = "okay"; - }; - - &wdt { - status = "okay"; - }; -+ --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-station-m2.patch b/patch/kernel/rockchip64-6.14/board-station-m2.patch deleted file mode 100644 index 0d0e925..0000000 --- a/patch/kernel/rockchip64-6.14/board-station-m2.patch +++ /dev/null @@ -1,248 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: chainsx -Date: Fri, 21 Feb 2025 19:36:41 +0800 -Subject: fix rk3566-roc-pc - ---- - arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 110 +++++++--- - 1 file changed, 80 insertions(+), 30 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts -@@ -52,6 +52,16 @@ led-user { - pinctrl-0 = <&user_led_enable_h>; - retain-state-suspended; - }; -+ -+ led-firefly { -+ label = "firefly-led"; -+ default-state = "off"; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&firefly_led_enable_h>; -+ retain-state-suspended; -+ }; - }; - - rk809-sound { -@@ -70,6 +80,14 @@ simple-audio-card,codec { - }; - }; - -+ rk_headset: rk-headset { -+ compatible = "rockchip_headset"; -+ headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_det>; -+ io-channels = <&saradc 2>; //HP_HOOK pin -+ }; -+ - sdio_pwrseq: sdio-pwrseq { - status = "okay"; - compatible = "mmc-pwrseq-simple"; -@@ -124,7 +142,7 @@ vcc5v0_usb30_host: regulator-vcc5v0-usb30-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb30_host"; - enable-active-high; -- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb30_host_en_h>; - regulator-always-on; -@@ -137,7 +155,7 @@ vcc5v0_usb_otg: regulator-vcc5v0-usb-otg { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb_otg"; - enable-active-high; -- gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; -+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en_h>; - regulator-always-on; -@@ -171,6 +189,16 @@ &cpu3 { - cpu-supply = <&vdd_cpu>; - }; - -+&cpu_thermal { -+ trips { -+ cpu_hot: cpu_hot { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+}; -+ - &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; -@@ -465,20 +493,6 @@ vcc3v3_sd: SWITCH_REG2 { - }; - }; - --&i2c1 { -- status = "okay"; --}; -- --&i2c2 { -- status = "okay"; --}; -- --&i2c3 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c3m0_xfer>; -- status = "okay"; --}; -- - &i2s0_8ch { - status = "okay"; - }; -@@ -509,15 +523,15 @@ &pcie2x1 { - &pinctrl { - bt { - bt_enable_h: bt-enable-h { -- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; -+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { -- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; -+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bt_wake_l: bt-wake-l { -- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - -@@ -525,6 +539,10 @@ leds { - user_led_enable_h: user-led-enable-h { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ -+ firefly_led_enable_h: firefly-led-enable-h { -+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; - }; - - pcie { -@@ -543,7 +561,7 @@ pmic_int: pmic_int { - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -- -+ - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -551,12 +569,18 @@ wifi_enable_h: wifi-enable-h { - }; - - usb { -- vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { -- rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en-h { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en-h { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ }; - -- vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { -- rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ headphone { -+ hp_det: hp-det { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - }; -@@ -574,6 +598,11 @@ &pmu_io_domains { - vccio7-supply = <&vcc_3v3>; - }; - -+&saradc { -+ vref-supply = <&vcca_1v8>; -+ status = "okay"; -+}; -+ - &sdhci { - bus-width = <8>; - mmc-hs200-1_8v; -@@ -600,28 +629,36 @@ &sdmmc1 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; -+ disable-wp; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; - vmmc-supply = <&vcc3v3_sys>; - vqmmc-supply = <&vcca1v8_pmu>; - pinctrl-names = "default"; -- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; -+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &uart9m1_xfer &uart8m1_xfer>; - status = "okay"; - }; - --&tsadc { -+&sdmmc2 { -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ bus-width = <4>; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcca1v8_pmu>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; -+ sd-uhs-sdr104; - status = "okay"; - }; - --&uart0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart0_xfer>; -+&tsadc { - status = "okay"; - }; - - &uart1 { - pinctrl-names = "default"; -- pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; -+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; - status = "okay"; - uart-has-rtscts; - -@@ -653,6 +690,11 @@ &usb2phy0_otg { - status = "okay"; - }; - -+&usb2phy1_host { -+ phy-supply = <&vcc5v0_usb30_host>; -+ status = "okay"; -+}; -+ - &usb2phy1_otg { - phy-supply = <&vcc5v0_usb30_host>; - status = "okay"; -@@ -682,6 +724,14 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ - &vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/board-station-p2.patch b/patch/kernel/rockchip64-6.14/board-station-p2.patch deleted file mode 100644 index 4d568d0..0000000 --- a/patch/kernel/rockchip64-6.14/board-station-p2.patch +++ /dev/null @@ -1,599 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: chainsx -Date: Thu, 25 Jul 2024 16:40:28 +0200 -Subject: [ARCHEOLOGY] fix rk3568-roc-pc - -> X-Git-Archeology: - Revision 1c7c5d302dbc52a5c9a16a4e9f12786277e56fac: https://github.com/armbian/build/commit/1c7c5d302dbc52a5c9a16a4e9f12786277e56fac -> X-Git-Archeology: Date: Thu, 25 Jul 2024 16:40:28 +0200 -> X-Git-Archeology: From: chainsx -> X-Git-Archeology: Subject: fix rk3568-roc-pc -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts | 380 ++++++++-- - 1 file changed, 325 insertions(+), 55 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts -@@ -48,17 +48,15 @@ gmac1_clkin: external-gmac1-clock { - #clock-cells = <0>; - }; - -- leds { -+ firefly_leds: leds { - compatible = "gpio-leds"; -- -- led-user { -- label = "user-led"; -+ power_led: power { -+ label = "firefly:blue:power"; -+ linux,default-trigger = "ir-power-click"; - default-state = "on"; - gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; -- pinctrl-0 = <&user_led_enable_h>; -- retain-state-suspended; -+ pinctrl-0 = <&led_power>; - }; - }; - -@@ -126,41 +124,134 @@ vcc5v0_sys: regulator-vcc5v0-sys { - vin-supply = <&dc_12v>; - }; - -- vcc5v0_usb: regulator-vcc5v0-usb { -- compatible = "regulator-fixed"; -- regulator-name = "vcc5v0_usb"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- - vcc5v0_host: regulator-vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - enable-active-high; -- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-always-on; -- vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_otg: regulator-vcc5v0-otg { - compatible = "regulator-fixed"; -- regulator-name = "vcc5v0_otg"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; -- vin-supply = <&vcc5v0_usb>; -+ regulator-name = "vcc5v0_otg"; - }; --}; - --&combphy0 { -- /* used for USB3 */ -- status = "okay"; -+ vcc2v5_sys: vcc2v5-ddr-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc2v5-sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vcc_hub_power: vcc-hub-power-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_hub_power_en>; -+ regulator-name = "vcc_hub_power_en"; -+ regulator-always-on; -+ }; -+ -+ vcc_hub_reset: vcc-hub-reset-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_hub_reset_en>; -+ regulator-name = "vcc_hub_reset_en"; -+ regulator-always-on; -+ }; -+ -+ pcie_pi6c_oe: pcie-pi6c-oe-regulator { -+ compatible = "regulator-fixed"; -+ //enable-active-high; -+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_pi6c_oe_en>; -+ regulator-name = "pcie_pi6c_oe_en"; -+ regulator-always-on; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ status = "okay"; -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk809 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h>; -+ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; -+ post-power-on-delay-ms = <100>; -+ }; -+ -+ wireless_wlan: wireless-wlan { -+ compatible = "wlan-platdata"; -+ rockchip,grf = <&grf>; -+ wifi_chip_type = "ap6275s"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_host_wake_irq>; -+ WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+ wireless_bluetooth: wireless-bluetooth { -+ compatible = "bluetooth-platdata"; -+ clocks = <&rk809 1>; -+ clock-names = "ext_clock"; -+ //wifi-bt-power-toggle; -+ uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default", "rts_gpio"; -+ pinctrl-0 = <&uart8m0_rtsn>; -+ pinctrl-1 = <&uart8_gpios>; -+ BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; -+ BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; -+ BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+ flash_led: flash-led { -+ compatible = "led,rgb13h"; -+ label = "pwm-flash-led"; -+ led-max-microamp = <20000>; -+ flash-max-microamp = <20000>; -+ flash-max-timeout-us = <1000000>; -+ pwms = <&pwm11 0 25000 0>; -+ rockchip,camera-module-index = <1>; -+ rockchip,camera-module-facing = "front"; -+ status = "disabled"; -+ }; -+ -+ rk809-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "Analog RK809"; -+ simple-audio-card,mclk-fs = <256>; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1_8ch>; -+ }; -+ simple-audio-card,codec { -+ sound-dai = <&rk809>; -+ }; -+ }; -+ -+ rk_headset: rk-headset { -+ compatible = "rockchip_headset"; -+ headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_det>; -+ io-channels = <&saradc 2>; //HP_HOOK pin -+ }; - }; - - &combphy1 { -@@ -247,15 +338,59 @@ &hdmi_sound { - &i2c0 { - status = "okay"; - -+ fusb0: fusb30x@22 { -+ compatible = "fairchild,fusb302"; -+ reg = <0x22>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_int>; -+ int-n-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; -+ fusb340-switch-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; -+ vbus-5v-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ vin-supply = <&vcc5v0_sys>; -+ regulator-compatible = "fan53555-reg"; -+ regulator-name = "vdd_cpu"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1390000>; -+ regulator-ramp-delay = <2300>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-boot-on; -+ regulator-always-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; -+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; -+ assigned-clock-rates = <12288000>; -+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pmic_int>; -+ clock-names = "mclk"; -+ clocks = <&cru I2S1_MCLKOUT_TX>; -+ pinctrl-names = "default", "pmic-sleep", -+ "pmic-power-off", "pmic-reset"; -+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; -+ - system-power-controller; -+ #sound-dai-cells = <0>; -+ clock-output-names = "rk808-clkout1", "rk808-clkout2"; -+ //fb-inner-reg-idxs = <2>; -+ /* 1: rst regs (default in codes), 0: rst the pmic */ -+ pmic-reset-func = <0>; -+ /* not save the PMIC_POWER_EN register in uboot */ -+ not-save-power-en = <1>; -+ - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; -@@ -283,6 +418,8 @@ regulator-state-mem { - }; - - vdd_gpu: DCDC_REG2 { -+ regulator-always-on; -+ regulator-boot-on; - regulator-name = "vdd_gpu"; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; -@@ -317,19 +454,9 @@ regulator-state-mem { - }; - }; - -- vcc_1v8: DCDC_REG5 { -- regulator-name = "vcc_1v8"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- - vdda0v9_image: LDO_REG1 { -+ regulator-boot-on; -+ regulator-always-on; - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; -@@ -365,6 +492,8 @@ regulator-state-mem { - }; - - vccio_acodec: LDO_REG4 { -+ regulator-always-on; -+ regulator-boot-on; - regulator-name = "vccio_acodec"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -@@ -376,6 +505,8 @@ regulator-state-mem { - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; -+ regulator-always-on; -+ regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - -@@ -423,6 +554,8 @@ regulator-state-mem { - }; - - vcca1v8_image: LDO_REG9 { -+ regulator-always-on; -+ regulator-boot-on; - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -@@ -432,6 +565,17 @@ regulator-state-mem { - }; - }; - -+ vcc_1v8: DCDC_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; -@@ -452,6 +596,10 @@ regulator-state-mem { - }; - }; - }; -+ -+ codec { -+ mic-in-differential; -+ }; - }; - }; - -@@ -474,7 +622,7 @@ rgmii_phy1: phy@0 { - }; - - &pcie30phy { -- status = "okay"; -+ tatus = "okay"; - }; - - &pcie3x2 { -@@ -487,19 +635,27 @@ &pcie3x2 { - - &pinctrl { - leds { -- user_led_enable_h: user-led-enable-h { -- rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ led_power: led-power { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { -- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_otg_en: vcc5v0-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ -+ vcc_hub_power_en: vcc-hub-power-en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc_hub_reset_en: vcc-hub-reset-en { -+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; - }; - - pcie { -@@ -509,21 +665,53 @@ pcie_reset_pin: pcie-reset-pin { - vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ pcie_pi6c_oe_en: pcie-pi6c-oe-en { -+ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; - }; - - pmic { -- pmic_int: pmic-int { -+ pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -+ -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ wireless-wlan { -+ wifi_host_wake_irq: wifi-host-wake-irq { -+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ wireless-bluetooth { -+ uart8_gpios: uart8-gpios { -+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ fusb30x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ headphone { -+ hp_det: hp-det { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; - }; - - &pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; -- vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; -@@ -545,25 +733,44 @@ &sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; -- pinctrl-names = "default"; -- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+ supports-emmc; - status = "okay"; - }; - - &sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; -- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; -- pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; -+ max-frequency = <150000000>; -+ supports-sd; -+ cap-mmc-highspeed; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&sdmmc2 { -+ max-frequency = <150000000>; -+ supports-sdio; -+ bus-width = <4>; -+ disable-wp; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; -+ sd-uhs-sdr104; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; - status = "okay"; - }; - - &tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; - status = "okay"; - }; - -@@ -585,6 +792,7 @@ &usb2phy1 { - }; - - &usb2phy0_otg { -+ vbus-supply = <&vcc5v0_otg>; - status = "okay"; - }; - -@@ -606,6 +814,10 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usb_host0_xhci { -+ status = "okay"; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; -@@ -614,11 +826,13 @@ &usb_host1_ohci { - status = "okay"; - }; - --&usb_host0_xhci { -+&usb_host1_xhci { - status = "okay"; - }; - --&usb_host1_xhci { -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; - }; - -@@ -629,12 +843,68 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - }; - }; - --&vop { -- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+&vop_mmu { - status = "okay"; - }; - --&vop_mmu { -+&i2s1_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s1m0_sclktx -+ &i2s1m0_lrcktx -+ &i2s1m0_sdi0 -+ &i2s1m0_sdo0>; -+ rockchip,trcm-sync-tx-only; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ status = "okay"; -+}; -+ -+&i2c4 { -+ status = "okay"; -+}; -+ -+&i2c5 { -+ status = "okay"; -+}; -+ -+&gic { -+ status = "okay"; -+}; -+ -+&uart3 { -+// status = "disabled"; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart4m1_xfer>; -+ status = "okay"; -+}; -+ -+&uart8 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; -+}; -+ -+&rk809 { -+ rtc { -+ status = "disabled"; -+ }; -+}; -+ -+&pwm4 { -+ status = "okay"; -+}; -+ -+&pwm5 { -+ status = "okay"; -+}; -+ -+&pwm7 { - status = "okay"; - }; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/dt/rk3308-sakurapi-rk3308b.dts b/patch/kernel/rockchip64-6.14/dt/rk3308-sakurapi-rk3308b.dts deleted file mode 100755 index 5f0b3a6..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3308-sakurapi-rk3308b.dts +++ /dev/null @@ -1,337 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Akash Gajjar - * Copyright (c) 2019 Jagan Teki - * Copyright (C) 2024 TheSnowfield - */ - -/dts-v1/; -#include "rk3308.dtsi" -#include - -/ { - model = "Sakura Pi RK3308B"; - compatible = "rockchip,rk3308"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-0 = <&wifi_enable_h>; - pinctrl-names = "default"; - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - }; - - vcc5v0_sys: regulator-vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdd_core: regulator-vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-init-microvolt = <1015000>; - regulator-settling-time-up-us = <250>; - regulator-always-on; - regulator-boot-on; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: regulator-vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_ddr: regulator-vcc-ddr { - compatible = "regulator-fixed"; - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_io: regulator-vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_phy: regulator-vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_otg: regulator-vcc5v0-otg { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - regulator-always-on; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - vin-supply = <&vcc5v0_sys>; - }; - - backlight: backlight { - status = "okay"; - compatible = "pwm-backlight"; - pwms = <&pwm3 0 25000 0>; - brightness-levels = <0 255>; - default-brightness-level = <255>; - }; - - display: panel { - compatible = "edt,et070080dh6"; - backlight = <&backlight>; - enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - enable-delay-ms = <20>; - status = "okay"; - - panel_in: port { - #address-cells = <1>; - #size-cells = <0>; - - panel_in_rgb: endpoint { - reg = <0>; - remote-endpoint = <&vop_out_rgb>; - }; - }; - }; - -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&sdmmc { - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - card-detect-delay = <800>; - status = "okay"; -}; - -&sdio { - #address-cells = <1>; - #size-cells = <0>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - no-mmc; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm43455-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake>; - }; -}; - -&dmac0 { - status = "okay"; -}; - -/* SPI0 for external gpio pin */ -&spi0 { - status = "okay"; - - spi_dev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <0x2faf080>; - }; -}; - -/* SPI1 for ws2812*/ -&spi1 { - status = "okay"; - - spi_dev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <0x2faf080>; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - - usb { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake: wifi-host-wake { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - bluetooth { - bt_reg_on: bt-reg-on { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_host: bt-wake-host { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - host_wake_bt: host-wake-bt { - rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_pin_pull_down>; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&vop { - status = "okay"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_rgb: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_rgb>; - }; - }; -}; - -&pwm3 { - status = "okay"; -}; - -&display_subsystem { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&cru SCLK_RTC32K>; - clock-names = "lpo"; - pinctrl-names = "default"; - pinctrl-0 = <&host_wake_bt &bt_wake_host &bt_reg_on>; - device-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - max-speed = <1500000>; - }; -}; - -&tsadc{ - status = "okay"; -}; - -&usb20_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci{ - status = "okay"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3318-box.dts b/patch/kernel/rockchip64-6.14/dt/rk3318-box.dts deleted file mode 100644 index 7690565..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3318-box.dts +++ /dev/null @@ -1,1009 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Paolo Sabatino - */ - -/dts-v1/; -#include "dt-bindings/pwm/pwm.h" -#include "dt-bindings/input/input.h" -#include -#include -#include "rk3328.dtsi" - -/ { - model = "Rockchip RK3318 BOX"; - compatible = "rockchip,rk3318-box", "rockchip,rk3328-box", "rockchip,rk3328"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &sdio; - mmc2 = &emmc; - mmc3 = &sdmmc_ext; - mmc4 = &sdio_ext; - }; - - /delete-node/ opp-table-0; - /delete-node/ gpu-opp-table; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <40000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1200000>; - clock-latency-ns = <40000>; - status = "disabled"; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1275000>; - clock-latency-ns = <40000>; - status = "disabled"; - }; - }; - - gpu_opp_table: gpu-opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000 950000 1200000>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1050000 950000 1200000>; - }; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000 950000 1200000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1100000 950000 1200000>; - }; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc_keys: adc-keys { - - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - recovery { - label = "recovery"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; - - gmac_clkin: gmac-clkin { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0x00>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <0x01>; - #size-cells = <0x00>; - - vcc_18: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vccio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_io: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vccio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - /* - * USB3 vbus - */ - vcc_host_vbus: vcc-host-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_host_drv>; - regulator-name = "vcc_host_vbus"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_sys>; - }; - - /* - * USB2 OTG vbus - */ - vcc_otg_vbus: vcc-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_otg_vbus"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_sys>; - }; - - vdd_arm: vdd-arm { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 PWM_POLARITY_INVERTED>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-settling-time-up-us = <250>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_logic: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <12500>; - regulator-settling-time-up-us = <250>; - regulator-always-on; - regulator-boot-on; - }; - - gpio_led: gpio-leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&working_led>; - - working { - gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - default-state = "on"; - }; - - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&ir_int>; - pinctrl-names = "default"; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - - /* - wireless-bluetooth { - compatible = "bluetooth-platdata"; - uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart0_rts>; - pinctrl-1 = <&uart0_rts_gpio>; - BT,power_gpio = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - }; - - wireless-wlan { - compatible = "wlan-platdata"; - rockchip,grf = <&grf>; - wifi_chip_type = "ap6330"; - sdio_vref = <1800>; - WIFI,host_wake_irq = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; - }; - */ - - fd628_dev { - compatible = "fd628_dev"; - fd628_gpio_clk = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; - fd628_gpio_dat = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - analog-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "ANALOG"; - - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - }; - }; - - hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,name = "HDMI"; - - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - /* - * This node is a duplicate of sdmmc_ext: most common board do not use sdmmc_ext - * controller, so it is left unused. Some other boards use it as sdio controller - * for wifi and some others use it as sdcard controller. - * To handle the most critical situation, the controller will be configured as - * sdcard controller by default. An overlay can be set to disable the sdmmc_ext - * node and enable this sdio_ext in case wifi chips are attached to this. - * Note also that the node name is a non-convential "sdio@...", to differentiate - * it from the mmc@ff5f0000 node in the base device tree. - */ - sdio_ext: sdio@ff5f0000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff5f0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, - <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMCEXT>; - reset-names = "reset"; - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - keep-power-in-suspend; - mmc-pwrseq = <>; - non-removable; - num-slots = <1>; - pinctrl-0 = <&sdmmc0ext_cmd &sdmmc0ext_clk &sdmmc0ext_bus4>; - pinctrl-names = "default"; - supports-sdio; - status = "disabled"; - }; - - ddr_timing: ddr_timing { - compatible = "rockchip,ddr-timing"; - ddr3_speed_bin = ; - ddr4_speed_bin = ; - pd_idle = <0>; - sr_idle = <0>; - sr_mc_gate_idle = <0>; - srpd_lite_idle = <0>; - standby_idle = <0>; - - auto_pd_dis_freq = <1066>; - auto_sr_dis_freq = <800>; - ddr3_dll_dis_freq = <300>; - ddr4_dll_dis_freq = <625>; - phy_dll_dis_freq = <400>; - - ddr3_odt_dis_freq = <100>; - phy_ddr3_odt_dis_freq = <100>; - ddr3_drv = ; - ddr3_odt = ; - phy_ddr3_ca_drv = ; - phy_ddr3_ck_drv = ; - phy_ddr3_dq_drv = ; - phy_ddr3_odt = ; - - lpddr3_odt_dis_freq = <666>; - phy_lpddr3_odt_dis_freq = <666>; - lpddr3_drv = ; - lpddr3_odt = ; - phy_lpddr3_ca_drv = ; - phy_lpddr3_ck_drv = ; - phy_lpddr3_dq_drv = ; - phy_lpddr3_odt = ; - - lpddr4_odt_dis_freq = <800>; - phy_lpddr4_odt_dis_freq = <800>; - lpddr4_drv = ; - lpddr4_dq_odt = ; - lpddr4_ca_odt = ; - phy_lpddr4_ca_drv = ; - phy_lpddr4_ck_cs_drv = ; - phy_lpddr4_dq_drv = ; - phy_lpddr4_odt = ; - - ddr4_odt_dis_freq = <666>; - phy_ddr4_odt_dis_freq = <666>; - ddr4_drv = ; - ddr4_odt = ; - phy_ddr4_ca_drv = ; - phy_ddr4_ck_drv = ; - phy_ddr4_dq_drv = ; - phy_ddr4_odt = ; - - /* CA de-skew, one step is 47.8ps, range 0-15 */ - ddr3a1_ddr4a9_de-skew = <2>; - ddr3a0_ddr4a10_de-skew = <3>; - ddr3a3_ddr4a6_de-skew = <3>; - ddr3a2_ddr4a4_de-skew = <2>; - ddr3a5_ddr4a8_de-skew = <3>; - ddr3a4_ddr4a5_de-skew = <2>; - ddr3a7_ddr4a11_de-skew = <3>; - ddr3a6_ddr4a7_de-skew = <2>; - ddr3a9_ddr4a0_de-skew = <2>; - ddr3a8_ddr4a13_de-skew = <1>; - ddr3a11_ddr4a3_de-skew = <2>; - ddr3a10_ddr4cs0_de-skew = <2>; - ddr3a13_ddr4a2_de-skew = <1>; - ddr3a12_ddr4ba1_de-skew = <2>; - ddr3a15_ddr4odt0_de-skew = <3>; - ddr3a14_ddr4a1_de-skew = <2>; - ddr3ba1_ddr4a15_de-skew = <2>; - ddr3ba0_ddr4bg0_de-skew = <4>; - ddr3ras_ddr4cke_de-skew = <4>; - ddr3ba2_ddr4ba0_de-skew = <3>; - ddr3we_ddr4bg1_de-skew = <2>; - ddr3cas_ddr4a12_de-skew = <2>; - ddr3ckn_ddr4ckn_de-skew = <11>; - ddr3ckp_ddr4ckp_de-skew = <11>; - ddr3cke_ddr4a16_de-skew = <2>; - ddr3odt0_ddr4a14_de-skew = <4>; - ddr3cs0_ddr4act_de-skew = <4>; - ddr3reset_ddr4reset_de-skew = <7>; - ddr3cs1_ddr4cs1_de-skew = <7>; - ddr3odt1_ddr4odt1_de-skew = <7>; - - /* DATA de-skew - * RX one step is 25.1ps, range 0-15 - * TX one step is 47.8ps, range 0-15 - */ - cs0_dm0_rx_de-skew = <12>; - cs0_dm0_tx_de-skew = <10>; - cs0_dq0_rx_de-skew = <12>; - cs0_dq0_tx_de-skew = <10>; - cs0_dq1_rx_de-skew = <12>; - cs0_dq1_tx_de-skew = <10>; - cs0_dq2_rx_de-skew = <12>; - cs0_dq2_tx_de-skew = <10>; - cs0_dq3_rx_de-skew = <12>; - cs0_dq3_tx_de-skew = <10>; - cs0_dq4_rx_de-skew = <12>; - cs0_dq4_tx_de-skew = <10>; - cs0_dq5_rx_de-skew = <12>; - cs0_dq5_tx_de-skew = <10>; - cs0_dq6_rx_de-skew = <12>; - cs0_dq6_tx_de-skew = <10>; - cs0_dq7_rx_de-skew = <12>; - cs0_dq7_tx_de-skew = <10>; - cs0_dqs0_rx_de-skew = <10>; - cs0_dqs0p_tx_de-skew = <12>; - cs0_dqs0n_tx_de-skew = <12>; - - cs0_dm1_rx_de-skew = <10>; - cs0_dm1_tx_de-skew = <8>; - cs0_dq8_rx_de-skew = <10>; - cs0_dq8_tx_de-skew = <8>; - cs0_dq9_rx_de-skew = <10>; - cs0_dq9_tx_de-skew = <8>; - cs0_dq10_rx_de-skew = <10>; - cs0_dq10_tx_de-skew = <8>; - cs0_dq11_rx_de-skew = <10>; - cs0_dq11_tx_de-skew = <8>; - cs0_dq12_rx_de-skew = <10>; - cs0_dq12_tx_de-skew = <8>; - cs0_dq13_rx_de-skew = <10>; - cs0_dq13_tx_de-skew = <8>; - cs0_dq14_rx_de-skew = <10>; - cs0_dq14_tx_de-skew = <8>; - cs0_dq15_rx_de-skew = <10>; - cs0_dq15_tx_de-skew = <8>; - cs0_dqs1_rx_de-skew = <9>; - cs0_dqs1p_tx_de-skew = <10>; - cs0_dqs1n_tx_de-skew = <10>; - - cs0_dm2_rx_de-skew = <10>; - cs0_dm2_tx_de-skew = <9>; - cs0_dq16_rx_de-skew = <10>; - cs0_dq16_tx_de-skew = <9>; - cs0_dq17_rx_de-skew = <10>; - cs0_dq17_tx_de-skew = <9>; - cs0_dq18_rx_de-skew = <10>; - cs0_dq18_tx_de-skew = <9>; - cs0_dq19_rx_de-skew = <10>; - cs0_dq19_tx_de-skew = <9>; - cs0_dq20_rx_de-skew = <10>; - cs0_dq20_tx_de-skew = <9>; - cs0_dq21_rx_de-skew = <10>; - cs0_dq21_tx_de-skew = <9>; - cs0_dq22_rx_de-skew = <10>; - cs0_dq22_tx_de-skew = <9>; - cs0_dq23_rx_de-skew = <10>; - cs0_dq23_tx_de-skew = <9>; - cs0_dqs2_rx_de-skew = <9>; - cs0_dqs2p_tx_de-skew = <11>; - cs0_dqs2n_tx_de-skew = <11>; - - cs0_dm3_rx_de-skew = <7>; - cs0_dm3_tx_de-skew = <7>; - cs0_dq24_rx_de-skew = <7>; - cs0_dq24_tx_de-skew = <7>; - cs0_dq25_rx_de-skew = <7>; - cs0_dq25_tx_de-skew = <7>; - cs0_dq26_rx_de-skew = <7>; - cs0_dq26_tx_de-skew = <7>; - cs0_dq27_rx_de-skew = <7>; - cs0_dq27_tx_de-skew = <7>; - cs0_dq28_rx_de-skew = <7>; - cs0_dq28_tx_de-skew = <7>; - cs0_dq29_rx_de-skew = <7>; - cs0_dq29_tx_de-skew = <7>; - cs0_dq30_rx_de-skew = <7>; - cs0_dq30_tx_de-skew = <7>; - cs0_dq31_rx_de-skew = <7>; - cs0_dq31_tx_de-skew = <7>; - cs0_dqs3_rx_de-skew = <7>; - cs0_dqs3p_tx_de-skew = <10>; - cs0_dqs3n_tx_de-skew = <10>; - - cs1_dm0_rx_de-skew = <7>; - cs1_dm0_tx_de-skew = <8>; - cs1_dq0_rx_de-skew = <7>; - cs1_dq0_tx_de-skew = <8>; - cs1_dq1_rx_de-skew = <7>; - cs1_dq1_tx_de-skew = <8>; - cs1_dq2_rx_de-skew = <7>; - cs1_dq2_tx_de-skew = <8>; - cs1_dq3_rx_de-skew = <7>; - cs1_dq3_tx_de-skew = <8>; - cs1_dq4_rx_de-skew = <7>; - cs1_dq4_tx_de-skew = <8>; - cs1_dq5_rx_de-skew = <7>; - cs1_dq5_tx_de-skew = <8>; - cs1_dq6_rx_de-skew = <7>; - cs1_dq6_tx_de-skew = <8>; - cs1_dq7_rx_de-skew = <7>; - cs1_dq7_tx_de-skew = <8>; - cs1_dqs0_rx_de-skew = <6>; - cs1_dqs0p_tx_de-skew = <9>; - cs1_dqs0n_tx_de-skew = <9>; - - cs1_dm1_rx_de-skew = <7>; - cs1_dm1_tx_de-skew = <7>; - cs1_dq8_rx_de-skew = <7>; - cs1_dq8_tx_de-skew = <8>; - cs1_dq9_rx_de-skew = <7>; - cs1_dq9_tx_de-skew = <7>; - cs1_dq10_rx_de-skew = <7>; - cs1_dq10_tx_de-skew = <8>; - cs1_dq11_rx_de-skew = <7>; - cs1_dq11_tx_de-skew = <7>; - cs1_dq12_rx_de-skew = <7>; - cs1_dq12_tx_de-skew = <8>; - cs1_dq13_rx_de-skew = <7>; - cs1_dq13_tx_de-skew = <7>; - cs1_dq14_rx_de-skew = <7>; - cs1_dq14_tx_de-skew = <8>; - cs1_dq15_rx_de-skew = <7>; - cs1_dq15_tx_de-skew = <7>; - cs1_dqs1_rx_de-skew = <7>; - cs1_dqs1p_tx_de-skew = <9>; - cs1_dqs1n_tx_de-skew = <9>; - - cs1_dm2_rx_de-skew = <7>; - cs1_dm2_tx_de-skew = <8>; - cs1_dq16_rx_de-skew = <7>; - cs1_dq16_tx_de-skew = <8>; - cs1_dq17_rx_de-skew = <7>; - cs1_dq17_tx_de-skew = <8>; - cs1_dq18_rx_de-skew = <7>; - cs1_dq18_tx_de-skew = <8>; - cs1_dq19_rx_de-skew = <7>; - cs1_dq19_tx_de-skew = <8>; - cs1_dq20_rx_de-skew = <7>; - cs1_dq20_tx_de-skew = <8>; - cs1_dq21_rx_de-skew = <7>; - cs1_dq21_tx_de-skew = <8>; - cs1_dq22_rx_de-skew = <7>; - cs1_dq22_tx_de-skew = <8>; - cs1_dq23_rx_de-skew = <7>; - cs1_dq23_tx_de-skew = <8>; - cs1_dqs2_rx_de-skew = <6>; - cs1_dqs2p_tx_de-skew = <9>; - cs1_dqs2n_tx_de-skew = <9>; - - cs1_dm3_rx_de-skew = <7>; - cs1_dm3_tx_de-skew = <7>; - cs1_dq24_rx_de-skew = <7>; - cs1_dq24_tx_de-skew = <8>; - cs1_dq25_rx_de-skew = <7>; - cs1_dq25_tx_de-skew = <7>; - cs1_dq26_rx_de-skew = <7>; - cs1_dq26_tx_de-skew = <7>; - cs1_dq27_rx_de-skew = <7>; - cs1_dq27_tx_de-skew = <7>; - cs1_dq28_rx_de-skew = <7>; - cs1_dq28_tx_de-skew = <7>; - cs1_dq29_rx_de-skew = <7>; - cs1_dq29_tx_de-skew = <7>; - cs1_dq30_rx_de-skew = <7>; - cs1_dq30_tx_de-skew = <7>; - cs1_dq31_rx_de-skew = <7>; - cs1_dq31_tx_de-skew = <7>; - cs1_dqs3_rx_de-skew = <7>; - cs1_dqs3p_tx_de-skew = <9>; - cs1_dqs3n_tx_de-skew = <9>; - }; - -}; - -&dfi { - status = "okay"; -}; - -&dmc { - center-supply = <&vdd_logic>; - ddr_timing = <&ddr_timing>; - status = "disabled"; -}; - -&codec { - status = "okay"; - mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&display_subsystem { - status = "okay"; -}; - -&emmc { - - supports-emmc; - no-sdio; - no-sd; - cap-mmc-highspeed; - disable-wp; - non-removable; - bus-width = <8>; - num-slots = <0x01>; - - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_18>; - - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <500>; - cd-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; - disable-wp; - no-sdio; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - supports-sd; - status = "okay"; - vmmc-supply = <&vcc_sd>; -}; - -&sdio { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - supports-sdio; - status = "okay"; -}; - -/* - * sdmmc_ext is configured as sdcard controller and enabled by default. - * In this way boards which have the sdcard attached to sdmmc_ext will work - * by default. In case the controller is not attached to anything, the - * kernel will just autodetect and give up. - */ -&sdmmc_ext { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <500>; - cd-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - disable-wp; - no-sdio; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_dectn &sdmmc0ext_bus4>; - supports-sd; - status = "okay"; - vmmc-supply = <&vcc_sd>; -}; - -&gmac2phy { - phy-supply = <&vcc_phy>; - - phy-mode = "rmii"; - - clock_in_out = "output"; - assigned-clocks = <&cru SCLK_MAC2PHY>; - assigned-clock-rate = <50000000>; - assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - tx_delay = <0x30>; - rx_delay = <0x10>; - - status = "okay"; - -}; - -&gpu { - status = "okay"; - mali-supply = <&vdd_logic>; -}; - -/* -&h265e { - status = "okay"; -}; -*/ - -&h265e_mmu { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&spdif { - pinctrl-0 = <&spdifm0_tx>; - status = "okay"; -}; - -&spdif_out { - status = "okay"; -}; - -&spdif_sound { - status = "okay"; -}; - -&hdmiphy { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc_18>; - vccio3-supply = <&vcc_io>; - vccio4-supply = <&vcc_18>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&clk_32k_out>; - - clk_32k { - clk_32k_out: clk-32k-out { - rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; - }; - }; - - leds { - working_led: working-led { - rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none_2ma>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_4ma>;/*, - <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none_4ma>;*/ - }; - }; - - usb2 { - usb20_host_drv: usb20-host-drv { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb3 { - usb30_host_drv: usb30-host-drv { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - - /* - * SDIO host wake interrupt on YX_RK3328 board (sdio is attached to - * regular mmc controller mmc@ff510000) - */ - sdio_host_wake: sdio-host-wake { - rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * SDIO host wake interrupt on X88_PRO_B board (sdio is attached to - * alternative mmc controller mmc@ff5f0000) - */ - sdio_host_wake_ext: sdio-host-wake-ext { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - }; - -}; - -/* -&vdec { - status = "okay"; - vcodec-supply = <&vdd_logic>; -}; -*/ - -&vdec_mmu { - status = "okay"; -}; - -&threshold { - temperature = <80000>; /* millicelsius */ -}; - -&target { - temperature = <95000>; /* millicelsius */ -}; - -&soc_crit { - temperature = <100000>; /* millicelsius */ -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart0 { - - status = "okay"; - -}; - -&uart2 { - /delete-property/ dmas; - /delete-property/ dma-names; - - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&usb20_otg { - dr_mode = "host"; - resets = <&cru SRST_USB2OTG>; - reset-names = "dwc2"; - status = "okay"; -}; - -&usb_host0_ehci { - resets = <&cru SRST_USB2HOST_EHCIPHY>; - reset-names = "ehci"; - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usbdrd3 { - #address-cells = <1>; - #size-cells = <0>; - dr_mode = "host"; - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vpu { - status = "okay"; - vcodec-supply = <&vdd_logic>; -}; - -&vpu_mmu { - status = "okay"; -}; - -/* -&vepu { - status = "okay"; -}; -*/ - -&vepu_mmu { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -/* -&rga { - status = "okay"; -}; -*/ - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&analog_sound { - status = "okay"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3328-heltec.dts b/patch/kernel/rockchip64-6.14/dt/rk3328-heltec.dts deleted file mode 100644 index c493f3a..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3328-heltec.dts +++ /dev/null @@ -1,288 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Rockchip RK3328 Heltec"; - compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &sdio; - mmc2 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; -}; - -&gmac2phy { - phy-supply = <&vcc_phy>; - clock_in_out = "output"; - assigned-clock-rate = <50000000>; - assigned-clocks = <&cru SCLK_MAC2PHY>; - assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - max-frequency = <150000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3328-mksklipad50.dts b/patch/kernel/rockchip64-6.14/dt/rk3328-mksklipad50.dts deleted file mode 100644 index 1bb606b..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3328-mksklipad50.dts +++ /dev/null @@ -1,620 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Based on rk3328-roc-cc.dtb from original MKS-Klipad50 image - * - * Copyright (c) 2025 Thorsten Maerz - */ - -/dts-v1/; -#include "rk3328-dram-renegade-timing.dtsi" -#include "rk3328.dtsi" - -/ { - model = "Makerbase MKS-KLIPAD50"; - compatible = "mks,rk3328-mksklipad50", "mks,rk3328-mkspi", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - ethernet1 = &gmac2phy; - mmc0 = &sdmmc; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - /delete-node/ dmc-opp-table; - dmc_opp_table: dmc-opp-table { - compatible = "operating-points-v2"; - - opp-786000000 { - opp-hz = /bits/ 64 <786000000>; - opp-microvolt = <1075000 1075000 12000000>; - status = "disabled"; - }; - opp-798000000 { - opp-hz = /bits/ 64 <798000000>; - opp-microvolt = <1075000 1075000 12000000>; - status = "disabled"; - }; - opp-840000000 { - opp-hz = /bits/ 64 <840000000>; - opp-microvolt = <1075000 1075000 12000000>; - }; - opp-924000000 { - opp-hz = /bits/ 64 <924000000>; - opp-microvolt = <1100000 1100000 12000000>; - }; - opp-1068000000 { - opp-hz = /bits/ 64 <1068000000>; - opp-microvolt = <1175000 1175000 12000000>; - }; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-boot-on; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_sdio: sdmmcio-regulator { - compatible = "regulator-gpio"; - gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&sdio_vcc_pin>; - pinctrl-names = "default"; - states = <1800000 0x0>, - <3300000 0x1>; - regulator-name = "vcc_sdio"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-settling-time-us = <5000>; - startup-delay-us = <2000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_io>; - }; - - vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host1_5v"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - - power_led: led-0 { - label = "firefly:green:power"; - linux,default-trigger = "heartbeat"; - gpios = <&rk805 1 GPIO_ACTIVE_LOW>; - default-state = "on"; - mode = <0x23>; - }; - - user_led: led-1 { - label = "firefly:blue:user"; - linux,default-trigger = "activity"; - gpios = <&rk805 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - mode = <0x05>; - }; - }; - - usb3phy_grf: syscon@ff460000 { - compatible = "rockchip,usb3phy-grf", "syscon"; - reg = <0x0 0xff460000 0x0 0x1000>; - }; - - u3phy: usb3-phy@ff470000 { - compatible = "rockchip,rk3328-u3phy"; - reg = <0x0 0xff470000 0x0 0x0>; - rockchip,u3phygrf = <&usb3phy_grf>; - rockchip,grf = <&grf>; - interrupts = ; - interrupt-names = "linestate"; - clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; - clock-names = "u3phy-otg", "u3phy-pipe"; - resets = <&cru SRST_USB3PHY_U2>, - <&cru SRST_USB3PHY_U3>, - <&cru SRST_USB3PHY_PIPE>, - <&cru SRST_USB3OTG_UTMI>, - <&cru SRST_USB3PHY_OTG_P>, - <&cru SRST_USB3PHY_PIPE_P>; - reset-names = "u3phy-u2-por", "u3phy-u3-por", - "u3phy-pipe-mac", "u3phy-utmi-mac", - "u3phy-utmi-apb", "u3phy-pipe-apb"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "okay"; - - u3phy_utmi: utmi@ff470000 { - reg = <0x0 0xff470000 0x0 0x8000>; - #phy-cells = <0>; - status = "okay"; - }; - - u3phy_pipe: pipe@ff478000 { - reg = <0x0 0xff478000 0x0 0x8000>; - #phy-cells = <0>; - status = "okay"; - }; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - rockchip,grf = <&grf>; - sdio_vref = <3300>; - status = "okay"; - WIFI,host_wake_irq = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; - wifi_chip_type = "rtl8723bs"; - }; - - sdio_pwrseq0: sdio_pwrseq0 { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; -}; - -&analog_sound { - simple-audio-card,name = "TRS Jack"; - status = "okay"; -}; - -&codec { - mute-gpios = <&grf_gpio RK_PA0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gmac2phy { - assigned-clocks = <&cru SCLK_MAC2PHY>; - assigned-clock-rate = <50000000>; - assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - phy-supply = <&vcc_phy>; - status = "disabled"; -}; - -&dfi { - status = "okay"; -}; - -&dmc { - center-supply = <&vdd_logic>; - ddr_timing = <&ddr_timing>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <150000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,aal; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,rxpbl = <0x4>; - snps,txpbl = <0x4>; - tx_delay = <0x24>; - rx_delay = <0x18>; - status = "disabled"; -}; - -&gpu { - mali-supply = <&vdd_logic>; -}; - -&hdmi { - interrupts = , - ; - clocks = <&cru PCLK_HDMI>, - <&cru SCLK_HDMI_SFC>, - <&hdmiphy>, - <&cru SCLK_RTC32K>; - clock-names = "iahb", - "isfr", - "vpll", - "cec"; - pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd &hdmi_backlight>; - status = "okay"; -}; - -&hdmiphy { - status = "okay"; -}; - -&hdmi_sound { - status = "disabled"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1175000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <1400000>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&i2s1 { - status = "okay"; -}; - -&pwm3 { - interrupts = ; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_sdio>; - vccio4-supply = <&vcc_io>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - - rtc: rtc { - rtc_32k: rtc-32k { - rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - usb20_host_drv: usb20-host-drv { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sd { - sdio_vcc_pin: sdio-vcc-pin { - rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - - sdio_pwrseq: sdio-pwrseq { - - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless_wlan_pin: wireless-wlan { - - wifi_wake_host: wifi-wake-host { - rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - hdmi_pin { - hdmi_backlight: hdmi-backlight { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - spi0_cs2 { - pinctrl_spi0_cs2: pinctrl_spi0_cs2 { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&spdif { - pinctrl-0 = <&spdifm0_tx>; - status = "disabled"; -}; - -&spdif_out { - status = "disabled"; -}; - -&spdif_sound { - status = "disabled"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&spi0 { - max-freq = <48000000>; - cs-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx>; - status = "okay"; - - - spi_for_cs2@0 { - reg = <0>; - compatible ="armbian,spi-dev"; - pinctrl-names ="default"; - pinctrl-0 = <&pinctrl_spi0_cs2>; - spi-max-frequency = <5000000>; - status = "okay"; - }; -}; - -&sdio { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - mmc-pwrseq = <&sdio_pwrseq0>; - status = "okay"; - non-removable; - bus-width = <0x04>; - cap-sd-highspeed; - cap-sdio-irq; -}; - -&usb20_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_LCDC>; - assigned-clock-parents = <&cru HDMIPHY>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vpu { - status = "disabled"; -}; - -&vdec { - status = "disabled"; -}; - -&rga { - status = "disabled"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3328-mkspi.dts b/patch/kernel/rockchip64-6.14/dt/rk3328-mkspi.dts deleted file mode 100644 index 9b3c1c8..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3328-mkspi.dts +++ /dev/null @@ -1,592 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Based on rk3328-roc-cc.dts - * - * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd - */ - -/dts-v1/; -#include "rk3328-dram-renegade-timing.dtsi" -#include "rk3328.dtsi" - -/ { - model = "Makerbase MKS-PI"; - compatible = "mks,rk3328-mkspi", "rockchip,rk3328"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - /delete-node/ dmc-opp-table; - dmc_opp_table: dmc-opp-table { - compatible = "operating-points-v2"; - - opp-786000000 { - opp-hz = /bits/ 64 <786000000>; - opp-microvolt = <1075000 1075000 12000000>; - }; - opp-798000000 { - opp-hz = /bits/ 64 <798000000>; - opp-microvolt = <1075000 1075000 12000000>; - }; - opp-840000000 { - opp-hz = /bits/ 64 <840000000>; - opp-microvolt = <1075000 1075000 12000000>; - }; - opp-924000000 { - opp-hz = /bits/ 64 <924000000>; - opp-microvolt = <1100000 1100000 12000000>; - }; - opp-1068000000 { - opp-hz = /bits/ 64 <1068000000>; - opp-microvolt = <1175000 1175000 12000000>; - }; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-boot-on; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_sdio: sdmmcio-regulator { - compatible = "regulator-gpio"; - gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&sdio_vcc_pin>; - pinctrl-names = "default"; - states = <1800000 0x0>, - <3300000 0x1>; - regulator-name = "vcc_sdio"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_io>; - }; - - vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host1_5v"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - - power_led: led-0 { - label = "firefly:blue:power"; - linux,default-trigger = "heartbeat"; - gpios = <&rk805 1 GPIO_ACTIVE_LOW>; - default-state = "on"; - mode = <0x23>; - }; - - user_led: led-1 { - label = "firefly:yellow:user"; - linux,default-trigger = "mmc1"; - gpios = <&rk805 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - mode = <0x05>; - }; - }; - - usb3phy_grf: syscon@ff460000 { - compatible = "rockchip,usb3phy-grf", "syscon"; - reg = <0x0 0xff460000 0x0 0x1000>; - }; - - u3phy: usb3-phy@ff470000 { - compatible = "rockchip,rk3328-u3phy"; - reg = <0x0 0xff470000 0x0 0x0>; - rockchip,u3phygrf = <&usb3phy_grf>; - rockchip,grf = <&grf>; - interrupts = ; - interrupt-names = "linestate"; - clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; - clock-names = "u3phy-otg", "u3phy-pipe"; - resets = <&cru SRST_USB3PHY_U2>, - <&cru SRST_USB3PHY_U3>, - <&cru SRST_USB3PHY_PIPE>, - <&cru SRST_USB3OTG_UTMI>, - <&cru SRST_USB3PHY_OTG_P>, - <&cru SRST_USB3PHY_PIPE_P>; - reset-names = "u3phy-u2-por", "u3phy-u3-por", - "u3phy-pipe-mac", "u3phy-utmi-mac", - "u3phy-utmi-apb", "u3phy-pipe-apb"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "okay"; - - u3phy_utmi: utmi@ff470000 { - reg = <0x0 0xff470000 0x0 0x8000>; - #phy-cells = <0>; - status = "okay"; - }; - - u3phy_pipe: pipe@ff478000 { - reg = <0x0 0xff478000 0x0 0x8000>; - #phy-cells = <0>; - status = "okay"; - }; - }; - -}; - -&analog_sound { - status = "disabled"; -}; - -&codec { - status = "okay"; -}; - -&gmac2phy { - assigned-clocks = <&cru SCLK_MAC2PHY>; - assigned-clock-rate = <50000000>; - assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - phy-supply = <&vcc_phy>; - status = "okay"; -}; - -&dfi { - status = "okay"; -}; - -&dmc { - center-supply = <&vdd_logic>; - ddr_timing = <&ddr_timing>; - status = "okay"; -}; - - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <150000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,aal; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,rxpbl = <0x4>; - snps,txpbl = <0x4>; - tx_delay = <0x24>; - rx_delay = <0x18>; - status = "disabled"; -}; - -&gpu { - mali-supply = <&vdd_logic>; -}; - -&hdmi { - interrupts = , - ; - clocks = <&cru PCLK_HDMI>, - <&cru SCLK_HDMI_SFC>, - <&hdmiphy>, //0x4b - <&cru SCLK_RTC32K>; - clock-names = "iahb", - "isfr", - "vpll", - "cec"; - status = "okay"; -}; - -&hdmiphy { - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_sdio>; - vccio4-supply = <&vcc_io>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; -}; - -&pinctrl { - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - usb20_host_drv: usb20-host-drv { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sd { - sdio_vcc_pin: sdio-vcc-pin { - rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touchscreen { - pinctrl_tsc2046_pendown: pinctrl_tsc2046_pendown { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - pinctrl_tsc2046_cs: pinctrl_tsc2046_cs { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - pinctrl_st7796_cs: pinctrl_st7796_cs { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - spi0_cs2 { - pinctrl_spi0_cs2: pinctrl_spi0_cs2 { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&spdif { - pinctrl-0 = <&spdifm0_tx>; - status = "okay"; -}; - -&spdif_out { - status = "okay"; -}; - -&spdif_sound { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&spi0 { - max-freq = <48000000>; - cs-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>,<&gpio3 RK_PA7 GPIO_ACTIVE_LOW>,<&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx>; - status = "okay"; - - spi_for_lcd@0 { - compatible ="ilitek,st7796"; - pinctrl-names ="default"; - pinctrl-0 = <&pinctrl_st7796_cs>; - reg = <0>; - spi-max-frequency = <25000000>; - bgr; - fps = <30>; - rotate = <270>; - buswidth = <8>; - dc-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; /* gpio3 A6 */ - reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; /* gpio3 A4 */ - led-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* gpio3 A5 */ - status = "okay"; - }; - - spi_for_touch@1 { - reg = <1>; - compatible = "ti,tsc2046"; - pinctrl-names ="default"; - pinctrl-0 = <&pinctrl_tsc2046_pendown &pinctrl_tsc2046_cs>; - ti,x-max = /bits/ 16 <3776>; - ti,x-min = /bits/ 16 <164>; - ti,y-min = /bits/ 16 <201>; - ti,y-max = /bits/ 16 <3919>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,pressure-max = /bits/ 16 <255>; - //touchscreen-fuzz-x = <16>; - //touchscreen-fuzz-y = <16>; - //touchscreen-fuzz-pressure = <10>; - ti,swap-xy = <1>; - touchscreen-inverted-y = <1>; - interrupt-parent = <&gpio1>; - interrupts = ; - spi-max-frequency = <2000000>; - pendown-gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; - vcc-supply = <&vcc_io>; - wakeup-source; - status = "okay"; - }; - - spi_for_cs2@2 { - reg = <2>; - compatible ="armbian,spi-dev"; - pinctrl-names ="default"; - pinctrl-0 = <&pinctrl_spi0_cs2>; - spi-max-frequency = <5000000>; - status = "okay"; - }; -}; - -&usb20_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_LCDC>; - assigned-clock-parents = <&cru HDMIPHY>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-neo3-rev02.dts b/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-neo3-rev02.dts deleted file mode 100644 index 496e334..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-neo3-rev02.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - */ - -/dts-v1/; -#include -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "FriendlyElec NanoPi NEO3"; - compatible = "friendlyelec,nanopi-neo3", "rockchip,rk3328"; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key1>; - - button@0 { - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - }; - - i2s-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "I2S Out"; - status = "okay"; - - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&pcm5102>; - }; - }; - - pcm5102: pcm510x { - #sound-dai-cells = <0>; - compatible = "ti,pcm5102a"; - pcm510x,format = "i2s"; - }; - - sound-spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - vcc_rtl8153: vcc-rtl8153-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_en_drv>; - regulator-always-on; - regulator-name = "vcc_rtl8153"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - off-on-delay-us = <5000>; - enable-active-high; - }; -}; - -&mach { - hwrev = <2>; - model = "NanoPi NEO3"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_mclk - &i2s1_sclk - &i2s1_lrcktx - &i2s1_lrckrx - &i2s1_sdo - &i2s1_sdi>; - status = "okay"; -}; - -&spdif { - status = "okay"; - pinctrl-0 = <&spdifm0_tx>; -}; - -&emmc { - status = "disabled"; -}; - -&i2c0 { - status = "okay"; -}; - -&leds { - status = "okay"; - -}; - -&leds_gpio { - rockchip,pins = - <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -}; - -&pwm2 { - pinctrl-names = "default", "sleep"; - pinctrl-1 = <&pwm2_sleep_pin>; - status = "okay"; -}; - -&rk805 { - interrupt-parent = <&gpio1>; - interrupts = ; -}; - -&vccio_sd { - status = "okay"; -}; - -&io_domains { - vccio3-supply = <&vccio_sd>; -}; - -&sdmmc { - vqmmc-supply = <&vccio_sd>; - max-frequency = <150000000>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc_ext { - status = "disabled"; -}; - -&sdio_pwrseq { - status = "disabled"; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pwm { - pwm2_sleep_pin: pwm2-sleep-pin { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - rockchip-key { - gpio_key1: gpio-key1 { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usb30_en_drv: usb30-en-drv { - rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&uart1{ - status = "okay"; - pinctl-0 = <&uart1_xfer>; -}; - diff --git a/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev00.dts b/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev00.dts deleted file mode 100644 index 8ba9518..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev00.dts +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - */ - -/dts-v1/; -#include -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "FriendlyElec NanoPi R2S"; - compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key1>; - - button@0 { - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - }; - - vcc_rtl8153: vcc-rtl8153-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_en_drv>; - regulator-always-on; - regulator-name = "vcc_rtl8153"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - off-on-delay-us = <5000>; - enable-active-high; - }; -}; - -&mach { - hwrev = <0>; - model = "NanoPi R2S"; -}; - -&emmc { - status = "disabled"; -}; - -&i2c0 { - status = "okay"; -}; - -&leds { - status = "okay"; - - led@2 { - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - label = "lan_led"; - }; - - led@3 { - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; - label = "wan_led"; - }; -}; - -&rk805 { - interrupt-parent = <&gpio1>; - interrupts = ; -}; - -&vccio_sd { - status = "okay"; -}; - -&io_domains { - vccio3-supply = <&vccio_sd>; -}; - -&sdmmc { - vqmmc-supply = <&vccio_sd>; - max-frequency = <150000000>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc_ext { - status = "disabled"; -}; - -&sdio_pwrseq { - status = "disabled"; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rockchip-key { - gpio_key1: gpio-key1 { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usb30_en_drv: usb30-en-drv { - rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev06.dts b/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev06.dts deleted file mode 100644 index 5de8b51..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev06.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - */ - -/dts-v1/; - -#include "rk3328-nanopi-r2-rev00.dts" - -/ { - model = "FriendlyElec NanoPi R2C"; - compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; -}; - -&mach { - hwrev = <6>; - model = "NanoPi R2C"; -}; - -&rgmiim1_pins { - rockchip,pins = - /* mac_txclk */ - <1 RK_PB4 2 &pcfg_pull_none_8ma>, - /* mac_rxclk */ - <1 RK_PB5 2 &pcfg_pull_none>, - /* mac_mdio */ - <1 RK_PC3 2 &pcfg_pull_none_2ma>, - /* mac_txen */ - <1 RK_PD1 2 &pcfg_pull_none_8ma>, - /* mac_clk */ - <1 RK_PC5 2 &pcfg_pull_none_2ma>, - /* mac_rxdv */ - <1 RK_PC6 2 &pcfg_pull_none>, - /* mac_mdc */ - <1 RK_PC7 2 &pcfg_pull_none_2ma>, - /* mac_rxd1 */ - <1 RK_PB2 2 &pcfg_pull_none>, - /* mac_rxd0 */ - <1 RK_PB3 2 &pcfg_pull_none>, - /* mac_txd1 */ - <1 RK_PB0 2 &pcfg_pull_none_8ma>, - /* mac_txd0 */ - <1 RK_PB1 2 &pcfg_pull_none_8ma>, - /* mac_rxd3 */ - <1 RK_PB6 2 &pcfg_pull_none>, - /* mac_rxd2 */ - <1 RK_PB7 2 &pcfg_pull_none>, - /* mac_txd3 */ - <1 RK_PC0 2 &pcfg_pull_none_8ma>, - /* mac_txd2 */ - <1 RK_PC1 2 &pcfg_pull_none_8ma>, - - /* mac_txclk */ - <0 RK_PB0 1 &pcfg_pull_none>, - /* mac_txen */ - <0 RK_PB4 1 &pcfg_pull_none>, - /* mac_clk */ - <0 RK_PD0 1 &pcfg_pull_none>, - /* mac_txd1 */ - <0 RK_PC0 1 &pcfg_pull_none>, - /* mac_txd0 */ - <0 RK_PC1 1 &pcfg_pull_none>, - /* mac_txd3 */ - <0 RK_PC7 1 &pcfg_pull_none>, - /* mac_txd2 */ - <0 RK_PC6 1 &pcfg_pull_none>; -}; - -/delete-node/ &rtl8211e; - -&gmac2io { - phy-handle = <ðphy3>; - snps,reset-delays-us = <0 15000 50000>; - tx_delay = <0x22>; - rx_delay = <0x12>; - mdio { - - ethphy3: ethernet-phy@3 { - compatible = "ethernet-phy-id0000.011a", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - interrupt-parent = <&gpio2>; - interrupts = ; - //reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - motorcomm,clk-out-frequency-hz = <125000000>; // enable gmac clock - motorcomm,keep-pll-enabled; // keep pll run without link - motorcomm,auto-sleep-disabled; // disable sleep without link - keep-clkout-on; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev20.dts b/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev20.dts deleted file mode 100644 index ad327ca..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2-rev20.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - */ - -/dts-v1/; -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "FriendlyElec NanoPi R2"; - compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; -}; - -&mach { - hwrev = <0x20>; - model = "NanoPi R2"; -}; - -&gmac2io { - pinctrl-0 = <&rgmiim1_pins>, <&phy_intb>, <&phy_rstb>; -}; - -&rtl8211e { - interrupt-parent = <&gpio1>; - interrupts = ; -}; - -&pinctrl { - phy { - phy_intb: phy-intb { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - phy_rstb: phy-rstb { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2s-plus-rev00.dts b/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2s-plus-rev00.dts deleted file mode 100644 index f660801..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3328-nanopi-r2s-plus-rev00.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2025 Ian Goodacre - */ - -/dts-v1/; -#include "rk3328-nanopi-r2s-plus.dts" - -/delete-node/ &rtl8211e; - -&gmac2io { - phy-handle = <&rtl8211f>; - snps,reset-delays-us = <0 15000 50000>; - tx_delay = <0x22>; - rx_delay = <0x12>; - - mdio { - rtl8211f: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - realtek,ledsel = <0xae00>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3328-z28pro.dts b/patch/kernel/rockchip64-6.14/dt/rk3328-z28pro.dts deleted file mode 100644 index 0b2e21a..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3328-z28pro.dts +++ /dev/null @@ -1 +0,0 @@ -#include "rk3328-rock64.dts" diff --git a/patch/kernel/rockchip64-6.14/dt/rk3399-am40.dts b/patch/kernel/rockchip64-6.14/dt/rk3399-am40.dts deleted file mode 100644 index a9f2938..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3399-am40.dts +++ /dev/null @@ -1,776 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2025 retro98boy - */ - -/dts-v1/; - -#include -#include -#include "rk3399.dtsi" - -/ { - model = "SMART AM40"; - compatible = "smart,am40", "rockchip,rk3399"; - - aliases { - ethernet0 = &gmac; - mmc0 = &sdhci; - mmc1 = &sdmmc; - rtc0 = &pt7c4563; - /* - * The rk808 circuit design on this board does not have the ability to maintain real-time time after a power outage. - * Registering rk808 as rtc99 (most kernel configurations read time from rtc0) can prevent the kernel from reading the time (2013) from rk808 during startup. - */ - rtc99 = &rk808; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_led>; - - pwr-led { - label = "pwr-led"; - gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_btn>; - - pwr-btn { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "pwr-btn"; - linux,code = ; - wakeup-source; - }; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <18000>; - }; - }; - - vcc1v8_s0: regulator-vcc1v8-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_sys: regulator-vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_phy: regulator-vcc-phy { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_phy_en>; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - vcc3v3_sys: regulator-vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; - - vcc5v0_host: regulator-vcc5v0-host { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc3v3_pcie: regulator-vcc3v3-pcie { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie_en>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - front_hdmi_5v: regulator-front-hdmi-5v { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&front_hdmi_5v_en>; - regulator-name = "front_hdmi_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_en>; - regulator-name = "otg_vbus"; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: regulator-vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - }; - - virtual_pd: virtual-pd { - compatible = "linux,extcon-usbc-virtual-pd"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - det-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; - vpd-data-role = "display-port"; - vpd-super-speed; - }; - - dp-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "dp-sound"; - - simple-audio-card,cpu { - // sound-dai = <&i2s2>; - sound-dai = <&spdif>; - }; - simple-audio-card,codec { - // sound-dai = <&cdn_dp 0>; - sound-dai = <&cdn_dp 1>; - }; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clock-parents = <&clkin_gmac>; - assigned-clocks = <&cru SCLK_RMII_SRC>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst_l>; - phy-handle = <&rtl8211f>; - phy-mode = "rgmii"; - phy-supply = <&vcc_phy>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211f: ethernet-phy@0 { - reg = <0>; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vcca0v9_hdmi>; - avdd-1v8-supply = <&vcca1v8_hdmi>; - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "disabled"; -}; - -&hdmi_sound { - status = "disabled"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_hdmi: LDO_REG2 { - regulator-name = "vcca1v8_hdmi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8: LDO_REG3 { - regulator-name = "vcca1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: LDO_REG4 { - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_sd: LDO_REG5 { - regulator-name = "vcc3v0_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_pin>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_pin>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c4 { - status = "okay"; - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <300>; - - pt7c4563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "rtc_xin32k"; - wakeup-source; - interrupt-parent = <&gpio0>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&rtc_int>; - pinctrl-names = "default"; - }; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - bt656-supply = <&vcc1v8_s0>; - audio-supply = <&vcc1v8_s0>; - sdmmc-supply = <&vcc_sd>; - gpio1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-0 = <&pcie_clkreqn>; - pinctrl-names = "default"; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pinctrl { - buttons { - pwr_btn: pwr-btn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - display { - dp_hpd: dp-hpd { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_input_pull_up>; - }; - - front_hdmi_5v_en: front-hdmi-5v-en { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_rst_l: phy-rst-l { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc_phy_en: vcc-phy-en { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - pwr_led: pwr-led { - rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_clkreqn: pci-clkreqn { - rockchip,pins = <2 RK_PD2 2 &pcfg_pull_none>; - }; - - vcc3v3_pcie_en: vcc3v3-pcie-en { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - rtc { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-hots-en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otg_vbus_en: otg-vbus-en { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_1v8>; - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8>; - status = "okay"; -}; - -&sdhci { - max-frequency = <150000000>; - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; - vqmmc-supply = <&vcc_sd>; - sd-uhs-sdr104; - status = "okay"; -}; - -&cdn_dp { - phys = <&tcphy0_dp>; - extcon = <&virtual_pd>; - status = "okay"; -}; - -&tcphy0 { - extcon = <&virtual_pd>; - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&vopl_out_dp { - status = "disabled"; -}; - -&dp_in_vopl { - status = "disabled"; -}; - -&vopb_out_hdmi { - status = "disabled"; -}; - -&hdmi_in_vopb { - status = "disabled"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3399-nanopi-m4v2.dts b/patch/kernel/rockchip64-6.14/dt/rk3399-nanopi-m4v2.dts deleted file mode 100644 index 094440c..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3399-nanopi-m4v2.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * FriendlyElec NanoPi M4V2 board device tree source - * - * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2018 Collabora Ltd. - * Copyright (c) 2019 Arm Ltd. - */ - -/dts-v1/; -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyElec NanoPi M4 Ver2.0"; - compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_core: vcc5v0-core { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_core"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v>; - }; - - vcc5v0_usb1: vcc5v0-usb1 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb1"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb2: vcc5v0-usb2 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb2"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-init-microvolt = <900000>; - vin-supply = <&vcc5v0_core>; - }; -}; - -&gmac { - rx_delay = <0x16>; -}; - -&rk808 { - max-buck-steps-per-change = <4>; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_core>; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_usb1>; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_usb2>; -}; - -&vbus_typec { - regulator-always-on; - vin-supply = <&vdd_5v>; -}; - diff --git a/patch/kernel/rockchip64-6.14/dt/rk3399-nanopi-r4se.dts b/patch/kernel/rockchip64-6.14/dt/rk3399-nanopi-r4se.dts deleted file mode 100644 index eaeeadc..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3399-nanopi-r4se.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include "rk3399-nanopi-r4s.dts" - -/ { - model = "FriendlyElec NanoPi R4SE"; - compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399"; -}; - -&emmc_phy { - status = "okay"; -}; - -&sdhci { - status = "okay"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3399-orangepi-4-lts.dts b/patch/kernel/rockchip64-6.14/dt/rk3399-orangepi-4-lts.dts deleted file mode 100644 index c799404..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3399-orangepi-4-lts.dts +++ /dev/null @@ -1,1333 +0,0 @@ -/* - * SPDX-License-Identifier: (GPL-2.0+ or MIT) - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2018 Akash Gajjar - * Copyright (c) 2020-2022 Armbian (chwe17, piter75, jock) - * - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "rk3399.dtsi" - -/ { - model = "OrangePi 4 LTS"; - compatible = "xunlong,orangepi-4-lts", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - aliases { - spi1 = &spi1; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - usb_vbus: usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3_vbus"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vbus_typec: vbus-typec { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vbus-5v"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* 0.9 V supply, over PMIC - vcc_0v9: vcc-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - } - */ - - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc3v0_sd"; - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_drv>; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc3v3_pcie"; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - }; - - es8316c_card: es8316c-card { - compatible = "simple-audio-card"; - - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip-es8316c"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphones"; - - simple-audio-card,routing = - "MIC1", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR"; - - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - - simple-audio-card,codec { - sound-dai = <&es8316c_codec>; - }; - - }; - - hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "hdmi-sound"; - status = "okay"; - - simple-audio-card,cpu { - sound-dai = <&i2s2>; - }; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - spdif-sound { - status = "disable"; - compatible = "simple-audio-card"; - simple-audio-card,name = "ROCKCHIP,SPDIF"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - status = "disable"; - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - pwm_bl: backlight { - status = "disable"; - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&power_key>; - - button@0 { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - poll-interval = <100>; - keyup-threshold-microvolt = <1800000>; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <100000>; - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <300000>; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 =<&leds_gpio>; - - led@1 { - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - label = "status_led"; - linux,default-trigger = "heartbeat"; - linux,default-trigger-delay-ms = <0>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ - }; - - unisoc_uwe_bsp: uwe-bsp { - compatible = "unisoc,uwe_bsp"; - //wl-reg-on = <&gpio0 10 GPIO_ACTIVE_HIGH>; // handled by sdio-pwrseq - bt-reg-on = <&gpio0 9 GPIO_ACTIVE_HIGH>; - wl-wake-host-gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; - bt-wake-host-gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - sdio-ext-int-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - unisoc,btwf-file-name = "/lib/firmware/uwe5622/wcnmodem-38222.bin"; - data-irq; - blksz-512; - keep-power-on; - status = "okay"; - }; - - sprd-wlan { - compatible = "sprd,uwe5622-wifi"; - status = "okay"; - }; - - sprd-mtty { - compatible = "sprd,mtty"; - sprd,name = "ttyBT"; - status = "okay"; - }; - - dmc_opp_table: dmc_opp_table { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <328000000>; - opp-microvolt = <900000>; - }; - - opp01 { - opp-hz = /bits/ 64 <416000000>; - opp-microvolt = <900000>; - }; - - opp02 { - opp-hz = /bits/ 64 <666000000>; - opp-microvolt = <900000>; - }; - - }; - -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&gpu { - status = "okay"; - mali-supply = <&vdd_gpu>; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rstb>; - phy-mode = "rgmii"; - phy-supply = <&vcc3v3_s3>; - phy-handle = <&yt8531c>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - yt8531c: ethernet-phy@0 { - compatible = "ethernet-phy-id4f51.e91b", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&phy_intb>; - motorcomm,clk-out-frequency-hz = <125000000>; - motorcomm,keep-pll-enabled; - motorcomm,auto-sleep-disabled; - interrupt-parent = <&gpio3>; - interrupts = ; - }; - }; - -}; - -&spi1 { - status = "disable"; - pinctrl-names = "default", "sleep"; - pinctrl-1 = <&spi1_gpio>; - - spidev0: spidev@0 { - compatible = "rockchip,spidev"; - reg = <0>; - spi-max-frequency = <10000000>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&vpu { - status = "okay"; -}; - -&rga { - status = "okay"; -}; - -&cdn_dp { - status = "okay"; - extcon = <&fusb0>; - phys = <&tcphy0_dp>; -}; - -&hdmi { - /* remove the hdmi_i2c_xfer */ - pinctrl-0 = <&hdmi_cec>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - status = "okay"; - ddc-i2c-bus = <&i2c7>; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio2>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vcc13-supply = <&vcc3v3_sys>; - vcc14-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc1v8: vcc1v8_s3: vcca1v8_s3: DCDC_REG4 { - regulator-name = "vcc1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_touch: LDO_REG2 { - regulator-name = "vcc3v0_touch"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-init-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - regulator-compatible = "fan53555-reg"; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - regulator-compatible = "fan53555-reg"; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - clock-frequency = <200000>; - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - es8316c_codec: es8316c@11 { - #sound-dai-cells = <0>; - compatible = "everest,es8316"; - reg = <17>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - //pinctrl-names = "default"; - //pinctrl-0 = <&i2s_8ch_mclk>; - status = "okay"; - }; - -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - clock-frequency = <400000>; - - fusb0: fusb30x@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - interrupt-parent = <&gpio1>; - interrupts = ; - vbus-supply = <&vbus_typec>; - status = "okay"; - - connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - sink-pdos = - ; - source-pdos = - ; - try-power-role = "sink"; - - extcon-cables = <1 2 5 6 9 10 12 44>; - typec-altmodes = <0xff01 1 0x001c0000 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usbc_hs: endpoint { - remote-endpoint = - <&u2phy0_typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usbc_ss: endpoint { - remote-endpoint = - <&tcphy0_typec_ss>; - }; - }; - - port@2 { - reg = <2>; - - usbc_dp: endpoint { - remote-endpoint = - <&tcphy0_typec_dp>; - }; - }; - }; - }; - - }; - - ft5x06_ts@38 { - compatible = "edt,edt-ft5x06", "ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - -}; - -&i2c7 { - status = "okay"; -}; - -&spdif { - status = "disable"; - pinctrl-0 = <&spdif_bus>; - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - #sound-dai-cells = <0>; -}; - -&i2s0 { - rockchip,i2s-broken-burst-len; - assigned-clocks = <&cru SCLK_I2SOUT_SRC>; - assigned-clock-parents = <&cru SCLK_I2S0_8CH>; - resets = <&cru SRST_I2S0_8CH>, <&cru SRST_H_I2S0_8CH>; - reset-names = "reset-m", "reset-h"; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; - #sound-dai-cells = <0>; -}; - -&i2s2 { - #sound-dai-cells = <0>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */ - audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ - sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ - gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_3v0>; -}; - -&pcie_phy { - status = "okay"; - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; -}; - -&pcie0 { - status = "okay"; - ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - max-link-speed = <1>; -}; - -&pwm_bl { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin_pull_down>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcca1v8_s3>; /* TBD */ -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - supports-emmc; - non-removable; - keep-power-in-suspend; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&emmc_phy { - status = "okay"; -}; - -&sdio0 { - clock-frequency = <150000000>; - max-frequency = <150000000>; - supports-sdio; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - cd-debounce-delay-ms = <500>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&tcphy0 { - extcon = <&fusb0>; - status = "okay"; -}; - -&tcphy0_dp { - port { - tcphy0_typec_dp: endpoint { - remote-endpoint = <&usbc_dp>; - }; - }; -}; - -&tcphy0_usb3 { - port { - tcphy0_typec_ss: endpoint { - remote-endpoint = <&usbc_ss>; - }; - }; -}; - -&tcphy1 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&usb3_vbus>; - status = "okay"; - }; - - port { - u2phy0_typec_hs: endpoint { - remote-endpoint = <&usbc_hs>; - }; - }; - -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&usb_vbus>; - status = "okay"; - }; -}; - -&usbdrd3_0 { - status = "okay"; - extcon = <&fusb0>; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&sdmmc_bus4 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_up_12ma>, - <4 RK_PB1 1 &pcfg_pull_up_12ma>, - <4 RK_PB2 1 &pcfg_pull_up_12ma>, - <4 RK_PB3 1 &pcfg_pull_up_12ma>; -}; - -&sdmmc_cmd { - rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_up_12ma>; -}; - -&pinctrl { - - pcfg_pull_up_12ma: pcfg-pull-up-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - pcie { - pcie_drv: pcie-drv { - rockchip,pins = - <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - /delete-node/ hdmi-i2c-xfer; - }; - - i2s0 { - i2s_8ch_mclk: i2s-8ch-mclk { - rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0_typec_en { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart0_gpios: uart0-gpios { - rockchip,pins = <2 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rockchip-key { - power_key: power-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gpio-leds { - leds_gpio: leds-gpio { - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - cam_pins { - cif_clkout_a: cif-clkout-a { - rockchip,pins = <2 11 3 &pcfg_pull_none>; - }; - - cif_clkout_a_sleep: cif-clkout-a-sleep { - rockchip,pins = <2 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - cam0_default_pins: cam0-default-pins { - rockchip,pins = - <4 27 0 &pcfg_pull_down>, - <2 11 3 &pcfg_pull_none>; - }; - - cam0_sleep_pins: cam0-sleep-pins { - rockchip,pins = - <4 27 3 &pcfg_pull_none>, - <2 11 0 &pcfg_pull_none>; - }; - - cam1_default_pins: cam1-default-pins { - rockchip,pins = - <0 12 RK_FUNC_GPIO &pcfg_pull_down>, - <0 8 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - spi1 { - spi1_gpio: spi1-gpio { - rockchip,pins = - <1 7 RK_FUNC_GPIO &pcfg_output_low>, - <1 8 RK_FUNC_GPIO &pcfg_output_low>, - <1 9 RK_FUNC_GPIO &pcfg_output_low>, - <1 10 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - bt { - bt_host_wake: bt-host-wake { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset: bt-reset { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake: bt-wake { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_intb: phy-intb { - rockchip,pins = <3 RK_PB2 1 &pcfg_pull_up>; - }; - - phy_rstb: phy-rstb { - rockchip,pins = <3 RK_PB7 1 &pcfg_pull_none>; - }; - }; - -}; - -&hdmi_in_vopb { - status = "okay"; -}; - -&hdmi_in_vopl { - status = "disable"; -}; - -&dp_in_vopb { - status = "disable"; -}; -&dp_in_vopl { - status = "okay"; -}; - -&dmc { - #cooling-cells = <2>; /* min followed by max */ - - status = "disabled"; - center-supply = <&vdd_log>; - operating-points-v2 = <&dmc_opp_table>; - - rockchip,pd-idle-ns = <160>; - rockchip,sr-idle-ns = <10240>; - rockchip,sr-mc-gate-idle-ns = <40960>; - rockchip,srpd-lite-idle-ns = <61440>; - rockchip,standby-idle-ns = <81920>; - - rockchip,ddr3_odt_dis_freq = <666000000>; - rockchip,lpddr3_odt_dis_freq = <666000000>; - rockchip,lpddr4_odt_dis_freq = <666000000>; - - rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>; - rockchip,srpd-lite-idle-dis-freq-hz = <0>; - rockchip,standby-idle-dis-freq-hz = <928000000>; - -}; - -&dfi { - status = "okay"; -}; - -/* - * Redefine some parameters for the thermal trip points for Opi4 LTS. - * First of all, the Soc does not like getting over 90°C. My sample - * froze at 94.4°C, so we lower the critical temprature to 90°C, hopefully - * giving enough room for safe reboot of the device. - * Big cores are getting throttled a bit when reaching 82°C, then at 85°C - * we aggressively throttle all the cores and even the memory controller. - * The GPU is handled by existing trip points in the base device tree, here - * we just set the same critical temperature as CPU. - */ -&cpu_alert0 { - temperature = <82000>; -}; - -&cpu_alert1 { - temperature = <85000>; -}; - -&cpu_crit { - temperatue = <90000>; -}; - -&gpu_crit { - temperatue = <90000>; -}; - -&cpu_thermal { - - cooling-maps { - - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT 3>, - <&cpu_b1 THERMAL_NO_LIMIT 3>; - }; - - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map2 { - trip = <&cpu_alert1>; - cooling-device = - <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - }; - -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3399-orangepi-4.dts b/patch/kernel/rockchip64-6.14/dt/rk3399-orangepi-4.dts deleted file mode 100644 index 3d85bd0..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3399-orangepi-4.dts +++ /dev/null @@ -1,1193 +0,0 @@ -/* - * SPDX-License-Identifier: (GPL-2.0+ or MIT) - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2018 Akash Gajjar - * Copyright (c) 2020 Armbian (chwe17, piter75) - * - */ - -/dts-v1/; -#include -#include -#include -//#include -#include "rk3399.dtsi" - -/ { - model = "OrangePi 4"; - compatible = "xunlong,orangepi-4", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - aliases { - spi1 = &spi1; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - usb_vbus: usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3_vbus"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vbus_typec: vbus-typec { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vbus_typec"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* 0.9 V supply, over PMIC - vcc_0v9: vcc-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - } - */ - - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_pwr_h>; - regulator-name = "vcc3v0_sd"; - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_drv>; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc3v3_pcie"; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - }; - - rt5651_card: rt5651-sound { - status = "okay"; - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - - simple-audio-card,name = "realtek,rt5651-codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; - - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Mic Jack", "micbias1", - "IN2P", "Mic Jack", - "IN3P", "Mic Jack", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - simple-audio-card,codec { - sound-dai = <&rt5651>; - }; - }; - - dw_hdmi_audio: dw-hdmi-audio { - status = "disable"; - compatible = "rockchip,dw-hdmi-audio"; - #sound-dai-cells = <0>; - }; - - hdmi_sound: hdmi-sound { - status = "okay"; - }; - - hdmi_dp_sound: hdmi-dp-sound { - status = "okay"; - compatible = "rockchip,rk3399-hdmi-dp"; - rockchip,cpu = <&i2s2>; - rockchip,codec = <&hdmi>, <&cdn_dp>; - }; - - spdif-sound { - status = "disable"; - compatible = "simple-audio-card"; - simple-audio-card,name = "ROCKCHIP,SPDIF"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - status = "disable"; - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - pwm_bl: backlight { - status = "disable"; - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&power_key>; - - button@0 { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - poll-interval = <100>; - keyup-threshold-microvolt = <1800000>; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <100000>; - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <300000>; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 =<&leds_gpio>; - - led@1 { - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - label = "status_led"; - linux,default-trigger = "heartbeat"; - linux,default-trigger-delay-ms = <0>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&gpu { - status = "okay"; - mali-supply = <&vdd_gpu>; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-supply = <&vcc3v3_s3>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&spi1 { - status = "disable"; - pinctrl-names = "default", "sleep"; - pinctrl-1 = <&spi1_gpio>; - - spidev0: spidev@0 { - compatible = "rockchip,spidev"; - reg = <0>; - spi-max-frequency = <10000000>; - status = "okay"; - }; -}; -/* -&spi1 { - status = "okay"; - max-freq = <48000000>; - spidev@00 { - compatible = "linux,spidev"; - reg = <0x00>; - spi-max-frequency = <48000000>; - }; -}; -*/ - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - max-speed = <1500000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake &bt_wake &bt_reset>; - }; - -}; - -&uart2 { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&vpu { - status = "okay"; - /* 0 means ion, 1 means drm */ - //allocator = <0>; -}; - -&rga { - status = "disabled"; -}; - -&cdn_dp { - status = "okay"; - extcon = <&fusb0>; - phys = <&tcphy0_dp>; -}; - -&hdmi { - /* remove the hdmi_i2c_xfer */ - pinctrl-0 = <&hdmi_cec>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - status = "okay"; - ddc-i2c-bus = <&i2c7>; - rockchip,defaultmode = <16>; /* CEA 1920x1080@60Hz */ -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vcc13-supply = <&vcc3v3_sys>; - vcc14-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc1v8: vcc1v8_s3: vcca1v8_s3: DCDC_REG4 { - regulator-name = "vcc1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_touch: LDO_REG2 { - regulator-name = "vcc3v0_touch"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-init-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - regulator-compatible = "fan53555-reg"; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - regulator-compatible = "fan53555-reg"; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - status = "okay"; - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - clock-frequency = <200000>; - - rt5651: rt5651@1a { - #sound-dai-cells = <0>; - compatible = "realtek,rt5651"; - reg = <0x1a>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - status = "okay"; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - clock-frequency = <400000>; - - fusb0: fusb30x@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - interrupt-parent = <&gpio1>; - interrupts = ; - vbus-supply = <&vbus_typec>; - status = "okay"; - - connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - sink-pdos = - ; - source-pdos = - ; - try-power-role = "sink"; - - extcon-cables = <1 2 5 6 9 10 12 44>; - typec-altmodes = <0xff01 1 0x001c0000 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usbc_hs: endpoint { - remote-endpoint = - <&u2phy0_typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usbc_ss: endpoint { - remote-endpoint = - <&tcphy0_typec_ss>; - }; - }; - - port@2 { - reg = <2>; - - usbc_dp: endpoint { - remote-endpoint = - <&tcphy0_typec_dp>; - }; - }; - }; - }; - - }; - - ft5x06_ts@38 { - compatible = "edt,edt-ft5x06", "ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - - /* - onewire_ts@2f { - compatible = "onewire"; - reg = <0x2f>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - }; */ -}; - -&i2c7 { - status = "okay"; -}; - -&spdif { - status = "disable"; - pinctrl-0 = <&spdif_bus>; - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - #sound-dai-cells = <0>; -}; - -&i2s1 { - assigned-clocks = <&cru SCLK_I2SOUT_SRC>; - assigned-clock-parents = <&cru SCLK_I2S1_8CH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s_8ch_mclk>,<&i2s1_2ch_bus>; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "okay"; -}; -/* -&i2s0 { - assigned-clocks = <&cru SCLK_I2S1_DIV>; - assigned-clock-parents = <&cru PLL_GPLL>; -};*/ - -&i2s2 { - #sound-dai-cells = <0>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */ - audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ - sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ - gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_3v0>; -}; - -&pcie_phy { - status = "okay"; - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; -}; - -&pcie0 { - status = "okay"; - ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - max-link-speed = <1>; -}; - -&pwm_bl { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin_pull_down>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcca1v8_s3>; /* TBD */ -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - supports-emmc; - non-removable; - keep-power-in-suspend; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&emmc_phy { - status = "okay"; -}; - -&sdio0 { - clock-frequency = <50000000>; - clock-freq-min-max = <200000 50000000>; - supports-sdio; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; -// sd-uhs-sdr104; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&tcphy0 { - extcon = <&fusb0>; - status = "okay"; -}; - -&tcphy0_dp { - port { - tcphy0_typec_dp: endpoint { - remote-endpoint = <&usbc_dp>; - }; - }; -}; - -&tcphy0_usb3 { - port { - tcphy0_typec_ss: endpoint { - remote-endpoint = <&usbc_ss>; - }; - }; -}; - -&tcphy1 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&usb3_vbus>; - status = "okay"; - }; - - port { - u2phy0_typec_hs: endpoint { - remote-endpoint = <&usbc_hs>; - }; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&usb_vbus>; - status = "okay"; - }; -}; - -&usbdrd3_0 { - status = "okay"; - extcon = <&fusb0>; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&pinctrl { - pcie { - pcie_drv: pcie-drv { - rockchip,pins = - <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - /delete-node/ hdmi-i2c-xfer; - }; - - i2s1 { - i2s_8ch_mclk: i2s-8ch-mclk { - rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdmmc { - sdmmc0_det_l: sdmmc0-det-l { - rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - sdmmc0_pwr_h: sdmmc0-pwr-h { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0_typec_en { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart0_gpios: uart0-gpios { - rockchip,pins = <2 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rockchip-key { - power_key: power-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gpio-leds { - leds_gpio: leds-gpio { - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - cam_pins { - cif_clkout_a: cif-clkout-a { - rockchip,pins = <2 11 3 &pcfg_pull_none>; - }; - - cif_clkout_a_sleep: cif-clkout-a-sleep { - rockchip,pins = <2 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - cam0_default_pins: cam0-default-pins { - rockchip,pins = - <4 27 0 &pcfg_pull_down>, - <2 11 3 &pcfg_pull_none>; - }; - cam0_sleep_pins: cam0-sleep-pins { - rockchip,pins = - <4 27 3 &pcfg_pull_none>, - <2 11 0 &pcfg_pull_none>; - }; - - cam1_default_pins: cam1-default-pins { - rockchip,pins = - <0 12 RK_FUNC_GPIO &pcfg_pull_down>, - <0 8 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - spi1 { - spi1_gpio: spi1-gpio { - rockchip,pins = - <1 7 RK_FUNC_GPIO &pcfg_output_low>, - <1 8 RK_FUNC_GPIO &pcfg_output_low>, - <1 9 RK_FUNC_GPIO &pcfg_output_low>, - <1 10 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - bt { - bt_host_wake: bt-host-wake { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset: bt-reset { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake: bt-wake { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - -}; - -&hdmi_in_vopb { - status = "okay"; -}; - -&hdmi_in_vopl { - status = "disable"; -}; - -&dp_in_vopb { - status = "disable"; -}; -&dp_in_vopl { - status = "okay"; -}; - diff --git a/patch/kernel/rockchip64-6.14/dt/rk3399-rock-pi-4.dts b/patch/kernel/rockchip64-6.14/dt/rk3399-rock-pi-4.dts deleted file mode 100644 index 8d0aa53..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3399-rock-pi-4.dts +++ /dev/null @@ -1 +0,0 @@ -#include "rk3399-rock-pi-4b.dts" diff --git a/patch/kernel/rockchip64-6.14/dt/rk3399-tinker-2.dts b/patch/kernel/rockchip64-6.14/dt/rk3399-tinker-2.dts deleted file mode 100644 index e929de3..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3399-tinker-2.dts +++ /dev/null @@ -1,751 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2021 Thomas McKahan - */ - -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-op1.dtsi" - -/ { - model = "Asus Tinker Board 2/2S"; - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - board_info: board-info { - compatible = "board-info"; - - hw-id0 = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - hw-id1 = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - hw-id2 = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - - pid-id0 = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; - pid-id1 = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; - pid-id2 = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; - - ddr-id1 = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - ddr-id2 = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - - pmic-reset = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - pwr-led { - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - retain-state-suspended = <1>; - }; - - act-led { - gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - linux,default-trigger="mmc0"; - }; - - rsv-led { - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; - linux,default-trigger="heartbeat"; - }; - }; - - vcc_lcd: vcc-lcd { - compatible = "regulator-fixed"; - regulator-name = "vcc_lcd"; - gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; - startup-delay-us = <20000>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - vbus_typec: vbus-5vout { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec0_en_pin>; - regulator-name = "vbus_5vout"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - - /* for rockchip boot on */ - rockchip,pwm_id= <2>; - rockchip,pwm_voltage = <900000>; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; -}; - -&cdn_dp { - status = "okay"; - extcon = <&fusb0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&cru SCLK_MAC>; - clock_in_out = "input"; - assigned-clock-rates = <125000000>; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 16000 72000>; - tx_delay = <0x25>; - rx_delay = <0x20>; - wakeup-enable = "0"; - status = "okay"; -}; -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc1v8_pmu>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc3v3_dsi: LDO_REG1 { - regulator-name = "vcc3v3_dsi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_hdmi: LDO_REG2 { - regulator-name = "vcca1v8_hdmi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG4 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_csi: LDO_REG5 { - regulator-name = "vcc3v3_csi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: vdd_cpu_b@60 { - compatible = "fcs,fan53200"; - reg = <0x60>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "fan53555-regulator"; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <1000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - - regulator-initial-state = <3>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - - status = "okay"; - i2c-scl-rising-time-ns = <475>; - i2c-scl-falling-time-ns = <26>; - fusb0: fusb30x@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - interrupt-parent = <&gpio1>; - interrupts = ; - vbus-supply = <&vbus_typec>; - status = "okay"; - - connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - sink-pdos = - ; - source-pdos = - ; - try-power-role = "sink"; - - extcon-cables = <1 2 5 6 9 10 12 44>; - typec-altmodes = <0xff01 1 0x001c0000 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usbc_hs: endpoint { - remote-endpoint = - <&u2phy0_typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usbc_ss: endpoint { - remote-endpoint = - <&tcphy0_typec_ss>; - }; - }; - - port@2 { - reg = <2>; - - usbc_dp: endpoint { - remote-endpoint = - <&tcphy0_typec_dp>; - }; - }; - }; - }; - - - - - }; - - vdd_gpu: vdd_gpu@60 { - compatible = "fcs,fan53200"; - reg = <0x60>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "fan53555-regulator"; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <1000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - - regulator-initial-state = <3>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c8 { - - m24c08: m24c08@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; - -&pwm0 { - status = "disabled"; -}; - -&pwm2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin_pull_down>; -}; - -&pwm3 { - status = "disabled"; -}; - -&saradc { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - supports-emmc; - //mmc-hs400-enhanced-strobe; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&sdmmc { - clock-frequency = <150000000>; - clock-freq-min-max = <100000 150000000>; - supports-sd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - num-slots = <1>; - //sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_s3>; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&tcphy0 { - extcon = <&fusb0>; - status = "okay"; -}; - -&tcphy0_dp { - port { - tcphy0_typec_dp: endpoint { - remote-endpoint = <&usbc_dp>; - }; - }; -}; - -&tcphy0_usb3 { - port { - tcphy0_typec_ss: endpoint { - remote-endpoint = <&usbc_ss>; - }; - }; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; - - port { - u2phy0_typec_hs: endpoint { - remote-endpoint = <&usbc_hs>; - }; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&pinctrl { - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 18 RK_FUNC_GPIO &pcfg_pull_up>, - <0 9 RK_FUNC_GPIO &pcfg_pull_none>; /* GPIO0_B1 */ - }; - vsel1_gpio: vsel1-gpio { - rockchip,pins = - <1 17 RK_FUNC_GPIO &pcfg_pull_down>; - }; - vsel2_gpio: vsel2-gpio { - rockchip,pins = - <1 14 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = - <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3399-xiaobao-nas.dts b/patch/kernel/rockchip64-6.14/dt/rk3399-xiaobao-nas.dts deleted file mode 100644 index 4f6ca79..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3399-xiaobao-nas.dts +++ /dev/null @@ -1,773 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include -#include -#include -#include "rk3399.dtsi" - -/ { - model = "Codinge Xiaobao NAS"; - compatible = "codinge,xiaobao-nas", "rockchip,rk3399"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &sdhci; - mmc2 = &sdio0; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - vcc_dc: vcc-dc { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_12v: vcc-12v { - compatible = "regulator-fixed"; - regulator-name = "vcc_12v"; - regulator-always-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - }; - - vcc_sd: vcc-sd { - compatible = "regulator-fixed"; - regulator-name = "vcc_sd"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_sd_h>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc5v0_typec: vcc5v0-typec { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_12v>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - enable-active-high; - gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr_en>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc_lan: vcc3v3-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_lan"; - regulator-always-on; - regulator-boot-on; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - recovery { - label = "Recovery"; - linux,code = <0x168>; - press-threshold-microvolt = <18000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - led1: system-led1 { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "system_led1"; - retain-state-suspended; - default-state = "on"; - }; - - led2: system-led2 { - gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; - label = "system_led2"; - retain-state-suspended; - default-state = "off"; - }; - }; - - pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm1 0 50000 0>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - ddc-i2c-scl-high-time-ns = <9625>; - ddc-i2c-scl-low-time-ns = <10000>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_1v8: LDO_REG2 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_pmupll: LDO_REG3 { - regulator-name = "vcc1v8_pmupll"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_pin>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_pin>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; - - typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc5v0_typec>; - }; -}; - -&i2s0 { - rockchip,capture-channels = <8>; - rockchip,playback-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,capture-channels = <2>; - rockchip,playback-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc_3v0>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pcie_phy { - status = "okay"; - drive-impedance-ohm = <50>; -}; - -&pcie0 { - ep-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqnb_cpm &fn8274_en_h>; - status = "okay"; -}; - -&pmu_io_domains { - status = "okay"; - - pmu1830-supply = <&vcc_3v0>; -}; - -&pinctrl { - pcie { - fn8274_en_h: fn8274-en-h { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>, - <4 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>, - <1 RK_PC7 RK_FUNC_GPIO &pcfg_output_high>; - }; - - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_typec_en: vcc5v0-typec-en { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - vcc_sd { - vcc_sd_h: vcc-sd-h { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - leds_pins: leds-pins { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&spi1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x00>; - spi-max-frequency = <10000000>; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - status = "okay"; - - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3566-h96-tvbox.dts b/patch/kernel/rockchip64-6.14/dt/rk3566-h96-tvbox.dts deleted file mode 100644 index 305bb5f..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3566-h96-tvbox.dts +++ /dev/null @@ -1,796 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2024 hqnicolas - */ - -/dts-v1/; - -#include -#include -#include -#include -#include "rk3566.dtsi" - -/ { - model = "h96 TVbox 3566"; - compatible = "h96-TVbox,rk3566", "rockchip,rk3566"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - mmc2 = &sdmmc1; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - vcc5v0_in: vcc5v0_in { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_in"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_receiver_pin>; - linux,rc-map-name = "rc-h96-max-v56"; - }; - - fddis_dev { - compatible = "fddis_dev"; - fddis_gpio_clk = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - fddis_gpio_dat = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&dis_ctl_clk &dis_ctl_dat>; - status = "okay"; - }; - - spdif_dit: spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif_sound: spdif-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_dit>; - }; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0_sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_in>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_otg: vcc5v0-otg-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_enable_h>; - regulator-name = "vcc3v3_pcie_p"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3>; - }; - - leds { - compatible = "gpio-leds"; - - led_status: led-status { - label = "led-status"; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_status_enable_h>; - }; - - led_power: led-power { - label = "led-power"; - gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&led_power_enable_h>; - }; - }; - - vbus: vbus-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbus"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sdio_pwrseq: sdio-pwrseq { - status = "okay"; - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <100>; - }; - - rk809_sound: rk809-sound { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,rk809-codec"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - simple-audio-card,codec { - sound-dai = <&rk809_codec>; - }; - }; - - rk_headset: rk-headset { - compatible = "rockchip_headset"; - headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - io-channels = <&saradc 2>; //HP_HOOK pin - }; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_3v3>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m0_miim - &gmac1m0_tx_bus2 - &gmac1m0_rx_bus2 - &gmac1m0_rgmii_clk - &gmac1m0_clkinout - &gmac1m0_rgmii_bus>; - snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ - snps,reset-delays-us = <0 20000 100000>; - tx_delay = <0x41>; - rx_delay = <0x2e>; - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&hdmi { - assigned-clocks = <&cru CLK_HDMI_CEC>; - assigned-clock-rates = <32768>; - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - #sound-dai-cells = <0>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_npu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_image"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda_0v9"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_acodec"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - rk809_codec: codec { - mic-in-differential; - }; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx - &i2s1m0_lrcktx - &i2s1m0_sdi0 - &i2s1m0_sdo0>; - rockchip,trcm-sync-tx-only; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - status = "okay"; - }; -}; - -&pcie2x1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie_p>; - status = "disabled"; -}; - -&pinctrl { - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_otg_en: vcc5v0-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_enable_h: pcie-enable-h { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_reset_h: pcie-reset-h { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ir-receiver { - ir_receiver_pin: ir-receiver-pin { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led_status_enable_h: led-status-enable-h { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_power_enable_h: led_power_enable_h { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fddis_ctr { - dis_ctl_clk: dis-ctl-clk { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - dis_ctl_dat: dis-ctl-dat { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sata2 { - status = "disabled"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc1 { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - sd-uhs-sdr50; - supports-sdio; - status = "okay"; - vmmc-supply = <&vcc3v3_sys>; - vqmmc-supply = <&vcca1v8_pmu>; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio2>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - }; -}; - -&tsadc { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; - status = "okay"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - max-speed = <3000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcca1v8_pmu>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - status = "okay"; -}; - -&usb2phy0_otg { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - status = "okay"; -}; - -&usb2phy1_otg { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vpu { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3566-jp-tvbox.dts b/patch/kernel/rockchip64-6.14/dt/rk3566-jp-tvbox.dts deleted file mode 100644 index f1b7d33..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3566-jp-tvbox.dts +++ /dev/null @@ -1,579 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 tdleiyao - */ - -/dts-v1/; - -#include -#include -#include -#include -#include "rk3566.dtsi" - -/ { - model = "JP TVbox 3566"; - compatible = "JP-TVbox,rk3566", "rockchip,rk3566"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc1; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - - led_status: led-status { - label = "led-status"; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_status_enable_h>; - }; - }; - - vbus: vbus-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbus"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vbus>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - sdio_pwrseq: sdio-pwrseq { - status = "okay"; - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <100>; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - rockchip,grf = <&grf>; - wifi_chip_type = "ap6398s"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_3v3>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m0_miim - &gmac1m0_tx_bus2 - &gmac1m0_rx_bus2 - &gmac1m0_rgmii_clk - &gmac1m0_clkinout - &gmac1m0_rgmii_bus>; - snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ - snps,reset-delays-us = <0 20000 100000>; - tx_delay = <0x41>; - rx_delay = <0x2e>; - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - status = "okay"; - }; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_npu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_image"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda_0v9"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_acodec"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca_1v8"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_image"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - }; - }; -}; - -&pinctrl { - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led_status_enable_h: led-status-enable-h { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc1 { - supports-sdio; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - non-removable; - mmc-pwrseq = <&sdio_pwrseq>; - status = "okay"; - -}; - -&tsadc { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - max-speed = <1500000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcca1v8_pmu>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - status = "okay"; -}; - -&usb2phy0_otg { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - status = "okay"; -}; - -&usb2phy1_otg { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3566-panther-x2.dts b/patch/kernel/rockchip64-6.14/dt/rk3566-panther-x2.dts deleted file mode 100644 index dc9f914..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3566-panther-x2.dts +++ /dev/null @@ -1,579 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 tdleiyao - */ - -/dts-v1/; - -#include -#include -#include -#include "rk3566.dtsi" - -/ { - model = "Panther X2"; - compatible = "panther,x2", "rockchip,rk3566"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - mmc2 = &sdmmc1; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - //Corresponds to the actual order - led_pwr: led-pwr { - label = "led-pwr"; - default-state = "on"; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&led_pwr_enable_h>; - retain-state-suspended; - status = "okay"; - }; - - led_wifi: led-wifi { - label = "led-wifi"; - default-state = "off"; - gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&led_wifi_enable_h>; - retain-state-suspended; - status = "okay"; - }; - - led_eth: led-eth { - label = "led-eth"; - default-state = "off"; - gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&led_eth_enable_h>; - retain-state-suspended; - status = "okay"; - }; - - led_status: led-status { - label = "led-status"; - default-state = "on"; - gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_status_enable_h>; - retain-state-suspended; - status = "okay"; - }; - }; - - vbus: vbus-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbus"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vbus>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - sdio_pwrseq: sdio-pwrseq { - status = "okay"; - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <100>; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - rockchip,grf = <&grf>; - wifi_chip_type = "ap6236"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_3v3>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m0_miim - &gmac1m0_tx_bus2 - &gmac1m0_rx_bus2 - &gmac1m0_rgmii_clk - &gmac1m0_clkinout - &gmac1m0_rgmii_bus>; - snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ - snps,reset-delays-us = <0 20000 100000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - status = "okay"; - }; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_npu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_image"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda_0v9"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_acodec"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca_1v8"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_pmu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_image"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - status = "disabled"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - }; - }; -}; - -&i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx - &i2s1m1_lrcktx &i2s1m1_lrckrx - &i2s1m1_sdi0 &i2s1m1_sdi1 - &i2s1m1_sdi2 &i2s1m1_sdi3 - &i2s1m1_sdo0 &i2s1m1_sdo1 - &i2s1m1_sdo2 &i2s1m1_sdo3>; - status = "disabled"; -}; - -&pinctrl { - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led_pwr_enable_h: led-pwr-enable-h { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_wifi_enable_h: led-wifi-enable-h { - rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_eth_enable_h: led-eth-enable-h { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_status_enable_h: led-status-enable-h { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vcc_3v3>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_3v3>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - broken-cd; - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc1 { - supports-sdio; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - non-removable; - mmc-pwrseq = <&sdio_pwrseq>; - status = "okay"; - -}; - -&tsadc { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - max-speed = <1500000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcca1v8_pmu>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - status = "okay"; -}; - -&usb2phy0_otg { - status = "okay"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-h66k.dts b/patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-h66k.dts deleted file mode 100644 index f51e626..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-h66k.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2022 AmadeusGhost -// Copyright (c) 2022 Flippy -// Copyright (c) 2023 amazingfate - -/dts-v1/; - -#include "rk3568-hinlink-h68k.dts" - -/ { - model = "HINLINK H66K"; - compatible = "hinlink,h66k", "rockchip,rk3568"; -}; - -&gmac0 { - status = "disabled"; -}; - -&gmac1 { - status = "disabled"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-h68k.dts b/patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-h68k.dts deleted file mode 100644 index 5ae1596..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-h68k.dts +++ /dev/null @@ -1,882 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2022 AmadeusGhost -// Copyright (c) 2023 amazingfate - -/dts-v1/; - -#include -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "HINLINK H68K"; - compatible = "hinlink,h68k", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc0; - - led-boot = &led_work; - led-failsafe = &led_work; - led-running = &led_work; - led-upgrade = &led_work; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&reset_button_pin>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <50>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_net_en>, <&led_sata_en>, <&led_work_en>; - - led_net: net { - label = "blue:net"; - gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; - }; - - led_sata: sata { - label = "amber:sata"; - gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; - }; - - led_work: work { - label = "green:work"; - gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; - }; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - rfkill-bt { - compatible = "rfkill-gpio"; - label = "rfkill-m2-bt"; - radio-type = "bluetooth"; - shutdown-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; - }; - - rfkill-wifi { - compatible = "rfkill-gpio"; - label = "rfkill-pcie-wlan"; - radio-type = "wlan"; - shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_sys_en>; - - vin-supply = <&vcc5v0_sys>; - }; - - /* eth 2.5g power - for H66K H69K - */ - vcc3v3_pcie3: vcc3v3-pcie3-regulator { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_pcie3"; - regulator-boot-on; - - enable-active-high; - gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie3_en>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - compatible = "regulator-fixed"; - - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - - vin-supply = <&vcc5v0_sys>; - - }; - - vcc3v3_sd_pwren: vcc3v3-sd-pwren-regulator { - compatible = "regulator-fixed"; - - regulator-name = "vcc3v3_sd_pwren"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; /* SD_PWREN */ - vin-supply = <&vcc3v3_sys>; - - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_sd_en>; - }; - - rk809-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Analog RK809"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - simple-audio-card,codec { - sound-dai = <&rk809>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 127 163 255>; - #cooling-cells = <2>; - fan-supply = <&vcc5v0_sys>; - pwms = <&pwm0 0 50000 0>; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_thermal { - trips { - cpu_cool: cpu_cool { - temperature = <45000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_warm: cpu_warm { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_hot: cpu_hot { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map1 { - trip = <&cpu_cool>; - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - }; - - map2 { - trip = <&cpu_warm>; - cooling-device = <&fan 2 THERMAL_NO_LIMIT>; - }; - - map3 { - trip = <&cpu_hot>; - cooling-device = <&fan 3 THERMAL_NO_LIMIT>; - }; - }; -}; - -&gmac0 { - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "input"; - phy-mode = "rgmii-id"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 200000>; - tx_delay = <0x3c>; - rx_delay = <0x2f>; - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "input"; - phy-mode = "rgmii-id"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 200000>; - tx_delay = <0x3c>; - rx_delay = <0x2f>; - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #sound-dai-cells = <0>; - - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; - - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - - pwrkey { - status = "okay"; - }; - - pinctrl_rk8xx: pinctrl_rk8xx { - gpio-controller; - #gpio-cells = <2>; - - rk817_slppin_null: rk817_slppin_null { - pins = "gpio_slp"; - function = "pin_fun0"; - }; - - rk817_slppin_slp: rk817_slppin_slp { - pins = "gpio_slp"; - function = "pin_fun1"; - }; - - rk817_slppin_pwrdn: rk817_slppin_pwrdn { - pins = "gpio_slp"; - function = "pin_fun2"; - }; - - rk817_slppin_rst: rk817_slppin_rst { - pins = "gpio_slp"; - function = "pin_fun3"; - }; - }; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - rk809_codec: codec { - #sound-dai-cells = <0>; - compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; - clocks = <&cru I2S1_MCLKOUT_TX>; - clock-names = "mclk"; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_mclk>; - hp-volume = <20>; - spk-volume = <3>; - mic-in-differential; - status = "okay"; - }; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - phy-supply = <&vcc3v3_sys>; - reg = <0x0>; - }; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - phy-supply = <&vcc3v3_sys>; - reg = <0x0>; - }; -}; - -&pcie2x1 { - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_sys>; - status = "okay"; -}; - -&pcie30phy { - data-lanes = <1 2>; - status = "okay"; -}; - -&pcie3x1 { - num-lanes = <1>; - reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie3>; - status = "okay"; - - pcie@0,0 { - reg = <0x00100000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - rtl8125_1: pcie-eth@10,0 { - compatible = "pci10ec,8125"; - reg = <0x000000 0 0 0 0>; - realtek,led-data = <0x0200>; - }; - }; -}; - -&pcie3x2 { - num-lanes = <1>; - rockchip,init-delay-ms = <100>; - reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie3>; - status = "okay"; - - pcie@0,0 { - reg = <0x00200000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - rtl8125_2: pcie-eth@20,0 { - compatible = "pci10ec,8125"; - reg = <0x000000 0 0 0 0>; - realtek,led-data = <0x0200>; - }; - }; -}; - -&pinctrl { - button { - reset_button_pin: reset-button-pin { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - led_work_en: led-work-en { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_sata_en: led-user-en { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_net_en: led-net-en { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - vcc { - vcc3v3_sys_en: vcc3v3-sys-en { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sd { - vcc3v3_sd_en: vcc3v3-sd_en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - vcc3v3_pcie3_en: vcc3v3_pcie3_en { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - vmmc-supply = <&vcc3v3_sd_pwren>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - status = "disabled"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-hnas.dts b/patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-hnas.dts deleted file mode 100644 index 9d966a8..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3568-hinlink-hnas.dts +++ /dev/null @@ -1,228 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2022 AmadeusGhost -// Copyright (c) 2022 Flippy -// Copyright (c) 2023 amazingfate - -/dts-v1/; - -#include "rk3568-hinlink-h68k.dts" - -/ { - model = "HINLINK HNAS"; - compatible = "hinlink,hnas", "rockchip,rk3568"; - - fan0: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - cooling-levels = <8 39 70 100 131 162 193 224 255>; - pwms = <&pwm0 0 10000 0>; - }; - - hdd_leds { - led_hdd1: led-hdd1 { - pinctrl-names = "default"; - pinctrl-0 = <&led_hdd1_pin>; - label = "led:hdd1"; - gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; - }; - - led_hdd2: led-hdd2 { - pinctrl-names = "default"; - pinctrl-0 = <&led_hdd2_pin>; - label = "led:hdd2"; - gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; - }; - - led_hdd3: led-hdd3 { - pinctrl-names = "default"; - pinctrl-0 = <&led_hdd3_pin>; - label = "led:hdd3"; - gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; - }; - - led_hdd4: led-hdd4 { - pinctrl-names = "default"; - pinctrl-0 = <&led_hdd4_pin>; - label = "led:hdd4"; - gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; - }; - }; - - sata_pm_power: sata-pm-power { - compatible = "regulator-fixed"; - regulator-name = "sata_pm_power"; - regulator-enable-ramp-delay = <1000000>; - regulator-always-on; - regulator-boot-on; - - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&sata_pm_power_en>; - vin-supply = <&vcc3v3_sys>; - }; - - sata_pm_reset: sata-pm-reset { - compatible = "regulator-fixed"; - regulator-name = "sata_pm_reset"; - regulator-enable-ramp-delay = <1000000>; - regulator-always-on; - regulator-boot-on; - - enable-active-high; - gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&sata_pm_reset_en>; - vin-supply = <&vcc3v3_sys>; - }; - - sata_hdd_power: sata-hdd-power { - compatible = "regulator-fixed"; - regulator-name = "sata_hdd_power"; - regulator-enable-ramp-delay = <1000000>; - regulator-always-on; - regulator-boot-on; - - enable-active-high; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&sata_hdd_power_en>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&gmac0 { - status = "disabled"; -}; - -&gmac1 { - status = "disabled"; -}; - -&pinctrl { - hdd-leds { - led_hdd1_pin: led-hdd1-pin { - rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_hdd2_pin: led-hdd2-pin { - rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_hdd3_pin: led-hdd3-pin { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_hdd4_pin: led-hdd4-pin { - rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sata-pm { - sata_pm_power_en: sata-pm-power-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - sata_pm_reset_en: sata-pm-reset-en { - rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - sata_hdd_power_en: sata-hdd-power-en { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&cpu_thermal { - trips { - trip0: trip-point@0 { - temperature = <45000>; - hysteresis = <5000>; - type = "active"; - }; - trip1: trip-point@1 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - trip2: trip-point@2 { - temperature = <55000>; - hysteresis = <5000>; - type = "active"; - }; - trip3: trip-point@3 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - trip4: trip-point@4 { - temperature = <65000>; - hysteresis = <5000>; - type = "active"; - }; - trip5: trip-point@5 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - trip6: trip-point@6 { - temperature = <75000>; - hysteresis = <5000>; - type = "active"; - }; - trip7: trip-point@7 { - temperature = <80000>; - hysteresis = <1000>; - type = "active"; - }; - }; - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&fan0 0 1>; - contribution = <1024>; - }; - map1 { - trip = <&trip1>; - cooling-device = <&fan0 1 2>; - contribution = <1024>; - }; - map2 { - trip = <&trip2>; - cooling-device = <&fan0 2 3>; - contribution = <1024>; - }; - map3 { - trip = <&trip3>; - cooling-device = <&fan0 3 4>; - contribution = <1024>; - }; - map4 { - trip = <&trip4>; - cooling-device = <&fan0 4 5>; - contribution = <1024>; - }; - map5 { - trip = <&trip5>; - cooling-device = <&fan0 5 6>; - contribution = <1024>; - }; - map6 { - trip = <&trip6>; - cooling-device = <&fan0 6 7>; - contribution = <1024>; - }; - map7 { - trip = <&trip7>; - cooling-device = <&fan0 7 8>; - contribution = <1024>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3568-mixtile-edge2.dts b/patch/kernel/rockchip64-6.14/dt/rk3568-mixtile-edge2.dts deleted file mode 100644 index 0aae412..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3568-mixtile-edge2.dts +++ /dev/null @@ -1,767 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2024 Focalcrest Co., Ltd. - * - */ - -/dts-v1/; -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "Mixtile Edge 2"; - compatible = "focalcrest,mixtile-edge2", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc0; - mmc2 = &sdmmc2; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - work_led: work { - gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - rk809-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Analog RK809"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - - simple-audio-card,codec { - sound-dai = <&rk809>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <200>; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb_hub: vcc5v0-usb-hub { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb_hub"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_hub_en>; - gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en>; - regulator-name = "vcc5v0_usb_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc3v3_pcie: vcc3v3-pcie { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie_en_pin>; - gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_m2: vcc3v3-m2 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_m2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - }; - - vcc1v8_m2: vcc1v8-m2 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_m2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - pinctrl-names = "default"; - pinctrl-0 = <&vcc1v8_m2_pin>; - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; - }; - - vcc3v3_minipcie: vcc3v3-minipcie { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_minipcie"; - regulator-always-on; - regulator-boot-on; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>,<&cru CLK_MAC1_2TOP>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; - snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; - system-power-controller; - #sound-dai-cells = <0>; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - codec { - mic-in-differential; - }; - }; -}; - - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m1_xfer>; - status = "disabled"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3m0_xfer>; - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "rtcic_32kout"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x2m1_pins>; - reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pinctrl { - ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - bt { - bt_enable: bt-enable { - rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake: bt-host-wake { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bt_wake: bt-wake { - rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_host_en: vcc5v0_usb_host_en { - rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - vcc1v8-m2-pin { - vcc1v8_m2_pin: vcc1v8-m2-pin { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr50; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc2 { - supports-sdio; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - sd-uhs-sdr50; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4m1_xfer>; -}; - -&uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - /* vddio comes from regulator on module, use IO bank voltage instead */ - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3568-yy3568.dts b/patch/kernel/rockchip64-6.14/dt/rk3568-yy3568.dts deleted file mode 100755 index 70022b7..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3568-yy3568.dts +++ /dev/null @@ -1,718 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - * - */ -/dts-v1/; - -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "Youyeetoo YY3568"; - compatible = "youyeetoo,yy3568", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - mmc2 = &sdmmc2; - mmc1 = &sdmmc0; - mmc0 = &sdhci; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led_user: led-0 { - gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_user_en>; - }; - led_power: led-1 { - gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_power_en>; - }; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - rk809-sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - hp-det-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Analog RK809"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - simple-audio-card,codec { - sound-dai = <&rk809>; - }; - }; - - vcc5v0_otg: regulator-vbus-typec { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; - regulator-name = "vcc5v0_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* actually fed by vcc5v0_sys, dependent - * on pi6c clock generator - */ - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie30x1: regulator-vcc3v3-pcie30x1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x1_enable_h>; - regulator-name = "vcc3v3_pcie30x1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_enable_h>; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - pcie30_avdd0v9: regulator-pcie30-avdd0v9 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: regulator-pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_sys: regulator-vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_input>; - }; - - vcc5v0_sys: regulator-vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_input>; - }; - - /* labeled +12v_input in schematic */ - vcc12v_input: regulator-vcc5v-input { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_input"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; -}; - -&combphy1 { - phy-supply = <&vcc3v3_pcie30x1>; - status = "okay"; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; - -&hdmi { - assigned-clocks = <&cru CLK_HDMI_CEC>; - assigned-clock-rates = <32768>; - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&pcie2x1 { - pinctrl-names = "default"; - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pi6c_05>; - status = "okay"; -}; - -&pcie30phy { - data-lanes = <1 2>; - status = "okay"; -}; - -&pcie3x2 { - num-lanes = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x2_reset_h>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pi6c_05>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc12v_input>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&pinctrl { - leds { - led_user_en: led_user_en { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - led_power_en: led_power_en { - rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcie { - pcie30x1_enable_h: pcie30x1-enable-h { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie30x2_reset_h: pcie30x2-reset-h { - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_enable_h: pcie-enable-h { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_otg_en: vcc5v0_otg_en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - /* Also used in pcie30x1_clkreqnm0 */ - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc2 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; - sd-uhs-sdr104; - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c916"; - reg = <0x0>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; - }; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c916"; - reg = <0x0>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; - }; -}; - -&gmac0 { - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy0>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - status = "okay"; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - extcon = <&usb2phy0>; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; \ No newline at end of file diff --git a/patch/kernel/rockchip64-6.14/dt/rk3588-bananapi-m7.dts b/patch/kernel/rockchip64-6.14/dt/rk3588-bananapi-m7.dts deleted file mode 100644 index 8489240..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3588-bananapi-m7.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3588-armsom-sige7.dts" - -/ { - model = "Banana Pi M7"; - compatible = "bananapi,m7", "rockchip,rk3588"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3588-cyber-aib.dts b/patch/kernel/rockchip64-6.14/dt/rk3588-cyber-aib.dts deleted file mode 100644 index 3098d48..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3588-cyber-aib.dts +++ /dev/null @@ -1,1099 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * Copyright (c) 2024 Cyber RD Group - * - * Copyright (c) 2024 Tianling Shen - * - * Copyright (c) 2024 chainsx - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include -#include "rk3588.dtsi" - -/ { - model = "Cyber 3588 AIB"; - compatible = "cyber,cyber3588-aib", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&red_led_pin>, <&green_led_pin>, <&blue_led_pin>; - - status_led: led-0 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - }; - - led-2 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 50 80 120 160 220>; - fan-supply = <&vcc5v0_sys>; - pwms = <&pwm1 0 10000 0>; - #cooling-cells = <2>; - }; - - rfkill-wlan { - compatible = "rfkill-gpio"; - label = "rfkill-pcie-wlan"; - radio-type = "wlan"; - shutdown-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - }; - - rfkill-wwan { - compatible = "rfkill-gpio"; - label = "rfkill-wwan"; - radio-type = "wwan"; - pinctrl-names = "default"; - pinctrl-0 = <&wwan_disable_h>; - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; - shutdown-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - /* pi6c pcie clock generator */ - vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_power_h>; - regulator-name = "vcc3v3_pi6c_03"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* actually fed by vcc5v0_sys, dependent on pi6c clock generator */ - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie2x1l0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc3v3_pi6c_03>; - }; - - vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie2x1l2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - /* actually fed by vcc5v0_sys, dependent on pi6c clock generator */ - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc3v3_pi6c_03>; - }; - - vcc3v3_switch: vcc3v3-switch-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&phy_pwr_en>; - regulator-name = "vcc3v3_switch"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_wwan: vcc3v3-wwan-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&wwan_power_h>; - regulator-name = "vcc3v3_wwan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc3v3_pcie30>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sata: vcc5v0-sata-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sata_pwr_en>; - regulator-name = "vcc5v0_sata"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; - regulator-name = "vcc5v0_typec"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac1 { - clock_in_out = "output"; - phy-mode = "rgmii-rxid"; - phy-supply = <&vcc3v3_switch>; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - tx_delay = <0x42>; - /* RK3588 GMAC is broken currently */ - status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&hdmi0 { - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&hdptxphy0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m0_xfer>; - status = "okay"; - - usbc0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vcc5v0_typec>; - status = "okay"; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - sink-pdos = - ; - source-pdos = - ; - try-power-role = "source"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - usbc0_role_sw: endpoint { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - - port@2 { - reg = <2>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&mdio1 { - switch@1d { - compatible = "realtek,rtl8365mb"; - reg = <29>; - reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan2"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan4"; - }; - - port@3 { - reg = <3>; - label = "lan5"; - }; - - port@4 { - reg = <4>; - label = "lan6"; - }; - - port@7 { - reg = <7>; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -/* M.2 M-Key */ -&pcie2x1l0 { - max-link-speed = <3>; - phys = <&pcie30phy>; - reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; - status = "okay"; -}; - -/* Right 2.5 GbE port */ -&pcie2x1l1 { - max-link-speed = <3>; - phys = <&pcie30phy>; - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; - - pcie@0,0 { - reg = <0x00300000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - rtl8125_0: pcie@30,0 { - compatible = "pci10ec,8125"; - reg = <0x000000 0 0 0 0>; - - label = "lan1"; - realtek,led-data = <0x0 0x0 0x200 0x2b>; - }; - }; -}; - -/* Left 2.5 GbE port */ -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; - status = "okay"; - - pcie@0,0 { - reg = <0x00400000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - rtl8125_1: pcie@40,0 { - compatible = "pci10ec,8125"; - reg = <0x000000 0 0 0 0>; - - label = "wan"; - realtek,led-data = <0x0 0x0 0x200 0x2b>; - }; - }; -}; - -&pcie30phy { - data-lanes = <1 3 2 4>; - status = "okay"; -}; - -/* M.2 E-key */ -&pcie3x4 { - max-link-speed = <3>; - num-lanes = <1>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -/* M.2 B-key */ -&pcie3x2 { - max-link-speed = <3>; - num-lanes = <1>; - reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_wwan>; - status = "okay"; -}; - -&pinctrl { - gpio-leds { - red_led_pin: red-led-pin { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - green_led_pin: green-led-pin { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - blue_led_pin: blue-led-pin { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_pwr_en: phy-pwr-en { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcie { - pcie_power_h: pcie-power-h { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - wwan_power_h: wwan-power-h { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - wwan_disable_h: wwan-disable-h { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sata { - sata_pwr_en: sata-pwr-en { - rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vcc5v0_otg_en: vcc5v0-otg-en { - rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&pwm1 { - pinctrl-names = "active"; - pinctrl-0 = <&pwm1m1_pins>; - status = "okay"; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sata1 { - ahci-supply = <&vcc5v0_sata>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - no-sdio; - no-sd; - non-removable; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - no-sdio; - no-mmc; - sd-uhs-sdr50; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - status = "okay"; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: dcdc-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&usbdp_phy0 { - mode-switch; - orientation-switch; - sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - usb-role-switch; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host2_xhci { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3588-hinlink-h88k.dts b/patch/kernel/rockchip64-6.14/dt/rk3588-hinlink-h88k.dts deleted file mode 100644 index fc9a7c8..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3588-hinlink-h88k.dts +++ /dev/null @@ -1,973 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include "rk3588.dtsi" - -/ { - model = "HINLINK H88K"; - compatible = "hinlink,h88k", "rockchip,rk3588"; - - aliases { - ethernet0 = &gmac0; - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; - }; - - analog-sound { - compatible = "simple-audio-card"; - label = "rockchip,es8388-codec"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_detect>; - simple-audio-card,name = "Analog"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - simple-audio-card,bitclock-master = <&daicpu>; - simple-audio-card,frame-master = <&daicpu>; - - simple-audio-card,widgets = - "Microphone", "Onboard Microphone", - "Microphone", "Microphone Jack", - "Speaker", "Speaker", - "Headphone", "Headphones"; - - simple-audio-card,routing = - "Headphones", "LOUT1", - "Headphones", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - - /* single ended signal to LINPUT1 */ - "LINPUT1", "Microphone Jack", - "RINPUT1", "Microphone Jack", - /* differential signal */ - "LINPUT2", "Onboard Microphone", - "RINPUT2", "Onboard Microphone"; - - daicpu: simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - system-clock-frequency = <12288000>; - }; - - daicodec: simple-audio-card,codec { - sound-dai = <&es8388>; - system-clock-frequency = <12288000>; - }; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_net_en>, <&led_sata_en>, - <&led_user_en>, <&led_work_en>; - - net { - label = "blue:net"; - gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; - }; - - sata { - label = "amber:sata"; - gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - }; - - user { - label = "green:user"; - gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - }; - - work { - label = "red:work"; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - hdmi0-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi0_con_in: endpoint { - remote-endpoint = <&hdmi0_out_con>; - }; - }; - }; - - hdmi1-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi1_con_in: endpoint { - remote-endpoint = <&hdmi1_out_con>; - }; - }; - }; - - rfkilli-wifi { - compatible = "rfkill-gpio"; - label = "rfkill-pcie-wlan"; - radio-type = "wlan"; - shutdown-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; - }; - - rfkill-bt { - compatible = "rfkill-gpio"; - label = "rfkill-m2-bt"; - radio-type = "bluetooth"; - shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-name = "vcc12v_dcin"; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - /* it's modem reset pin */ - modem_enable: modem-enable { - compatible = "regulator-fixed"; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "modem-enable"; - vin-supply = <&vcc_3v3_s3>; - startup-delay-us = <500000>; - pinctrl-names = "default"; - pintctrl-0 = <&modem_reset_en>; - }; - - vcc3v3_modem: vcc3v3-modem { - compatible = "regulator-fixed"; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_modem"; - pinctrl-names = "default"; - pintctrl-0 = <&modem_power_en>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb_hub: vcc5v0-usb-hub { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_hub_en>; - regulator-name = "vcc5v0_usb_hub"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac0 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - pinctrl-names = "default"; - rx_delay = <0x00>; - tx_delay = <0x43>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&hdmi0 { - status = "okay"; -}; - - -&hdptxphy0 { - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&hdmi0_out { - hdmi0_out_con: endpoint { - remote-endpoint = <&hdmi0_con_in>; - }; -}; - -&hdmi1 { - status = "okay"; -}; - -&hdmi1_in { - hdmi1_in_vp1: endpoint { - remote-endpoint = <&vp1_out_hdmi1>; - }; -}; - -&hdmi1_out { - hdmi1_out_con: endpoint { - remote-endpoint = <&hdmi1_con_in>; - }; -}; - -&hdptxphy1 { - status = "okay"; -}; - -&hdmi_receiver_cma { - status = "okay"; -}; - -&hdmi_receiver { - status = "okay"; - hpd-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; - pinctrl-names = "default"; - memory-region = <&hdmi_receiver_cma>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c7 { - status = "okay"; - - es8388: audio-codec@11 { - compatible = "everest,es8388"; - reg = <0x11>; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - AVDD-supply = <&vcc_3v3_s3>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - DVDD-supply = <&vcc_1v8_s3>; - HPVDD-supply = <&vcc_3v3_s3>; - PVDD-supply = <&vcc_1v8_s3>; - #sound-dai-cells = <0>; - }; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; -}; - -&mdio0 { - rgmii_phy: ethernet-phy@1 { - /* RTL8211F */ - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - pinctrl-names = "default"; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - hdmirx { - hdmirx_hpd: hdmirx-hpd { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led_net_en: led_net_en { - rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_sata_en: led_sata_en { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_user_en: led_user_en { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_work_en: led_work_en { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - modem { - modem_power_en: modem-power-en { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - modem_reset_en: modem-reset-en { - rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8211f { - rtl8211f_rst: rtl8211f-rst { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { - rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - no-sdio; - no-sd; - non-removable; - status = "okay"; -}; - -&sdmmc { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - /* connected to USB hub, which is powered by vcc5v0_sys */ - phy-supply = <&vcc5v0_sys>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usbdp_phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host2_xhci { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; - -&vp1 { - vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { - reg = ; - remote-endpoint = <&hdmi1_in_vp1>; - }; -}; \ No newline at end of file diff --git a/patch/kernel/rockchip64-6.14/dt/rk3588-mixtile-blade3.dts b/patch/kernel/rockchip64-6.14/dt/rk3588-mixtile-blade3.dts deleted file mode 100644 index ef0adae..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3588-mixtile-blade3.dts +++ /dev/null @@ -1,712 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include "rk3588.dtsi" - -/ { - model = "Mixtile Blade 3"; - compatible = "mixtile,blade3", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; - - pcie20_avdd0v85: pcie20-avdd0v85-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_vcc3v3_en>; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s0"; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - enable-active-high; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c4 { - pinctrl-0 = <&i2c4m0_xfer>; - status = "okay"; -}; - -/* exposed on the 30-pin connector; shows up as i2c-3 */ -&i2c5 { - pinctrl-0 = <&i2c5m3_xfer>; - status = "okay"; -}; - -&i2s2_2ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m1_mclk - &i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi - &i2s2m1_sdo>; - status = "okay"; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; - status = "okay"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; - status = "okay"; -}; - -&pinctrl { - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_1_rst: pcie2-1-rst { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie3 { - pcie3_rst: pcie3-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie3_vcc3v3_en: pcie3-vcc3v3-en { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm8 { - pinctrl-names = "active"; - pinctrl-0 = <&pwm8m2_pins>; - status = "okay"; -}; - -&pwm14 { - pinctrl-0 = <&pwm14m2_pins>; - status = "okay"; -}; - -&pwm15 { - pinctrl-0 = <&pwm15m3_pins>; - status = "disabled"; -}; - -&spi4 { - pinctrl-names = "default"; - pinctrl-0 = <&spi4m2_cs0 &spi4m2_pins>; - num-cs = <1>; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - // hs400 causes immediate trouble, hs200 works at around 150mb/s - // mmc-hs400-1_8v; - // mmc-hs400-enhanced-strobe; - mmc-hs200-1_8v; - status = "okay"; -}; - -&sdmmc { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3588-rock-5b-plus.dts b/patch/kernel/rockchip64-6.14/dt/rk3588-rock-5b-plus.dts deleted file mode 100644 index d0f9a96..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3588-rock-5b-plus.dts +++ /dev/null @@ -1,1039 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include -#include "rk3588.dtsi" - -/ { - model = "Radxa ROCK 5B+"; - compatible = "radxa,rock-5b-plus", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - analog-sound { - compatible = "audio-graph-card"; - label = "rk3588-es8316"; - - widgets = "Microphone", "Mic Jack", - "Headphone", "Headphones"; - - routing = "MIC2", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR"; - - dais = <&i2s0_8ch_p0>; - hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_detect>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_rgb_b>; - - led_rgb_b { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 120 150 180 210 240 255>; - fan-supply = <&vcc5v0_sys>; - pwms = <&pwm1 0 50000 0>; - #cooling-cells = <2>; - }; - - rfkill { - compatible = "rfkill-gpio"; - label = "rfkill-pcie-wlan"; - radio-type = "wlan"; - shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - - rfkill-bt { - compatible = "rfkill-gpio"; - label = "rfkill-m2-bt"; - radio-type = "bluetooth"; - shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - }; - - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_vcc3v3_en>; - regulator-name = "vcc3v3_pcie2x1l0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie2x1l2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_vcc3v3_en>; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc5v0_sys>; - }; - - vbus5v0_typec: vbus5v0-typec-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vbus5v0_typec_en>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&hdmi0 { - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&hdptxphy0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c4 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m1_xfer>; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio3>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - - source-pdos = - ; - - altmodes { - displayport { - svid = /bits/ 16 <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - // TODO this still does not work right. kind of poking in the dark right now though.. - port@0 { - reg = <0>; - - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <0>; - - usbc0_role_sw: endpoint { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - - port@2 { - reg = <1>; - - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&i2c6 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c7 { - status = "okay"; - - es8316: audio-codec@11 { - compatible = "everest,es8316"; - reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s0_8ch_p0_0>; - }; - }; - }; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; - - i2s0_8ch_p0: port { - i2s0_8ch_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8316_p0_0>; - }; - }; -}; - -&package_thermal { - polling-delay = <1000>; - - trips { - package_fan0: package-fan0 { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - - package_fan1: package-fan1 { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map0 { - trip = <&package_fan0>; - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - }; - - map1 { - trip = <&package_fan1>; - cooling-device = <&fan 2 THERMAL_NO_LIMIT>; - }; - }; -}; - -&pcie2x1l0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; - status = "okay"; -}; - -&pcie2x1l2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led_rgb_b: led-rgb-b { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_0_vcc3v3_en: pcie2-0-vcc-en { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie3 { - pcie3_rst: pcie3-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie3_vcc3v3_en: pcie3-vcc3v3-en { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vbus5v0_typec_en: vbus5v0-typec-en { - rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - // CHANGED: manually applied rock5b hs200 patch - mmc-hs200-1_8v; - status = "okay"; -}; - -&sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -// removed from -plus vs 5b in vendor DT -// TODO find out why? -/* -&sdio { - max-frequency = <200000000>; - no-sd; - no-mmc; - non-removable; - bus-width = <4>; - cap-sdio-irq; - disable-wp; - keep-power-in-suspend; - wakeup-source; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_pcie2x1l0>; - vqmmc-supply = <&vcc_1v8_s3>; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom0_pins>; - status = "okay"; -}; -*/ - -&sfc { - pinctrl-names = "default"; - pinctrl-0 = <&fspim2_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -&tsadc { - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - /* connected to USB hub, which is powered by vcc5v0_sys */ - phy-supply = <&vcc5v0_sys>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; - - mode-switch; - orientation-switch; - sbu1-dc-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - usb-role-switch; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host2_xhci { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3588s-nanopi-m6.dts b/patch/kernel/rockchip64-6.14/dt/rk3588s-nanopi-m6.dts deleted file mode 100644 index 30c10ce..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3588s-nanopi-m6.dts +++ /dev/null @@ -1,907 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include -#include "rk3588s.dtsi" - -/ { - model = "FriendlyElec NanoPi M6"; - compatible = "friendlyelec,nanopi-m6", "rockchip,rk3588s"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - analog-sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - - simple-audio-card,format = "i2s"; - simple-audio-card,hp-det-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "realtek,rt5616-codec"; - - simple-audio-card,routing = - "Headphones", "HPOL", - "Headphones", "HPOR", - "MIC1", "Microphone Jack", - "Microphone Jack", "micbias1"; - simple-audio-card,widgets = - "Headphone", "Headphones", - "Microphone", "Microphone Jack"; - - simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - }; - - simple-audio-card,codec { - sound-dai = <&rt5616>; - }; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-maskrom { - label = "Maskrom"; - linux,code = ; - press-threshold-microvolt = <1800>; - }; - }; - - adc-keys-1 { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-maskrom { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <1800>; - }; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi0_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - sys_led: led-0 { - label = "sys_led"; - gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; - - user_led: led-1 { - label = "user_led"; - gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&user_led_pin>; - }; - }; - - vcc5v0_sys: regulator-vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_3v3_s0: regulator-vcc-3v3-s0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s0"; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_s0_pwr>; - regulator-name = "vcc_3v3_sd_s0"; - regulator-boot-on; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <3000000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_3v3_pcie20: regulator-vcc3v3-pcie20 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_pcie20"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_3v3_pcie20_m2: regulator-vcc3v3-pcie20-m2 { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_m2_0_pwren>; - regulator-name = "vcc_3v3_pcie20_m2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc5v0_usb: regulator-vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host_20: regulator-vcc5v0-host-20 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host20_en>; - regulator-name = "vcc5v0_host_20"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb_otg0: regulator-vbus5v0-typec { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - regulator-name = "vcc5v0_usb_otg0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - pinctrl-names = "default"; - tx_delay = <0x42>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&hdmi0 { - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&hdmi0_out { - hdmi0_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdptxphy0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - clock-frequency = <200000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m0_xfer>; - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c7 { - clock-frequency = <200000>; - status = "okay"; - - rt5616: audio-codec@1b { - compatible = "realtek,rt5616"; - reg = <0x1b>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - status = "okay"; - #sound-dai-cells = <0>; - }; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id001c.c916"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; - status = "okay"; -}; - -&pcie2x1l2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_m2_0_prsnt>; - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20_m2>; - status = "okay"; -}; - -&pinctrl { - gpio-leds { - sys_led_pin: sys-led-pin { - rockchip,pins = - <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led_pin: lan1-led-pin { - rockchip,pins = - <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_m2_0_pwren: pcie-m20-pwren { - rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - pcie_m2_0_prsnt: pcie-m20-prsnt { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sd_s0_pwr: sd-s0-pwr { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - typec5v_pwren: typec5v-pwren { - rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_host20_en: vcc5v0-host20-en { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8211f { - rtl8211f_rst: rtl8211f-rst { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs200-1_8v; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - no-mmc; - no-sdio; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "avcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - avdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "avdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "avdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - phy-supply = <&vcc5v0_usb_otg0>; - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host_20>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host_20>; - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/dt/rk3588s-youyeetoo-r1.dts b/patch/kernel/rockchip64-6.14/dt/rk3588s-youyeetoo-r1.dts deleted file mode 100644 index 953c660..0000000 --- a/patch/kernel/rockchip64-6.14/dt/rk3588s-youyeetoo-r1.dts +++ /dev/null @@ -1,887 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include -#include "rk3588s.dtsi" - -/ { - model = "Youyeetoo R1"; - compatible = "youyeetoo,r1", "rockchip,rk3588s"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - - sys_led: led-0 { - label = "sys_led"; - gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; - }; - - /* HDMI 0 CONNECTOR */ - - hdmi0-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi0_con_in: endpoint { - remote-endpoint = <&hdmi0_out_con>; - }; - }; - }; - - /* POWER REGULATOR 12V DC-IN */ - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* POWER REGULATOR 5V SYS */ - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - /* POWER REGULATOR CPU */ - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* POWER REGULATOR 3V (SD) */ - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s0"; - enable-active-high; - regulator-boot-on; - gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_s0_pwr>; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <3000000>; - vin-supply = <&vcc_3v3_s3>; - }; - - /* POWER REGULATOR 3.3V (PCIE)*/ - - vcc_3v3_pcie20: vcc3v3-pcie20-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_pcie20"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - /* POWER REGULATOR 5V (USB2 & USB3) */ - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host_20: vcc5v0-host-20 { // U13 (USB 2.0) - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host20_en>; - regulator-name = "vcc5v0_host_20"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_host_30: vcc5v0-host-30 { // U12 (USB 3.0) - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host30_en>; - regulator-name = "vcc5v0_host_30"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - - /* BLUETOOTH */ - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - status = "okay"; - }; - - /* WIFI */ - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "rtl8852be"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - /* FAN */ - fan0: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - cooling-levels = <100 160 190 200 215 235 255>; - pwms = <&pwm6 0 40000 0>; - fan-supply = <&vcc12v_dcin>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - pinctrl-names = "default"; - tx_delay = <0x42>; - tx_delay = <0x43>; - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&hdmi0_out { - hdmi0_out_con: endpoint { - remote-endpoint = <&hdmi0_con_in>; - }; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdptxphy0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - - /* RTC */ - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - status = "okay"; - }; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&package_thermal { - polling-delay = <1000>; - - trips { - package_fan0: package-fan0 { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - package_fan1: package-fan1 { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map1 { - trip = <&package_fan0>; - cooling-device = <&fan0 THERMAL_NO_LIMIT 1>; - }; - map2 { - trip = <&package_fan1>; - cooling-device = <&fan0 2 THERMAL_NO_LIMIT>; - }; - }; -}; - - -&mdio1 { - rgmii_phy1: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - rockchip,init-delay-ms = <100>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; - status = "okay"; -}; - - -&pinctrl { - /* TODO: SOUND */ - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - /* GPIO LEDS */ - gpio-leds { - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - - }; - }; - /* RTC */ - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - /* SD */ - sdmmc { - sd_s0_pwr: sd-s0-pwr { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - /* USB */ - usb { - vcc5v0_host20_en: vcc5v0-host20-en { // USB 2.0 - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - vcc5v0_host30_en: vcc5v0-host30-en { // USB 3.0 - rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - /* WIRELESS */ - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - /* HS400 doesn't work properly -> https://github.com/torvalds/linux/commit/cee572756aa2cb46e959e9797ad4b730b78a050b */ - mmc-hs200-1_8v; - max-frequency = <200000000>; - status = "okay"; -}; - -&sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fudr_moden0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&pwm6{ - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -/* USB */ - -&u2phy0 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy0_otg { - phy-supply = <&vcc5v0_host_30>; - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host_20>; - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host_20>; - status = "okay"; -}; - -&usb_host0_xhci { - status = "okay"; - dr_mode = "host"; - extcon = <&u2phy0>; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/general-clk-rockchip-rk3568-Add-PLL-rate-for-33.3MHz.patch b/patch/kernel/rockchip64-6.14/general-clk-rockchip-rk3568-Add-PLL-rate-for-33.3MHz.patch deleted file mode 100644 index 73170fd..0000000 --- a/patch/kernel/rockchip64-6.14/general-clk-rockchip-rk3568-Add-PLL-rate-for-33.3MHz.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Vasily Khoruzhick -Date: Mon, 17 Mar 2025 22:22:46 -0700 -Subject: clk: rockchip: rk3568: Add PLL rate for 33.3MHz - -Add PLL rate for 33.3 MHz to allow BTT HDMI5 screen to run at its native -mode of 800x480 - -Signed-off-by: Vasily Khoruzhick ---- - drivers/clk/rockchip/clk-rk3568.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c -index 111111111111..222222222222 100644 ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { - RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), - RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0), - RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), -+ RK3036_PLL_RATE(33300000, 4, 111, 5, 4, 1, 0), - { /* sentinel */ }, - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/general-fix-inno-usb2-phy-init.patch b/patch/kernel/rockchip64-6.14/general-fix-inno-usb2-phy-init.patch deleted file mode 100644 index 6c608e4..0000000 --- a/patch/kernel/rockchip64-6.14/general-fix-inno-usb2-phy-init.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Mon, 22 Aug 2022 20:51:22 +0000 -Subject: remove usb2phy extcon initialization causing kernel oops - ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 5 ----- - 1 file changed, 5 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -index 111111111111..222222222222 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1323,11 +1323,6 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, - goto out; - } - -- if (!of_property_read_bool(rphy->dev->of_node, "extcon")) { -- /* do initial sync of usb state */ -- id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); -- extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id); -- } - } - - out: --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/general-rk3328-dtsi-trb-ent-quirk.patch b/patch/kernel/rockchip64-6.14/general-rk3328-dtsi-trb-ent-quirk.patch deleted file mode 100644 index 2b93925..0000000 --- a/patch/kernel/rockchip64-6.14/general-rk3328-dtsi-trb-ent-quirk.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: schwar3kat <61094841+schwar3kat@users.noreply.github.com> -Date: Sat, 7 May 2022 15:51:38 +0200 -Subject: [ARCHEOLOGY] Enable rockchip64: XHCI HCD USB TRB ENT quirk for RK3328 - (#3763) - -> X-Git-Archeology: > recovered message: > This resolves a bug that affects r8153b USB network interface causing the RX interface to hang on load. -> X-Git-Archeology: > recovered message: > On some xHCI controllers (e.g. Rockchip RK3399/RK3328/RK1808), -> X-Git-Archeology: > recovered message: > they need to enable the ENT flag in the TRB data structure -> X-Git-Archeology: > recovered message: > to force xHC to prefetch the next TRB of a TD. -> X-Git-Archeology: > recovered message: > The quirk patch is already applied to dwc3 xhci usb on rockchip64. -> X-Git-Archeology: > recovered message: > Enable the quirk on RK3328 through device tree node properties in rk3328.dtsi -> X-Git-Archeology: - Revision 5e477fd42c734794edc13efd474ad1099d449446: https://github.com/armbian/build/commit/5e477fd42c734794edc13efd474ad1099d449446 -> X-Git-Archeology: Date: Sat, 07 May 2022 15:51:38 +0200 -> X-Git-Archeology: From: schwar3kat <61094841+schwar3kat@users.noreply.github.com> -> X-Git-Archeology: Subject: Enable rockchip64: XHCI HCD USB TRB ENT quirk for RK3328 (#3763) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -1071,6 +1071,7 @@ usbdrd3: usb@ff600000 { - snps,dis-del-phy-power-chg-quirk; - snps,dis_enblslpm_quirk; - snps,dis-tx-ipgap-linecheck-quirk; -+ snps,xhci-trb-ent-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/general-rt5651-add-mclk.patch b/patch/kernel/rockchip64-6.14/general-rt5651-add-mclk.patch deleted file mode 100644 index 785cb5c..0000000 --- a/patch/kernel/rockchip64-6.14/general-rt5651-add-mclk.patch +++ /dev/null @@ -1,133 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Piotr Szczepanik -Date: Sun, 5 Apr 2020 18:15:06 +0200 -Subject: [ARCHEOLOGY] Fixed sound from rt5651 on OrangePi 4 (#1870) - -> X-Git-Archeology: - Revision e14a61c229db1216fedc397e351c4bed15df820e: https://github.com/armbian/build/commit/e14a61c229db1216fedc397e351c4bed15df820e -> X-Git-Archeology: Date: Sun, 05 Apr 2020 18:15:06 +0200 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Fixed sound from rt5651 on OrangePi 4 (#1870) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 -> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 -> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) -> X-Git-Archeology: -> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e -> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - sound/soc/codecs/rt5651.c | 16 ++++++++++ - sound/soc/codecs/rt5651.h | 1 + - 2 files changed, 17 insertions(+) - -diff --git a/sound/soc/codecs/rt5651.c b/sound/soc/codecs/rt5651.c -index 111111111111..222222222222 100644 ---- a/sound/soc/codecs/rt5651.c -+++ b/sound/soc/codecs/rt5651.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - - #include "rl6231.h" - #include "rt5651.h" -@@ -1511,6 +1512,7 @@ static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, - static int rt5651_set_bias_level(struct snd_soc_component *component, - enum snd_soc_bias_level level) - { -+ struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component); - switch (level) { - case SND_SOC_BIAS_PREPARE: - if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) { -@@ -1518,6 +1520,13 @@ static int rt5651_set_bias_level(struct snd_soc_component *component, - snd_soc_component_update_bits(component, RT5651_D_MISC, - 0xc00, 0xc00); - } -+ if (!IS_ERR(rt5651->mclk)){ -+ if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) { -+ clk_disable_unprepare(rt5651->mclk); -+ } else { -+ clk_prepare_enable(rt5651->mclk); -+ } -+ } - break; - case SND_SOC_BIAS_STANDBY: - if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) { -@@ -2059,6 +2068,13 @@ static int rt5651_probe(struct snd_soc_component *component) - { - struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component); - -+ /* Check if MCLK provided */ -+ rt5651->mclk = devm_clk_get(component->dev, "mclk"); -+ if (PTR_ERR(rt5651->mclk) == -EPROBE_DEFER){ -+ dev_err(component->dev, "unable to get mclk\n"); -+ return -EPROBE_DEFER; -+ } -+ - rt5651->component = component; - - snd_soc_component_update_bits(component, RT5651_PWR_ANLG1, -diff --git a/sound/soc/codecs/rt5651.h b/sound/soc/codecs/rt5651.h -index 111111111111..222222222222 100644 ---- a/sound/soc/codecs/rt5651.h -+++ b/sound/soc/codecs/rt5651.h -@@ -2097,6 +2097,7 @@ struct rt5651_priv { - - int dmic_en; - bool hp_mute; -+ struct clk *mclk; - }; - - #endif /* __RT5651_H__ */ --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/general-v4l2-rkvdec-00-fixes.patch b/patch/kernel/rockchip64-6.14/general-v4l2-rkvdec-00-fixes.patch deleted file mode 100644 index 5f97698..0000000 --- a/patch/kernel/rockchip64-6.14/general-v4l2-rkvdec-00-fixes.patch +++ /dev/null @@ -1,673 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:35 +0000 -Subject: media: v4l2-common: Add helpers to calculate bytesperline and - sizeimage - -Add helper functions to calculate plane bytesperline and sizeimage, these -new helpers consider block width and height when calculating plane -bytesperline and sizeimage. - -This prepare support for new pixel formats added in next patch that make -use of block width and height. - -Signed-off-by: Jonas Karlman ---- - drivers/media/v4l2-core/v4l2-common.c | 77 +++++----- - 1 file changed, 38 insertions(+), 39 deletions(-) - -diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index 111111111111..222222222222 100644 ---- a/drivers/media/v4l2-core/v4l2-common.c -+++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -357,6 +357,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf - return info->block_h[plane]; - } - -+static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane, -+ unsigned int width) -+{ -+ unsigned int hdiv = plane ? info->hdiv : 1; -+ unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane], -+ v4l2_format_block_width(info, plane) * -+ v4l2_format_block_height(info, plane)); -+ -+ return DIV_ROUND_UP(bytes, hdiv); -+} -+ -+static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane, -+ unsigned int height) -+{ -+ unsigned int vdiv = plane ? info->vdiv : 1; -+ unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane)); -+ -+ return DIV_ROUND_UP(lines, vdiv); -+} -+ -+static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane, -+ unsigned int width, unsigned int height) -+{ -+ return v4l2_format_plane_width(info, plane, width) * -+ v4l2_format_plane_height(info, plane, height); -+} -+ - void v4l2_apply_frmsize_constraints(u32 *width, u32 *height, - const struct v4l2_frmsize_stepwise *frmsize) - { -@@ -392,37 +419,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, - - if (info->mem_planes == 1) { - plane = &pixfmt->plane_fmt[0]; -- plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0]; -+ plane->bytesperline = v4l2_format_plane_width(info, 0, width); - plane->sizeimage = 0; - -- for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- -- plane->sizeimage += info->bpp[i] * -- DIV_ROUND_UP(aligned_width, hdiv) * -- DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i]; -- } -+ for (i = 0; i < info->comp_planes; i++) -+ plane->sizeimage += -+ v4l2_format_plane_size(info, i, width, height); - } else { - for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- - plane = &pixfmt->plane_fmt[i]; - plane->bytesperline = -- info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv) / info->bpp_div[i]; -- plane->sizeimage = -- plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv); -+ v4l2_format_plane_width(info, i, width); -+ plane->sizeimage = plane->bytesperline * -+ v4l2_format_plane_height(info, i, height); - } - } - return 0; -@@ -446,22 +455,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat, - pixfmt->width = width; - pixfmt->height = height; - pixfmt->pixelformat = pixelformat; -- pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0]; -+ pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width); - pixfmt->sizeimage = 0; - -- for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- -- pixfmt->sizeimage += info->bpp[i] * -- DIV_ROUND_UP(aligned_width, hdiv) * -- DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i]; -- } -+ for (i = 0; i < info->comp_planes; i++) -+ pixfmt->sizeimage += -+ v4l2_format_plane_size(info, i, width, height); - return 0; - } - EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:36 +0000 -Subject: media: v4l2: Add NV15 and NV20 pixel formats - -Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for -10-bit buffers. - -NV15 and NV20 is a packed 10-bit 4:2:0/4:2:2 semi-planar Y/UV format -similar to P010 and P210 but has no padding between components. Instead, -luminance and chrominance samples are grouped into 4s so that each group is -packed into an integer number of bytes: - -YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes - -The '15' and '20' suffix refers to the optimum effective bits per pixel -which is achieved when the total number of luminance samples is a multiple -of 8 for NV15 and 4 for NV20. - -Signed-off-by: Jonas Karlman ---- - drivers/media/v4l2-core/v4l2-common.c | 3 +++ - drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ - include/uapi/linux/videodev2.h | 3 +++ - 3 files changed, 8 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index 111111111111..222222222222 100644 ---- a/drivers/media/v4l2-core/v4l2-common.c -+++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -284,6 +284,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) - { .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 }, - { .format = V4L2_PIX_FMT_P012, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 4, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2 }, - -+ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, -+ { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, -+ - { .format = V4L2_PIX_FMT_YUV410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 4 }, - { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 4 }, - { .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 4, .vdiv = 1 }, -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 111111111111..222222222222 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1367,6 +1367,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_NV42: descr = "Y/VU 4:4:4"; break; - case V4L2_PIX_FMT_P010: descr = "10-bit Y/UV 4:2:0"; break; - case V4L2_PIX_FMT_P012: descr = "12-bit Y/UV 4:2:0"; break; -+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break; -+ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/UV 4:2:2 (Packed)"; break; - case V4L2_PIX_FMT_NV12_4L4: descr = "Y/UV 4:2:0 (4x4 Linear)"; break; - case V4L2_PIX_FMT_NV12_16L16: descr = "Y/UV 4:2:0 (16x16 Linear)"; break; - case V4L2_PIX_FMT_NV12_32L32: descr = "Y/UV 4:2:0 (32x32 Linear)"; break; -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 111111111111..222222222222 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -650,6 +650,9 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit per component */ - #define V4L2_PIX_FMT_P012 v4l2_fourcc('P', '0', '1', '2') /* 24 Y/CbCr 4:2:0 12-bit per component */ - -+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/UV 4:2:0 10-bit packed */ -+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/UV 4:2:2 10-bit packed */ -+ - /* two non contiguous planes - one Y, one Cr + Cb interleaved */ - #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */ - #define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:36 +0000 -Subject: media: rkvdec: h264: Use bytesperline and buffer height to calculate - stride - -Use bytesperline and buffer height to calculate the strides configured. - -This does not really change anything other than ensuring the bytesperline -that is signaled to userspace matches what is configured in HW. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx, - dma_addr_t rlc_addr; - dma_addr_t refer_addr; - u32 rlc_len; -- u32 hor_virstride = 0; -- u32 ver_virstride = 0; -- u32 y_virstride = 0; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; - u32 yuv_virstride = 0; - u32 offset; - dma_addr_t dst_addr; -@@ -909,8 +909,8 @@ static void config_registers(struct rkvdec_ctx *ctx, - - f = &ctx->decoded_fmt; - dst_fmt = &f->fmt.pix_mp; -- hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8; -- ver_virstride = round_up(dst_fmt->height, 16); -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; - y_virstride = hor_virstride * ver_virstride; - - if (sps->chroma_format_idc == 0) --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:37 +0000 -Subject: media: rkvdec: Extract rkvdec_fill_decoded_pixfmt helper method - -This extract setting decoded pixfmt into a helper method, current code is -replaced with a call to the new helper method. - -The helper method is also called from a new function in next patch. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 29 +++++----- - 1 file changed, 15 insertions(+), 14 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -27,6 +27,17 @@ - #include "rkvdec.h" - #include "rkvdec-regs.h" - -+static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, -+ struct v4l2_pix_format_mplane *pix_mp) -+{ -+ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -+ pix_mp->width, pix_mp->height); -+ pix_mp->plane_fmt[0].sizeimage += 128 * -+ DIV_ROUND_UP(pix_mp->width, 16) * -+ DIV_ROUND_UP(pix_mp->height, 16); -+ pix_mp->field = V4L2_FIELD_NONE; -+} -+ - static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -@@ -192,13 +203,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) - - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); - f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; -- v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, -- ctx->coded_fmt_desc->decoded_fmts[0], -- ctx->coded_fmt.fmt.pix_mp.width, -- ctx->coded_fmt.fmt.pix_mp.height); -- f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 * -- DIV_ROUND_UP(f->fmt.pix_mp.width, 16) * -- DIV_ROUND_UP(f->fmt.pix_mp.height, 16); -+ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -+ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height; -+ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp); - } - - static int rkvdec_enum_framesizes(struct file *file, void *priv, -@@ -264,13 +271,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, - &pix_mp->height, - &coded_desc->frmsize); - -- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -- pix_mp->width, pix_mp->height); -- pix_mp->plane_fmt[0].sizeimage += -- 128 * -- DIV_ROUND_UP(pix_mp->width, 16) * -- DIV_ROUND_UP(pix_mp->height, 16); -- pix_mp->field = V4L2_FIELD_NONE; -+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp); - - return 0; - } --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:37 +0000 -Subject: media: rkvdec: Lock capture pixel format in s_ctrl and s_fmt - -Add an optional valid_fmt operation that should return the valid -pixelformat of CAPTURE buffers. - -This is used in next patch to ensure correct pixelformat is used for 10-bit -and 4:2:2 content. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 67 ++++++++-- - drivers/staging/media/rkvdec/rkvdec.h | 2 + - 2 files changed, 61 insertions(+), 8 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -38,19 +38,56 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - pix_mp->field = V4L2_FIELD_NONE; - } - -+static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc; -+ -+ if (coded_desc->ops->valid_fmt) -+ return coded_desc->ops->valid_fmt(ctx, ctrl); -+ -+ return ctx->valid_fmt; -+} -+ - static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); - const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; - -- if (desc->ops->try_ctrl) -- return desc->ops->try_ctrl(ctx, ctrl); -+ if (desc->ops->try_ctrl) { -+ int ret; -+ ret = desc->ops->try_ctrl(ctx, ctrl); -+ if (ret) -+ return ret; -+ } -+ -+ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) -+ /* Only current valid format */ -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) -+{ -+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -+ -+ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { -+ ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); -+ if (ctx->valid_fmt) { -+ struct v4l2_pix_format_mplane *pix_mp; -+ -+ pix_mp = &ctx->decoded_fmt.fmt.pix_mp; -+ pix_mp->pixelformat = ctx->valid_fmt; -+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp); -+ } -+ } - - return 0; - } - - static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { - .try_ctrl = rkvdec_try_ctrl, -+ .s_ctrl = rkvdec_s_ctrl, - }; - - static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { -@@ -201,6 +238,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) - { - struct v4l2_format *f = &ctx->decoded_fmt; - -+ ctx->valid_fmt = 0; - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); - f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; - f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -@@ -256,13 +294,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, - if (WARN_ON(!coded_desc)) - return -EINVAL; - -- for (i = 0; i < coded_desc->num_decoded_fmts; i++) { -- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) -- break; -- } -+ if (ctx->valid_fmt) { -+ pix_mp->pixelformat = ctx->valid_fmt; -+ } else { -+ for (i = 0; i < coded_desc->num_decoded_fmts; i++) { -+ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) -+ break; -+ } - -- if (i == coded_desc->num_decoded_fmts) -- pix_mp->pixelformat = coded_desc->decoded_fmts[0]; -+ if (i == coded_desc->num_decoded_fmts) -+ pix_mp->pixelformat = coded_desc->decoded_fmts[0]; -+ } - - /* Always apply the frmsize constraint of the coded end. */ - pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -@@ -326,6 +368,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, - return ret; - - ctx->decoded_fmt = *f; -+ ctx->valid_fmt = f->fmt.pix_mp.pixelformat; - return 0; - } - -@@ -429,6 +472,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, - if (WARN_ON(!ctx->coded_fmt_desc)) - return -EINVAL; - -+ if (ctx->valid_fmt) { -+ if (f->index) -+ return -EINVAL; -+ -+ f->pixelformat = ctx->valid_fmt; -+ return 0; -+ } -+ - if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) - return -EINVAL; - -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - struct rkvdec_coded_fmt_ops { - int (*adjust_fmt)(struct rkvdec_ctx *ctx, - struct v4l2_format *f); -+ u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); - int (*start)(struct rkvdec_ctx *ctx); - void (*stop)(struct rkvdec_ctx *ctx); - int (*run)(struct rkvdec_ctx *ctx); -@@ -101,6 +102,7 @@ struct rkvdec_ctx { - struct v4l2_fh fh; - struct v4l2_format coded_fmt; - struct v4l2_format decoded_fmt; -+ u32 valid_fmt; - const struct rkvdec_coded_fmt_desc *coded_fmt_desc; - struct v4l2_ctrl_handler ctrl_hdl; - struct rkvdec_dev *dev; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:37 +0000 -Subject: media: rkvdec: h264: Support High 10 and 4:2:2 profiles - -Add support and enable decoding of H264 High 10 and 4:2:2 profiles. - -Decoded CAPTURE buffer width is aligned to 64 pixels to accommodate HW -requirement on 10-bit format buffers. - -The new valid_fmt operation is implemented and return a valid pixelformat -for the provided SPS control. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 33 +++++++--- - drivers/staging/media/rkvdec/rkvdec.c | 19 ++++-- - 2 files changed, 37 insertions(+), 15 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -1031,19 +1031,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, - { - unsigned int width, height; - -- /* -- * TODO: The hardware supports 10-bit and 4:2:2 profiles, -- * but it's currently broken in the driver. -- * Reject them for now, until it's fixed. -- */ -- if (sps->chroma_format_idc > 1) -- /* Only 4:0:0 and 4:2:0 are supported */ -+ if (sps->chroma_format_idc > 2) -+ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */ - return -EINVAL; - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) - /* Luma and chroma bit depth mismatch */ - return -EINVAL; -- if (sps->bit_depth_luma_minus8 != 0) -- /* Only 8-bit is supported */ -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ - return -EINVAL; - - width = (sps->pic_width_in_mbs_minus1 + 1) * 16; -@@ -1064,6 +1059,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, - return 0; - } - -+static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; -+ -+ if (sps->bit_depth_luma_minus8 == 0) { -+ if (sps->chroma_format_idc == 2) -+ return V4L2_PIX_FMT_NV16; -+ else -+ return V4L2_PIX_FMT_NV12; -+ } else if (sps->bit_depth_luma_minus8 == 2) { -+ if (sps->chroma_format_idc == 2) -+ return V4L2_PIX_FMT_NV20; -+ else -+ return V4L2_PIX_FMT_NV15; -+ } -+ -+ return 0; -+} -+ - static int rkvdec_h264_start(struct rkvdec_ctx *ctx) - { - struct rkvdec_dev *rkvdec = ctx->dev; -@@ -1185,6 +1199,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) - - const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = { - .adjust_fmt = rkvdec_h264_adjust_fmt, -+ .valid_fmt = rkvdec_h264_valid_fmt, - .start = rkvdec_h264_start, - .stop = rkvdec_h264_stop, - .run = rkvdec_h264_run, -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - struct v4l2_pix_format_mplane *pix_mp) - { - v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -- pix_mp->width, pix_mp->height); -+ ALIGN(pix_mp->width, 64), pix_mp->height); - pix_mp->plane_fmt[0].sizeimage += 128 * - DIV_ROUND_UP(pix_mp->width, 16) * - DIV_ROUND_UP(pix_mp->height, 16); -@@ -136,8 +136,11 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), - }; - --static const u32 rkvdec_h264_vp9_decoded_fmts[] = { -+static const u32 rkvdec_h264_decoded_fmts[] = { - V4L2_PIX_FMT_NV12, -+ V4L2_PIX_FMT_NV15, -+ V4L2_PIX_FMT_NV16, -+ V4L2_PIX_FMT_NV20, - }; - - static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { -@@ -160,6 +163,10 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs), - }; - -+static const u32 rkvdec_vp9_decoded_fmts[] = { -+ V4L2_PIX_FMT_NV12, -+}; -+ - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, -@@ -173,8 +180,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - }, - .ctrls = &rkvdec_h264_ctrls, - .ops = &rkvdec_h264_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, - }, - { -@@ -189,8 +196,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - }, - .ctrls = &rkvdec_vp9_ctrls, - .ops = &rkvdec_vp9_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), -+ .decoded_fmts = rkvdec_vp9_decoded_fmts, - } - }; - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 27 Mar 2022 14:18:07 +0200 -Subject: media: rkvdec-h264: Don't hardcode SPS/PPS parameters - -Some SPS/PPS parameters are currently hardcoded in the driver -even though so do exist in the uapi which is stable by now. - -Use them instead of hardcoding them. - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 13 +++++----- - 1 file changed, 7 insertions(+), 6 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - - #define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) - /* write sps */ -- WRITE_PPS(0xf, SEQ_PARAMETER_SET_ID); -- WRITE_PPS(0xff, PROFILE_IDC); -- WRITE_PPS(1, CONSTRAINT_SET3_FLAG); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->profile_idc, PROFILE_IDC); -+ WRITE_PPS((sps->constraint_set_flags & 1 << 3) ? 1 : 0, CONSTRAINT_SET3_FLAG); - WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); - WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA); - WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA); -- WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS), -+ QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); - WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4); - WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES); - WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE); -@@ -688,8 +689,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - DIRECT_8X8_INFERENCE_FLAG); - - /* write pps */ -- WRITE_PPS(0xff, PIC_PARAMETER_SET_ID); -- WRITE_PPS(0x1f, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); - WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE), - ENTROPY_CODING_MODE_FLAG); - WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT), --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/general-v4l2-rkvdec-02-hevc.patch b/patch/kernel/rockchip64-6.14/general-v4l2-rkvdec-02-hevc.patch deleted file mode 100644 index 8bc6fe7..0000000 --- a/patch/kernel/rockchip64-6.14/general-v4l2-rkvdec-02-hevc.patch +++ /dev/null @@ -1,3238 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 15:17:45 +0000 -Subject: WIP: media: rkvdec: add HEVC backend - -NOTE: cabac table and scailing list code is copied 1:1 from mpp -TODO: fix lowdelay flag and rework the scaling list part - -Signed-off-by: Jonas Karlman -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/Makefile | 2 +- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 2572 ++++++++++ - drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + - drivers/staging/media/rkvdec/rkvdec.c | 73 +- - drivers/staging/media/rkvdec/rkvdec.h | 1 + - 5 files changed, 2647 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/Makefile -+++ b/drivers/staging/media/rkvdec/Makefile -@@ -1,3 +1,3 @@ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o - --rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o -+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -0,0 +1,2572 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder HEVC backend -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Jeffy Chen -+ */ -+ -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-regs.h" -+ -+/* Size in u8/u32 units. */ -+#define RKV_CABAC_TABLE_SIZE 27456 -+#define RKV_SCALING_LIST_SIZE 1360 -+#define RKV_PPS_SIZE (80 / 4) -+#define RKV_PPS_LEN 64 -+#define RKV_RPS_SIZE (32 / 4) -+#define RKV_RPS_LEN 600 -+ -+struct rkvdec_sps_pps_packet { -+ u32 info[RKV_PPS_SIZE]; -+}; -+ -+struct rkvdec_rps_packet { -+ u32 info[RKV_RPS_SIZE]; -+}; -+ -+struct rkvdec_ps_field { -+ u16 offset; -+ u8 len; -+}; -+ -+#define PS_FIELD(_offset, _len) \ -+ ((struct rkvdec_ps_field){ _offset, _len }) -+ -+/* SPS */ -+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4) -+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4) -+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2) -+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13) -+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13) -+#define BIT_DEPTH_LUMA PS_FIELD(36, 4) -+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4) -+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5) -+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2) -+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3) -+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3) -+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3) -+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1) -+#define AMP_ENABLED_FLAG PS_FIELD(66, 1) -+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1) -+#define PCM_ENABLED_FLAG PS_FIELD(68, 1) -+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4) -+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4) -+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1) -+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3) -+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3) -+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7) -+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1) -+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6) -+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1) -+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1) -+/* PPS */ -+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6) -+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4) -+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1) -+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1) -+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13) -+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1) -+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1) -+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4) -+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4) -+#define INIT_QP_MINUS26 PS_FIELD(163, 7) -+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1) -+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1) -+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1) -+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3) -+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5) -+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5) -+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1) -+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1) -+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1) -+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1) -+#define TILES_ENABLED_FLAG PS_FIELD(190, 1) -+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1) -+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1) -+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1) -+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1) -+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1) -+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4) -+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4) -+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1) -+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3) -+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1) -+#define NUM_TILE_COLUMNS PS_FIELD(212, 5) -+#define NUM_TILE_ROWS PS_FIELD(217, 5) -+#define COLUMN_WIDTH(i) PS_FIELD(256 + (i * 8), 8) -+#define ROW_HEIGHT(i) PS_FIELD(416 + (i * 8), 8) -+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32) -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_hevc_priv_tbl { -+ u8 cabac_table[RKV_CABAC_TABLE_SIZE]; -+ u8 scaling_list[RKV_SCALING_LIST_SIZE]; -+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; -+ struct rkvdec_rps_packet rps[RKV_RPS_LEN]; -+}; -+ -+struct rkvdec_hevc_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -+ int num_slices; -+}; -+ -+struct rkvdec_hevc_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+}; -+ -+// TODO: refactor scaling list code, was copied 1:1 from mpp -+ -+typedef struct ScalingList { -+ /* This is a little wasteful, since sizeID 0 only needs 8 coeffs, -+ * and size ID 3 only has 2 arrays, not 6. */ -+ u8 sl[4][6][64]; -+ u8 sl_dc[2][6]; -+} scalingList_t; -+ -+typedef struct ScalingFactor_Model { -+ u8 scalingfactor0[1248]; -+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ -+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/ -+ u8 reserverd[4]; /*16Bytes align*/ -+} scalingFactor_t; -+ -+#define SCALING_LIST_SIZE_NUM 4 -+ -+static void -+hal_record_scaling_list(scalingFactor_t *pScalingFactor_out, -+ scalingList_t *pScalingList) -+{ -+ int i; -+ u32 g_scalingListNum_model[SCALING_LIST_SIZE_NUM] = {6, 6, 6, 2}; // from C Model -+ u32 nIndex = 0; -+ u32 sizeId, matrixId, listId; -+ u8 *p = pScalingFactor_out->scalingfactor0; -+ u8 tmpBuf[8 * 8]; -+ -+ //output non-default scalingFactor Table (1248 BYTES) -+ for (sizeId = 0; sizeId < SCALING_LIST_SIZE_NUM; sizeId++) { -+ for (listId = 0; listId < g_scalingListNum_model[sizeId]; listId++) { -+ if (sizeId < 3) { -+ for (i = 0; i < (sizeId == 0 ? 16 : 64); i++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i]; -+ } -+ } else { -+ for (i = 0; i < 64; i ++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i]; -+ } -+ for (i = 0; i < 128; i ++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = 0; -+ } -+ } -+ } -+ } -+ //output non-default scalingFactor Table Rotation(96 Bytes) -+ nIndex = 0; -+ for (listId = 0; listId < g_scalingListNum_model[0]; listId++) { -+ u8 temp16[16] = {0}; -+ for (i = 0; i < 16; i ++) { -+ temp16[i] = (u8)pScalingList->sl[0][listId][i]; -+ } -+ for (i = 0; i < 4; i ++) { -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 4]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 8]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 12]; -+ } -+ } -+ //output non-default ScalingList_DC_Coeff (12 BYTES) -+ nIndex = 0; -+ for (listId = 0; listId < g_scalingListNum_model[2]; listId++) { //sizeId = 2 -+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[0][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC -+ } -+ for (listId = 0; listId < g_scalingListNum_model[3]; listId++) { //sizeId = 3 -+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[1][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC -+ pScalingFactor_out->scalingdc[nIndex++] = 0; -+ pScalingFactor_out->scalingdc[nIndex++] = 0; -+ } -+ -+ //align 16X address -+ nIndex = 0; -+ for (i = 0; i < 4; i ++) { -+ pScalingFactor_out->reserverd[nIndex++] = 0; -+ } -+ -+ //----------------------All above code show the normal store way in HM-------------------------- -+ //--------from now on, the scalingfactor0 is rotated 90', the scalingfactor1 is also rotated 90' -+ -+ //sizeId == 0 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + matrixId * 16; -+ -+ for (i = 0; i < 4; i++) { -+ tmpBuf[4 * 0 + i] = p[i * 4 + 0]; -+ tmpBuf[4 * 1 + i] = p[i * 4 + 1]; -+ tmpBuf[4 * 2 + i] = p[i * 4 + 2]; -+ tmpBuf[4 * 3 + i] = p[i * 4 + 3]; -+ } -+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8)); -+ } -+ //sizeId == 1 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ //sizeId == 2 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ //sizeId == 3 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + 6 * 64 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ -+ //sizeId == 0 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor1 + matrixId * 16; -+ -+ for (i = 0; i < 4; i++) { -+ tmpBuf[4 * 0 + i] = p[i * 4 + 0]; -+ tmpBuf[4 * 1 + i] = p[i * 4 + 1]; -+ tmpBuf[4 * 2 + i] = p[i * 4 + 2]; -+ tmpBuf[4 * 3 + i] = p[i * 4 + 3]; -+ } -+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8)); -+ } -+} -+ -+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { -+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x68, -+ 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x68, -+ 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, 0x60, 0x50, 0x58, -+ 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, 0x60, 0x60, -+ 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, -+ 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, -+ 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, -+ 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, -+ 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, -+ 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x0f, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, -+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, -+ 0x57, 0x5e, 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, -+ 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f, -+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, -+ 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, 0x57, 0x57, -+ 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x4f, -+ 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, 0x47, 0x67, 0x40, 0x40, -+ 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, 0x4e, 0x47, 0x47, 0x00, 0x0f, -+ 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64, -+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66, -+ 0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56, -+ 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e, -+ 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, -+ 0x45, 0x48, 0x20, 0x57, 0x66, 0x66, 0x56, 0x5e, 0x5e, 0x5d, 0x4e, 0x4e, 0x4e, 0x46, 0x56, 0x57, -+ 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f, -+ 0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x66, 0x10, 0x47, 0x66, 0x40, 0x40, -+ 0x4f, 0x4d, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x03, 0x27, 0x4d, 0x47, 0x46, 0x01, 0x0f, -+ 0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x34, 0x01, 0x26, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x0d, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x62, -+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x65, -+ 0x57, 0x5c, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5d, 0x5d, 0x4e, 0x56, -+ 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62, 0x5d, 0x5d, -+ 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62, -+ 0x44, 0x48, 0x20, 0x57, 0x65, 0x65, 0x56, 0x5d, 0x5d, 0x5c, 0x4e, 0x4d, 0x4e, 0x45, 0x56, 0x57, -+ 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f, -+ 0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x65, 0x10, 0x47, 0x65, 0x40, 0x40, -+ 0x4f, 0x4c, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x04, 0x27, 0x4c, 0x47, 0x45, 0x01, 0x0f, -+ 0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x33, 0x01, 0x25, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x0c, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0d, 0x40, 0x40, 0x40, 0x0d, 0x60, -+ 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x64, -+ 0x56, 0x5b, 0x01, 0x1d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5c, 0x5c, 0x4d, 0x55, -+ 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60, 0x5c, 0x5c, -+ 0x4d, 0x55, 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60, -+ 0x43, 0x49, 0x21, 0x56, 0x64, 0x64, 0x55, 0x5c, 0x5c, 0x5b, 0x4d, 0x4c, 0x4d, 0x44, 0x55, 0x56, -+ 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x4e, -+ 0x46, 0x1d, 0x1d, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x64, 0x11, 0x46, 0x64, 0x40, 0x40, -+ 0x4e, 0x4b, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x06, 0x27, 0x4b, 0x46, 0x44, 0x02, 0x0f, -+ 0x4e, 0x35, 0x1e, 0x1d, 0x4e, 0x31, 0x02, 0x24, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x0b, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5e, -+ 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x63, -+ 0x56, 0x59, 0x01, 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5b, 0x5b, 0x4c, 0x54, -+ 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e, 0x5b, 0x5b, -+ 0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e, -+ 0x41, 0x49, 0x21, 0x56, 0x63, 0x63, 0x54, 0x5b, 0x5b, 0x59, 0x4c, 0x4b, 0x4c, 0x43, 0x54, 0x56, -+ 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e, -+ 0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x63, 0x11, 0x46, 0x63, 0x40, 0x40, -+ 0x4e, 0x49, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x07, 0x27, 0x49, 0x46, 0x43, 0x03, 0x0f, -+ 0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x30, 0x03, 0x23, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x0a, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5c, -+ 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x62, -+ 0x56, 0x58, 0x01, 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5a, 0x5a, 0x4c, 0x54, -+ 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c, 0x5a, 0x5a, -+ 0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c, -+ 0x40, 0x49, 0x21, 0x56, 0x62, 0x62, 0x54, 0x5a, 0x5a, 0x58, 0x4c, 0x4a, 0x4c, 0x42, 0x54, 0x56, -+ 0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e, -+ 0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x62, 0x11, 0x46, 0x62, 0x40, 0x40, -+ 0x4e, 0x48, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x09, 0x27, 0x48, 0x46, 0x42, 0x03, 0x0f, -+ 0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x2e, 0x03, 0x22, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x09, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0b, 0x40, 0x40, 0x40, 0x0b, 0x5a, -+ 0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x61, -+ 0x55, 0x57, 0x02, 0x1b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x59, 0x59, 0x4b, 0x53, -+ 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x51, 0x61, 0x65, 0x63, 0x61, 0x5d, 0x49, 0x43, 0x5a, 0x59, 0x59, -+ 0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x51, 0x61, 0x65, 0x63, 0x61, 0x5d, 0x49, 0x43, 0x5a, -+ 0x00, 0x4a, 0x22, 0x55, 0x61, 0x61, 0x53, 0x59, 0x59, 0x57, 0x4b, 0x49, 0x4b, 0x41, 0x53, 0x55, -+ 0x33, 0x07, 0x53, 0x41, 0x53, 0x55, 0x33, 0x07, 0x53, 0x41, 0x53, 0x55, 0x33, 0x07, 0x53, 0x4d, -+ 0x45, 0x1b, 0x1b, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x61, 0x12, 0x45, 0x61, 0x40, 0x40, -+ 0x4d, 0x47, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0a, 0x27, 0x47, 0x45, 0x41, 0x04, 0x0f, -+ 0x4d, 0x33, 0x1d, 0x1b, 0x4d, 0x2d, 0x04, 0x21, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x08, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, 0x40, 0x40, 0x40, 0x0a, 0x59, -+ 0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x60, -+ 0x55, 0x56, 0x02, 0x1a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x58, 0x58, 0x4b, 0x53, -+ 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x50, 0x60, 0x65, 0x63, 0x60, 0x5b, 0x48, 0x43, 0x59, 0x58, 0x58, -+ 0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x50, 0x60, 0x65, 0x63, 0x60, 0x5b, 0x48, 0x43, 0x59, -+ 0x01, 0x4a, 0x22, 0x55, 0x60, 0x60, 0x53, 0x58, 0x58, 0x56, 0x4b, 0x48, 0x4b, 0x40, 0x53, 0x55, -+ 0x32, 0x07, 0x53, 0x40, 0x53, 0x55, 0x32, 0x07, 0x53, 0x40, 0x53, 0x55, 0x32, 0x07, 0x53, 0x4d, -+ 0x45, 0x1a, 0x1a, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x60, 0x12, 0x45, 0x60, 0x40, 0x40, -+ 0x4d, 0x46, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0c, 0x27, 0x46, 0x45, 0x40, 0x04, 0x0f, -+ 0x4d, 0x32, 0x1d, 0x1a, 0x4d, 0x2b, 0x04, 0x20, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x07, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, 0x40, 0x40, 0x40, 0x0a, 0x57, -+ 0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x5f, -+ 0x55, 0x54, 0x02, 0x1a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x57, 0x57, 0x4a, 0x52, -+ 0x4d, 0x07, 0x52, 0x62, 0x4d, 0x4f, 0x5f, 0x65, 0x62, 0x5f, 0x59, 0x47, 0x42, 0x57, 0x57, 0x57, -+ 0x4a, 0x52, 0x4d, 0x07, 0x52, 0x62, 0x4d, 0x4f, 0x5f, 0x65, 0x62, 0x5f, 0x59, 0x47, 0x42, 0x57, -+ 0x03, 0x4a, 0x22, 0x55, 0x5f, 0x5f, 0x52, 0x57, 0x57, 0x54, 0x4a, 0x47, 0x4a, 0x00, 0x52, 0x55, -+ 0x32, 0x07, 0x52, 0x00, 0x52, 0x55, 0x32, 0x07, 0x52, 0x00, 0x52, 0x55, 0x32, 0x07, 0x52, 0x4d, -+ 0x45, 0x1a, 0x1a, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x5f, 0x12, 0x45, 0x5f, 0x40, 0x40, -+ 0x4d, 0x44, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0e, 0x27, 0x44, 0x45, 0x00, 0x05, 0x0f, -+ 0x4d, 0x32, 0x1d, 0x1a, 0x4d, 0x29, 0x05, 0x1f, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x06, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x09, 0x40, 0x40, 0x40, 0x09, 0x55, -+ 0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5e, -+ 0x54, 0x53, 0x03, 0x19, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x56, 0x56, 0x49, 0x51, -+ 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4e, 0x5e, 0x64, 0x61, 0x5e, 0x58, 0x46, 0x41, 0x55, 0x56, 0x56, -+ 0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4e, 0x5e, 0x64, 0x61, 0x5e, 0x58, 0x46, 0x41, 0x55, -+ 0x04, 0x4b, 0x23, 0x54, 0x5e, 0x5e, 0x51, 0x56, 0x56, 0x53, 0x49, 0x46, 0x49, 0x01, 0x51, 0x54, -+ 0x31, 0x07, 0x51, 0x01, 0x51, 0x54, 0x31, 0x07, 0x51, 0x01, 0x51, 0x54, 0x31, 0x07, 0x51, 0x4c, -+ 0x44, 0x19, 0x19, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5e, 0x13, 0x44, 0x5e, 0x40, 0x40, -+ 0x4c, 0x43, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x0f, 0x27, 0x43, 0x44, 0x01, 0x06, 0x0f, -+ 0x4c, 0x31, 0x1c, 0x19, 0x4c, 0x28, 0x06, 0x1e, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x05, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x09, 0x40, 0x40, 0x40, 0x09, 0x53, -+ 0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5d, -+ 0x54, 0x52, 0x03, 0x19, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x55, 0x55, 0x49, 0x51, -+ 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4d, 0x5d, 0x64, 0x61, 0x5d, 0x56, 0x45, 0x41, 0x53, 0x55, 0x55, -+ 0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4d, 0x5d, 0x64, 0x61, 0x5d, 0x56, 0x45, 0x41, 0x53, -+ 0x05, 0x4b, 0x23, 0x54, 0x5d, 0x5d, 0x51, 0x55, 0x55, 0x52, 0x49, 0x45, 0x49, 0x02, 0x51, 0x54, -+ 0x31, 0x07, 0x51, 0x02, 0x51, 0x54, 0x31, 0x07, 0x51, 0x02, 0x51, 0x54, 0x31, 0x07, 0x51, 0x4c, -+ 0x44, 0x19, 0x19, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5d, 0x13, 0x44, 0x5d, 0x40, 0x40, -+ 0x4c, 0x42, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x11, 0x27, 0x42, 0x44, 0x02, 0x06, 0x0f, -+ 0x4c, 0x31, 0x1c, 0x19, 0x4c, 0x26, 0x06, 0x1d, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x04, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x08, 0x40, 0x40, 0x40, 0x08, 0x51, -+ 0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5c, -+ 0x54, 0x51, 0x03, 0x18, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x54, 0x54, 0x48, 0x50, -+ 0x4c, 0x07, 0x50, 0x60, 0x4c, 0x4c, 0x5c, 0x64, 0x60, 0x5c, 0x55, 0x44, 0x40, 0x51, 0x54, 0x54, -+ 0x48, 0x50, 0x4c, 0x07, 0x50, 0x60, 0x4c, 0x4c, 0x5c, 0x64, 0x60, 0x5c, 0x55, 0x44, 0x40, 0x51, -+ 0x06, 0x4b, 0x23, 0x54, 0x5c, 0x5c, 0x50, 0x54, 0x54, 0x51, 0x48, 0x44, 0x48, 0x03, 0x50, 0x54, -+ 0x30, 0x07, 0x50, 0x03, 0x50, 0x54, 0x30, 0x07, 0x50, 0x03, 0x50, 0x54, 0x30, 0x07, 0x50, 0x4c, -+ 0x44, 0x18, 0x18, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5c, 0x13, 0x44, 0x5c, 0x40, 0x40, -+ 0x4c, 0x41, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x12, 0x27, 0x41, 0x44, 0x03, 0x07, 0x0f, -+ 0x4c, 0x30, 0x1c, 0x18, 0x4c, 0x25, 0x07, 0x1c, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x03, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x07, 0x4f, -+ 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x5b, -+ 0x53, 0x4f, 0x04, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x53, 0x53, 0x47, 0x4f, -+ 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4b, 0x5b, 0x63, 0x5f, 0x5b, 0x53, 0x43, 0x00, 0x4f, 0x53, 0x53, -+ 0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4b, 0x5b, 0x63, 0x5f, 0x5b, 0x53, 0x43, 0x00, 0x4f, -+ 0x08, 0x4c, 0x24, 0x53, 0x5b, 0x5b, 0x4f, 0x53, 0x53, 0x4f, 0x47, 0x43, 0x47, 0x04, 0x4f, 0x53, -+ 0x2f, 0x07, 0x4f, 0x04, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x04, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x4b, -+ 0x43, 0x17, 0x17, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x5b, 0x14, 0x43, 0x5b, 0x40, 0x40, -+ 0x4b, 0x00, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x14, 0x27, 0x00, 0x43, 0x04, 0x08, 0x0f, -+ 0x4b, 0x2f, 0x1b, 0x17, 0x4b, 0x23, 0x08, 0x1b, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x02, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x07, 0x4d, -+ 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x5a, -+ 0x53, 0x4e, 0x04, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x52, 0x52, 0x47, 0x4f, -+ 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4a, 0x5a, 0x63, 0x5f, 0x5a, 0x52, 0x42, 0x00, 0x4d, 0x52, 0x52, -+ 0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4a, 0x5a, 0x63, 0x5f, 0x5a, 0x52, 0x42, 0x00, 0x4d, -+ 0x09, 0x4c, 0x24, 0x53, 0x5a, 0x5a, 0x4f, 0x52, 0x52, 0x4e, 0x47, 0x42, 0x47, 0x05, 0x4f, 0x53, -+ 0x2f, 0x07, 0x4f, 0x05, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x05, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x4b, -+ 0x43, 0x17, 0x17, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x5a, 0x14, 0x43, 0x5a, 0x40, 0x40, -+ 0x4b, 0x01, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x15, 0x27, 0x01, 0x43, 0x05, 0x08, 0x0f, -+ 0x4b, 0x2f, 0x1b, 0x17, 0x4b, 0x22, 0x08, 0x1a, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x01, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x40, 0x40, 0x40, 0x06, 0x4b, -+ 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x59, -+ 0x53, 0x4d, 0x04, 0x16, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x51, 0x51, 0x46, 0x4e, -+ 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x50, 0x41, 0x01, 0x4b, 0x51, 0x51, -+ 0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x50, 0x41, 0x01, 0x4b, -+ 0x0a, 0x4c, 0x24, 0x53, 0x59, 0x59, 0x4e, 0x51, 0x51, 0x4d, 0x46, 0x41, 0x46, 0x06, 0x4e, 0x53, -+ 0x2e, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, 0x4b, -+ 0x43, 0x16, 0x16, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x59, 0x14, 0x43, 0x59, 0x40, 0x40, -+ 0x4b, 0x02, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x17, 0x27, 0x02, 0x43, 0x06, 0x09, 0x0f, -+ 0x4b, 0x2e, 0x1b, 0x16, 0x4b, 0x20, 0x09, 0x19, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x00, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x05, 0x4a, -+ 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x59, -+ 0x53, 0x4c, 0x04, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x51, 0x51, 0x46, 0x4e, -+ 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x4f, 0x41, 0x01, 0x4a, 0x51, 0x51, -+ 0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x4f, 0x41, 0x01, 0x4a, -+ 0x0b, 0x4d, 0x24, 0x53, 0x59, 0x59, 0x4e, 0x51, 0x51, 0x4c, 0x46, 0x41, 0x46, 0x06, 0x4e, 0x53, -+ 0x2d, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2d, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2d, 0x07, 0x4e, 0x4b, -+ 0x43, 0x15, 0x15, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x59, 0x14, 0x43, 0x59, 0x40, 0x40, -+ 0x4b, 0x03, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x18, 0x27, 0x03, 0x43, 0x06, 0x09, 0x0f, -+ 0x4b, 0x2d, 0x1a, 0x15, 0x4b, 0x1e, 0x09, 0x18, 0x04, 0x07, 0x14, 0x12, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x00, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x05, 0x48, -+ 0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x58, -+ 0x52, 0x4a, 0x05, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x50, 0x50, 0x45, 0x4d, -+ 0x4a, 0x07, 0x4d, 0x5d, 0x4a, 0x48, 0x58, 0x62, 0x5d, 0x58, 0x4d, 0x40, 0x02, 0x48, 0x50, 0x50, -+ 0x45, 0x4d, 0x4a, 0x07, 0x4d, 0x5d, 0x4a, 0x48, 0x58, 0x62, 0x5d, 0x58, 0x4d, 0x40, 0x02, 0x48, -+ 0x0d, 0x4d, 0x25, 0x52, 0x58, 0x58, 0x4d, 0x50, 0x50, 0x4a, 0x45, 0x40, 0x45, 0x07, 0x4d, 0x52, -+ 0x2d, 0x07, 0x4d, 0x07, 0x4d, 0x52, 0x2d, 0x07, 0x4d, 0x07, 0x4d, 0x52, 0x2d, 0x07, 0x4d, 0x4a, -+ 0x42, 0x15, 0x15, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x58, 0x15, 0x42, 0x58, 0x40, 0x40, -+ 0x4a, 0x05, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1a, 0x27, 0x05, 0x42, 0x07, 0x0a, 0x0f, -+ 0x4a, 0x2d, 0x1a, 0x15, 0x4a, 0x1d, 0x0a, 0x18, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x40, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x40, 0x40, 0x40, 0x04, 0x46, -+ 0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x57, -+ 0x52, 0x49, 0x05, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4f, 0x4f, 0x44, 0x4c, -+ 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x47, 0x57, 0x62, 0x5c, 0x57, 0x4b, 0x00, 0x03, 0x46, 0x4f, 0x4f, -+ 0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x47, 0x57, 0x62, 0x5c, 0x57, 0x4b, 0x00, 0x03, 0x46, -+ 0x0e, 0x4d, 0x25, 0x52, 0x57, 0x57, 0x4c, 0x4f, 0x4f, 0x49, 0x44, 0x00, 0x44, 0x08, 0x4c, 0x52, -+ 0x2c, 0x07, 0x4c, 0x08, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x08, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x4a, -+ 0x42, 0x14, 0x14, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x57, 0x15, 0x42, 0x57, 0x40, 0x40, -+ 0x4a, 0x06, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1c, 0x27, 0x06, 0x42, 0x08, 0x0b, 0x0f, -+ 0x4a, 0x2c, 0x1a, 0x14, 0x4a, 0x1b, 0x0b, 0x17, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x41, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x40, 0x40, 0x40, 0x04, 0x44, -+ 0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x56, -+ 0x52, 0x48, 0x05, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4e, 0x4e, 0x44, 0x4c, -+ 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x46, 0x56, 0x62, 0x5c, 0x56, 0x4a, 0x01, 0x03, 0x44, 0x4e, 0x4e, -+ 0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x46, 0x56, 0x62, 0x5c, 0x56, 0x4a, 0x01, 0x03, 0x44, -+ 0x0f, 0x4d, 0x25, 0x52, 0x56, 0x56, 0x4c, 0x4e, 0x4e, 0x48, 0x44, 0x01, 0x44, 0x09, 0x4c, 0x52, -+ 0x2c, 0x07, 0x4c, 0x09, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x09, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x4a, -+ 0x42, 0x14, 0x14, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x56, 0x15, 0x42, 0x56, 0x40, 0x40, -+ 0x4a, 0x07, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1d, 0x27, 0x07, 0x42, 0x09, 0x0b, 0x0f, -+ 0x4a, 0x2c, 0x1a, 0x14, 0x4a, 0x1a, 0x0b, 0x16, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x42, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x40, 0x40, 0x40, 0x03, 0x42, -+ 0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x55, -+ 0x51, 0x47, 0x06, 0x13, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4d, 0x4d, 0x43, 0x4b, -+ 0x49, 0x07, 0x4b, 0x5b, 0x49, 0x45, 0x55, 0x61, 0x5b, 0x55, 0x48, 0x02, 0x04, 0x42, 0x4d, 0x4d, -+ 0x43, 0x4b, 0x49, 0x07, 0x4b, 0x5b, 0x49, 0x45, 0x55, 0x61, 0x5b, 0x55, 0x48, 0x02, 0x04, 0x42, -+ 0x10, 0x4e, 0x26, 0x51, 0x55, 0x55, 0x4b, 0x4d, 0x4d, 0x47, 0x43, 0x02, 0x43, 0x0a, 0x4b, 0x51, -+ 0x2b, 0x07, 0x4b, 0x0a, 0x4b, 0x51, 0x2b, 0x07, 0x4b, 0x0a, 0x4b, 0x51, 0x2b, 0x07, 0x4b, 0x49, -+ 0x41, 0x13, 0x13, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x55, 0x16, 0x41, 0x55, 0x40, 0x40, -+ 0x49, 0x08, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x1f, 0x27, 0x08, 0x41, 0x0a, 0x0c, 0x0f, -+ 0x49, 0x2b, 0x19, 0x13, 0x49, 0x18, 0x0c, 0x15, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x43, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x40, 0x40, 0x40, 0x02, 0x40, -+ 0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x54, -+ 0x51, 0x45, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4c, 0x4c, 0x42, 0x4a, -+ 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x44, 0x54, 0x61, 0x5a, 0x54, 0x47, 0x03, 0x05, 0x40, 0x4c, 0x4c, -+ 0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x44, 0x54, 0x61, 0x5a, 0x54, 0x47, 0x03, 0x05, 0x40, -+ 0x12, 0x4e, 0x26, 0x51, 0x54, 0x54, 0x4a, 0x4c, 0x4c, 0x45, 0x42, 0x03, 0x42, 0x0b, 0x4a, 0x51, -+ 0x2a, 0x07, 0x4a, 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x49, -+ 0x41, 0x12, 0x12, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x54, 0x16, 0x41, 0x54, 0x40, 0x40, -+ 0x49, 0x0a, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x20, 0x27, 0x0a, 0x41, 0x0b, 0x0d, 0x0f, -+ 0x49, 0x2a, 0x19, 0x12, 0x49, 0x17, 0x0d, 0x14, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x44, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x40, 0x40, 0x40, 0x02, 0x01, -+ 0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x53, -+ 0x51, 0x44, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4b, 0x42, 0x4a, -+ 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x43, 0x53, 0x61, 0x5a, 0x53, 0x45, 0x04, 0x05, 0x01, 0x4b, 0x4b, -+ 0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x43, 0x53, 0x61, 0x5a, 0x53, 0x45, 0x04, 0x05, 0x01, -+ 0x13, 0x4e, 0x26, 0x51, 0x53, 0x53, 0x4a, 0x4b, 0x4b, 0x44, 0x42, 0x04, 0x42, 0x0c, 0x4a, 0x51, -+ 0x2a, 0x07, 0x4a, 0x0c, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x0c, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x49, -+ 0x41, 0x12, 0x12, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x53, 0x16, 0x41, 0x53, 0x40, 0x40, -+ 0x49, 0x0b, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x22, 0x27, 0x0b, 0x41, 0x0c, 0x0d, 0x0f, -+ 0x49, 0x2a, 0x19, 0x12, 0x49, 0x15, 0x0d, 0x13, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x45, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x40, 0x40, 0x40, 0x01, 0x03, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x52, -+ 0x50, 0x43, 0x07, 0x11, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x4a, 0x41, 0x49, -+ 0x48, 0x07, 0x49, 0x59, 0x48, 0x42, 0x52, 0x60, 0x59, 0x52, 0x44, 0x05, 0x06, 0x03, 0x4a, 0x4a, -+ 0x41, 0x49, 0x48, 0x07, 0x49, 0x59, 0x48, 0x42, 0x52, 0x60, 0x59, 0x52, 0x44, 0x05, 0x06, 0x03, -+ 0x14, 0x4f, 0x27, 0x50, 0x52, 0x52, 0x49, 0x4a, 0x4a, 0x43, 0x41, 0x05, 0x41, 0x0d, 0x49, 0x50, -+ 0x29, 0x07, 0x49, 0x0d, 0x49, 0x50, 0x29, 0x07, 0x49, 0x0d, 0x49, 0x50, 0x29, 0x07, 0x49, 0x48, -+ 0x40, 0x11, 0x11, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x52, 0x17, 0x40, 0x52, 0x40, 0x40, -+ 0x48, 0x0c, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x23, 0x27, 0x0c, 0x40, 0x0d, 0x0e, 0x0f, -+ 0x48, 0x29, 0x18, 0x11, 0x48, 0x14, 0x0e, 0x12, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x46, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, 0x40, 0x40, 0x00, 0x04, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x51, -+ 0x50, 0x42, 0x07, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x41, 0x49, -+ 0x48, 0x07, 0x49, 0x59, 0x48, 0x41, 0x51, 0x60, 0x59, 0x51, 0x42, 0x06, 0x06, 0x04, 0x49, 0x49, -+ 0x41, 0x49, 0x48, 0x07, 0x49, 0x59, 0x48, 0x41, 0x51, 0x60, 0x59, 0x51, 0x42, 0x06, 0x06, 0x04, -+ 0x15, 0x4f, 0x27, 0x50, 0x51, 0x51, 0x49, 0x49, 0x49, 0x42, 0x41, 0x06, 0x41, 0x0e, 0x49, 0x50, -+ 0x28, 0x07, 0x49, 0x0e, 0x49, 0x50, 0x28, 0x07, 0x49, 0x0e, 0x49, 0x50, 0x28, 0x07, 0x49, 0x48, -+ 0x40, 0x10, 0x10, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x51, 0x17, 0x40, 0x51, 0x40, 0x40, -+ 0x48, 0x0d, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x25, 0x27, 0x0d, 0x40, 0x0e, 0x0e, 0x0f, -+ 0x48, 0x28, 0x18, 0x10, 0x48, 0x12, 0x0e, 0x11, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x47, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, 0x40, 0x40, 0x00, 0x06, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x50, -+ 0x50, 0x40, 0x07, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48, -+ 0x48, 0x07, 0x48, 0x58, 0x48, 0x40, 0x50, 0x60, 0x58, 0x50, 0x40, 0x07, 0x07, 0x06, 0x48, 0x48, -+ 0x40, 0x48, 0x48, 0x07, 0x48, 0x58, 0x48, 0x40, 0x50, 0x60, 0x58, 0x50, 0x40, 0x07, 0x07, 0x06, -+ 0x17, 0x4f, 0x27, 0x50, 0x50, 0x50, 0x48, 0x48, 0x48, 0x40, 0x40, 0x07, 0x40, 0x0f, 0x48, 0x50, -+ 0x28, 0x07, 0x48, 0x0f, 0x48, 0x50, 0x28, 0x07, 0x48, 0x0f, 0x48, 0x50, 0x28, 0x07, 0x48, 0x48, -+ 0x40, 0x10, 0x10, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x50, 0x17, 0x40, 0x50, 0x40, 0x40, -+ 0x48, 0x0f, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x27, 0x27, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, -+ 0x48, 0x28, 0x18, 0x10, 0x48, 0x10, 0x0f, 0x10, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x48, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x08, -+ 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4f, -+ 0x4f, 0x00, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47, -+ 0x47, 0x07, 0x47, 0x57, 0x47, 0x00, 0x4f, 0x5f, 0x57, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47, -+ 0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x00, 0x4f, 0x5f, 0x57, 0x4f, 0x00, 0x08, 0x08, 0x08, -+ 0x18, 0x50, 0x28, 0x4f, 0x4f, 0x4f, 0x47, 0x47, 0x47, 0x00, 0x00, 0x08, 0x00, 0x10, 0x47, 0x4f, -+ 0x27, 0x07, 0x47, 0x10, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x10, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x47, -+ 0x00, 0x0f, 0x0f, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4f, 0x18, 0x00, 0x4f, 0x40, 0x40, -+ 0x47, 0x10, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x28, 0x27, 0x10, 0x00, 0x10, 0x10, 0x0f, -+ 0x47, 0x27, 0x17, 0x0f, 0x47, 0x0f, 0x10, 0x0f, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x49, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, -+ 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4e, -+ 0x4f, 0x01, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x46, 0x00, 0x47, -+ 0x47, 0x07, 0x47, 0x57, 0x47, 0x01, 0x4e, 0x5f, 0x57, 0x4e, 0x02, 0x09, 0x08, 0x0a, 0x46, 0x46, -+ 0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x01, 0x4e, 0x5f, 0x57, 0x4e, 0x02, 0x09, 0x08, 0x0a, -+ 0x19, 0x50, 0x28, 0x4f, 0x4e, 0x4e, 0x47, 0x46, 0x46, 0x01, 0x00, 0x09, 0x00, 0x11, 0x47, 0x4f, -+ 0x27, 0x07, 0x47, 0x11, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x11, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x47, -+ 0x00, 0x0f, 0x0f, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4e, 0x18, 0x00, 0x4e, 0x40, 0x40, -+ 0x47, 0x11, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x2a, 0x27, 0x11, 0x00, 0x11, 0x10, 0x0f, -+ 0x47, 0x27, 0x17, 0x0f, 0x47, 0x0d, 0x10, 0x0e, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4a, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x40, 0x40, 0x40, 0x41, 0x0c, -+ 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4d, -+ 0x4f, 0x02, 0x08, 0x0e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x45, 0x45, 0x01, 0x46, -+ 0x47, 0x07, 0x46, 0x56, 0x47, 0x02, 0x4d, 0x5f, 0x56, 0x4d, 0x03, 0x0a, 0x09, 0x0c, 0x45, 0x45, -+ 0x01, 0x46, 0x47, 0x07, 0x46, 0x56, 0x47, 0x02, 0x4d, 0x5f, 0x56, 0x4d, 0x03, 0x0a, 0x09, 0x0c, -+ 0x1a, 0x50, 0x28, 0x4f, 0x4d, 0x4d, 0x46, 0x45, 0x45, 0x02, 0x01, 0x0a, 0x01, 0x12, 0x46, 0x4f, -+ 0x26, 0x07, 0x46, 0x12, 0x46, 0x4f, 0x26, 0x07, 0x46, 0x12, 0x46, 0x4f, 0x26, 0x07, 0x46, 0x47, -+ 0x00, 0x0e, 0x0e, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4d, 0x18, 0x00, 0x4d, 0x40, 0x40, -+ 0x47, 0x12, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x2b, 0x27, 0x12, 0x00, 0x12, 0x11, 0x0f, -+ 0x47, 0x26, 0x17, 0x0e, 0x47, 0x0c, 0x11, 0x0d, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4b, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x40, 0x40, 0x40, 0x42, 0x0e, -+ 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4c, -+ 0x4e, 0x04, 0x09, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x44, 0x02, 0x45, -+ 0x46, 0x07, 0x45, 0x55, 0x46, 0x03, 0x4c, 0x5e, 0x55, 0x4c, 0x05, 0x0b, 0x0a, 0x0e, 0x44, 0x44, -+ 0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x03, 0x4c, 0x5e, 0x55, 0x4c, 0x05, 0x0b, 0x0a, 0x0e, -+ 0x1c, 0x51, 0x29, 0x4e, 0x4c, 0x4c, 0x45, 0x44, 0x44, 0x04, 0x02, 0x0b, 0x02, 0x13, 0x45, 0x4e, -+ 0x25, 0x07, 0x45, 0x13, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x13, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x46, -+ 0x01, 0x0d, 0x0d, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4c, 0x19, 0x01, 0x4c, 0x40, 0x40, -+ 0x46, 0x14, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x2d, 0x27, 0x14, 0x01, 0x13, 0x12, 0x0f, -+ 0x46, 0x25, 0x16, 0x0d, 0x46, 0x0a, 0x12, 0x0c, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4c, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x40, 0x40, 0x40, 0x42, 0x10, -+ 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4b, -+ 0x4e, 0x05, 0x09, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x43, 0x43, 0x02, 0x45, -+ 0x46, 0x07, 0x45, 0x55, 0x46, 0x04, 0x4b, 0x5e, 0x55, 0x4b, 0x06, 0x0c, 0x0a, 0x10, 0x43, 0x43, -+ 0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x04, 0x4b, 0x5e, 0x55, 0x4b, 0x06, 0x0c, 0x0a, 0x10, -+ 0x1d, 0x51, 0x29, 0x4e, 0x4b, 0x4b, 0x45, 0x43, 0x43, 0x05, 0x02, 0x0c, 0x02, 0x14, 0x45, 0x4e, -+ 0x25, 0x07, 0x45, 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x46, -+ 0x01, 0x0d, 0x0d, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4b, 0x19, 0x01, 0x4b, 0x40, 0x40, -+ 0x46, 0x15, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x2e, 0x27, 0x15, 0x01, 0x14, 0x12, 0x0f, -+ 0x46, 0x25, 0x16, 0x0d, 0x46, 0x09, 0x12, 0x0b, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4d, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x40, 0x40, 0x40, 0x43, 0x12, -+ 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4a, -+ 0x4e, 0x06, 0x09, 0x0c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x42, 0x42, 0x03, 0x44, -+ 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x08, 0x0d, 0x0b, 0x12, 0x42, 0x42, -+ 0x03, 0x44, 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x08, 0x0d, 0x0b, 0x12, -+ 0x1e, 0x51, 0x29, 0x4e, 0x4a, 0x4a, 0x44, 0x42, 0x42, 0x06, 0x03, 0x0d, 0x03, 0x15, 0x44, 0x4e, -+ 0x24, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x24, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x24, 0x07, 0x44, 0x46, -+ 0x01, 0x0c, 0x0c, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4a, 0x19, 0x01, 0x4a, 0x40, 0x40, -+ 0x46, 0x16, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x30, 0x27, 0x16, 0x01, 0x15, 0x13, 0x0f, -+ 0x46, 0x24, 0x16, 0x0c, 0x46, 0x07, 0x13, 0x0a, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4e, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x40, 0x40, 0x40, 0x44, 0x13, -+ 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4a, -+ 0x4e, 0x07, 0x09, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x42, 0x42, 0x03, 0x44, -+ 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x09, 0x0d, 0x0b, 0x13, 0x42, 0x42, -+ 0x03, 0x44, 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x09, 0x0d, 0x0b, 0x13, -+ 0x1f, 0x52, 0x29, 0x4e, 0x4a, 0x4a, 0x44, 0x42, 0x42, 0x07, 0x03, 0x0d, 0x03, 0x15, 0x44, 0x4e, -+ 0x23, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x23, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x23, 0x07, 0x44, 0x46, -+ 0x01, 0x0b, 0x0b, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4a, 0x19, 0x01, 0x4a, 0x40, 0x40, -+ 0x46, 0x17, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x31, 0x27, 0x17, 0x01, 0x15, 0x13, 0x0f, -+ 0x46, 0x23, 0x15, 0x0b, 0x46, 0x05, 0x13, 0x09, 0x09, 0x07, 0x19, 0x0d, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4e, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x40, 0x40, 0x40, 0x44, 0x15, -+ 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x49, -+ 0x4d, 0x09, 0x0a, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x41, 0x41, 0x04, 0x43, -+ 0x45, 0x07, 0x43, 0x53, 0x45, 0x06, 0x49, 0x5d, 0x53, 0x49, 0x0b, 0x0e, 0x0c, 0x15, 0x41, 0x41, -+ 0x04, 0x43, 0x45, 0x07, 0x43, 0x53, 0x45, 0x06, 0x49, 0x5d, 0x53, 0x49, 0x0b, 0x0e, 0x0c, 0x15, -+ 0x21, 0x52, 0x2a, 0x4d, 0x49, 0x49, 0x43, 0x41, 0x41, 0x09, 0x04, 0x0e, 0x04, 0x16, 0x43, 0x4d, -+ 0x23, 0x07, 0x43, 0x16, 0x43, 0x4d, 0x23, 0x07, 0x43, 0x16, 0x43, 0x4d, 0x23, 0x07, 0x43, 0x45, -+ 0x02, 0x0b, 0x0b, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x49, 0x1a, 0x02, 0x49, 0x40, 0x40, -+ 0x45, 0x19, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x33, 0x27, 0x19, 0x02, 0x16, 0x14, 0x0f, -+ 0x45, 0x23, 0x15, 0x0b, 0x45, 0x04, 0x14, 0x09, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4f, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x40, 0x40, 0x40, 0x45, 0x17, -+ 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x48, -+ 0x4d, 0x0a, 0x0a, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x40, 0x40, 0x05, 0x42, -+ 0x45, 0x07, 0x42, 0x52, 0x45, 0x07, 0x48, 0x5d, 0x52, 0x48, 0x0d, 0x0f, 0x0d, 0x17, 0x40, 0x40, -+ 0x05, 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x07, 0x48, 0x5d, 0x52, 0x48, 0x0d, 0x0f, 0x0d, 0x17, -+ 0x22, 0x52, 0x2a, 0x4d, 0x48, 0x48, 0x42, 0x40, 0x40, 0x0a, 0x05, 0x0f, 0x05, 0x17, 0x42, 0x4d, -+ 0x22, 0x07, 0x42, 0x17, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x17, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x45, -+ 0x02, 0x0a, 0x0a, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x48, 0x1a, 0x02, 0x48, 0x40, 0x40, -+ 0x45, 0x1a, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x35, 0x27, 0x1a, 0x02, 0x17, 0x15, 0x0f, -+ 0x45, 0x22, 0x15, 0x0a, 0x45, 0x02, 0x15, 0x08, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x50, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x40, 0x40, 0x40, 0x45, 0x19, -+ 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x47, -+ 0x4d, 0x0b, 0x0a, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x00, 0x00, 0x05, 0x42, -+ 0x45, 0x07, 0x42, 0x52, 0x45, 0x08, 0x47, 0x5d, 0x52, 0x47, 0x0e, 0x10, 0x0d, 0x19, 0x00, 0x00, -+ 0x05, 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x08, 0x47, 0x5d, 0x52, 0x47, 0x0e, 0x10, 0x0d, 0x19, -+ 0x23, 0x52, 0x2a, 0x4d, 0x47, 0x47, 0x42, 0x00, 0x00, 0x0b, 0x05, 0x10, 0x05, 0x18, 0x42, 0x4d, -+ 0x22, 0x07, 0x42, 0x18, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x18, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x45, -+ 0x02, 0x0a, 0x0a, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x47, 0x1a, 0x02, 0x47, 0x40, 0x40, -+ 0x45, 0x1b, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x36, 0x27, 0x1b, 0x02, 0x18, 0x15, 0x0f, -+ 0x45, 0x22, 0x15, 0x0a, 0x45, 0x01, 0x15, 0x07, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x51, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x40, 0x40, 0x40, 0x46, 0x1b, -+ 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x46, -+ 0x4c, 0x0c, 0x0b, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x01, 0x01, 0x06, 0x41, -+ 0x44, 0x07, 0x41, 0x51, 0x44, 0x09, 0x46, 0x5c, 0x51, 0x46, 0x10, 0x11, 0x0e, 0x1b, 0x01, 0x01, -+ 0x06, 0x41, 0x44, 0x07, 0x41, 0x51, 0x44, 0x09, 0x46, 0x5c, 0x51, 0x46, 0x10, 0x11, 0x0e, 0x1b, -+ 0x24, 0x53, 0x2b, 0x4c, 0x46, 0x46, 0x41, 0x01, 0x01, 0x0c, 0x06, 0x11, 0x06, 0x19, 0x41, 0x4c, -+ 0x21, 0x07, 0x41, 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, 0x44, -+ 0x03, 0x09, 0x09, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x46, 0x1b, 0x03, 0x46, 0x40, 0x40, -+ 0x44, 0x1c, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x38, 0x27, 0x1c, 0x03, 0x19, 0x16, 0x0f, -+ 0x44, 0x21, 0x14, 0x09, 0x44, 0x40, 0x16, 0x06, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x52, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x40, 0x40, 0x40, 0x47, 0x1d, -+ 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x45, -+ 0x4c, 0x0e, 0x0b, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x02, 0x02, 0x07, 0x40, -+ 0x44, 0x07, 0x40, 0x50, 0x44, 0x0a, 0x45, 0x5c, 0x50, 0x45, 0x11, 0x12, 0x0f, 0x1d, 0x02, 0x02, -+ 0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0a, 0x45, 0x5c, 0x50, 0x45, 0x11, 0x12, 0x0f, 0x1d, -+ 0x26, 0x53, 0x2b, 0x4c, 0x45, 0x45, 0x40, 0x02, 0x02, 0x0e, 0x07, 0x12, 0x07, 0x1a, 0x40, 0x4c, -+ 0x20, 0x07, 0x40, 0x1a, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1a, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x44, -+ 0x03, 0x08, 0x08, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x45, 0x1b, 0x03, 0x45, 0x40, 0x40, -+ 0x44, 0x1e, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x39, 0x27, 0x1e, 0x03, 0x1a, 0x17, 0x0f, -+ 0x44, 0x20, 0x14, 0x08, 0x44, 0x41, 0x17, 0x05, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x53, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x40, 0x40, 0x40, 0x47, 0x1f, -+ 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x44, -+ 0x4c, 0x0f, 0x0b, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x03, 0x03, 0x07, 0x40, -+ 0x44, 0x07, 0x40, 0x50, 0x44, 0x0b, 0x44, 0x5c, 0x50, 0x44, 0x13, 0x13, 0x0f, 0x1f, 0x03, 0x03, -+ 0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0b, 0x44, 0x5c, 0x50, 0x44, 0x13, 0x13, 0x0f, 0x1f, -+ 0x27, 0x53, 0x2b, 0x4c, 0x44, 0x44, 0x40, 0x03, 0x03, 0x0f, 0x07, 0x13, 0x07, 0x1b, 0x40, 0x4c, -+ 0x20, 0x07, 0x40, 0x1b, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1b, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x44, -+ 0x03, 0x08, 0x08, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x44, 0x1b, 0x03, 0x44, 0x40, 0x40, -+ 0x44, 0x1f, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x3b, 0x27, 0x1f, 0x03, 0x1b, 0x17, 0x0f, -+ 0x44, 0x20, 0x14, 0x08, 0x44, 0x43, 0x17, 0x04, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x54, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x40, 0x40, 0x40, 0x48, 0x21, -+ 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x43, -+ 0x4b, 0x10, 0x0c, 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x04, 0x04, 0x08, 0x00, -+ 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0c, 0x43, 0x5b, 0x4f, 0x43, 0x14, 0x14, 0x10, 0x21, 0x04, 0x04, -+ 0x08, 0x00, 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0c, 0x43, 0x5b, 0x4f, 0x43, 0x14, 0x14, 0x10, 0x21, -+ 0x28, 0x54, 0x2c, 0x4b, 0x43, 0x43, 0x00, 0x04, 0x04, 0x10, 0x08, 0x14, 0x08, 0x1c, 0x00, 0x4b, -+ 0x1f, 0x07, 0x00, 0x1c, 0x00, 0x4b, 0x1f, 0x07, 0x00, 0x1c, 0x00, 0x4b, 0x1f, 0x07, 0x00, 0x43, -+ 0x04, 0x07, 0x07, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x43, 0x1c, 0x04, 0x43, 0x40, 0x40, -+ 0x43, 0x20, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3c, 0x27, 0x20, 0x04, 0x1c, 0x18, 0x0f, -+ 0x43, 0x1f, 0x13, 0x07, 0x43, 0x44, 0x18, 0x03, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x55, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x40, 0x40, 0x40, 0x49, 0x22, -+ 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x42, -+ 0x4b, 0x11, 0x0c, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x05, 0x05, 0x08, 0x00, -+ 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0d, 0x42, 0x5b, 0x4f, 0x42, 0x16, 0x15, 0x10, 0x22, 0x05, 0x05, -+ 0x08, 0x00, 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0d, 0x42, 0x5b, 0x4f, 0x42, 0x16, 0x15, 0x10, 0x22, -+ 0x29, 0x54, 0x2c, 0x4b, 0x42, 0x42, 0x00, 0x05, 0x05, 0x11, 0x08, 0x15, 0x08, 0x1d, 0x00, 0x4b, -+ 0x1e, 0x07, 0x00, 0x1d, 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x1d, 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x43, -+ 0x04, 0x06, 0x06, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x42, 0x1c, 0x04, 0x42, 0x40, 0x40, -+ 0x43, 0x21, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3e, 0x27, 0x21, 0x04, 0x1d, 0x18, 0x0f, -+ 0x43, 0x1e, 0x13, 0x06, 0x43, 0x46, 0x18, 0x02, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x56, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x40, 0x40, 0x40, 0x49, 0x24, -+ 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x41, -+ 0x4b, 0x13, 0x0c, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x06, 0x06, 0x09, 0x01, -+ 0x43, 0x07, 0x01, 0x4e, 0x43, 0x0e, 0x41, 0x5b, 0x4e, 0x41, 0x18, 0x16, 0x11, 0x24, 0x06, 0x06, -+ 0x09, 0x01, 0x43, 0x07, 0x01, 0x4e, 0x43, 0x0e, 0x41, 0x5b, 0x4e, 0x41, 0x18, 0x16, 0x11, 0x24, -+ 0x2b, 0x54, 0x2c, 0x4b, 0x41, 0x41, 0x01, 0x06, 0x06, 0x13, 0x09, 0x16, 0x09, 0x1e, 0x01, 0x4b, -+ 0x1e, 0x07, 0x01, 0x1e, 0x01, 0x4b, 0x1e, 0x07, 0x01, 0x1e, 0x01, 0x4b, 0x1e, 0x07, 0x01, 0x43, -+ 0x04, 0x06, 0x06, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x41, 0x1c, 0x04, 0x41, 0x40, 0x40, -+ 0x43, 0x23, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3e, 0x27, 0x23, 0x04, 0x1e, 0x19, 0x0f, -+ 0x43, 0x1e, 0x13, 0x06, 0x43, 0x48, 0x19, 0x01, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x57, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x40, 0x40, 0x40, 0x4a, 0x26, -+ 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x40, -+ 0x4a, 0x14, 0x0d, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x07, 0x07, 0x0a, 0x02, -+ 0x42, 0x07, 0x02, 0x4d, 0x42, 0x0f, 0x40, 0x5a, 0x4d, 0x40, 0x19, 0x17, 0x12, 0x26, 0x07, 0x07, -+ 0x0a, 0x02, 0x42, 0x07, 0x02, 0x4d, 0x42, 0x0f, 0x40, 0x5a, 0x4d, 0x40, 0x19, 0x17, 0x12, 0x26, -+ 0x2c, 0x55, 0x2d, 0x4a, 0x40, 0x40, 0x02, 0x07, 0x07, 0x14, 0x0a, 0x17, 0x0a, 0x1f, 0x02, 0x4a, -+ 0x1d, 0x07, 0x02, 0x1f, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x1f, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x42, -+ 0x05, 0x05, 0x05, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x40, 0x1d, 0x05, 0x40, 0x40, 0x40, -+ 0x42, 0x24, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x24, 0x05, 0x1f, 0x1a, 0x0f, -+ 0x42, 0x1d, 0x12, 0x05, 0x42, 0x49, 0x1a, 0x00, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x58, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x40, 0x40, 0x40, 0x4a, 0x28, -+ 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x00, -+ 0x4a, 0x15, 0x0d, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x08, 0x08, 0x0a, 0x02, -+ 0x42, 0x07, 0x02, 0x4d, 0x42, 0x10, 0x00, 0x5a, 0x4d, 0x00, 0x1b, 0x18, 0x12, 0x28, 0x08, 0x08, -+ 0x0a, 0x02, 0x42, 0x07, 0x02, 0x4d, 0x42, 0x10, 0x00, 0x5a, 0x4d, 0x00, 0x1b, 0x18, 0x12, 0x28, -+ 0x2d, 0x55, 0x2d, 0x4a, 0x00, 0x00, 0x02, 0x08, 0x08, 0x15, 0x0a, 0x18, 0x0a, 0x20, 0x02, 0x4a, -+ 0x1d, 0x07, 0x02, 0x20, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x20, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x42, -+ 0x05, 0x05, 0x05, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x00, 0x1d, 0x05, 0x00, 0x40, 0x40, -+ 0x42, 0x25, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x25, 0x05, 0x20, 0x1a, 0x0f, -+ 0x42, 0x1d, 0x12, 0x05, 0x42, 0x4b, 0x1a, 0x40, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x59, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4b, 0x40, 0x40, 0x40, 0x4b, 0x2a, -+ 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x01, -+ 0x4a, 0x16, 0x0d, 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x09, 0x09, 0x0b, 0x03, -+ 0x42, 0x07, 0x03, 0x4c, 0x42, 0x11, 0x01, 0x5a, 0x4c, 0x01, 0x1c, 0x19, 0x13, 0x2a, 0x09, 0x09, -+ 0x0b, 0x03, 0x42, 0x07, 0x03, 0x4c, 0x42, 0x11, 0x01, 0x5a, 0x4c, 0x01, 0x1c, 0x19, 0x13, 0x2a, -+ 0x2e, 0x55, 0x2d, 0x4a, 0x01, 0x01, 0x03, 0x09, 0x09, 0x16, 0x0b, 0x19, 0x0b, 0x21, 0x03, 0x4a, -+ 0x1c, 0x07, 0x03, 0x21, 0x03, 0x4a, 0x1c, 0x07, 0x03, 0x21, 0x03, 0x4a, 0x1c, 0x07, 0x03, 0x42, -+ 0x05, 0x04, 0x04, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x01, 0x1d, 0x05, 0x01, 0x40, 0x40, -+ 0x42, 0x26, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x26, 0x05, 0x21, 0x1b, 0x0f, -+ 0x42, 0x1c, 0x12, 0x04, 0x42, 0x4c, 0x1b, 0x41, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x5a, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4c, 0x40, 0x40, 0x40, 0x4c, 0x2c, -+ 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x02, -+ 0x49, 0x18, 0x0e, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0a, 0x0a, 0x0c, 0x04, -+ 0x41, 0x07, 0x04, 0x4b, 0x41, 0x12, 0x02, 0x59, 0x4b, 0x02, 0x1e, 0x1a, 0x14, 0x2c, 0x0a, 0x0a, -+ 0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x12, 0x02, 0x59, 0x4b, 0x02, 0x1e, 0x1a, 0x14, 0x2c, -+ 0x30, 0x56, 0x2e, 0x49, 0x02, 0x02, 0x04, 0x0a, 0x0a, 0x18, 0x0c, 0x1a, 0x0c, 0x22, 0x04, 0x49, -+ 0x1b, 0x07, 0x04, 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x41, -+ 0x06, 0x03, 0x03, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x02, 0x1e, 0x06, 0x02, 0x40, 0x40, -+ 0x41, 0x28, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x28, 0x06, 0x22, 0x1c, 0x0f, -+ 0x41, 0x1b, 0x11, 0x03, 0x41, 0x4e, 0x1c, 0x42, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x5b, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4c, 0x40, 0x40, 0x40, 0x4c, 0x2e, -+ 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x03, -+ 0x49, 0x19, 0x0e, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0b, 0x0b, 0x0c, 0x04, -+ 0x41, 0x07, 0x04, 0x4b, 0x41, 0x13, 0x03, 0x59, 0x4b, 0x03, 0x1f, 0x1b, 0x14, 0x2e, 0x0b, 0x0b, -+ 0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x13, 0x03, 0x59, 0x4b, 0x03, 0x1f, 0x1b, 0x14, 0x2e, -+ 0x31, 0x56, 0x2e, 0x49, 0x03, 0x03, 0x04, 0x0b, 0x0b, 0x19, 0x0c, 0x1b, 0x0c, 0x23, 0x04, 0x49, -+ 0x1b, 0x07, 0x04, 0x23, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x23, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x41, -+ 0x06, 0x03, 0x03, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x03, 0x1e, 0x06, 0x03, 0x40, 0x40, -+ 0x41, 0x29, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x29, 0x06, 0x23, 0x1c, 0x0f, -+ 0x41, 0x1b, 0x11, 0x03, 0x41, 0x4f, 0x1c, 0x43, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x5c, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4d, 0x40, 0x40, 0x40, 0x4d, 0x30, -+ 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x04, -+ 0x49, 0x1a, 0x0e, 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0c, 0x0c, 0x0d, 0x05, -+ 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x21, 0x1c, 0x15, 0x30, 0x0c, 0x0c, -+ 0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x21, 0x1c, 0x15, 0x30, -+ 0x32, 0x56, 0x2e, 0x49, 0x04, 0x04, 0x05, 0x0c, 0x0c, 0x1a, 0x0d, 0x1c, 0x0d, 0x24, 0x05, 0x49, -+ 0x1a, 0x07, 0x05, 0x24, 0x05, 0x49, 0x1a, 0x07, 0x05, 0x24, 0x05, 0x49, 0x1a, 0x07, 0x05, 0x41, -+ 0x06, 0x02, 0x02, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x04, 0x1e, 0x06, 0x04, 0x40, 0x40, -+ 0x41, 0x2a, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x2a, 0x06, 0x24, 0x1d, 0x0f, -+ 0x41, 0x1a, 0x11, 0x02, 0x41, 0x51, 0x1d, 0x44, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x5d, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x4e, 0x31, -+ 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x04, -+ 0x49, 0x1b, 0x0e, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0c, 0x0c, 0x0d, 0x05, -+ 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x22, 0x1c, 0x15, 0x31, 0x0c, 0x0c, -+ 0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x22, 0x1c, 0x15, 0x31, -+ 0x33, 0x57, 0x2e, 0x49, 0x04, 0x04, 0x05, 0x0c, 0x0c, 0x1b, 0x0d, 0x1c, 0x0d, 0x24, 0x05, 0x49, -+ 0x19, 0x07, 0x05, 0x24, 0x05, 0x49, 0x19, 0x07, 0x05, 0x24, 0x05, 0x49, 0x19, 0x07, 0x05, 0x41, -+ 0x06, 0x01, 0x01, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x04, 0x1e, 0x06, 0x04, 0x40, 0x40, -+ 0x41, 0x2b, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x2b, 0x06, 0x24, 0x1d, 0x0f, -+ 0x41, 0x19, 0x10, 0x01, 0x41, 0x53, 0x1d, 0x45, 0x0e, 0x07, 0x1e, 0x08, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x5d, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x4e, 0x33, -+ 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x05, -+ 0x48, 0x1d, 0x0f, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0d, 0x0d, 0x0e, 0x06, -+ 0x40, 0x07, 0x06, 0x49, 0x40, 0x15, 0x05, 0x58, 0x49, 0x05, 0x24, 0x1d, 0x16, 0x33, 0x0d, 0x0d, -+ 0x0e, 0x06, 0x40, 0x07, 0x06, 0x49, 0x40, 0x15, 0x05, 0x58, 0x49, 0x05, 0x24, 0x1d, 0x16, 0x33, -+ 0x35, 0x57, 0x2f, 0x48, 0x05, 0x05, 0x06, 0x0d, 0x0d, 0x1d, 0x0e, 0x1d, 0x0e, 0x25, 0x06, 0x48, -+ 0x19, 0x07, 0x06, 0x25, 0x06, 0x48, 0x19, 0x07, 0x06, 0x25, 0x06, 0x48, 0x19, 0x07, 0x06, 0x40, -+ 0x07, 0x01, 0x01, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x05, 0x1f, 0x07, 0x05, 0x40, 0x40, -+ 0x40, 0x2d, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2d, 0x07, 0x25, 0x1e, 0x0f, -+ 0x40, 0x19, 0x10, 0x01, 0x40, 0x54, 0x1e, 0x45, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x5e, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x4f, 0x35, -+ 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x06, -+ 0x48, 0x1e, 0x0f, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0e, 0x0e, 0x0f, 0x07, -+ 0x40, 0x07, 0x07, 0x48, 0x40, 0x16, 0x06, 0x58, 0x48, 0x06, 0x26, 0x1e, 0x17, 0x35, 0x0e, 0x0e, -+ 0x0f, 0x07, 0x40, 0x07, 0x07, 0x48, 0x40, 0x16, 0x06, 0x58, 0x48, 0x06, 0x26, 0x1e, 0x17, 0x35, -+ 0x36, 0x57, 0x2f, 0x48, 0x06, 0x06, 0x07, 0x0e, 0x0e, 0x1e, 0x0f, 0x1e, 0x0f, 0x26, 0x07, 0x48, -+ 0x18, 0x07, 0x07, 0x26, 0x07, 0x48, 0x18, 0x07, 0x07, 0x26, 0x07, 0x48, 0x18, 0x07, 0x07, 0x40, -+ 0x07, 0x00, 0x00, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x06, 0x1f, 0x07, 0x06, 0x40, 0x40, -+ 0x40, 0x2e, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2e, 0x07, 0x26, 0x1f, 0x0f, -+ 0x40, 0x18, 0x10, 0x00, 0x40, 0x56, 0x1f, 0x46, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x5f, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x4f, 0x37, -+ 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x07, -+ 0x48, 0x1f, 0x0f, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x07, -+ 0x40, 0x07, 0x07, 0x48, 0x40, 0x17, 0x07, 0x58, 0x48, 0x07, 0x27, 0x1f, 0x17, 0x37, 0x0f, 0x0f, -+ 0x0f, 0x07, 0x40, 0x07, 0x07, 0x48, 0x40, 0x17, 0x07, 0x58, 0x48, 0x07, 0x27, 0x1f, 0x17, 0x37, -+ 0x37, 0x57, 0x2f, 0x48, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x1f, 0x0f, 0x1f, 0x0f, 0x27, 0x07, 0x48, -+ 0x18, 0x07, 0x07, 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, 0x40, -+ 0x07, 0x00, 0x00, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x07, 0x1f, 0x07, 0x07, 0x40, 0x40, -+ 0x40, 0x2f, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2f, 0x07, 0x27, 0x1f, 0x0f, -+ 0x40, 0x18, 0x10, 0x00, 0x40, 0x57, 0x1f, 0x47, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x07, 0x48, 0x48, 0x60, 0x40, 0x27, 0x07, 0x07, 0x27, 0x40, 0x48, 0x40, 0x40, 0x40, 0x0f, -+ 0x48, 0x68, 0x60, 0x40, 0x68, 0x68, 0x68, 0x68, 0x68, 0x07, 0x07, 0x0f, 0x50, 0x40, 0x60, 0x07, -+ 0x68, 0x27, 0x48, 0x17, 0x40, 0x50, 0x1f, 0x40, 0x40, 0x40, 0x48, 0x48, 0x58, 0x60, 0x60, 0x60, -+ 0x68, 0x68, 0x58, 0x68, 0x60, 0x60, 0x60, 0x68, 0x68, 0x68, 0x60, 0x50, 0x48, 0x50, 0x58, 0x60, -+ 0x60, 0x60, 0x68, 0x68, 0x58, 0x68, 0x60, 0x60, 0x60, 0x68, 0x68, 0x68, 0x60, 0x50, 0x48, 0x50, -+ 0x07, 0x50, 0x58, 0x40, 0x48, 0x40, 0x48, 0x07, 0x48, 0x48, 0x48, 0x68, 0x07, 0x1f, 0x17, 0x50, -+ 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x40, -+ 0x07, 0x48, 0x48, 0x48, 0x07, 0x48, 0x07, 0x17, 0x17, 0x17, 0x50, 0x17, 0x17, 0x50, 0x40, 0x40, -+ 0x40, 0x2f, 0x2f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x1f, 0x27, 0x0f, 0x07, 0x07, 0x0f, 0x07, -+ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x07, 0x1f, 0x48, 0x17, 0x48, 0x40, 0x48, 0x17, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x07, 0x47, 0x47, 0x5f, 0x40, 0x27, 0x07, 0x07, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f, -+ 0x47, 0x66, 0x5f, 0x00, 0x66, 0x66, 0x66, 0x65, 0x65, 0x07, 0x07, 0x0f, 0x4f, 0x00, 0x5e, 0x07, -+ 0x67, 0x27, 0x47, 0x17, 0x40, 0x4f, 0x1f, 0x40, 0x40, 0x40, 0x47, 0x47, 0x57, 0x5f, 0x5e, 0x5f, -+ 0x66, 0x66, 0x57, 0x67, 0x5f, 0x5e, 0x5f, 0x67, 0x67, 0x66, 0x5e, 0x4f, 0x47, 0x4f, 0x57, 0x5f, -+ 0x5e, 0x5f, 0x66, 0x66, 0x57, 0x67, 0x5f, 0x5e, 0x5f, 0x67, 0x67, 0x66, 0x5e, 0x4f, 0x47, 0x4f, -+ 0x08, 0x4f, 0x56, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x47, 0x47, 0x66, 0x07, 0x1f, 0x17, 0x4f, -+ 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x40, -+ 0x07, 0x47, 0x47, 0x47, 0x08, 0x47, 0x08, 0x17, 0x17, 0x17, 0x4f, 0x17, 0x17, 0x4f, 0x40, 0x40, -+ 0x40, 0x2f, 0x2f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x20, 0x27, 0x10, 0x07, 0x08, 0x10, 0x08, -+ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1f, 0x47, 0x17, 0x46, 0x00, 0x47, 0x17, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x06, 0x46, 0x47, 0x5e, 0x40, 0x26, 0x06, 0x06, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f, -+ 0x47, 0x64, 0x5e, 0x01, 0x65, 0x64, 0x64, 0x63, 0x63, 0x07, 0x07, 0x0f, 0x4e, 0x00, 0x5d, 0x07, -+ 0x66, 0x27, 0x46, 0x17, 0x40, 0x4f, 0x1e, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5e, 0x5d, 0x5e, -+ 0x65, 0x64, 0x56, 0x66, 0x5e, 0x5c, 0x5e, 0x66, 0x66, 0x65, 0x5d, 0x4e, 0x46, 0x4e, 0x56, 0x5e, -+ 0x5d, 0x5e, 0x65, 0x64, 0x56, 0x66, 0x5e, 0x5c, 0x5e, 0x66, 0x66, 0x65, 0x5d, 0x4e, 0x46, 0x4e, -+ 0x09, 0x4f, 0x54, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x64, 0x07, 0x1f, 0x16, 0x4f, -+ 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40, -+ 0x07, 0x46, 0x46, 0x46, 0x09, 0x46, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40, -+ 0x40, 0x2e, 0x2e, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x08, -+ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1e, 0x46, 0x17, 0x45, 0x01, 0x46, 0x17, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x06, 0x45, 0x47, 0x5e, 0x40, 0x25, 0x06, 0x05, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f, -+ 0x47, 0x63, 0x5d, 0x01, 0x64, 0x63, 0x62, 0x60, 0x60, 0x07, 0x07, 0x0f, 0x4e, 0x00, 0x5c, 0x07, -+ 0x65, 0x27, 0x45, 0x17, 0x40, 0x4f, 0x1d, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5d, 0x5c, 0x5d, -+ 0x64, 0x63, 0x56, 0x65, 0x5d, 0x5b, 0x5d, 0x65, 0x65, 0x64, 0x5c, 0x4d, 0x46, 0x4d, 0x56, 0x5d, -+ 0x5c, 0x5d, 0x64, 0x63, 0x56, 0x65, 0x5d, 0x5b, 0x5d, 0x65, 0x65, 0x64, 0x5c, 0x4d, 0x46, 0x4d, -+ 0x09, 0x4f, 0x52, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x62, 0x07, 0x1f, 0x16, 0x4f, -+ 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40, -+ 0x07, 0x46, 0x46, 0x45, 0x09, 0x45, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40, -+ 0x40, 0x2d, 0x2d, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x08, -+ 0x07, 0x3d, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1e, 0x45, 0x17, 0x44, 0x01, 0x45, 0x17, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x05, 0x44, 0x46, 0x5d, 0x40, 0x24, 0x05, 0x04, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f, -+ 0x46, 0x61, 0x5c, 0x02, 0x63, 0x61, 0x60, 0x5e, 0x5e, 0x07, 0x07, 0x0e, 0x4d, 0x01, 0x5b, 0x07, -+ 0x64, 0x27, 0x44, 0x16, 0x40, 0x4e, 0x1c, 0x40, 0x40, 0x40, 0x46, 0x46, 0x55, 0x5c, 0x5b, 0x5c, -+ 0x63, 0x61, 0x55, 0x64, 0x5c, 0x59, 0x5c, 0x64, 0x64, 0x63, 0x5b, 0x4c, 0x45, 0x4c, 0x55, 0x5c, -+ 0x5b, 0x5c, 0x63, 0x61, 0x55, 0x64, 0x5c, 0x59, 0x5c, 0x64, 0x64, 0x63, 0x5b, 0x4c, 0x45, 0x4c, -+ 0x0a, 0x4e, 0x50, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x45, 0x45, 0x60, 0x07, 0x1e, 0x15, 0x4e, -+ 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x41, -+ 0x07, 0x45, 0x45, 0x44, 0x0a, 0x44, 0x0a, 0x16, 0x17, 0x15, 0x4e, 0x17, 0x15, 0x4e, 0x40, 0x40, -+ 0x40, 0x2c, 0x2c, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x1d, 0x21, 0x27, 0x11, 0x07, 0x0a, 0x11, 0x09, -+ 0x06, 0x3c, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1d, 0x44, 0x16, 0x43, 0x02, 0x44, 0x16, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x04, 0x43, 0x46, 0x5c, 0x40, 0x23, 0x04, 0x03, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f, -+ 0x46, 0x60, 0x5b, 0x03, 0x61, 0x60, 0x5e, 0x5b, 0x5b, 0x07, 0x07, 0x0e, 0x4c, 0x01, 0x59, 0x07, -+ 0x63, 0x27, 0x43, 0x16, 0x40, 0x4e, 0x1b, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5b, 0x59, 0x5b, -+ 0x61, 0x60, 0x54, 0x63, 0x5b, 0x58, 0x5b, 0x63, 0x63, 0x61, 0x59, 0x4b, 0x44, 0x4b, 0x54, 0x5b, -+ 0x59, 0x5b, 0x61, 0x60, 0x54, 0x63, 0x5b, 0x58, 0x5b, 0x63, 0x63, 0x61, 0x59, 0x4b, 0x44, 0x4b, -+ 0x0b, 0x4e, 0x4e, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5e, 0x07, 0x1e, 0x14, 0x4e, -+ 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41, -+ 0x07, 0x44, 0x44, 0x43, 0x0b, 0x43, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40, -+ 0x40, 0x2b, 0x2b, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x09, -+ 0x06, 0x3b, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1c, 0x43, 0x16, 0x41, 0x03, 0x43, 0x16, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x04, 0x42, 0x46, 0x5c, 0x40, 0x22, 0x04, 0x02, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f, -+ 0x46, 0x5e, 0x5a, 0x03, 0x60, 0x5e, 0x5c, 0x59, 0x59, 0x07, 0x07, 0x0e, 0x4c, 0x01, 0x58, 0x07, -+ 0x62, 0x27, 0x42, 0x16, 0x40, 0x4e, 0x1a, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5a, 0x58, 0x5a, -+ 0x60, 0x5e, 0x54, 0x62, 0x5a, 0x56, 0x5a, 0x62, 0x62, 0x60, 0x58, 0x4a, 0x44, 0x4a, 0x54, 0x5a, -+ 0x58, 0x5a, 0x60, 0x5e, 0x54, 0x62, 0x5a, 0x56, 0x5a, 0x62, 0x62, 0x60, 0x58, 0x4a, 0x44, 0x4a, -+ 0x0b, 0x4e, 0x4c, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5c, 0x07, 0x1e, 0x14, 0x4e, -+ 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41, -+ 0x07, 0x44, 0x44, 0x42, 0x0b, 0x42, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40, -+ 0x40, 0x2a, 0x2a, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x09, -+ 0x06, 0x3a, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1c, 0x42, 0x16, 0x40, 0x03, 0x42, 0x16, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x03, 0x41, 0x45, 0x5b, 0x40, 0x21, 0x03, 0x01, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f, -+ 0x45, 0x5d, 0x59, 0x04, 0x5f, 0x5d, 0x5a, 0x56, 0x56, 0x07, 0x07, 0x0d, 0x4b, 0x02, 0x57, 0x07, -+ 0x61, 0x27, 0x41, 0x15, 0x40, 0x4d, 0x19, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x59, 0x57, 0x59, -+ 0x5f, 0x5d, 0x53, 0x61, 0x59, 0x55, 0x59, 0x61, 0x61, 0x5f, 0x57, 0x49, 0x43, 0x49, 0x53, 0x59, -+ 0x57, 0x59, 0x5f, 0x5d, 0x53, 0x61, 0x59, 0x55, 0x59, 0x61, 0x61, 0x5f, 0x57, 0x49, 0x43, 0x49, -+ 0x0c, 0x4d, 0x4a, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x5a, 0x07, 0x1d, 0x13, 0x4d, -+ 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x42, -+ 0x07, 0x43, 0x43, 0x41, 0x0c, 0x41, 0x0c, 0x15, 0x17, 0x13, 0x4d, 0x17, 0x13, 0x4d, 0x40, 0x40, -+ 0x40, 0x29, 0x29, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x1b, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x0a, -+ 0x05, 0x39, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1b, 0x41, 0x15, 0x00, 0x04, 0x41, 0x15, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x02, 0x40, 0x45, 0x5b, 0x40, 0x20, 0x02, 0x00, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f, -+ 0x45, 0x5b, 0x58, 0x04, 0x5e, 0x5b, 0x59, 0x54, 0x54, 0x07, 0x07, 0x0d, 0x4b, 0x02, 0x56, 0x07, -+ 0x60, 0x27, 0x40, 0x15, 0x40, 0x4d, 0x18, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x58, 0x56, 0x58, -+ 0x5e, 0x5b, 0x53, 0x60, 0x58, 0x53, 0x58, 0x60, 0x60, 0x5e, 0x56, 0x48, 0x43, 0x48, 0x53, 0x58, -+ 0x56, 0x58, 0x5e, 0x5b, 0x53, 0x60, 0x58, 0x53, 0x58, 0x60, 0x60, 0x5e, 0x56, 0x48, 0x43, 0x48, -+ 0x0c, 0x4d, 0x49, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x59, 0x07, 0x1d, 0x12, 0x4d, -+ 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42, -+ 0x07, 0x43, 0x43, 0x40, 0x0c, 0x40, 0x0c, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, -+ 0x40, 0x28, 0x28, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x0a, -+ 0x05, 0x38, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1a, 0x40, 0x15, 0x01, 0x04, 0x40, 0x15, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x02, 0x00, 0x45, 0x5a, 0x40, 0x1f, 0x02, 0x40, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f, -+ 0x45, 0x59, 0x57, 0x05, 0x5c, 0x59, 0x57, 0x51, 0x51, 0x07, 0x07, 0x0d, 0x4a, 0x02, 0x54, 0x07, -+ 0x5f, 0x27, 0x00, 0x15, 0x40, 0x4d, 0x17, 0x40, 0x40, 0x40, 0x45, 0x45, 0x52, 0x57, 0x54, 0x57, -+ 0x5c, 0x59, 0x52, 0x5f, 0x57, 0x51, 0x57, 0x5f, 0x5f, 0x5c, 0x54, 0x47, 0x42, 0x47, 0x52, 0x57, -+ 0x54, 0x57, 0x5c, 0x59, 0x52, 0x5f, 0x57, 0x51, 0x57, 0x5f, 0x5f, 0x5c, 0x54, 0x47, 0x42, 0x47, -+ 0x0d, 0x4d, 0x47, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x42, 0x42, 0x57, 0x07, 0x1d, 0x12, 0x4d, -+ 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42, -+ 0x07, 0x42, 0x42, 0x00, 0x0d, 0x00, 0x0d, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, -+ 0x40, 0x27, 0x27, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0d, 0x12, 0x0a, -+ 0x05, 0x37, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1a, 0x00, 0x15, 0x03, 0x05, 0x00, 0x15, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x01, 0x01, 0x44, 0x59, 0x40, 0x1e, 0x01, 0x41, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f, -+ 0x44, 0x58, 0x56, 0x06, 0x5b, 0x58, 0x55, 0x4f, 0x4f, 0x07, 0x07, 0x0c, 0x49, 0x03, 0x53, 0x07, -+ 0x5e, 0x27, 0x01, 0x14, 0x40, 0x4c, 0x16, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x56, 0x53, 0x56, -+ 0x5b, 0x58, 0x51, 0x5e, 0x56, 0x50, 0x56, 0x5e, 0x5e, 0x5b, 0x53, 0x46, 0x41, 0x46, 0x51, 0x56, -+ 0x53, 0x56, 0x5b, 0x58, 0x51, 0x5e, 0x56, 0x50, 0x56, 0x5e, 0x5e, 0x5b, 0x53, 0x46, 0x41, 0x46, -+ 0x0e, 0x4c, 0x45, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x55, 0x07, 0x1c, 0x11, 0x4c, -+ 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, -+ 0x07, 0x41, 0x41, 0x01, 0x0e, 0x01, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, -+ 0x40, 0x26, 0x26, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x0b, -+ 0x04, 0x36, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x19, 0x01, 0x14, 0x04, 0x06, 0x01, 0x14, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x01, 0x02, 0x44, 0x59, 0x40, 0x1d, 0x01, 0x42, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f, -+ 0x44, 0x56, 0x55, 0x06, 0x5a, 0x56, 0x53, 0x4c, 0x4c, 0x07, 0x07, 0x0c, 0x49, 0x03, 0x52, 0x07, -+ 0x5d, 0x27, 0x02, 0x14, 0x40, 0x4c, 0x15, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x55, 0x52, 0x55, -+ 0x5a, 0x56, 0x51, 0x5d, 0x55, 0x4e, 0x55, 0x5d, 0x5d, 0x5a, 0x52, 0x45, 0x41, 0x45, 0x51, 0x55, -+ 0x52, 0x55, 0x5a, 0x56, 0x51, 0x5d, 0x55, 0x4e, 0x55, 0x5d, 0x5d, 0x5a, 0x52, 0x45, 0x41, 0x45, -+ 0x0e, 0x4c, 0x43, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x53, 0x07, 0x1c, 0x11, 0x4c, -+ 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, -+ 0x07, 0x41, 0x41, 0x02, 0x0e, 0x02, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, -+ 0x40, 0x25, 0x25, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x0b, -+ 0x04, 0x35, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x19, 0x02, 0x14, 0x05, 0x06, 0x02, 0x14, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x00, 0x03, 0x44, 0x58, 0x40, 0x1c, 0x00, 0x43, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f, -+ 0x44, 0x55, 0x54, 0x07, 0x59, 0x55, 0x51, 0x4a, 0x4a, 0x07, 0x07, 0x0c, 0x48, 0x03, 0x51, 0x07, -+ 0x5c, 0x27, 0x03, 0x14, 0x40, 0x4c, 0x14, 0x40, 0x40, 0x40, 0x44, 0x44, 0x50, 0x54, 0x51, 0x54, -+ 0x59, 0x55, 0x50, 0x5c, 0x54, 0x4d, 0x54, 0x5c, 0x5c, 0x59, 0x51, 0x44, 0x40, 0x44, 0x50, 0x54, -+ 0x51, 0x54, 0x59, 0x55, 0x50, 0x5c, 0x54, 0x4d, 0x54, 0x5c, 0x5c, 0x59, 0x51, 0x44, 0x40, 0x44, -+ 0x0f, 0x4c, 0x41, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x40, 0x40, 0x51, 0x07, 0x1c, 0x10, 0x4c, -+ 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x43, -+ 0x07, 0x40, 0x40, 0x03, 0x0f, 0x03, 0x0f, 0x14, 0x17, 0x10, 0x4c, 0x17, 0x10, 0x4c, 0x40, 0x40, -+ 0x40, 0x24, 0x24, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x18, 0x23, 0x27, 0x13, 0x07, 0x0f, 0x13, 0x0b, -+ 0x04, 0x34, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x18, 0x03, 0x14, 0x06, 0x07, 0x03, 0x14, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x40, 0x04, 0x43, 0x57, 0x40, 0x1b, 0x40, 0x44, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, -+ 0x43, 0x53, 0x53, 0x08, 0x57, 0x53, 0x4f, 0x47, 0x47, 0x07, 0x07, 0x0b, 0x47, 0x04, 0x4f, 0x07, -+ 0x5b, 0x27, 0x04, 0x13, 0x40, 0x4b, 0x13, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x53, 0x4f, 0x53, -+ 0x57, 0x53, 0x4f, 0x5b, 0x53, 0x4b, 0x53, 0x5b, 0x5b, 0x57, 0x4f, 0x43, 0x00, 0x43, 0x4f, 0x53, -+ 0x4f, 0x53, 0x57, 0x53, 0x4f, 0x5b, 0x53, 0x4b, 0x53, 0x5b, 0x5b, 0x57, 0x4f, 0x43, 0x00, 0x43, -+ 0x10, 0x4b, 0x00, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4f, 0x07, 0x1b, 0x0f, 0x4b, -+ 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44, -+ 0x07, 0x00, 0x00, 0x04, 0x10, 0x04, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40, -+ 0x40, 0x23, 0x23, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x0c, -+ 0x03, 0x33, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x17, 0x04, 0x13, 0x08, 0x08, 0x04, 0x13, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x40, 0x05, 0x43, 0x57, 0x40, 0x1a, 0x40, 0x45, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, -+ 0x43, 0x52, 0x52, 0x08, 0x56, 0x52, 0x4d, 0x45, 0x45, 0x07, 0x07, 0x0b, 0x47, 0x04, 0x4e, 0x07, -+ 0x5a, 0x27, 0x05, 0x13, 0x40, 0x4b, 0x12, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x52, 0x4e, 0x52, -+ 0x56, 0x52, 0x4f, 0x5a, 0x52, 0x4a, 0x52, 0x5a, 0x5a, 0x56, 0x4e, 0x42, 0x00, 0x42, 0x4f, 0x52, -+ 0x4e, 0x52, 0x56, 0x52, 0x4f, 0x5a, 0x52, 0x4a, 0x52, 0x5a, 0x5a, 0x56, 0x4e, 0x42, 0x00, 0x42, -+ 0x10, 0x4b, 0x02, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4d, 0x07, 0x1b, 0x0f, 0x4b, -+ 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44, -+ 0x07, 0x00, 0x00, 0x05, 0x10, 0x05, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40, -+ 0x40, 0x22, 0x22, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x0c, -+ 0x03, 0x32, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x17, 0x05, 0x13, 0x09, 0x08, 0x05, 0x13, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x41, 0x06, 0x43, 0x56, 0x40, 0x19, 0x41, 0x46, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, -+ 0x43, 0x50, 0x51, 0x09, 0x55, 0x50, 0x4b, 0x42, 0x42, 0x07, 0x07, 0x0b, 0x46, 0x04, 0x4d, 0x07, -+ 0x59, 0x27, 0x06, 0x13, 0x40, 0x4b, 0x11, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x4d, 0x51, -+ 0x55, 0x50, 0x4e, 0x59, 0x51, 0x48, 0x51, 0x59, 0x59, 0x55, 0x4d, 0x41, 0x01, 0x41, 0x4e, 0x51, -+ 0x4d, 0x51, 0x55, 0x50, 0x4e, 0x59, 0x51, 0x48, 0x51, 0x59, 0x59, 0x55, 0x4d, 0x41, 0x01, 0x41, -+ 0x11, 0x4b, 0x04, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4b, 0x07, 0x1b, 0x0e, 0x4b, -+ 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x44, -+ 0x07, 0x01, 0x01, 0x06, 0x11, 0x06, 0x11, 0x13, 0x17, 0x0e, 0x4b, 0x17, 0x0e, 0x4b, 0x40, 0x40, -+ 0x40, 0x21, 0x21, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x16, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x0c, -+ 0x03, 0x31, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x16, 0x06, 0x13, 0x0a, 0x09, 0x06, 0x13, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x42, 0x06, 0x43, 0x56, 0x40, 0x18, 0x42, 0x47, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, -+ 0x43, 0x4f, 0x51, 0x09, 0x54, 0x4f, 0x4a, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x46, 0x04, 0x4c, 0x07, -+ 0x59, 0x27, 0x06, 0x12, 0x40, 0x4b, 0x10, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x4c, 0x51, -+ 0x54, 0x4f, 0x4e, 0x59, 0x51, 0x47, 0x51, 0x59, 0x59, 0x54, 0x4c, 0x41, 0x01, 0x41, 0x4e, 0x51, -+ 0x4c, 0x51, 0x54, 0x4f, 0x4e, 0x59, 0x51, 0x47, 0x51, 0x59, 0x59, 0x54, 0x4c, 0x41, 0x01, 0x41, -+ 0x11, 0x4b, 0x05, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4a, 0x07, 0x1a, 0x0d, 0x4b, -+ 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x45, -+ 0x07, 0x01, 0x01, 0x06, 0x11, 0x06, 0x11, 0x12, 0x17, 0x0d, 0x4b, 0x17, 0x0d, 0x4b, 0x40, 0x40, -+ 0x40, 0x20, 0x20, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x0c, -+ 0x02, 0x30, 0x1a, 0x12, 0x40, 0x12, 0x0c, 0x15, 0x06, 0x12, 0x0b, 0x09, 0x06, 0x12, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x42, 0x07, 0x42, 0x55, 0x40, 0x18, 0x42, 0x47, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f, -+ 0x42, 0x4d, 0x50, 0x0a, 0x52, 0x4d, 0x48, 0x02, 0x02, 0x07, 0x07, 0x0a, 0x45, 0x05, 0x4a, 0x07, -+ 0x58, 0x27, 0x07, 0x12, 0x40, 0x4a, 0x10, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4d, 0x50, 0x4a, 0x50, -+ 0x52, 0x4d, 0x4d, 0x58, 0x50, 0x45, 0x50, 0x58, 0x58, 0x52, 0x4a, 0x40, 0x02, 0x40, 0x4d, 0x50, -+ 0x4a, 0x50, 0x52, 0x4d, 0x4d, 0x58, 0x50, 0x45, 0x50, 0x58, 0x58, 0x52, 0x4a, 0x40, 0x02, 0x40, -+ 0x12, 0x4a, 0x07, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x02, 0x02, 0x48, 0x07, 0x1a, 0x0d, 0x4a, -+ 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x45, -+ 0x07, 0x02, 0x02, 0x07, 0x12, 0x07, 0x12, 0x12, 0x17, 0x0d, 0x4a, 0x17, 0x0d, 0x4a, 0x40, 0x40, -+ 0x40, 0x20, 0x20, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x25, 0x27, 0x15, 0x07, 0x12, 0x15, 0x0d, -+ 0x02, 0x30, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x15, 0x07, 0x12, 0x0d, 0x0a, 0x07, 0x12, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x43, 0x08, 0x42, 0x54, 0x40, 0x17, 0x43, 0x48, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f, -+ 0x42, 0x4b, 0x4f, 0x0b, 0x51, 0x4b, 0x46, 0x04, 0x04, 0x07, 0x07, 0x0a, 0x44, 0x05, 0x49, 0x07, -+ 0x57, 0x27, 0x08, 0x12, 0x40, 0x4a, 0x0f, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4f, 0x49, 0x4f, -+ 0x51, 0x4b, 0x4c, 0x57, 0x4f, 0x43, 0x4f, 0x57, 0x57, 0x51, 0x49, 0x00, 0x03, 0x00, 0x4c, 0x4f, -+ 0x49, 0x4f, 0x51, 0x4b, 0x4c, 0x57, 0x4f, 0x43, 0x4f, 0x57, 0x57, 0x51, 0x49, 0x00, 0x03, 0x00, -+ 0x13, 0x4a, 0x09, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x46, 0x07, 0x1a, 0x0c, 0x4a, -+ 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, -+ 0x07, 0x03, 0x03, 0x08, 0x13, 0x08, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, -+ 0x40, 0x1f, 0x1f, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0d, -+ 0x02, 0x2f, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x14, 0x08, 0x12, 0x0e, 0x0b, 0x08, 0x12, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x43, 0x09, 0x42, 0x54, 0x40, 0x16, 0x43, 0x49, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f, -+ 0x42, 0x4a, 0x4e, 0x0b, 0x50, 0x4a, 0x44, 0x07, 0x07, 0x07, 0x07, 0x0a, 0x44, 0x05, 0x48, 0x07, -+ 0x56, 0x27, 0x09, 0x12, 0x40, 0x4a, 0x0e, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4e, 0x48, 0x4e, -+ 0x50, 0x4a, 0x4c, 0x56, 0x4e, 0x42, 0x4e, 0x56, 0x56, 0x50, 0x48, 0x01, 0x03, 0x01, 0x4c, 0x4e, -+ 0x48, 0x4e, 0x50, 0x4a, 0x4c, 0x56, 0x4e, 0x42, 0x4e, 0x56, 0x56, 0x50, 0x48, 0x01, 0x03, 0x01, -+ 0x13, 0x4a, 0x0b, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x44, 0x07, 0x1a, 0x0c, 0x4a, -+ 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, -+ 0x07, 0x03, 0x03, 0x09, 0x13, 0x09, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, -+ 0x40, 0x1e, 0x1e, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0d, -+ 0x02, 0x2e, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x14, 0x09, 0x12, 0x0f, 0x0b, 0x09, 0x12, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x44, 0x0a, 0x41, 0x53, 0x40, 0x15, 0x44, 0x4a, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f, -+ 0x41, 0x48, 0x4d, 0x0c, 0x4f, 0x48, 0x42, 0x09, 0x09, 0x07, 0x07, 0x09, 0x43, 0x06, 0x47, 0x07, -+ 0x55, 0x27, 0x0a, 0x11, 0x40, 0x49, 0x0d, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4d, 0x47, 0x4d, -+ 0x4f, 0x48, 0x4b, 0x55, 0x4d, 0x40, 0x4d, 0x55, 0x55, 0x4f, 0x47, 0x02, 0x04, 0x02, 0x4b, 0x4d, -+ 0x47, 0x4d, 0x4f, 0x48, 0x4b, 0x55, 0x4d, 0x40, 0x4d, 0x55, 0x55, 0x4f, 0x47, 0x02, 0x04, 0x02, -+ 0x14, 0x49, 0x0d, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x04, 0x04, 0x42, 0x07, 0x19, 0x0b, 0x49, -+ 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x46, -+ 0x07, 0x04, 0x04, 0x0a, 0x14, 0x0a, 0x14, 0x11, 0x17, 0x0b, 0x49, 0x17, 0x0b, 0x49, 0x40, 0x40, -+ 0x40, 0x1d, 0x1d, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x13, 0x26, 0x27, 0x16, 0x07, 0x14, 0x16, 0x0e, -+ 0x01, 0x2d, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x13, 0x0a, 0x11, 0x10, 0x0c, 0x0a, 0x11, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x45, 0x0b, 0x41, 0x52, 0x40, 0x14, 0x45, 0x4b, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f, -+ 0x41, 0x47, 0x4c, 0x0d, 0x4d, 0x47, 0x40, 0x0c, 0x0c, 0x07, 0x07, 0x09, 0x42, 0x06, 0x45, 0x07, -+ 0x54, 0x27, 0x0b, 0x11, 0x40, 0x49, 0x0c, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4c, 0x45, 0x4c, -+ 0x4d, 0x47, 0x4a, 0x54, 0x4c, 0x00, 0x4c, 0x54, 0x54, 0x4d, 0x45, 0x03, 0x05, 0x03, 0x4a, 0x4c, -+ 0x45, 0x4c, 0x4d, 0x47, 0x4a, 0x54, 0x4c, 0x00, 0x4c, 0x54, 0x54, 0x4d, 0x45, 0x03, 0x05, 0x03, -+ 0x15, 0x49, 0x0f, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x40, 0x07, 0x19, 0x0a, 0x49, -+ 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, -+ 0x07, 0x05, 0x05, 0x0b, 0x15, 0x0b, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40, -+ 0x40, 0x1c, 0x1c, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0e, -+ 0x01, 0x2c, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x12, 0x0b, 0x11, 0x12, 0x0d, 0x0b, 0x11, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x45, 0x0c, 0x41, 0x52, 0x40, 0x13, 0x45, 0x4c, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f, -+ 0x41, 0x45, 0x4b, 0x0d, 0x4c, 0x45, 0x01, 0x0e, 0x0e, 0x07, 0x07, 0x09, 0x42, 0x06, 0x44, 0x07, -+ 0x53, 0x27, 0x0c, 0x11, 0x40, 0x49, 0x0b, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4b, 0x44, 0x4b, -+ 0x4c, 0x45, 0x4a, 0x53, 0x4b, 0x02, 0x4b, 0x53, 0x53, 0x4c, 0x44, 0x04, 0x05, 0x04, 0x4a, 0x4b, -+ 0x44, 0x4b, 0x4c, 0x45, 0x4a, 0x53, 0x4b, 0x02, 0x4b, 0x53, 0x53, 0x4c, 0x44, 0x04, 0x05, 0x04, -+ 0x15, 0x49, 0x11, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x01, 0x07, 0x19, 0x0a, 0x49, -+ 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, -+ 0x07, 0x05, 0x05, 0x0c, 0x15, 0x0c, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40, -+ 0x40, 0x1b, 0x1b, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0e, -+ 0x01, 0x2b, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x12, 0x0c, 0x11, 0x13, 0x0d, 0x0c, 0x11, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x46, 0x0d, 0x40, 0x51, 0x40, 0x12, 0x46, 0x4d, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, -+ 0x40, 0x44, 0x4a, 0x0e, 0x4b, 0x44, 0x03, 0x11, 0x11, 0x07, 0x07, 0x08, 0x41, 0x07, 0x43, 0x07, -+ 0x52, 0x27, 0x0d, 0x10, 0x40, 0x48, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x4a, 0x43, 0x4a, -+ 0x4b, 0x44, 0x49, 0x52, 0x4a, 0x03, 0x4a, 0x52, 0x52, 0x4b, 0x43, 0x05, 0x06, 0x05, 0x49, 0x4a, -+ 0x43, 0x4a, 0x4b, 0x44, 0x49, 0x52, 0x4a, 0x03, 0x4a, 0x52, 0x52, 0x4b, 0x43, 0x05, 0x06, 0x05, -+ 0x16, 0x48, 0x13, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x03, 0x07, 0x18, 0x09, 0x48, -+ 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x47, -+ 0x07, 0x06, 0x06, 0x0d, 0x16, 0x0d, 0x16, 0x10, 0x17, 0x09, 0x48, 0x17, 0x09, 0x48, 0x40, 0x40, -+ 0x40, 0x1a, 0x1a, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x11, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0f, -+ 0x00, 0x2a, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x11, 0x0d, 0x10, 0x14, 0x0e, 0x0d, 0x10, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x47, 0x0e, 0x40, 0x51, 0x40, 0x11, 0x47, 0x4e, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, -+ 0x40, 0x42, 0x49, 0x0e, 0x4a, 0x42, 0x04, 0x13, 0x13, 0x07, 0x07, 0x08, 0x41, 0x07, 0x42, 0x07, -+ 0x51, 0x27, 0x0e, 0x10, 0x40, 0x48, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x42, 0x49, -+ 0x4a, 0x42, 0x49, 0x51, 0x49, 0x05, 0x49, 0x51, 0x51, 0x4a, 0x42, 0x06, 0x06, 0x06, 0x49, 0x49, -+ 0x42, 0x49, 0x4a, 0x42, 0x49, 0x51, 0x49, 0x05, 0x49, 0x51, 0x51, 0x4a, 0x42, 0x06, 0x06, 0x06, -+ 0x16, 0x48, 0x14, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x04, 0x07, 0x18, 0x08, 0x48, -+ 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47, -+ 0x07, 0x06, 0x06, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40, -+ 0x40, 0x19, 0x19, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0f, -+ 0x00, 0x29, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x10, 0x0e, 0x10, 0x15, 0x0e, 0x0e, 0x10, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x47, 0x0f, 0x40, 0x50, 0x40, 0x10, 0x47, 0x4f, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, -+ 0x40, 0x40, 0x48, 0x0f, 0x48, 0x40, 0x06, 0x16, 0x16, 0x07, 0x07, 0x08, 0x40, 0x07, 0x40, 0x07, -+ 0x50, 0x27, 0x0f, 0x10, 0x40, 0x48, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48, -+ 0x48, 0x40, 0x48, 0x50, 0x48, 0x07, 0x48, 0x50, 0x50, 0x48, 0x40, 0x07, 0x07, 0x07, 0x48, 0x48, -+ 0x40, 0x48, 0x48, 0x40, 0x48, 0x50, 0x48, 0x07, 0x48, 0x50, 0x50, 0x48, 0x40, 0x07, 0x07, 0x07, -+ 0x17, 0x48, 0x16, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x07, 0x07, 0x06, 0x07, 0x18, 0x08, 0x48, -+ 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47, -+ 0x07, 0x07, 0x07, 0x0f, 0x17, 0x0f, 0x17, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40, -+ 0x40, 0x18, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x17, 0x17, 0x0f, -+ 0x00, 0x28, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x10, 0x0f, 0x10, 0x17, 0x0f, 0x0f, 0x10, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x48, 0x10, 0x00, 0x4f, 0x40, 0x0f, 0x48, 0x50, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f, -+ 0x00, 0x00, 0x47, 0x10, 0x47, 0x00, 0x08, 0x18, 0x18, 0x07, 0x07, 0x07, 0x00, 0x08, 0x00, 0x07, -+ 0x4f, 0x27, 0x10, 0x0f, 0x40, 0x47, 0x07, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47, -+ 0x47, 0x00, 0x47, 0x4f, 0x47, 0x08, 0x47, 0x4f, 0x4f, 0x47, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47, -+ 0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x47, 0x08, 0x47, 0x4f, 0x4f, 0x47, 0x00, 0x08, 0x08, 0x08, -+ 0x18, 0x47, 0x18, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x08, 0x07, 0x17, 0x07, 0x47, -+ 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, -+ 0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, -+ 0x40, 0x17, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, -+ 0x40, 0x27, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0f, 0x10, 0x0f, 0x18, 0x10, 0x10, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x48, 0x11, 0x00, 0x4f, 0x40, 0x0e, 0x48, 0x51, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f, -+ 0x00, 0x02, 0x46, 0x10, 0x46, 0x02, 0x0a, 0x1b, 0x1b, 0x07, 0x07, 0x07, 0x00, 0x08, 0x01, 0x07, -+ 0x4e, 0x27, 0x11, 0x0f, 0x40, 0x47, 0x06, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x46, 0x01, 0x46, -+ 0x46, 0x02, 0x47, 0x4e, 0x46, 0x0a, 0x46, 0x4e, 0x4e, 0x46, 0x01, 0x09, 0x08, 0x09, 0x47, 0x46, -+ 0x01, 0x46, 0x46, 0x02, 0x47, 0x4e, 0x46, 0x0a, 0x46, 0x4e, 0x4e, 0x46, 0x01, 0x09, 0x08, 0x09, -+ 0x18, 0x47, 0x1a, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x0a, 0x07, 0x17, 0x07, 0x47, -+ 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, -+ 0x07, 0x08, 0x08, 0x11, 0x18, 0x11, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, -+ 0x40, 0x16, 0x16, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, -+ 0x40, 0x26, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0f, 0x11, 0x0f, 0x19, 0x10, 0x11, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x49, 0x12, 0x00, 0x4e, 0x40, 0x0d, 0x49, 0x52, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f, -+ 0x00, 0x03, 0x45, 0x11, 0x45, 0x03, 0x0c, 0x1d, 0x1d, 0x07, 0x07, 0x07, 0x01, 0x08, 0x02, 0x07, -+ 0x4d, 0x27, 0x12, 0x0f, 0x40, 0x47, 0x05, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x45, 0x02, 0x45, -+ 0x45, 0x03, 0x46, 0x4d, 0x45, 0x0b, 0x45, 0x4d, 0x4d, 0x45, 0x02, 0x0a, 0x09, 0x0a, 0x46, 0x45, -+ 0x02, 0x45, 0x45, 0x03, 0x46, 0x4d, 0x45, 0x0b, 0x45, 0x4d, 0x4d, 0x45, 0x02, 0x0a, 0x09, 0x0a, -+ 0x19, 0x47, 0x1c, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x09, 0x09, 0x0c, 0x07, 0x17, 0x06, 0x47, -+ 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x48, -+ 0x07, 0x09, 0x09, 0x12, 0x19, 0x12, 0x19, 0x0f, 0x17, 0x06, 0x47, 0x17, 0x06, 0x47, 0x40, 0x40, -+ 0x40, 0x15, 0x15, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x0e, 0x28, 0x27, 0x18, 0x07, 0x19, 0x18, 0x10, -+ 0x40, 0x25, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0e, 0x12, 0x0f, 0x1a, 0x11, 0x12, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4a, 0x13, 0x01, 0x4d, 0x40, 0x0c, 0x4a, 0x53, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, -+ 0x01, 0x05, 0x44, 0x12, 0x43, 0x05, 0x0e, 0x20, 0x20, 0x07, 0x07, 0x06, 0x02, 0x09, 0x04, 0x07, -+ 0x4c, 0x27, 0x13, 0x0e, 0x40, 0x46, 0x04, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x44, 0x04, 0x44, -+ 0x43, 0x05, 0x45, 0x4c, 0x44, 0x0d, 0x44, 0x4c, 0x4c, 0x43, 0x04, 0x0b, 0x0a, 0x0b, 0x45, 0x44, -+ 0x04, 0x44, 0x43, 0x05, 0x45, 0x4c, 0x44, 0x0d, 0x44, 0x4c, 0x4c, 0x43, 0x04, 0x0b, 0x0a, 0x0b, -+ 0x1a, 0x46, 0x1e, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x0e, 0x07, 0x16, 0x05, 0x46, -+ 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, -+ 0x07, 0x0a, 0x0a, 0x13, 0x1a, 0x13, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, -+ 0x40, 0x14, 0x14, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x11, -+ 0x41, 0x24, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0d, 0x13, 0x0e, 0x1c, 0x12, 0x13, 0x0e, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4a, 0x14, 0x01, 0x4d, 0x40, 0x0b, 0x4a, 0x54, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, -+ 0x01, 0x06, 0x43, 0x12, 0x42, 0x06, 0x10, 0x22, 0x22, 0x07, 0x07, 0x06, 0x02, 0x09, 0x05, 0x07, -+ 0x4b, 0x27, 0x14, 0x0e, 0x40, 0x46, 0x03, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x43, 0x05, 0x43, -+ 0x42, 0x06, 0x45, 0x4b, 0x43, 0x0e, 0x43, 0x4b, 0x4b, 0x42, 0x05, 0x0c, 0x0a, 0x0c, 0x45, 0x43, -+ 0x05, 0x43, 0x42, 0x06, 0x45, 0x4b, 0x43, 0x0e, 0x43, 0x4b, 0x4b, 0x42, 0x05, 0x0c, 0x0a, 0x0c, -+ 0x1a, 0x46, 0x20, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x10, 0x07, 0x16, 0x05, 0x46, -+ 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, -+ 0x07, 0x0a, 0x0a, 0x14, 0x1a, 0x14, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, -+ 0x40, 0x13, 0x13, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x11, -+ 0x41, 0x23, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0d, 0x14, 0x0e, 0x1d, 0x12, 0x14, 0x0e, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4b, 0x15, 0x01, 0x4c, 0x40, 0x0a, 0x4b, 0x55, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, -+ 0x01, 0x08, 0x42, 0x13, 0x41, 0x08, 0x12, 0x25, 0x25, 0x07, 0x07, 0x06, 0x03, 0x09, 0x06, 0x07, -+ 0x4a, 0x27, 0x15, 0x0e, 0x40, 0x46, 0x02, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x06, 0x42, -+ 0x41, 0x08, 0x44, 0x4a, 0x42, 0x10, 0x42, 0x4a, 0x4a, 0x41, 0x06, 0x0d, 0x0b, 0x0d, 0x44, 0x42, -+ 0x06, 0x42, 0x41, 0x08, 0x44, 0x4a, 0x42, 0x10, 0x42, 0x4a, 0x4a, 0x41, 0x06, 0x0d, 0x0b, 0x0d, -+ 0x1b, 0x46, 0x22, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x12, 0x07, 0x16, 0x04, 0x46, -+ 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x49, -+ 0x07, 0x0b, 0x0b, 0x15, 0x1b, 0x15, 0x1b, 0x0e, 0x17, 0x04, 0x46, 0x17, 0x04, 0x46, 0x40, 0x40, -+ 0x40, 0x12, 0x12, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x0c, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x11, -+ 0x41, 0x22, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0c, 0x15, 0x0e, 0x1e, 0x13, 0x15, 0x0e, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4c, 0x15, 0x01, 0x4c, 0x40, 0x09, 0x4c, 0x56, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, -+ 0x01, 0x09, 0x42, 0x13, 0x40, 0x09, 0x13, 0x27, 0x27, 0x07, 0x07, 0x05, 0x03, 0x09, 0x07, 0x07, -+ 0x4a, 0x27, 0x15, 0x0d, 0x40, 0x46, 0x01, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x07, 0x42, -+ 0x40, 0x09, 0x44, 0x4a, 0x42, 0x11, 0x42, 0x4a, 0x4a, 0x40, 0x07, 0x0d, 0x0b, 0x0d, 0x44, 0x42, -+ 0x07, 0x42, 0x40, 0x09, 0x44, 0x4a, 0x42, 0x11, 0x42, 0x4a, 0x4a, 0x40, 0x07, 0x0d, 0x0b, 0x0d, -+ 0x1b, 0x46, 0x23, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x13, 0x07, 0x15, 0x03, 0x46, -+ 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x4a, -+ 0x07, 0x0b, 0x0b, 0x15, 0x1b, 0x15, 0x1b, 0x0d, 0x17, 0x03, 0x46, 0x17, 0x03, 0x46, 0x40, 0x40, -+ 0x40, 0x11, 0x11, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x11, -+ 0x42, 0x21, 0x15, 0x0d, 0x40, 0x0d, 0x11, 0x0b, 0x15, 0x0d, 0x1f, 0x13, 0x15, 0x0d, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4c, 0x16, 0x02, 0x4b, 0x40, 0x09, 0x4c, 0x56, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f, -+ 0x02, 0x0b, 0x41, 0x14, 0x01, 0x0b, 0x15, 0x2a, 0x2a, 0x07, 0x07, 0x05, 0x04, 0x0a, 0x09, 0x07, -+ 0x49, 0x27, 0x16, 0x0d, 0x40, 0x45, 0x01, 0x40, 0x40, 0x40, 0x02, 0x02, 0x43, 0x41, 0x09, 0x41, -+ 0x01, 0x0b, 0x43, 0x49, 0x41, 0x13, 0x41, 0x49, 0x49, 0x01, 0x09, 0x0e, 0x0c, 0x0e, 0x43, 0x41, -+ 0x09, 0x41, 0x01, 0x0b, 0x43, 0x49, 0x41, 0x13, 0x41, 0x49, 0x49, 0x01, 0x09, 0x0e, 0x0c, 0x0e, -+ 0x1c, 0x45, 0x25, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0c, 0x0c, 0x15, 0x07, 0x15, 0x03, 0x45, -+ 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x4a, -+ 0x07, 0x0c, 0x0c, 0x16, 0x1c, 0x16, 0x1c, 0x0d, 0x17, 0x03, 0x45, 0x17, 0x03, 0x45, 0x40, 0x40, -+ 0x40, 0x11, 0x11, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x2a, 0x27, 0x1a, 0x07, 0x1c, 0x1a, 0x12, -+ 0x42, 0x21, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0b, 0x16, 0x0d, 0x21, 0x14, 0x16, 0x0d, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4d, 0x17, 0x02, 0x4a, 0x40, 0x08, 0x4d, 0x57, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f, -+ 0x02, 0x0d, 0x40, 0x15, 0x02, 0x0d, 0x17, 0x2c, 0x2c, 0x07, 0x07, 0x05, 0x05, 0x0a, 0x0a, 0x07, -+ 0x48, 0x27, 0x17, 0x0d, 0x40, 0x45, 0x00, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x40, 0x0a, 0x40, -+ 0x02, 0x0d, 0x42, 0x48, 0x40, 0x15, 0x40, 0x48, 0x48, 0x02, 0x0a, 0x0f, 0x0d, 0x0f, 0x42, 0x40, -+ 0x0a, 0x40, 0x02, 0x0d, 0x42, 0x48, 0x40, 0x15, 0x40, 0x48, 0x48, 0x02, 0x0a, 0x0f, 0x0d, 0x0f, -+ 0x1d, 0x45, 0x27, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x17, 0x07, 0x15, 0x02, 0x45, -+ 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, -+ 0x07, 0x0d, 0x0d, 0x17, 0x1d, 0x17, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, -+ 0x40, 0x10, 0x10, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x12, -+ 0x42, 0x20, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0a, 0x17, 0x0d, 0x22, 0x15, 0x17, 0x0d, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4d, 0x18, 0x02, 0x4a, 0x40, 0x07, 0x4d, 0x58, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f, -+ 0x02, 0x0e, 0x00, 0x15, 0x03, 0x0e, 0x19, 0x2f, 0x2f, 0x07, 0x07, 0x05, 0x05, 0x0a, 0x0b, 0x07, -+ 0x47, 0x27, 0x18, 0x0d, 0x40, 0x45, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x00, 0x0b, 0x00, -+ 0x03, 0x0e, 0x42, 0x47, 0x00, 0x16, 0x00, 0x47, 0x47, 0x03, 0x0b, 0x10, 0x0d, 0x10, 0x42, 0x00, -+ 0x0b, 0x00, 0x03, 0x0e, 0x42, 0x47, 0x00, 0x16, 0x00, 0x47, 0x47, 0x03, 0x0b, 0x10, 0x0d, 0x10, -+ 0x1d, 0x45, 0x29, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x19, 0x07, 0x15, 0x02, 0x45, -+ 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, -+ 0x07, 0x0d, 0x0d, 0x18, 0x1d, 0x18, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, -+ 0x40, 0x0f, 0x0f, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x12, -+ 0x42, 0x1f, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0a, 0x18, 0x0d, 0x23, 0x15, 0x18, 0x0d, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4e, 0x19, 0x03, 0x49, 0x40, 0x06, 0x4e, 0x59, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f, -+ 0x03, 0x10, 0x01, 0x16, 0x04, 0x10, 0x1b, 0x31, 0x31, 0x07, 0x07, 0x04, 0x06, 0x0b, 0x0c, 0x07, -+ 0x46, 0x27, 0x19, 0x0c, 0x40, 0x44, 0x41, 0x40, 0x40, 0x40, 0x03, 0x03, 0x41, 0x01, 0x0c, 0x01, -+ 0x04, 0x10, 0x41, 0x46, 0x01, 0x18, 0x01, 0x46, 0x46, 0x04, 0x0c, 0x11, 0x0e, 0x11, 0x41, 0x01, -+ 0x0c, 0x01, 0x04, 0x10, 0x41, 0x46, 0x01, 0x18, 0x01, 0x46, 0x46, 0x04, 0x0c, 0x11, 0x0e, 0x11, -+ 0x1e, 0x44, 0x2b, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0e, 0x0e, 0x1b, 0x07, 0x14, 0x01, 0x44, -+ 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x4b, -+ 0x07, 0x0e, 0x0e, 0x19, 0x1e, 0x19, 0x1e, 0x0c, 0x17, 0x01, 0x44, 0x17, 0x01, 0x44, 0x40, 0x40, -+ 0x40, 0x0e, 0x0e, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x09, 0x2b, 0x27, 0x1b, 0x07, 0x1e, 0x1b, 0x13, -+ 0x43, 0x1e, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x09, 0x19, 0x0c, 0x24, 0x16, 0x19, 0x0c, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4f, 0x1a, 0x03, 0x48, 0x40, 0x05, 0x4f, 0x5a, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f, -+ 0x03, 0x11, 0x02, 0x17, 0x06, 0x11, 0x1d, 0x34, 0x34, 0x07, 0x07, 0x04, 0x07, 0x0b, 0x0e, 0x07, -+ 0x45, 0x27, 0x1a, 0x0c, 0x40, 0x44, 0x42, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x02, 0x0e, 0x02, -+ 0x06, 0x11, 0x40, 0x45, 0x02, 0x19, 0x02, 0x45, 0x45, 0x06, 0x0e, 0x12, 0x0f, 0x12, 0x40, 0x02, -+ 0x0e, 0x02, 0x06, 0x11, 0x40, 0x45, 0x02, 0x19, 0x02, 0x45, 0x45, 0x06, 0x0e, 0x12, 0x0f, 0x12, -+ 0x1f, 0x44, 0x2d, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1d, 0x07, 0x14, 0x00, 0x44, -+ 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, -+ 0x07, 0x0f, 0x0f, 0x1a, 0x1f, 0x1a, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, -+ 0x40, 0x0d, 0x0d, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x13, -+ 0x43, 0x1d, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x08, 0x1a, 0x0c, 0x26, 0x17, 0x1a, 0x0c, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x4f, 0x1b, 0x03, 0x48, 0x40, 0x04, 0x4f, 0x5b, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f, -+ 0x03, 0x13, 0x03, 0x17, 0x07, 0x13, 0x1f, 0x36, 0x36, 0x07, 0x07, 0x04, 0x07, 0x0b, 0x0f, 0x07, -+ 0x44, 0x27, 0x1b, 0x0c, 0x40, 0x44, 0x43, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x03, 0x0f, 0x03, -+ 0x07, 0x13, 0x40, 0x44, 0x03, 0x1b, 0x03, 0x44, 0x44, 0x07, 0x0f, 0x13, 0x0f, 0x13, 0x40, 0x03, -+ 0x0f, 0x03, 0x07, 0x13, 0x40, 0x44, 0x03, 0x1b, 0x03, 0x44, 0x44, 0x07, 0x0f, 0x13, 0x0f, 0x13, -+ 0x1f, 0x44, 0x2f, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1f, 0x07, 0x14, 0x00, 0x44, -+ 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, -+ 0x07, 0x0f, 0x0f, 0x1b, 0x1f, 0x1b, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, -+ 0x40, 0x0c, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x13, -+ 0x43, 0x1c, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x08, 0x1b, 0x0c, 0x27, 0x17, 0x1b, 0x0c, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x50, 0x1c, 0x04, 0x47, 0x40, 0x03, 0x50, 0x5c, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, -+ 0x04, 0x14, 0x04, 0x18, 0x08, 0x14, 0x21, 0x39, 0x39, 0x07, 0x07, 0x03, 0x08, 0x0c, 0x10, 0x07, -+ 0x43, 0x27, 0x1c, 0x0b, 0x40, 0x43, 0x44, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x04, 0x10, 0x04, -+ 0x08, 0x14, 0x00, 0x43, 0x04, 0x1c, 0x04, 0x43, 0x43, 0x08, 0x10, 0x14, 0x10, 0x14, 0x00, 0x04, -+ 0x10, 0x04, 0x08, 0x14, 0x00, 0x43, 0x04, 0x1c, 0x04, 0x43, 0x43, 0x08, 0x10, 0x14, 0x10, 0x14, -+ 0x20, 0x43, 0x31, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x21, 0x07, 0x13, 0x40, 0x43, -+ 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x4c, -+ 0x07, 0x10, 0x10, 0x1c, 0x20, 0x1c, 0x20, 0x0b, 0x17, 0x40, 0x43, 0x17, 0x40, 0x43, 0x40, 0x40, -+ 0x40, 0x0b, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x07, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x14, -+ 0x44, 0x1b, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x07, 0x1c, 0x0b, 0x28, 0x18, 0x1c, 0x0b, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x51, 0x1d, 0x04, 0x47, 0x40, 0x02, 0x51, 0x5d, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, -+ 0x04, 0x16, 0x05, 0x18, 0x09, 0x16, 0x22, 0x3b, 0x3b, 0x07, 0x07, 0x03, 0x08, 0x0c, 0x11, 0x07, -+ 0x42, 0x27, 0x1d, 0x0b, 0x40, 0x43, 0x45, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x05, 0x11, 0x05, -+ 0x09, 0x16, 0x00, 0x42, 0x05, 0x1e, 0x05, 0x42, 0x42, 0x09, 0x11, 0x15, 0x10, 0x15, 0x00, 0x05, -+ 0x11, 0x05, 0x09, 0x16, 0x00, 0x42, 0x05, 0x1e, 0x05, 0x42, 0x42, 0x09, 0x11, 0x15, 0x10, 0x15, -+ 0x20, 0x43, 0x32, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x22, 0x07, 0x13, 0x41, 0x43, -+ 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, -+ 0x07, 0x10, 0x10, 0x1d, 0x20, 0x1d, 0x20, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, -+ 0x40, 0x0a, 0x0a, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x14, -+ 0x44, 0x1a, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x06, 0x1d, 0x0b, 0x29, 0x18, 0x1d, 0x0b, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x51, 0x1e, 0x04, 0x46, 0x40, 0x01, 0x51, 0x5e, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, -+ 0x04, 0x18, 0x06, 0x19, 0x0b, 0x18, 0x24, 0x3e, 0x3e, 0x07, 0x07, 0x03, 0x09, 0x0c, 0x13, 0x07, -+ 0x41, 0x27, 0x1e, 0x0b, 0x40, 0x43, 0x46, 0x40, 0x40, 0x40, 0x04, 0x04, 0x01, 0x06, 0x13, 0x06, -+ 0x0b, 0x18, 0x01, 0x41, 0x06, 0x20, 0x06, 0x41, 0x41, 0x0b, 0x13, 0x16, 0x11, 0x16, 0x01, 0x06, -+ 0x13, 0x06, 0x0b, 0x18, 0x01, 0x41, 0x06, 0x20, 0x06, 0x41, 0x41, 0x0b, 0x13, 0x16, 0x11, 0x16, -+ 0x21, 0x43, 0x34, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x11, 0x11, 0x24, 0x07, 0x13, 0x41, 0x43, -+ 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, -+ 0x07, 0x11, 0x11, 0x1e, 0x21, 0x1e, 0x21, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, -+ 0x40, 0x09, 0x09, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x21, 0x1c, 0x14, -+ 0x44, 0x19, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x06, 0x1e, 0x0b, 0x2b, 0x19, 0x1e, 0x0b, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x52, 0x1f, 0x05, 0x45, 0x40, 0x00, 0x52, 0x5f, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f, -+ 0x05, 0x19, 0x07, 0x1a, 0x0c, 0x19, 0x26, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0a, 0x0d, 0x14, 0x07, -+ 0x40, 0x27, 0x1f, 0x0a, 0x40, 0x42, 0x47, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x07, 0x14, 0x07, -+ 0x0c, 0x19, 0x02, 0x40, 0x07, 0x21, 0x07, 0x40, 0x40, 0x0c, 0x14, 0x17, 0x12, 0x17, 0x02, 0x07, -+ 0x14, 0x07, 0x0c, 0x19, 0x02, 0x40, 0x07, 0x21, 0x07, 0x40, 0x40, 0x0c, 0x14, 0x17, 0x12, 0x17, -+ 0x22, 0x42, 0x36, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x26, 0x07, 0x12, 0x42, 0x42, -+ 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d, -+ 0x07, 0x12, 0x12, 0x1f, 0x22, 0x1f, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40, -+ 0x40, 0x08, 0x08, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x15, -+ 0x45, 0x18, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x05, 0x1f, 0x0a, 0x2c, 0x1a, 0x1f, 0x0a, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x52, 0x20, 0x05, 0x45, 0x40, 0x40, 0x52, 0x60, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f, -+ 0x05, 0x1b, 0x08, 0x1a, 0x0d, 0x1b, 0x28, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0a, 0x0d, 0x15, 0x07, -+ 0x00, 0x27, 0x20, 0x0a, 0x40, 0x42, 0x48, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x08, 0x15, 0x08, -+ 0x0d, 0x1b, 0x02, 0x00, 0x08, 0x23, 0x08, 0x00, 0x00, 0x0d, 0x15, 0x18, 0x12, 0x18, 0x02, 0x08, -+ 0x15, 0x08, 0x0d, 0x1b, 0x02, 0x00, 0x08, 0x23, 0x08, 0x00, 0x00, 0x0d, 0x15, 0x18, 0x12, 0x18, -+ 0x22, 0x42, 0x38, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x28, 0x07, 0x12, 0x42, 0x42, -+ 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d, -+ 0x07, 0x12, 0x12, 0x20, 0x22, 0x20, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40, -+ 0x40, 0x07, 0x07, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x15, -+ 0x45, 0x17, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x05, 0x20, 0x0a, 0x2d, 0x1a, 0x20, 0x0a, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x53, 0x21, 0x05, 0x44, 0x40, 0x41, 0x53, 0x61, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f, -+ 0x05, 0x1c, 0x09, 0x1b, 0x0e, 0x1c, 0x2a, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0d, 0x16, 0x07, -+ 0x01, 0x27, 0x21, 0x0a, 0x40, 0x42, 0x49, 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x16, 0x09, -+ 0x0e, 0x1c, 0x03, 0x01, 0x09, 0x24, 0x09, 0x01, 0x01, 0x0e, 0x16, 0x19, 0x13, 0x19, 0x03, 0x09, -+ 0x16, 0x09, 0x0e, 0x1c, 0x03, 0x01, 0x09, 0x24, 0x09, 0x01, 0x01, 0x0e, 0x16, 0x19, 0x13, 0x19, -+ 0x23, 0x42, 0x3a, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x07, 0x12, 0x43, 0x42, -+ 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d, -+ 0x07, 0x13, 0x13, 0x21, 0x23, 0x21, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, 0x40, -+ 0x40, 0x06, 0x06, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, 0x1d, 0x15, -+ 0x45, 0x16, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x04, 0x21, 0x0a, 0x2e, 0x1b, 0x21, 0x0a, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x54, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, -+ 0x06, 0x1e, 0x0a, 0x1c, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0c, 0x0e, 0x18, 0x07, -+ 0x02, 0x27, 0x22, 0x09, 0x40, 0x41, 0x4a, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0a, 0x18, 0x0a, -+ 0x10, 0x1e, 0x04, 0x02, 0x0a, 0x26, 0x0a, 0x02, 0x02, 0x10, 0x18, 0x1a, 0x14, 0x1a, 0x04, 0x0a, -+ 0x18, 0x0a, 0x10, 0x1e, 0x04, 0x02, 0x0a, 0x26, 0x0a, 0x02, 0x02, 0x10, 0x18, 0x1a, 0x14, 0x1a, -+ 0x24, 0x41, 0x3c, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2c, 0x07, 0x11, 0x44, 0x41, -+ 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, -+ 0x07, 0x14, 0x14, 0x22, 0x24, 0x22, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, -+ 0x40, 0x05, 0x05, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x16, -+ 0x46, 0x15, 0x11, 0x09, 0x40, 0x09, 0x16, 0x03, 0x22, 0x09, 0x30, 0x1c, 0x22, 0x09, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x54, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, -+ 0x06, 0x1f, 0x0b, 0x1c, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0c, 0x0e, 0x19, 0x07, -+ 0x03, 0x27, 0x23, 0x09, 0x40, 0x41, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x19, 0x0b, -+ 0x11, 0x1f, 0x04, 0x03, 0x0b, 0x27, 0x0b, 0x03, 0x03, 0x11, 0x19, 0x1b, 0x14, 0x1b, 0x04, 0x0b, -+ 0x19, 0x0b, 0x11, 0x1f, 0x04, 0x03, 0x0b, 0x27, 0x0b, 0x03, 0x03, 0x11, 0x19, 0x1b, 0x14, 0x1b, -+ 0x24, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, 0x07, 0x11, 0x44, 0x41, -+ 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, -+ 0x07, 0x14, 0x14, 0x23, 0x24, 0x23, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, -+ 0x40, 0x04, 0x04, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x16, -+ 0x46, 0x14, 0x11, 0x09, 0x40, 0x09, 0x16, 0x03, 0x23, 0x09, 0x31, 0x1c, 0x23, 0x09, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x55, 0x24, 0x06, 0x42, 0x40, 0x44, 0x55, 0x64, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, -+ 0x06, 0x21, 0x0c, 0x1d, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0d, 0x0e, 0x1a, 0x07, -+ 0x04, 0x27, 0x24, 0x09, 0x40, 0x41, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x1a, 0x0c, -+ 0x12, 0x21, 0x05, 0x04, 0x0c, 0x29, 0x0c, 0x04, 0x04, 0x12, 0x1a, 0x1c, 0x15, 0x1c, 0x05, 0x0c, -+ 0x1a, 0x0c, 0x12, 0x21, 0x05, 0x04, 0x0c, 0x29, 0x0c, 0x04, 0x04, 0x12, 0x1a, 0x1c, 0x15, 0x1c, -+ 0x25, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x07, 0x11, 0x45, 0x41, -+ 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x4e, -+ 0x07, 0x15, 0x15, 0x24, 0x25, 0x24, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, 0x40, 0x40, -+ 0x40, 0x03, 0x03, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x16, -+ 0x46, 0x13, 0x11, 0x09, 0x40, 0x09, 0x16, 0x02, 0x24, 0x09, 0x32, 0x1d, 0x24, 0x09, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x56, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, -+ 0x06, 0x22, 0x0c, 0x1d, 0x13, 0x22, 0x31, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0d, 0x0e, 0x1b, 0x07, -+ 0x04, 0x27, 0x24, 0x08, 0x40, 0x41, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x1b, 0x0c, -+ 0x13, 0x22, 0x05, 0x04, 0x0c, 0x2a, 0x0c, 0x04, 0x04, 0x13, 0x1b, 0x1c, 0x15, 0x1c, 0x05, 0x0c, -+ 0x1b, 0x0c, 0x13, 0x22, 0x05, 0x04, 0x0c, 0x2a, 0x0c, 0x04, 0x04, 0x13, 0x1b, 0x1c, 0x15, 0x1c, -+ 0x25, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x07, 0x10, 0x46, 0x41, -+ 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f, -+ 0x07, 0x15, 0x15, 0x24, 0x25, 0x24, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40, -+ 0x40, 0x02, 0x02, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x16, -+ 0x47, 0x12, 0x10, 0x08, 0x40, 0x08, 0x16, 0x01, 0x24, 0x08, 0x33, 0x1d, 0x24, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x56, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f, -+ 0x07, 0x24, 0x0d, 0x1e, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0e, 0x0f, 0x1d, 0x07, -+ 0x05, 0x27, 0x25, 0x08, 0x40, 0x40, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x1d, 0x0d, -+ 0x15, 0x24, 0x06, 0x05, 0x0d, 0x2c, 0x0d, 0x05, 0x05, 0x15, 0x1d, 0x1d, 0x16, 0x1d, 0x06, 0x0d, -+ 0x1d, 0x0d, 0x15, 0x24, 0x06, 0x05, 0x0d, 0x2c, 0x0d, 0x05, 0x05, 0x15, 0x1d, 0x1d, 0x16, 0x1d, -+ 0x26, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x07, 0x10, 0x46, 0x40, -+ 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f, -+ 0x07, 0x16, 0x16, 0x25, 0x26, 0x25, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40, -+ 0x40, 0x02, 0x02, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x17, -+ 0x47, 0x12, 0x10, 0x08, 0x40, 0x08, 0x17, 0x01, 0x25, 0x08, 0x35, 0x1e, 0x25, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x57, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f, -+ 0x07, 0x26, 0x0e, 0x1f, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0f, 0x0f, 0x1e, 0x07, -+ 0x06, 0x27, 0x26, 0x08, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x1e, 0x0e, -+ 0x16, 0x26, 0x07, 0x06, 0x0e, 0x2e, 0x0e, 0x06, 0x06, 0x16, 0x1e, 0x1e, 0x17, 0x1e, 0x07, 0x0e, -+ 0x1e, 0x0e, 0x16, 0x26, 0x07, 0x06, 0x0e, 0x2e, 0x0e, 0x06, 0x06, 0x16, 0x1e, 0x1e, 0x17, 0x1e, -+ 0x27, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x07, 0x10, 0x47, 0x40, -+ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, -+ 0x07, 0x17, 0x17, 0x26, 0x27, 0x26, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, -+ 0x40, 0x01, 0x01, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x17, -+ 0x47, 0x11, 0x10, 0x08, 0x40, 0x08, 0x17, 0x00, 0x26, 0x08, 0x36, 0x1f, 0x26, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x57, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f, -+ 0x07, 0x27, 0x0f, 0x1f, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0f, 0x0f, 0x1f, 0x07, -+ 0x07, 0x27, 0x27, 0x08, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x1f, 0x0f, -+ 0x17, 0x27, 0x07, 0x07, 0x0f, 0x2f, 0x0f, 0x07, 0x07, 0x17, 0x1f, 0x1f, 0x17, 0x1f, 0x07, 0x0f, -+ 0x1f, 0x0f, 0x17, 0x27, 0x07, 0x07, 0x0f, 0x2f, 0x0f, 0x07, 0x07, 0x17, 0x1f, 0x1f, 0x17, 0x1f, -+ 0x27, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x07, 0x10, 0x47, 0x40, -+ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, -+ 0x07, 0x17, 0x17, 0x27, 0x27, 0x27, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, -+ 0x40, 0x00, 0x00, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x17, -+ 0x47, 0x10, 0x10, 0x08, 0x40, 0x08, 0x17, 0x00, 0x27, 0x08, 0x37, 0x1f, 0x27, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x48, 0x48, 0x60, 0x40, 0x27, 0x07, 0x07, 0x1f, 0x40, 0x48, 0x40, 0x40, 0x17, 0x0f, -+ 0x48, 0x68, 0x40, 0x07, 0x68, 0x68, 0x68, 0x68, 0x68, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x40, 0x07, -+ 0x68, 0x27, 0x50, 0x17, 0x40, 0x07, 0x1f, 0x40, 0x40, 0x40, 0x48, 0x48, 0x58, 0x60, 0x50, 0x60, -+ 0x68, 0x60, 0x58, 0x68, 0x68, 0x68, 0x58, 0x60, 0x68, 0x68, 0x68, 0x50, 0x48, 0x58, 0x58, 0x60, -+ 0x50, 0x60, 0x68, 0x60, 0x58, 0x68, 0x68, 0x68, 0x58, 0x60, 0x68, 0x68, 0x68, 0x50, 0x48, 0x58, -+ 0x07, 0x50, 0x58, 0x40, 0x40, 0x40, 0x48, 0x07, 0x48, 0x48, 0x48, 0x68, 0x50, 0x1f, 0x17, 0x50, -+ 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x40, -+ 0x07, 0x40, 0x40, 0x40, 0x07, 0x40, 0x07, 0x17, 0x17, 0x17, 0x50, 0x17, 0x17, 0x50, 0x40, 0x40, -+ 0x40, 0x2f, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x1f, 0x27, 0x0f, 0x07, 0x07, 0x0f, 0x40, -+ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x48, 0x17, 0x48, 0x48, 0x48, 0x17, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x47, 0x47, 0x5f, 0x40, 0x27, 0x07, 0x07, 0x20, 0x40, 0x47, 0x40, 0x40, 0x17, 0x0f, -+ 0x47, 0x66, 0x40, 0x08, 0x66, 0x66, 0x66, 0x65, 0x65, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x00, 0x07, -+ 0x67, 0x27, 0x4e, 0x17, 0x40, 0x07, 0x1f, 0x40, 0x40, 0x40, 0x47, 0x47, 0x57, 0x5f, 0x4f, 0x5f, -+ 0x66, 0x5e, 0x57, 0x67, 0x67, 0x66, 0x57, 0x5f, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x56, 0x57, 0x5f, -+ 0x4f, 0x5f, 0x66, 0x5e, 0x57, 0x67, 0x67, 0x66, 0x57, 0x5f, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x56, -+ 0x08, 0x4f, 0x56, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x47, 0x47, 0x66, 0x4f, 0x1f, 0x17, 0x4f, -+ 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x40, -+ 0x07, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x17, 0x17, 0x17, 0x4f, 0x17, 0x17, 0x4f, 0x40, 0x40, -+ 0x40, 0x2f, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x20, 0x27, 0x10, 0x07, 0x08, 0x10, 0x00, -+ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x47, 0x17, 0x46, 0x47, 0x47, 0x17, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x46, 0x47, 0x5e, 0x40, 0x26, 0x06, 0x06, 0x20, 0x40, 0x47, 0x40, 0x40, 0x16, 0x0f, -+ 0x47, 0x64, 0x40, 0x08, 0x65, 0x64, 0x64, 0x63, 0x63, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x01, 0x07, -+ 0x66, 0x27, 0x4d, 0x17, 0x40, 0x07, 0x1e, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5e, 0x4e, 0x5e, -+ 0x65, 0x5d, 0x56, 0x66, 0x66, 0x64, 0x56, 0x5e, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x55, 0x56, 0x5e, -+ 0x4e, 0x5e, 0x65, 0x5d, 0x56, 0x66, 0x66, 0x64, 0x56, 0x5e, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x55, -+ 0x09, 0x4f, 0x54, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x64, 0x4e, 0x1f, 0x16, 0x4f, -+ 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40, -+ 0x07, 0x00, 0x00, 0x01, 0x09, 0x01, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40, -+ 0x40, 0x2e, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x01, -+ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x46, 0x17, 0x45, 0x46, 0x46, 0x17, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x45, 0x47, 0x5e, 0x40, 0x25, 0x06, 0x05, 0x20, 0x40, 0x47, 0x40, 0x40, 0x16, 0x0f, -+ 0x47, 0x63, 0x40, 0x08, 0x64, 0x63, 0x62, 0x60, 0x60, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x01, 0x07, -+ 0x65, 0x27, 0x4c, 0x17, 0x40, 0x07, 0x1d, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5d, 0x4e, 0x5d, -+ 0x64, 0x5c, 0x56, 0x65, 0x65, 0x63, 0x56, 0x5e, 0x65, 0x65, 0x63, 0x4d, 0x46, 0x54, 0x56, 0x5d, -+ 0x4e, 0x5d, 0x64, 0x5c, 0x56, 0x65, 0x65, 0x63, 0x56, 0x5e, 0x65, 0x65, 0x63, 0x4d, 0x46, 0x54, -+ 0x09, 0x4f, 0x52, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x62, 0x4e, 0x1f, 0x16, 0x4f, -+ 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40, -+ 0x07, 0x00, 0x00, 0x01, 0x09, 0x01, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40, -+ 0x40, 0x2d, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x01, -+ 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x45, 0x17, 0x44, 0x45, 0x45, 0x17, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x44, 0x46, 0x5d, 0x40, 0x24, 0x05, 0x04, 0x21, 0x40, 0x46, 0x40, 0x40, 0x15, 0x0f, -+ 0x46, 0x61, 0x40, 0x09, 0x63, 0x61, 0x60, 0x5e, 0x5e, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x02, 0x07, -+ 0x64, 0x27, 0x4b, 0x16, 0x40, 0x06, 0x1c, 0x40, 0x40, 0x40, 0x46, 0x46, 0x55, 0x5c, 0x4d, 0x5c, -+ 0x63, 0x5b, 0x55, 0x64, 0x64, 0x61, 0x55, 0x5d, 0x64, 0x64, 0x61, 0x4c, 0x45, 0x53, 0x55, 0x5c, -+ 0x4d, 0x5c, 0x63, 0x5b, 0x55, 0x64, 0x64, 0x61, 0x55, 0x5d, 0x64, 0x64, 0x61, 0x4c, 0x45, 0x53, -+ 0x0a, 0x4e, 0x50, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x45, 0x45, 0x60, 0x4d, 0x1e, 0x15, 0x4e, -+ 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x41, -+ 0x07, 0x01, 0x01, 0x02, 0x0a, 0x02, 0x0a, 0x16, 0x17, 0x15, 0x4e, 0x17, 0x15, 0x4e, 0x40, 0x40, -+ 0x40, 0x2c, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x1d, 0x21, 0x27, 0x11, 0x07, 0x0a, 0x11, 0x02, -+ 0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x44, 0x16, 0x43, 0x44, 0x44, 0x16, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x43, 0x46, 0x5c, 0x40, 0x23, 0x04, 0x03, 0x21, 0x40, 0x46, 0x40, 0x40, 0x14, 0x0f, -+ 0x46, 0x60, 0x40, 0x09, 0x61, 0x60, 0x5e, 0x5b, 0x5b, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x03, 0x07, -+ 0x63, 0x27, 0x49, 0x16, 0x40, 0x06, 0x1b, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5b, 0x4c, 0x5b, -+ 0x61, 0x59, 0x54, 0x63, 0x63, 0x60, 0x54, 0x5c, 0x63, 0x63, 0x60, 0x4b, 0x44, 0x51, 0x54, 0x5b, -+ 0x4c, 0x5b, 0x61, 0x59, 0x54, 0x63, 0x63, 0x60, 0x54, 0x5c, 0x63, 0x63, 0x60, 0x4b, 0x44, 0x51, -+ 0x0b, 0x4e, 0x4e, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5e, 0x4c, 0x1e, 0x14, 0x4e, -+ 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41, -+ 0x07, 0x01, 0x01, 0x03, 0x0b, 0x03, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40, -+ 0x40, 0x2b, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x03, -+ 0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x43, 0x16, 0x41, 0x43, 0x43, 0x16, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x42, 0x46, 0x5c, 0x40, 0x22, 0x04, 0x02, 0x21, 0x40, 0x46, 0x40, 0x40, 0x14, 0x0f, -+ 0x46, 0x5e, 0x40, 0x09, 0x60, 0x5e, 0x5c, 0x59, 0x59, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x03, 0x07, -+ 0x62, 0x27, 0x48, 0x16, 0x40, 0x06, 0x1a, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5a, 0x4c, 0x5a, -+ 0x60, 0x58, 0x54, 0x62, 0x62, 0x5e, 0x54, 0x5c, 0x62, 0x62, 0x5e, 0x4a, 0x44, 0x50, 0x54, 0x5a, -+ 0x4c, 0x5a, 0x60, 0x58, 0x54, 0x62, 0x62, 0x5e, 0x54, 0x5c, 0x62, 0x62, 0x5e, 0x4a, 0x44, 0x50, -+ 0x0b, 0x4e, 0x4c, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5c, 0x4c, 0x1e, 0x14, 0x4e, -+ 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41, -+ 0x07, 0x01, 0x01, 0x03, 0x0b, 0x03, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40, -+ 0x40, 0x2a, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x03, -+ 0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x42, 0x16, 0x40, 0x42, 0x42, 0x16, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x41, 0x45, 0x5b, 0x40, 0x21, 0x03, 0x01, 0x22, 0x40, 0x45, 0x40, 0x40, 0x13, 0x0f, -+ 0x45, 0x5d, 0x40, 0x0a, 0x5f, 0x5d, 0x5a, 0x56, 0x56, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x04, 0x07, -+ 0x61, 0x27, 0x47, 0x15, 0x40, 0x05, 0x19, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x59, 0x4b, 0x59, -+ 0x5f, 0x57, 0x53, 0x61, 0x61, 0x5d, 0x53, 0x5b, 0x61, 0x61, 0x5d, 0x49, 0x43, 0x4f, 0x53, 0x59, -+ 0x4b, 0x59, 0x5f, 0x57, 0x53, 0x61, 0x61, 0x5d, 0x53, 0x5b, 0x61, 0x61, 0x5d, 0x49, 0x43, 0x4f, -+ 0x0c, 0x4d, 0x4a, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x5a, 0x4b, 0x1d, 0x13, 0x4d, -+ 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x42, -+ 0x07, 0x02, 0x02, 0x04, 0x0c, 0x04, 0x0c, 0x15, 0x17, 0x13, 0x4d, 0x17, 0x13, 0x4d, 0x40, 0x40, -+ 0x40, 0x29, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x1b, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x04, -+ 0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x41, 0x15, 0x00, 0x41, 0x41, 0x15, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x40, 0x45, 0x5b, 0x40, 0x20, 0x02, 0x00, 0x22, 0x40, 0x45, 0x40, 0x40, 0x12, 0x0f, -+ 0x45, 0x5b, 0x40, 0x0a, 0x5e, 0x5b, 0x59, 0x54, 0x54, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x04, 0x07, -+ 0x60, 0x27, 0x46, 0x15, 0x40, 0x05, 0x18, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x58, 0x4b, 0x58, -+ 0x5e, 0x56, 0x53, 0x60, 0x60, 0x5b, 0x53, 0x5b, 0x60, 0x60, 0x5b, 0x48, 0x43, 0x4e, 0x53, 0x58, -+ 0x4b, 0x58, 0x5e, 0x56, 0x53, 0x60, 0x60, 0x5b, 0x53, 0x5b, 0x60, 0x60, 0x5b, 0x48, 0x43, 0x4e, -+ 0x0c, 0x4d, 0x49, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x59, 0x4b, 0x1d, 0x12, 0x4d, -+ 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42, -+ 0x07, 0x02, 0x02, 0x04, 0x0c, 0x04, 0x0c, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, -+ 0x40, 0x28, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x04, -+ 0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x40, 0x15, 0x01, 0x40, 0x40, 0x15, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x00, 0x45, 0x5a, 0x40, 0x1f, 0x02, 0x40, 0x22, 0x40, 0x45, 0x40, 0x40, 0x12, 0x0f, -+ 0x45, 0x59, 0x40, 0x0a, 0x5c, 0x59, 0x57, 0x51, 0x51, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x05, 0x07, -+ 0x5f, 0x27, 0x44, 0x15, 0x40, 0x05, 0x17, 0x40, 0x40, 0x40, 0x45, 0x45, 0x52, 0x57, 0x4a, 0x57, -+ 0x5c, 0x54, 0x52, 0x5f, 0x5f, 0x59, 0x52, 0x5a, 0x5f, 0x5f, 0x59, 0x47, 0x42, 0x4c, 0x52, 0x57, -+ 0x4a, 0x57, 0x5c, 0x54, 0x52, 0x5f, 0x5f, 0x59, 0x52, 0x5a, 0x5f, 0x5f, 0x59, 0x47, 0x42, 0x4c, -+ 0x0d, 0x4d, 0x47, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x42, 0x42, 0x57, 0x4a, 0x1d, 0x12, 0x4d, -+ 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42, -+ 0x07, 0x02, 0x02, 0x05, 0x0d, 0x05, 0x0d, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, -+ 0x40, 0x27, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0d, 0x12, 0x05, -+ 0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x00, 0x15, 0x03, 0x00, 0x00, 0x15, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x01, 0x44, 0x59, 0x40, 0x1e, 0x01, 0x41, 0x23, 0x40, 0x44, 0x40, 0x40, 0x11, 0x0f, -+ 0x44, 0x58, 0x40, 0x0b, 0x5b, 0x58, 0x55, 0x4f, 0x4f, 0x07, 0x07, 0x0c, 0x3e, 0x14, 0x06, 0x07, -+ 0x5e, 0x27, 0x43, 0x14, 0x40, 0x04, 0x16, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x56, 0x49, 0x56, -+ 0x5b, 0x53, 0x51, 0x5e, 0x5e, 0x58, 0x51, 0x59, 0x5e, 0x5e, 0x58, 0x46, 0x41, 0x4b, 0x51, 0x56, -+ 0x49, 0x56, 0x5b, 0x53, 0x51, 0x5e, 0x5e, 0x58, 0x51, 0x59, 0x5e, 0x5e, 0x58, 0x46, 0x41, 0x4b, -+ 0x0e, 0x4c, 0x45, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x55, 0x49, 0x1c, 0x11, 0x4c, -+ 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, -+ 0x07, 0x03, 0x03, 0x06, 0x0e, 0x06, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, -+ 0x40, 0x26, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x06, -+ 0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x01, 0x14, 0x04, 0x01, 0x01, 0x14, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x02, 0x44, 0x59, 0x40, 0x1d, 0x01, 0x42, 0x23, 0x40, 0x44, 0x40, 0x40, 0x11, 0x0f, -+ 0x44, 0x56, 0x40, 0x0b, 0x5a, 0x56, 0x53, 0x4c, 0x4c, 0x07, 0x07, 0x0c, 0x3e, 0x14, 0x06, 0x07, -+ 0x5d, 0x27, 0x42, 0x14, 0x40, 0x04, 0x15, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x55, 0x49, 0x55, -+ 0x5a, 0x52, 0x51, 0x5d, 0x5d, 0x56, 0x51, 0x59, 0x5d, 0x5d, 0x56, 0x45, 0x41, 0x4a, 0x51, 0x55, -+ 0x49, 0x55, 0x5a, 0x52, 0x51, 0x5d, 0x5d, 0x56, 0x51, 0x59, 0x5d, 0x5d, 0x56, 0x45, 0x41, 0x4a, -+ 0x0e, 0x4c, 0x43, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x53, 0x49, 0x1c, 0x11, 0x4c, -+ 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, -+ 0x07, 0x03, 0x03, 0x06, 0x0e, 0x06, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, -+ 0x40, 0x25, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x06, -+ 0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x02, 0x14, 0x05, 0x02, 0x02, 0x14, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x03, 0x44, 0x58, 0x40, 0x1c, 0x00, 0x43, 0x23, 0x40, 0x44, 0x40, 0x40, 0x10, 0x0f, -+ 0x44, 0x55, 0x40, 0x0b, 0x59, 0x55, 0x51, 0x4a, 0x4a, 0x07, 0x07, 0x0c, 0x3d, 0x14, 0x07, 0x07, -+ 0x5c, 0x27, 0x41, 0x14, 0x40, 0x04, 0x14, 0x40, 0x40, 0x40, 0x44, 0x44, 0x50, 0x54, 0x48, 0x54, -+ 0x59, 0x51, 0x50, 0x5c, 0x5c, 0x55, 0x50, 0x58, 0x5c, 0x5c, 0x55, 0x44, 0x40, 0x49, 0x50, 0x54, -+ 0x48, 0x54, 0x59, 0x51, 0x50, 0x5c, 0x5c, 0x55, 0x50, 0x58, 0x5c, 0x5c, 0x55, 0x44, 0x40, 0x49, -+ 0x0f, 0x4c, 0x41, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x40, 0x40, 0x51, 0x48, 0x1c, 0x10, 0x4c, -+ 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x43, -+ 0x07, 0x03, 0x03, 0x07, 0x0f, 0x07, 0x0f, 0x14, 0x17, 0x10, 0x4c, 0x17, 0x10, 0x4c, 0x40, 0x40, -+ 0x40, 0x24, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x18, 0x23, 0x27, 0x13, 0x07, 0x0f, 0x13, 0x07, -+ 0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x18, 0x03, 0x14, 0x06, 0x03, 0x03, 0x14, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x04, 0x43, 0x57, 0x40, 0x1b, 0x40, 0x44, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0f, 0x0f, -+ 0x43, 0x53, 0x40, 0x0c, 0x57, 0x53, 0x4f, 0x47, 0x47, 0x07, 0x07, 0x0b, 0x3b, 0x13, 0x08, 0x07, -+ 0x5b, 0x27, 0x00, 0x13, 0x40, 0x03, 0x13, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x53, 0x47, 0x53, -+ 0x57, 0x4f, 0x4f, 0x5b, 0x5b, 0x53, 0x4f, 0x57, 0x5b, 0x5b, 0x53, 0x43, 0x00, 0x47, 0x4f, 0x53, -+ 0x47, 0x53, 0x57, 0x4f, 0x4f, 0x5b, 0x5b, 0x53, 0x4f, 0x57, 0x5b, 0x5b, 0x53, 0x43, 0x00, 0x47, -+ 0x10, 0x4b, 0x00, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4f, 0x47, 0x1b, 0x0f, 0x4b, -+ 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44, -+ 0x07, 0x04, 0x04, 0x08, 0x10, 0x08, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40, -+ 0x40, 0x23, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x08, -+ 0x03, 0x3e, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x04, 0x13, 0x08, 0x04, 0x04, 0x13, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x05, 0x43, 0x57, 0x40, 0x1a, 0x40, 0x45, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0f, 0x0f, -+ 0x43, 0x52, 0x40, 0x0c, 0x56, 0x52, 0x4d, 0x45, 0x45, 0x07, 0x07, 0x0b, 0x3a, 0x13, 0x08, 0x07, -+ 0x5a, 0x27, 0x01, 0x13, 0x40, 0x03, 0x12, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x52, 0x47, 0x52, -+ 0x56, 0x4e, 0x4f, 0x5a, 0x5a, 0x52, 0x4f, 0x57, 0x5a, 0x5a, 0x52, 0x42, 0x00, 0x46, 0x4f, 0x52, -+ 0x47, 0x52, 0x56, 0x4e, 0x4f, 0x5a, 0x5a, 0x52, 0x4f, 0x57, 0x5a, 0x5a, 0x52, 0x42, 0x00, 0x46, -+ 0x10, 0x4b, 0x02, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4d, 0x47, 0x1b, 0x0f, 0x4b, -+ 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44, -+ 0x07, 0x04, 0x04, 0x08, 0x10, 0x08, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40, -+ 0x40, 0x22, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x08, -+ 0x03, 0x3e, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x05, 0x13, 0x09, 0x05, 0x05, 0x13, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x06, 0x43, 0x56, 0x40, 0x19, 0x41, 0x46, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0e, 0x0f, -+ 0x43, 0x50, 0x40, 0x0c, 0x55, 0x50, 0x4b, 0x42, 0x42, 0x07, 0x07, 0x0b, 0x38, 0x13, 0x09, 0x07, -+ 0x59, 0x27, 0x02, 0x13, 0x40, 0x03, 0x11, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x46, 0x51, -+ 0x55, 0x4d, 0x4e, 0x59, 0x59, 0x50, 0x4e, 0x56, 0x59, 0x59, 0x50, 0x41, 0x01, 0x45, 0x4e, 0x51, -+ 0x46, 0x51, 0x55, 0x4d, 0x4e, 0x59, 0x59, 0x50, 0x4e, 0x56, 0x59, 0x59, 0x50, 0x41, 0x01, 0x45, -+ 0x11, 0x4b, 0x04, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4b, 0x46, 0x1b, 0x0e, 0x4b, -+ 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x44, -+ 0x07, 0x04, 0x04, 0x09, 0x11, 0x09, 0x11, 0x13, 0x17, 0x0e, 0x4b, 0x17, 0x0e, 0x4b, 0x40, 0x40, -+ 0x40, 0x21, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x16, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x09, -+ 0x03, 0x3d, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x06, 0x13, 0x0a, 0x06, 0x06, 0x13, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x06, 0x43, 0x56, 0x40, 0x18, 0x42, 0x47, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0d, 0x0f, -+ 0x43, 0x4f, 0x40, 0x0c, 0x54, 0x4f, 0x4a, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x36, 0x12, 0x09, 0x07, -+ 0x59, 0x27, 0x03, 0x12, 0x40, 0x02, 0x10, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x46, 0x51, -+ 0x54, 0x4c, 0x4e, 0x59, 0x59, 0x4f, 0x4e, 0x56, 0x59, 0x59, 0x4f, 0x41, 0x01, 0x44, 0x4e, 0x51, -+ 0x46, 0x51, 0x54, 0x4c, 0x4e, 0x59, 0x59, 0x4f, 0x4e, 0x56, 0x59, 0x59, 0x4f, 0x41, 0x01, 0x44, -+ 0x11, 0x4b, 0x05, 0x40, 0x45, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4a, 0x46, 0x1a, 0x0d, 0x4b, -+ 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x45, -+ 0x07, 0x04, 0x04, 0x09, 0x11, 0x09, 0x11, 0x12, 0x17, 0x0d, 0x4b, 0x17, 0x0d, 0x4b, 0x40, 0x40, -+ 0x40, 0x20, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x09, -+ 0x02, 0x3b, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x06, 0x12, 0x0b, 0x06, 0x06, 0x12, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x07, 0x42, 0x55, 0x40, 0x18, 0x42, 0x47, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0d, 0x0f, -+ 0x42, 0x4d, 0x40, 0x0d, 0x52, 0x4d, 0x48, 0x02, 0x02, 0x07, 0x07, 0x0a, 0x35, 0x12, 0x0a, 0x07, -+ 0x58, 0x27, 0x05, 0x12, 0x40, 0x02, 0x10, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4d, 0x50, 0x45, 0x50, -+ 0x52, 0x4a, 0x4d, 0x58, 0x58, 0x4d, 0x4d, 0x55, 0x58, 0x58, 0x4d, 0x40, 0x02, 0x42, 0x4d, 0x50, -+ 0x45, 0x50, 0x52, 0x4a, 0x4d, 0x58, 0x58, 0x4d, 0x4d, 0x55, 0x58, 0x58, 0x4d, 0x40, 0x02, 0x42, -+ 0x12, 0x4a, 0x07, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x02, 0x02, 0x48, 0x45, 0x1a, 0x0d, 0x4a, -+ 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x45, -+ 0x07, 0x05, 0x05, 0x0a, 0x12, 0x0a, 0x12, 0x12, 0x17, 0x0d, 0x4a, 0x17, 0x0d, 0x4a, 0x40, 0x40, -+ 0x40, 0x20, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x25, 0x27, 0x15, 0x07, 0x12, 0x15, 0x0a, -+ 0x02, 0x3a, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x07, 0x12, 0x0d, 0x07, 0x07, 0x12, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x08, 0x42, 0x54, 0x40, 0x17, 0x43, 0x48, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0c, 0x0f, -+ 0x42, 0x4b, 0x40, 0x0d, 0x51, 0x4b, 0x46, 0x04, 0x04, 0x07, 0x07, 0x0a, 0x33, 0x12, 0x0b, 0x07, -+ 0x57, 0x27, 0x06, 0x12, 0x40, 0x02, 0x0f, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4f, 0x44, 0x4f, -+ 0x51, 0x49, 0x4c, 0x57, 0x57, 0x4b, 0x4c, 0x54, 0x57, 0x57, 0x4b, 0x00, 0x03, 0x41, 0x4c, 0x4f, -+ 0x44, 0x4f, 0x51, 0x49, 0x4c, 0x57, 0x57, 0x4b, 0x4c, 0x54, 0x57, 0x57, 0x4b, 0x00, 0x03, 0x41, -+ 0x13, 0x4a, 0x09, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x46, 0x44, 0x1a, 0x0c, 0x4a, -+ 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, -+ 0x07, 0x05, 0x05, 0x0b, 0x13, 0x0b, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, -+ 0x40, 0x1f, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0b, -+ 0x02, 0x39, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x08, 0x12, 0x0e, 0x08, 0x08, 0x12, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x09, 0x42, 0x54, 0x40, 0x16, 0x43, 0x49, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0c, 0x0f, -+ 0x42, 0x4a, 0x40, 0x0d, 0x50, 0x4a, 0x44, 0x07, 0x07, 0x07, 0x07, 0x0a, 0x32, 0x12, 0x0b, 0x07, -+ 0x56, 0x27, 0x07, 0x12, 0x40, 0x02, 0x0e, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4e, 0x44, 0x4e, -+ 0x50, 0x48, 0x4c, 0x56, 0x56, 0x4a, 0x4c, 0x54, 0x56, 0x56, 0x4a, 0x01, 0x03, 0x40, 0x4c, 0x4e, -+ 0x44, 0x4e, 0x50, 0x48, 0x4c, 0x56, 0x56, 0x4a, 0x4c, 0x54, 0x56, 0x56, 0x4a, 0x01, 0x03, 0x40, -+ 0x13, 0x4a, 0x0b, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x44, 0x44, 0x1a, 0x0c, 0x4a, -+ 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, -+ 0x07, 0x05, 0x05, 0x0b, 0x13, 0x0b, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, -+ 0x40, 0x1e, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0b, -+ 0x02, 0x38, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x09, 0x12, 0x0f, 0x09, 0x09, 0x12, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x0a, 0x41, 0x53, 0x40, 0x15, 0x44, 0x4a, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0b, 0x0f, -+ 0x41, 0x48, 0x40, 0x0e, 0x4f, 0x48, 0x42, 0x09, 0x09, 0x07, 0x07, 0x09, 0x30, 0x11, 0x0c, 0x07, -+ 0x55, 0x27, 0x08, 0x11, 0x40, 0x01, 0x0d, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4d, 0x43, 0x4d, -+ 0x4f, 0x47, 0x4b, 0x55, 0x55, 0x48, 0x4b, 0x53, 0x55, 0x55, 0x48, 0x02, 0x04, 0x00, 0x4b, 0x4d, -+ 0x43, 0x4d, 0x4f, 0x47, 0x4b, 0x55, 0x55, 0x48, 0x4b, 0x53, 0x55, 0x55, 0x48, 0x02, 0x04, 0x00, -+ 0x14, 0x49, 0x0d, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x04, 0x04, 0x42, 0x43, 0x19, 0x0b, 0x49, -+ 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x46, -+ 0x07, 0x06, 0x06, 0x0c, 0x14, 0x0c, 0x14, 0x11, 0x17, 0x0b, 0x49, 0x17, 0x0b, 0x49, 0x40, 0x40, -+ 0x40, 0x1d, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x13, 0x26, 0x27, 0x16, 0x07, 0x14, 0x16, 0x0c, -+ 0x01, 0x36, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x0a, 0x11, 0x10, 0x0a, 0x0a, 0x11, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x0b, 0x41, 0x52, 0x40, 0x14, 0x45, 0x4b, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0a, 0x0f, -+ 0x41, 0x47, 0x40, 0x0e, 0x4d, 0x47, 0x40, 0x0c, 0x0c, 0x07, 0x07, 0x09, 0x2f, 0x11, 0x0d, 0x07, -+ 0x54, 0x27, 0x0a, 0x11, 0x40, 0x01, 0x0c, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4c, 0x42, 0x4c, -+ 0x4d, 0x45, 0x4a, 0x54, 0x54, 0x47, 0x4a, 0x52, 0x54, 0x54, 0x47, 0x03, 0x05, 0x02, 0x4a, 0x4c, -+ 0x42, 0x4c, 0x4d, 0x45, 0x4a, 0x54, 0x54, 0x47, 0x4a, 0x52, 0x54, 0x54, 0x47, 0x03, 0x05, 0x02, -+ 0x15, 0x49, 0x0f, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x40, 0x42, 0x19, 0x0a, 0x49, -+ 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, -+ 0x07, 0x06, 0x06, 0x0d, 0x15, 0x0d, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40, -+ 0x40, 0x1c, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0d, -+ 0x01, 0x35, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x0b, 0x11, 0x12, 0x0b, 0x0b, 0x11, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x0c, 0x41, 0x52, 0x40, 0x13, 0x45, 0x4c, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0a, 0x0f, -+ 0x41, 0x45, 0x40, 0x0e, 0x4c, 0x45, 0x01, 0x0e, 0x0e, 0x07, 0x07, 0x09, 0x2d, 0x11, 0x0d, 0x07, -+ 0x53, 0x27, 0x0b, 0x11, 0x40, 0x01, 0x0b, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4b, 0x42, 0x4b, -+ 0x4c, 0x44, 0x4a, 0x53, 0x53, 0x45, 0x4a, 0x52, 0x53, 0x53, 0x45, 0x04, 0x05, 0x03, 0x4a, 0x4b, -+ 0x42, 0x4b, 0x4c, 0x44, 0x4a, 0x53, 0x53, 0x45, 0x4a, 0x52, 0x53, 0x53, 0x45, 0x04, 0x05, 0x03, -+ 0x15, 0x49, 0x11, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x01, 0x42, 0x19, 0x0a, 0x49, -+ 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, -+ 0x07, 0x06, 0x06, 0x0d, 0x15, 0x0d, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40, -+ 0x40, 0x1b, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0d, -+ 0x01, 0x34, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x0c, 0x11, 0x13, 0x0c, 0x0c, 0x11, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x0d, 0x40, 0x51, 0x40, 0x12, 0x46, 0x4d, 0x27, 0x40, 0x40, 0x40, 0x40, 0x09, 0x0f, -+ 0x40, 0x44, 0x40, 0x0f, 0x4b, 0x44, 0x03, 0x11, 0x11, 0x07, 0x07, 0x08, 0x2c, 0x10, 0x0e, 0x07, -+ 0x52, 0x27, 0x0c, 0x10, 0x40, 0x00, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x4a, 0x41, 0x4a, -+ 0x4b, 0x43, 0x49, 0x52, 0x52, 0x44, 0x49, 0x51, 0x52, 0x52, 0x44, 0x05, 0x06, 0x04, 0x49, 0x4a, -+ 0x41, 0x4a, 0x4b, 0x43, 0x49, 0x52, 0x52, 0x44, 0x49, 0x51, 0x52, 0x52, 0x44, 0x05, 0x06, 0x04, -+ 0x16, 0x48, 0x13, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x03, 0x41, 0x18, 0x09, 0x48, -+ 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x47, -+ 0x07, 0x07, 0x07, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x09, 0x48, 0x17, 0x09, 0x48, 0x40, 0x40, -+ 0x40, 0x1a, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x11, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0e, -+ 0x00, 0x33, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x11, 0x0d, 0x10, 0x14, 0x0d, 0x0d, 0x10, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x0e, 0x40, 0x51, 0x40, 0x11, 0x47, 0x4e, 0x27, 0x40, 0x40, 0x40, 0x40, 0x08, 0x0f, -+ 0x40, 0x42, 0x40, 0x0f, 0x4a, 0x42, 0x04, 0x13, 0x13, 0x07, 0x07, 0x08, 0x2a, 0x10, 0x0e, 0x07, -+ 0x51, 0x27, 0x0d, 0x10, 0x40, 0x00, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x41, 0x49, -+ 0x4a, 0x42, 0x49, 0x51, 0x51, 0x42, 0x49, 0x51, 0x51, 0x51, 0x42, 0x06, 0x06, 0x05, 0x49, 0x49, -+ 0x41, 0x49, 0x4a, 0x42, 0x49, 0x51, 0x51, 0x42, 0x49, 0x51, 0x51, 0x51, 0x42, 0x06, 0x06, 0x05, -+ 0x16, 0x48, 0x14, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x04, 0x41, 0x18, 0x08, 0x48, -+ 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47, -+ 0x07, 0x07, 0x07, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40, -+ 0x40, 0x19, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0e, -+ 0x00, 0x31, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x0e, 0x10, 0x15, 0x0e, 0x0e, 0x10, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x0f, 0x40, 0x50, 0x40, 0x10, 0x47, 0x4f, 0x27, 0x40, 0x40, 0x40, 0x40, 0x08, 0x0f, -+ 0x40, 0x40, 0x40, 0x0f, 0x48, 0x40, 0x06, 0x16, 0x16, 0x07, 0x07, 0x08, 0x28, 0x10, 0x0f, 0x07, -+ 0x50, 0x27, 0x0f, 0x10, 0x40, 0x00, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48, -+ 0x48, 0x40, 0x48, 0x50, 0x50, 0x40, 0x48, 0x50, 0x50, 0x50, 0x40, 0x07, 0x07, 0x07, 0x48, 0x48, -+ 0x40, 0x48, 0x48, 0x40, 0x48, 0x50, 0x50, 0x40, 0x48, 0x50, 0x50, 0x50, 0x40, 0x07, 0x07, 0x07, -+ 0x17, 0x48, 0x16, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x07, 0x07, 0x06, 0x40, 0x18, 0x08, 0x48, -+ 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47, -+ 0x07, 0x07, 0x07, 0x0f, 0x17, 0x0f, 0x17, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40, -+ 0x40, 0x18, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x17, 0x17, 0x0f, -+ 0x00, 0x30, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x0f, 0x10, 0x17, 0x0f, 0x0f, 0x10, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x10, 0x00, 0x4f, 0x40, 0x0f, 0x48, 0x50, 0x28, 0x40, 0x00, 0x40, 0x40, 0x07, 0x0f, -+ 0x00, 0x00, 0x40, 0x10, 0x47, 0x00, 0x08, 0x18, 0x18, 0x07, 0x07, 0x07, 0x27, 0x0f, 0x10, 0x07, -+ 0x4f, 0x27, 0x10, 0x0f, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47, -+ 0x47, 0x00, 0x47, 0x4f, 0x4f, 0x00, 0x47, 0x4f, 0x4f, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47, -+ 0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x4f, 0x00, 0x47, 0x4f, 0x4f, 0x4f, 0x00, 0x08, 0x08, 0x08, -+ 0x18, 0x47, 0x18, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x08, 0x00, 0x17, 0x07, 0x47, -+ 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, -+ 0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, -+ 0x40, 0x17, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, -+ 0x40, 0x2f, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x10, 0x0f, 0x18, 0x10, 0x10, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x11, 0x00, 0x4f, 0x40, 0x0e, 0x48, 0x51, 0x28, 0x40, 0x00, 0x40, 0x40, 0x07, 0x0f, -+ 0x00, 0x02, 0x40, 0x10, 0x46, 0x02, 0x0a, 0x1b, 0x1b, 0x07, 0x07, 0x07, 0x25, 0x0f, 0x10, 0x07, -+ 0x4e, 0x27, 0x11, 0x0f, 0x40, 0x40, 0x06, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x46, 0x00, 0x46, -+ 0x46, 0x01, 0x47, 0x4e, 0x4e, 0x02, 0x47, 0x4f, 0x4e, 0x4e, 0x02, 0x09, 0x08, 0x09, 0x47, 0x46, -+ 0x00, 0x46, 0x46, 0x01, 0x47, 0x4e, 0x4e, 0x02, 0x47, 0x4f, 0x4e, 0x4e, 0x02, 0x09, 0x08, 0x09, -+ 0x18, 0x47, 0x1a, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x0a, 0x00, 0x17, 0x07, 0x47, -+ 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, -+ 0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, -+ 0x40, 0x16, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, -+ 0x40, 0x2e, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x11, 0x0f, 0x19, 0x11, 0x11, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x12, 0x00, 0x4e, 0x40, 0x0d, 0x49, 0x52, 0x28, 0x40, 0x00, 0x40, 0x40, 0x06, 0x0f, -+ 0x00, 0x03, 0x40, 0x10, 0x45, 0x03, 0x0c, 0x1d, 0x1d, 0x07, 0x07, 0x07, 0x24, 0x0f, 0x11, 0x07, -+ 0x4d, 0x27, 0x12, 0x0f, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x45, 0x01, 0x45, -+ 0x45, 0x02, 0x46, 0x4d, 0x4d, 0x03, 0x46, 0x4e, 0x4d, 0x4d, 0x03, 0x0a, 0x09, 0x0a, 0x46, 0x45, -+ 0x01, 0x45, 0x45, 0x02, 0x46, 0x4d, 0x4d, 0x03, 0x46, 0x4e, 0x4d, 0x4d, 0x03, 0x0a, 0x09, 0x0a, -+ 0x19, 0x47, 0x1c, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x09, 0x09, 0x0c, 0x01, 0x17, 0x06, 0x47, -+ 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x48, -+ 0x07, 0x08, 0x08, 0x11, 0x19, 0x11, 0x19, 0x0f, 0x17, 0x06, 0x47, 0x17, 0x06, 0x47, 0x40, 0x40, -+ 0x40, 0x15, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x0e, 0x28, 0x27, 0x18, 0x07, 0x19, 0x18, 0x11, -+ 0x40, 0x2c, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x12, 0x0f, 0x1a, 0x12, 0x12, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x13, 0x01, 0x4d, 0x40, 0x0c, 0x4a, 0x53, 0x29, 0x40, 0x01, 0x40, 0x40, 0x05, 0x0f, -+ 0x01, 0x05, 0x40, 0x11, 0x43, 0x05, 0x0e, 0x20, 0x20, 0x07, 0x07, 0x06, 0x22, 0x0e, 0x12, 0x07, -+ 0x4c, 0x27, 0x14, 0x0e, 0x40, 0x41, 0x04, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x44, 0x02, 0x44, -+ 0x43, 0x04, 0x45, 0x4c, 0x4c, 0x05, 0x45, 0x4d, 0x4c, 0x4c, 0x05, 0x0b, 0x0a, 0x0c, 0x45, 0x44, -+ 0x02, 0x44, 0x43, 0x04, 0x45, 0x4c, 0x4c, 0x05, 0x45, 0x4d, 0x4c, 0x4c, 0x05, 0x0b, 0x0a, 0x0c, -+ 0x1a, 0x46, 0x1e, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x0e, 0x02, 0x16, 0x05, 0x46, -+ 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, -+ 0x07, 0x09, 0x09, 0x12, 0x1a, 0x12, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, -+ 0x40, 0x14, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x12, -+ 0x41, 0x2b, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x13, 0x0e, 0x1c, 0x13, 0x13, 0x0e, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x14, 0x01, 0x4d, 0x40, 0x0b, 0x4a, 0x54, 0x29, 0x40, 0x01, 0x40, 0x40, 0x05, 0x0f, -+ 0x01, 0x06, 0x40, 0x11, 0x42, 0x06, 0x10, 0x22, 0x22, 0x07, 0x07, 0x06, 0x21, 0x0e, 0x12, 0x07, -+ 0x4b, 0x27, 0x15, 0x0e, 0x40, 0x41, 0x03, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x43, 0x02, 0x43, -+ 0x42, 0x05, 0x45, 0x4b, 0x4b, 0x06, 0x45, 0x4d, 0x4b, 0x4b, 0x06, 0x0c, 0x0a, 0x0d, 0x45, 0x43, -+ 0x02, 0x43, 0x42, 0x05, 0x45, 0x4b, 0x4b, 0x06, 0x45, 0x4d, 0x4b, 0x4b, 0x06, 0x0c, 0x0a, 0x0d, -+ 0x1a, 0x46, 0x20, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x10, 0x02, 0x16, 0x05, 0x46, -+ 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, -+ 0x07, 0x09, 0x09, 0x12, 0x1a, 0x12, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, -+ 0x40, 0x13, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x12, -+ 0x41, 0x2a, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x14, 0x0e, 0x1d, 0x14, 0x14, 0x0e, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x15, 0x01, 0x4c, 0x40, 0x0a, 0x4b, 0x55, 0x29, 0x40, 0x01, 0x40, 0x40, 0x04, 0x0f, -+ 0x01, 0x08, 0x40, 0x11, 0x41, 0x08, 0x12, 0x25, 0x25, 0x07, 0x07, 0x06, 0x1f, 0x0e, 0x13, 0x07, -+ 0x4a, 0x27, 0x16, 0x0e, 0x40, 0x41, 0x02, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x03, 0x42, -+ 0x41, 0x06, 0x44, 0x4a, 0x4a, 0x08, 0x44, 0x4c, 0x4a, 0x4a, 0x08, 0x0d, 0x0b, 0x0e, 0x44, 0x42, -+ 0x03, 0x42, 0x41, 0x06, 0x44, 0x4a, 0x4a, 0x08, 0x44, 0x4c, 0x4a, 0x4a, 0x08, 0x0d, 0x0b, 0x0e, -+ 0x1b, 0x46, 0x22, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x12, 0x03, 0x16, 0x04, 0x46, -+ 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x49, -+ 0x07, 0x09, 0x09, 0x13, 0x1b, 0x13, 0x1b, 0x0e, 0x17, 0x04, 0x46, 0x17, 0x04, 0x46, 0x40, 0x40, -+ 0x40, 0x12, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x0c, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x13, -+ 0x41, 0x29, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x15, 0x0e, 0x1e, 0x15, 0x15, 0x0e, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x15, 0x01, 0x4c, 0x40, 0x09, 0x4c, 0x56, 0x29, 0x40, 0x01, 0x40, 0x40, 0x03, 0x0f, -+ 0x01, 0x09, 0x40, 0x11, 0x40, 0x09, 0x13, 0x27, 0x27, 0x07, 0x07, 0x05, 0x1d, 0x0d, 0x13, 0x07, -+ 0x4a, 0x27, 0x17, 0x0d, 0x40, 0x42, 0x01, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x03, 0x42, -+ 0x40, 0x07, 0x44, 0x4a, 0x4a, 0x09, 0x44, 0x4c, 0x4a, 0x4a, 0x09, 0x0d, 0x0b, 0x0f, 0x44, 0x42, -+ 0x03, 0x42, 0x40, 0x07, 0x44, 0x4a, 0x4a, 0x09, 0x44, 0x4c, 0x4a, 0x4a, 0x09, 0x0d, 0x0b, 0x0f, -+ 0x1b, 0x46, 0x23, 0x40, 0x4a, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x13, 0x03, 0x15, 0x03, 0x46, -+ 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x4a, -+ 0x07, 0x09, 0x09, 0x13, 0x1b, 0x13, 0x1b, 0x0d, 0x17, 0x03, 0x46, 0x17, 0x03, 0x46, 0x40, 0x40, -+ 0x40, 0x11, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x13, -+ 0x42, 0x27, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x15, 0x0d, 0x1f, 0x15, 0x15, 0x0d, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x16, 0x02, 0x4b, 0x40, 0x09, 0x4c, 0x56, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x03, 0x0f, -+ 0x02, 0x0b, 0x40, 0x12, 0x01, 0x0b, 0x15, 0x2a, 0x2a, 0x07, 0x07, 0x05, 0x1c, 0x0d, 0x14, 0x07, -+ 0x49, 0x27, 0x19, 0x0d, 0x40, 0x42, 0x01, 0x40, 0x40, 0x40, 0x02, 0x02, 0x43, 0x41, 0x04, 0x41, -+ 0x01, 0x09, 0x43, 0x49, 0x49, 0x0b, 0x43, 0x4b, 0x49, 0x49, 0x0b, 0x0e, 0x0c, 0x11, 0x43, 0x41, -+ 0x04, 0x41, 0x01, 0x09, 0x43, 0x49, 0x49, 0x0b, 0x43, 0x4b, 0x49, 0x49, 0x0b, 0x0e, 0x0c, 0x11, -+ 0x1c, 0x45, 0x25, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0c, 0x0c, 0x15, 0x04, 0x15, 0x03, 0x45, -+ 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x4a, -+ 0x07, 0x0a, 0x0a, 0x14, 0x1c, 0x14, 0x1c, 0x0d, 0x17, 0x03, 0x45, 0x17, 0x03, 0x45, 0x40, 0x40, -+ 0x40, 0x11, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x2a, 0x27, 0x1a, 0x07, 0x1c, 0x1a, 0x14, -+ 0x42, 0x26, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x16, 0x0d, 0x21, 0x16, 0x16, 0x0d, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x17, 0x02, 0x4a, 0x40, 0x08, 0x4d, 0x57, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x02, 0x0f, -+ 0x02, 0x0d, 0x40, 0x12, 0x02, 0x0d, 0x17, 0x2c, 0x2c, 0x07, 0x07, 0x05, 0x1a, 0x0d, 0x15, 0x07, -+ 0x48, 0x27, 0x1a, 0x0d, 0x40, 0x42, 0x00, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x40, 0x05, 0x40, -+ 0x02, 0x0a, 0x42, 0x48, 0x48, 0x0d, 0x42, 0x4a, 0x48, 0x48, 0x0d, 0x0f, 0x0d, 0x12, 0x42, 0x40, -+ 0x05, 0x40, 0x02, 0x0a, 0x42, 0x48, 0x48, 0x0d, 0x42, 0x4a, 0x48, 0x48, 0x0d, 0x0f, 0x0d, 0x12, -+ 0x1d, 0x45, 0x27, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x17, 0x05, 0x15, 0x02, 0x45, -+ 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, -+ 0x07, 0x0a, 0x0a, 0x15, 0x1d, 0x15, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, -+ 0x40, 0x10, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x15, -+ 0x42, 0x25, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x17, 0x0d, 0x22, 0x17, 0x17, 0x0d, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x18, 0x02, 0x4a, 0x40, 0x07, 0x4d, 0x58, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x02, 0x0f, -+ 0x02, 0x0e, 0x40, 0x12, 0x03, 0x0e, 0x19, 0x2f, 0x2f, 0x07, 0x07, 0x05, 0x19, 0x0d, 0x15, 0x07, -+ 0x47, 0x27, 0x1b, 0x0d, 0x40, 0x42, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x00, 0x05, 0x00, -+ 0x03, 0x0b, 0x42, 0x47, 0x47, 0x0e, 0x42, 0x4a, 0x47, 0x47, 0x0e, 0x10, 0x0d, 0x13, 0x42, 0x00, -+ 0x05, 0x00, 0x03, 0x0b, 0x42, 0x47, 0x47, 0x0e, 0x42, 0x4a, 0x47, 0x47, 0x0e, 0x10, 0x0d, 0x13, -+ 0x1d, 0x45, 0x29, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x19, 0x05, 0x15, 0x02, 0x45, -+ 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, -+ 0x07, 0x0a, 0x0a, 0x15, 0x1d, 0x15, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, -+ 0x40, 0x0f, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x15, -+ 0x42, 0x24, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x18, 0x0d, 0x23, 0x18, 0x18, 0x0d, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x19, 0x03, 0x49, 0x40, 0x06, 0x4e, 0x59, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x01, 0x0f, -+ 0x03, 0x10, 0x40, 0x13, 0x04, 0x10, 0x1b, 0x31, 0x31, 0x07, 0x07, 0x04, 0x17, 0x0c, 0x16, 0x07, -+ 0x46, 0x27, 0x1c, 0x0c, 0x40, 0x43, 0x41, 0x40, 0x40, 0x40, 0x03, 0x03, 0x41, 0x01, 0x06, 0x01, -+ 0x04, 0x0c, 0x41, 0x46, 0x46, 0x10, 0x41, 0x49, 0x46, 0x46, 0x10, 0x11, 0x0e, 0x14, 0x41, 0x01, -+ 0x06, 0x01, 0x04, 0x0c, 0x41, 0x46, 0x46, 0x10, 0x41, 0x49, 0x46, 0x46, 0x10, 0x11, 0x0e, 0x14, -+ 0x1e, 0x44, 0x2b, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0e, 0x0e, 0x1b, 0x06, 0x14, 0x01, 0x44, -+ 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x4b, -+ 0x07, 0x0b, 0x0b, 0x16, 0x1e, 0x16, 0x1e, 0x0c, 0x17, 0x01, 0x44, 0x17, 0x01, 0x44, 0x40, 0x40, -+ 0x40, 0x0e, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x09, 0x2b, 0x27, 0x1b, 0x07, 0x1e, 0x1b, 0x16, -+ 0x43, 0x22, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x19, 0x0c, 0x24, 0x19, 0x19, 0x0c, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x1a, 0x03, 0x48, 0x40, 0x05, 0x4f, 0x5a, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x00, 0x0f, -+ 0x03, 0x11, 0x40, 0x13, 0x06, 0x11, 0x1d, 0x34, 0x34, 0x07, 0x07, 0x04, 0x16, 0x0c, 0x17, 0x07, -+ 0x45, 0x27, 0x1e, 0x0c, 0x40, 0x43, 0x42, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x02, 0x07, 0x02, -+ 0x06, 0x0e, 0x40, 0x45, 0x45, 0x11, 0x40, 0x48, 0x45, 0x45, 0x11, 0x12, 0x0f, 0x16, 0x40, 0x02, -+ 0x07, 0x02, 0x06, 0x0e, 0x40, 0x45, 0x45, 0x11, 0x40, 0x48, 0x45, 0x45, 0x11, 0x12, 0x0f, 0x16, -+ 0x1f, 0x44, 0x2d, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1d, 0x07, 0x14, 0x00, 0x44, -+ 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, -+ 0x07, 0x0b, 0x0b, 0x17, 0x1f, 0x17, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, -+ 0x40, 0x0d, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x17, -+ 0x43, 0x21, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x1a, 0x0c, 0x26, 0x1a, 0x1a, 0x0c, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x1b, 0x03, 0x48, 0x40, 0x04, 0x4f, 0x5b, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x00, 0x0f, -+ 0x03, 0x13, 0x40, 0x13, 0x07, 0x13, 0x1f, 0x36, 0x36, 0x07, 0x07, 0x04, 0x14, 0x0c, 0x17, 0x07, -+ 0x44, 0x27, 0x1f, 0x0c, 0x40, 0x43, 0x43, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x03, 0x07, 0x03, -+ 0x07, 0x0f, 0x40, 0x44, 0x44, 0x13, 0x40, 0x48, 0x44, 0x44, 0x13, 0x13, 0x0f, 0x17, 0x40, 0x03, -+ 0x07, 0x03, 0x07, 0x0f, 0x40, 0x44, 0x44, 0x13, 0x40, 0x48, 0x44, 0x44, 0x13, 0x13, 0x0f, 0x17, -+ 0x1f, 0x44, 0x2f, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1f, 0x07, 0x14, 0x00, 0x44, -+ 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, -+ 0x07, 0x0b, 0x0b, 0x17, 0x1f, 0x17, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, -+ 0x40, 0x0c, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x17, -+ 0x43, 0x20, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x1b, 0x0c, 0x27, 0x1b, 0x1b, 0x0c, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x1c, 0x04, 0x47, 0x40, 0x03, 0x50, 0x5c, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, -+ 0x04, 0x14, 0x40, 0x14, 0x08, 0x14, 0x21, 0x39, 0x39, 0x07, 0x07, 0x03, 0x13, 0x0b, 0x18, 0x07, -+ 0x43, 0x27, 0x20, 0x0b, 0x40, 0x44, 0x44, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x04, 0x08, 0x04, -+ 0x08, 0x10, 0x00, 0x43, 0x43, 0x14, 0x00, 0x47, 0x43, 0x43, 0x14, 0x14, 0x10, 0x18, 0x00, 0x04, -+ 0x08, 0x04, 0x08, 0x10, 0x00, 0x43, 0x43, 0x14, 0x00, 0x47, 0x43, 0x43, 0x14, 0x14, 0x10, 0x18, -+ 0x20, 0x43, 0x31, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x21, 0x08, 0x13, 0x40, 0x43, -+ 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x4c, -+ 0x07, 0x0c, 0x0c, 0x18, 0x20, 0x18, 0x20, 0x0b, 0x17, 0x40, 0x43, 0x17, 0x40, 0x43, 0x40, 0x40, -+ 0x40, 0x0b, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x07, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x18, -+ 0x44, 0x1f, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x1c, 0x0b, 0x28, 0x1c, 0x1c, 0x0b, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x1d, 0x04, 0x47, 0x40, 0x02, 0x51, 0x5d, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x41, 0x0f, -+ 0x04, 0x16, 0x40, 0x14, 0x09, 0x16, 0x22, 0x3b, 0x3b, 0x07, 0x07, 0x03, 0x11, 0x0b, 0x18, 0x07, -+ 0x42, 0x27, 0x21, 0x0b, 0x40, 0x44, 0x45, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x05, 0x08, 0x05, -+ 0x09, 0x11, 0x00, 0x42, 0x42, 0x16, 0x00, 0x47, 0x42, 0x42, 0x16, 0x15, 0x10, 0x19, 0x00, 0x05, -+ 0x08, 0x05, 0x09, 0x11, 0x00, 0x42, 0x42, 0x16, 0x00, 0x47, 0x42, 0x42, 0x16, 0x15, 0x10, 0x19, -+ 0x20, 0x43, 0x32, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x22, 0x08, 0x13, 0x41, 0x43, -+ 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, -+ 0x07, 0x0c, 0x0c, 0x18, 0x20, 0x18, 0x20, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, -+ 0x40, 0x0a, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x18, -+ 0x44, 0x1d, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x1d, 0x0b, 0x29, 0x1d, 0x1d, 0x0b, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x1e, 0x04, 0x46, 0x40, 0x01, 0x51, 0x5e, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x41, 0x0f, -+ 0x04, 0x18, 0x40, 0x14, 0x0b, 0x18, 0x24, 0x3e, 0x3e, 0x07, 0x07, 0x03, 0x0f, 0x0b, 0x19, 0x07, -+ 0x41, 0x27, 0x23, 0x0b, 0x40, 0x44, 0x46, 0x40, 0x40, 0x40, 0x04, 0x04, 0x01, 0x06, 0x09, 0x06, -+ 0x0b, 0x13, 0x01, 0x41, 0x41, 0x18, 0x01, 0x46, 0x41, 0x41, 0x18, 0x16, 0x11, 0x1b, 0x01, 0x06, -+ 0x09, 0x06, 0x0b, 0x13, 0x01, 0x41, 0x41, 0x18, 0x01, 0x46, 0x41, 0x41, 0x18, 0x16, 0x11, 0x1b, -+ 0x21, 0x43, 0x34, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x11, 0x11, 0x24, 0x09, 0x13, 0x41, 0x43, -+ 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, -+ 0x07, 0x0c, 0x0c, 0x19, 0x21, 0x19, 0x21, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, -+ 0x40, 0x09, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x21, 0x1c, 0x19, -+ 0x44, 0x1c, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x1e, 0x0b, 0x2b, 0x1e, 0x1e, 0x0b, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x1f, 0x05, 0x45, 0x40, 0x00, 0x52, 0x5f, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x42, 0x0f, -+ 0x05, 0x19, 0x40, 0x15, 0x0c, 0x19, 0x26, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0e, 0x0a, 0x1a, 0x07, -+ 0x40, 0x27, 0x24, 0x0a, 0x40, 0x45, 0x47, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x07, 0x0a, 0x07, -+ 0x0c, 0x14, 0x02, 0x40, 0x40, 0x19, 0x02, 0x45, 0x40, 0x40, 0x19, 0x17, 0x12, 0x1c, 0x02, 0x07, -+ 0x0a, 0x07, 0x0c, 0x14, 0x02, 0x40, 0x40, 0x19, 0x02, 0x45, 0x40, 0x40, 0x19, 0x17, 0x12, 0x1c, -+ 0x22, 0x42, 0x36, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x26, 0x0a, 0x12, 0x42, 0x42, -+ 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d, -+ 0x07, 0x0d, 0x0d, 0x1a, 0x22, 0x1a, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40, -+ 0x40, 0x08, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a, -+ 0x45, 0x1b, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x1f, 0x0a, 0x2c, 0x1f, 0x1f, 0x0a, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x20, 0x05, 0x45, 0x40, 0x40, 0x52, 0x60, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x42, 0x0f, -+ 0x05, 0x1b, 0x40, 0x15, 0x0d, 0x1b, 0x28, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0c, 0x0a, 0x1a, 0x07, -+ 0x00, 0x27, 0x25, 0x0a, 0x40, 0x45, 0x48, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x08, 0x0a, 0x08, -+ 0x0d, 0x15, 0x02, 0x00, 0x00, 0x1b, 0x02, 0x45, 0x00, 0x00, 0x1b, 0x18, 0x12, 0x1d, 0x02, 0x08, -+ 0x0a, 0x08, 0x0d, 0x15, 0x02, 0x00, 0x00, 0x1b, 0x02, 0x45, 0x00, 0x00, 0x1b, 0x18, 0x12, 0x1d, -+ 0x22, 0x42, 0x38, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x28, 0x0a, 0x12, 0x42, 0x42, -+ 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d, -+ 0x07, 0x0d, 0x0d, 0x1a, 0x22, 0x1a, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40, -+ 0x40, 0x07, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a, -+ 0x45, 0x1a, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x20, 0x0a, 0x2d, 0x20, 0x20, 0x0a, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x21, 0x05, 0x44, 0x40, 0x41, 0x53, 0x61, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x43, 0x0f, -+ 0x05, 0x1c, 0x40, 0x15, 0x0e, 0x1c, 0x2a, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0a, 0x1b, 0x07, -+ 0x01, 0x27, 0x26, 0x0a, 0x40, 0x45, 0x49, 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x0b, 0x09, -+ 0x0e, 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e, 0x03, 0x09, -+ 0x0b, 0x09, 0x0e, 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e, -+ 0x23, 0x42, 0x3a, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x0b, 0x12, 0x43, 0x42, -+ 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d, -+ 0x07, 0x0d, 0x0d, 0x1b, 0x23, 0x1b, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, 0x40, -+ 0x40, 0x06, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, 0x1d, 0x1b, -+ 0x45, 0x18, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x21, 0x0a, 0x2e, 0x21, 0x21, 0x0a, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f, -+ 0x06, 0x1e, 0x40, 0x16, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x09, 0x09, 0x1c, 0x07, -+ 0x02, 0x27, 0x28, 0x09, 0x40, 0x46, 0x4a, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0a, 0x0c, 0x0a, -+ 0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20, 0x04, 0x0a, -+ 0x0c, 0x0a, 0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20, -+ 0x24, 0x41, 0x3c, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2c, 0x0c, 0x11, 0x44, 0x41, -+ 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, -+ 0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, -+ 0x40, 0x05, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c, -+ 0x46, 0x17, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x22, 0x09, 0x30, 0x22, 0x22, 0x09, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f, -+ 0x06, 0x1f, 0x40, 0x16, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x08, 0x09, 0x1c, 0x07, -+ 0x03, 0x27, 0x29, 0x09, 0x40, 0x46, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x0c, 0x0b, -+ 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21, 0x04, 0x0b, -+ 0x0c, 0x0b, 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21, -+ 0x24, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, 0x0c, 0x11, 0x44, 0x41, -+ 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, -+ 0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, -+ 0x40, 0x04, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c, -+ 0x46, 0x16, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x23, 0x09, 0x31, 0x23, 0x23, 0x09, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x44, 0x55, 0x64, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x45, 0x0f, -+ 0x06, 0x21, 0x40, 0x16, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x06, 0x09, 0x1d, 0x07, -+ 0x04, 0x27, 0x2a, 0x09, 0x40, 0x46, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c, -+ 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22, 0x05, 0x0c, -+ 0x0d, 0x0c, 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22, -+ 0x25, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x0d, 0x11, 0x45, 0x41, -+ 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x4e, -+ 0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, 0x40, 0x40, -+ 0x40, 0x03, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d, -+ 0x46, 0x15, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x24, 0x09, 0x32, 0x24, 0x24, 0x09, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x46, 0x0f, -+ 0x06, 0x22, 0x40, 0x16, 0x13, 0x22, 0x31, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x04, 0x08, 0x1d, 0x07, -+ 0x04, 0x27, 0x2b, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c, -+ 0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x05, 0x0c, -+ 0x0d, 0x0c, 0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, -+ 0x25, 0x41, 0x3e, 0x40, 0x4f, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x0d, 0x10, 0x46, 0x41, -+ 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f, -+ 0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40, -+ 0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d, -+ 0x47, 0x13, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x24, 0x08, 0x33, 0x24, 0x24, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x46, 0x0f, -+ 0x07, 0x24, 0x40, 0x17, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x03, 0x08, 0x1e, 0x07, -+ 0x05, 0x27, 0x2d, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x0e, 0x0d, -+ 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, 0x06, 0x0d, -+ 0x0e, 0x0d, 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, -+ 0x26, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x0e, 0x10, 0x46, 0x40, -+ 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f, -+ 0x07, 0x0f, 0x0f, 0x1e, 0x26, 0x1e, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40, -+ 0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x1e, -+ 0x47, 0x12, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x25, 0x08, 0x35, 0x25, 0x25, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, -+ 0x07, 0x26, 0x40, 0x17, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x01, 0x08, 0x1f, 0x07, -+ 0x06, 0x27, 0x2e, 0x08, 0x40, 0x47, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x0f, 0x0e, -+ 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26, 0x07, 0x0e, -+ 0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26, -+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x0f, 0x10, 0x47, 0x40, -+ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, -+ 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, -+ 0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f, -+ 0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, -+ 0x07, 0x27, 0x40, 0x17, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, -+ 0x07, 0x27, 0x2f, 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f, -+ 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f, -+ 0x0f, 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, -+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, 0x40, -+ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, -+ 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, -+ 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f, -+ 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, 0x27, 0x27, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+}; -+ -+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) -+{ -+ u8 bit = field.offset % 32, word = field.offset / 32; -+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit); -+ u64 val = ((u64)value << bit) & mask; -+ -+ buf[word] &= ~mask; -+ buf[word] |= val; -+ if (bit + field.len > 32) { -+ buf[word + 1] &= ~(mask >> 32); -+ buf[word + 1] |= val >> 32; -+ } -+} -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps_packet *hw_ps; -+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y; -+ u32 log2_min_cu_qp_delta_size; -+ dma_addr_t scaling_list_address; -+ u32 scaling_distance; -+ int i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 80 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ ctb_log2_size_y = min_cb_log2_size_y + -+ sps->log2_diff_max_min_luma_coding_block_size; -+ ctb_size_y = 1 << ctb_log2_size_y; -+ -+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) -+ /* write sps */ -+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); -+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); -+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4, -+ LOG2_MAX_PIC_ORDER_CNT_LSB); -+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2, -+ LOG2_MIN_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED), -+ SCALING_LIST_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED), -+ AMP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET), -+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG); -+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) { -+ WRITE_PPS(1, PCM_ENABLED_FLAG); -+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_CHROMA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED), -+ PCM_LOOP_FILTER_DISABLED_FLAG); -+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ } -+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT), -+ LONG_TERM_REF_PICS_PRESENT_FLAG); -+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED), -+ SPS_TEMPORAL_MVP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), -+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG); -+ -+ /* write pps */ -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), -+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), -+ OUTPUT_FLAG_PRESENT_FLAG); -+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), -+ SIGN_DATA_HIDING_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), -+ CABAC_INIT_PRESENT_FLAG); -+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, -+ NUM_REF_IDX_L0_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, -+ NUM_REF_IDX_L1_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED), -+ CONSTRAINED_INTRA_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED), -+ TRANSFORM_SKIP_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED), -+ CU_QP_DELTA_ENABLED_FLAG); -+ -+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; -+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE); -+ -+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET); -+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT), -+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED), -+ WEIGHTED_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED), -+ WEIGHTED_BIPRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED), -+ TRANSQUANT_BYPASS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED), -+ TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED), -+ ENTROPY_CODING_SYNC_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED), -+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED), -+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED), -+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER), -+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG); -+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2); -+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT), -+ LISTS_MODIFICATION_PRESENT_FLAG); -+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), -+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); -+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); -+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); -+ -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { -+ for (i = 0; i <= pps->num_tile_columns_minus1; i++) -+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i)); -+ for (i = 0; i <= pps->num_tile_rows_minus1; i++) -+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); -+ } else { -+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ COLUMN_WIDTH(0)); -+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ ROW_HEIGHT(0)); -+ } -+ -+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); -+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; -+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); -+} -+ -+static void assemble_hw_rps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params; -+ const struct v4l2_hevc_dpb_entry *dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_rps_packet *hw_ps; -+ int i, j; -+ unsigned int lowdelay; -+ -+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) -+ -+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD(i * 5, 1) -+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + (i * 5), 4) -+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD((i < 5 ? 75 : 132) + (i * 5), 1) -+#define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) -+ -+#define LOWDELAY PS_FIELD(182, 1) -+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) -+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) -+#define NUM_RPS_POC PS_FIELD(202, 4) -+ -+ for (j = 0; j < run->num_slices; j++) { -+ sl_params = &run->slices_params[j]; -+ dpb = decode_params->dpb; -+ lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; -+ -+ hw_ps = &priv_tbl->rps[j]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L0(i)); -+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -+ -+ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ -+ } -+ -+ for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L1(i)); -+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); -+ -+ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ } -+ -+ WRITE_RPS(lowdelay, LOWDELAY); -+ -+ WRITE_RPS(sl_params->long_term_ref_pic_set_size + -+ sl_params->short_term_ref_pic_set_size, -+ LONG_TERM_RPS_BIT_OFFSET); -+ WRITE_RPS(sl_params->short_term_ref_pic_set_size, -+ SHORT_TERM_RPS_BIT_OFFSET); -+ -+ WRITE_RPS(decode_params->num_poc_st_curr_before + -+ decode_params->num_poc_st_curr_after + -+ decode_params->num_poc_lt_curr, -+ NUM_RPS_POC); -+ } -+} -+ -+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -+ u8 *dst; -+ scalingList_t sl; -+ int i, j; -+ -+ if (!memcmp((void*)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) -+ return; -+ -+ memset(&sl, 0, sizeof(scalingList_t)); -+ -+ for (i = 0; i < 6; i++) { -+ for (j = 0; j < 16; j++) -+ sl.sl[0][i][j] = scaling->scaling_list_4x4[i][j]; -+ for (j = 0; j < 64; j++) { -+ sl.sl[1][i][j] = scaling->scaling_list_8x8[i][j]; -+ sl.sl[2][i][j] = scaling->scaling_list_16x16[i][j]; -+ if (i < 2) -+ sl.sl[3][i][j] = scaling->scaling_list_32x32[i][j]; -+ } -+ sl.sl_dc[0][i] = scaling->scaling_list_dc_coef_16x16[i]; -+ if (i < 2) -+ sl.sl_dc[1][i] = scaling->scaling_list_dc_coef_32x32[i]; -+ } -+ -+ dst = tbl->scaling_list; -+ hal_record_scaling_list((scalingFactor_t *)dst, &sl); -+ -+ memcpy((void*)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); -+} -+ -+static struct vb2_buffer * -+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *vb2_buf = NULL; -+ -+ if (dpb_idx < decode_params->num_active_dpb_entries) -+ vb2_buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); -+ -+ /* -+ * If a DPB entry is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ if (!vb2_buf) -+ return &run->base.bufs.dst->vb2_buf; -+ -+ return vb2_buf; -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t refer_addr; -+ u32 rlc_len; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; -+ u32 uv_virstride; -+ u32 yuv_virstride; -+ u32 offset; -+ dma_addr_t dst_addr; -+ u32 reg, i; -+ -+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ uv_virstride = y_virstride / 2; -+ yuv_virstride = y_virstride + uv_virstride; -+ -+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); -+ -+ /* config rlc base address */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -+ -+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ -+ /* config cabac table */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ -+ /* config output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ -+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ -+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ -+ /* config ref pic address */ -+ for (i = 0; i < 15; i++) { -+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); -+ -+ if (i < 4 && decode_params->num_active_dpb_entries) { -+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); -+ reg = (reg >> (i * 4)) & 0xf; -+ } else -+ reg = 0; -+ -+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ writel_relaxed(refer_addr | reg, -+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ -+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); -+ writel_relaxed(reg, -+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); -+ } -+ -+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); -+ -+ /* config hw pps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ -+ /* config hw rps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_RPS_BASE); -+ -+ reg = RKVDEC_AXI_DDR_RDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); -+ -+ reg = RKVDEC_AXI_DDR_WDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+} -+ -+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -+ -+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; -+ return 0; -+} -+ -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (sps->bit_depth_luma_minus8 == 2) -+ return V4L2_PIX_FMT_NV15; -+ else -+ return V4L2_PIX_FMT_NV12; -+} -+ -+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_priv_tbl *priv_tbl; -+ struct rkvdec_hevc_ctx *hevc_ctx; -+ struct v4l2_ctrl *ctrl; -+ int ret; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ if (ret) -+ return ret; -+ -+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); -+ if (!hevc_ctx) -+ return -ENOMEM; -+ -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ hevc_ctx->priv_tbl.cpu = priv_tbl; -+ memset(priv_tbl, 0, sizeof(*priv_tbl)); -+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, -+ sizeof(rkvdec_hevc_cabac_table)); -+ -+ ctx->priv = hevc_ctx; -+ return 0; -+ -+err_free_ctx: -+ kfree(hevc_ctx); -+ return ret; -+} -+ -+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, -+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); -+ kfree(hevc_ctx); -+} -+ -+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct v4l2_ctrl *ctrl; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); -+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -+ run->num_slices = ctrl->new_elems; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ run->sps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_PPS); -+ run->pps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); -+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ -+ rkvdec_run_preamble(ctx, &run->base); -+} -+ -+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_run run; -+ -+ rkvdec_hevc_run_preamble(ctx, &run); -+ -+ assemble_hw_scaling_list(ctx, &run); -+ assemble_hw_pps(ctx, &run); -+ assemble_hw_rps(ctx, &run); -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ // sw_cabac_error_e - cabac error enable -+ writel_relaxed(0xfdfffffd, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ // slice end error enable = BIT(28) -+ // frame end error enable = BIT(29) -+ writel_relaxed(0x30000000, rkvdec->regs + RKVDEC_REG_H264_ERR_E); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); -+ -+ /* Start decoding! */ -+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | -+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { -+ .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .start = rkvdec_hevc_start, -+ .stop = rkvdec_hevc_stop, -+ .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .valid_fmt = rkvdec_hevc_valid_fmt, -+}; -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-regs.h -+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h -@@ -48,6 +48,7 @@ - #define RKVDEC_RLC_MODE BIT(11) - #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) - #define RKVDEC_MODE(x) (((x) & 0x03) << 20) -+#define RKVDEC_MODE_HEVC 0 - #define RKVDEC_MODE_H264 1 - #define RKVDEC_MODE_VP9 2 - #define RKVDEC_RPS_MODE BIT(24) -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); - -- if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { -+ if (!ctx->valid_fmt) { - ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); - if (ctx->valid_fmt) { - struct v4l2_pix_format_mplane *pix_mp; -@@ -134,6 +134,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { - }, - }; - -+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, -+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, -+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, -+ .cfg.dims = { 600 }, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, -+ .cfg.ops = &rkvdec_ctrl_ops, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, -+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, -+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, -+ }, -+}; -+ -+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { -+ .ctrls = rkvdec_hevc_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), -+}; -+ -+static const u32 rkvdec_hevc_decoded_fmts[] = { -+ V4L2_PIX_FMT_NV12, -+ V4L2_PIX_FMT_NV15, -+}; -+ -+ - static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .ctrls = rkvdec_h264_ctrl_descs, - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), -@@ -187,6 +243,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_hevc_ctrls, -+ .ops = &rkvdec_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, - .frmsize = { -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -133,6 +133,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; - - #endif /* RKVDEC_H_ */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 30 Jan 2021 18:16:39 +0100 -Subject: media: rkvdec: add variants support - -rkvdec IP has different versions which among others differ in -the supported decoding formats. -This adds an variant implementation in order support other -than the currently supported RK3399 version. - -Note: Since matching of supported codecs is index-based the -available codec options have been reordered here: from -supported by all versions to not commonly supported. This seems -the better soultion than duplicatiing code for every newly added IP. - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec.c | 105 +++++++--- - drivers/staging/media/rkvdec/rkvdec.h | 10 + - 2 files changed, 85 insertions(+), 30 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -227,6 +228,22 @@ static const u32 rkvdec_vp9_decoded_fmts[] = { - }; - - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_hevc_ctrls, -+ .ops = &rkvdec_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_HEVC, -+ }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, - .frmsize = { -@@ -242,21 +259,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), - .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -- }, -- { -- .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -- .frmsize = { -- .min_width = 64, -- .max_width = 4096, -- .step_width = 64, -- .min_height = 64, -- .max_height = 2304, -- .step_height = 16, -- }, -- .ctrls = &rkvdec_hevc_ctrls, -- .ops = &rkvdec_hevc_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -- .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_H264, - }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -272,16 +275,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .ops = &rkvdec_vp9_fmt_ops, - .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), - .decoded_fmts = rkvdec_vp9_decoded_fmts, -- } -+ .capability = RKVDEC_CAPABILITY_VP9, -+ }, - }; - - static const struct rkvdec_coded_fmt_desc * --rkvdec_find_coded_fmt_desc(u32 fourcc) -+rkvdec_default_coded_fmt_desc(unsigned int capabilities) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -+ if (rkvdec_coded_fmts[i].capability & capabilities) -+ return &rkvdec_coded_fmts[i]; -+ } -+ -+ return NULL; -+} -+ -+static const struct rkvdec_coded_fmt_desc * -+rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities) - { - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- if (rkvdec_coded_fmts[i].fourcc == fourcc) -+ if (rkvdec_coded_fmts[i].fourcc == fourcc && -+ (rkvdec_coded_fmts[i].capability & capabilities)) - return &rkvdec_coded_fmts[i]; - } - -@@ -304,7 +322,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) - { - struct v4l2_format *f = &ctx->coded_fmt; - -- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0]; -+ ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); - - f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -@@ -331,11 +349,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, - struct v4l2_frmsizeenum *fsize) - { - const struct rkvdec_coded_fmt_desc *fmt; -+ struct rkvdec_dev *rkvdec = video_drvdata(file); - - if (fsize->index != 0) - return -EINVAL; - -- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format); -+ fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format, -+ rkvdec->capabilities); - if (!fmt) - return -EINVAL; - -@@ -406,10 +426,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, - struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); - const struct rkvdec_coded_fmt_desc *desc; - -- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat, -+ ctx->dev->capabilities); - if (!desc) { -- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc; -- desc = &rkvdec_coded_fmts[0]; -+ desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); -+ pix_mp->pixelformat = desc->fourcc; - } - - v4l2_apply_frmsize_constraints(&pix_mp->width, -@@ -487,7 +508,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, - if (ret) - return ret; - -- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat, -+ ctx->dev->capabilities); - if (!desc) - return -EINVAL; - ctx->coded_fmt_desc = desc; -@@ -538,7 +560,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, - static int rkvdec_enum_output_fmt(struct file *file, void *priv, - struct v4l2_fmtdesc *f) - { -- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts)) -+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); -+ -+ if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) || -+ !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability)) - return -EINVAL; - - f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; -@@ -947,14 +972,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) - int ret; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) -- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; -+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) -+ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; - - v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -- if (ret) -- goto err_free_handler; -+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) { -+ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -+ if (ret) -+ goto err_free_handler; -+ } - } - - ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); -@@ -1156,8 +1184,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+static const struct rkvdec_variant rk3399_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_HEVC | -+ RKVDEC_CAPABILITY_VP9 -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { -- { .compatible = "rockchip,rk3399-vdec" }, -+ { -+ .compatible = "rockchip,rk3399-vdec", -+ .data = &rk3399_rkvdec_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1169,6 +1206,7 @@ static const char * const rkvdec_clk_names[] = { - static int rkvdec_probe(struct platform_device *pdev) - { - struct rkvdec_dev *rkvdec; -+ const struct rkvdec_variant *variant; - unsigned int i; - int ret, irq; - -@@ -1194,6 +1232,13 @@ static int rkvdec_probe(struct platform_device *pdev) - if (ret) - return ret; - -+ variant = of_device_get_match_data(rkvdec->dev); -+ if (!variant) -+ return -EINVAL; -+ -+ rkvdec->capabilities = variant->capabilities; -+ -+ - rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(rkvdec->regs)) - return PTR_ERR(rkvdec->regs); -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -29,6 +29,10 @@ - - #define RKVDEC_RESET_DELAY 5 - -+#define RKVDEC_CAPABILITY_H264 BIT(0) -+#define RKVDEC_CAPABILITY_HEVC BIT(1) -+#define RKVDEC_CAPABILITY_VP9 BIT(2) -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - base.vb.vb2_buf); - } - -+struct rkvdec_variant { -+ unsigned int capabilities; -+}; -+ - struct rkvdec_coded_fmt_ops { - int (*adjust_fmt)(struct rkvdec_ctx *ctx, - struct v4l2_format *f); -@@ -91,6 +99,7 @@ struct rkvdec_coded_fmt_desc { - unsigned int num_decoded_fmts; - const u32 *decoded_fmts; - u32 subsystem_flags; -+ unsigned int capability; - }; - - struct rkvdec_dev { -@@ -105,6 +114,7 @@ struct rkvdec_dev { - struct delayed_work watchdog_work; - struct reset_control *rstc; - u8 reset_mask; -+ unsigned int capabilities; - }; - - struct rkvdec_ctx { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 30 Jan 2021 18:21:59 +0100 -Subject: media: rkvdec: add RK3288 variant - -This adds RK3288 variant to rkvdec driver. In this earlier version -of the IP only HEVC decoding is supported. - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1190,11 +1190,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { - RKVDEC_CAPABILITY_VP9 - }; - -+static const struct rkvdec_variant rk3288_hevc_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { - { - .compatible = "rockchip,rk3399-vdec", - .data = &rk3399_rkvdec_variant, - }, -+ { -+ .compatible = "rockchip,rk3288-hevc", -+ .data = &rk3288_hevc_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 30 Jan 2021 18:27:30 +0100 -Subject: ARM: dts: RK3288: add hevc node - -Signed-off-by: Alex Bee ---- - arch/arm/boot/dts/rockchip/rk3288.dtsi | 21 +++++++++- - 1 file changed, 20 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -1307,6 +1307,25 @@ vpu_mmu: iommu@ff9a0800 { - power-domains = <&power RK3288_PD_VIDEO>; - }; - -+ hevc: hevc@ff9c0000 { -+ compatible = "rockchip,rk3288-hevc"; -+ reg = <0x0 0xff9c0000 0x0 0x400>; -+ interrupts = ; -+ interrupt-names = "irq_dec"; -+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>, -+ <&cru SCLK_HEVC_CORE>; -+ clock-names = "axi", "ahb", "cabac", "core"; -+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, -+ <&cru SCLK_HEVC_CORE>, -+ <&cru SCLK_HEVC_CABAC>; -+ assigned-clock-rates = <400000000>, <100000000>, -+ <300000000>, <300000000>; -+ iommus = <&hevc_mmu>; -+ power-domains = <&power RK3288_PD_HEVC>; -+ resets = <&cru SRST_HEVC>; -+ reset-names = "video_core"; -+ }; -+ - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; -@@ -1314,7 +1333,7 @@ hevc_mmu: iommu@ff9c0440 { - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -- status = "disabled"; -+ power-domains = <&power RK3288_PD_HEVC>; - }; - - gpu: gpu@ffa30000 { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Dufresne -Date: Tue, 10 May 2022 14:37:29 -0400 -Subject: media: rkvdec: Fix HEVC RPS bit offsets - -The offsets from the uAPI need to be extended to include some bits -that can be calculated from the parameters. This has been compared -to match with the vendor bit sizes (which simply parse again the -data to calcualte it). - -Fixed by this change: -- LTRPSPS_A_Qualcomm_1 -- RPS_C_ericsson_5 -- RPS_D_ericsson_6 -- RPS_E_qualcomm_5 - -Signed-off-by: Nicolas Dufresne ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 26 ++++++++-- - 1 file changed, 23 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -10,6 +10,7 @@ - */ - - #include -+#include - - #include "rkvdec.h" - #include "rkvdec-regs.h" -@@ -2175,6 +2176,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run) - { - const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; - const struct v4l2_ctrl_hevc_slice_params *sl_params; - const struct v4l2_hevc_dpb_entry *dpb; - struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -@@ -2196,9 +2198,21 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - #define NUM_RPS_POC PS_FIELD(202, 4) - - for (j = 0; j < run->num_slices; j++) { -+ uint st_bit_offset = 0; -+ - sl_params = &run->slices_params[j]; - dpb = decode_params->dpb; -- lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; -+ -+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { -+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; -+ -+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) -+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; -+ -+ lowdelay = 1; -+ } else { -+ lowdelay = 0; -+ } - - hw_ps = &priv_tbl->rps[j]; - memset(hw_ps, 0, sizeof(*hw_ps)); -@@ -2224,8 +2238,14 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - WRITE_RPS(lowdelay, LOWDELAY); - -- WRITE_RPS(sl_params->long_term_ref_pic_set_size + -- sl_params->short_term_ref_pic_set_size, -+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { -+ if (sl_params->short_term_ref_pic_set_size) -+ st_bit_offset = sl_params->short_term_ref_pic_set_size; -+ else if (sps->num_short_term_ref_pic_sets > 1) -+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); -+ } -+ -+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, - LONG_TERM_RPS_BIT_OFFSET); - WRITE_RPS(sl_params->short_term_ref_pic_set_size, - SHORT_TERM_RPS_BIT_OFFSET); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Dufresne -Date: Tue, 10 May 2022 15:12:03 -0400 -Subject: media: rkvdec: Fix number of HEVC references being set in RPS - -The numbers from the bitstream are values between 1 - 16 (as they are -the number - 1). The difference between 0 and 1 needs to be determined -base on the slice type. I frames have no reference, P frames only have -L0 reference, and B frames have both. - -Signed-off-by: Nicolas Dufresne ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - for (j = 0; j < run->num_slices; j++) { - uint st_bit_offset = 0; -+ uint num_l0_refs = 0; -+ uint num_l1_refs = 0; - - sl_params = &run->slices_params[j]; - dpb = decode_params->dpb; -@@ -2217,7 +2219,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - hw_ps = &priv_tbl->rps[j]; - memset(hw_ps, 0, sizeof(*hw_ps)); - -- for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -+ for (i = 0; i < num_l0_refs; i++) { - WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L0(i)); - WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -@@ -2227,7 +2229,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - } - -- for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -+ for (i = 0; i < num_l1_refs; i++) { - WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L1(i)); - WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/general-workaround-broadcom-bt-serdev.patch b/patch/kernel/rockchip64-6.14/general-workaround-broadcom-bt-serdev.patch deleted file mode 100644 index 882460f..0000000 --- a/patch/kernel/rockchip64-6.14/general-workaround-broadcom-bt-serdev.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Sat, 1 May 2021 12:41:14 +0000 -Subject: Workaround to make several broadcom bluetooth serdev devices work - even without proper MAC address - ---- - drivers/bluetooth/btbcm.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c -index 111111111111..222222222222 100644 ---- a/drivers/bluetooth/btbcm.c -+++ b/drivers/bluetooth/btbcm.c -@@ -135,7 +135,7 @@ int btbcm_check_bdaddr(struct hci_dev *hdev) - if (btbcm_set_bdaddr_from_efi(hdev) != 0) { - bt_dev_info(hdev, "BCM: Using default device address (%pMR)", - &bda->bdaddr); -- set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks); -+ //set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks); - } - } - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/kernel-6.8-tools-cgroup-makefile.patch b/patch/kernel/rockchip64-6.14/kernel-6.8-tools-cgroup-makefile.patch deleted file mode 100644 index 7bf4a25..0000000 --- a/patch/kernel/rockchip64-6.14/kernel-6.8-tools-cgroup-makefile.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Mon, 25 Mar 2024 19:38:38 +0100 -Subject: [ARCHEOLOGY] rockchip: bump edge kernel to 6.8 - -> X-Git-Archeology: - Revision 47d2e8287e34fed3e47f37ab076d0f34ed0ac399: https://github.com/armbian/build/commit/47d2e8287e34fed3e47f37ab076d0f34ed0ac399 -> X-Git-Archeology: Date: Mon, 25 Mar 2024 19:38:38 +0100 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip: bump edge kernel to 6.8 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 724573bf7a21e61b0b626f835031a4c3206bb8ba: https://github.com/armbian/build/commit/724573bf7a21e61b0b626f835031a4c3206bb8ba -> X-Git-Archeology: Date: Wed, 05 Jun 2024 22:18:51 +0200 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: bump rockchip family edge kernel to 6.9 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 4ae0a958146810117050d0dbd359b99691a0fa0c: https://github.com/armbian/build/commit/4ae0a958146810117050d0dbd359b99691a0fa0c -> X-Git-Archeology: Date: Mon, 22 Jul 2024 19:17:52 +0200 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip64: bump edge kernel to 6.10 -> X-Git-Archeology: ---- - tools/cgroup/Makefile | 11 ++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/tools/cgroup/Makefile b/tools/cgroup/Makefile -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/tools/cgroup/Makefile -@@ -0,0 +1,11 @@ -+# SPDX-License-Identifier: GPL-2.0 -+# Makefile for cgroup tools -+ -+CFLAGS = -Wall -Wextra -+ -+all: cgroup_event_listener -+%: %.c -+ $(CC) $(CFLAGS) -o $@ $^ -+ -+clean: -+ $(RM) cgroup_event_listener --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/overlay/Makefile b/patch/kernel/rockchip64-6.14/overlay/Makefile deleted file mode 100644 index fd90f1e..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/Makefile +++ /dev/null @@ -1,107 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ - hinlink-h88k-240x135-lcd.dtbo \ - rk3308-s0-ext-antenna.dtbo \ - rk3308-b@1.3ghz.dtbo \ - rk3308-bs.dtbo rk3308-bs@1.3ghz.dtbo \ - rk3308-emmc.dtbo \ - rk3308-sdio@10mhz.dtbo rk3308-sdio@4mhz.dtbo \ - rockchip-sakurapi-rk3308b-ws2812.dtbo \ - rockchip-rockpi4cplus-usb-host.dtbo \ - rockchip-rockpro64-lcd.dtbo \ - rockchip-rk3318-box-cpu-hs.dtbo \ - rockchip-rk3318-box-emmc-ddr.dtbo \ - rockchip-rk3318-box-emmc-hs200.dtbo \ - rockchip-rk3318-box-led-conf1.dtbo \ - rockchip-rk3318-box-led-conf2.dtbo \ - rockchip-rk3318-box-led-conf3.dtbo \ - rockchip-rk3318-box-led-conf4.dtbo \ - rockchip-rk3318-box-led-conf5.dtbo \ - rockchip-rk3318-box-wlan-ap6330.dtbo \ - rockchip-rk3318-box-wlan-ap6334.dtbo \ - rockchip-rk3318-box-wlan-ext.dtbo \ - rockchip-rk3328-i2c0.dtbo \ - rockchip-rk3328-i2s1-pcm5102.dtbo \ - rockchip-rk3328-mksklipad50-enable-rtc-end1.dtbo \ - rockchip-rk3328-mksklipad50-enable-v4l2.dtbo \ - rockchip-rk3328-mkspi-disable-lcd-spi.dtbo \ - rockchip-rk3328-opp-1.4ghz.dtbo \ - rockchip-rk3328-opp-1.5ghz.dtbo \ - rockchip-rk3328-spi-spidev.dtbo \ - rockchip-rk3328-uart1.dtbo \ - rockchip-rk3399-dwc3-0-host.dtbo \ - rockchip-rk3399-i2c7.dtbo \ - rockchip-rk3399-i2c8.dtbo \ - rockchip-rk3399-opp-2ghz.dtbo \ - rockchip-rk3399-pcie-gen2.dtbo \ - rockchip-rk3399-spi-jedec-nor.dtbo \ - rockchip-rk3399-spi-spidev.dtbo \ - rockchip-rk3399-uart4.dtbo \ - rockchip-rk3399-w1-gpio.dtbo \ - rockchip-rk3566-sata2.dtbo \ - rockchip-rk3568-nanopi-r5c-leds.dtbo \ - rockchip-rk3568-nanopi-r5s-leds.dtbo \ - rockchip-rk3568-hk-i2c0.dtbo \ - rockchip-rk3568-hk-i2c1.dtbo \ - rockchip-rk3568-hk-pwm1.dtbo \ - rockchip-rk3568-hk-pwm2.dtbo \ - rockchip-rk3568-hk-pwm9.dtbo \ - rockchip-rk3568-hk-spi-spidev.dtbo \ - rockchip-rk3568-hk-uart0.dtbo \ - rockchip-rk3568-hk-uart0-rts_cts.dtbo \ - rockchip-rk3568-hk-uart1.dtbo \ - rockchip-rk3568-rock-3a-disable-uart2.dtbo \ - rockchip-rk3588-fanctrl.dtbo \ - rockchip-rk3588-sata1.dtbo \ - rockchip-rk3588-sata2.dtbo \ - rockchip-rk3588-hdmirx.dtbo \ - rockchip-rk3588-i2c8-m2.dtbo \ - rockchip-rk3588-pwm0-m0.dtbo \ - rockchip-rk3588-pwm0-m1.dtbo \ - rockchip-rk3588-pwm0-m2.dtbo \ - rockchip-rk3588-pwm1-m0.dtbo \ - rockchip-rk3588-pwm1-m1.dtbo \ - rockchip-rk3588-pwm1-m2.dtbo \ - rockchip-rk3588-pwm2-m1.dtbo \ - rockchip-rk3588-pwm3-m0.dtbo \ - rockchip-rk3588-pwm3-m1.dtbo \ - rockchip-rk3588-pwm3-m2.dtbo \ - rockchip-rk3588-pwm3-m3.dtbo \ - rockchip-rk3588-pwm5-m2.dtbo \ - rockchip-rk3588-pwm6-m0.dtbo \ - rockchip-rk3588-pwm6-m2.dtbo \ - rockchip-rk3588-pwm7-m0.dtbo \ - rockchip-rk3588-pwm7-m3.dtbo \ - rockchip-rk3588-pwm8-m0.dtbo \ - rockchip-rk3588-pwm10-m0.dtbo \ - rockchip-rk3588-pwm11-m0.dtbo \ - rockchip-rk3588-pwm11-m1.dtbo \ - rockchip-rk3588-pwm12-m0.dtbo \ - rockchip-rk3588-pwm13-m0.dtbo \ - rockchip-rk3588-pwm13-m2.dtbo \ - rockchip-rk3588-pwm14-m0.dtbo \ - rockchip-rk3588-pwm14-m1.dtbo \ - rockchip-rk3588-pwm14-m2.dtbo \ - rockchip-rk3588-pwm15-m0.dtbo \ - rockchip-rk3588-pwm15-m1.dtbo \ - rockchip-rk3588-pwm15-m2.dtbo \ - rockchip-rk3588-pwm15-m3.dtbo \ - rockchip-rk3588-uart1-m1.dtbo \ - rockchip-rk3588-uart3-m1.dtbo \ - rockchip-rk3588-uart4-m2.dtbo \ - rockchip-rk3588-uart6-m1.dtbo \ - rockchip-rk3588-uart7-m2.dtbo \ - rockchip-rk3588-uart8-m1.dtbo \ - rockchip-rk3588-rkvenc-overlay.dtbo \ - rockchip-rk3588-nanopi-m6-spi-nor-flash.dtbo - -scr-$(CONFIG_ARCH_ROCKCHIP) += \ - rockchip-fixup.scr - -dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \ - README.rockchip-overlays - -dtb-y += $(dtbo-y) $(scr-y) $(dtbotxt-y) - -clean-files := *.dtbo *.scr - diff --git a/patch/kernel/rockchip64-6.14/overlay/README.rockchip-overlays b/patch/kernel/rockchip64-6.14/overlay/README.rockchip-overlays deleted file mode 100644 index 56530cc..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/README.rockchip-overlays +++ /dev/null @@ -1,263 +0,0 @@ -This document describes overlays provided in the kernel packages -For generic Armbian overlays documentation please see -https://docs.armbian.com/User-Guide_Allwinner_overlays/ - -### Platform: - -rockchip (Rockchip) - -### Provided overlays: - -- i2c7, i2c8, pcie-gen2, spi-spidev, uart4, w1-gpio - -for RK3308 (Rock PI-S) - -- rk3308bs rk3308bs-1.3ghz sdio-10mhz sdio-4mhz emmc - -### Overlay details: - -### mkspi-disable-lcd-spi - -DTBO to disable spi_for_{lcd,touch} when enabling uart1 - -### i2c7 - -Activates TWI/I2C bus 7 - -I2C7 pins (SCL, SDA): GPIO2-B0, GPIO2-A7 GPIO1-C5, GPIO1-C4 - -### i2c8 - -Activates TWI/I2C bus 8 - -I2C8 pins (SCL, SDA): GPIO1-C5, GPIO1-C4 - -### pcie-gen2 - -Enables PCIe Gen2 link speed on RK3399. -WARNING! Not officially supported by Rockchip!!! - -### rk3328-i2c0 - -Activates TWI/I2C bus 0 - -I2C0 (SCL, SDA): GPIO2-D0, GPIO2-D1 - -### rk3328-uart1 - -Activates UART1 - -UART1 pins (RX, TX): GPIO3_A6, GPIO3_A4 - -### rk3328-opp-1.4ghz - -Adds the 1.4GHz opp for overclocking -WARNING! Not officially supported by Rockchip!!! - -### rk3328-opp-1.5ghz - -Adds the 1.5GHz opp for overclocking -WARNING! Not officially supported by Rockchip!!! - -### rk3399-opp-2ghz - -Adds the 2GHz big and 1.5 GHz LITTLE opps for overclocking -WARNING! Not officially supported by Rockchip!!! - -### rockpi4cplus-usb-host - -Switches the top USB 3.0 port to host mode. -WARNING! Not officially supported by Rockchip!!! - -### spi-jedec-nor - -Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus -supported by the kernel SPI NOR driver - -SPI 0 pins (MOSI, MISO, SCK, CS): GPIO3_A5, GPIO3_A4, GPIO3_A6, GPIO3_A7 -SPI 1 pins (MOSI, MISO, SCK, CS): GPIO1_A7, GPIO1_B0, GPIO1_B1, GPIO1_B2 -SPI 2 pins (MOSI, MISO, SCK, CS): GPIO1_C0, GPIO1_B7, GPIO1_C1, GPIO1_C2 -SPI 3 pins (MOSI, MISO, SCK, CS): GPIO2_B2, GPIO2_B1, GPIO2_B3, GPIO2_B4 - -Parameters: - -param_spinor_spi_bus (int) - SPI bus to activate SPI NOR flash support on - Required - Supported values: 0, 1, 2 - -param_spinor_max_freq (int) - Maximum SPI frequency - Optional - Default: 1000000 - Range: 3000 - 100000000 - -### spi-spidev - -Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, -where X is the bus number and Y is the CS number - -SPI 0 pins (MOSI, MISO, SCK, CS): GPIO3_A5, GPIO3_A4, GPIO3_A6, GPIO3_A7 -SPI 1 pins (MOSI, MISO, SCK, CS): GPIO1_A7, GPIO1_B0, GPIO1_B1, GPIO1_B2 -SPI 2 pins (MOSI, MISO, SCK, CS): GPIO1_C0, GPIO1_B7, GPIO1_C1, GPIO1_C2 -SPI 3 pins (MOSI, MISO, SCK, CS): GPIO2_B2, GPIO2_B1, GPIO2_B3, GPIO2_B4 - -Parameters: - -param_spidev_spi_bus (int) - SPI bus to activate SPIdev support on - Required - Supported values: 0, 1 - -param_spidev_spi_cs (int) - SPI chip select number - Optional - Default: 0 - Supported values: 0, 1 - Using chip select 1 requires using "spi-add-cs1" overlay - -param_spidev_max_freq (int) - Maximum SPIdev frequency - Optional - Default: 1000000 - Range: 3000 - 100000000 - -### uart4 - -Activates UART4 - -UART4 pins (RX, TX): GPIO1_A7, GPIO1_B0 - -Notice: UART4 cannot be activated together with SPI1 - they share the sam pins. -Enabling this overlay disables SPI1. - -### dwc3-0-host - -Forces port 0 of the DesignWare xHCI controller to host mode. - -This can be used on plaforms such as NanoPC-T4, where devices plugged into the -USB-C port may not be detected otherwise. - -### w1-gpio - -Activates 1-Wire GPIO master -Requires an external pull-up resistor on the data pin -or enabling the internal pull-up - -### rk3318-box-led-conf1 - -Activates led/gpio configuration for rk3318 tv box boards with signature -YX_RK3328 and clones - -### rk3318-box-led-conf2 - -Activates led/gpio configuration for rk3318 tv box boards withs signature -X88_PRO_B and clones - -### rk3318-box-led-conf3 - -This device tree overlay is suitable for MXQ-RK3328-D4_A board which -has an integrated PMIC (RK805). The dtbo is very important to achieve -1.3 Ghz speed for CPU and stable voltages for other parts of the -system. Also enables gpio leds and keys. - -### rk3318-box-led-conf4 - -Generic rk3318-box configuration but with sdio chip on sdmmc-ext connector - -### rk3318-box-emmc-ddr - -Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips -nowadays support DDR mode, but its reliability heavily depends upon the quality -of board wiring - -### rk3318-box-emmc-hs200 - -Activates eMMC HS200 capability for rk3318 tv box boards. -It should in autodetect mode, but some board have faulty or cheap circuitry that -enable the mode but then it doesn't work correctly. - -### rk3318-box-wlan-ap6334 - -Set up additional device tree bits to properly support ap6334 (broadcom BCM4334) -wifi chip and clones - -### rk3318-box-wlan-ext - -Use sdmmc_ext device for sdio devices, enabled wifi on some boards (notably -X88 Pro) which have wifi chip attached to sdmmc_ext controller. - -### rk3318-box-wlan-ap6330 - -Set up additional device tree bits properly support ap6330 (broaccom BCM4330) -wifi + bt chip and clones. - -### rk3318-box-cpu-hs - -Enable additional cpu "high-speed" bins up to 1.3ghz - -********************************** -Details for Rock Pi-S overlays (2 Mar 2024): - -Older V1.1 and V1.2 boards use the B variant of the RK3308. -Some V1.3 boards manufactured after October 2023 also use the B variant. -To overclock the RK3308B, apply: -### rk3308-b@1.3ghz - -V1.3 boards produced during 2022 and most of 2023 use the lower voltage -B-S variant of the RK3308. -Per Radxa, these chips will be marked RK3308BS instead of RK3308B -All boards utilizing the RK3308B-S part should apply the: -### rk3308-bs -overlay to operate at the appropriate (lower) the core voltage. -This overlay also enables operation at 1.1Ghz. - -Optionally, boards utilizing the RK3308B-S parts may add the -### rk3308-bs@1.3ghz -to overclock the B-S CPU to 1.3Ghz. -Apply the rk3308-bs@1.3Ghz overlay *after applying* rk3308-bs - -Applying the *-bs overlays to the B variant of the SOC may result in -unstable operation due to undervolting. -Applying the rk3308-b@1.3ghz to a BS variant chip consumes more power and -has the potential to damage the SOC due to overvolting. - -===== For Older Kernels ====== -Install the following overlays only on older (unpatched) mainline kernels: - -Older mainline kernels disable the Rock Pi S built-in SDNAND (EMMC) -### rk3308-emmc -enables your SDNAND chip. It is OK to install for boards that lack the SDNAND. - -The legacy 4.4 and this mainline kernel drive the SDIO clock at 50Mhz to provide -maximum WiFi throughput. However... - -Older versions of the Mainline kernel drive the SDIO clock at only 1Mhz -This reduces WiFi throughput to < 500kB/s ! - -### rk3308-sdio@10mhz -increases the SDIO clock to 10Mhz, providing about 2.4MB/s WiFi throughput. - -### rk3308-sdio@4mhz -increases the SDIO clock to only 4Mhz, providing about 1MB/s WiFi throughput. -use this only if 10Mhz SDIO clock is unstable - -Note that older mainline kernels cannot drive the SDIO clock faster than 10Mhz. - - -********************************** -Details for Rock S0 overlays (10 Apr 2024): - -By default, the internal WiFi selects its internal chip antenna. -This antenna is so noisy as to be nearly unusable. -The external antenna, fortunately, works quite well. -Connect an external WiFi antenna and select it with: -### rk3308-s0-ext-antenna - -All Rock S0 boards use the RK3308B chip. -The: -### rk3308-b@1.3ghz -overlay enables (overclocked) operation at 1.3ghz -1.3Ghz operation appears stable on the two boards I've tested. - -The legacy kernel is not supported on the Rock S0 diff --git a/patch/kernel/rockchip64-6.14/overlay/hinlink-h88k-240x135-lcd.dtso b/patch/kernel/rockchip64-6.14/overlay/hinlink-h88k-240x135-lcd.dtso deleted file mode 100644 index 011962e..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/hinlink-h88k-240x135-lcd.dtso +++ /dev/null @@ -1,64 +0,0 @@ -/dts-v1/; -/plugin/; -#include -#include -#include - -/ { - fragment@0 { - target = <&spi4>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - assigned-clocks = <&cru CLK_SPI4>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi4_custom_pins &spi4m2_cs0>; - status = "okay"; - - panel: panel@0 { - compatible = "hinlink-h88k-240x135-lcd", "panel-mipi-dbi-spi"; - reg = <0>; - - spi-max-frequency = <2000000>; - - width-mm = <25>; - height-mm = <15>; - - dc-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - - write-only; - - timing: panel-timing { - hactive = <240>; - vactive = <135>; - hback-porch = <40>; - vback-porch = <52>; - - clock-frequency = <0>; - hfront-porch = <0>; - hsync-len = <0>; - vfront-porch = <0>; - vsync-len = <0>; - }; - }; - }; - }; - fragment@1 { - target = <&pinctrl>; - __overlay__ { - lcd { - spi4_custom_pins: spi4-custom-pins { - rockchip,pins = - /* spi4_clk_m2 */ - <1 RK_PA2 8 &pcfg_pull_up_drv_level_6>, - /* spi4_mosi_m2 */ - <1 RK_PA1 8 &pcfg_pull_up_drv_level_6>, - /* spi4_miso_m0 */ - <1 RK_PC0 8 &pcfg_pull_up_drv_level_6>; - }; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rk3308-b@1.3ghz.dtso b/patch/kernel/rockchip64-6.14/overlay/rk3308-b@1.3ghz.dtso deleted file mode 100644 index 4f022bd..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rk3308-b@1.3ghz.dtso +++ /dev/null @@ -1,27 +0,0 @@ -//Overclock the Rockchip RK3308-B suffix SOC to 1.3 Ghz -// THIS SHOULD NOT BE APPLIED to RK3308-B-S suffix chips -// because is will overvolt them - -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&cpu0_opp_table>; - __overlay__ { - //the following are unsupported, overclocked operating points - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1250000 1250000 1340000>; - clock-latency-ns = <40000>; - status = "okay"; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1300000 1300000 1340000>; - clock-latency-ns = <40000>; - status = "okay"; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rk3308-bs.dtso b/patch/kernel/rockchip64-6.14/overlay/rk3308-bs.dtso deleted file mode 100644 index 978f679..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rk3308-bs.dtso +++ /dev/null @@ -1,39 +0,0 @@ -//Adjustments for Rockchip RK3308-BS suffix SOC -//https://dl.radxa.com/rockpis/docs/sw/RK3308B-S&RK3308H-S_Software_Compatibility_Introduction_V1.0.0_20211016.pdf - -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&cpu0_opp_table>; - __overlay__ { - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <850000 850000 1200000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000 900000 1200000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000 1000000 1200000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1125000 1125000 1200000>; - clock-latency-ns = <40000>; - }; - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <1200000 1200000 1200000>; - clock-latency-ns = <40000>; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rk3308-bs@1.3ghz.dtso b/patch/kernel/rockchip64-6.14/overlay/rk3308-bs@1.3ghz.dtso deleted file mode 100644 index 3fae0dd..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rk3308-bs@1.3ghz.dtso +++ /dev/null @@ -1,26 +0,0 @@ -//Overclock the Rockchip RK3308-BS suffix SOC to 1.3 Ghz -// assumes rk3308bs-rock-pi-s.dts overlay has already been added - -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&cpu0_opp_table>; - __overlay__ { - //the following are unsupported, overclocked operating points - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1200000 1200000 1200000>; - clock-latency-ns = <40000>; - status = "okay"; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1200000 1200000 1200000>; - clock-latency-ns = <40000>; - status = "okay"; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rk3308-emmc.dtso b/patch/kernel/rockchip64-6.14/overlay/rk3308-emmc.dtso deleted file mode 100644 index 4a4c380..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rk3308-emmc.dtso +++ /dev/null @@ -1,13 +0,0 @@ -//For RockPI-S: enable SDnand chip - -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&emmc>; - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rk3308-s0-ext-antenna.dtso b/patch/kernel/rockchip64-6.14/overlay/rk3308-s0-ext-antenna.dtso deleted file mode 100644 index 7fa7638..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rk3308-s0-ext-antenna.dtso +++ /dev/null @@ -1,48 +0,0 @@ -//Select Rock S0's external WiFi antenna input -//(instead of default internal WiFi antenna) - -/dts-v1/; -/plugin/; -#include -#include - -/ { - fragment@0 { - target-path = "/"; - - __overlay__ { - ext_antenna: ext-antenna { - status = "okay"; - compatible = "regulator-fixed"; - enable-active-low; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - pinctrl-0 = <&ant_2>; - pinctrl-names = "default"; - regulator-name = "ext_antenna"; - }; - }; - }; - - fragment@1 { - target = <&board_antenna>; - - __overlay__ { - status = "disabled"; - }; - }; - - fragment@2 { - target = <&pinctrl>; - - __overlay__ { - antenna { - ant_2: ant-2 { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - }; - }; -}; - diff --git a/patch/kernel/rockchip64-6.14/overlay/rk3308-sdio@10mhz.dtso b/patch/kernel/rockchip64-6.14/overlay/rk3308-sdio@10mhz.dtso deleted file mode 100644 index c7f2e28..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rk3308-sdio@10mhz.dtso +++ /dev/null @@ -1,14 +0,0 @@ -//For RockPI-S: Increase SDIO Max Frequency from 1Mhz to 10Mhz -//Increases RTL8723-BS WiFi's throughput from 300KB/s to 2.4MB/s - -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&sdio>; - __overlay__ { - max-frequency = <10000000>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rk3308-sdio@4mhz.dtso b/patch/kernel/rockchip64-6.14/overlay/rk3308-sdio@4mhz.dtso deleted file mode 100644 index efcc5c2..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rk3308-sdio@4mhz.dtso +++ /dev/null @@ -1,14 +0,0 @@ -//For RockPI-S: Increase SDIO Max Frequency from 1Mhz to 4Mhz -//Increases RTL8723-BS WiFi's throughput from 300KB/s to 1MB/s - -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&sdio>; - __overlay__ { - max-frequency = <4000000>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-fixup.scr-cmd b/patch/kernel/rockchip64-6.14/overlay/rockchip-fixup.scr-cmd deleted file mode 100644 index c6cd5d8..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-fixup.scr-cmd +++ /dev/null @@ -1,65 +0,0 @@ -# overlays fixup script -# implements (or rather substitutes) overlay arguments functionality -# using u-boot scripting, environment variables and "fdt" command - -setenv decompose_pin 'setexpr tmp_pinctrl sub "GPIO(0|1|2|3|4)_\\S\\d+" "\\1"; -setexpr tmp_bank sub "GPIO\\d_(\\S)\\d+" "\\1"; -test "${tmp_bank}" = "A" && setenv tmp_bank 0; -test "${tmp_bank}" = "B" && setenv tmp_bank 1; -test "${tmp_bank}" = "C" && setenv tmp_bank 2; -test "${tmp_bank}" = "D" && setenv tmp_bank 3; -setexpr tmp_pin sub "GPIO\\d_\\S(\\d+)" "\\1"; -setexpr tmp_bank ${tmp_bank} * 8; -setexpr tmp_pin ${tmp_bank} + ${tmp_pin}' - -if test -n "${param_spidev_max_freq}"; then - fdt set /spi@fe610000/spidev spi-max-frequency "<${param_spidev_max_freq}>" -fi - -if test -n "${param_spinor_spi_bus}"; then - test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@ff1c0000" - test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@ff1d0000" - test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@ff1e0000" - test "${param_spinor_spi_bus}" = "3" && setenv tmp_spi_path "spi@ff1f0000" - fdt set /${tmp_spi_path} status "okay" - fdt set /${tmp_spi_path}/spiflash@0 status "okay" - if test -n "${param_spinor_max_freq}"; then - fdt set /${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" - fi - if test "${param_spinor_spi_cs}" = "1"; then - fdt set /${tmp_spi_path}/spiflash@0 reg "<1>" - fi - env delete tmp_spi_path -fi - -if test -n "${param_spidev_spi_bus}"; then - test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@ff1c0000" - test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@ff1d0000" - test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@ff1e0000" - test "${param_spidev_spi_bus}" = "3" && setenv tmp_spi_path "spi@ff1f0000" - fdt set /${tmp_spi_path} status "okay" - fdt set /${tmp_spi_path}/spidev status "okay" - if test -n "${param_spidev_max_freq}"; then - fdt set /${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" - fi - if test "${param_spidev_spi_cs}" = "1"; then - fdt set /${tmp_spi_path}/spidev reg "<1>"; - fi -fi - -if test -n "${param_w1_pin}"; then - setenv tmp_pinctrl "${param_w1_pin}" - setenv tmp_bank "${param_w1_pin}" - setenv tmp_pin "${param_w1_pin}" - run decompose_pin - #echo "${param_w1_pin} ---> pinctrl = ${tmp_pinctrl}" - #echo "${param_w1_pin} ---> bank = ${tmp_bank}" - #echo "${param_w1_pin} ---> pin = ${tmp_pin}" - fdt get value tmp_pinctrl /__symbols__ gpio${tmp_pinctrl} - #echo "${param_w1_pin} ---> tmp_pinctrl = ${tmp_pinctrl}" - fdt get value tmp_phandle ${tmp_pinctrl} phandle - #echo "${param_w1_pin} ---> tmp_phandle = ${tmp_phandle}" - fdt set /onewire@0 gpios "<${tmp_phandle} 0x000000${tmp_pin} 0 0>" - env delete tmp_pinctrl tmp_bank tmp_pin tmp_phandle -fi - diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-cpu-hs.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-cpu-hs.dtso deleted file mode 100644 index e6bc1ad..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-cpu-hs.dtso +++ /dev/null @@ -1,24 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - - fragment@0 { - target-path = "/opp_table0/opp-1200000000"; - __overlay__ { - - status = "okay"; - - }; - }; - - fragment@1 { - target-path = "/opp_table0/opp-1296000000"; - __overlay__ { - - status = "okay"; - - }; - }; - -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-emmc-ddr.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-emmc-ddr.dtso deleted file mode 100644 index b8f1390..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-emmc-ddr.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - - fragment@0 { - target = <&emmc>; - __overlay__ { - status = "okay"; - mmc-ddr-1_8v; - }; - }; - -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-emmc-hs200.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-emmc-hs200.dtso deleted file mode 100644 index 55f8f7e..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-emmc-hs200.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - - fragment@0 { - target = <&emmc>; - __overlay__ { - status = "okay"; - mmc-hs200-1_8v; - }; - }; - -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf1.dtso deleted file mode 100644 index fd15c8b..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf1.dtso +++ /dev/null @@ -1,36 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include - -/** - * Generic rk3318 board with base common configuration. - * Some boards with this configuration have signature: RK3318_V1.x - */ - -&gpio_led { - - working { - gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - }; - -}; - -/* - * TODO: needs to find the GPIO for this - * -&gpio_keys { - - reset { - gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - debounce-interval = <200>; - wakeup-source; - }; - -}; -*/ diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf2.dtso deleted file mode 100644 index 5b6890a..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf2.dtso +++ /dev/null @@ -1,111 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include -#include - - -&gpio_led { - - working { - gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - -}; - -&{/} { - - i2c_aux_display: i2c-aux-display { - - #address-cells = <1>; - #size-cells = <0>; - compatible = "spi-gpio"; - sck-gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - aux-display-controller@24 { - - compatible = "fdhisi,fd628"; - - reg = <0x24>; - spi-3wire; - spi-lsb-first; - spi-rx-delay-us = <1>; - spi-max-frequency = <500000>; - - tm16xx,digits = [00 01 02 03]; - tm16xx,segment-mapping = [03 01 02 06 04 05 00]; - - #address-cells = <2>; - #size-cells = <0>; - - led@4,3 { - reg = <4 3>; - function = LED_FUNCTION_POWER; - }; - - led@4,2 { - reg = <4 2>; - function = LED_FUNCTION_LAN; - linux,default-trigger = "stmmac-0:00:link"; - }; - - led@4,4 { - reg = <4 4>; - function = "colon"; - }; - - led@4,5 { - reg = <4 5>; - function = "wlan-lo"; - }; - - led@4,6 { - reg = <4 6>; - function = "wlan-hi"; - linux,default-trigger = "mmc1"; - }; - - }; - }; - -}; - -&vcc_otg_vbus { - gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; -}; - -&working_led { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none_2ma>; -}; - -&io_domains { - vccio6-supply = <&vcc_18>; -}; - -/* - * Following section enables the sdio bus on sdmmc_ext controller - */ -&sdio { - /delete-property/ mmc-pwrseq; - status = "disabled"; -}; - -&sdio_ext { - mmc-pwrseq = <&sdio_pwrseq>; - status = "okay"; -}; - -&sdmmc_ext { - status = "disabled"; -}; - -&spdif { - pinctrl-0 = <&spdifm1_tx>; -}; - diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf3.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf3.dtso deleted file mode 100644 index 28fcedf..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf3.dtso +++ /dev/null @@ -1,305 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include -#include - -&{/regulators/regulator@0} { - status = "disabled"; -}; - -&{/regulators/regulator@1} { - status = "disabled"; -}; - -&{/vdd-arm} { - status = "disabled"; -}; - -&{/vdd-log} { - status = "disabled"; -}; - -&{/xin32k} { - status = "disabled"; -}; - -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - - clock-frequency = <1000000>; - i2c-scl-rising-time-ns = <83>; - i2c-scl-falling-time-ns = <5>; - status = "okay"; - - rk805: rk805@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - status = "okay"; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&gpio2>; - interrupts = ; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - - system-power-controller; - wakeup-source; - - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&rk805_vcc_io>; - vcc6-supply = <&rk805_vcc_io>; - - rtc { - status = "okay"; - }; - - pwrkey { - status = "okay"; - }; - - gpio { - status = "okay"; - }; - - regulators { - compatible = "rk805-regulator"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: rk805_vcc_io: DCDC_REG4 { - regulator-name = "vccio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_18: vcc_18: LDO_REG1 { - regulator-name = "vccio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_18emmc: LDO_REG2 { - regulator-name = "vcc_18emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_11: LDO_REG3 { - regulator-name = "vdd_11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1100000>; - }; - }; - }; - }; - -}; - -&pinctrl { - - leds { - ir_led: ir-led { - rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - -}; - -&gpio_led { - - pinctrl-names = "default"; - pinctrl-0 = <&ir_led>; - - working { - gpios = <&rk805 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc2"; - default-state = "off"; - mode = <35>; - }; - - /* - * These leds are described in the original dtb, but are not present on the board - auxiliary { - gpios = <&rk805 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc2"; - default-state = "off"; - mode = <5>; - }; - - ir { - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ir"; - default-state = "off"; - mode = <0>; - }; - */ - -}; - -&io_domains { - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc_18emmc>; - vccio3-supply = <&vcc_io>; - vccio4-supply = <&vdd_18>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; -}; - -&{/} { - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power button"; - linux,code = ; - gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&dmc { - center-supply = <&vdd_logic>; -}; - -&gpu { - mali-supply = <&vdd_logic>; -}; - -&vpu { - vcodec-supply = <&vdd_logic>; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - - -&vcc_sd { - vin-supply = <&vcc_io>; -}; - -&emmc { - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_18emmc>; -}; - -&saradc { - vref-supply = <&vcc_18>; -}; - -&pwm0 { - status = "disabled"; -}; - -&pwm1 { - status = "disabled"; -}; - -/* - * Following section enables the sdio bus on sdmmc_ext controller - */ -&sdio { - /delete-property/ mmc-pwrseq; - status = "disabled"; -}; - -&sdio_ext { - rockchip,default-sample-phase = <112>; // Allows ssv6051 chips to be detected at 50 MHz - sd-uhs-sdr50; - mmc-pwrseq = <&sdio_pwrseq>; - status = "okay"; -}; - -&sdmmc_ext { - status = "disabled"; -}; - -&spdif { - pinctrl-0 = <&spdifm1_tx>; -}; - diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf4.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf4.dtso deleted file mode 100644 index 5d60f51..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf4.dtso +++ /dev/null @@ -1,38 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include - -/** - * Generic rk3318 board with sdio bus on sdmmc_ext connector - */ - -&gpio_led { - - working { - gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - }; - -}; - -/* - * Following section enables the sdio bus on sdmmc_ext controller - */ -&sdio { - /delete-property/ mmc-pwrseq; - status = "disabled"; -}; - -&sdio_ext { - rockchip,default-sample-phase = <112>; - sd-uhs-sdr50; - mmc-pwrseq = <&sdio_pwrseq>; - status = "okay"; -}; - -&sdmmc_ext { - status = "disabled"; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf5.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf5.dtso deleted file mode 100644 index 3c305fe..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-led-conf5.dtso +++ /dev/null @@ -1,104 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include -#include - -/** - * YX_RK3318 (circular) board - */ - -&gpio_led { - - working { - gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - -}; - -&{/} { - - i2c_aux_display: i2c-aux-display { - - compatible = "i2c-gpio"; - sda-gpios = <&gpio2 RK_PC5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio2 RK_PC6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - i2c-gpio,sda-output-only; - i2c-gpio,scl-output-only; - #address-cells = <1>; - #size-cells = <0>; - - aux-display-controller@24 { - compatible = "fdhisi,fd6551"; - reg = <0x24>; - - tm16xx,digits = [04 03 02 01]; - tm16xx,segment-mapping = [00 01 02 03 04 05 06]; - - #address-cells = <2>; - #size-cells = <0>; - - led@0,0 { - reg = <0 0>; - function = LED_FUNCTION_ALARM; - }; - - led@0,1 { - reg = <0 1>; - function = "usb"; - linux,default-trigger = "usb-host"; - }; - - led@0,2 { - reg = <0 2>; - function = "pause"; - linux,default-trigger = "mmc2"; - }; - - led@0,3 { - reg = <0 3>; - function = "play"; - linux,default-trigger = "mmc0"; - }; - - led@0,4 { - reg = <0 4>; - function = "colon"; - }; - - led@0,5 { - reg = <0 5>; - function = LED_FUNCTION_LAN; - linux,default-trigger = "stmmac-0:00:link"; - }; - - led@0,6 { - reg = <0 6>; - function = LED_FUNCTION_WLAN; - linux,default-trigger = "mmc1"; - }; - - }; - }; - -}; - -/* - * TODO: needs to find the GPIO for this - * -&gpio_keys { - - reset { - gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - debounce-interval = <200>; - wakeup-source; - }; - -}; -*/ diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-wlan-ap6330.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-wlan-ap6330.dtso deleted file mode 100644 index 9bc02a2..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-wlan-ap6330.dtso +++ /dev/null @@ -1,106 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include - -/ { - - fragment@0 { - target = <&sdio>; - __overlay__ { - - #address-cells = <1>; - #size-cells = <0>; - - brcmf_sdio: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - //brcm,drive-strength = <2>; - interrupt-parent = <&gpio1>; - interrupt-names = "host_wake"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_host_wake>; - }; - - }; - }; - - fragment@1 { - target = <&sdio_ext>; - __overlay__ { - - #address-cells = <1>; - #size-cells = <0>; - - brcmf_ext: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - //brcm,drive-strength = <2>; - interrupt-parent = <&gpio3>; - interrupt-names = "host_wake"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_host_wake_ext>; - }; - - }; - }; - - fragment@2 { - target = <&uart0>; - __overlay__ { - - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - max-speed = <4000000>; - shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; - //host-wakeup-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - vbat-supply = <&vcc_io>; - vddio-supply = <&vcc_18>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_reg_on_h>, <&bt_host_wake_l>, <&bt_device_wake_l>; - /* - interrupt-names = "host-wakeup"; - interrupt-parent = <&gpio1>; - interrupts = ; - */ - brcm,bt-pcm-int-params = [01 02 00 01 01]; - }; - - - }; - - }; - - fragment@3 { - target = <&pinctrl>; - __overlay__ { - - bluetooth { - - - bt_reg_on_h: bt-enable { - rockchip,pins = <1 RK_PC5 0 &pcfg_pull_none>; - }; - - bt_device_wake_l: bt-device-wake { - rockchip,pins = <1 RK_PC7 0 &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake { - rockchip,pins = <1 RK_PD2 0 &pcfg_pull_none>; - }; - - }; - - }; - }; - -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-wlan-ap6334.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-wlan-ap6334.dtso deleted file mode 100644 index b7befaa..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-wlan-ap6334.dtso +++ /dev/null @@ -1,117 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include - -/ { - - fragment@0 { - target = <&sdio>; - __overlay__ { - - #address-cells = <1>; - #size-cells = <0>; - - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - //sd-uhs-ddr50; - - brcmf_sdio: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - //brcm,drive-strength = <4>; - interrupt-parent = <&gpio1>; - interrupt-names = "host_wake"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_host_wake>; - }; - - }; - }; - - fragment@1 { - target = <&sdio_ext>; - __overlay__ { - - #address-cells = <1>; - #size-cells = <0>; - - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - //sd-uhs-ddr50; - - brcmf_ext: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - //brcm,drive-strength = <8>; - interrupt-parent = <&gpio3>; - interrupt-names = "host_wake"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_host_wake_ext>; - }; - - }; - }; - - fragment@2 { - target = <&uart0>; - __overlay__ { - - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; - - bluetooth { - compatible = "brcm,bcm4334b0-bt", "brcm,bcm4330-bt"; - max-speed = <4000000>; - shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; - //host-wakeup-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - vbat-supply = <&vcc_io>; - vddio-supply = <&vcc_18>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_reg_on_h>, <&bt_host_wake_l>, <&bt_device_wake_l>; - /* - interrupt-names = "host-wakeup"; - interrupt-parent = <&gpio1>; - interrupts = ; - */ - brcm,bt-pcm-int-params = [01 02 00 01 01]; - }; - - }; - - }; - - fragment@3 { - target = <&pinctrl>; - __overlay__ { - - bluetooth { - - - bt_reg_on_h: bt-enable { - rockchip,pins = <1 RK_PC5 0 &pcfg_pull_down>; - }; - - bt_device_wake_l: bt-device-wake { - rockchip,pins = <1 RK_PC7 0 &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake { - rockchip,pins = <1 RK_PD2 0 &pcfg_pull_none>; - }; - - }; - - }; - }; - -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-wlan-ext.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-wlan-ext.dtso deleted file mode 100644 index bf8a289..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3318-box-wlan-ext.dtso +++ /dev/null @@ -1,33 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include - -/ { - - fragment@0 { - target = <&sdio>; - __overlay__ { - mmc-pwrseq = <>; - status = "disabled"; - }; - }; - - fragment@1 { - target = <&sdio_ext>; - __overlay__ { - mmc-pwrseq = <&sdio_pwrseq>; - status = "okay"; - }; - }; - - fragment@2 { - target = <&sdmmc_ext>; - __overlay__ { - status = "disabled"; - }; - }; - -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-i2c0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-i2c0.dtso deleted file mode 100644 index af2d61e..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-i2c0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; - -/ { - compatible = "rockchip,rk3328"; - - fragment@0 { - target-path = "/i2c@ff150000"; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-i2s1-pcm5102.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-i2s1-pcm5102.dtso deleted file mode 100644 index 5153440..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-i2s1-pcm5102.dtso +++ /dev/null @@ -1,104 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include - -/* - * Device tree overlay to disabled internal analog codec for - * rk3328 boards and enable external i2s, binding it to a - * pcm5102-based DAC. - * Tested on rock-pi E, but should be suitable for other - * similar boards - */ - -&{/} { - - pcm5102: pcm510x { - #sound-dai-cells = <0>; - compatible = "ti,pcm5102a"; - pcm510x,format = "i2s"; - status = "okay"; - }; - - i2s_sound: i2s-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "I2S"; - status = "okay"; - - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&pcm5102>; - }; - }; - -}; - -&analog_sound { - status = "disabled"; -}; - -&codec { - status = "disabled"; -}; - -&i2s1_mclk { - rockchip,pins = <2 RK_PB7 1 &pcfg_pull_down>; -}; - -&i2s1_sclk { - rockchip,pins = <2 RK_PC2 1 &pcfg_pull_down>; -}; - -&i2s1_lrckrx { - rockchip,pins = <2 RK_PC0 1 &pcfg_pull_up>; -}; - -&i2s1_lrcktx { - rockchip,pins = <2 RK_PC1 1 &pcfg_pull_up>; -}; - -&i2s1_sdi { - rockchip,pins = <2 RK_PC3 1 &pcfg_pull_up>; -}; - -&i2s1_sdo { - rockchip,pins = <2 RK_PC7 1 &pcfg_pull_up>; -}; - -&i2s1_sdio1 { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up>; -}; - -&i2s1_sdio2 { - rockchip,pins = <2 RK_PC5 1 &pcfg_pull_up>; -}; - -&i2s1_sdio3 { - rockchip,pins = <2 RK_PC6 1 &pcfg_pull_up>; -}; - -&i2s1_sleep { - rockchip,pins = - <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; -}; - -&i2s1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_mclk>, <&i2s1_sclk>, <&i2s1_lrckrx>, <&i2s1_lrcktx>, <&i2s1_sdi>, <&i2s1_sdo>, <&i2s1_sdio1>, <&i2s1_sdio2>; - rockchip,playback-channels = <8>; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-mksklipad50-enable-rtc-end1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-mksklipad50-enable-rtc-end1.dtso deleted file mode 100644 index 16cf2f5..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-mksklipad50-enable-rtc-end1.dtso +++ /dev/null @@ -1,7 +0,0 @@ -/dts-v1/; -/plugin/; - -// enable end1 ethernet adapter -&gmac2phy { - status = "okay"; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-mksklipad50-enable-v4l2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-mksklipad50-enable-v4l2.dtso deleted file mode 100644 index 78221f5..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-mksklipad50-enable-v4l2.dtso +++ /dev/null @@ -1,18 +0,0 @@ -/dts-v1/; -/plugin/; - -// disable /dev/video1 + /dev/media0 -&vpu { - status = "okay"; -}; - -// disable /dev/video2 + /dev/media1 -&vdec { - status = "okay"; -}; - -// disable /dev/video0 -&rga { - status = "okay"; -}; - diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-mkspi-disable-lcd-spi.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-mkspi-disable-lcd-spi.dtso deleted file mode 100644 index c5c135c..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-mkspi-disable-lcd-spi.dtso +++ /dev/null @@ -1,30 +0,0 @@ -/dts-v1/; - -/ { - compatible = "rockchip,rk3328"; - - fragment@0 { - target-path = "/spi@ff190000"; - - __overlay__ { - spi_for_lcd@0 { - status = "disabled"; - }; - spi_for_touch@1 { - status = "disabled"; - }; - }; - }; - - fragment@1 { - target = <0xffffffff>; - - __overlay__ { - status = "okay"; - }; - }; - - __fixups__ { - uart1 = "/fragment@1:target:0"; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-opp-1.4ghz.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-opp-1.4ghz.dtso deleted file mode 100644 index 5cc0540..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-opp-1.4ghz.dtso +++ /dev/null @@ -1,15 +0,0 @@ -/dts-v1/; - -/ { - compatible = "rockchip,rk3328"; - fragment@0 { - target-path = "/opp-table-0"; - __overlay__ { - opp-1392000000 { - opp-hz = /bits/ 64 <1392000000>; - opp-microvolt = <1400000>; - clock-latency-ns = <40000>; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-opp-1.5ghz.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-opp-1.5ghz.dtso deleted file mode 100644 index 497de74..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-opp-1.5ghz.dtso +++ /dev/null @@ -1,15 +0,0 @@ -/dts-v1/; - -/ { - compatible = "rockchip,rk3328"; - fragment@0 { - target-path = "/opp-table-0"; - __overlay__ { - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <1450000>; - clock-latency-ns = <40000>; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-spi-spidev.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-spi-spidev.dtso deleted file mode 100644 index 9cc0238..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-spi-spidev.dtso +++ /dev/null @@ -1,33 +0,0 @@ -/dts-v1/; - -/ { - compatible = "rockchip,rk3328"; - - fragment@0 { - target-path = "/aliases"; - - __overlay__ { - status = "okay"; - spi0 = "/spi@ff190000"; - }; - }; - - fragment@1 { - target = <0xffffffff>; - - __overlay__ { - status = "okay"; - - spidev { - compatible = "armbian,spi-dev"; - status = "okay"; - reg = <0x00>; - spi-max-frequency = <0x989680>; - }; - }; - }; - - __fixups__ { - spi0 = "/fragment@1:target:0"; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-uart1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-uart1.dtso deleted file mode 100644 index 9ff6a00..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3328-uart1.dtso +++ /dev/null @@ -1,17 +0,0 @@ -/dts-v1/; - -/ { - compatible = "rockchip,rk3328"; - - fragment@1 { - target = <0xffffffff>; - - __overlay__ { - status = "okay"; - }; - }; - - __fixups__ { - uart1 = "/fragment@1:target:0"; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-dwc3-0-host.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-dwc3-0-host.dtso deleted file mode 100644 index be2f4a2..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-dwc3-0-host.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - compatible = "rockchip,rk3399"; - - fragment@0 { - target = <&usbdrd_dwc3_0>; - __overlay__ { - dr_mode = "host"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-i2c7.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-i2c7.dtso deleted file mode 100644 index f8c6015..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-i2c7.dtso +++ /dev/null @@ -1,11 +0,0 @@ -/dts-v1/; - -/ { - compatible = "rockchip,rk3399"; - fragment@0 { - target-path = "/i2c@ff160000"; - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-i2c8.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-i2c8.dtso deleted file mode 100644 index 54bc844..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-i2c8.dtso +++ /dev/null @@ -1,11 +0,0 @@ -/dts-v1/; - -/ { - compatible = "rockchip,rk3399"; - fragment@0 { - target-path = "/i2c@ff3e0000"; - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-opp-2ghz.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-opp-2ghz.dtso deleted file mode 100644 index 5123c84..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-opp-2ghz.dtso +++ /dev/null @@ -1,24 +0,0 @@ -/dts-v1/; - -/ { - compatible = "rockchip,rk3399"; - fragment@0 { - target-path = "/opp-table-0"; - __overlay__ { - opp06 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <1200000>; - }; - }; - }; - - fragment@1 { - target-path = "/opp-table-1"; - __overlay__ { - opp08 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <1300000>; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-pcie-gen2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-pcie-gen2.dtso deleted file mode 100644 index e8a51dc..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-pcie-gen2.dtso +++ /dev/null @@ -1,12 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - compatible = "rockchip,rk3399"; - fragment@0 { - target = <&pcie0>; - __overlay__ { - max-link-speed = <2>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-spi-jedec-nor.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-spi-jedec-nor.dtso deleted file mode 100644 index c4b1f36..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-spi-jedec-nor.dtso +++ /dev/null @@ -1,72 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - compatible = "rockchip,rk3399"; - - fragment@0 { - target-path = "/aliases"; - __overlay__ { - spi0 = "/spi@ff1c0000"; - spi1 = "/spi@ff1d0000"; - spi2 = "/spi@ff1e0000"; - spi3 = "/spi@ff1f0000"; - }; - }; - - fragment@1 { - target = <&spi0>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - spiflash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - status = "disabled"; - }; - }; - }; - - fragment@2 { - target = <&spi1>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - spiflash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - status = "disabled"; - }; - }; - }; - - fragment@3 { - target = <&spi2>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - spiflash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - status = "disabled"; - }; - }; - }; - - fragment@4 { - target = <&spi3>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - spiflash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-spi-spidev.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-spi-spidev.dtso deleted file mode 100644 index 53f0740..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-spi-spidev.dtso +++ /dev/null @@ -1,72 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - compatible = "rockchip,rk3399"; - - fragment@0 { - target-path = "/aliases"; - __overlay__ { - spi0 = "/spi@ff1c0000"; - spi1 = "/spi@ff1d0000"; - spi2 = "/spi@ff1e0000"; - spi3 = "/spi@ff1f0000"; - }; - }; - - fragment@1 { - target = <&spi0>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - spidev { - compatible = "armbian,spi-dev"; - status = "disabled"; - reg = <0>; - spi-max-frequency = <10000000>; - }; - }; - }; - - fragment@2 { - target = <&spi1>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - spidev { - compatible = "armbian,spi-dev"; - status = "disabled"; - reg = <0>; - spi-max-frequency = <10000000>; - }; - }; - }; - - fragment@3 { - target = <&spi2>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - spidev { - compatible = "armbian,spi-dev"; - status = "disabled"; - reg = <0>; - spi-max-frequency = <10000000>; - }; - }; - }; - - fragment@4 { - target = <&spi3>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - spidev { - compatible = "armbian,spi-dev"; - status = "disabled"; - reg = <0>; - spi-max-frequency = <10000000>; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-uart4.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-uart4.dtso deleted file mode 100644 index 305304e..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-uart4.dtso +++ /dev/null @@ -1,20 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - compatible = "rockchip,rk3399"; - - fragment@0 { - target = <&spi1>; - __overlay__ { - status = "disabled"; - }; - }; - - fragment@1 { - target = <&uart4>; - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-w1-gpio.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-w1-gpio.dtso deleted file mode 100644 index bfbc16a..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3399-w1-gpio.dtso +++ /dev/null @@ -1,20 +0,0 @@ -// Definitions for w1-gpio module (without external pullup) -/dts-v1/; -/plugin/; - -/ { - compatible = "rockchip,rk3399"; - - fragment@0 { - target-path = "/"; - __overlay__ { - - w1: onewire@0 { - compatible = "w1-gpio"; - pinctrl-names = "default"; - gpios = <&gpio1 4 0 0xae>; // GPIO1_A4 - status = "okay"; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3566-sata2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3566-sata2.dtso deleted file mode 100644 index 0505079..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3566-sata2.dtso +++ /dev/null @@ -1,20 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pcie2x1>; - - __overlay__ { - status = "disabled"; - }; - }; - - fragment@1 { - target = <&sata2>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-i2c0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-i2c0.dtso deleted file mode 100644 index a6942df..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-i2c0.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - // i2c3 aliased with i2c0. - // This activates i2c3 but it will be named as i2c0 on the userspace. - target = <&i2c3>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-i2c1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-i2c1.dtso deleted file mode 100644 index 344161c..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-i2c1.dtso +++ /dev/null @@ -1,12 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&i2c1>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-pwm1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-pwm1.dtso deleted file mode 100644 index 0b78ad9..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-pwm1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - // pwmchip0, pwm@fdd70010 - target = <&pwm1>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-pwm2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-pwm2.dtso deleted file mode 100644 index c7f1898..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-pwm2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - // pwmchip1, pwm@fdd70020 - target = <&pwm2>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-pwm9.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-pwm9.dtso deleted file mode 100644 index 7f52929..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-pwm9.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - // pwmchip3, pwm@fe6f0010 - target = <&pwm9>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-spi-spidev.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-spi-spidev.dtso deleted file mode 100644 index f25e855..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-spi-spidev.dtso +++ /dev/null @@ -1,22 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&spi0>; - - __overlay__ { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - spidev: spidev@0 { - status = "okay"; - compatible = "armbian,spi-dev"; - reg = <0>; - /* spi default max clock 100Mhz */ - spi-max-frequency = <100000000>; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso deleted file mode 100644 index fb85596..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - // uart1 aliased with serial0. - target = <&uart1>; - - __overlay__ { - status = "okay"; - pinctrl-names = "not_use_it", "default"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-uart0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-uart0.dtso deleted file mode 100644 index e57ba54..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-uart0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - // uart1 aliased with serial0. - target = <&uart1>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-uart1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-uart1.dtso deleted file mode 100644 index cdc75c4..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-hk-uart1.dtso +++ /dev/null @@ -1,15 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - // uart0 aliased with serial1. - target = <&uart0>; - - __overlay__ { - status = "okay"; - - dma-names = "tx", "rx"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso deleted file mode 100644 index b768f63..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso +++ /dev/null @@ -1,11 +0,0 @@ -/dts-v1/; -/plugin/; - - -&{/gpio-leds/led-lan} { - linux,default-trigger = "r8169-1-100:00:link"; -}; - -&{/gpio-leds/led-wan} { - linux,default-trigger = "r8169-2-100:00:link"; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso deleted file mode 100644 index 68bb358..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso +++ /dev/null @@ -1,15 +0,0 @@ -/dts-v1/; -/plugin/; - - -&{/gpio-leds/led-wan} { - linux,default-trigger = "stmmac-0:01:link"; -}; - -&{/gpio-leds/led-lan1} { - linux,default-trigger = "r8169-0-100:00:link"; -}; - -&{/gpio-leds/led-lan2} { - linux,default-trigger = "r8169-1-100:00:link"; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-rock-3a-disable-uart2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-rock-3a-disable-uart2.dtso deleted file mode 100644 index 5b7421e..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3568-rock-3a-disable-uart2.dtso +++ /dev/null @@ -1,12 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart2>; - - __overlay__ { - status = "disabled"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-fanctrl.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-fanctrl.dtso deleted file mode 100644 index 28110b0..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-fanctrl.dtso +++ /dev/null @@ -1,11 +0,0 @@ -/dts-v1/; -/plugin/; -/ { - fragment@0 { - target = <&fan>; - __overlay__ { - cooling-levels = <146 146 146 146 146 146 149 149 151>; - }; - }; -}; - diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-hdmirx.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-hdmirx.dtso deleted file mode 100644 index b61eff3..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-hdmirx.dtso +++ /dev/null @@ -1,20 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&hdmi_receiver_cma>; - - __overlay__ { - status = "okay"; - }; - }; - - fragment@1 { - target = <&hdmi_receiver>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-i2c8-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-i2c8-m2.dtso deleted file mode 100644 index 24993c8..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-i2c8-m2.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&i2c8>; - - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-nanopi-m6-spi-nor-flash.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-nanopi-m6-spi-nor-flash.dtso deleted file mode 100644 index 9972b4b..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-nanopi-m6-spi-nor-flash.dtso +++ /dev/null @@ -1,30 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&sdhci>; - - __overlay__ { - status = "disabled"; - }; - }; - - fragment@1 { - target = <&sfc>; - - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&fspim0_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm0-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm0-m0.dtso deleted file mode 100644 index 211ddc6..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm0-m0.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm0>; - - __overlay__ { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm0m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm0-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm0-m1.dtso deleted file mode 100644 index 353162e..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm0-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm0>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm0m1_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm0-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm0-m2.dtso deleted file mode 100644 index f7c03e9..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm0-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm0>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm0m2_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm1-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm1-m0.dtso deleted file mode 100644 index bb19090..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm1-m0.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm1>; - - __overlay__ { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm1m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm1-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm1-m1.dtso deleted file mode 100644 index e935135..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm1-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm1>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm1m1_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm1-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm1-m2.dtso deleted file mode 100644 index 155d0bd..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm1-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm1>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm1m2_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm10-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm10-m0.dtso deleted file mode 100644 index 281071b..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm10-m0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm10>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm10m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm11-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm11-m0.dtso deleted file mode 100644 index 1bebcd6..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm11-m0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm11>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm11m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm11-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm11-m1.dtso deleted file mode 100644 index b85076f..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm11-m1.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM11-M1"; - compatible = "radxa,rock-5a"; - category = "misc"; - exclusive = "GPIO4_B4"; - description = "Enable PWM11-M1.\nOn Radxa ROCK 5A this is pin 15."; - }; - - fragment@0 { - target = <&pwm11>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm11m1_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm12-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm12-m0.dtso deleted file mode 100644 index 6dc0c7e..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm12-m0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm12>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm12m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm13-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm13-m0.dtso deleted file mode 100644 index 38ec499..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm13-m0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm13>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm13m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm13-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm13-m2.dtso deleted file mode 100644 index 0d9b225..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm13-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm13>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm13m2_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm14-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm14-m0.dtso deleted file mode 100644 index 330406d..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm14-m0.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm14>; - - __overlay__ { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm14m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm14-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm14-m1.dtso deleted file mode 100644 index 82fec22..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm14-m1.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm14>; - - __overlay__ { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm14m1_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm14-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm14-m2.dtso deleted file mode 100644 index 7a26f2d..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm14-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm14>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm14m2_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m0.dtso deleted file mode 100644 index 076bef9..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m0.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM15-M0"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO3_C3"; - description = "Enable PWM15-M0.\nOn Radxa ROCK 5B this is pin 7."; - }; - - fragment@0 { - target = <&pwm15>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm15m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m1.dtso deleted file mode 100644 index 7d3de70..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm15>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm15m1_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m2.dtso deleted file mode 100644 index c1b2aea..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm15>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm15m2_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m3.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m3.dtso deleted file mode 100644 index 79e421a..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm15-m3.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM15-M3"; - compatible = "radxa,rock-5a", "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO1_D7"; - description = "Enable PWM15-M3.\nOn Radxa ROCK 5A this is pin 3.\nOn Radxa ROCK 5B this is pin 29."; - }; - - fragment@0 { - target = <&pwm15>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm15m3_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm2-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm2-m1.dtso deleted file mode 100644 index 653583f..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm2-m1.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM2-M1"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO3_B1"; - description = "Enable PWM2-M1.\nOn Radxa ROCK 5B this is pin 36."; - }; - - fragment@0 { - target = <&pwm2>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm2m1_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m0.dtso deleted file mode 100644 index a6a9181..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm3>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm3m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m1.dtso deleted file mode 100644 index 23ff1ad..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m1.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM3-M1"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO3_B2"; - description = "Enable PWM3-M1.\nOn Radxa ROCK 5B this is pin 38."; - }; - - fragment@0 { - target = <&pwm3>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm3m1_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m2.dtso deleted file mode 100644 index b70d209..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm3>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm3m2_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m3.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m3.dtso deleted file mode 100644 index db544f2..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm3-m3.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm3>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm3m3_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm5-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm5-m2.dtso deleted file mode 100644 index ce26d29..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm5-m2.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM5-M2"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO4_C4"; - description = "Enable PWM5-M2.\nOn Radxa ROCK 5B this is pin 18."; - }; - - fragment@0 { - target = <&pwm5>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm5m2_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm6-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm6-m0.dtso deleted file mode 100644 index e4d0ce3..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm6-m0.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM6-M0"; - compatible = "radxa,rock-5a"; - category = "misc"; - exclusive = "GPIO0_C7"; - description = "Enable PWM6-M0.\nOn Radxa ROCK 5A this is pin 27."; - }; - - fragment@0 { - target = <&pwm6>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm6m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm6-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm6-m2.dtso deleted file mode 100644 index 5e66d1d..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm6-m2.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM6-M2"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO4_C5"; - description = "Enable PWM6-M2.\nOn Radxa ROCK 5B this is pin 28."; - }; - - fragment@0 { - target = <&pwm6>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm6m2_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm7-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm7-m0.dtso deleted file mode 100644 index 6516762..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm7-m0.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM7-M0"; - compatible = "radxa,rock-5a"; - category = "misc"; - exclusive = "GPIO0_D0"; - description = "Enable PWM7-M0.\nOn Radxa ROCK 5A this is pin 28."; - }; - - fragment@0 { - target = <&pwm7>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm7m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm7-m3.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm7-m3.dtso deleted file mode 100644 index 9a7d919..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm7-m3.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM7-M3"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO4_C6"; - description = "Enable PWM7-M3.\nOn Radxa ROCK 5B this is pin 27."; - }; - - fragment@0 { - target = <&pwm7>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm7m3_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm8-m0.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm8-m0.dtso deleted file mode 100644 index e461cff..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-pwm8-m0.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM8-M0"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO3_A7"; - description = "Enable PWM8-M0.\nOn Radxa ROCK 5B this is pin 33."; - }; - - fragment@0 { - target = <&pwm8>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm8m0_pins>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-rkvenc-overlay.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-rkvenc-overlay.dtso deleted file mode 100644 index 0b95d7f..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-rkvenc-overlay.dtso +++ /dev/null @@ -1,123 +0,0 @@ -/dts-v1/; -/plugin/; -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - - fragment@0 { - target-path = "/"; - __overlay__ { - mpp_srv: mpp-srv { - compatible = "rockchip,mpp-service"; - rockchip,taskqueue-count = <12>; - }; - }; - }; - - fragment@1 { - target-path = "/"; - __overlay__ { - rkvenc_ccu: rkvenc-ccu { - compatible = "rockchip,rkv-encoder-v2-ccu"; - }; - }; - }; - - fragment@2 { - target-path = "/"; - __overlay__ { - rkvenc0: rkvenc-core@fdbd0000 { - compatible = "rockchip,rkv-encoder-v2-core"; - reg = <0x0 0xfdbd0000 0x0 0x6000>; - interrupts = ; - interrupt-names = "irq_rkvenc0"; - clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>; - clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; - rockchip,normal-rates = <600000000>, <0>, <800000000>; - assigned-clocks = <&cru ACLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>; - assigned-clock-rates = <600000000>, <800000000>; - resets = <&cru SRST_A_RKVENC0>, <&cru SRST_H_RKVENC0>, <&cru SRST_RKVENC0_CORE>; - reset-names = "video_a", "video_h", "video_core"; - rockchip,skip-pmu-idle-request; - iommus = <&rkvenc0_mmu>; - rockchip,srv = <&mpp_srv>; - rockchip,ccu = <&rkvenc_ccu>; - rockchip,taskqueue-node = <7>; - rockchip,task-capacity = <8>; - power-domains = <&power RK3588_PD_VENC0>; - }; - }; - }; - - fragment@3 { - target-path = "/"; - __overlay__ { - rkvenc0_mmu: iommu@fdbdf000 { - compatible = "rockchip,rk3568-iommu"; - reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>; - interrupts = <0 99 4 0>, <0 100 4 0>; - interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1"; - clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>; - clock-names = "aclk", "iface"; - rockchip,disable-mmu-reset; - rockchip,enable-cmd-retry; - rockchip,shootdown-entire; - #iommu-cells = <0>; - power-domains = <&power RK3588_PD_VENC0>; - }; - }; - }; - - fragment@4 { - target-path = "/"; - __overlay__ { - rkvenc1: rkvenc-core@fdbe0000 { - compatible = "rockchip,rkv-encoder-v2-core"; - reg = <0x0 0xfdbe0000 0x0 0x6000>; - interrupts = <0 104 4 0>; - interrupt-names = "irq_rkvenc1"; - clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>; - clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; - rockchip,normal-rates = <600000000>, <0>, <800000000>; - assigned-clocks = <&cru ACLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>; - assigned-clock-rates = <600000000>, <800000000>; - resets = <&cru SRST_A_RKVENC1>, <&cru SRST_H_RKVENC1>, <&cru SRST_RKVENC1_CORE>; - reset-names = "video_a", "video_h", "video_core"; - rockchip,skip-pmu-idle-request; - iommus = <&rkvenc1_mmu>; - rockchip,srv = <&mpp_srv>; - rockchip,ccu = <&rkvenc_ccu>; - rockchip,taskqueue-node = <7>; - rockchip,task-capacity = <8>; - power-domains = <&power RK3588_PD_VENC1>; - }; - }; - }; - - fragment@5 { - target-path = "/"; - __overlay__ { - rkvenc1_mmu: iommu@fdbef000 { - compatible = "rockchip,rk3568-iommu"; - reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>; - interrupts = <0 102 4 0>, <0 103 4 0>; - interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1"; - clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>; - clock-names = "aclk", "iface"; - rockchip,disable-mmu-reset; - rockchip,enable-cmd-retry; - rockchip,shootdown-entire; - #iommu-cells = <0>; - power-domains = <&power RK3588_PD_VENC1>; - }; - }; - }; -}; - diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-sata1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-sata1.dtso deleted file mode 100644 index 2759ab9..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-sata1.dtso +++ /dev/null @@ -1,20 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pcie2x1l0>; - - __overlay__ { - status = "disabled"; - }; - }; - - fragment@1 { - target = <&sata1>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-sata2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-sata2.dtso deleted file mode 100644 index c68e11d..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-sata2.dtso +++ /dev/null @@ -1,20 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pcie2x1l1>; - - __overlay__ { - status = "disabled"; - }; - }; - - fragment@1 { - target = <&sata2>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart1-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart1-m1.dtso deleted file mode 100644 index 909f605..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart1-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart1>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart1m1_xfer>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart3-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart3-m1.dtso deleted file mode 100644 index cc5522c..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart3-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart3>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart3m1_xfer>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart4-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart4-m2.dtso deleted file mode 100644 index a371018..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart4-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart4>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart4m2_xfer>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart6-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart6-m1.dtso deleted file mode 100644 index 46cea59..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart6-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart6>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart6m1_xfer>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart7-m2.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart7-m2.dtso deleted file mode 100644 index 6a56f61..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart7-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart7>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart7m2_xfer>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart8-m1.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart8-m1.dtso deleted file mode 100644 index e1b3b3a..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rk3588-uart8-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart8>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart8m1_xfer>; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rockpi4cplus-usb-host.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rockpi4cplus-usb-host.dtso deleted file mode 100644 index 654ae88..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rockpi4cplus-usb-host.dtso +++ /dev/null @@ -1,16 +0,0 @@ -//For RockPI 4C+: Change the top USB3.0 port to host mode - -/dts-v1/; -/plugin/; - -/ { - compatible = "radxa,rockpi4c-plus", "radxa,rockpi4", "rockchip,rk3399"; - - fragment@0 { - target = <&usbdrd_dwc3_0>; - __overlay__ { - dr_mode = "host"; - }; - }; -}; - diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-rockpro64-lcd.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-rockpro64-lcd.dtso deleted file mode 100644 index c9ce8f8..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-rockpro64-lcd.dtso +++ /dev/null @@ -1,58 +0,0 @@ -//For RockPro64 7″ LCD TOUCH SCREEN PANEL - -/dts-v1/; -/plugin/; - -/ { - compatible = "rockchip,rk3399"; - - fragment@0 { - target=<&backlight>; - __overlay__ { - status = "okay"; - }; - }; - - fragment@1 { - target=<&touch>; - __overlay__ { - status = "okay"; - }; - }; - - fragment@2 { - target=<&mipi_dsi>; - __overlay__ { - status = "okay"; - }; - }; - - fragment@3 { - target=<&vopl>; - __overlay__ { - status = "okay"; - }; - }; - - fragment@4 { - target=<&vopl_mmu>; - __overlay__ { - status = "okay"; - }; - }; - - fragment@5 { - target=<&vopb>; - __overlay__ { - status = "okay"; - }; - }; - - fragment@6 { - target=<&vopb_mmu>; - __overlay__ { - status = "okay"; - }; - }; -}; - diff --git a/patch/kernel/rockchip64-6.14/overlay/rockchip-sakurapi-rk3308b-ws2812.dtso b/patch/kernel/rockchip64-6.14/overlay/rockchip-sakurapi-rk3308b-ws2812.dtso deleted file mode 100644 index fc94f4a..0000000 --- a/patch/kernel/rockchip64-6.14/overlay/rockchip-sakurapi-rk3308b-ws2812.dtso +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -/* - * For SakuraPi Rk3308B: Enable on-board ws2812 LEDs - * Need to load an external driver, see https://github.com/Sakura-Pi/ws2812-vleds - * - * (C) Copyright 2025 TheSnowfield - */ - -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&spi1>; - __overlay__ { - - status = "okay"; - - ws2812@0 { - compatible = "ws2812-vleds"; - reg = <0>; - - // tested spi clk 6750000hz on rk3308b - spi-max-frequency = <6750000>; - - leds { - - // user defined - ws_led3: vled3 { - label = "ws-led3"; - default-state = "off"; - color-value = "#69b3f2"; - }; - - // user defined - ws_led2: vled2 { - label = "ws-led2"; - default-state = "off"; - color-value = "#9376c8"; - }; - - // user defined - ws_led1: vled1 { - label = "ws-led1"; - default-state = "off"; - color-value = "#b66bc3"; - }; - - // mmc1(emmc) r/w state - ws_led0: vled0 { - label = "ws-led0"; - default-state = "on"; - linux,default-trigger = "mmc1"; - color-value = "#eb698f"; - }; - - }; - }; - }; - }; -}; diff --git a/patch/kernel/rockchip64-6.14/rk3308-0001-pinctrl-slew-mux.patch b/patch/kernel/rockchip64-6.14/rk3308-0001-pinctrl-slew-mux.patch deleted file mode 100644 index 0e530b8..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-0001-pinctrl-slew-mux.patch +++ /dev/null @@ -1,257 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: brentr -Date: Thu, 13 Oct 2022 18:34:43 +0200 -Subject: [ARCHEOLOGY] Rockpis wifi fixes (#4008) - -> X-Git-Archeology: > recovered message: > * RockPI-S board has no video I/O -> X-Git-Archeology: > recovered message: > * udev rule to fix MAC address of iface based on UUID -> X-Git-Archeology: > recovered message: > Deals with WiFi chip lacking any EEPROM to store its unique Ethernet MAC address -> X-Git-Archeology: > recovered message: > Generic mechanism -- could be utilized for other boards having similar issues -> X-Git-Archeology: > recovered message: > * Handy Device Tree overlays for the RockPI S -> X-Git-Archeology: > recovered message: > Use armbian-add-overlay to install these -> X-Git-Archeology: > recovered message: > Reduce CPU voltage for the RK3308 B-S -> X-Git-Archeology: > recovered message: > Option to overclock RK3308 B-S to 1.3Ghz -> X-Git-Archeology: > recovered message: > Increase SDIO clock rate from 1Mhz to 10Mhz -> X-Git-Archeology: > recovered message: > This increases WiFi throughput from 300K bytes/s to 2.4M bytes/s -> X-Git-Archeology: > recovered message: > * corrected comment -> X-Git-Archeology: > recovered message: > * No longer repeat standard opp's in this dts -> X-Git-Archeology: > recovered message: > Require that the standard bs dts already be installed -> X-Git-Archeology: > recovered message: > * User README for adding RockPI-S board variant specific dts overlays -> X-Git-Archeology: > recovered message: > * "enabled" --> "okay" -> X-Git-Archeology: > recovered message: > * added mention of sdnand.dts, fixed typo -> X-Git-Archeology: > recovered message: > * added p2p0 to interfaces whose MAC address should be "fixed" -> X-Git-Archeology: > recovered message: > * RK3308 CPU serial number in nvmem replaces UUID for derivation of fixed MAC addr -> X-Git-Archeology: > recovered message: > Restored use of install utility -> X-Git-Archeology: > recovered message: > * Use RK3308 specific CPU serial number -> X-Git-Archeology: > recovered message: > rather than rootfs UUID -> X-Git-Archeology: > recovered message: > * remove generic fixMACaddress -> X-Git-Archeology: > recovered message: > * Install fixMACaddr file-by-file via install utility -> X-Git-Archeology: > recovered message: > * Drive SDIO bus signals faster -> X-Git-Archeology: > recovered message: > setting RK3308_SOC_CON0_VCCIO3 reduces signal rise/fall times to WiFi SDIO chip -> X-Git-Archeology: > recovered message: > from 30ns to 5ns. -> X-Git-Archeology: > recovered message: > This odd fix forward ported from legacy kernel. -> X-Git-Archeology: > recovered message: > Allows Rock Pi-S WiFi to operate at full speed. -> X-Git-Archeology: > recovered message: > * Set RK3308 I/O voltage domains before SDIO initializes -> X-Git-Archeology: > recovered message: > This patch moves responibility form the io-domain to the pinctrl driver because -> X-Git-Archeology: > recovered message: > the io-domain driver is probed after the SDIO devices are discovered. -> X-Git-Archeology: > recovered message: > This was causing multiple SDIO I/O failures during boot. -> X-Git-Archeology: > recovered message: > A new pinctrl property is added: -> X-Git-Archeology: > recovered message: > io-1v8-domains -> X-Git-Archeology: > recovered message: > is a u32 interpreted as a bit mask where each set bit corresponds to -> X-Git-Archeology: > recovered message: > a 1.8V I/O domain (as opposed to the default of 3.3V for I/O) -> X-Git-Archeology: > recovered message: > The mask is writted to the RK3308_SOC_CON0 GRF register -> X-Git-Archeology: > recovered message: > (once) when the pinctrl driver starts -> X-Git-Archeology: > recovered message: > The default mask is 0x10 where only I/O domain 4 runs at 1.8V -> X-Git-Archeology: > recovered message: > This is necessary for the RockPI-S to run the SDIO clock at high (50Mhz) speed -> X-Git-Archeology: > recovered message: > * align whitespace -> X-Git-Archeology: > recovered message: > * factored rk3308bs overlays out up sdio speedup patch -> X-Git-Archeology: > recovered message: > * factored dts for RK3308 iodomains and pinctrl patches out of speedup patch -> X-Git-Archeology: > recovered message: > * remains of sdio speedup patch merely add iodomains support for rk3308 -> X-Git-Archeology: > recovered message: > * factored rockpis dts modification out from rk3308 io voltage domains -> X-Git-Archeology: > recovered message: > replaced rk3308 support from iodomains with -> X-Git-Archeology: > recovered message: > new io-voltage-domains property added to pinctrl -> X-Git-Archeology: > recovered message: > io-voltage-domains specific to rk3308 for now, others SOCs may be added later. -> X-Git-Archeology: > recovered message: > * add sequence numbering to names of rk3308 patches -> X-Git-Archeology: > recovered message: > * corrected tab alignment -> X-Git-Archeology: - Revision d3a3afe3850861ceaeb44f3631251c764a28cd43: https://github.com/armbian/build/commit/d3a3afe3850861ceaeb44f3631251c764a28cd43 -> X-Git-Archeology: Date: Thu, 13 Oct 2022 18:34:43 +0200 -> X-Git-Archeology: From: brentr -> X-Git-Archeology: Subject: Rockpis wifi fixes (#4008) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - drivers/pinctrl/pinconf-generic.c | 1 + - drivers/pinctrl/pinctrl-rockchip.c | 95 ++++++++++ - drivers/pinctrl/pinctrl-rockchip.h | 3 + - include/linux/pinctrl/pinconf-generic.h | 1 + - 4 files changed, 100 insertions(+) - -diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c -index 111111111111..222222222222 100644 ---- a/drivers/pinctrl/pinconf-generic.c -+++ b/drivers/pinctrl/pinconf-generic.c -@@ -54,6 +54,7 @@ static const struct pin_config_item conf_items[] = { - PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false), - PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), - PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true), -+ PCONFDUMP(PIN_CONFIG_MUX, "mux", NULL, true), - }; - - static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, -diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c -index 111111111111..222222222222 100644 ---- a/drivers/pinctrl/pinctrl-rockchip.c -+++ b/drivers/pinctrl/pinctrl-rockchip.c -@@ -2888,6 +2888,26 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, - return ret; - } - -+#define RK3308_SLEW_PINS_PER_REG 8 -+#define RK3308_SLEW_BANK_STRIDE 16 -+#define RK3308_SLEW_GRF_OFFSET 0x150 -+ -+static int rk3308_calc_slew_reg_and_bit(struct rockchip_pin_bank *bank, -+ int pin_num, struct regmap **regmap, -+ int *reg, u8 *bit) -+{ -+ struct rockchip_pinctrl *info = bank->drvdata; -+ -+ *regmap = info->regmap_base; -+ *reg = RK3308_SLEW_GRF_OFFSET; -+ -+ *reg += bank->bank_num * RK3308_SLEW_BANK_STRIDE; -+ *reg += ((pin_num / RK3308_SLEW_PINS_PER_REG) * 4); -+ *bit = pin_num % RK3308_SLEW_PINS_PER_REG; -+ -+ return 0; -+} -+ - #define RK3328_SCHMITT_BITS_PER_PIN 1 - #define RK3328_SCHMITT_PINS_PER_REG 16 - #define RK3328_SCHMITT_BANK_STRIDE 8 -@@ -3003,6 +3023,51 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, - return regmap_update_bits(regmap, reg, rmask, data); - } - -+static int rockchip_get_slew_rate(struct rockchip_pin_bank *bank, int pin_num) -+{ -+ struct rockchip_pinctrl *info = bank->drvdata; -+ struct rockchip_pin_ctrl *ctrl = info->ctrl; -+ struct regmap *regmap; -+ int reg, ret; -+ u8 bit; -+ u32 data; -+ -+ ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); -+ if (ret) -+ return ret; -+ -+ ret = regmap_read(regmap, reg, &data); -+ if (ret) -+ return ret; -+ -+ data >>= bit; -+ return data & 0x1; -+} -+ -+static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank, -+ int pin_num, int speed) -+{ -+ struct rockchip_pinctrl *info = bank->drvdata; -+ struct rockchip_pin_ctrl *ctrl = info->ctrl; -+ struct regmap *regmap; -+ int reg, ret; -+ u8 bit; -+ u32 data, rmask; -+ -+ dev_dbg(info->dev, "setting slew rate of GPIO%d-%d to %d\n", -+ bank->bank_num, pin_num, speed); -+ -+ ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); -+ if (ret) -+ return ret; -+ -+ /* enable the write to the equivalent lower bits */ -+ data = BIT(bit + 16) | (speed << bit); -+ rmask = BIT(bit + 16) | BIT(bit); -+ -+ return regmap_update_bits(regmap, reg, rmask, data); -+} -+ - /* - * Pinmux_ops handling - */ -@@ -3240,6 +3305,15 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - if (rc < 0) - return rc; - break; -+ case PIN_CONFIG_SLEW_RATE: -+ if (!info->ctrl->slew_rate_calc_reg) -+ return -ENOTSUPP; -+ -+ rc = rockchip_set_slew_rate(bank, -+ pin - bank->pin_base, arg); -+ if (rc < 0) -+ return rc; -+ break; - default: - return -ENOTSUPP; - break; -@@ -3314,6 +3388,26 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, - if (rc < 0) - return rc; - -+ arg = rc; -+ break; -+ case PIN_CONFIG_SLEW_RATE: -+ if (!info->ctrl->slew_rate_calc_reg) -+ return -ENOTSUPP; -+ -+ rc = rockchip_get_slew_rate(bank, pin - bank->pin_base); -+ if (rc < 0) -+ return rc; -+ -+ arg = rc; -+ break; -+ case PIN_CONFIG_MUX: -+ if (!info->ctrl->schmitt_calc_reg) -+ return -ENOTSUPP; -+ -+ rc = rockchip_get_mux(bank, pin - bank->pin_base); -+ if (rc < 0) -+ return rc; -+ - arg = rc; - break; - default: -@@ -4116,6 +4210,7 @@ static struct rockchip_pin_ctrl rk3308_pin_ctrl = { - .pull_calc_reg = rk3308_calc_pull_reg_and_bit, - .drv_calc_reg = rk3308_calc_drv_reg_and_bit, - .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, -+ .slew_rate_calc_reg = rk3308_calc_slew_reg_and_bit, - }; - - static struct rockchip_pin_bank rk3328_pin_banks[] = { -diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h -index 111111111111..222222222222 100644 ---- a/drivers/pinctrl/pinctrl-rockchip.h -+++ b/drivers/pinctrl/pinctrl-rockchip.h -@@ -409,6 +409,9 @@ struct rockchip_pin_ctrl { - int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, - int pin_num, struct regmap **regmap, - int *reg, u8 *bit); -+ int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, -+ int pin_num, struct regmap **regmap, -+ int *reg, u8 *bit); - }; - - struct rockchip_pin_config { -diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h -index 111111111111..222222222222 100644 ---- a/include/linux/pinctrl/pinconf-generic.h -+++ b/include/linux/pinctrl/pinconf-generic.h -@@ -145,6 +145,7 @@ enum pin_config_param { - PIN_CONFIG_SKEW_DELAY, - PIN_CONFIG_SLEEP_HARDWARE_STATE, - PIN_CONFIG_SLEW_RATE, -+ PIN_CONFIG_MUX, - PIN_CONFIG_END = 0x7F, - PIN_CONFIG_MAX = 0xFF, - }; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3308-0003-pinctrl-io-voltage-domains.patch b/patch/kernel/rockchip64-6.14/rk3308-0003-pinctrl-io-voltage-domains.patch deleted file mode 100644 index 463c927..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-0003-pinctrl-io-voltage-domains.patch +++ /dev/null @@ -1,197 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: brentr -Date: Thu, 13 Oct 2022 18:34:43 +0200 -Subject: [ARCHEOLOGY] Rockpis wifi fixes (#4008) - -> X-Git-Archeology: > recovered message: > * RockPI-S board has no video I/O -> X-Git-Archeology: > recovered message: > * udev rule to fix MAC address of iface based on UUID -> X-Git-Archeology: > recovered message: > Deals with WiFi chip lacking any EEPROM to store its unique Ethernet MAC address -> X-Git-Archeology: > recovered message: > Generic mechanism -- could be utilized for other boards having similar issues -> X-Git-Archeology: > recovered message: > * Handy Device Tree overlays for the RockPI S -> X-Git-Archeology: > recovered message: > Use armbian-add-overlay to install these -> X-Git-Archeology: > recovered message: > Reduce CPU voltage for the RK3308 B-S -> X-Git-Archeology: > recovered message: > Option to overclock RK3308 B-S to 1.3Ghz -> X-Git-Archeology: > recovered message: > Increase SDIO clock rate from 1Mhz to 10Mhz -> X-Git-Archeology: > recovered message: > This increases WiFi throughput from 300K bytes/s to 2.4M bytes/s -> X-Git-Archeology: > recovered message: > * corrected comment -> X-Git-Archeology: > recovered message: > * No longer repeat standard opp's in this dts -> X-Git-Archeology: > recovered message: > Require that the standard bs dts already be installed -> X-Git-Archeology: > recovered message: > * User README for adding RockPI-S board variant specific dts overlays -> X-Git-Archeology: > recovered message: > * "enabled" --> "okay" -> X-Git-Archeology: > recovered message: > * added mention of sdnand.dts, fixed typo -> X-Git-Archeology: > recovered message: > * added p2p0 to interfaces whose MAC address should be "fixed" -> X-Git-Archeology: > recovered message: > * RK3308 CPU serial number in nvmem replaces UUID for derivation of fixed MAC addr -> X-Git-Archeology: > recovered message: > Restored use of install utility -> X-Git-Archeology: > recovered message: > * Use RK3308 specific CPU serial number -> X-Git-Archeology: > recovered message: > rather than rootfs UUID -> X-Git-Archeology: > recovered message: > * remove generic fixMACaddress -> X-Git-Archeology: > recovered message: > * Install fixMACaddr file-by-file via install utility -> X-Git-Archeology: > recovered message: > * Drive SDIO bus signals faster -> X-Git-Archeology: > recovered message: > setting RK3308_SOC_CON0_VCCIO3 reduces signal rise/fall times to WiFi SDIO chip -> X-Git-Archeology: > recovered message: > from 30ns to 5ns. -> X-Git-Archeology: > recovered message: > This odd fix forward ported from legacy kernel. -> X-Git-Archeology: > recovered message: > Allows Rock Pi-S WiFi to operate at full speed. -> X-Git-Archeology: > recovered message: > * Set RK3308 I/O voltage domains before SDIO initializes -> X-Git-Archeology: > recovered message: > This patch moves responibility form the io-domain to the pinctrl driver because -> X-Git-Archeology: > recovered message: > the io-domain driver is probed after the SDIO devices are discovered. -> X-Git-Archeology: > recovered message: > This was causing multiple SDIO I/O failures during boot. -> X-Git-Archeology: > recovered message: > A new pinctrl property is added: -> X-Git-Archeology: > recovered message: > io-1v8-domains -> X-Git-Archeology: > recovered message: > is a u32 interpreted as a bit mask where each set bit corresponds to -> X-Git-Archeology: > recovered message: > a 1.8V I/O domain (as opposed to the default of 3.3V for I/O) -> X-Git-Archeology: > recovered message: > The mask is writted to the RK3308_SOC_CON0 GRF register -> X-Git-Archeology: > recovered message: > (once) when the pinctrl driver starts -> X-Git-Archeology: > recovered message: > The default mask is 0x10 where only I/O domain 4 runs at 1.8V -> X-Git-Archeology: > recovered message: > This is necessary for the RockPI-S to run the SDIO clock at high (50Mhz) speed -> X-Git-Archeology: > recovered message: > * align whitespace -> X-Git-Archeology: > recovered message: > * factored rk3308bs overlays out up sdio speedup patch -> X-Git-Archeology: > recovered message: > * factored dts for RK3308 iodomains and pinctrl patches out of speedup patch -> X-Git-Archeology: > recovered message: > * remains of sdio speedup patch merely add iodomains support for rk3308 -> X-Git-Archeology: > recovered message: > * factored rockpis dts modification out from rk3308 io voltage domains -> X-Git-Archeology: > recovered message: > replaced rk3308 support from iodomains with -> X-Git-Archeology: > recovered message: > new io-voltage-domains property added to pinctrl -> X-Git-Archeology: > recovered message: > io-voltage-domains specific to rk3308 for now, others SOCs may be added later. -> X-Git-Archeology: > recovered message: > * add sequence numbering to names of rk3308 patches -> X-Git-Archeology: > recovered message: > * corrected tab alignment -> X-Git-Archeology: - Revision d3a3afe3850861ceaeb44f3631251c764a28cd43: https://github.com/armbian/build/commit/d3a3afe3850861ceaeb44f3631251c764a28cd43 -> X-Git-Archeology: Date: Thu, 13 Oct 2022 18:34:43 +0200 -> X-Git-Archeology: From: brentr -> X-Git-Archeology: Subject: Rockpis wifi fixes (#4008) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - drivers/pinctrl/pinctrl-rockchip.c | 24 ++++++ - drivers/soc/rockchip/io-domain.c | 40 ---------- - 2 files changed, 24 insertions(+), 40 deletions(-) - -diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c -index 111111111111..222222222222 100644 ---- a/drivers/pinctrl/pinctrl-rockchip.c -+++ b/drivers/pinctrl/pinctrl-rockchip.c -@@ -40,6 +40,12 @@ - #include "pinconf.h" - #include "pinctrl-rockchip.h" - -+#define RK3308_SOC_CON0 0x300 -+#define RK3308_SOC_CON0_DOMAINS ((BIT(9)-1)-BIT(7)) -+#define RK3308_SOC_CON0_DEFAULT 0x10 //default if no io_1v8_domains specified -+//note that this is supposed to be the reset value, but something early -+//in boot sets SOC_CON0 to zero -+ - /* - * Generate a bitmask for setting a value (v) with a write mask bit in hiword - * register 31:16 area. -@@ -3873,6 +3879,24 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) - if (ret) - return ret; - -+ if (ctrl->type == RK3308) { -+ /* -+ * Update GRF_SOC_CON0 early to reflect board's (fixed) I/O domain voltages -+ * The io-1v8-domains property may be specified to override default value -+ */ -+ u32 ioVoltSelect = RK3308_SOC_CON0_DEFAULT; -+ device_property_read_u32(dev, "io-1v8-domains", &ioVoltSelect); -+ if (ioVoltSelect & ~RK3308_SOC_CON0_DOMAINS) { -+ dev_warn(dev, "ignored invalid io-1v8-domains\n"); -+ ioVoltSelect = RK3308_SOC_CON0_DEFAULT; -+ } -+ ret = regmap_write(info->regmap_base, RK3308_SOC_CON0, -+ ioVoltSelect | (RK3308_SOC_CON0_DOMAINS << 16)); -+ dev_info(dev, "1.8V I/O domains assigned 0x%03x\n", ioVoltSelect); -+ if (ret < 0) -+ dev_warn(dev, "Couldn't update 1.8V I/O domains\n"); -+ } -+ - platform_set_drvdata(pdev, info); - - ret = of_platform_populate(np, NULL, NULL, &pdev->dev); -diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c -index 111111111111..222222222222 100644 ---- a/drivers/soc/rockchip/io-domain.c -+++ b/drivers/soc/rockchip/io-domain.c -@@ -39,10 +39,6 @@ - #define RK3288_SOC_CON2_FLASH0 BIT(7) - #define RK3288_SOC_FLASH_SUPPLY_NUM 2 - --#define RK3308_SOC_CON0 0x300 --#define RK3308_SOC_CON0_VCCIO3 BIT(8) --#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3 -- - #define RK3328_SOC_CON4 0x410 - #define RK3328_SOC_CON4_VCCIO2 BIT(7) - #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1 -@@ -233,25 +229,6 @@ static void rk3288_iodomain_init(struct rockchip_iodomain *iod) - dev_warn(iod->dev, "couldn't update flash0 ctrl\n"); - } - --static void rk3308_iodomain_init(struct rockchip_iodomain *iod) --{ -- int ret; -- u32 val; -- -- /* if no vccio3 supply we should leave things alone */ -- if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg) -- return; -- -- /* -- * set vccio3 iodomain to also use this framework -- * instead of a special gpio. -- */ -- val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16); -- ret = regmap_write(iod->grf, RK3308_SOC_CON0, val); -- if (ret < 0) -- dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n"); --} -- - static void rk3328_iodomain_init(struct rockchip_iodomain *iod) - { - int ret; -@@ -399,19 +376,6 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3288 = { - .init = rk3288_iodomain_init, - }; - --static const struct rockchip_iodomain_soc_data soc_data_rk3308 = { -- .grf_offset = 0x300, -- .supply_names = { -- "vccio0", -- "vccio1", -- "vccio2", -- "vccio3", -- "vccio4", -- "vccio5", -- }, -- .init = rk3308_iodomain_init, --}; -- - static const struct rockchip_iodomain_soc_data soc_data_rk3328 = { - .grf_offset = 0x410, - .supply_names = { -@@ -564,10 +528,6 @@ static const struct of_device_id rockchip_iodomain_match[] = { - .compatible = "rockchip,rk3288-io-voltage-domain", - .data = &soc_data_rk3288 - }, -- { -- .compatible = "rockchip,rk3308-io-voltage-domain", -- .data = &soc_data_rk3308 -- }, - { - .compatible = "rockchip,rk3328-io-voltage-domain", - .data = &soc_data_rk3328 --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3308-acodec-vendor-driver.patch b/patch/kernel/rockchip64-6.14/rk3308-acodec-vendor-driver.patch deleted file mode 100644 index b532fa5..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-acodec-vendor-driver.patch +++ /dev/null @@ -1,7158 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Fri, 20 Dec 2024 11:48:31 +0100 -Subject: revert rk3308 analog codec to vendor code - ---- - arch/arm64/boot/dts/rockchip/rk3308.dtsi | 7 +- - sound/soc/codecs/rk3308_codec.c | 5681 ++++++++-- - sound/soc/codecs/rk3308_codec.h | 892 +- - sound/soc/codecs/rk3308_codec_provider.h | 28 + - 4 files changed, 5665 insertions(+), 943 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -@@ -836,11 +836,14 @@ codec: codec@ff560000 { - compatible = "rockchip,rk3308-codec"; - reg = <0x0 0xff560000 0x0 0x10000>; - rockchip,grf = <&grf>; -- clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ rockchip,detect-grf = <&detect_grf>; -+ clock-names = "mclk_tx", "mclk_rx", "acodec"; - clocks = <&cru SCLK_I2S2_8CH_TX_OUT>, - <&cru SCLK_I2S2_8CH_RX_OUT>, - <&cru PCLK_ACODEC>; -- reset-names = "codec"; -+ interrupts = <&gic 114 IRQ_TYPE_LEVEL_HIGH>, -+ <&gic 115 IRQ_TYPE_LEVEL_HIGH>; -+ reset-names = "acodec-reset"; - resets = <&cru SRST_ACODEC_P>; - #sound-dai-cells = <0>; - status = "disabled"; -diff --git a/sound/soc/codecs/rk3308_codec.c b/sound/soc/codecs/rk3308_codec.c -index 111111111111..222222222222 100644 ---- a/sound/soc/codecs/rk3308_codec.c -+++ b/sound/soc/codecs/rk3308_codec.c -@@ -1,9 +1,20 @@ --// SPDX-License-Identifier: GPL-2.0-only - /* -- * Rockchip RK3308 internal audio codec driver -+ * rk3308_codec.c -- RK3308 ALSA Soc Audio Driver - * - * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. -- * Copyright (c) 2024, Vivax-Metrotech Ltd -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ * - */ - - #include -@@ -14,961 +25,5151 @@ - #include - #include - #include -+#include - #include -+#include - #include -+#include - #include --#include -+// #include -+#include - #include -+#include -+#include -+#include - #include - #include -+#include - #include - #include - - #include "rk3308_codec.h" -+#include "rk3308_codec_provider.h" - -+#if defined(CONFIG_DEBUG_FS) -+#include -+#include -+#include -+#endif -+ -+#define CODEC_DRV_NAME "rk3308-acodec" -+ -+#define ADC_GRP_SKIP_MAGIC 0x1001 - #define ADC_LR_GROUP_MAX 4 -+#define ADC_STABLE_MS 200 -+#define DEBUG_POP_ALWAYS 0 -+#define HPDET_POLL_MS 2000 -+#define NOT_USED 255 -+#define LOOPBACK_HANDLE_MS 100 -+#define PA_DRV_MS 5 - -+#define GRF_SOC_CON1 0x304 - #define GRF_CHIP_ID 0x800 -+#define GRF_I2S2_8CH_SDI_SFT 0 -+#define GRF_I2S3_4CH_SDI_SFT 8 -+#define GRF_I2S1_2CH_SDI_SFT 12 -+ -+#define GRF_I2S2_8CH_SDI_R_MSK(i, v) ((v >> (i * 2 + GRF_I2S2_8CH_SDI_SFT)) & 0x3) -+#define GRF_I2S2_8CH_SDI_W_MSK(i) (0x3 << (i * 2 + GRF_I2S2_8CH_SDI_SFT + 16)) -+#define GRF_I2S2_8CH_SDI(i, v) (((v & 0x3) << (i * 2 + GRF_I2S2_8CH_SDI_SFT)) |\ -+ GRF_I2S2_8CH_SDI_W_MSK(i)) -+ -+#define GRF_I2S3_4CH_SDI_W_MSK(i) (0x3 << (i * 2 + GRF_I2S3_4CH_SDI_SFT + 16)) -+#define GRF_I2S3_4CH_SDI(i, v) (((v & 0x3) << (i * 2 + GRF_I2S3_4CH_SDI_SFT)) |\ -+ GRF_I2S3_4CH_SDI_W_MSK(i)) -+ -+#define GRF_I2S1_2CH_SDI_W_MSK (0x3 << (GRF_I2S1_2CH_SDI_SFT + 16)) -+#define GRF_I2S1_2CH_SDI(v) (((v & 0x3) << GRF_I2S1_2CH_SDI_SFT) |\ -+ GRF_I2S1_2CH_SDI_W_MSK) -+ -+#define DETECT_GRF_ACODEC_HPDET_COUNTER 0x0030 -+#define DETECT_GRF_ACODEC_HPDET_CON 0x0034 -+#define DETECT_GRF_ACODEC_HPDET_STATUS 0x0038 -+#define DETECT_GRF_ACODEC_HPDET_STATUS_CLR 0x003c -+ -+/* 200ms based on pclk is 100MHz */ -+#define DEFAULT_HPDET_COUNT 20000000 -+#define HPDET_NEG_IRQ_SFT 1 -+#define HPDET_POS_IRQ_SFT 0 -+#define HPDET_BOTH_NEG_POS ((1 << HPDET_NEG_IRQ_SFT) |\ -+ (1 << HPDET_POS_IRQ_SFT)) -+ -+#define ACODEC_VERSION_A 0xa -+#define ACODEC_VERSION_B 0xb -+ -+enum { -+ ACODEC_TO_I2S2_8CH = 0, -+ ACODEC_TO_I2S3_4CH, -+ ACODEC_TO_I2S1_2CH, -+}; -+ -+enum { -+ ADC_GRP0_MICIN = 0, -+ ADC_GRP0_LINEIN -+}; -+ -+enum { -+ ADC_TYPE_NORMAL = 0, -+ ADC_TYPE_LOOPBACK, -+ ADC_TYPE_DBG, -+ ADC_TYPE_ALL, -+}; -+ -+enum { -+ DAC_LINEOUT = 0, -+ DAC_HPOUT = 1, -+ DAC_LINEOUT_HPOUT = 11, -+}; - - enum { -- ACODEC_VERSION_A = 'A', -- ACODEC_VERSION_B, -- ACODEC_VERSION_C, -+ EXT_MICBIAS_NONE = 0, -+ EXT_MICBIAS_FUNC1, /* enable external micbias via GPIO */ -+ EXT_MICBIAS_FUNC2, /* enable external micbias via regulator */ -+}; -+ -+enum { -+ PATH_IDLE = 0, -+ PATH_BUSY, -+}; -+ -+enum { -+ PM_NORMAL = 0, -+ PM_LLP_DOWN, /* light low power down */ -+ PM_LLP_UP, -+ PM_DLP_DOWN, /* deep low power down */ -+ PM_DLP_UP, -+ PM_DLP_DOWN2, -+ PM_DLP_UP2, - }; - - struct rk3308_codec_priv { -- const struct device *dev; -+ const struct device *plat_dev; -+ struct device dev; -+ struct reset_control *reset; - struct regmap *regmap; - struct regmap *grf; -- struct reset_control *reset; -- struct clk *hclk; -+ struct regmap *detect_grf; -+ struct clk *pclk; - struct clk *mclk_rx; - struct clk *mclk_tx; -+ struct gpio_desc *micbias_en_gpio; -+ struct gpio_desc *hp_ctl_gpio; -+ struct gpio_desc *spk_ctl_gpio; -+ struct gpio_desc *pa_drv_gpio; - struct snd_soc_component *component; -- unsigned char codec_ver; --}; -+ struct snd_soc_jack *hpdet_jack; -+ struct regulator *vcc_micbias; -+ u32 codec_ver; -+ -+ /* -+ * To select ADCs for groups: -+ * -+ * grp 0 -- select ADC1 / ADC2 -+ * grp 1 -- select ADC3 / ADC4 -+ * grp 2 -- select ADC5 / ADC6 -+ * grp 3 -- select ADC7 / ADC8 -+ */ -+ u32 used_adc_grps; -+ /* The ADC group which is used for loop back */ -+ u32 loopback_grp; -+ u32 cur_dbg_grp; -+ u32 en_always_grps[ADC_LR_GROUP_MAX]; -+ u32 en_always_grps_num; -+ u32 skip_grps[ADC_LR_GROUP_MAX]; -+ u32 i2s_sdis[ADC_LR_GROUP_MAX]; -+ u32 to_i2s_grps; -+ u32 delay_loopback_handle_ms; -+ u32 delay_start_play_ms; -+ u32 delay_pa_drv_ms; -+ u32 micbias_num; -+ u32 micbias_volt; -+ int which_i2s; -+ int irq; -+ int adc_grp0_using_linein; -+ int adc_zerocross; -+ /* 0: line out, 1: hp out, 11: lineout and hpout */ -+ int dac_output; -+ int dac_path_state; -+ -+ int ext_micbias; -+ int pm_state; -+ -+ /* AGC L/R Off/on */ -+ unsigned int agc_l[ADC_LR_GROUP_MAX]; -+ unsigned int agc_r[ADC_LR_GROUP_MAX]; - --static struct clk_bulk_data rk3308_codec_clocks[] = { -- { .id = "hclk" }, -- { .id = "mclk_rx" }, -- { .id = "mclk_tx" }, -+ /* AGC L/R Approximate Sample Rate */ -+ unsigned int agc_asr_l[ADC_LR_GROUP_MAX]; -+ unsigned int agc_asr_r[ADC_LR_GROUP_MAX]; -+ -+ /* ADC MIC Mute/Work */ -+ unsigned int mic_mute_l[ADC_LR_GROUP_MAX]; -+ unsigned int mic_mute_r[ADC_LR_GROUP_MAX]; -+ -+ /* For the high pass filter */ -+ unsigned int hpf_cutoff[ADC_LR_GROUP_MAX]; -+ -+ /* Only hpout do fade-in and fade-out */ -+ unsigned int hpout_l_dgain; -+ unsigned int hpout_r_dgain; -+ -+ bool adc_grps_endisable[ADC_LR_GROUP_MAX]; -+ bool dac_endisable; -+ bool enable_all_adcs; -+ bool enable_micbias; -+ bool micbias1; -+ bool micbias2; -+ bool hp_jack_reversed; -+ bool hp_plugged; -+ bool loopback_dacs_enabled; -+ bool no_deep_low_power; -+ bool no_hp_det; -+ struct delayed_work hpdet_work; -+ struct delayed_work loopback_work; -+ -+#if defined(CONFIG_DEBUG_FS) -+ struct dentry *dbg_codec; -+#endif - }; - --static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_alc_gain_tlv, -1800, 150, 0); --static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpout_gain_tlv, -3900, 150, 0); --static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpmix_gain_tlv, -600, 600, 0); -+static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_gain_tlv, -+ -1800, 150, 2850); -+static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_max_gain_tlv, -+ -1350, 600, 2850); -+static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_min_gain_tlv, -+ -1800, 600, 2400); -+static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_alc_gain_tlv, -+ -1800, 150, 2850); -+static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_lineout_gain_tlv, -+ -600, 150, 0); -+static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpout_gain_tlv, -+ -3900, 150, 600); -+static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpmix_gain_tlv, -+ -600, 600, 0); -+ -+static const DECLARE_TLV_DB_RANGE(rk3308_codec_adc_mic_gain_tlv_a, -+ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), -+ 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0), -+); - --static const DECLARE_TLV_DB_RANGE(rk3308_codec_dac_lineout_gain_tlv, -- 0, 0, TLV_DB_SCALE_ITEM(-600, 0, 0), -- 1, 1, TLV_DB_SCALE_ITEM(-300, 0, 0), -- 2, 2, TLV_DB_SCALE_ITEM(-150, 0, 0), -- 3, 3, TLV_DB_SCALE_ITEM(0, 0, 0), -+static const DECLARE_TLV_DB_RANGE(rk3308_codec_adc_mic_gain_tlv_b, -+ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), -+ 1, 1, TLV_DB_SCALE_ITEM(660, 0, 0), -+ 2, 2, TLV_DB_SCALE_ITEM(1300, 0, 0), -+ 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0), - ); - --static const char * const rk3308_codec_hpf_cutoff_text[] = { -- "20 Hz", "245 Hz", "612 Hz" -+static bool handle_loopback(struct rk3308_codec_priv *rk3308); -+ -+static int check_micbias(int micbias); -+ -+static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308, -+ int micbias); -+static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308); -+ -+static int rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_mic_gain_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+static int rk3308_codec_main_micbias_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol); -+ -+static const char *offon_text[2] = { -+ [0] = "Off", -+ [1] = "On", -+}; -+ -+static const char *mute_text[2] = { -+ [0] = "Work", -+ [1] = "Mute", -+}; -+ -+/* ADC MICBIAS Volt */ -+#define MICBIAS_VOLT_NUM 8 -+ -+#define MICBIAS_VREFx0_5 0 -+#define MICBIAS_VREFx0_55 1 -+#define MICBIAS_VREFx0_6 2 -+#define MICBIAS_VREFx0_65 3 -+#define MICBIAS_VREFx0_7 4 -+#define MICBIAS_VREFx0_75 5 -+#define MICBIAS_VREFx0_8 6 -+#define MICBIAS_VREFx0_85 7 -+ -+static const char *micbias_volts_enum_array[MICBIAS_VOLT_NUM] = { -+ [MICBIAS_VREFx0_5] = "VREFx0_5", -+ [MICBIAS_VREFx0_55] = "VREFx0_55", -+ [MICBIAS_VREFx0_6] = "VREFx0_6", -+ [MICBIAS_VREFx0_65] = "VREFx0_65", -+ [MICBIAS_VREFx0_7] = "VREFx0_7", -+ [MICBIAS_VREFx0_75] = "VREFx0_75", -+ [MICBIAS_VREFx0_8] = "VREFx0_8", -+ [MICBIAS_VREFx0_85] = "VREFx0_85", -+}; -+ -+static const struct soc_enum rk3308_micbias_volts_enum_array[] = { -+ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(micbias_volts_enum_array), micbias_volts_enum_array), -+}; -+ -+/* ADC MICBIAS1 and MICBIAS2 Main Switch */ -+static const struct soc_enum rk3308_main_micbias_enum_array[] = { -+ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text), -+}; -+ -+static const struct soc_enum rk3308_hpf_enum_array[] = { -+ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text), -+ SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(offon_text), offon_text), -+ SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(offon_text), offon_text), -+ SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(offon_text), offon_text), -+}; -+ -+/* ALC AGC Switch */ -+static const struct soc_enum rk3308_agc_enum_array[] = { -+ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text), -+ SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(offon_text), offon_text), -+ SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(offon_text), offon_text), -+ SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(offon_text), offon_text), -+ SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(offon_text), offon_text), -+ SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(offon_text), offon_text), -+ SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(offon_text), offon_text), -+ SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(offon_text), offon_text), -+}; -+ -+/* ADC MIC Mute/Work Switch */ -+static const struct soc_enum rk3308_mic_mute_enum_array[] = { -+ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(mute_text), mute_text), -+ SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(mute_text), mute_text), -+ SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(mute_text), mute_text), -+ SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(mute_text), mute_text), -+ SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(mute_text), mute_text), -+ SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(mute_text), mute_text), -+ SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(mute_text), mute_text), -+ SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(mute_text), mute_text), -+}; -+ -+/* ALC AGC Approximate Sample Rate */ -+#define AGC_ASR_NUM 8 -+ -+#define AGC_ASR_96KHZ 0 -+#define AGC_ASR_48KHZ 1 -+#define AGC_ASR_44_1KHZ 2 -+#define AGC_ASR_32KHZ 3 -+#define AGC_ASR_24KHZ 4 -+#define AGC_ASR_16KHZ 5 -+#define AGC_ASR_12KHZ 6 -+#define AGC_ASR_8KHZ 7 -+ -+static const char *agc_asr_text[AGC_ASR_NUM] = { -+ [AGC_ASR_96KHZ] = "96KHz", -+ [AGC_ASR_48KHZ] = "48KHz", -+ [AGC_ASR_44_1KHZ] = "44.1KHz", -+ [AGC_ASR_32KHZ] = "32KHz", -+ [AGC_ASR_24KHZ] = "24KHz", -+ [AGC_ASR_16KHZ] = "16KHz", -+ [AGC_ASR_12KHZ] = "12KHz", -+ [AGC_ASR_8KHZ] = "8KHz", -+}; -+ -+static const struct soc_enum rk3308_agc_asr_enum_array[] = { -+ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text), -+ SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text), -+ SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text), -+ SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text), -+ SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text), -+ SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text), -+ SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text), -+ SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text), -+}; -+ -+static const struct snd_kcontrol_new mic_gains_a[] = { -+ /* ADC MIC */ -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Left Volume", -+ RK3308_ADC_ANA_CON01(0), -+ RK3308_ADC_CH1_MIC_GAIN_SFT, -+ RK3308_ADC_CH1_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_a), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Right Volume", -+ RK3308_ADC_ANA_CON01(0), -+ RK3308_ADC_CH2_MIC_GAIN_SFT, -+ RK3308_ADC_CH2_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_a), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Left Volume", -+ RK3308_ADC_ANA_CON01(1), -+ RK3308_ADC_CH1_MIC_GAIN_SFT, -+ RK3308_ADC_CH1_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_a), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Right Volume", -+ RK3308_ADC_ANA_CON01(1), -+ RK3308_ADC_CH2_MIC_GAIN_SFT, -+ RK3308_ADC_CH2_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_a), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Left Volume", -+ RK3308_ADC_ANA_CON01(2), -+ RK3308_ADC_CH1_MIC_GAIN_SFT, -+ RK3308_ADC_CH1_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_a), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Right Volume", -+ RK3308_ADC_ANA_CON01(2), -+ RK3308_ADC_CH2_MIC_GAIN_SFT, -+ RK3308_ADC_CH2_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_a), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Left Volume", -+ RK3308_ADC_ANA_CON01(3), -+ RK3308_ADC_CH1_MIC_GAIN_SFT, -+ RK3308_ADC_CH1_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_a), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Right Volume", -+ RK3308_ADC_ANA_CON01(3), -+ RK3308_ADC_CH2_MIC_GAIN_SFT, -+ RK3308_ADC_CH2_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_a), -+}; -+ -+static const struct snd_kcontrol_new mic_gains_b[] = { -+ /* ADC MIC */ -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Left Volume", -+ RK3308_ADC_ANA_CON01(0), -+ RK3308_ADC_CH1_MIC_GAIN_SFT, -+ RK3308_ADC_CH1_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_b), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Right Volume", -+ RK3308_ADC_ANA_CON01(0), -+ RK3308_ADC_CH2_MIC_GAIN_SFT, -+ RK3308_ADC_CH2_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_b), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Left Volume", -+ RK3308_ADC_ANA_CON01(1), -+ RK3308_ADC_CH1_MIC_GAIN_SFT, -+ RK3308_ADC_CH1_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_b), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Right Volume", -+ RK3308_ADC_ANA_CON01(1), -+ RK3308_ADC_CH2_MIC_GAIN_SFT, -+ RK3308_ADC_CH2_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_b), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Left Volume", -+ RK3308_ADC_ANA_CON01(2), -+ RK3308_ADC_CH1_MIC_GAIN_SFT, -+ RK3308_ADC_CH1_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_b), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Right Volume", -+ RK3308_ADC_ANA_CON01(2), -+ RK3308_ADC_CH2_MIC_GAIN_SFT, -+ RK3308_ADC_CH2_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_b), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Left Volume", -+ RK3308_ADC_ANA_CON01(3), -+ RK3308_ADC_CH1_MIC_GAIN_SFT, -+ RK3308_ADC_CH1_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_b), -+ SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Right Volume", -+ RK3308_ADC_ANA_CON01(3), -+ RK3308_ADC_CH2_MIC_GAIN_SFT, -+ RK3308_ADC_CH2_MIC_GAIN_MAX, -+ 0, -+ rk3308_codec_mic_gain_get, -+ rk3308_codec_mic_gain_put, -+ rk3308_codec_adc_mic_gain_tlv_b), - }; - --static SOC_ENUM_SINGLE_DECL(rk3308_codec_hpf_cutoff_enum12, RK3308_ADC_DIG_CON04(0), 0, -- rk3308_codec_hpf_cutoff_text); --static SOC_ENUM_SINGLE_DECL(rk3308_codec_hpf_cutoff_enum34, RK3308_ADC_DIG_CON04(1), 0, -- rk3308_codec_hpf_cutoff_text); --static SOC_ENUM_SINGLE_DECL(rk3308_codec_hpf_cutoff_enum56, RK3308_ADC_DIG_CON04(2), 0, -- rk3308_codec_hpf_cutoff_text); --static SOC_ENUM_SINGLE_DECL(rk3308_codec_hpf_cutoff_enum78, RK3308_ADC_DIG_CON04(3), 0, -- rk3308_codec_hpf_cutoff_text); -- --static const struct snd_kcontrol_new rk3308_codec_controls[] = { -- /* Despite the register names, these set the gain when AGC is OFF */ -- SOC_SINGLE_RANGE_TLV("MIC1 Capture Volume", -+static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = { -+ /* ALC AGC Group */ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Volume", -+ RK3308_ALC_L_DIG_CON03(0), -+ RK3308_AGC_PGA_GAIN_SFT, -+ RK3308_AGC_PGA_GAIN_MIN, -+ RK3308_AGC_PGA_GAIN_MAX, -+ 0, rk3308_codec_alc_agc_grp_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Volume", -+ RK3308_ALC_R_DIG_CON03(0), -+ RK3308_AGC_PGA_GAIN_SFT, -+ RK3308_AGC_PGA_GAIN_MIN, -+ RK3308_AGC_PGA_GAIN_MAX, -+ 0, rk3308_codec_alc_agc_grp_gain_tlv), -+ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Volume", -+ RK3308_ALC_L_DIG_CON03(1), -+ RK3308_AGC_PGA_GAIN_SFT, -+ RK3308_AGC_PGA_GAIN_MIN, -+ RK3308_AGC_PGA_GAIN_MAX, -+ 0, rk3308_codec_alc_agc_grp_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Volume", -+ RK3308_ALC_R_DIG_CON03(1), -+ RK3308_AGC_PGA_GAIN_SFT, -+ RK3308_AGC_PGA_GAIN_MIN, -+ RK3308_AGC_PGA_GAIN_MAX, -+ 0, rk3308_codec_alc_agc_grp_gain_tlv), -+ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Volume", -+ RK3308_ALC_L_DIG_CON03(2), -+ RK3308_AGC_PGA_GAIN_SFT, -+ RK3308_AGC_PGA_GAIN_MIN, -+ RK3308_AGC_PGA_GAIN_MAX, -+ 0, rk3308_codec_alc_agc_grp_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Volume", -+ RK3308_ALC_R_DIG_CON03(2), -+ RK3308_AGC_PGA_GAIN_SFT, -+ RK3308_AGC_PGA_GAIN_MIN, -+ RK3308_AGC_PGA_GAIN_MAX, -+ 0, rk3308_codec_alc_agc_grp_gain_tlv), -+ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Volume", -+ RK3308_ALC_L_DIG_CON03(3), -+ RK3308_AGC_PGA_GAIN_SFT, -+ RK3308_AGC_PGA_GAIN_MIN, -+ RK3308_AGC_PGA_GAIN_MAX, -+ 0, rk3308_codec_alc_agc_grp_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Volume", -+ RK3308_ALC_R_DIG_CON03(3), -+ RK3308_AGC_PGA_GAIN_SFT, -+ RK3308_AGC_PGA_GAIN_MIN, -+ RK3308_AGC_PGA_GAIN_MAX, -+ 0, rk3308_codec_alc_agc_grp_gain_tlv), -+ -+ /* ALC AGC MAX */ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Max Volume", -+ RK3308_ALC_L_DIG_CON09(0), -+ RK3308_AGC_MAX_GAIN_PGA_SFT, -+ RK3308_AGC_MAX_GAIN_PGA_MIN, -+ RK3308_AGC_MAX_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Max Volume", -+ RK3308_ALC_R_DIG_CON09(0), -+ RK3308_AGC_MAX_GAIN_PGA_SFT, -+ RK3308_AGC_MAX_GAIN_PGA_MIN, -+ RK3308_AGC_MAX_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), -+ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Max Volume", -+ RK3308_ALC_L_DIG_CON09(1), -+ RK3308_AGC_MAX_GAIN_PGA_SFT, -+ RK3308_AGC_MAX_GAIN_PGA_MIN, -+ RK3308_AGC_MAX_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Max Volume", -+ RK3308_ALC_R_DIG_CON09(1), -+ RK3308_AGC_MAX_GAIN_PGA_SFT, -+ RK3308_AGC_MAX_GAIN_PGA_MIN, -+ RK3308_AGC_MAX_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), -+ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Max Volume", -+ RK3308_ALC_L_DIG_CON09(2), -+ RK3308_AGC_MAX_GAIN_PGA_SFT, -+ RK3308_AGC_MAX_GAIN_PGA_MIN, -+ RK3308_AGC_MAX_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Max Volume", -+ RK3308_ALC_R_DIG_CON09(2), -+ RK3308_AGC_MAX_GAIN_PGA_SFT, -+ RK3308_AGC_MAX_GAIN_PGA_MIN, -+ RK3308_AGC_MAX_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), -+ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Max Volume", -+ RK3308_ALC_L_DIG_CON09(3), -+ RK3308_AGC_MAX_GAIN_PGA_SFT, -+ RK3308_AGC_MAX_GAIN_PGA_MIN, -+ RK3308_AGC_MAX_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Max Volume", -+ RK3308_ALC_R_DIG_CON09(3), -+ RK3308_AGC_MAX_GAIN_PGA_SFT, -+ RK3308_AGC_MAX_GAIN_PGA_MIN, -+ RK3308_AGC_MAX_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), -+ -+ /* ALC AGC MIN */ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Min Volume", -+ RK3308_ALC_L_DIG_CON09(0), -+ RK3308_AGC_MIN_GAIN_PGA_SFT, -+ RK3308_AGC_MIN_GAIN_PGA_MIN, -+ RK3308_AGC_MIN_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Min Volume", -+ RK3308_ALC_R_DIG_CON09(0), -+ RK3308_AGC_MIN_GAIN_PGA_SFT, -+ RK3308_AGC_MIN_GAIN_PGA_MIN, -+ RK3308_AGC_MIN_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), -+ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Min Volume", -+ RK3308_ALC_L_DIG_CON09(1), -+ RK3308_AGC_MIN_GAIN_PGA_SFT, -+ RK3308_AGC_MIN_GAIN_PGA_MIN, -+ RK3308_AGC_MIN_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Min Volume", -+ RK3308_ALC_R_DIG_CON09(1), -+ RK3308_AGC_MIN_GAIN_PGA_SFT, -+ RK3308_AGC_MIN_GAIN_PGA_MIN, -+ RK3308_AGC_MIN_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), -+ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Min Volume", -+ RK3308_ALC_L_DIG_CON09(2), -+ RK3308_AGC_MIN_GAIN_PGA_SFT, -+ RK3308_AGC_MIN_GAIN_PGA_MIN, -+ RK3308_AGC_MIN_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Min Volume", -+ RK3308_ALC_R_DIG_CON09(2), -+ RK3308_AGC_MIN_GAIN_PGA_SFT, -+ RK3308_AGC_MIN_GAIN_PGA_MIN, -+ RK3308_AGC_MIN_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), -+ -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Min Volume", -+ RK3308_ALC_L_DIG_CON09(3), -+ RK3308_AGC_MIN_GAIN_PGA_SFT, -+ RK3308_AGC_MIN_GAIN_PGA_MIN, -+ RK3308_AGC_MIN_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Min Volume", -+ RK3308_ALC_R_DIG_CON09(3), -+ RK3308_AGC_MIN_GAIN_PGA_SFT, -+ RK3308_AGC_MIN_GAIN_PGA_MIN, -+ RK3308_AGC_MIN_GAIN_PGA_MAX, -+ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), -+ -+ /* ALC AGC Switch */ -+ SOC_ENUM_EXT("ALC AGC Group 0 Left Switch", rk3308_agc_enum_array[0], -+ rk3308_codec_agc_get, rk3308_codec_agc_put), -+ SOC_ENUM_EXT("ALC AGC Group 0 Right Switch", rk3308_agc_enum_array[1], -+ rk3308_codec_agc_get, rk3308_codec_agc_put), -+ SOC_ENUM_EXT("ALC AGC Group 1 Left Switch", rk3308_agc_enum_array[2], -+ rk3308_codec_agc_get, rk3308_codec_agc_put), -+ SOC_ENUM_EXT("ALC AGC Group 1 Right Switch", rk3308_agc_enum_array[3], -+ rk3308_codec_agc_get, rk3308_codec_agc_put), -+ SOC_ENUM_EXT("ALC AGC Group 2 Left Switch", rk3308_agc_enum_array[4], -+ rk3308_codec_agc_get, rk3308_codec_agc_put), -+ SOC_ENUM_EXT("ALC AGC Group 2 Right Switch", rk3308_agc_enum_array[5], -+ rk3308_codec_agc_get, rk3308_codec_agc_put), -+ SOC_ENUM_EXT("ALC AGC Group 3 Left Switch", rk3308_agc_enum_array[6], -+ rk3308_codec_agc_get, rk3308_codec_agc_put), -+ SOC_ENUM_EXT("ALC AGC Group 3 Right Switch", rk3308_agc_enum_array[7], -+ rk3308_codec_agc_get, rk3308_codec_agc_put), -+ -+ /* ALC AGC Approximate Sample Rate */ -+ SOC_ENUM_EXT("AGC Group 0 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[0], -+ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), -+ SOC_ENUM_EXT("AGC Group 0 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[1], -+ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), -+ SOC_ENUM_EXT("AGC Group 1 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[2], -+ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), -+ SOC_ENUM_EXT("AGC Group 1 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[3], -+ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), -+ SOC_ENUM_EXT("AGC Group 2 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[4], -+ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), -+ SOC_ENUM_EXT("AGC Group 2 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[5], -+ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), -+ SOC_ENUM_EXT("AGC Group 3 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[6], -+ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), -+ SOC_ENUM_EXT("AGC Group 3 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[7], -+ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), -+ -+ /* ADC MICBIAS Voltage */ -+ SOC_ENUM_EXT("ADC MICBIAS Voltage", rk3308_micbias_volts_enum_array[0], -+ rk3308_codec_micbias_volts_get, rk3308_codec_micbias_volts_put), -+ -+ /* ADC Main MICBIAS Switch */ -+ SOC_ENUM_EXT("ADC Main MICBIAS", rk3308_main_micbias_enum_array[0], -+ rk3308_codec_main_micbias_get, rk3308_codec_main_micbias_put), -+ -+ /* ADC MICBIAS1 and MICBIAS2 Switch */ -+ SOC_SINGLE("ADC MICBIAS1", RK3308_ADC_ANA_CON07(1), -+ RK3308_ADC_MIC_BIAS_BUF_SFT, 1, 0), -+ SOC_SINGLE("ADC MICBIAS2", RK3308_ADC_ANA_CON07(2), -+ RK3308_ADC_MIC_BIAS_BUF_SFT, 1, 0), -+ -+ /* ADC MIC Mute/Work Switch */ -+ SOC_ENUM_EXT("ADC MIC Group 0 Left Switch", rk3308_mic_mute_enum_array[0], -+ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), -+ SOC_ENUM_EXT("ADC MIC Group 0 Right Switch", rk3308_mic_mute_enum_array[1], -+ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), -+ SOC_ENUM_EXT("ADC MIC Group 1 Left Switch", rk3308_mic_mute_enum_array[2], -+ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), -+ SOC_ENUM_EXT("ADC MIC Group 1 Right Switch", rk3308_mic_mute_enum_array[3], -+ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), -+ SOC_ENUM_EXT("ADC MIC Group 2 Left Switch", rk3308_mic_mute_enum_array[4], -+ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), -+ SOC_ENUM_EXT("ADC MIC Group 2 Right Switch", rk3308_mic_mute_enum_array[5], -+ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), -+ SOC_ENUM_EXT("ADC MIC Group 3 Left Switch", rk3308_mic_mute_enum_array[6], -+ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), -+ SOC_ENUM_EXT("ADC MIC Group 3 Right Switch", rk3308_mic_mute_enum_array[7], -+ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), -+ -+ /* ADC ALC */ -+ SOC_SINGLE_RANGE_TLV("ADC ALC Group 0 Left Volume", - RK3308_ADC_ANA_CON03(0), - RK3308_ADC_CH1_ALC_GAIN_SFT, - RK3308_ADC_CH1_ALC_GAIN_MIN, - RK3308_ADC_CH1_ALC_GAIN_MAX, - 0, rk3308_codec_adc_alc_gain_tlv), -- SOC_SINGLE_RANGE_TLV("MIC2 Capture Volume", -+ SOC_SINGLE_RANGE_TLV("ADC ALC Group 0 Right Volume", - RK3308_ADC_ANA_CON04(0), - RK3308_ADC_CH2_ALC_GAIN_SFT, - RK3308_ADC_CH2_ALC_GAIN_MIN, - RK3308_ADC_CH2_ALC_GAIN_MAX, - 0, rk3308_codec_adc_alc_gain_tlv), -- SOC_SINGLE_RANGE_TLV("MIC3 Capture Volume", -+ SOC_SINGLE_RANGE_TLV("ADC ALC Group 1 Left Volume", - RK3308_ADC_ANA_CON03(1), - RK3308_ADC_CH1_ALC_GAIN_SFT, - RK3308_ADC_CH1_ALC_GAIN_MIN, - RK3308_ADC_CH1_ALC_GAIN_MAX, - 0, rk3308_codec_adc_alc_gain_tlv), -- SOC_SINGLE_RANGE_TLV("MIC4 Capture Volume", -+ SOC_SINGLE_RANGE_TLV("ADC ALC Group 1 Right Volume", - RK3308_ADC_ANA_CON04(1), - RK3308_ADC_CH2_ALC_GAIN_SFT, - RK3308_ADC_CH2_ALC_GAIN_MIN, - RK3308_ADC_CH2_ALC_GAIN_MAX, - 0, rk3308_codec_adc_alc_gain_tlv), -- SOC_SINGLE_RANGE_TLV("MIC5 Capture Volume", -+ SOC_SINGLE_RANGE_TLV("ADC ALC Group 2 Left Volume", - RK3308_ADC_ANA_CON03(2), - RK3308_ADC_CH1_ALC_GAIN_SFT, - RK3308_ADC_CH1_ALC_GAIN_MIN, - RK3308_ADC_CH1_ALC_GAIN_MAX, - 0, rk3308_codec_adc_alc_gain_tlv), -- SOC_SINGLE_RANGE_TLV("MIC6 Capture Volume", -+ SOC_SINGLE_RANGE_TLV("ADC ALC Group 2 Right Volume", - RK3308_ADC_ANA_CON04(2), - RK3308_ADC_CH2_ALC_GAIN_SFT, - RK3308_ADC_CH2_ALC_GAIN_MIN, - RK3308_ADC_CH2_ALC_GAIN_MAX, - 0, rk3308_codec_adc_alc_gain_tlv), -- SOC_SINGLE_RANGE_TLV("MIC7 Capture Volume", -+ SOC_SINGLE_RANGE_TLV("ADC ALC Group 3 Left Volume", - RK3308_ADC_ANA_CON03(3), - RK3308_ADC_CH1_ALC_GAIN_SFT, - RK3308_ADC_CH1_ALC_GAIN_MIN, - RK3308_ADC_CH1_ALC_GAIN_MAX, - 0, rk3308_codec_adc_alc_gain_tlv), -- SOC_SINGLE_RANGE_TLV("MIC8 Capture Volume", -+ SOC_SINGLE_RANGE_TLV("ADC ALC Group 3 Right Volume", - RK3308_ADC_ANA_CON04(3), - RK3308_ADC_CH2_ALC_GAIN_SFT, - RK3308_ADC_CH2_ALC_GAIN_MIN, - RK3308_ADC_CH2_ALC_GAIN_MAX, - 0, rk3308_codec_adc_alc_gain_tlv), - -- SOC_SINGLE("MIC1 Capture Switch", RK3308_ADC_ANA_CON00(0), 3, 1, 0), -- SOC_SINGLE("MIC2 Capture Switch", RK3308_ADC_ANA_CON00(0), 7, 1, 0), -- SOC_SINGLE("MIC3 Capture Switch", RK3308_ADC_ANA_CON00(1), 3, 1, 0), -- SOC_SINGLE("MIC4 Capture Switch", RK3308_ADC_ANA_CON00(1), 7, 1, 0), -- SOC_SINGLE("MIC5 Capture Switch", RK3308_ADC_ANA_CON00(2), 3, 1, 0), -- SOC_SINGLE("MIC6 Capture Switch", RK3308_ADC_ANA_CON00(2), 7, 1, 0), -- SOC_SINGLE("MIC7 Capture Switch", RK3308_ADC_ANA_CON00(3), 3, 1, 0), -- SOC_SINGLE("MIC8 Capture Switch", RK3308_ADC_ANA_CON00(3), 7, 1, 0), -- -- SOC_SINGLE("MIC12 HPF Capture Switch", RK3308_ADC_DIG_CON04(0), 2, 1, 1), -- SOC_SINGLE("MIC34 HPF Capture Switch", RK3308_ADC_DIG_CON04(1), 2, 1, 1), -- SOC_SINGLE("MIC56 HPF Capture Switch", RK3308_ADC_DIG_CON04(2), 2, 1, 1), -- SOC_SINGLE("MIC78 HPF Capture Switch", RK3308_ADC_DIG_CON04(3), 2, 1, 1), -- -- SOC_ENUM("MIC12 HPF Cutoff", rk3308_codec_hpf_cutoff_enum12), -- SOC_ENUM("MIC34 HPF Cutoff", rk3308_codec_hpf_cutoff_enum34), -- SOC_ENUM("MIC56 HPF Cutoff", rk3308_codec_hpf_cutoff_enum56), -- SOC_ENUM("MIC78 HPF Cutoff", rk3308_codec_hpf_cutoff_enum78), -- -- SOC_DOUBLE_TLV("Line Out Playback Volume", -+ /* ADC High Pass Filter */ -+ SOC_ENUM_EXT("ADC Group 0 HPF Cut-off", rk3308_hpf_enum_array[0], -+ rk3308_codec_hpf_get, rk3308_codec_hpf_put), -+ SOC_ENUM_EXT("ADC Group 1 HPF Cut-off", rk3308_hpf_enum_array[1], -+ rk3308_codec_hpf_get, rk3308_codec_hpf_put), -+ SOC_ENUM_EXT("ADC Group 2 HPF Cut-off", rk3308_hpf_enum_array[2], -+ rk3308_codec_hpf_get, rk3308_codec_hpf_put), -+ SOC_ENUM_EXT("ADC Group 3 HPF Cut-off", rk3308_hpf_enum_array[3], -+ rk3308_codec_hpf_get, rk3308_codec_hpf_put), -+ -+ /* DAC LINEOUT */ -+ SOC_SINGLE_TLV("DAC LINEOUT Left Volume", - RK3308_DAC_ANA_CON04, - RK3308_DAC_L_LINEOUT_GAIN_SFT, -+ RK3308_DAC_L_LINEOUT_GAIN_MAX, -+ 0, rk3308_codec_dac_lineout_gain_tlv), -+ SOC_SINGLE_TLV("DAC LINEOUT Right Volume", -+ RK3308_DAC_ANA_CON04, - RK3308_DAC_R_LINEOUT_GAIN_SFT, -- RK3308_DAC_x_LINEOUT_GAIN_MAX, -+ RK3308_DAC_R_LINEOUT_GAIN_MAX, - 0, rk3308_codec_dac_lineout_gain_tlv), -- SOC_DOUBLE("Line Out Playback Switch", -- RK3308_DAC_ANA_CON04, -- RK3308_DAC_L_LINEOUT_MUTE_SFT, -- RK3308_DAC_R_LINEOUT_MUTE_SFT, 1, 0), -- SOC_DOUBLE_R_TLV("Headphone Playback Volume", -- RK3308_DAC_ANA_CON05, -- RK3308_DAC_ANA_CON06, -- RK3308_DAC_x_HPOUT_GAIN_SFT, -- RK3308_DAC_x_HPOUT_GAIN_MAX, -- 0, rk3308_codec_dac_hpout_gain_tlv), -- SOC_DOUBLE("Headphone Playback Switch", -- RK3308_DAC_ANA_CON03, -- RK3308_DAC_L_HPOUT_MUTE_SFT, -- RK3308_DAC_R_HPOUT_MUTE_SFT, 1, 0), -- SOC_DOUBLE_RANGE_TLV("DAC HPMIX Playback Volume", -+ -+ /* DAC HPOUT */ -+ SOC_SINGLE_EXT_TLV("DAC HPOUT Left Volume", -+ RK3308_DAC_ANA_CON05, -+ RK3308_DAC_L_HPOUT_GAIN_SFT, -+ RK3308_DAC_L_HPOUT_GAIN_MAX, -+ 0, -+ rk3308_codec_hpout_l_get_tlv, -+ rk3308_codec_hpout_l_put_tlv, -+ rk3308_codec_dac_hpout_gain_tlv), -+ SOC_SINGLE_EXT_TLV("DAC HPOUT Right Volume", -+ RK3308_DAC_ANA_CON06, -+ RK3308_DAC_R_HPOUT_GAIN_SFT, -+ RK3308_DAC_R_HPOUT_GAIN_MAX, -+ 0, -+ rk3308_codec_hpout_r_get_tlv, -+ rk3308_codec_hpout_r_put_tlv, -+ rk3308_codec_dac_hpout_gain_tlv), -+ -+ /* DAC HPMIX */ -+ SOC_SINGLE_RANGE_TLV("DAC HPMIX Left Volume", - RK3308_DAC_ANA_CON12, - RK3308_DAC_L_HPMIX_GAIN_SFT, -+ RK3308_DAC_L_HPMIX_GAIN_MIN, -+ RK3308_DAC_L_HPMIX_GAIN_MAX, -+ 0, rk3308_codec_dac_hpmix_gain_tlv), -+ SOC_SINGLE_RANGE_TLV("DAC HPMIX Right Volume", -+ RK3308_DAC_ANA_CON12, - RK3308_DAC_R_HPMIX_GAIN_SFT, -- 1, 2, 0, rk3308_codec_dac_hpmix_gain_tlv), -+ RK3308_DAC_R_HPMIX_GAIN_MIN, -+ RK3308_DAC_R_HPMIX_GAIN_MAX, -+ 0, rk3308_codec_dac_hpmix_gain_tlv), - }; - --static int rk3308_codec_pop_sound_set(struct snd_soc_dapm_widget *w, -- struct snd_kcontrol *kcontrol, -- int event) -+static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) - { -- struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); - struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -- unsigned int val = (event == SND_SOC_DAPM_POST_PMU) ? -- RK3308_DAC_HPOUT_POP_SOUND_x_WORK : -- RK3308_DAC_HPOUT_POP_SOUND_x_INIT; -- unsigned int mask = RK3308_DAC_HPOUT_POP_SOUND_x_MSK; -+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; - -- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, -- mask << w->shift, val << w->shift); -- -- return 0; --} -- --static const struct snd_soc_dapm_widget rk3308_codec_dapm_widgets[] = { -- SND_SOC_DAPM_INPUT("MIC1"), -- SND_SOC_DAPM_INPUT("MIC2"), -- SND_SOC_DAPM_INPUT("MIC3"), -- SND_SOC_DAPM_INPUT("MIC4"), -- SND_SOC_DAPM_INPUT("MIC5"), -- SND_SOC_DAPM_INPUT("MIC6"), -- SND_SOC_DAPM_INPUT("MIC7"), -- SND_SOC_DAPM_INPUT("MIC8"), -- -- SND_SOC_DAPM_SUPPLY("ADC_CURRENT_EN12", RK3308_ADC_ANA_CON06(0), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC_CURRENT_EN34", RK3308_ADC_ANA_CON06(1), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC_CURRENT_EN56", RK3308_ADC_ANA_CON06(2), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC_CURRENT_EN78", RK3308_ADC_ANA_CON06(3), 0, 0, NULL, 0), -- -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC1_EN", RK3308_ADC_ANA_CON00(0), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC2_EN", RK3308_ADC_ANA_CON00(0), 5, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC3_EN", RK3308_ADC_ANA_CON00(1), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC4_EN", RK3308_ADC_ANA_CON00(1), 5, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC5_EN", RK3308_ADC_ANA_CON00(2), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC6_EN", RK3308_ADC_ANA_CON00(2), 5, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC7_EN", RK3308_ADC_ANA_CON00(3), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC8_EN", RK3308_ADC_ANA_CON00(3), 5, 1, 1, 0), -- -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC1_WORK", RK3308_ADC_ANA_CON00(0), 2, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC2_WORK", RK3308_ADC_ANA_CON00(0), 6, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC3_WORK", RK3308_ADC_ANA_CON00(1), 2, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC4_WORK", RK3308_ADC_ANA_CON00(1), 6, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC5_WORK", RK3308_ADC_ANA_CON00(2), 2, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC6_WORK", RK3308_ADC_ANA_CON00(2), 6, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC7_WORK", RK3308_ADC_ANA_CON00(3), 2, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_mic, "MIC8_WORK", RK3308_ADC_ANA_CON00(3), 6, 1, 1, 0), -- -- /* -- * In theory MIC1 and MIC2 can switch to LINE IN, but this is not -- * supported so all we can do is enabling the MIC input. -- */ -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "CH1_IN_SEL", RK3308_ADC_ANA_CON07(0), 4, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "CH2_IN_SEL", RK3308_ADC_ANA_CON07(0), 6, 1, 1, 0), -- -- SND_SOC_DAPM_SUPPLY("ADC1_BUF_REF_EN", RK3308_ADC_ANA_CON00(0), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC2_BUF_REF_EN", RK3308_ADC_ANA_CON00(0), 4, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC3_BUF_REF_EN", RK3308_ADC_ANA_CON00(1), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC4_BUF_REF_EN", RK3308_ADC_ANA_CON00(1), 4, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC5_BUF_REF_EN", RK3308_ADC_ANA_CON00(2), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC6_BUF_REF_EN", RK3308_ADC_ANA_CON00(2), 4, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC7_BUF_REF_EN", RK3308_ADC_ANA_CON00(3), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC8_BUF_REF_EN", RK3308_ADC_ANA_CON00(3), 4, 0, NULL, 0), -- -- SND_SOC_DAPM_SUPPLY("ADC_MCLK_GATE", RK3308_GLB_CON, 5, 1, NULL, 0), -- -- SND_SOC_DAPM_SUPPLY("ADC1_CLK_EN", RK3308_ADC_ANA_CON05(0), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC2_CLK_EN", RK3308_ADC_ANA_CON05(0), 4, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC3_CLK_EN", RK3308_ADC_ANA_CON05(1), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC4_CLK_EN", RK3308_ADC_ANA_CON05(1), 4, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC5_CLK_EN", RK3308_ADC_ANA_CON05(2), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC6_CLK_EN", RK3308_ADC_ANA_CON05(2), 4, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC7_CLK_EN", RK3308_ADC_ANA_CON05(3), 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("ADC8_CLK_EN", RK3308_ADC_ANA_CON05(3), 4, 0, NULL, 0), -- -- /* The "ALC" name from the TRM is misleading, these are needed even without ALC/AGC */ -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC1_EN", RK3308_ADC_ANA_CON02(0), 0, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC2_EN", RK3308_ADC_ANA_CON02(0), 4, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC3_EN", RK3308_ADC_ANA_CON02(1), 0, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC4_EN", RK3308_ADC_ANA_CON02(1), 4, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC5_EN", RK3308_ADC_ANA_CON02(2), 0, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC6_EN", RK3308_ADC_ANA_CON02(2), 4, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC7_EN", RK3308_ADC_ANA_CON02(3), 0, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC8_EN", RK3308_ADC_ANA_CON02(3), 4, 1, 1, 0), -- -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC1_EN", RK3308_ADC_ANA_CON05(0), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC2_EN", RK3308_ADC_ANA_CON05(0), 5, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC3_EN", RK3308_ADC_ANA_CON05(1), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC4_EN", RK3308_ADC_ANA_CON05(1), 5, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC5_EN", RK3308_ADC_ANA_CON05(2), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC6_EN", RK3308_ADC_ANA_CON05(2), 5, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC7_EN", RK3308_ADC_ANA_CON05(3), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC8_EN", RK3308_ADC_ANA_CON05(3), 5, 1, 1, 0), -- -- SND_SOC_DAPM_ADC("ADC1_WORK", "Capture", RK3308_ADC_ANA_CON05(0), 2, 0), -- SND_SOC_DAPM_ADC("ADC2_WORK", "Capture", RK3308_ADC_ANA_CON05(0), 6, 0), -- SND_SOC_DAPM_ADC("ADC3_WORK", "Capture", RK3308_ADC_ANA_CON05(1), 2, 0), -- SND_SOC_DAPM_ADC("ADC4_WORK", "Capture", RK3308_ADC_ANA_CON05(1), 6, 0), -- SND_SOC_DAPM_ADC("ADC5_WORK", "Capture", RK3308_ADC_ANA_CON05(2), 2, 0), -- SND_SOC_DAPM_ADC("ADC6_WORK", "Capture", RK3308_ADC_ANA_CON05(2), 6, 0), -- SND_SOC_DAPM_ADC("ADC7_WORK", "Capture", RK3308_ADC_ANA_CON05(3), 2, 0), -- SND_SOC_DAPM_ADC("ADC8_WORK", "Capture", RK3308_ADC_ANA_CON05(3), 6, 0), -- -- /* The "ALC" name from the TRM is misleading, these are needed even without ALC/AGC */ -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC1_WORK", RK3308_ADC_ANA_CON02(0), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC2_WORK", RK3308_ADC_ANA_CON02(0), 5, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC3_WORK", RK3308_ADC_ANA_CON02(1), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC4_WORK", RK3308_ADC_ANA_CON02(1), 5, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC5_WORK", RK3308_ADC_ANA_CON02(2), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC6_WORK", RK3308_ADC_ANA_CON02(2), 5, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC7_WORK", RK3308_ADC_ANA_CON02(3), 1, 1, 1, 0), -- SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ALC8_WORK", RK3308_ADC_ANA_CON02(3), 5, 1, 1, 0), -- -- SND_SOC_DAPM_SUPPLY("MICBIAS Current", RK3308_ADC_ANA_CON08(0), 4, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("MICBIAS1", RK3308_ADC_ANA_CON07(1), 3, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("MICBIAS2", RK3308_ADC_ANA_CON07(2), 3, 0, NULL, 0), -- -- SND_SOC_DAPM_OUT_DRV("DAC_L_HPMIX_EN", RK3308_DAC_ANA_CON13, 0, 0, NULL, 0), -- SND_SOC_DAPM_OUT_DRV("DAC_R_HPMIX_EN", RK3308_DAC_ANA_CON13, 4, 0, NULL, 0), -- SND_SOC_DAPM_OUT_DRV("DAC_L_HPMIX_WORK", RK3308_DAC_ANA_CON13, 1, 0, NULL, 0), -- SND_SOC_DAPM_OUT_DRV("DAC_R_HPMIX_WORK", RK3308_DAC_ANA_CON13, 5, 0, NULL, 0), -- /* HPMIX is not actually acting as a mixer as the only supported input is I2S */ -- SND_SOC_DAPM_OUT_DRV("DAC_L_HPMIX_SEL", RK3308_DAC_ANA_CON12, 2, 0, NULL, 0), -- SND_SOC_DAPM_OUT_DRV("DAC_R_HPMIX_SEL", RK3308_DAC_ANA_CON12, 6, 0, NULL, 0), -- SND_SOC_DAPM_MIXER("DAC HPMIX Left", RK3308_DAC_ANA_CON13, 2, 0, NULL, 0), -- SND_SOC_DAPM_MIXER("DAC HPMIX Right", RK3308_DAC_ANA_CON13, 6, 0, NULL, 0), -- -- SND_SOC_DAPM_SUPPLY("DAC_MCLK_GATE", RK3308_GLB_CON, 4, 1, NULL, 0), -- -- SND_SOC_DAPM_SUPPLY("DAC_CURRENT_EN", RK3308_DAC_ANA_CON00, 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("DAC_L_REF_EN", RK3308_DAC_ANA_CON02, 0, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("DAC_R_REF_EN", RK3308_DAC_ANA_CON02, 4, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("DAC_L_CLK_EN", RK3308_DAC_ANA_CON02, 1, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("DAC_R_CLK_EN", RK3308_DAC_ANA_CON02, 5, 0, NULL, 0), -- SND_SOC_DAPM_DAC("DAC_L_DAC_WORK", NULL, RK3308_DAC_ANA_CON02, 3, 0), -- SND_SOC_DAPM_DAC("DAC_R_DAC_WORK", NULL, RK3308_DAC_ANA_CON02, 7, 0), -- -- SND_SOC_DAPM_SUPPLY("DAC_BUF_REF_L", RK3308_DAC_ANA_CON01, 2, 0, NULL, 0), -- SND_SOC_DAPM_SUPPLY("DAC_BUF_REF_R", RK3308_DAC_ANA_CON01, 6, 0, NULL, 0), -- SND_SOC_DAPM_OUT_DRV_E("HPOUT_POP_SOUND_L", SND_SOC_NOPM, 0, 0, NULL, 0, -- rk3308_codec_pop_sound_set, -- SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), -- SND_SOC_DAPM_OUT_DRV_E("HPOUT_POP_SOUND_R", SND_SOC_NOPM, 4, 0, NULL, 0, -- rk3308_codec_pop_sound_set, -- SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), -- SND_SOC_DAPM_OUT_DRV("L_HPOUT_EN", RK3308_DAC_ANA_CON03, 1, 0, NULL, 0), -- SND_SOC_DAPM_OUT_DRV("R_HPOUT_EN", RK3308_DAC_ANA_CON03, 5, 0, NULL, 0), -- SND_SOC_DAPM_OUT_DRV("L_HPOUT_WORK", RK3308_DAC_ANA_CON03, 2, 0, NULL, 0), -- SND_SOC_DAPM_OUT_DRV("R_HPOUT_WORK", RK3308_DAC_ANA_CON03, 6, 0, NULL, 0), -- SND_SOC_DAPM_OUTPUT("HPOUT_L"), -- SND_SOC_DAPM_OUTPUT("HPOUT_R"), -- -- SND_SOC_DAPM_OUT_DRV("L_LINEOUT_EN", RK3308_DAC_ANA_CON04, 0, 0, NULL, 0), -- SND_SOC_DAPM_OUT_DRV("R_LINEOUT_EN", RK3308_DAC_ANA_CON04, 4, 0, NULL, 0), -- SND_SOC_DAPM_OUTPUT("LINEOUT_L"), -- SND_SOC_DAPM_OUTPUT("LINEOUT_R"), --}; -+ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { -+ dev_err(rk3308->plat_dev, -+ "%s: Invalid ADC grp: %d\n", __func__, e->reg); -+ return -EINVAL; -+ } - --static const struct snd_soc_dapm_route rk3308_codec_dapm_routes[] = { -- { "MICBIAS1", NULL, "MICBIAS Current" }, -- { "MICBIAS2", NULL, "MICBIAS Current" }, -- -- { "MIC1_EN", NULL, "MIC1" }, -- { "MIC2_EN", NULL, "MIC2" }, -- { "MIC3_EN", NULL, "MIC3" }, -- { "MIC4_EN", NULL, "MIC4" }, -- { "MIC5_EN", NULL, "MIC5" }, -- { "MIC6_EN", NULL, "MIC6" }, -- { "MIC7_EN", NULL, "MIC7" }, -- { "MIC8_EN", NULL, "MIC8" }, -- -- { "MIC1_WORK", NULL, "MIC1_EN" }, -- { "MIC2_WORK", NULL, "MIC2_EN" }, -- { "MIC3_WORK", NULL, "MIC3_EN" }, -- { "MIC4_WORK", NULL, "MIC4_EN" }, -- { "MIC5_WORK", NULL, "MIC5_EN" }, -- { "MIC6_WORK", NULL, "MIC6_EN" }, -- { "MIC7_WORK", NULL, "MIC7_EN" }, -- { "MIC8_WORK", NULL, "MIC8_EN" }, -- -- { "CH1_IN_SEL", NULL, "MIC1_WORK" }, -- { "CH2_IN_SEL", NULL, "MIC2_WORK" }, -- -- { "ALC1_EN", NULL, "CH1_IN_SEL" }, -- { "ALC2_EN", NULL, "CH2_IN_SEL" }, -- { "ALC3_EN", NULL, "MIC3_WORK" }, -- { "ALC4_EN", NULL, "MIC4_WORK" }, -- { "ALC5_EN", NULL, "MIC5_WORK" }, -- { "ALC6_EN", NULL, "MIC6_WORK" }, -- { "ALC7_EN", NULL, "MIC7_WORK" }, -- { "ALC8_EN", NULL, "MIC8_WORK" }, -- -- { "ADC1_EN", NULL, "ALC1_EN" }, -- { "ADC2_EN", NULL, "ALC2_EN" }, -- { "ADC3_EN", NULL, "ALC3_EN" }, -- { "ADC4_EN", NULL, "ALC4_EN" }, -- { "ADC5_EN", NULL, "ALC5_EN" }, -- { "ADC6_EN", NULL, "ALC6_EN" }, -- { "ADC7_EN", NULL, "ALC7_EN" }, -- { "ADC8_EN", NULL, "ALC8_EN" }, -- -- { "ADC1_WORK", NULL, "ADC1_EN" }, -- { "ADC2_WORK", NULL, "ADC2_EN" }, -- { "ADC3_WORK", NULL, "ADC3_EN" }, -- { "ADC4_WORK", NULL, "ADC4_EN" }, -- { "ADC5_WORK", NULL, "ADC5_EN" }, -- { "ADC6_WORK", NULL, "ADC6_EN" }, -- { "ADC7_WORK", NULL, "ADC7_EN" }, -- { "ADC8_WORK", NULL, "ADC8_EN" }, -- -- { "ADC1_BUF_REF_EN", NULL, "ADC_CURRENT_EN12" }, -- { "ADC2_BUF_REF_EN", NULL, "ADC_CURRENT_EN12" }, -- { "ADC3_BUF_REF_EN", NULL, "ADC_CURRENT_EN34" }, -- { "ADC4_BUF_REF_EN", NULL, "ADC_CURRENT_EN34" }, -- { "ADC5_BUF_REF_EN", NULL, "ADC_CURRENT_EN56" }, -- { "ADC6_BUF_REF_EN", NULL, "ADC_CURRENT_EN56" }, -- { "ADC7_BUF_REF_EN", NULL, "ADC_CURRENT_EN78" }, -- { "ADC8_BUF_REF_EN", NULL, "ADC_CURRENT_EN78" }, -- -- { "ADC1_WORK", NULL, "ADC1_BUF_REF_EN" }, -- { "ADC2_WORK", NULL, "ADC2_BUF_REF_EN" }, -- { "ADC3_WORK", NULL, "ADC3_BUF_REF_EN" }, -- { "ADC4_WORK", NULL, "ADC4_BUF_REF_EN" }, -- { "ADC5_WORK", NULL, "ADC5_BUF_REF_EN" }, -- { "ADC6_WORK", NULL, "ADC6_BUF_REF_EN" }, -- { "ADC7_WORK", NULL, "ADC7_BUF_REF_EN" }, -- { "ADC8_WORK", NULL, "ADC8_BUF_REF_EN" }, -- -- { "ADC1_CLK_EN", NULL, "ADC_MCLK_GATE" }, -- { "ADC2_CLK_EN", NULL, "ADC_MCLK_GATE" }, -- { "ADC3_CLK_EN", NULL, "ADC_MCLK_GATE" }, -- { "ADC4_CLK_EN", NULL, "ADC_MCLK_GATE" }, -- { "ADC5_CLK_EN", NULL, "ADC_MCLK_GATE" }, -- { "ADC6_CLK_EN", NULL, "ADC_MCLK_GATE" }, -- { "ADC7_CLK_EN", NULL, "ADC_MCLK_GATE" }, -- { "ADC8_CLK_EN", NULL, "ADC_MCLK_GATE" }, -- -- { "ADC1_WORK", NULL, "ADC1_CLK_EN" }, -- { "ADC2_WORK", NULL, "ADC2_CLK_EN" }, -- { "ADC3_WORK", NULL, "ADC3_CLK_EN" }, -- { "ADC4_WORK", NULL, "ADC4_CLK_EN" }, -- { "ADC5_WORK", NULL, "ADC5_CLK_EN" }, -- { "ADC6_WORK", NULL, "ADC6_CLK_EN" }, -- { "ADC7_WORK", NULL, "ADC7_CLK_EN" }, -- { "ADC8_WORK", NULL, "ADC8_CLK_EN" }, -- -- { "ALC1_WORK", NULL, "ADC1_WORK" }, -- { "ALC2_WORK", NULL, "ADC2_WORK" }, -- { "ALC3_WORK", NULL, "ADC3_WORK" }, -- { "ALC4_WORK", NULL, "ADC4_WORK" }, -- { "ALC5_WORK", NULL, "ADC5_WORK" }, -- { "ALC6_WORK", NULL, "ADC6_WORK" }, -- { "ALC7_WORK", NULL, "ADC7_WORK" }, -- { "ALC8_WORK", NULL, "ADC8_WORK" }, -- -- { "HiFi Capture", NULL, "ALC1_WORK" }, -- { "HiFi Capture", NULL, "ALC2_WORK" }, -- { "HiFi Capture", NULL, "ALC3_WORK" }, -- { "HiFi Capture", NULL, "ALC4_WORK" }, -- { "HiFi Capture", NULL, "ALC5_WORK" }, -- { "HiFi Capture", NULL, "ALC6_WORK" }, -- { "HiFi Capture", NULL, "ALC7_WORK" }, -- { "HiFi Capture", NULL, "ALC8_WORK" }, -- -- { "DAC_L_HPMIX_EN", NULL, "HiFi Playback" }, -- { "DAC_R_HPMIX_EN", NULL, "HiFi Playback" }, -- { "DAC_L_HPMIX_WORK", NULL, "DAC_L_HPMIX_EN" }, -- { "DAC_R_HPMIX_WORK", NULL, "DAC_R_HPMIX_EN" }, -- { "DAC HPMIX Left", NULL, "DAC_L_HPMIX_WORK" }, -- { "DAC HPMIX Right", NULL, "DAC_R_HPMIX_WORK" }, -- -- { "DAC_L_DAC_WORK", NULL, "DAC HPMIX Left" }, -- { "DAC_R_DAC_WORK", NULL, "DAC HPMIX Right" }, -- -- { "DAC_L_REF_EN", NULL, "DAC_CURRENT_EN" }, -- { "DAC_R_REF_EN", NULL, "DAC_CURRENT_EN" }, -- { "DAC_L_CLK_EN", NULL, "DAC_L_REF_EN" }, -- { "DAC_R_CLK_EN", NULL, "DAC_R_REF_EN" }, -- { "DAC_L_CLK_EN", NULL, "DAC_MCLK_GATE" }, -- { "DAC_R_CLK_EN", NULL, "DAC_MCLK_GATE" }, -- { "DAC_L_DAC_WORK", NULL, "DAC_L_CLK_EN" }, -- { "DAC_R_DAC_WORK", NULL, "DAC_R_CLK_EN" }, -- { "DAC_L_HPMIX_SEL", NULL, "DAC_L_DAC_WORK" }, -- { "DAC_R_HPMIX_SEL", NULL, "DAC_R_DAC_WORK" }, -- -- { "HPOUT_L", NULL, "DAC_BUF_REF_L" }, -- { "HPOUT_R", NULL, "DAC_BUF_REF_R" }, -- { "L_HPOUT_EN", NULL, "DAC_L_HPMIX_SEL" }, -- { "R_HPOUT_EN", NULL, "DAC_R_HPMIX_SEL" }, -- { "L_HPOUT_WORK", NULL, "L_HPOUT_EN" }, -- { "R_HPOUT_WORK", NULL, "R_HPOUT_EN" }, -- { "HPOUT_POP_SOUND_L", NULL, "L_HPOUT_WORK" }, -- { "HPOUT_POP_SOUND_R", NULL, "R_HPOUT_WORK" }, -- { "HPOUT_L", NULL, "HPOUT_POP_SOUND_L" }, -- { "HPOUT_R", NULL, "HPOUT_POP_SOUND_R" }, -- -- { "L_LINEOUT_EN", NULL, "DAC_L_HPMIX_SEL" }, -- { "R_LINEOUT_EN", NULL, "DAC_R_HPMIX_SEL" }, -- { "LINEOUT_L", NULL, "L_LINEOUT_EN" }, -- { "LINEOUT_R", NULL, "R_LINEOUT_EN" }, --}; -+ if (e->shift_l) -+ ucontrol->value.integer.value[0] = rk3308->agc_r[e->reg]; -+ else -+ ucontrol->value.integer.value[0] = rk3308->agc_l[e->reg]; -+ -+ return 0; -+} - --static int rk3308_codec_set_dai_fmt(struct snd_soc_dai *codec_dai, -- unsigned int fmt) -+static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) - { -- struct snd_soc_component *component = codec_dai->component; -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); - struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -- const unsigned int inv_bits = fmt & SND_SOC_DAIFMT_INV_MASK; -- const bool inv_bitclk = -- (inv_bits & SND_SOC_DAIFMT_IB_IF) || -- (inv_bits & SND_SOC_DAIFMT_IB_NF); -- const bool inv_frmclk = -- (inv_bits & SND_SOC_DAIFMT_IB_IF) || -- (inv_bits & SND_SOC_DAIFMT_NB_IF); -- const unsigned int dac_master_bits = rk3308->codec_ver < ACODEC_VERSION_C ? -- RK3308_DAC_IO_MODE_MASTER | RK3308_DAC_MODE_MASTER : -- RK3308BS_DAC_IO_MODE_MASTER | RK3308BS_DAC_MODE_MASTER; -- unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0; -- bool is_master = false; -- int grp; -+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; -+ unsigned int value = ucontrol->value.integer.value[0]; -+ int grp = e->reg; - -- switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -- case SND_SOC_DAIFMT_CBC_CFC: -- break; -- case SND_SOC_DAIFMT_CBP_CFP: -- adc_aif2 |= RK3308_ADC_IO_MODE_MASTER; -- adc_aif2 |= RK3308_ADC_MODE_MASTER; -- dac_aif2 |= dac_master_bits; -- is_master = true; -- break; -- default: -+ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { -+ dev_err(rk3308->plat_dev, -+ "%s: Invalid ADC grp: %d\n", __func__, e->reg); - return -EINVAL; - } - -- switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -- case SND_SOC_DAIFMT_DSP_A: -- adc_aif1 |= RK3308_ADC_I2S_MODE_PCM; -- dac_aif1 |= RK3308_DAC_I2S_MODE_PCM; -- break; -- case SND_SOC_DAIFMT_I2S: -- adc_aif1 |= RK3308_ADC_I2S_MODE_I2S; -- dac_aif1 |= RK3308_DAC_I2S_MODE_I2S; -- break; -- case SND_SOC_DAIFMT_RIGHT_J: -- adc_aif1 |= RK3308_ADC_I2S_MODE_RJ; -- dac_aif1 |= RK3308_DAC_I2S_MODE_RJ; -- break; -- case SND_SOC_DAIFMT_LEFT_J: -- adc_aif1 |= RK3308_ADC_I2S_MODE_LJ; -- dac_aif1 |= RK3308_DAC_I2S_MODE_LJ; -- break; -- default: -- return -EINVAL; -- } -+ if (value) { -+ /* ALC AGC On */ -+ if (e->shift_l) { -+ /* ALC AGC Right On */ -+ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp), -+ RK3308_AGC_FUNC_SEL_MSK, -+ RK3308_AGC_FUNC_SEL_EN); -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp), -+ RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK, -+ RK3308_ADC_ALCR_CON_GAIN_PGAR_EN); - -- if (inv_bitclk) { -- adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL; -- dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL; -- } -+ rk3308->agc_r[e->reg] = 1; -+ } else { -+ /* ALC AGC Left On */ -+ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp), -+ RK3308_AGC_FUNC_SEL_MSK, -+ RK3308_AGC_FUNC_SEL_EN); -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp), -+ RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK, -+ RK3308_ADC_ALCL_CON_GAIN_PGAL_EN); - -- if (inv_frmclk) { -- adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL; -- dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL; -- } -+ rk3308->agc_l[e->reg] = 1; -+ } -+ } else { -+ /* ALC AGC Off */ -+ if (e->shift_l) { -+ /* ALC AGC Right Off */ -+ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp), -+ RK3308_AGC_FUNC_SEL_MSK, -+ RK3308_AGC_FUNC_SEL_DIS); -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp), -+ RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK, -+ RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS); - -- /* -- * Hold ADC Digital registers start at master mode -- * -- * There are 8 ADCs which use the same internal SCLK and LRCK for -- * master mode. We need to make sure that they are in effect at the -- * same time, otherwise they will cause abnormal clocks. -- */ -- if (is_master) -- regmap_clear_bits(rk3308->regmap, RK3308_GLB_CON, RK3308_ADC_DIG_WORK); -+ rk3308->agc_r[e->reg] = 0; -+ } else { -+ /* ALC AGC Left Off */ -+ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp), -+ RK3308_AGC_FUNC_SEL_MSK, -+ RK3308_AGC_FUNC_SEL_DIS); -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp), -+ RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK, -+ RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS); - -- for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) { -- regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp), -- RK3308_ADC_I2S_LRC_POL_REVERSAL | -- RK3308_ADC_I2S_MODE_MSK, -- adc_aif1); -- regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp), -- RK3308_ADC_IO_MODE_MASTER | -- RK3308_ADC_MODE_MASTER | -- RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL, -- adc_aif2); -+ rk3308->agc_l[e->reg] = 0; -+ } - } - -- /* Hold ADC Digital registers end at master mode */ -- if (is_master) -- regmap_set_bits(rk3308->regmap, RK3308_GLB_CON, RK3308_ADC_DIG_WORK); -- -- regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, -- RK3308_DAC_I2S_LRC_POL_REVERSAL | -- RK3308_DAC_I2S_MODE_MSK, -- dac_aif1); -- regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, -- dac_master_bits | RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL, -- dac_aif2); -- - return 0; - } - --static int rk3308_codec_dac_dig_config(struct rk3308_codec_priv *rk3308, -- struct snd_pcm_hw_params *params) -+static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) - { -- unsigned int dac_aif1 = 0; -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; -+ unsigned int value; -+ int grp = e->reg; - -- switch (params_format(params)) { -- case SNDRV_PCM_FORMAT_S16_LE: -- dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_16BITS; -- break; -- case SNDRV_PCM_FORMAT_S20_3LE: -- dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_20BITS; -- break; -- case SNDRV_PCM_FORMAT_S24_LE: -- dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_24BITS; -- break; -- case SNDRV_PCM_FORMAT_S32_LE: -- dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_32BITS; -- break; -- default: -+ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { -+ dev_err(rk3308->plat_dev, -+ "%s: Invalid ADC grp: %d\n", __func__, e->reg); - return -EINVAL; - } - -- regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, -- RK3308_DAC_I2S_VALID_LEN_MSK, dac_aif1); -- regmap_set_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, RK3308_DAC_I2S_WORK); -+ if (e->shift_l) { -+ regmap_read(rk3308->regmap, RK3308_ALC_R_DIG_CON04(grp), &value); -+ rk3308->agc_asr_r[e->reg] = value >> RK3308_AGC_APPROX_RATE_SFT; -+ ucontrol->value.integer.value[0] = rk3308->agc_asr_r[e->reg]; -+ } else { -+ regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON04(grp), &value); -+ rk3308->agc_asr_l[e->reg] = value >> RK3308_AGC_APPROX_RATE_SFT; -+ ucontrol->value.integer.value[0] = rk3308->agc_asr_l[e->reg]; -+ } - - return 0; - } - --static int rk3308_codec_adc_dig_config(struct rk3308_codec_priv *rk3308, -- struct snd_pcm_hw_params *params) -+static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) - { -- unsigned int adc_aif1 = 0; -- /* -- * grp 0 = ADC1 and ADC2 -- * grp 1 = ADC3 and ADC4 -- * grp 2 = ADC5 and ADC6 -- * grp 3 = ADC7 and ADC8 -- */ -- u32 used_adc_grps; -- int grp; -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; -+ unsigned int value; -+ int grp = e->reg; - -- switch (params_channels(params)) { -- case 1: -- adc_aif1 |= RK3308_ADC_I2S_MONO; -- used_adc_grps = 1; -- break; -- case 2: -- case 4: -- case 6: -- case 8: -- used_adc_grps = params_channels(params) / 2; -- break; -- default: -- dev_err(rk3308->dev, "Invalid channel number %d\n", params_channels(params)); -+ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { -+ dev_err(rk3308->plat_dev, -+ "%s: Invalid ADC grp: %d\n", __func__, e->reg); - return -EINVAL; - } - -- switch (params_format(params)) { -- case SNDRV_PCM_FORMAT_S16_LE: -- adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_16BITS; -- break; -- case SNDRV_PCM_FORMAT_S20_3LE: -- adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_20BITS; -- break; -- case SNDRV_PCM_FORMAT_S24_LE: -- adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_24BITS; -- break; -- case SNDRV_PCM_FORMAT_S32_LE: -- adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_32BITS; -- break; -- default: -+ value = ucontrol->value.integer.value[0] << RK3308_AGC_APPROX_RATE_SFT; -+ -+ if (e->shift_l) { -+ /* ALC AGC Right Approximate Sample Rate */ -+ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON04(grp), -+ RK3308_AGC_APPROX_RATE_MSK, -+ value); -+ rk3308->agc_asr_r[e->reg] = ucontrol->value.integer.value[0]; -+ } else { -+ /* ALC AGC Left Approximate Sample Rate */ -+ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON04(grp), -+ RK3308_AGC_APPROX_RATE_MSK, -+ value); -+ rk3308->agc_asr_l[e->reg] = ucontrol->value.integer.value[0]; -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; -+ unsigned int value; -+ int grp = e->reg; -+ -+ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { -+ dev_err(rk3308->plat_dev, -+ "%s: Invalid ADC grp: %d\n", __func__, e->reg); - return -EINVAL; - } - -- for (grp = 0; grp < used_adc_grps; grp++) { -- regmap_update_bits(rk3308->regmap, -- RK3308_ADC_DIG_CON03(grp), -- RK3308_ADC_L_CH_BIST_MSK | RK3308_ADC_R_CH_BIST_MSK, -- RK3308_ADC_L_CH_NORMAL_LEFT | RK3308_ADC_R_CH_NORMAL_RIGHT); -- regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp), -- RK3308_ADC_I2S_VALID_LEN_MSK | RK3308_ADC_I2S_MONO, adc_aif1); -- regmap_set_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp), RK3308_ADC_I2S_WORK); -+ if (e->shift_l) { -+ /* ADC MIC Right Mute/Work Infos */ -+ regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), &value); -+ rk3308->mic_mute_r[e->reg] = (value & RK3308_ADC_R_CH_BIST_SINE) >> -+ RK3308_ADC_R_CH_BIST_SFT; -+ ucontrol->value.integer.value[0] = rk3308->mic_mute_r[e->reg]; -+ } else { -+ /* ADC MIC Left Mute/Work Infos */ -+ regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), &value); -+ rk3308->mic_mute_l[e->reg] = (value & RK3308_ADC_L_CH_BIST_SINE) >> -+ RK3308_ADC_L_CH_BIST_SFT; -+ ucontrol->value.integer.value[0] = rk3308->mic_mute_l[e->reg]; - } - - return 0; - } - --static int rk3308_codec_hw_params(struct snd_pcm_substream *substream, -- struct snd_pcm_hw_params *params, -- struct snd_soc_dai *dai) -+static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) - { -- struct snd_soc_component *component = dai->component; -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); - struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; -+ unsigned int value; -+ int grp = e->reg; - -- return (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? -- rk3308_codec_dac_dig_config(rk3308, params) : -- rk3308_codec_adc_dig_config(rk3308, params); --} -+ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { -+ dev_err(rk3308->plat_dev, -+ "%s: Invalid ADC grp: %d\n", __func__, e->reg); -+ return -EINVAL; -+ } - --static const struct snd_soc_dai_ops rk3308_codec_dai_ops = { -- .hw_params = rk3308_codec_hw_params, -- .set_fmt = rk3308_codec_set_dai_fmt, --}; -+ if (e->shift_l) { -+ /* ADC MIC Right Mute/Work Configuration */ -+ value = ucontrol->value.integer.value[0] << RK3308_ADC_R_CH_BIST_SFT; -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_R_CH_BIST_SINE, -+ value); -+ rk3308->mic_mute_r[e->reg] = ucontrol->value.integer.value[0]; -+ } else { -+ /* ADC MIC Left Mute/Work Configuration */ -+ value = ucontrol->value.integer.value[0] << RK3308_ADC_L_CH_BIST_SFT; -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_L_CH_BIST_SINE, -+ value); -+ rk3308->mic_mute_l[e->reg] = ucontrol->value.integer.value[0]; -+ } - --static struct snd_soc_dai_driver rk3308_codec_dai_driver = { -- .name = "rk3308-hifi", -- .playback = { -- .stream_name = "HiFi Playback", -- .channels_min = 2, -- .channels_max = 2, -- .rates = SNDRV_PCM_RATE_8000_192000, -- .formats = (SNDRV_PCM_FMTBIT_S16_LE | -- SNDRV_PCM_FMTBIT_S20_3LE | -- SNDRV_PCM_FMTBIT_S24_LE | -- SNDRV_PCM_FMTBIT_S32_LE), -- }, -- .capture = { -- .stream_name = "HiFi Capture", -- .channels_min = 1, -- .channels_max = 8, -- .rates = SNDRV_PCM_RATE_8000_192000, -- .formats = (SNDRV_PCM_FMTBIT_S16_LE | -- SNDRV_PCM_FMTBIT_S20_3LE | -- SNDRV_PCM_FMTBIT_S24_LE | -- SNDRV_PCM_FMTBIT_S32_LE), -- }, -- .ops = &rk3308_codec_dai_ops, --}; -+ return 0; -+} - --static void rk3308_codec_reset(struct snd_soc_component *component) -+static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) - { -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); - struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); - -- reset_control_assert(rk3308->reset); -- usleep_range(10000, 11000); /* estimated value */ -- reset_control_deassert(rk3308->reset); -+ ucontrol->value.integer.value[0] = rk3308->micbias_volt; - -- regmap_write(rk3308->regmap, RK3308_GLB_CON, 0x00); -- usleep_range(10000, 11000); /* estimated value */ -- regmap_write(rk3308->regmap, RK3308_GLB_CON, -- RK3308_SYS_WORK | -- RK3308_DAC_DIG_WORK | -- RK3308_ADC_DIG_WORK); -+ return 0; - } - --/* -- * Initialize register whose default after HW reset is problematic or which -- * are never modified. -- */ --static int rk3308_codec_initialize(struct rk3308_codec_priv *rk3308) -+static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) - { -- int grp; -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ unsigned int volt = ucontrol->value.integer.value[0]; -+ int ret; - -- /* -- * Init ADC digital vol to 0 dB (reset value is 0xff, undocumented). -- * Range: -97dB ~ +32dB. -- */ -- if (rk3308->codec_ver == ACODEC_VERSION_C) { -- for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) { -- regmap_write(rk3308->regmap, RK3308_ADC_DIG_CON05(grp), -- RK3308_ADC_DIG_VOL_CON_x_0DB); -- regmap_write(rk3308->regmap, RK3308_ADC_DIG_CON06(grp), -- RK3308_ADC_DIG_VOL_CON_x_0DB); -- } -+ ret = check_micbias(volt); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, "The invalid micbias volt: %d\n", -+ volt); -+ return ret; - } - -- /* set HPMIX default gains (reset value is 0, which is illegal) */ -- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, -- RK3308_DAC_L_HPMIX_GAIN_MSK | -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0), -+ RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK, -+ volt); -+ -+ rk3308->micbias_volt = volt; -+ -+ return 0; -+} -+ -+static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ -+ ucontrol->value.integer.value[0] = rk3308->enable_micbias; -+ -+ return 0; -+} -+ -+static int rk3308_codec_main_micbias_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ unsigned int on = ucontrol->value.integer.value[0]; -+ -+ if (on) { -+ if (!rk3308->enable_micbias) -+ rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt); -+ } else { -+ if (rk3308->enable_micbias) -+ rk3308_codec_micbias_disable(rk3308); -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_mic_gain_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ return snd_soc_get_volsw_range(kcontrol, ucontrol); -+} -+ -+static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ unsigned int gain = ucontrol->value.integer.value[0]; -+ -+ if (gain > RK3308_ADC_CH1_MIC_GAIN_MAX) { -+ dev_err(rk3308->plat_dev, "%s: invalid mic gain: %d\n", -+ __func__, gain); -+ return -EINVAL; -+ } -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_A) { -+ /* -+ * From the TRM, there are only suupport 0dB(gain==0) and -+ * 20dB(gain==3) on the codec version A. -+ */ -+ if (!(gain == 0 || gain == RK3308_ADC_CH1_MIC_GAIN_MAX)) { -+ dev_err(rk3308->plat_dev, -+ "version A doesn't supported: %d, expect: 0,%d\n", -+ gain, RK3308_ADC_CH1_MIC_GAIN_MAX); -+ return 0; -+ } -+ } -+ -+ return snd_soc_put_volsw_range(kcontrol, ucontrol); -+} -+ -+static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; -+ unsigned int value; -+ -+ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { -+ dev_err(rk3308->plat_dev, -+ "%s: Invalid ADC grp: %d\n", __func__, e->reg); -+ return -EINVAL; -+ } -+ -+ regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg), &value); -+ if (value & RK3308_ADC_HPF_PATH_MSK) -+ rk3308->hpf_cutoff[e->reg] = 0; -+ else -+ rk3308->hpf_cutoff[e->reg] = 1; -+ -+ ucontrol->value.integer.value[0] = rk3308->hpf_cutoff[e->reg]; -+ -+ return 0; -+} -+ -+static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; -+ unsigned int value = ucontrol->value.integer.value[0]; -+ -+ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { -+ dev_err(rk3308->plat_dev, -+ "%s: Invalid ADC grp: %d\n", __func__, e->reg); -+ return -EINVAL; -+ } -+ -+ if (value) { -+ /* Enable high pass filter for ADCs */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg), -+ RK3308_ADC_HPF_PATH_MSK, -+ RK3308_ADC_HPF_PATH_EN); -+ } else { -+ /* Disable high pass filter for ADCs. */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg), -+ RK3308_ADC_HPF_PATH_MSK, -+ RK3308_ADC_HPF_PATH_DIS); -+ } -+ -+ rk3308->hpf_cutoff[e->reg] = value; -+ -+ return 0; -+} -+ -+static int rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ return snd_soc_get_volsw_range(kcontrol, ucontrol); -+} -+ -+static int rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ unsigned int dgain = ucontrol->value.integer.value[0]; -+ -+ if (dgain > RK3308_DAC_L_HPOUT_GAIN_MAX) { -+ dev_err(rk3308->plat_dev, "%s: invalid l_dgain: %d\n", -+ __func__, dgain); -+ return -EINVAL; -+ } -+ -+ rk3308->hpout_l_dgain = dgain; -+ -+ return snd_soc_put_volsw_range(kcontrol, ucontrol); -+} -+ -+static int rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ return snd_soc_get_volsw_range(kcontrol, ucontrol); -+} -+ -+static int rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ unsigned int dgain = ucontrol->value.integer.value[0]; -+ -+ if (dgain > RK3308_DAC_R_HPOUT_GAIN_MAX) { -+ dev_err(rk3308->plat_dev, "%s: invalid r_dgain: %d\n", -+ __func__, dgain); -+ return -EINVAL; -+ } -+ -+ rk3308->hpout_r_dgain = dgain; -+ -+ return snd_soc_put_volsw_range(kcontrol, ucontrol); -+} -+ -+static u32 to_mapped_grp(struct rk3308_codec_priv *rk3308, int idx) -+{ -+ return rk3308->i2s_sdis[idx]; -+} -+ -+static bool adc_for_each_grp(struct rk3308_codec_priv *rk3308, -+ int type, int idx, u32 *grp) -+{ -+ if (type == ADC_TYPE_NORMAL) { -+ u32 mapped_grp = to_mapped_grp(rk3308, idx); -+ int max_grps; -+ -+ if (rk3308->enable_all_adcs) -+ max_grps = ADC_LR_GROUP_MAX; -+ else -+ max_grps = rk3308->used_adc_grps; -+ -+ if (idx >= max_grps) -+ return false; -+ -+ if ((!rk3308->loopback_dacs_enabled) && -+ handle_loopback(rk3308) && -+ rk3308->loopback_grp == mapped_grp) { -+ /* -+ * Ths loopback DACs are closed, and specify the -+ * loopback ADCs. -+ */ -+ *grp = ADC_GRP_SKIP_MAGIC; -+ } else if (rk3308->en_always_grps_num && -+ rk3308->skip_grps[mapped_grp]) { -+ /* To set the skip flag if the ADC GRP is enabled. */ -+ *grp = ADC_GRP_SKIP_MAGIC; -+ } else { -+ *grp = mapped_grp; -+ } -+ -+ dev_dbg(rk3308->plat_dev, -+ "ADC_TYPE_NORMAL, idx: %d, mapped_grp: %d, get grp: %d,\n", -+ idx, mapped_grp, *grp); -+ } else if (type == ADC_TYPE_ALL) { -+ if (idx >= ADC_LR_GROUP_MAX) -+ return false; -+ -+ *grp = idx; -+ dev_dbg(rk3308->plat_dev, -+ "ADC_TYPE_ALL, idx: %d, get grp: %d\n", -+ idx, *grp); -+ } else if (type == ADC_TYPE_DBG) { -+ if (idx >= ADC_LR_GROUP_MAX) -+ return false; -+ -+ if (idx == (int)rk3308->cur_dbg_grp) -+ *grp = idx; -+ else -+ *grp = ADC_GRP_SKIP_MAGIC; -+ -+ dev_dbg(rk3308->plat_dev, -+ "ADC_TYPE_DBG, idx: %d, get grp: %d\n", -+ idx, *grp); -+ } else { -+ if (idx >= 1) -+ return false; -+ -+ *grp = rk3308->loopback_grp; -+ dev_dbg(rk3308->plat_dev, -+ "ADC_TYPE_LOOPBACK, idx: %d, get grp: %d\n", -+ idx, *grp); -+ } -+ -+ return true; -+} -+ -+static int rk3308_codec_get_dac_path_state(struct rk3308_codec_priv *rk3308) -+{ -+ return rk3308->dac_path_state; -+} -+ -+static void rk3308_codec_set_dac_path_state(struct rk3308_codec_priv *rk3308, -+ int state) -+{ -+ rk3308->dac_path_state = state; -+} -+ -+static void rk3308_headphone_ctl(struct rk3308_codec_priv *rk3308, int on) -+{ -+ if (rk3308->hp_ctl_gpio) -+ gpiod_direction_output(rk3308->hp_ctl_gpio, on); -+} -+ -+static void rk3308_speaker_ctl(struct rk3308_codec_priv *rk3308, int on) -+{ -+ if (on) { -+ if (rk3308->pa_drv_gpio) { -+ gpiod_direction_output(rk3308->pa_drv_gpio, on); -+ msleep(rk3308->delay_pa_drv_ms); -+ } -+ -+ if (rk3308->spk_ctl_gpio) -+ gpiod_direction_output(rk3308->spk_ctl_gpio, on); -+ } else { -+ if (rk3308->spk_ctl_gpio) -+ gpiod_direction_output(rk3308->spk_ctl_gpio, on); -+ -+ if (rk3308->pa_drv_gpio) { -+ msleep(rk3308->delay_pa_drv_ms); -+ gpiod_direction_output(rk3308->pa_drv_gpio, on); -+ } -+ } -+} -+ -+static int rk3308_codec_reset(struct snd_soc_component *component) -+{ -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ -+ reset_control_assert(rk3308->reset); -+ usleep_range(2000, 2500); /* estimated value */ -+ reset_control_deassert(rk3308->reset); -+ -+ regmap_write(rk3308->regmap, RK3308_GLB_CON, 0x00); -+ usleep_range(200, 300); /* estimated value */ -+ regmap_write(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_SYS_WORK | -+ RK3308_DAC_DIG_WORK | -+ RK3308_ADC_DIG_WORK); -+ -+ return 0; -+} -+ -+static int rk3308_codec_adc_dig_reset(struct rk3308_codec_priv *rk3308) -+{ -+ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_ADC_DIG_WORK, -+ RK3308_ADC_DIG_RESET); -+ udelay(50); -+ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_ADC_DIG_WORK, -+ RK3308_ADC_DIG_WORK); -+ -+ return 0; -+} -+ -+static int rk3308_codec_dac_dig_reset(struct rk3308_codec_priv *rk3308) -+{ -+ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_DAC_DIG_WORK, -+ RK3308_DAC_DIG_RESET); -+ udelay(50); -+ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_DAC_DIG_WORK, -+ RK3308_DAC_DIG_WORK); -+ -+ return 0; -+} -+ -+static int rk3308_set_bias_level(struct snd_soc_component *component, -+ enum snd_soc_bias_level level) -+{ -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ -+ switch (level) { -+ case SND_SOC_BIAS_ON: -+ break; -+ case SND_SOC_BIAS_PREPARE: -+ break; -+ case SND_SOC_BIAS_STANDBY: -+ regcache_cache_only(rk3308->regmap, false); -+ regcache_sync(rk3308->regmap); -+ break; -+ case SND_SOC_BIAS_OFF: -+ break; -+ } -+ -+ return 0; -+} -+ -+static int rk3308_set_dai_fmt(struct snd_soc_dai *dai, -+ unsigned int fmt) -+{ -+ struct snd_soc_component *component = dai->component; -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0; -+ int idx, grp, is_master; -+ int type = ADC_TYPE_ALL; -+ -+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -+ case SND_SOC_DAIFMT_CBS_CFS: -+ adc_aif2 |= RK3308_ADC_IO_MODE_SLAVE; -+ adc_aif2 |= RK3308_ADC_MODE_SLAVE; -+ dac_aif2 |= RK3308_DAC_IO_MODE_SLAVE; -+ dac_aif2 |= RK3308_DAC_MODE_SLAVE; -+ is_master = 0; -+ break; -+ case SND_SOC_DAIFMT_CBM_CFM: -+ adc_aif2 |= RK3308_ADC_IO_MODE_MASTER; -+ adc_aif2 |= RK3308_ADC_MODE_MASTER; -+ dac_aif2 |= RK3308_DAC_IO_MODE_MASTER; -+ dac_aif2 |= RK3308_DAC_MODE_MASTER; -+ is_master = 1; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_DSP_A: -+ adc_aif1 |= RK3308_ADC_I2S_MODE_PCM; -+ dac_aif1 |= RK3308_DAC_I2S_MODE_PCM; -+ break; -+ case SND_SOC_DAIFMT_I2S: -+ adc_aif1 |= RK3308_ADC_I2S_MODE_I2S; -+ dac_aif1 |= RK3308_DAC_I2S_MODE_I2S; -+ break; -+ case SND_SOC_DAIFMT_RIGHT_J: -+ adc_aif1 |= RK3308_ADC_I2S_MODE_RJ; -+ dac_aif1 |= RK3308_DAC_I2S_MODE_RJ; -+ break; -+ case SND_SOC_DAIFMT_LEFT_J: -+ adc_aif1 |= RK3308_ADC_I2S_MODE_LJ; -+ dac_aif1 |= RK3308_DAC_I2S_MODE_LJ; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { -+ case SND_SOC_DAIFMT_NB_NF: -+ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL; -+ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL; -+ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL; -+ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL; -+ break; -+ case SND_SOC_DAIFMT_IB_IF: -+ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL; -+ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL; -+ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL; -+ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL; -+ break; -+ case SND_SOC_DAIFMT_IB_NF: -+ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL; -+ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL; -+ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL; -+ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL; -+ break; -+ case SND_SOC_DAIFMT_NB_IF: -+ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL; -+ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL; -+ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL; -+ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* -+ * Hold ADC Digital registers start at master mode -+ * -+ * There are 8 ADCs and use the same SCLK and LRCK internal for master -+ * mode, We need to make sure that they are in effect at the same time, -+ * otherwise they will cause the abnormal clocks. -+ */ -+ if (is_master) -+ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_ADC_DIG_WORK, -+ RK3308_ADC_DIG_RESET); -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp), -+ RK3308_ADC_I2S_LRC_POL_MSK | -+ RK3308_ADC_I2S_MODE_MSK, -+ adc_aif1); -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp), -+ RK3308_ADC_IO_MODE_MSK | -+ RK3308_ADC_MODE_MSK | -+ RK3308_ADC_I2S_BIT_CLK_POL_MSK, -+ adc_aif2); -+ } -+ -+ /* Hold ADC Digital registers end at master mode */ -+ if (is_master) -+ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_ADC_DIG_WORK, -+ RK3308_ADC_DIG_WORK); -+ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, -+ RK3308_DAC_I2S_LRC_POL_MSK | -+ RK3308_DAC_I2S_MODE_MSK, -+ dac_aif1); -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, -+ RK3308_DAC_IO_MODE_MSK | -+ RK3308_DAC_MODE_MSK | -+ RK3308_DAC_I2S_BIT_CLK_POL_MSK, -+ dac_aif2); -+ -+ return 0; -+} -+ -+static int rk3308_codec_dac_dig_config(struct rk3308_codec_priv *rk3308, -+ struct snd_pcm_hw_params *params) -+{ -+ unsigned int dac_aif1 = 0, dac_aif2 = 0; -+ -+ /* Clear the status of DAC DIG Digital reigisters */ -+ rk3308_codec_dac_dig_reset(rk3308); -+ -+ switch (params_format(params)) { -+ case SNDRV_PCM_FORMAT_S16_LE: -+ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_16BITS; -+ break; -+ case SNDRV_PCM_FORMAT_S20_3LE: -+ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_20BITS; -+ break; -+ case SNDRV_PCM_FORMAT_S24_LE: -+ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_24BITS; -+ break; -+ case SNDRV_PCM_FORMAT_S32_LE: -+ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_32BITS; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ dac_aif1 |= RK3308_DAC_I2S_LR_NORMAL; -+ dac_aif2 |= RK3308_DAC_I2S_WORK; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, -+ RK3308_DAC_I2S_VALID_LEN_MSK | -+ RK3308_DAC_I2S_LR_MSK, -+ dac_aif1); -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, -+ RK3308_DAC_I2S_MSK, -+ dac_aif2); -+ -+ return 0; -+} -+ -+static int rk3308_codec_adc_dig_config(struct rk3308_codec_priv *rk3308, -+ struct snd_pcm_hw_params *params) -+{ -+ unsigned int adc_aif1 = 0, adc_aif2 = 0; -+ int type = ADC_TYPE_NORMAL; -+ int idx, grp; -+ -+ /* Clear the status of ADC DIG Digital reigisters */ -+ rk3308_codec_adc_dig_reset(rk3308); -+ -+ switch (params_format(params)) { -+ case SNDRV_PCM_FORMAT_S16_LE: -+ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_16BITS; -+ break; -+ case SNDRV_PCM_FORMAT_S20_3LE: -+ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_20BITS; -+ break; -+ case SNDRV_PCM_FORMAT_S24_LE: -+ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_24BITS; -+ break; -+ case SNDRV_PCM_FORMAT_S32_LE: -+ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_32BITS; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (params_channels(params)) { -+ case 1: -+ adc_aif1 |= RK3308_ADC_I2S_MONO; -+ break; -+ case 2: -+ case 4: -+ case 6: -+ case 8: -+ adc_aif1 |= RK3308_ADC_I2S_STEREO; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ adc_aif1 |= RK3308_ADC_I2S_LR_NORMAL; -+ adc_aif2 |= RK3308_ADC_I2S_WORK; -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp), -+ RK3308_ADC_I2S_VALID_LEN_MSK | -+ RK3308_ADC_I2S_LR_MSK | -+ RK3308_ADC_I2S_TYPE_MSK, -+ adc_aif1); -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp), -+ RK3308_ADC_I2S_MSK, -+ adc_aif2); -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_update_adc_grps(struct rk3308_codec_priv *rk3308, -+ struct snd_pcm_hw_params *params) -+{ -+ switch (params_channels(params)) { -+ case 1: -+ rk3308->used_adc_grps = 1; -+ break; -+ case 2: -+ case 4: -+ case 6: -+ case 8: -+ rk3308->used_adc_grps = params_channels(params) / 2; -+ break; -+ default: -+ dev_err(rk3308->plat_dev, "Invalid channels: %d\n", -+ params_channels(params)); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int rk3308_mute_stream(struct snd_soc_dai *dai, int mute, int stream) -+{ -+ struct snd_soc_component *component = dai->component; -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ -+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) { -+ int dgain; -+ -+ if (mute) { -+ for (dgain = 0x2; dgain <= 0x7; dgain++) { -+ /* -+ * Keep the max -> min digital CIC interpolation -+ * filter gain step by step. -+ * -+ * loud: 0x2; whisper: 0x7 -+ */ -+ regmap_update_bits(rk3308->regmap, -+ RK3308_DAC_DIG_CON04, -+ RK3308_DAC_CIC_IF_GAIN_MSK, -+ dgain); -+ usleep_range(200, 300); /* estimated value */ -+ } -+ -+#if !DEBUG_POP_ALWAYS -+ rk3308_headphone_ctl(rk3308, 0); -+ rk3308_speaker_ctl(rk3308, 0); -+#endif -+ } else { -+#if !DEBUG_POP_ALWAYS -+ if (rk3308->dac_output == DAC_LINEOUT) -+ rk3308_speaker_ctl(rk3308, 1); -+ else if (rk3308->dac_output == DAC_HPOUT) -+ rk3308_headphone_ctl(rk3308, 1); -+ -+ if (rk3308->delay_start_play_ms) -+ msleep(rk3308->delay_start_play_ms); -+#endif -+ for (dgain = 0x7; dgain >= 0x2; dgain--) { -+ /* -+ * Keep the min -> max digital CIC interpolation -+ * filter gain step by step -+ * -+ * loud: 0x2; whisper: 0x7 -+ */ -+ regmap_update_bits(rk3308->regmap, -+ RK3308_DAC_DIG_CON04, -+ RK3308_DAC_CIC_IF_GAIN_MSK, -+ dgain); -+ usleep_range(200, 300); /* estimated value */ -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_digital_fadein(struct rk3308_codec_priv *rk3308) -+{ -+ unsigned int dgain, dgain_ref; -+ -+ if (rk3308->hpout_l_dgain != rk3308->hpout_r_dgain) { -+ pr_warn("HPOUT l_dgain: 0x%x != r_dgain: 0x%x\n", -+ rk3308->hpout_l_dgain, rk3308->hpout_r_dgain); -+ dgain_ref = min(rk3308->hpout_l_dgain, rk3308->hpout_r_dgain); -+ } else { -+ dgain_ref = rk3308->hpout_l_dgain; -+ } -+ -+ /* -+ * We'd better change the gain of the left and right channels -+ * at the same time to avoid different listening -+ */ -+ for (dgain = RK3308_DAC_L_HPOUT_GAIN_NDB_39; -+ dgain <= dgain_ref; dgain++) { -+ /* Step 02 decrease dgains for de-pop */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05, -+ RK3308_DAC_L_HPOUT_GAIN_MSK, -+ dgain); -+ -+ /* Step 02 decrease dgains for de-pop */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06, -+ RK3308_DAC_R_HPOUT_GAIN_MSK, -+ dgain); -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_digital_fadeout(struct rk3308_codec_priv *rk3308) -+{ -+ unsigned int l_dgain, r_dgain; -+ -+ /* -+ * Note. In the step2, adjusting the register step by step to -+ * the appropriate value and taking 20ms as time step -+ */ -+ regmap_read(rk3308->regmap, RK3308_DAC_ANA_CON05, &l_dgain); -+ l_dgain &= RK3308_DAC_L_HPOUT_GAIN_MSK; -+ -+ regmap_read(rk3308->regmap, RK3308_DAC_ANA_CON06, &r_dgain); -+ r_dgain &= RK3308_DAC_R_HPOUT_GAIN_MSK; -+ -+ if (l_dgain != r_dgain) { -+ pr_warn("HPOUT l_dgain: 0x%x != r_dgain: 0x%x\n", -+ l_dgain, r_dgain); -+ l_dgain = min(l_dgain, r_dgain); -+ } -+ -+ /* -+ * We'd better change the gain of the left and right channels -+ * at the same time to avoid different listening -+ */ -+ while (l_dgain >= RK3308_DAC_L_HPOUT_GAIN_NDB_39) { -+ /* Step 02 decrease dgains for de-pop */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05, -+ RK3308_DAC_L_HPOUT_GAIN_MSK, -+ l_dgain); -+ -+ /* Step 02 decrease dgains for de-pop */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06, -+ RK3308_DAC_R_HPOUT_GAIN_MSK, -+ l_dgain); -+ -+ usleep_range(200, 300); /* estimated value */ -+ -+ if (l_dgain == RK3308_DAC_L_HPOUT_GAIN_NDB_39) -+ break; -+ -+ l_dgain--; -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_dac_lineout_enable(struct rk3308_codec_priv *rk3308) -+{ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* Step 04 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, -+ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK | -+ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_L_SEL_DC_FROM_INTERNAL | -+ RK3308_DAC_R_SEL_DC_FROM_INTERNAL); -+ } -+ -+ /* Step 07 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, -+ RK3308_DAC_L_LINEOUT_EN | -+ RK3308_DAC_R_LINEOUT_EN, -+ RK3308_DAC_L_LINEOUT_EN | -+ RK3308_DAC_R_LINEOUT_EN); -+ -+ udelay(20); -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* Step 10 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, -+ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK | -+ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL | -+ RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL); -+ -+ udelay(20); -+ } -+ -+ /* Step 19 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, -+ RK3308_DAC_L_LINEOUT_UNMUTE | -+ RK3308_DAC_R_LINEOUT_UNMUTE, -+ RK3308_DAC_L_LINEOUT_UNMUTE | -+ RK3308_DAC_R_LINEOUT_UNMUTE); -+ udelay(20); -+ -+ return 0; -+} -+ -+static int rk3308_codec_dac_lineout_disable(struct rk3308_codec_priv *rk3308) -+{ -+ /* Step 08 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, -+ RK3308_DAC_L_LINEOUT_UNMUTE | -+ RK3308_DAC_R_LINEOUT_UNMUTE, -+ RK3308_DAC_L_LINEOUT_MUTE | -+ RK3308_DAC_R_LINEOUT_MUTE); -+ -+ /* Step 09 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, -+ RK3308_DAC_L_LINEOUT_EN | -+ RK3308_DAC_R_LINEOUT_EN, -+ RK3308_DAC_L_LINEOUT_DIS | -+ RK3308_DAC_R_LINEOUT_DIS); -+ -+ return 0; -+} -+ -+static int rk3308_codec_dac_hpout_enable(struct rk3308_codec_priv *rk3308) -+{ -+ /* Step 03 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, -+ RK3308_DAC_HPOUT_POP_SOUND_L_MSK | -+ RK3308_DAC_HPOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_HPOUT_POP_SOUND_L_WORK | -+ RK3308_DAC_HPOUT_POP_SOUND_R_WORK); -+ -+ udelay(20); -+ -+ /* Step 07 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_EN | -+ RK3308_DAC_R_HPOUT_EN, -+ RK3308_DAC_L_HPOUT_EN | -+ RK3308_DAC_R_HPOUT_EN); -+ -+ udelay(20); -+ -+ /* Step 08 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_WORK | -+ RK3308_DAC_R_HPOUT_WORK, -+ RK3308_DAC_L_HPOUT_WORK | -+ RK3308_DAC_R_HPOUT_WORK); -+ -+ udelay(20); -+ -+ /* Step 16 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_UNMUTE | -+ RK3308_DAC_R_HPOUT_UNMUTE, -+ RK3308_DAC_L_HPOUT_UNMUTE | -+ RK3308_DAC_R_HPOUT_UNMUTE); -+ -+ udelay(20); -+ -+ return 0; -+} -+ -+static int rk3308_codec_dac_hpout_disable(struct rk3308_codec_priv *rk3308) -+{ -+ /* Step 03 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, -+ RK3308_DAC_HPOUT_POP_SOUND_L_MSK | -+ RK3308_DAC_HPOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_HPOUT_POP_SOUND_L_INIT | -+ RK3308_DAC_HPOUT_POP_SOUND_R_INIT); -+ -+ /* Step 07 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_EN | -+ RK3308_DAC_R_HPOUT_EN, -+ RK3308_DAC_L_HPOUT_DIS | -+ RK3308_DAC_R_HPOUT_DIS); -+ -+ /* Step 08 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_WORK | -+ RK3308_DAC_R_HPOUT_WORK, -+ RK3308_DAC_L_HPOUT_INIT | -+ RK3308_DAC_R_HPOUT_INIT); -+ -+ /* Step 16 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_UNMUTE | -+ RK3308_DAC_R_HPOUT_UNMUTE, -+ RK3308_DAC_L_HPOUT_MUTE | -+ RK3308_DAC_R_HPOUT_MUTE); -+ -+ return 0; -+} -+ -+static int rk3308_codec_dac_switch(struct rk3308_codec_priv *rk3308, -+ int dac_output) -+{ int ret = 0; -+ -+ if (rk3308->dac_output == dac_output) { -+ dev_info(rk3308->plat_dev, -+ "Don't need to change dac_output: %d\n", dac_output); -+ goto out; -+ } -+ -+ switch (dac_output) { -+ case DAC_LINEOUT: -+ case DAC_HPOUT: -+ case DAC_LINEOUT_HPOUT: -+ break; -+ default: -+ dev_err(rk3308->plat_dev, "Unknown value: %d\n", dac_output); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ if (rk3308_codec_get_dac_path_state(rk3308) == PATH_BUSY) { -+ /* -+ * We can only switch the audio path to LINEOUT or HPOUT on -+ * codec during playbacking, otherwise, just update the -+ * dac_output flag. -+ */ -+ switch (dac_output) { -+ case DAC_LINEOUT: -+ rk3308_headphone_ctl(rk3308, 0); -+ rk3308_speaker_ctl(rk3308, 1); -+ rk3308_codec_dac_hpout_disable(rk3308); -+ rk3308_codec_dac_lineout_enable(rk3308); -+ break; -+ case DAC_HPOUT: -+ rk3308_speaker_ctl(rk3308, 0); -+ rk3308_headphone_ctl(rk3308, 1); -+ rk3308_codec_dac_lineout_disable(rk3308); -+ rk3308_codec_dac_hpout_enable(rk3308); -+ break; -+ case DAC_LINEOUT_HPOUT: -+ rk3308_speaker_ctl(rk3308, 1); -+ rk3308_headphone_ctl(rk3308, 1); -+ rk3308_codec_dac_lineout_enable(rk3308); -+ rk3308_codec_dac_hpout_enable(rk3308); -+ break; -+ default: -+ break; -+ } -+ } -+ -+ rk3308->dac_output = dac_output; -+out: -+ dev_dbg(rk3308->plat_dev, "switch dac_output to: %d\n", -+ rk3308->dac_output); -+ -+ return ret; -+} -+ -+static int rk3308_codec_dac_enable(struct rk3308_codec_priv *rk3308) -+{ -+ /* -+ * Note1. If the ACODEC_DAC_ANA_CON12[6] or ACODEC_DAC_ANA_CON12[2] -+ * is set to 0x1, ignoring the step9~12. -+ */ -+ -+ /* -+ * Note2. If the ACODEC_ DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3] -+ * is set to 0x1, the ADC0 or ADC1 should be enabled firstly, and -+ * please refer to Enable ADC Configuration Standard Usage Flow(expect -+ * step7~step9,step14). -+ */ -+ -+ /* -+ * Note3. If no opening the line out, ignoring the step6, step17 and -+ * step19. -+ */ -+ -+ /* -+ * Note4. If no opening the headphone out, ignoring the step3,step7~8, -+ * step16 and step18. -+ */ -+ -+ /* -+ * Note5. In the step18, adjust the register step by step to the -+ * appropriate value and taking 10ms as one time step -+ */ -+ -+ /* -+ * 1. Set the ACODEC_DAC_ANA_CON0[0] to 0x1, to enable the current -+ * source of DAC -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, -+ RK3308_DAC_CURRENT_MSK, -+ RK3308_DAC_CURRENT_EN); -+ -+ udelay(20); -+ -+ /* -+ * 2. Set the ACODEC_DAC_ANA_CON1[6] and ACODEC_DAC_ANA_CON1[2] to 0x1, -+ * to enable the reference voltage buffer -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, -+ RK3308_DAC_BUF_REF_L_MSK | -+ RK3308_DAC_BUF_REF_R_MSK, -+ RK3308_DAC_BUF_REF_L_EN | -+ RK3308_DAC_BUF_REF_R_EN); -+ -+ /* Waiting the stable reference voltage */ -+ mdelay(1); -+ -+ if (rk3308->dac_output == DAC_HPOUT || -+ rk3308->dac_output == DAC_LINEOUT_HPOUT) { -+ /* Step 03 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, -+ RK3308_DAC_HPOUT_POP_SOUND_L_MSK | -+ RK3308_DAC_HPOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_HPOUT_POP_SOUND_L_WORK | -+ RK3308_DAC_HPOUT_POP_SOUND_R_WORK); -+ -+ udelay(20); -+ } -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B && -+ (rk3308->dac_output == DAC_LINEOUT || -+ rk3308->dac_output == DAC_LINEOUT_HPOUT)) { -+ /* Step 04 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, -+ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK | -+ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_L_SEL_DC_FROM_INTERNAL | -+ RK3308_DAC_R_SEL_DC_FROM_INTERNAL); -+ -+ udelay(20); -+ } -+ -+ /* Step 05 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, -+ RK3308_DAC_L_HPMIX_EN | -+ RK3308_DAC_R_HPMIX_EN, -+ RK3308_DAC_L_HPMIX_EN | -+ RK3308_DAC_R_HPMIX_EN); -+ -+ /* Waiting the stable HPMIX */ -+ mdelay(1); -+ -+ /* Step 06. Reset HPMIX and recover HPMIX gains */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, -+ RK3308_DAC_L_HPMIX_WORK | -+ RK3308_DAC_R_HPMIX_WORK, -+ RK3308_DAC_L_HPMIX_INIT | -+ RK3308_DAC_R_HPMIX_INIT); -+ udelay(50); -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, -+ RK3308_DAC_L_HPMIX_WORK | -+ RK3308_DAC_R_HPMIX_WORK, -+ RK3308_DAC_L_HPMIX_WORK | -+ RK3308_DAC_R_HPMIX_WORK); -+ -+ udelay(20); -+ -+ if (rk3308->dac_output == DAC_LINEOUT || -+ rk3308->dac_output == DAC_LINEOUT_HPOUT) { -+ /* Step 07 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, -+ RK3308_DAC_L_LINEOUT_EN | -+ RK3308_DAC_R_LINEOUT_EN, -+ RK3308_DAC_L_LINEOUT_EN | -+ RK3308_DAC_R_LINEOUT_EN); -+ -+ udelay(20); -+ } -+ -+ if (rk3308->dac_output == DAC_HPOUT || -+ rk3308->dac_output == DAC_LINEOUT_HPOUT) { -+ /* Step 08 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_EN | -+ RK3308_DAC_R_HPOUT_EN, -+ RK3308_DAC_L_HPOUT_EN | -+ RK3308_DAC_R_HPOUT_EN); -+ -+ udelay(20); -+ -+ /* Step 09 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_WORK | -+ RK3308_DAC_R_HPOUT_WORK, -+ RK3308_DAC_L_HPOUT_WORK | -+ RK3308_DAC_R_HPOUT_WORK); -+ -+ udelay(20); -+ } -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* Step 10 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, -+ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK | -+ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL | -+ RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL); -+ -+ udelay(20); -+ } -+ -+ /* Step 11 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, -+ RK3308_DAC_L_REF_EN | -+ RK3308_DAC_R_REF_EN, -+ RK3308_DAC_L_REF_EN | -+ RK3308_DAC_R_REF_EN); -+ -+ udelay(20); -+ -+ /* Step 12 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, -+ RK3308_DAC_L_CLK_EN | -+ RK3308_DAC_R_CLK_EN, -+ RK3308_DAC_L_CLK_EN | -+ RK3308_DAC_R_CLK_EN); -+ -+ udelay(20); -+ -+ /* Step 13 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, -+ RK3308_DAC_L_DAC_EN | -+ RK3308_DAC_R_DAC_EN, -+ RK3308_DAC_L_DAC_EN | -+ RK3308_DAC_R_DAC_EN); -+ -+ udelay(20); -+ -+ /* Step 14 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, -+ RK3308_DAC_L_DAC_WORK | -+ RK3308_DAC_R_DAC_WORK, -+ RK3308_DAC_L_DAC_WORK | -+ RK3308_DAC_R_DAC_WORK); -+ -+ udelay(20); -+ -+ /* Step 15 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, -+ RK3308_DAC_L_HPMIX_SEL_MSK | -+ RK3308_DAC_R_HPMIX_SEL_MSK, -+ RK3308_DAC_L_HPMIX_I2S | -+ RK3308_DAC_R_HPMIX_I2S); -+ -+ udelay(20); -+ -+ /* Step 16 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, -+ RK3308_DAC_L_HPMIX_UNMUTE | -+ RK3308_DAC_R_HPMIX_UNMUTE, -+ RK3308_DAC_L_HPMIX_UNMUTE | -+ RK3308_DAC_R_HPMIX_UNMUTE); -+ -+ udelay(20); -+ -+ /* Step 17: Put configuration HPMIX Gain to DAPM */ -+ -+ if (rk3308->dac_output == DAC_HPOUT || -+ rk3308->dac_output == DAC_LINEOUT_HPOUT) { -+ /* Step 18 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_UNMUTE | -+ RK3308_DAC_R_HPOUT_UNMUTE, -+ RK3308_DAC_L_HPOUT_UNMUTE | -+ RK3308_DAC_R_HPOUT_UNMUTE); -+ -+ udelay(20); -+ } -+ -+ if (rk3308->dac_output == DAC_LINEOUT || -+ rk3308->dac_output == DAC_LINEOUT_HPOUT) { -+ /* Step 19 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, -+ RK3308_DAC_L_LINEOUT_UNMUTE | -+ RK3308_DAC_R_LINEOUT_UNMUTE, -+ RK3308_DAC_L_LINEOUT_UNMUTE | -+ RK3308_DAC_R_LINEOUT_UNMUTE); -+ udelay(20); -+ } -+ -+ /* Step 20, put configuration HPOUT gain to DAPM control */ -+ /* Step 21, put configuration LINEOUT gain to DAPM control */ -+ -+ if (rk3308->dac_output == DAC_HPOUT || -+ rk3308->dac_output == DAC_LINEOUT_HPOUT) { -+ /* Just for HPOUT */ -+ rk3308_codec_digital_fadein(rk3308); -+ } -+ -+ rk3308->dac_endisable = true; -+ -+ /* TODO: TRY TO TEST DRIVE STRENGTH */ -+ -+ return 0; -+} -+ -+static int rk3308_codec_dac_disable(struct rk3308_codec_priv *rk3308) -+{ -+ /* -+ * Step 00 skipped. Keep the DAC channel work and input the mute signal. -+ */ -+ -+ /* Step 01 skipped. May set the min gain for LINEOUT. */ -+ -+ /* Step 02 skipped. May set the min gain for HPOUT. */ -+ -+ if (rk3308->dac_output == DAC_HPOUT || -+ rk3308->dac_output == DAC_LINEOUT_HPOUT) { -+ /* Just for HPOUT */ -+ rk3308_codec_digital_fadeout(rk3308); -+ } -+ -+ /* Step 03 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, -+ RK3308_DAC_L_HPMIX_UNMUTE | -+ RK3308_DAC_R_HPMIX_UNMUTE, -+ RK3308_DAC_L_HPMIX_UNMUTE | -+ RK3308_DAC_R_HPMIX_UNMUTE); -+ -+ /* Step 04 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, -+ RK3308_DAC_L_HPMIX_SEL_MSK | -+ RK3308_DAC_R_HPMIX_SEL_MSK, -+ RK3308_DAC_L_HPMIX_NONE | -+ RK3308_DAC_R_HPMIX_NONE); -+ /* Step 05 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_UNMUTE | -+ RK3308_DAC_R_HPOUT_UNMUTE, -+ RK3308_DAC_L_HPOUT_MUTE | -+ RK3308_DAC_R_HPOUT_MUTE); -+ -+ /* Step 06 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, -+ RK3308_DAC_L_DAC_WORK | -+ RK3308_DAC_R_DAC_WORK, -+ RK3308_DAC_L_DAC_INIT | -+ RK3308_DAC_R_DAC_INIT); -+ -+ /* Step 07 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_EN | -+ RK3308_DAC_R_HPOUT_EN, -+ RK3308_DAC_L_HPOUT_DIS | -+ RK3308_DAC_R_HPOUT_DIS); -+ -+ /* Step 08 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, -+ RK3308_DAC_L_LINEOUT_UNMUTE | -+ RK3308_DAC_R_LINEOUT_UNMUTE, -+ RK3308_DAC_L_LINEOUT_MUTE | -+ RK3308_DAC_R_LINEOUT_MUTE); -+ -+ /* Step 09 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, -+ RK3308_DAC_L_LINEOUT_EN | -+ RK3308_DAC_R_LINEOUT_EN, -+ RK3308_DAC_L_LINEOUT_DIS | -+ RK3308_DAC_R_LINEOUT_DIS); -+ -+ /* Step 10 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, -+ RK3308_DAC_L_HPMIX_EN | -+ RK3308_DAC_R_HPMIX_EN, -+ RK3308_DAC_L_HPMIX_DIS | -+ RK3308_DAC_R_HPMIX_DIS); -+ -+ /* Step 11 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, -+ RK3308_DAC_L_DAC_EN | -+ RK3308_DAC_R_DAC_EN, -+ RK3308_DAC_L_DAC_DIS | -+ RK3308_DAC_R_DAC_DIS); -+ -+ /* Step 12 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, -+ RK3308_DAC_L_CLK_EN | -+ RK3308_DAC_R_CLK_EN, -+ RK3308_DAC_L_CLK_DIS | -+ RK3308_DAC_R_CLK_DIS); -+ -+ /* Step 13 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, -+ RK3308_DAC_L_REF_EN | -+ RK3308_DAC_R_REF_EN, -+ RK3308_DAC_L_REF_DIS | -+ RK3308_DAC_R_REF_DIS); -+ -+ /* Step 14 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, -+ RK3308_DAC_HPOUT_POP_SOUND_L_MSK | -+ RK3308_DAC_HPOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_HPOUT_POP_SOUND_L_INIT | -+ RK3308_DAC_HPOUT_POP_SOUND_R_INIT); -+ -+ /* Step 15 */ -+ if (rk3308->codec_ver == ACODEC_VERSION_B && -+ (rk3308->dac_output == DAC_LINEOUT || -+ rk3308->dac_output == DAC_LINEOUT_HPOUT)) { -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, -+ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK | -+ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_L_SEL_DC_FROM_VCM | -+ RK3308_DAC_R_SEL_DC_FROM_VCM); -+ } -+ -+ /* Step 16 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, -+ RK3308_DAC_BUF_REF_L_EN | -+ RK3308_DAC_BUF_REF_R_EN, -+ RK3308_DAC_BUF_REF_L_DIS | -+ RK3308_DAC_BUF_REF_R_DIS); -+ -+ /* Step 17 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, -+ RK3308_DAC_CURRENT_EN, -+ RK3308_DAC_CURRENT_DIS); -+ -+ /* Step 18 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, -+ RK3308_DAC_L_HPOUT_WORK | -+ RK3308_DAC_R_HPOUT_WORK, -+ RK3308_DAC_L_HPOUT_INIT | -+ RK3308_DAC_R_HPOUT_INIT); -+ -+ /* Step 19 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, -+ RK3308_DAC_L_HPMIX_WORK | -+ RK3308_DAC_R_HPMIX_WORK, -+ RK3308_DAC_L_HPMIX_WORK | -+ RK3308_DAC_R_HPMIX_WORK); -+ -+ /* Step 20 skipped, may set the min gain for HPOUT. */ -+ -+ /* -+ * Note2. If the ACODEC_DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3] -+ * is set to 0x1, add the steps from the section Disable ADC -+ * Configuration Standard Usage Flow after complete the step 19 -+ * -+ * IF USING LINE-IN -+ * rk3308_codec_adc_ana_disable(rk3308, type); -+ */ -+ -+ rk3308->dac_endisable = false; -+ -+ return 0; -+} -+ -+static int rk3308_codec_power_on(struct rk3308_codec_priv *rk3308) -+{ -+ unsigned int v; -+ -+ /* 0. Supply the power of digital part and reset the Audio Codec */ -+ /* Do nothing */ -+ -+ /* -+ * 1. Configure ACODEC_DAC_ANA_CON1[1:0] and ACODEC_DAC_ANA_CON1[5:4] -+ * to 0x1, to setup dc voltage of the DAC channel output. -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, -+ RK3308_DAC_HPOUT_POP_SOUND_L_MSK, -+ RK3308_DAC_HPOUT_POP_SOUND_L_INIT); -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, -+ RK3308_DAC_HPOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_HPOUT_POP_SOUND_R_INIT); -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* -+ * 2. Configure ACODEC_DAC_ANA_CON15[1:0] and -+ * ACODEC_DAC_ANA_CON15[5:4] to 0x1, to setup dc voltage of -+ * the DAC channel output. -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, -+ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK, -+ RK3308_DAC_L_SEL_DC_FROM_VCM); -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, -+ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, -+ RK3308_DAC_R_SEL_DC_FROM_VCM); -+ } -+ -+ /* -+ * 3. Configure the register ACODEC_ADC_ANA_CON10[3:0] to 7’b000_0001. -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -+ RK3308_ADC_CURRENT_CHARGE_MSK, -+ RK3308_ADC_SEL_I(0x1)); -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* -+ * 4. Configure the register ACODEC_ADC_ANA_CON14[3:0] to -+ * 4’b0001. -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, -+ RK3308_DAC_CURRENT_CHARGE_MSK, -+ RK3308_DAC_SEL_I(0x1)); -+ } -+ -+ /* 5. Supply the power of the analog part(AVDD,AVDDRV) */ -+ -+ /* -+ * 6. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x1 to setup -+ * reference voltage -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -+ RK3308_ADC_REF_EN, RK3308_ADC_REF_EN); -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* -+ * 7. Configure the register ACODEC_ADC_ANA_CON14[4] to 0x1 to -+ * setup reference voltage -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, -+ RK3308_DAC_VCM_LINEOUT_EN, -+ RK3308_DAC_VCM_LINEOUT_EN); -+ } -+ -+ /* -+ * 8. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to -+ * 0x7f step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to -+ * 0x7f directly. Here the slot time of the step is 200us. -+ */ -+ for (v = 0x1; v <= 0x7f; v++) { -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -+ RK3308_ADC_CURRENT_CHARGE_MSK, -+ v); -+ udelay(200); -+ } -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* -+ * 9. Change the register ACODEC_ADC_ANA_CON14[3:0] from the 0x1 -+ * to 0xf step by step or configure the -+ * ACODEC_ADC_ANA_CON14[3:0] to 0xf directly. Here the slot -+ * time of the step is 200us. -+ */ -+ for (v = 0x1; v <= 0xf; v++) { -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, -+ RK3308_DAC_CURRENT_CHARGE_MSK, -+ v); -+ udelay(200); -+ } -+ } -+ -+ /* 10. Wait until the voltage of VCM keeps stable at the AVDD/2 */ -+ msleep(20); /* estimated value */ -+ -+ /* -+ * 11. Configure the register ACODEC_ADC_ANA_CON10[6:0] to the -+ * appropriate value(expect 0x0) for reducing power. -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -+ RK3308_ADC_CURRENT_CHARGE_MSK, 0x7c); -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* -+ * 12. Configure the register ACODEC_DAC_ANA_CON14[6:0] to the -+ * appropriate value(expect 0x0) for reducing power. -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, -+ RK3308_DAC_CURRENT_CHARGE_MSK, 0xf); -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_power_off(struct rk3308_codec_priv *rk3308) -+{ -+ unsigned int v; -+ -+ /* -+ * 0. Keep the power on and disable the DAC and ADC path according to -+ * the section power on configuration standard usage flow. -+ */ -+ -+ /* -+ * 1. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 7’b000_0001. -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -+ RK3308_ADC_CURRENT_CHARGE_MSK, -+ RK3308_ADC_SEL_I(0x1)); -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* -+ * 2. Configure the register ACODEC_DAC_ANA_CON14[3:0] to -+ * 4’b0001. -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, -+ RK3308_DAC_CURRENT_CHARGE_MSK, -+ RK3308_DAC_SEL_I(0x1)); -+ } -+ -+ /* 3. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x0 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -+ RK3308_ADC_REF_EN, -+ RK3308_ADC_REF_DIS); -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* 4. Configure the register ACODEC_DAC_ANA_CON14[7] to 0x0 */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, -+ RK3308_DAC_VCM_LINEOUT_EN, -+ RK3308_DAC_VCM_LINEOUT_DIS); -+ } -+ -+ /* -+ * 5. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to 0x7f -+ * step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to 0x7f -+ * directly. Here the slot time of the step is 200us. -+ */ -+ for (v = 0x1; v <= 0x7f; v++) { -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -+ RK3308_ADC_CURRENT_CHARGE_MSK, -+ v); -+ udelay(200); -+ } -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* -+ * 6. Change the register ACODEC_DAC_ANA_CON14[3:0] from the 0x1 -+ * to 0xf step by step or configure the -+ * ACODEC_DAC_ANA_CON14[3:0] to 0xf directly. Here the slot -+ * time of the step is 200us. -+ */ -+ for (v = 0x1; v <= 0x7f; v++) { -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_ANA_CON10(0), -+ RK3308_ADC_CURRENT_CHARGE_MSK, -+ v); -+ udelay(200); -+ } -+ } -+ -+ /* 7. Wait until the voltage of VCM keeps stable at the AGND */ -+ msleep(20); /* estimated value */ -+ -+ /* 8. Power off the analog power supply */ -+ /* 9. Power off the digital power supply */ -+ -+ /* Do something via hardware */ -+ -+ return 0; -+} -+ -+static int rk3308_codec_headset_detect_enable(struct rk3308_codec_priv *rk3308) -+{ -+ /* -+ * Set ACODEC_DAC_ANA_CON0[1] to 0x1, to enable the headset insert -+ * detection -+ * -+ * Note. When the voltage of PAD HPDET> 8*AVDD/9, the output value of -+ * the pin_hpdet will be set to 0x1 and assert a interrupt -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, -+ RK3308_DAC_HEADPHONE_DET_MSK, -+ RK3308_DAC_HEADPHONE_DET_EN); -+ -+ return 0; -+} -+ -+static int rk3308_codec_headset_detect_disable(struct rk3308_codec_priv *rk3308) -+{ -+ /* -+ * Set ACODEC_DAC_ANA_CON0[1] to 0x0, to disable the headset insert -+ * detection -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, -+ RK3308_DAC_HEADPHONE_DET_MSK, -+ RK3308_DAC_HEADPHONE_DET_DIS); -+ -+ return 0; -+} -+ -+static int rk3308_codec_check_i2s_sdis(struct rk3308_codec_priv *rk3308, -+ int num) -+{ -+ int i, j, ret = 0; -+ -+ switch (num) { -+ case 1: -+ rk3308->which_i2s = ACODEC_TO_I2S1_2CH; -+ break; -+ case 2: -+ rk3308->which_i2s = ACODEC_TO_I2S3_4CH; -+ break; -+ case 4: -+ rk3308->which_i2s = ACODEC_TO_I2S2_8CH; -+ break; -+ default: -+ dev_err(rk3308->plat_dev, "Invalid i2s sdis num: %d\n", num); -+ ret = -EINVAL; -+ goto err; -+ } -+ -+ for (i = 0; i < num; i++) { -+ if (rk3308->i2s_sdis[i] > ADC_LR_GROUP_MAX - 1) { -+ dev_err(rk3308->plat_dev, -+ "i2s_sdis[%d]: %d is overflow\n", -+ i, rk3308->i2s_sdis[i]); -+ ret = -EINVAL; -+ goto err; -+ } -+ -+ for (j = 0; j < num; j++) { -+ if (i == j) -+ continue; -+ -+ if (rk3308->i2s_sdis[i] == rk3308->i2s_sdis[j]) { -+ dev_err(rk3308->plat_dev, -+ "Invalid i2s_sdis: [%d]%d == [%d]%d\n", -+ i, rk3308->i2s_sdis[i], -+ j, rk3308->i2s_sdis[j]); -+ ret = -EINVAL; -+ goto err; -+ } -+ } -+ } -+ -+err: -+ return ret; -+} -+ -+static int rk3308_codec_adc_grps_route_config(struct rk3308_codec_priv *rk3308) -+{ -+ int idx = 0; -+ -+ if (rk3308->which_i2s == ACODEC_TO_I2S2_8CH) { -+ for (idx = 0; idx < rk3308->to_i2s_grps; idx++) { -+ regmap_write(rk3308->grf, GRF_SOC_CON1, -+ GRF_I2S2_8CH_SDI(idx, rk3308->i2s_sdis[idx])); -+ } -+ } else if (rk3308->which_i2s == ACODEC_TO_I2S3_4CH) { -+ for (idx = 0; idx < rk3308->to_i2s_grps; idx++) { -+ regmap_write(rk3308->grf, GRF_SOC_CON1, -+ GRF_I2S3_4CH_SDI(idx, rk3308->i2s_sdis[idx])); -+ } -+ } else if (rk3308->which_i2s == ACODEC_TO_I2S1_2CH) { -+ regmap_write(rk3308->grf, GRF_SOC_CON1, -+ GRF_I2S1_2CH_SDI(rk3308->i2s_sdis[idx])); -+ } -+ -+ return 0; -+} -+ -+/* Put default one-to-one mapping */ -+static int rk3308_codec_adc_grps_route_default(struct rk3308_codec_priv *rk3308) -+{ -+ unsigned int idx; -+ -+ /* -+ * The GRF values may be kept the previous status after hot reboot, -+ * if the property 'rockchip,adc-grps-route' is not set, we need to -+ * recover default the order of sdi/sdo for i2s2_8ch/i2s3_8ch/i2s1_2ch. -+ */ -+ regmap_write(rk3308->grf, GRF_SOC_CON1, -+ GRF_I2S1_2CH_SDI(0)); -+ -+ for (idx = 0; idx < 2; idx++) { -+ regmap_write(rk3308->grf, GRF_SOC_CON1, -+ GRF_I2S3_4CH_SDI(idx, idx)); -+ } -+ -+ /* Using i2s2_8ch by default. */ -+ rk3308->which_i2s = ACODEC_TO_I2S2_8CH; -+ rk3308->to_i2s_grps = ADC_LR_GROUP_MAX; -+ -+ for (idx = 0; idx < ADC_LR_GROUP_MAX; idx++) { -+ rk3308->i2s_sdis[idx] = idx; -+ regmap_write(rk3308->grf, GRF_SOC_CON1, -+ GRF_I2S2_8CH_SDI(idx, idx)); -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_adc_grps_route(struct rk3308_codec_priv *rk3308, -+ struct device_node *np) -+{ -+ int num, ret; -+ -+ num = of_count_phandle_with_args(np, "rockchip,adc-grps-route", NULL); -+ if (num < 0) { -+ if (num == -ENOENT) { -+ /* Not use 'rockchip,adc-grps-route' property here */ -+ rk3308_codec_adc_grps_route_default(rk3308); -+ ret = 0; -+ } else { -+ dev_err(rk3308->plat_dev, -+ "Failed to read 'rockchip,adc-grps-route' num: %d\n", -+ num); -+ ret = num; -+ } -+ return ret; -+ } -+ -+ ret = of_property_read_u32_array(np, "rockchip,adc-grps-route", -+ rk3308->i2s_sdis, num); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, -+ "Failed to read 'rockchip,adc-grps-route': %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = rk3308_codec_check_i2s_sdis(rk3308, num); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, -+ "Failed to check i2s_sdis: %d\n", ret); -+ return ret; -+ } -+ -+ rk3308->to_i2s_grps = num; -+ -+ rk3308_codec_adc_grps_route_config(rk3308); -+ -+ return 0; -+} -+ -+static int check_micbias(int micbias) -+{ -+ switch (micbias) { -+ case RK3308_ADC_MICBIAS_VOLT_0_85: -+ case RK3308_ADC_MICBIAS_VOLT_0_8: -+ case RK3308_ADC_MICBIAS_VOLT_0_75: -+ case RK3308_ADC_MICBIAS_VOLT_0_7: -+ case RK3308_ADC_MICBIAS_VOLT_0_65: -+ case RK3308_ADC_MICBIAS_VOLT_0_6: -+ case RK3308_ADC_MICBIAS_VOLT_0_55: -+ case RK3308_ADC_MICBIAS_VOLT_0_5: -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+ -+static bool handle_loopback(struct rk3308_codec_priv *rk3308) -+{ -+ /* The version B doesn't need to handle loopback. */ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) -+ return false; -+ -+ switch (rk3308->loopback_grp) { -+ case 0: -+ case 1: -+ case 2: -+ case 3: -+ return true; -+ } -+ -+ return false; -+} -+ -+static bool has_en_always_grps(struct rk3308_codec_priv *rk3308) -+{ -+ int idx; -+ -+ if (rk3308->en_always_grps_num) { -+ for (idx = 0; idx < ADC_LR_GROUP_MAX; idx++) { -+ if (rk3308->en_always_grps[idx] >= 0 && -+ rk3308->en_always_grps[idx] <= ADC_LR_GROUP_MAX - 1) -+ return true; -+ } -+ } -+ -+ return false; -+} -+ -+static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308, -+ int micbias) -+{ -+ int ret; -+ -+ if (rk3308->ext_micbias != EXT_MICBIAS_NONE) -+ return 0; -+ -+ /* 0. Power up the ACODEC and keep the AVDDH stable */ -+ -+ /* Step 1. Configure ACODEC_ADC_ANA_CON7[2:0] to the certain value */ -+ ret = check_micbias(micbias); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, "This is an invalid micbias: %d\n", -+ micbias); -+ return ret; -+ } -+ -+ /* -+ * Note: Only the reg (ADC_ANA_CON7+0x0)[2:0] represent the level range -+ * control signal of MICBIAS voltage -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0), -+ RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK, -+ micbias); -+ -+ /* Step 2. Wait until the VCMH keep stable */ -+ msleep(20); /* estimated value */ -+ -+ /* -+ * Step 3. Configure ACODEC_ADC_ANA_CON8[4] to 0x1 -+ * -+ * Note: Only the reg (ADC_ANA_CON8+0x0)[4] represent the enable -+ * signal of current source for MICBIAS -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(0), -+ RK3308_ADC_MICBIAS_CURRENT_MSK, -+ RK3308_ADC_MICBIAS_CURRENT_EN); -+ -+ /* -+ * Step 4. Configure the (ADC_ANA_CON7+0x40)[3] or -+ * (ADC_ANA_CON7+0x80)[3] to 0x1. -+ * -+ * (ADC_ANA_CON7+0x40)[3] used to control the MICBIAS1, and -+ * (ADC_ANA_CON7+0x80)[3] used to control the MICBIAS2 -+ */ -+ if (rk3308->micbias1) -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(1), -+ RK3308_ADC_MIC_BIAS_BUF_EN, -+ RK3308_ADC_MIC_BIAS_BUF_EN); -+ -+ if (rk3308->micbias2) -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(2), -+ RK3308_ADC_MIC_BIAS_BUF_EN, -+ RK3308_ADC_MIC_BIAS_BUF_EN); -+ -+ /* waiting micbias stabled*/ -+ mdelay(50); -+ -+ rk3308->enable_micbias = true; -+ -+ return 0; -+} -+ -+static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308) -+{ -+ if (rk3308->ext_micbias != EXT_MICBIAS_NONE) -+ return 0; -+ -+ /* Step 0. Enable the MICBIAS and keep the Audio Codec stable */ -+ /* Do nothing */ -+ -+ /* -+ * Step 1. Configure the (ADC_ANA_CON7+0x40)[3] or -+ * (ADC_ANA_CON7+0x80)[3] to 0x0 -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(1), -+ RK3308_ADC_MIC_BIAS_BUF_EN, -+ RK3308_ADC_MIC_BIAS_BUF_DIS); -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(2), -+ RK3308_ADC_MIC_BIAS_BUF_EN, -+ RK3308_ADC_MIC_BIAS_BUF_DIS); -+ -+ /* -+ * Step 2. Configure ACODEC_ADC_ANA_CON8[4] to 0x0 -+ * -+ * Note: Only the reg (ADC_ANA_CON8+0x0)[4] represent the enable -+ * signal of current source for MICBIAS -+ */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(0), -+ RK3308_ADC_MICBIAS_CURRENT_MSK, -+ RK3308_ADC_MICBIAS_CURRENT_DIS); -+ -+ rk3308->enable_micbias = false; -+ -+ return 0; -+} -+ -+static int rk3308_codec_adc_reinit_mics(struct rk3308_codec_priv *rk3308, -+ int type) -+{ -+ int idx, grp; -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 1 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), -+ RK3308_ADC_CH1_ADC_WORK | -+ RK3308_ADC_CH2_ADC_WORK, -+ RK3308_ADC_CH1_ADC_INIT | -+ RK3308_ADC_CH2_ADC_INIT); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 2 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), -+ RK3308_ADC_CH1_ALC_WORK | -+ RK3308_ADC_CH2_ALC_WORK, -+ RK3308_ADC_CH1_ALC_INIT | -+ RK3308_ADC_CH2_ALC_INIT); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 3 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), -+ RK3308_ADC_CH1_MIC_WORK | -+ RK3308_ADC_CH2_MIC_WORK, -+ RK3308_ADC_CH1_MIC_INIT | -+ RK3308_ADC_CH2_MIC_INIT); -+ } -+ -+ usleep_range(200, 250); /* estimated value */ -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 1 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), -+ RK3308_ADC_CH1_ADC_WORK | -+ RK3308_ADC_CH2_ADC_WORK, -+ RK3308_ADC_CH1_ADC_WORK | -+ RK3308_ADC_CH2_ADC_WORK); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 2 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), -+ RK3308_ADC_CH1_ALC_WORK | -+ RK3308_ADC_CH2_ALC_WORK, -+ RK3308_ADC_CH1_ALC_WORK | -+ RK3308_ADC_CH2_ALC_WORK); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 3 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), -+ RK3308_ADC_CH1_MIC_WORK | -+ RK3308_ADC_CH2_MIC_WORK, -+ RK3308_ADC_CH1_MIC_WORK | -+ RK3308_ADC_CH2_MIC_WORK); -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_adc_ana_enable(struct rk3308_codec_priv *rk3308, -+ int type) -+{ -+ unsigned int agc_func_en; -+ int idx, grp; -+ -+ /* -+ * 1. Set the ACODEC_ADC_ANA_CON7[7:6] and ACODEC_ADC_ANA_CON7[5:4], -+ * to select the line-in or microphone as input of ADC -+ * -+ * Note1. Please ignore the step1 for enabling ADC3, ADC4, ADC5, -+ * ADC6, ADC7, and ADC8 -+ */ -+ if (rk3308->adc_grp0_using_linein) { -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0), -+ RK3308_ADC_CH1_IN_SEL_MSK | -+ RK3308_ADC_CH2_IN_SEL_MSK, -+ RK3308_ADC_CH1_IN_LINEIN | -+ RK3308_ADC_CH2_IN_LINEIN); -+ -+ /* Keep other ADCs as MIC-IN */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ /* The groups without line-in are >= 1 */ -+ if (grp < 1 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_ANA_CON07(grp), -+ RK3308_ADC_CH1_IN_SEL_MSK | -+ RK3308_ADC_CH2_IN_SEL_MSK, -+ RK3308_ADC_CH1_IN_MIC | -+ RK3308_ADC_CH2_IN_MIC); -+ } -+ } else { -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_ANA_CON07(grp), -+ RK3308_ADC_CH1_IN_SEL_MSK | -+ RK3308_ADC_CH2_IN_SEL_MSK, -+ RK3308_ADC_CH1_IN_MIC | -+ RK3308_ADC_CH2_IN_MIC); -+ } -+ } -+ -+ /* -+ * 2. Set ACODEC_ADC_ANA_CON0[7] and [3] to 0x1, to end the mute station -+ * of ADC, to enable the MIC module, to enable the reference voltage -+ * buffer, and to end the initialization of MIC -+ */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), -+ RK3308_ADC_CH1_MIC_UNMUTE | -+ RK3308_ADC_CH2_MIC_UNMUTE, -+ RK3308_ADC_CH1_MIC_UNMUTE | -+ RK3308_ADC_CH2_MIC_UNMUTE); -+ } -+ -+ /* -+ * 3. Set ACODEC_ADC_ANA_CON6[0] to 0x1, to enable the current source -+ * of audio -+ */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(grp), -+ RK3308_ADC_CURRENT_MSK, -+ RK3308_ADC_CURRENT_EN); -+ } -+ -+ /* -+ * This is mainly used for BIST mode that wait ADCs are stable. -+ * -+ * By tested results, the type delay is >40us, but we need to leave -+ * enough delay margin. -+ */ -+ usleep_range(400, 500); -+ -+ /* vendor step 4*/ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), -+ RK3308_ADC_CH1_BUF_REF_EN | -+ RK3308_ADC_CH2_BUF_REF_EN, -+ RK3308_ADC_CH1_BUF_REF_EN | -+ RK3308_ADC_CH2_BUF_REF_EN); -+ } -+ -+ /* vendor step 5 */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), -+ RK3308_ADC_CH1_MIC_EN | -+ RK3308_ADC_CH2_MIC_EN, -+ RK3308_ADC_CH1_MIC_EN | -+ RK3308_ADC_CH2_MIC_EN); -+ } -+ -+ /* vendor step 6 */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), -+ RK3308_ADC_CH1_ALC_EN | -+ RK3308_ADC_CH2_ALC_EN, -+ RK3308_ADC_CH1_ALC_EN | -+ RK3308_ADC_CH2_ALC_EN); -+ } -+ -+ /* vendor step 7 */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), -+ RK3308_ADC_CH1_CLK_EN | -+ RK3308_ADC_CH2_CLK_EN, -+ RK3308_ADC_CH1_CLK_EN | -+ RK3308_ADC_CH2_CLK_EN); -+ } -+ -+ /* vendor step 8 */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), -+ RK3308_ADC_CH1_ADC_EN | -+ RK3308_ADC_CH2_ADC_EN, -+ RK3308_ADC_CH1_ADC_EN | -+ RK3308_ADC_CH2_ADC_EN); -+ } -+ -+ /* vendor step 9 */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), -+ RK3308_ADC_CH1_ADC_WORK | -+ RK3308_ADC_CH2_ADC_WORK, -+ RK3308_ADC_CH1_ADC_WORK | -+ RK3308_ADC_CH2_ADC_WORK); -+ } -+ -+ /* vendor step 10 */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), -+ RK3308_ADC_CH1_ALC_WORK | -+ RK3308_ADC_CH2_ALC_WORK, -+ RK3308_ADC_CH1_ALC_WORK | -+ RK3308_ADC_CH2_ALC_WORK); -+ } -+ -+ /* vendor step 11 */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), -+ RK3308_ADC_CH1_MIC_WORK | -+ RK3308_ADC_CH2_MIC_WORK, -+ RK3308_ADC_CH1_MIC_WORK | -+ RK3308_ADC_CH2_MIC_WORK); -+ } -+ -+ /* vendor step 12 */ -+ -+ /* vendor step 13 */ -+ -+ /* vendor step 14 */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp), -+ &agc_func_en); -+ if (rk3308->adc_zerocross || -+ agc_func_en & RK3308_AGC_FUNC_SEL_EN) { -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_ANA_CON02(grp), -+ RK3308_ADC_CH1_ZEROCROSS_DET_EN, -+ RK3308_ADC_CH1_ZEROCROSS_DET_EN); -+ } -+ regmap_read(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp), -+ &agc_func_en); -+ if (rk3308->adc_zerocross || -+ agc_func_en & RK3308_AGC_FUNC_SEL_EN) { -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_ANA_CON02(grp), -+ RK3308_ADC_CH2_ZEROCROSS_DET_EN, -+ RK3308_ADC_CH2_ZEROCROSS_DET_EN); -+ } -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ rk3308->adc_grps_endisable[grp] = true; -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_adc_ana_disable(struct rk3308_codec_priv *rk3308, -+ int type) -+{ -+ int idx, grp; -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 1 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), -+ RK3308_ADC_CH1_ZEROCROSS_DET_EN | -+ RK3308_ADC_CH2_ZEROCROSS_DET_EN, -+ RK3308_ADC_CH1_ZEROCROSS_DET_DIS | -+ RK3308_ADC_CH2_ZEROCROSS_DET_DIS); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 2 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), -+ RK3308_ADC_CH1_ADC_EN | -+ RK3308_ADC_CH2_ADC_EN, -+ RK3308_ADC_CH1_ADC_DIS | -+ RK3308_ADC_CH2_ADC_DIS); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 3 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), -+ RK3308_ADC_CH1_CLK_EN | -+ RK3308_ADC_CH2_CLK_EN, -+ RK3308_ADC_CH1_CLK_DIS | -+ RK3308_ADC_CH2_CLK_DIS); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 4 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), -+ RK3308_ADC_CH1_ALC_EN | -+ RK3308_ADC_CH2_ALC_EN, -+ RK3308_ADC_CH1_ALC_DIS | -+ RK3308_ADC_CH2_ALC_DIS); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 5 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), -+ RK3308_ADC_CH1_MIC_EN | -+ RK3308_ADC_CH2_MIC_EN, -+ RK3308_ADC_CH1_MIC_DIS | -+ RK3308_ADC_CH2_MIC_DIS); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 6 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), -+ RK3308_ADC_CH1_BUF_REF_EN | -+ RK3308_ADC_CH2_BUF_REF_EN, -+ RK3308_ADC_CH1_BUF_REF_DIS | -+ RK3308_ADC_CH2_BUF_REF_DIS); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 7 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(grp), -+ RK3308_ADC_CURRENT_MSK, -+ RK3308_ADC_CURRENT_DIS); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 8 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), -+ RK3308_ADC_CH1_ADC_WORK | -+ RK3308_ADC_CH2_ADC_WORK, -+ RK3308_ADC_CH1_ADC_INIT | -+ RK3308_ADC_CH2_ADC_INIT); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 9 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), -+ RK3308_ADC_CH1_ALC_WORK | -+ RK3308_ADC_CH2_ALC_WORK, -+ RK3308_ADC_CH1_ALC_INIT | -+ RK3308_ADC_CH2_ALC_INIT); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ /* vendor step 10 */ -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), -+ RK3308_ADC_CH1_MIC_WORK | -+ RK3308_ADC_CH2_MIC_WORK, -+ RK3308_ADC_CH1_MIC_INIT | -+ RK3308_ADC_CH2_MIC_INIT); -+ } -+ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ rk3308->adc_grps_endisable[grp] = false; -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_open_capture(struct rk3308_codec_priv *rk3308) -+{ -+ int idx, grp = 0; -+ int type = ADC_TYPE_NORMAL; -+ -+ rk3308_codec_adc_ana_enable(rk3308, type); -+ rk3308_codec_adc_reinit_mics(rk3308, type); -+ -+ if (rk3308->adc_grp0_using_linein) { -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(0), -+ RK3308_ADC_L_CH_BIST_MSK, -+ RK3308_ADC_L_CH_NORMAL_RIGHT); -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(0), -+ RK3308_ADC_R_CH_BIST_MSK, -+ RK3308_ADC_R_CH_NORMAL_LEFT); -+ } else { -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (handle_loopback(rk3308) && -+ idx == rk3308->loopback_grp && -+ grp == ADC_GRP_SKIP_MAGIC) { -+ /* -+ * Switch to dummy BIST mode (BIST keep reset -+ * now) to keep the zero input data in I2S bus. -+ * -+ * It may cause the glitch if we hold the ADC -+ * digtital i2s module in codec. -+ * -+ * Then, the grp which is set from loopback_grp. -+ */ -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(rk3308->loopback_grp), -+ RK3308_ADC_L_CH_BIST_MSK, -+ RK3308_ADC_L_CH_BIST_SINE); -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(rk3308->loopback_grp), -+ RK3308_ADC_R_CH_BIST_MSK, -+ RK3308_ADC_R_CH_BIST_SINE); -+ } else { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_L_CH_BIST_MSK, -+ RK3308_ADC_L_CH_NORMAL_LEFT); -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_R_CH_BIST_MSK, -+ RK3308_ADC_R_CH_NORMAL_RIGHT); -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+static void rk3308_codec_adc_mclk_disable(struct rk3308_codec_priv *rk3308) -+{ -+ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_ADC_MCLK_MSK, -+ RK3308_ADC_MCLK_DIS); -+} -+ -+static void rk3308_codec_adc_mclk_enable(struct rk3308_codec_priv *rk3308) -+{ -+ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_ADC_MCLK_MSK, -+ RK3308_ADC_MCLK_EN); -+ udelay(20); -+} -+ -+static void rk3308_codec_dac_mclk_disable(struct rk3308_codec_priv *rk3308) -+{ -+ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_DAC_MCLK_MSK, -+ RK3308_DAC_MCLK_DIS); -+} -+ -+static void rk3308_codec_dac_mclk_enable(struct rk3308_codec_priv *rk3308) -+{ -+ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, -+ RK3308_DAC_MCLK_MSK, -+ RK3308_DAC_MCLK_EN); -+ udelay(20); -+} -+ -+static int rk3308_codec_open_dbg_capture(struct rk3308_codec_priv *rk3308) -+{ -+ rk3308_codec_adc_ana_enable(rk3308, ADC_TYPE_DBG); -+ -+ return 0; -+} -+ -+static int rk3308_codec_close_dbg_capture(struct rk3308_codec_priv *rk3308) -+{ -+ rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_DBG); -+ -+ return 0; -+} -+ -+static int rk3308_codec_close_all_capture(struct rk3308_codec_priv *rk3308) -+{ -+ rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_ALL); -+ -+ return 0; -+} -+ -+static int rk3308_codec_close_capture(struct rk3308_codec_priv *rk3308) -+{ -+ rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_NORMAL); -+ -+ return 0; -+} -+ -+static int rk3308_codec_open_playback(struct rk3308_codec_priv *rk3308) -+{ -+ rk3308_codec_dac_enable(rk3308); -+ -+ return 0; -+} -+ -+static int rk3308_codec_close_playback(struct rk3308_codec_priv *rk3308) -+{ -+ rk3308_codec_dac_disable(rk3308); -+ -+ return 0; -+} -+ -+static int rk3308_codec_llp_down(struct rk3308_codec_priv *rk3308) -+{ -+ rk3308_codec_adc_mclk_disable(rk3308); -+ rk3308_codec_dac_mclk_disable(rk3308); -+ -+ return 0; -+} -+ -+static int rk3308_codec_llp_up(struct rk3308_codec_priv *rk3308) -+{ -+ rk3308_codec_adc_mclk_enable(rk3308); -+ rk3308_codec_dac_mclk_enable(rk3308); -+ -+ return 0; -+} -+ -+static int rk3308_codec_dlp_down(struct rk3308_codec_priv *rk3308) -+{ -+ rk3308_codec_micbias_disable(rk3308); -+ rk3308_codec_power_off(rk3308); -+ -+ return 0; -+} -+ -+static int rk3308_codec_dlp_up(struct rk3308_codec_priv *rk3308) -+{ -+ rk3308_codec_power_on(rk3308); -+ rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt); -+ -+ return 0; -+} -+ -+/* Just used for debug and trace power state */ -+static void rk3308_codec_set_pm_state(struct rk3308_codec_priv *rk3308, -+ int pm_state) -+{ -+ int ret; -+ -+ switch (pm_state) { -+ case PM_LLP_DOWN: -+ rk3308_codec_llp_down(rk3308); -+ break; -+ case PM_LLP_UP: -+ rk3308_codec_llp_up(rk3308); -+ break; -+ case PM_DLP_DOWN: -+ rk3308_codec_dlp_down(rk3308); -+ break; -+ case PM_DLP_UP: -+ rk3308_codec_dlp_up(rk3308); -+ break; -+ case PM_DLP_DOWN2: -+ clk_disable_unprepare(rk3308->mclk_rx); -+ clk_disable_unprepare(rk3308->mclk_tx); -+ clk_disable_unprepare(rk3308->pclk); -+ break; -+ case PM_DLP_UP2: -+ ret = clk_prepare_enable(rk3308->pclk); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, -+ "Failed to enable acodec pclk: %d\n", ret); -+ goto err; -+ } -+ -+ ret = clk_prepare_enable(rk3308->mclk_rx); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, -+ "Failed to enable i2s mclk_rx: %d\n", ret); -+ goto err; -+ } -+ -+ ret = clk_prepare_enable(rk3308->mclk_tx); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, -+ "Failed to enable i2s mclk_tx: %d\n", ret); -+ goto err; -+ } -+ break; -+ default: -+ dev_err(rk3308->plat_dev, "Invalid pm_state: %d\n", pm_state); -+ goto err; -+ } -+ -+ rk3308->pm_state = pm_state; -+ -+err: -+ return; -+} -+ -+static void rk3308_codec_update_adcs_status(struct rk3308_codec_priv *rk3308, -+ int state) -+{ -+ int idx, grp; -+ -+ /* Update skip_grps flags if the ADCs need to be enabled always. */ -+ if (state == PATH_BUSY) { -+ for (idx = 0; idx < rk3308->used_adc_grps; idx++) { -+ u32 mapped_grp = to_mapped_grp(rk3308, idx); -+ -+ for (grp = 0; grp < rk3308->en_always_grps_num; grp++) { -+ u32 en_always_grp = rk3308->en_always_grps[grp]; -+ -+ if (mapped_grp == en_always_grp) -+ rk3308->skip_grps[en_always_grp] = 1; -+ } -+ } -+ } -+} -+ -+static int rk3308_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params, -+ struct snd_soc_dai *dai) -+{ -+ struct snd_soc_component *component = dai->component; -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ struct snd_pcm_str *playback_str = -+ &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK]; -+ int type = ADC_TYPE_LOOPBACK; -+ int idx, grp; -+ int ret; -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { -+ /* DAC only supports 2 channels */ -+ rk3308_codec_dac_mclk_enable(rk3308); -+ rk3308_codec_open_playback(rk3308); -+ rk3308_codec_dac_dig_config(rk3308, params); -+ rk3308_codec_set_dac_path_state(rk3308, PATH_BUSY); -+ } else { -+ if (rk3308->micbias_num && -+ !rk3308->enable_micbias) -+ rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt); -+ -+ rk3308_codec_adc_mclk_enable(rk3308); -+ ret = rk3308_codec_update_adc_grps(rk3308, params); -+ if (ret < 0) -+ return ret; -+ -+ if (handle_loopback(rk3308)) { -+ if (rk3308->micbias_num && -+ (params_channels(params) == 2) && -+ to_mapped_grp(rk3308, 0) == rk3308->loopback_grp) -+ rk3308_codec_micbias_disable(rk3308); -+ -+ /* Check the DACs are opened */ -+ if (playback_str->substream_opened) { -+ rk3308->loopback_dacs_enabled = true; -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_L_CH_BIST_MSK, -+ RK3308_ADC_L_CH_NORMAL_LEFT); -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_R_CH_BIST_MSK, -+ RK3308_ADC_R_CH_NORMAL_RIGHT); -+ } -+ } else { -+ rk3308->loopback_dacs_enabled = false; -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_L_CH_BIST_MSK, -+ RK3308_ADC_L_CH_BIST_SINE); -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_R_CH_BIST_MSK, -+ RK3308_ADC_R_CH_BIST_SINE); -+ } -+ } -+ } -+ -+ rk3308_codec_open_capture(rk3308); -+ rk3308_codec_adc_dig_config(rk3308, params); -+ rk3308_codec_update_adcs_status(rk3308, PATH_BUSY); -+ } -+ -+ return 0; -+} -+ -+static int rk3308_pcm_trigger(struct snd_pcm_substream *substream, -+ int cmd, struct snd_soc_dai *dai) -+{ -+ struct snd_soc_component *component = dai->component; -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ int type = ADC_TYPE_LOOPBACK; -+ int idx, grp; -+ -+ if (handle_loopback(rk3308) && -+ rk3308->dac_output == DAC_LINEOUT && -+ substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { -+ if (cmd == SNDRV_PCM_TRIGGER_START) { -+ struct snd_pcm_str *capture_str = -+ &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE]; -+ -+ if (capture_str->substream_opened) -+ queue_delayed_work(system_power_efficient_wq, -+ &rk3308->loopback_work, -+ msecs_to_jiffies(rk3308->delay_loopback_handle_ms)); -+ } else if (cmd == SNDRV_PCM_TRIGGER_STOP) { -+ /* -+ * Switch to dummy bist mode to kick the glitch during disable -+ * ADCs and keep zero input data -+ */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_L_CH_BIST_MSK, -+ RK3308_ADC_L_CH_BIST_SINE); -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_R_CH_BIST_MSK, -+ RK3308_ADC_R_CH_BIST_SINE); -+ } -+ rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_LOOPBACK); -+ } -+ } -+ -+ return 0; -+} -+ -+static void rk3308_pcm_shutdown(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct snd_soc_component *component = dai->component; -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { -+ rk3308_codec_close_playback(rk3308); -+ rk3308_codec_dac_mclk_disable(rk3308); -+ regcache_cache_only(rk3308->regmap, false); -+ regcache_sync(rk3308->regmap); -+ rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE); -+ } else { -+ rk3308_codec_close_capture(rk3308); -+ if (!has_en_always_grps(rk3308)) { -+ rk3308_codec_adc_mclk_disable(rk3308); -+ rk3308_codec_update_adcs_status(rk3308, PATH_IDLE); -+ if (rk3308->micbias_num && -+ rk3308->enable_micbias) -+ rk3308_codec_micbias_disable(rk3308); -+ } -+ -+ regcache_cache_only(rk3308->regmap, false); -+ regcache_sync(rk3308->regmap); -+ } -+} -+ -+static struct snd_soc_dai_ops rk3308_dai_ops = { -+ .hw_params = rk3308_hw_params, -+ .set_fmt = rk3308_set_dai_fmt, -+ .mute_stream = rk3308_mute_stream, -+ .trigger = rk3308_pcm_trigger, -+ .shutdown = rk3308_pcm_shutdown, -+}; -+ -+static struct snd_soc_dai_driver rk3308_dai[] = { -+ { -+ .name = "rk3308-hifi", -+ .id = RK3308_HIFI, -+ .playback = { -+ .stream_name = "HiFi Playback", -+ .channels_min = 2, -+ .channels_max = 2, -+ .rates = SNDRV_PCM_RATE_8000_192000, -+ .formats = (SNDRV_PCM_FMTBIT_S16_LE | -+ SNDRV_PCM_FMTBIT_S20_3LE | -+ SNDRV_PCM_FMTBIT_S24_LE | -+ SNDRV_PCM_FMTBIT_S32_LE), -+ }, -+ .capture = { -+ .stream_name = "HiFi Capture", -+ .channels_min = 1, -+ .channels_max = 8, -+ .rates = SNDRV_PCM_RATE_8000_192000, -+ .formats = (SNDRV_PCM_FMTBIT_S16_LE | -+ SNDRV_PCM_FMTBIT_S20_3LE | -+ SNDRV_PCM_FMTBIT_S24_LE | -+ SNDRV_PCM_FMTBIT_S32_LE), -+ }, -+ .ops = &rk3308_dai_ops, -+ }, -+}; -+ -+static int rk3308_suspend(struct snd_soc_component *component) -+{ -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ -+ if (rk3308->no_deep_low_power) -+ goto out; -+ -+ rk3308_codec_dlp_down(rk3308); -+ clk_disable_unprepare(rk3308->mclk_rx); -+ clk_disable_unprepare(rk3308->mclk_tx); -+ clk_disable_unprepare(rk3308->pclk); -+ -+out: -+ rk3308_set_bias_level(component, SND_SOC_BIAS_OFF); -+ return 0; -+} -+ -+static int rk3308_resume(struct snd_soc_component *component) -+{ -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ int ret = 0; -+ -+ if (rk3308->no_deep_low_power) -+ goto out; -+ -+ ret = clk_prepare_enable(rk3308->pclk); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, -+ "Failed to enable acodec pclk: %d\n", ret); -+ goto out; -+ } -+ -+ ret = clk_prepare_enable(rk3308->mclk_rx); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, -+ "Failed to enable i2s mclk_rx: %d\n", ret); -+ goto out; -+ } -+ -+ ret = clk_prepare_enable(rk3308->mclk_tx); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, -+ "Failed to enable i2s mclk_tx: %d\n", ret); -+ goto out; -+ } -+ -+ rk3308_codec_dlp_up(rk3308); -+out: -+ rk3308_set_bias_level(component, SND_SOC_BIAS_STANDBY); -+ return ret; -+} -+ -+static int rk3308_codec_default_gains(struct rk3308_codec_priv *rk3308) -+{ -+ int grp; -+ -+ /* Prepare ADC gains */ -+ /* vendor step 12, set MIC PGA default gains */ -+ for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) { -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON01(grp), -+ RK3308_ADC_CH1_MIC_GAIN_MSK | -+ RK3308_ADC_CH2_MIC_GAIN_MSK, -+ RK3308_ADC_CH1_MIC_GAIN_0DB | -+ RK3308_ADC_CH2_MIC_GAIN_0DB); -+ } -+ -+ /* vendor step 13, set ALC default gains */ -+ for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) { -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON03(grp), -+ RK3308_ADC_CH1_ALC_GAIN_MSK, -+ RK3308_ADC_CH1_ALC_GAIN_0DB); -+ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON04(grp), -+ RK3308_ADC_CH2_ALC_GAIN_MSK, -+ RK3308_ADC_CH2_ALC_GAIN_0DB); -+ } -+ -+ /* Prepare DAC gains */ -+ /* Step 15, set HPMIX default gains */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, -+ RK3308_DAC_L_HPMIX_GAIN_MSK | - RK3308_DAC_R_HPMIX_GAIN_MSK, - RK3308_DAC_L_HPMIX_GAIN_NDB_6 | - RK3308_DAC_R_HPMIX_GAIN_NDB_6); - -- /* recover DAC digital gain to 0 dB (reset value is 0xff, undocumented) */ -- if (rk3308->codec_ver == ACODEC_VERSION_C) -- regmap_write(rk3308->regmap, RK3308_DAC_DIG_CON04, -- RK3308BS_DAC_DIG_GAIN_0DB); -+ /* Step 18, set HPOUT default gains */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05, -+ RK3308_DAC_L_HPOUT_GAIN_MSK, -+ RK3308_DAC_L_HPOUT_GAIN_NDB_39); -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06, -+ RK3308_DAC_R_HPOUT_GAIN_MSK, -+ RK3308_DAC_R_HPOUT_GAIN_NDB_39); -+ -+ /* Using the same gain to HPOUT LR channels */ -+ rk3308->hpout_l_dgain = RK3308_DAC_L_HPOUT_GAIN_NDB_39; -+ -+ /* Step 19, set LINEOUT default gains */ -+ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, -+ RK3308_DAC_L_LINEOUT_GAIN_MSK | -+ RK3308_DAC_R_LINEOUT_GAIN_MSK, -+ RK3308_DAC_L_LINEOUT_GAIN_NDB_6 | -+ RK3308_DAC_R_LINEOUT_GAIN_NDB_6); -+ -+ return 0; -+} -+ -+static int rk3308_codec_setup_en_always_adcs(struct rk3308_codec_priv *rk3308, -+ struct device_node *np) -+{ -+ int num, ret; -+ -+ num = of_count_phandle_with_args(np, "rockchip,en-always-grps", NULL); -+ if (num < 0) { -+ if (num == -ENOENT) { -+ /* -+ * If there is note use 'rockchip,en-always-grps' -+ * property, return 0 is also right. -+ */ -+ ret = 0; -+ } else { -+ dev_err(rk3308->plat_dev, -+ "Failed to read 'rockchip,adc-grps-route' num: %d\n", -+ num); -+ ret = num; -+ } -+ -+ rk3308->en_always_grps_num = 0; -+ return ret; -+ } -+ -+ rk3308->en_always_grps_num = num; -+ -+ ret = of_property_read_u32_array(np, "rockchip,en-always-grps", -+ rk3308->en_always_grps, num); -+ if (ret < 0) { -+ dev_err(rk3308->plat_dev, -+ "Failed to read 'rockchip,en-always-grps': %d\n", -+ ret); -+ return ret; -+ } -+ -+ /* Clear all of skip_grps flags. */ -+ for (num = 0; num < ADC_LR_GROUP_MAX; num++) -+ rk3308->skip_grps[num] = 0; -+ -+ /* The loopback grp should not be enabled always. */ -+ for (num = 0; num < rk3308->en_always_grps_num; num++) { -+ if (rk3308->en_always_grps[num] == rk3308->loopback_grp) { -+ dev_err(rk3308->plat_dev, -+ "loopback_grp: %d should not be enabled always!\n", -+ rk3308->loopback_grp); -+ ret = -EINVAL; -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_dapm_mic_gains(struct rk3308_codec_priv *rk3308) -+{ -+ int ret; -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ ret = snd_soc_add_component_controls(rk3308->component, -+ mic_gains_b, -+ ARRAY_SIZE(mic_gains_b)); -+ if (ret) { -+ dev_err(rk3308->plat_dev, -+ "%s: add mic_gains_b failed: %d\n", -+ __func__, ret); -+ return ret; -+ } -+ } else { -+ ret = snd_soc_add_component_controls(rk3308->component, -+ mic_gains_a, -+ ARRAY_SIZE(mic_gains_a)); -+ if (ret) { -+ dev_err(rk3308->plat_dev, -+ "%s: add mic_gains_a failed: %d\n", -+ __func__, ret); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static int rk3308_codec_check_micbias(struct rk3308_codec_priv *rk3308, -+ struct device_node *np) -+{ -+ struct device *dev = (struct device *)rk3308->plat_dev; -+ int num = 0, ret; -+ -+ /* Check internal micbias */ -+ rk3308->micbias1 = -+ of_property_read_bool(np, "rockchip,micbias1"); -+ if (rk3308->micbias1) -+ num++; -+ -+ rk3308->micbias2 = -+ of_property_read_bool(np, "rockchip,micbias2"); -+ if (rk3308->micbias2) -+ num++; -+ -+ rk3308->micbias_volt = RK3308_ADC_MICBIAS_VOLT_0_85; /* by default */ -+ rk3308->micbias_num = num; -+ -+ /* Check external micbias */ -+ rk3308->ext_micbias = EXT_MICBIAS_NONE; -+ -+ rk3308->micbias_en_gpio = devm_gpiod_get_optional(dev, -+ "micbias-en", -+ GPIOD_IN); -+ if (!rk3308->micbias_en_gpio) { -+ dev_info(dev, "Don't need micbias-en gpio\n"); -+ } else if (IS_ERR(rk3308->micbias_en_gpio)) { -+ ret = PTR_ERR(rk3308->micbias_en_gpio); -+ dev_err(dev, "Unable to claim gpio micbias-en\n"); -+ return ret; -+ } else if (gpiod_get_value(rk3308->micbias_en_gpio)) { -+ rk3308->ext_micbias = EXT_MICBIAS_FUNC1; -+ } -+ -+ rk3308->vcc_micbias = devm_regulator_get_optional(dev, -+ "vmicbias"); -+ if (IS_ERR(rk3308->vcc_micbias)) { -+ if (PTR_ERR(rk3308->vcc_micbias) == -EPROBE_DEFER) -+ return -EPROBE_DEFER; -+ dev_info(dev, "no vmicbias regulator found\n"); -+ } else { -+ ret = regulator_enable(rk3308->vcc_micbias); -+ if (ret) { -+ dev_err(dev, "Can't enable vmicbias: %d\n", ret); -+ return ret; -+ } -+ rk3308->ext_micbias = EXT_MICBIAS_FUNC2; -+ } -+ -+ dev_info(dev, "Check ext_micbias: %d\n", rk3308->ext_micbias); -+ -+ return 0; -+} -+ -+static int rk3308_codec_dapm_controls_prepare(struct rk3308_codec_priv *rk3308) -+{ -+ int grp; -+ -+ for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) { -+ rk3308->hpf_cutoff[grp] = 0; -+ rk3308->agc_l[grp] = 0; -+ rk3308->agc_r[grp] = 0; -+ rk3308->agc_asr_l[grp] = AGC_ASR_96KHZ; -+ rk3308->agc_asr_r[grp] = AGC_ASR_96KHZ; -+ } -+ -+ rk3308_codec_dapm_mic_gains(rk3308); -+ -+ return 0; -+} -+ -+static int rk3308_codec_prepare(struct rk3308_codec_priv *rk3308) -+{ -+ /* Clear registers for ADC and DAC */ -+ rk3308_codec_close_playback(rk3308); -+ rk3308_codec_close_all_capture(rk3308); -+ rk3308_codec_default_gains(rk3308); -+ rk3308_codec_llp_down(rk3308); -+ rk3308_codec_dapm_controls_prepare(rk3308); -+ -+ return 0; -+} -+ -+static int rk3308_probe(struct snd_soc_component *component) -+{ -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ int ext_micbias; -+ -+ rk3308->component = component; -+ rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE); -+ -+ rk3308_codec_reset(component); -+ rk3308_codec_power_on(rk3308); -+ -+ /* From vendor recommend, disable micbias at first. */ -+ ext_micbias = rk3308->ext_micbias; -+ rk3308->ext_micbias = EXT_MICBIAS_NONE; -+ rk3308_codec_micbias_disable(rk3308); -+ rk3308->ext_micbias = ext_micbias; -+ -+ rk3308_codec_prepare(rk3308); -+ if (!rk3308->no_hp_det) -+ rk3308_codec_headset_detect_enable(rk3308); -+ -+ regcache_cache_only(rk3308->regmap, false); -+ regcache_sync(rk3308->regmap); -+ -+ return 0; -+} -+ -+static void rk3308_remove(struct snd_soc_component *component) -+{ -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ -+ rk3308_headphone_ctl(rk3308, 0); -+ rk3308_speaker_ctl(rk3308, 0); -+ if (!rk3308->no_hp_det) -+ rk3308_codec_headset_detect_disable(rk3308); -+ rk3308_codec_micbias_disable(rk3308); -+ rk3308_codec_power_off(rk3308); -+ -+ rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE); -+ -+ regcache_cache_only(rk3308->regmap, false); -+ regcache_sync(rk3308->regmap); -+ -+ return; -+} -+ -+static const struct snd_soc_component_driver soc_codec_dev_rk3308_component = { -+ .probe = rk3308_probe, -+ .remove = rk3308_remove, -+ .resume = rk3308_resume, -+ .suspend = rk3308_suspend, -+ .set_bias_level = rk3308_set_bias_level, -+ .controls = rk3308_codec_dapm_controls, -+ .num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls), -+ // .dapm_widgets = rk3308_dapm_widgets, -+ // .num_dapm_widgets = ARRAY_SIZE(rk3308_dapm_widgets), -+ // .dapm_routes = rk3308_dapm_routes, -+ // .num_dapm_routes = ARRAY_SIZE(rk3308_dapm_routes), -+ // .suspend_bias_off = 1, -+ // .idle_bias_on = 1, -+ // .use_pmdown_time = 1, -+ .endianness = 1, -+ .legacy_dai_naming = 1, -+}; -+ -+static const struct reg_default rk3308_codec_reg_defaults[] = { -+ { RK3308_GLB_CON, 0x07 }, -+}; -+ -+static bool rk3308_codec_write_read_reg(struct device *dev, unsigned int reg) -+{ -+ /* All registers can be read / write */ -+ return true; -+} -+ -+static bool rk3308_codec_volatile_reg(struct device *dev, unsigned int reg) -+{ -+ return true; -+} -+ -+static void rk3308_codec_hpdetect_work(struct work_struct *work) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(work, struct rk3308_codec_priv, hpdet_work.work); -+ unsigned int val; -+ int need_poll = 0, need_irq = 0; -+ int need_report = 0, report_type = 0; -+ int dac_output = DAC_LINEOUT; -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ /* Check headphone plugged/unplugged directly. */ -+ regmap_read(rk3308->detect_grf, -+ DETECT_GRF_ACODEC_HPDET_STATUS, &val); -+ regmap_write(rk3308->detect_grf, -+ DETECT_GRF_ACODEC_HPDET_STATUS_CLR, val); -+ -+ if (rk3308->hp_jack_reversed) { -+ switch (val) { -+ case 0x0: -+ case 0x2: -+ dac_output = DAC_HPOUT; -+ report_type = SND_JACK_HEADPHONE; -+ break; -+ default: -+ break; -+ } -+ } else { -+ switch (val) { -+ case 0x1: -+ dac_output = DAC_HPOUT; -+ report_type = SND_JACK_HEADPHONE; -+ break; -+ default: -+ /* Includes val == 2 or others. */ -+ break; -+ } -+ } -+ -+ rk3308_codec_dac_switch(rk3308, dac_output); -+ if (rk3308->hpdet_jack) -+ snd_soc_jack_report(rk3308->hpdet_jack, -+ report_type, -+ SND_JACK_HEADPHONE); -+ -+ enable_irq(rk3308->irq); -+ -+ return; -+ } -+ -+ /* Check headphone unplugged via poll. */ -+ regmap_read(rk3308->regmap, RK3308_DAC_DIG_CON14, &val); -+ -+ if (rk3308->hp_jack_reversed) { -+ if (!val) { -+ rk3308->hp_plugged = true; -+ report_type = SND_JACK_HEADPHONE; -+ -+ need_report = 1; -+ need_irq = 1; -+ } else { -+ if (rk3308->hp_plugged) { -+ rk3308->hp_plugged = false; -+ need_report = 1; -+ } -+ need_poll = 1; -+ } -+ } else { -+ if (!val) { -+ rk3308->hp_plugged = false; -+ -+ need_report = 1; -+ need_irq = 1; -+ } else { -+ if (!rk3308->hp_plugged) { -+ rk3308->hp_plugged = true; -+ report_type = SND_JACK_HEADPHONE; -+ need_report = 1; -+ } -+ need_poll = 1; -+ } -+ } -+ -+ if (need_poll) -+ queue_delayed_work(system_power_efficient_wq, -+ &rk3308->hpdet_work, -+ msecs_to_jiffies(HPDET_POLL_MS)); -+ -+ if (need_report) { -+ if (report_type) -+ dac_output = DAC_HPOUT; -+ -+ rk3308_codec_dac_switch(rk3308, dac_output); -+ -+ if (rk3308->hpdet_jack) -+ snd_soc_jack_report(rk3308->hpdet_jack, -+ report_type, -+ SND_JACK_HEADPHONE); -+ } -+ -+ if (need_irq) -+ enable_irq(rk3308->irq); -+} -+ -+static void rk3308_codec_loopback_work(struct work_struct *work) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(work, struct rk3308_codec_priv, loopback_work.work); -+ int type = ADC_TYPE_LOOPBACK; -+ int idx, grp; -+ -+ /* Prepare loopback ADCs */ -+ rk3308_codec_adc_ana_enable(rk3308, type); -+ -+ /* Waiting ADCs are stable */ -+ msleep(ADC_STABLE_MS); -+ -+ /* Recover normal mode after enable ADCs */ -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { -+ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) -+ continue; -+ -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_L_CH_BIST_MSK, -+ RK3308_ADC_L_CH_NORMAL_LEFT); -+ regmap_update_bits(rk3308->regmap, -+ RK3308_ADC_DIG_CON03(grp), -+ RK3308_ADC_R_CH_BIST_MSK, -+ RK3308_ADC_R_CH_NORMAL_RIGHT); -+ } -+} -+ -+static irqreturn_t rk3308_codec_hpdet_isr(int irq, void *data) -+{ -+ struct rk3308_codec_priv *rk3308 = data; -+ -+ /* -+ * For the high level irq trigger, disable irq and avoid a lot of -+ * repeated irq handlers entry. -+ */ -+ disable_irq_nosync(rk3308->irq); -+ queue_delayed_work(system_power_efficient_wq, -+ &rk3308->hpdet_work, msecs_to_jiffies(10)); -+ -+ return IRQ_HANDLED; -+} -+ -+void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_component *component, -+ struct snd_soc_jack *hpdet_jack); -+EXPORT_SYMBOL_GPL(rk3308_codec_set_jack_detect_cb); -+ -+static void rk3308_codec_set_jack_detect(struct snd_soc_component *component, -+ struct snd_soc_jack *hpdet_jack) -+{ -+ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ -+ rk3308->hpdet_jack = hpdet_jack; -+ -+ /* To detect jack once during startup */ -+ disable_irq_nosync(rk3308->irq); -+ queue_delayed_work(system_power_efficient_wq, -+ &rk3308->hpdet_work, msecs_to_jiffies(10)); -+ -+ dev_info(rk3308->plat_dev, "%s: Request detect hp jack once\n", -+ __func__); -+} -+ -+static const struct regmap_config rk3308_codec_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .max_register = RK3308_DAC_ANA_CON15, -+ .writeable_reg = rk3308_codec_write_read_reg, -+ .readable_reg = rk3308_codec_write_read_reg, -+ .volatile_reg = rk3308_codec_volatile_reg, -+ .reg_defaults = rk3308_codec_reg_defaults, -+ .num_reg_defaults = ARRAY_SIZE(rk3308_codec_reg_defaults), -+ .cache_type = REGCACHE_FLAT, -+}; -+ -+static ssize_t pm_state_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ -+ return sprintf(buf, "pm_state: %d\n", rk3308->pm_state); -+} - -- /* -- * Unconditionally enable zero-cross detection (needed for AGC, -- * harmless without AGC) -- */ -- for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) -- regmap_set_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), -- RK3308_ADC_CH1_ZEROCROSS_DET_EN | -- RK3308_ADC_CH2_ZEROCROSS_DET_EN); -+static ssize_t pm_state_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ unsigned long pm_state; -+ int ret = kstrtoul(buf, 10, &pm_state); - -- return 0; -+ if (ret < 0) { -+ dev_err(dev, "Invalid pm_state: %ld, ret: %d\n", -+ pm_state, ret); -+ return -EINVAL; -+ } -+ -+ rk3308_codec_set_pm_state(rk3308, pm_state); -+ -+ dev_info(dev, "Store pm_state: %d\n", rk3308->pm_state); -+ -+ return count; - } - --static int rk3308_codec_probe(struct snd_soc_component *component) -+static ssize_t adc_grps_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) - { -- struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ u32 grp; -+ int type = ADC_TYPE_NORMAL, count = 0; -+ int idx; - -- rk3308->component = component; -+ count += sprintf(buf + count, "current used adc_grps:\n"); -+ count += sprintf(buf + count, "- normal:"); -+ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) -+ count += sprintf(buf + count, " %d", grp); -+ count += sprintf(buf + count, "\n"); -+ count += sprintf(buf + count, "- loopback: %d\n", -+ rk3308->loopback_grp); - -- rk3308_codec_reset(component); -- rk3308_codec_initialize(rk3308); -+ return count; -+} - -- return 0; -+static ssize_t adc_grps_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ char adc_type; -+ int grps, ret; -+ -+ ret = sscanf(buf, "%c,%d", &adc_type, &grps); -+ if (ret != 2) { -+ dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n", -+ __func__, ret); -+ return -EFAULT; -+ } -+ -+ if (adc_type == 'n') -+ rk3308->used_adc_grps = grps; -+ else if (adc_type == 'l') -+ rk3308->loopback_grp = grps; -+ -+ return count; - } - --static int rk3308_codec_set_bias_level(struct snd_soc_component *component, -- enum snd_soc_bias_level level) -+static ssize_t adc_grps_route_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) - { -- struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ char which_i2s[32] = {0}; -+ int count = 0; -+ u32 grp; - -- switch (level) { -- case SND_SOC_BIAS_ON: -+ switch (rk3308->which_i2s) { -+ case ACODEC_TO_I2S1_2CH: -+ strcpy(which_i2s, "i2s1_2ch"); - break; -- case SND_SOC_BIAS_PREPARE: -+ case ACODEC_TO_I2S3_4CH: -+ strcpy(which_i2s, "i2s3_4ch"); - break; -- case SND_SOC_BIAS_STANDBY: -- if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_OFF) -- break; -+ default: -+ strcpy(which_i2s, "i2s2_8ch"); -+ break; -+ } - -- /* Sequence from TRM Section 8.6.3 "Power Up" */ -- regmap_set_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, -- RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN); -- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -- RK3308_ADC_CURRENT_CHARGE_MSK, 1); -- regmap_set_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -- RK3308_ADC_REF_EN); -- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -- RK3308_ADC_CURRENT_CHARGE_MSK, 0x7f); -- msleep(20); /* estimated value */ -+ count += sprintf(buf + count, "%s from acodec route mapping:\n", -+ which_i2s); -+ for (grp = 0; grp < rk3308->to_i2s_grps; grp++) { -+ count += sprintf(buf + count, "* sdi_%d <-- sdo_%d\n", -+ grp, rk3308->i2s_sdis[grp]); -+ } -+ -+ return count; -+} -+ -+static ssize_t adc_grps_route_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ int which_i2s, idx, i2s_sdis[ADC_LR_GROUP_MAX]; -+ int ret; -+ -+ ret = sscanf(buf, "%d,%d,%d,%d,%d", &which_i2s, -+ &i2s_sdis[0], &i2s_sdis[1], &i2s_sdis[2], &i2s_sdis[3]); -+ if (ret != 5) { -+ dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n", -+ __func__, ret); -+ goto err; -+ } -+ -+ if (which_i2s < ACODEC_TO_I2S2_8CH || -+ which_i2s > ACODEC_TO_I2S1_2CH) { -+ dev_err(rk3308->plat_dev, "Invalid i2s type: %d\n", which_i2s); -+ goto err; -+ } -+ -+ rk3308->which_i2s = which_i2s; -+ -+ switch (rk3308->which_i2s) { -+ case ACODEC_TO_I2S1_2CH: -+ rk3308->to_i2s_grps = 1; - break; -- case SND_SOC_BIAS_OFF: -- /* Sequence from TRM Section 8.6.4 "Power Down" */ -- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -- RK3308_ADC_CURRENT_CHARGE_MSK, 1); -- regmap_clear_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), -- RK3308_ADC_REF_EN); -- regmap_clear_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, -- RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN); -- msleep(20); /* estimated value */ -+ case ACODEC_TO_I2S3_4CH: -+ rk3308->to_i2s_grps = 2; -+ break; -+ default: -+ rk3308->to_i2s_grps = 4; - break; - } -- return 0; -+ -+ for (idx = 0; idx < rk3308->to_i2s_grps; idx++) -+ rk3308->i2s_sdis[idx] = i2s_sdis[idx]; -+ -+ rk3308_codec_adc_grps_route_config(rk3308); -+ -+err: -+ return count; - } - --static const struct snd_soc_component_driver rk3308_codec_component_driver = { -- .probe = rk3308_codec_probe, -- .set_bias_level = rk3308_codec_set_bias_level, -- .controls = rk3308_codec_controls, -- .num_controls = ARRAY_SIZE(rk3308_codec_controls), -- .dapm_widgets = rk3308_codec_dapm_widgets, -- .num_dapm_widgets = ARRAY_SIZE(rk3308_codec_dapm_widgets), -- .dapm_routes = rk3308_codec_dapm_routes, -- .num_dapm_routes = ARRAY_SIZE(rk3308_codec_dapm_routes), --}; -+static ssize_t adc_grp0_in_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); - --static const struct regmap_config rk3308_codec_regmap_config = { -- .reg_bits = 32, -- .reg_stride = 4, -- .val_bits = 32, -- .max_register = RK3308_DAC_ANA_CON15, --}; -+ return sprintf(buf, "adc ch0 using: %s\n", -+ rk3308->adc_grp0_using_linein ? "line in" : "mic in"); -+} - --static int rk3308_codec_get_version(struct rk3308_codec_priv *rk3308) -+static ssize_t adc_grp0_in_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) - { -- unsigned int chip_id; -- int err; -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ unsigned long using_linein; -+ int ret = kstrtoul(buf, 10, &using_linein); - -- err = regmap_read(rk3308->grf, GRF_CHIP_ID, &chip_id); -- if (err) -- return err; -+ if (ret < 0 || using_linein > 1) { -+ dev_err(dev, "Invalid input status: %ld, ret: %d\n", -+ using_linein, ret); -+ return -EINVAL; -+ } - -- switch (chip_id) { -- case 3306: -- rk3308->codec_ver = ACODEC_VERSION_A; -+ rk3308->adc_grp0_using_linein = using_linein; -+ -+ dev_info(dev, "store using_linein: %d\n", -+ rk3308->adc_grp0_using_linein); -+ -+ return count; -+} -+ -+static ssize_t adc_zerocross_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ -+ return sprintf(buf, "adc zerocross: %s\n", -+ rk3308->adc_zerocross ? "enabled" : "disabled"); -+} -+ -+static ssize_t adc_zerocross_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ unsigned long zerocross; -+ int ret = kstrtoul(buf, 10, &zerocross); -+ -+ if (ret < 0 || zerocross > 1) { -+ dev_err(dev, "Invalid zerocross: %ld, ret: %d\n", -+ zerocross, ret); -+ return -EINVAL; -+ } -+ -+ rk3308->adc_zerocross = zerocross; -+ -+ dev_info(dev, "store adc zerocross: %d\n", rk3308->adc_zerocross); -+ -+ return count; -+} -+ -+static ssize_t adc_grps_endisable_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ int count = 0, i; -+ -+ count += sprintf(buf + count, "enabled adc grps:"); -+ for (i = 0; i < ADC_LR_GROUP_MAX; i++) -+ count += sprintf(buf + count, "%d ", -+ rk3308->adc_grps_endisable[i]); -+ -+ count += sprintf(buf + count, "\n"); -+ return count; -+} -+ -+static ssize_t adc_grps_endisable_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ int grp, endisable, ret; -+ -+ ret = sscanf(buf, "%d,%d", &grp, &endisable); -+ if (ret != 2) { -+ dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n", -+ __func__, ret); -+ return -EFAULT; -+ } -+ -+ rk3308->cur_dbg_grp = grp; -+ -+ if (endisable) -+ rk3308_codec_open_dbg_capture(rk3308); -+ else -+ rk3308_codec_close_dbg_capture(rk3308); -+ -+ dev_info(dev, "ADC grp %d endisable: %d\n", grp, endisable); -+ -+ return count; -+} -+ -+static ssize_t dac_endisable_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ -+ return sprintf(buf, "%d\n", rk3308->dac_endisable); -+} -+ -+static ssize_t dac_endisable_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ unsigned long endisable; -+ int ret = kstrtoul(buf, 10, &endisable); -+ -+ if (ret < 0) { -+ dev_err(dev, "Invalid endisable: %ld, ret: %d\n", -+ endisable, ret); -+ return -EINVAL; -+ } -+ -+ if (endisable) -+ rk3308_codec_open_playback(rk3308); -+ else -+ rk3308_codec_close_playback(rk3308); -+ -+ dev_info(dev, "DAC endisable: %ld\n", endisable); -+ -+ return count; -+} -+ -+static ssize_t dac_output_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ ssize_t ret = 0; -+ -+ switch (rk3308->dac_output) { -+ case DAC_LINEOUT: -+ ret = sprintf(buf, "dac path: %s\n", "line out"); - break; -- case 0x3308: -- rk3308->codec_ver = ACODEC_VERSION_B; -- return dev_err_probe(rk3308->dev, -EINVAL, "Chip version B not supported\n"); -- case 0x3308c: -- rk3308->codec_ver = ACODEC_VERSION_C; -+ case DAC_HPOUT: -+ ret = sprintf(buf, "dac path: %s\n", "hp out"); -+ break; -+ case DAC_LINEOUT_HPOUT: -+ ret = sprintf(buf, "dac path: %s\n", -+ "both line out and hp out"); - break; - default: -- return dev_err_probe(rk3308->dev, -EINVAL, "Unknown chip_id: 0x%x\n", chip_id); -+ pr_err("Invalid dac path: %d ?\n", rk3308->dac_output); -+ break; -+ } -+ -+ return ret; -+} -+ -+static ssize_t dac_output_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ unsigned long dac_output; -+ int ret = kstrtoul(buf, 10, &dac_output); -+ -+ if (ret < 0) { -+ dev_err(dev, "Invalid input status: %ld, ret: %d\n", -+ dac_output, ret); -+ return -EINVAL; -+ } -+ -+ rk3308_codec_dac_switch(rk3308, dac_output); -+ -+ dev_info(dev, "Store dac_output: %d\n", rk3308->dac_output); -+ -+ return count; -+} -+ -+static ssize_t enable_all_adcs_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ -+ return sprintf(buf, "%d\n", rk3308->enable_all_adcs); -+} -+ -+static ssize_t enable_all_adcs_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ container_of(dev, struct rk3308_codec_priv, dev); -+ unsigned long enable; -+ int ret = kstrtoul(buf, 10, &enable); -+ -+ if (ret < 0) { -+ dev_err(dev, "Invalid enable value: %ld, ret: %d\n", -+ enable, ret); -+ return -EINVAL; -+ } -+ -+ rk3308->enable_all_adcs = enable; -+ -+ return count; -+} -+ -+static const struct device_attribute acodec_attrs[] = { -+ __ATTR_RW(adc_grps), -+ __ATTR_RW(adc_grps_endisable), -+ __ATTR_RW(adc_grps_route), -+ __ATTR_RW(adc_grp0_in), -+ __ATTR_RW(adc_zerocross), -+ __ATTR_RW(dac_endisable), -+ __ATTR_RW(dac_output), -+ __ATTR_RW(enable_all_adcs), -+ __ATTR_RW(pm_state), -+}; -+ -+static void rk3308_codec_device_release(struct device *dev) -+{ -+ /* Do nothing */ -+} -+ -+static int rk3308_codec_sysfs_init(struct platform_device *pdev, -+ struct rk3308_codec_priv *rk3308) -+{ -+ struct device *dev = &rk3308->dev; -+ int i; -+ -+ dev->release = rk3308_codec_device_release; -+ dev->parent = &pdev->dev; -+ set_dev_node(dev, dev_to_node(&pdev->dev)); -+ dev_set_name(dev, "rk3308-acodec-dev"); -+ -+ if (device_register(dev)) { -+ dev_err(&pdev->dev, -+ "Register 'rk3308-acodec-dev' failed\n"); -+ dev->parent = NULL; -+ return -ENOMEM; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(acodec_attrs); i++) { -+ if (device_create_file(dev, &acodec_attrs[i])) { -+ dev_err(&pdev->dev, -+ "Create 'rk3308-acodec-dev' attr failed\n"); -+ device_unregister(dev); -+ return -ENOMEM; -+ } - } - -- dev_info(rk3308->dev, "Found codec version %c\n", rk3308->codec_ver); - return 0; - } - --static int rk3308_codec_set_micbias_level(struct rk3308_codec_priv *rk3308) -+#if defined(CONFIG_DEBUG_FS) -+static int rk3308_codec_debugfs_reg_show(struct seq_file *s, void *v) - { -- struct device_node *np = rk3308->dev->of_node; -- u32 percent; -- u32 mult; -- int err; -+ struct rk3308_codec_priv *rk3308 = s->private; -+ unsigned int i; -+ unsigned int val; - -- err = of_property_read_u32(np, "rockchip,micbias-avdd-percent", &percent); -- if (err == -EINVAL) -- return 0; -- if (err) -- return dev_err_probe(rk3308->dev, err, -- "Error reading 'rockchip,micbias-avdd-percent'\n"); -+ for (i = RK3308_GLB_CON; i <= RK3308_DAC_ANA_CON13; i += 4) { -+ regmap_read(rk3308->regmap, i, &val); -+ if (!(i % 16)) -+ seq_printf(s, "\nR:%04x: ", i); -+ seq_printf(s, "%08x ", val); -+ } - -- /* Convert percent to register value, linerarly (50% -> 0, 5% step = +1) */ -- mult = (percent - 50) / 5; -+ seq_puts(s, "\n"); - -- /* Check range and that the percent was an exact value allowed */ -- if (mult > RK3308_ADC_LEVEL_RANGE_MICBIAS_MAX || mult * 5 + 50 != percent) -- return dev_err_probe(rk3308->dev, -EINVAL, -- "Invalid value %u for 'rockchip,micbias-avdd-percent'\n", -- percent); -+ return 0; -+} - -- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0), -- RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK, -- mult << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT); -+static ssize_t rk3308_codec_debugfs_reg_operate(struct file *file, -+ const char __user *buf, -+ size_t count, loff_t *ppos) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ ((struct seq_file *)file->private_data)->private; -+ unsigned int reg, val; -+ char op; -+ char kbuf[32]; -+ int ret; - -+ if (count >= sizeof(kbuf)) -+ return -EINVAL; -+ -+ if (copy_from_user(kbuf, buf, count)) -+ return -EFAULT; -+ kbuf[count] = '\0'; -+ -+ ret = sscanf(kbuf, "%c,%x,%x", &op, ®, &val); -+ if (ret != 3) { -+ pr_err("sscanf failed: %d\n", ret); -+ return -EFAULT; -+ } -+ -+ if (op == 'w') { -+ pr_info("Write reg: 0x%04x with val: 0x%08x\n", reg, val); -+ regmap_write(rk3308->regmap, reg, val); -+ regcache_cache_only(rk3308->regmap, false); -+ regcache_sync(rk3308->regmap); -+ pr_info("Read back reg: 0x%04x with val: 0x%08x\n", reg, val); -+ } else if (op == 'r') { -+ regmap_read(rk3308->regmap, reg, &val); -+ pr_info("Read reg: 0x%04x with val: 0x%08x\n", reg, val); -+ } else { -+ pr_err("This is an invalid operation: %c\n", op); -+ } -+ -+ return count; -+} -+ -+static int rk3308_codec_debugfs_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, -+ rk3308_codec_debugfs_reg_show, inode->i_private); -+} -+ -+static const struct file_operations rk3308_codec_reg_debugfs_fops = { -+ .owner = THIS_MODULE, -+ .open = rk3308_codec_debugfs_open, -+ .read = seq_read, -+ .write = rk3308_codec_debugfs_reg_operate, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+#endif /* CONFIG_DEBUG_FS */ -+ -+static int rk3308_codec_get_version(struct rk3308_codec_priv *rk3308) -+{ -+ unsigned int chip_id; -+ -+ regmap_read(rk3308->grf, GRF_CHIP_ID, &chip_id); -+ switch (chip_id) { -+ case 3306: -+ rk3308->codec_ver = ACODEC_VERSION_A; -+ break; -+ case 0x3308: -+ rk3308->codec_ver = ACODEC_VERSION_B; -+ break; -+ default: -+ pr_err("Unknown chip_id: %d / 0x%x\n", chip_id, chip_id); -+ return -EFAULT; -+ } -+ -+ pr_info("The acodec version is: %x\n", rk3308->codec_ver); - return 0; - } - --static int rk3308_codec_platform_probe(struct platform_device *pdev) -+static int rk3308_platform_probe(struct platform_device *pdev) - { - struct device_node *np = pdev->dev.of_node; -- struct device *dev = &pdev->dev; - struct rk3308_codec_priv *rk3308; -+ struct resource *res; - void __iomem *base; -- int err; -+ int ret; - - rk3308 = devm_kzalloc(&pdev->dev, sizeof(*rk3308), GFP_KERNEL); - if (!rk3308) - return -ENOMEM; - -- rk3308->dev = dev; -- - rk3308->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); -- if (IS_ERR(rk3308->grf)) -- return dev_err_probe(dev, PTR_ERR(rk3308->grf), "Error getting GRF\n"); -+ if (IS_ERR(rk3308->grf)) { -+ dev_err(&pdev->dev, -+ "Missing 'rockchip,grf' property\n"); -+ return PTR_ERR(rk3308->grf); -+ } -+ -+ ret = rk3308_codec_sysfs_init(pdev, rk3308); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Sysfs init failed\n"); -+ return ret; -+ } - -- rk3308->reset = devm_reset_control_get_optional_exclusive(dev, "codec"); -- if (IS_ERR(rk3308->reset)) -- return dev_err_probe(dev, PTR_ERR(rk3308->reset), "Failed to get reset control\n"); -+#if defined(CONFIG_DEBUG_FS) -+ rk3308->dbg_codec = debugfs_create_dir(CODEC_DRV_NAME, NULL); -+ if (IS_ERR(rk3308->dbg_codec)) -+ dev_err(&pdev->dev, -+ "Failed to create debugfs dir for rk3308!\n"); -+ else -+ debugfs_create_file("reg", 0644, rk3308->dbg_codec, -+ rk3308, &rk3308_codec_reg_debugfs_fops); -+#endif -+ rk3308->plat_dev = &pdev->dev; - -- err = devm_clk_bulk_get(dev, ARRAY_SIZE(rk3308_codec_clocks), rk3308_codec_clocks); -- if (err) -- return dev_err_probe(dev, err, "Failed to get clocks\n"); -+ rk3308->reset = devm_reset_control_get(&pdev->dev, "acodec-reset"); -+ if (IS_ERR(rk3308->reset)) { -+ ret = PTR_ERR(rk3308->reset); -+ if (ret != -ENOENT) -+ return ret; - -- err = clk_bulk_prepare_enable(ARRAY_SIZE(rk3308_codec_clocks), rk3308_codec_clocks); -- if (err) -- return dev_err_probe(dev, err, "Failed to enable clocks\n"); -+ dev_dbg(&pdev->dev, "No reset control found\n"); -+ rk3308->reset = NULL; -+ } -+ -+ rk3308->hp_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "hp-ctl", -+ GPIOD_OUT_LOW); -+ if (!rk3308->hp_ctl_gpio) { -+ dev_info(&pdev->dev, "Don't need hp-ctl gpio\n"); -+ } else if (IS_ERR(rk3308->hp_ctl_gpio)) { -+ ret = PTR_ERR(rk3308->hp_ctl_gpio); -+ dev_err(&pdev->dev, "Unable to claim gpio hp-ctl\n"); -+ return ret; -+ } -+ -+ rk3308->spk_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "spk-ctl", -+ GPIOD_OUT_LOW); -+ -+ if (!rk3308->spk_ctl_gpio) { -+ dev_info(&pdev->dev, "Don't need spk-ctl gpio\n"); -+ } else if (IS_ERR(rk3308->spk_ctl_gpio)) { -+ ret = PTR_ERR(rk3308->spk_ctl_gpio); -+ dev_err(&pdev->dev, "Unable to claim gpio spk-ctl\n"); -+ return ret; -+ } -+ -+ rk3308->pa_drv_gpio = devm_gpiod_get_optional(&pdev->dev, "pa-drv", -+ GPIOD_OUT_LOW); -+ -+ if (!rk3308->pa_drv_gpio) { -+ dev_info(&pdev->dev, "Don't need pa-drv gpio\n"); -+ } else if (IS_ERR(rk3308->pa_drv_gpio)) { -+ ret = PTR_ERR(rk3308->pa_drv_gpio); -+ dev_err(&pdev->dev, "Unable to claim gpio pa-drv\n"); -+ return ret; -+ } -+ -+ if (rk3308->pa_drv_gpio) { -+ rk3308->delay_pa_drv_ms = PA_DRV_MS; -+ ret = of_property_read_u32(np, "rockchip,delay-pa-drv-ms", -+ &rk3308->delay_pa_drv_ms); -+ } -+ -+#if DEBUG_POP_ALWAYS -+ dev_info(&pdev->dev, "Enable all ctl gpios always for debugging pop\n"); -+ rk3308_headphone_ctl(rk3308, 1); -+ rk3308_speaker_ctl(rk3308, 1); -+#else -+ dev_info(&pdev->dev, "De-pop as much as possible\n"); -+ rk3308_headphone_ctl(rk3308, 0); -+ rk3308_speaker_ctl(rk3308, 0); -+#endif -+ -+ rk3308->pclk = devm_clk_get(&pdev->dev, "acodec"); -+ if (IS_ERR(rk3308->pclk)) { -+ dev_err(&pdev->dev, "Can't get acodec pclk\n"); -+ return PTR_ERR(rk3308->pclk); -+ } -+ -+ rk3308->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx"); -+ if (IS_ERR(rk3308->mclk_rx)) { -+ dev_err(&pdev->dev, "Can't get acodec mclk_rx\n"); -+ return PTR_ERR(rk3308->mclk_rx); -+ } -+ -+ rk3308->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx"); -+ if (IS_ERR(rk3308->mclk_tx)) { -+ dev_err(&pdev->dev, "Can't get acodec mclk_tx\n"); -+ return PTR_ERR(rk3308->mclk_tx); -+ } -+ -+ ret = clk_prepare_enable(rk3308->pclk); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Failed to enable acodec pclk: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(rk3308->mclk_rx); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Failed to enable i2s mclk_rx: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(rk3308->mclk_tx); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Failed to enable i2s mclk_tx: %d\n", ret); -+ return ret; -+ } -+ -+ rk3308_codec_check_micbias(rk3308, np); -+ -+ rk3308->enable_all_adcs = -+ of_property_read_bool(np, "rockchip,enable-all-adcs"); -+ -+ rk3308->hp_jack_reversed = -+ of_property_read_bool(np, "rockchip,hp-jack-reversed"); -+ -+ rk3308->no_deep_low_power = -+ of_property_read_bool(np, "rockchip,no-deep-low-power"); -+ -+ rk3308->no_hp_det = -+ of_property_read_bool(np, "rockchip,no-hp-det"); -+ -+ rk3308->delay_loopback_handle_ms = LOOPBACK_HANDLE_MS; -+ ret = of_property_read_u32(np, "rockchip,delay-loopback-handle-ms", -+ &rk3308->delay_loopback_handle_ms); -+ -+ rk3308->delay_start_play_ms = 0; -+ ret = of_property_read_u32(np, "rockchip,delay-start-play-ms", -+ &rk3308->delay_start_play_ms); -+ -+ rk3308->loopback_grp = NOT_USED; -+ ret = of_property_read_u32(np, "rockchip,loopback-grp", -+ &rk3308->loopback_grp); -+ /* -+ * If there is no loopback on some board, the -EINVAL indicates that -+ * we don't need add the node, and it is not an error. -+ */ -+ if (ret < 0 && ret != -EINVAL) { -+ dev_err(&pdev->dev, "Failed to read loopback property: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = rk3308_codec_adc_grps_route(rk3308, np); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Failed to route ADC groups: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = rk3308_codec_setup_en_always_adcs(rk3308, np); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Failed to setup enabled always ADCs: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = rk3308_codec_get_version(rk3308); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Failed to get acodec version: %d\n", -+ ret); -+ return ret; -+ } -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(base)) { -+ ret = PTR_ERR(base); -+ dev_err(&pdev->dev, "Failed to ioremap resource\n"); -+ goto failed; -+ } -+ -+ rk3308->regmap = devm_regmap_init_mmio(&pdev->dev, base, -+ &rk3308_codec_regmap_config); -+ if (IS_ERR(rk3308->regmap)) { -+ ret = PTR_ERR(rk3308->regmap); -+ dev_err(&pdev->dev, "Failed to regmap mmio\n"); -+ goto failed; -+ } -+ -+ if (!rk3308->no_hp_det) { -+ int index = 0; -+ -+ if (rk3308->codec_ver == ACODEC_VERSION_B) -+ index = 1; -+ -+ rk3308->irq = platform_get_irq(pdev, index); -+ if (rk3308->irq < 0) { -+ dev_err(&pdev->dev, "Can not get codec irq\n"); -+ goto failed; -+ } -+ -+ INIT_DELAYED_WORK(&rk3308->hpdet_work, rk3308_codec_hpdetect_work); -+ -+ ret = devm_request_irq(&pdev->dev, rk3308->irq, -+ rk3308_codec_hpdet_isr, -+ 0, -+ "acodec-hpdet", -+ rk3308); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Failed to request IRQ: %d\n", ret); -+ goto failed; -+ } - -- err = rk3308_codec_get_version(rk3308); -- if (err) -- return err; -+ if (rk3308->codec_ver == ACODEC_VERSION_B) { -+ rk3308->detect_grf = -+ syscon_regmap_lookup_by_phandle(np, "rockchip,detect-grf"); -+ if (IS_ERR(rk3308->detect_grf)) { -+ dev_err(&pdev->dev, -+ "Missing 'rockchip,detect-grf' property\n"); -+ return PTR_ERR(rk3308->detect_grf); -+ } -+ -+ /* Configure filter count and enable hpdet irq. */ -+ regmap_write(rk3308->detect_grf, -+ DETECT_GRF_ACODEC_HPDET_COUNTER, -+ DEFAULT_HPDET_COUNT); -+ regmap_write(rk3308->detect_grf, -+ DETECT_GRF_ACODEC_HPDET_CON, -+ (HPDET_BOTH_NEG_POS << 16) | -+ HPDET_BOTH_NEG_POS); -+ } -+ -+ rk3308_codec_set_jack_detect_cb = rk3308_codec_set_jack_detect; -+ } - -- base = devm_platform_ioremap_resource(pdev, 0); -- if (IS_ERR(base)) -- return PTR_ERR(base); -+ if (rk3308->codec_ver == ACODEC_VERSION_A) -+ INIT_DELAYED_WORK(&rk3308->loopback_work, -+ rk3308_codec_loopback_work); - -- rk3308->regmap = devm_regmap_init_mmio(dev, base, &rk3308_codec_regmap_config); -- if (IS_ERR(rk3308->regmap)) -- return dev_err_probe(dev, PTR_ERR(rk3308->regmap), -- "Failed to init regmap\n"); -+ rk3308->adc_grp0_using_linein = ADC_GRP0_MICIN; -+ rk3308->dac_output = DAC_LINEOUT; -+ rk3308->adc_zerocross = 1; -+ rk3308->pm_state = PM_NORMAL; - - platform_set_drvdata(pdev, rk3308); - -- err = rk3308_codec_set_micbias_level(rk3308); -- if (err) -- return err; -+ ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk3308_component, -+ rk3308_dai, ARRAY_SIZE(rk3308_dai)); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Failed to register component: %d\n", ret); -+ goto failed; -+ } - -- err = devm_snd_soc_register_component(dev, &rk3308_codec_component_driver, -- &rk3308_codec_dai_driver, 1); -- if (err) -- return dev_err_probe(dev, err, "Failed to register codec\n"); -+ return ret; - -- return 0; -+failed: -+ clk_disable_unprepare(rk3308->mclk_rx); -+ clk_disable_unprepare(rk3308->mclk_tx); -+ clk_disable_unprepare(rk3308->pclk); -+ device_unregister(&rk3308->dev); -+ -+ return ret; -+} -+ -+static void rk3308_platform_remove(struct platform_device *pdev) -+{ -+ struct rk3308_codec_priv *rk3308 = -+ (struct rk3308_codec_priv *)platform_get_drvdata(pdev); -+ -+ clk_disable_unprepare(rk3308->mclk_rx); -+ clk_disable_unprepare(rk3308->mclk_tx); -+ clk_disable_unprepare(rk3308->pclk); -+ device_unregister(&rk3308->dev); -+ -+ return; - } - --static const struct of_device_id __maybe_unused rk3308_codec_of_match[] = { -+static const struct of_device_id rk3308codec_of_match[] = { - { .compatible = "rockchip,rk3308-codec", }, - {}, - }; --MODULE_DEVICE_TABLE(of, rk3308_codec_of_match); -+MODULE_DEVICE_TABLE(of, rk3308codec_of_match); - - static struct platform_driver rk3308_codec_driver = { - .driver = { -- .name = "rk3308-acodec", -- .of_match_table = rk3308_codec_of_match, -+ .name = CODEC_DRV_NAME, -+ .of_match_table = of_match_ptr(rk3308codec_of_match), - }, -- .probe = rk3308_codec_platform_probe, -+ .probe = rk3308_platform_probe, -+ .remove = rk3308_platform_remove, - }; - module_platform_driver(rk3308_codec_driver); - - MODULE_AUTHOR("Xing Zheng "); --MODULE_AUTHOR("Luca Ceresoli "); - MODULE_DESCRIPTION("ASoC RK3308 Codec Driver"); --MODULE_LICENSE("GPL"); -+MODULE_LICENSE("GPL v2"); -diff --git a/sound/soc/codecs/rk3308_codec.h b/sound/soc/codecs/rk3308_codec.h -index 111111111111..222222222222 100644 ---- a/sound/soc/codecs/rk3308_codec.h -+++ b/sound/soc/codecs/rk3308_codec.h -@@ -1,15 +1,114 @@ --/* SPDX-License-Identifier: GPL-2.0-only */ - /* -- * Rockchip RK3308 internal audio codec driver -- register definitions -+ * rk3308_codec.h -- RK3308 ALSA Soc Audio Driver - * - * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. -- * Copyright (c) 2022, Vivax-Metrotech Ltd -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ * - */ - - #ifndef __RK3308_CODEC_H__ - #define __RK3308_CODEC_H__ - --#define RK3308_GLB_CON 0x00 -+#define ACODEC_RESET_CTL 0x00 /* REG 0x00 */ -+ -+/* ADC DIGITAL REGISTERS */ -+#define ACODEC_ADC_I2S_CTL0 0x04 /* REG 0x01 */ -+#define ACODEC_ADC_I2S_CTL1 0x08 /* REG 0x02 */ -+#define ACODEC_ADC_BIST_MODE_SEL 0x0c /* REG 0x03 */ -+#define ACODEC_ADC_HPF_PATH 0x10 /* REG 0x04 */ -+/* Resevred REG 0x05 ~ 0x06 */ -+#define ACODEC_ADC_DATA_PATH 0x1c /* REG 0x07 */ -+/* Resevred REG 0x08 ~ 0x0f */ -+ -+/* REG 0x10 ~ 0x1c are used to configure AGC of Left channel (ALC1) */ -+#define ACODEC_ADC_PGA_AGC_L_CTL0 0x40 /* REG 0x10 */ -+#define ACODEC_ADC_PGA_AGC_L_CTL1 0x44 /* REG 0x11 */ -+#define ACODEC_ADC_PGA_AGC_L_CTL2 0x48 /* REG 0x12 */ -+#define ACODEC_ADC_PGA_AGC_L_CTL3 0x4c /* REG 0x13 */ -+#define ACODEC_ADC_PGA_AGC_L_CTL4 0x50 /* REG 0x14 */ -+#define ACODEC_ADC_PGA_AGC_L_LO_MAX 0x54 /* REG 0x15 */ -+#define ACODEC_ADC_PGA_AGC_L_HI_MAX 0x58 /* REG 0x16 */ -+#define ACODEC_ADC_PGA_AGC_L_LO_MIN 0x5c /* REG 0x17 */ -+#define ACODEC_ADC_PGA_AGC_L_HI_MIN 0x60 /* REG 0x18 */ -+#define ACODEC_ADC_PGA_AGC_L_CTL5 0x64 /* REG 0x19 */ -+/* Resevred REG 0x1a ~ 0x1b */ -+#define ACODEC_ADC_AGC_L_RO_GAIN 0x70 /* REG 0x1c */ -+ -+/* REG 0x20 ~ 0x2c are used to configure AGC of Right channel (ALC2) */ -+#define ACODEC_ADC_PGA_AGC_R_CTL0 0x80 /* REG 0x20 */ -+#define ACODEC_ADC_PGA_AGC_R_CTL1 0x84 /* REG 0x21 */ -+#define ACODEC_ADC_PGA_AGC_R_CTL2 0x88 /* REG 0x22 */ -+#define ACODEC_ADC_PGA_AGC_R_CTL3 0x8c /* REG 0x23 */ -+#define ACODEC_ADC_PGA_AGC_R_CTL4 0x90 /* REG 0x24 */ -+#define ACODEC_ADC_PGA_AGC_R_LO_MAX 0x94 /* REG 0x25 */ -+#define ACODEC_ADC_PGA_AGC_R_HI_MAX 0x98 /* REG 0x26 */ -+#define ACODEC_ADC_PGA_AGC_R_LO_MIN 0x9c /* REG 0x27 */ -+#define ACODEC_ADC_PGA_AGC_R_HI_MIN 0xa0 /* REG 0x28 */ -+#define ACODEC_ADC_PGA_AGC_R_CTL5 0xa4 /* REG 0x29 */ -+/* Resevred REG 0x2a ~ 0x2b */ -+#define ACODEC_ADC_AGC_R_RO_GAIN 0xb0 /* REG 0x2c */ -+ -+/* DAC DIGITAL REGISTERS */ -+#define ACODEC_DAC_I2S_CTL0 0x04 /* REG 0x01 */ -+#define ACODEC_DAC_I2S_CTL1 0x08 /* REG 0x02 */ -+#define ACODEC_DAC_BIST_MODE_SEL 0x0c /* REG 0x03 */ -+#define ACODEC_DAC_DIGITAL_GAIN 0x10 /* REG 0x04 */ -+#define ACODEC_DAC_DATA_SEL 0x14 /* REG 0x05 */ -+/* Resevred REG 0x06 ~ 0x09 */ -+#define ACODEC_DAC_DATA_HI 0x28 /* REG 0x0a */ -+#define ACODEC_DAC_DATA_LO 0x2c /* REG 0x0b */ -+/* Resevred REG 0x0c */ -+#define ACODEC_DAC_HPDET_DELAYTIME 0x34 /* REG 0x0d */ -+#define ACODEC_DAC_HPDET_STATUS 0x38 /* REG 0x0e, Read-only */ -+/* Resevred REG 0x0f */ -+ -+/* ADC ANALOG REGISTERS */ -+#define ACODEC_ADC_ANA_MIC_CTL 0x00 /* REG 0x00 */ -+#define ACODEC_ADC_ANA_MIC_GAIN 0x04 /* REG 0x01 */ -+#define ACODEC_ADC_ANA_ALC_CTL 0x08 /* REG 0x02 */ -+#define ACODEC_ADC_ANA_ALC_GAIN1 0x0c /* REG 0x03 */ -+#define ACODEC_ADC_ANA_ALC_GAIN2 0x10 /* REG 0x04 */ -+#define ACODEC_ADC_ANA_CTL0 0x14 /* REG 0x05 */ -+#define ACODEC_ADC_ANA_CTL1 0x18 /* REG 0x06 */ -+#define ACODEC_ADC_ANA_CTL2 0x1c /* REG 0x07 */ -+#define ACODEC_ADC_ANA_CTL3 0x20 /* REG 0x08 */ -+/* Resevred REG 0x09 */ -+#define ACODEC_ADC_ANA_CTL4 0x28 /* REG 0x0a */ -+#define ACODEC_ADC_ANA_ALC_PGA 0x2c /* REG 0x0b */ -+/* Resevred REG 0x0c ~ 0x0f */ -+ -+/* DAC ANALOG REGISTERS */ -+#define ACODEC_DAC_ANA_CTL0 0x00 /* REG 0x00 */ -+#define ACODEC_DAC_ANA_POP_VOLT 0x04 /* REG 0x01 */ -+#define ACODEC_DAC_ANA_CTL1 0x08 /* REG 0x02 */ -+#define ACODEC_DAC_ANA_HPOUT 0x0c /* REG 0x03 */ -+#define ACODEC_DAC_ANA_LINEOUT 0x10 /* REG 0x04 */ -+#define ACODEC_DAC_ANA_L_HPOUT_GAIN 0x14 /* REG 0x05 */ -+#define ACODEC_DAC_ANA_R_HPOUT_GAIN 0x18 /* REG 0x06 */ -+#define ACODEC_DAC_ANA_DRV_HPOUT 0x1c /* REG 0x07 */ -+#define ACODEC_DAC_ANA_DRV_LINEOUT 0x20 /* REG 0x08 */ -+/* Resevred REG 0x07 ~ 0x0b */ -+#define ACODEC_DAC_ANA_HPMIX_CTL0 0x30 /* REG 0x0c */ -+#define ACODEC_DAC_ANA_HPMIX_CTL1 0x34 /* REG 0x0d */ -+#define ACODEC_DAC_ANA_LINEOUT_CTL0 0x38 /* REG 0x0e */ -+#define ACODEC_DAC_ANA_LINEOUT_CTL1 0x3c /* REG 0x0f */ -+ -+/* -+ * These registers are referenced by codec driver -+ */ -+ -+#define RK3308_GLB_CON ACODEC_RESET_CTL - - /* ADC DIGITAL REGISTERS */ - -@@ -21,51 +120,50 @@ - * CH2: left_2(ADC5) and right_2(ADC6) - * CH3: left_3(ADC7) and right_3(ADC8) - */ --#define RK3308_ADC_DIG_OFFSET(ch) (((ch) & 0x3) * 0xc0 + 0x0) -- --#define RK3308_ADC_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x04) --#define RK3308_ADC_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x08) --#define RK3308_ADC_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x0c) --#define RK3308_ADC_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x10) --#define RK3308_ADC_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x14) // ver.C only --#define RK3308_ADC_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x18) // ver.C only --#define RK3308_ADC_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x1c) -- --#define RK3308_ALC_L_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x40) --#define RK3308_ALC_L_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x44) --#define RK3308_ALC_L_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x48) --#define RK3308_ALC_L_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x4c) --#define RK3308_ALC_L_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x50) --#define RK3308_ALC_L_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x54) --#define RK3308_ALC_L_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x58) --#define RK3308_ALC_L_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x5c) --#define RK3308_ALC_L_DIG_CON08(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x60) --#define RK3308_ALC_L_DIG_CON09(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x64) --#define RK3308_ALC_L_DIG_CON12(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x70) -- --#define RK3308_ALC_R_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x80) --#define RK3308_ALC_R_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x84) --#define RK3308_ALC_R_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x88) --#define RK3308_ALC_R_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x8c) --#define RK3308_ALC_R_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x90) --#define RK3308_ALC_R_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x94) --#define RK3308_ALC_R_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x98) --#define RK3308_ALC_R_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x9c) --#define RK3308_ALC_R_DIG_CON08(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0xa0) --#define RK3308_ALC_R_DIG_CON09(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0xa4) --#define RK3308_ALC_R_DIG_CON12(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0xb0) -+#define RK3308_ADC_DIG_OFFSET(ch) ((ch & 0x3) * 0xc0 + 0x0) -+ -+#define RK3308_ADC_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL0) -+#define RK3308_ADC_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL1) -+#define RK3308_ADC_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_BIST_MODE_SEL) -+#define RK3308_ADC_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_HPF_PATH) -+#define RK3308_ADC_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH) -+ -+#define RK3308_ALC_L_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL0) -+#define RK3308_ALC_L_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL1) -+#define RK3308_ALC_L_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL2) -+#define RK3308_ALC_L_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL3) -+#define RK3308_ALC_L_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL4) -+#define RK3308_ALC_L_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MAX) -+#define RK3308_ALC_L_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MAX) -+#define RK3308_ALC_L_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MIN) -+#define RK3308_ALC_L_DIG_CON08(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MIN) -+#define RK3308_ALC_L_DIG_CON09(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL5) -+#define RK3308_ALC_L_DIG_CON12(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_L_RO_GAIN) -+ -+#define RK3308_ALC_R_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL0) -+#define RK3308_ALC_R_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL1) -+#define RK3308_ALC_R_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL2) -+#define RK3308_ALC_R_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL3) -+#define RK3308_ALC_R_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL4) -+#define RK3308_ALC_R_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MAX) -+#define RK3308_ALC_R_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MAX) -+#define RK3308_ALC_R_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MIN) -+#define RK3308_ALC_R_DIG_CON08(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MIN) -+#define RK3308_ALC_R_DIG_CON09(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL5) -+#define RK3308_ALC_R_DIG_CON12(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_R_RO_GAIN) - - /* DAC DIGITAL REGISTERS */ - #define RK3308_DAC_DIG_OFFSET 0x300 --#define RK3308_DAC_DIG_CON01 (RK3308_DAC_DIG_OFFSET + 0x04) --#define RK3308_DAC_DIG_CON02 (RK3308_DAC_DIG_OFFSET + 0x08) --#define RK3308_DAC_DIG_CON03 (RK3308_DAC_DIG_OFFSET + 0x0c) --#define RK3308_DAC_DIG_CON04 (RK3308_DAC_DIG_OFFSET + 0x10) --#define RK3308_DAC_DIG_CON05 (RK3308_DAC_DIG_OFFSET + 0x14) --#define RK3308_DAC_DIG_CON10 (RK3308_DAC_DIG_OFFSET + 0x28) --#define RK3308_DAC_DIG_CON11 (RK3308_DAC_DIG_OFFSET + 0x2c) --#define RK3308_DAC_DIG_CON13 (RK3308_DAC_DIG_OFFSET + 0x34) --#define RK3308_DAC_DIG_CON14 (RK3308_DAC_DIG_OFFSET + 0x38) -+ -+#define RK3308_DAC_DIG_CON01 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL0) -+#define RK3308_DAC_DIG_CON02 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL1) -+#define RK3308_DAC_DIG_CON03 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_BIST_MODE_SEL) -+#define RK3308_DAC_DIG_CON04 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DIGITAL_GAIN) -+#define RK3308_DAC_DIG_CON05 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_SEL) -+#define RK3308_DAC_DIG_CON10 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_HI) -+#define RK3308_DAC_DIG_CON11 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_LO) -+#define RK3308_DAC_DIG_CON13 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_DELAYTIME) -+#define RK3308_DAC_DIG_CON14 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_STATUS) - - /* ADC ANALOG REGISTERS */ - /* -@@ -76,50 +174,63 @@ - * CH2: left_2(ADC5) and right_2(ADC6) - * CH3: left_3(ADC7) and right_3(ADC8) - */ --#define RK3308_ADC_ANA_OFFSET(ch) (((ch) & 0x3) * 0x40 + 0x340) --#define RK3308_ADC_ANA_CON00(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x00) --#define RK3308_ADC_ANA_CON01(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x04) --#define RK3308_ADC_ANA_CON02(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x08) --#define RK3308_ADC_ANA_CON03(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x0c) --#define RK3308_ADC_ANA_CON04(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x10) --#define RK3308_ADC_ANA_CON05(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x14) --#define RK3308_ADC_ANA_CON06(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x18) --#define RK3308_ADC_ANA_CON07(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x1c) --#define RK3308_ADC_ANA_CON08(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x20) --#define RK3308_ADC_ANA_CON10(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x28) --#define RK3308_ADC_ANA_CON11(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x2c) -+#define RK3308_ADC_ANA_OFFSET(ch) ((ch & 0x3) * 0x40 + 0x340) -+ -+#define RK3308_ADC_ANA_CON00(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_CTL) -+#define RK3308_ADC_ANA_CON01(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_GAIN) -+#define RK3308_ADC_ANA_CON02(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_CTL) -+#define RK3308_ADC_ANA_CON03(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_GAIN1) -+#define RK3308_ADC_ANA_CON04(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_GAIN2) -+#define RK3308_ADC_ANA_CON05(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL0) -+#define RK3308_ADC_ANA_CON06(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL1) -+#define RK3308_ADC_ANA_CON07(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL2) -+#define RK3308_ADC_ANA_CON08(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL3) -+#define RK3308_ADC_ANA_CON10(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL4) -+#define RK3308_ADC_ANA_CON11(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_PGA) - - /* DAC ANALOG REGISTERS */ - #define RK3308_DAC_ANA_OFFSET 0x440 --#define RK3308_DAC_ANA_CON00 (RK3308_DAC_ANA_OFFSET + 0x00) --#define RK3308_DAC_ANA_CON01 (RK3308_DAC_ANA_OFFSET + 0x04) --#define RK3308_DAC_ANA_CON02 (RK3308_DAC_ANA_OFFSET + 0x08) --#define RK3308_DAC_ANA_CON03 (RK3308_DAC_ANA_OFFSET + 0x0c) --#define RK3308_DAC_ANA_CON04 (RK3308_DAC_ANA_OFFSET + 0x10) --#define RK3308_DAC_ANA_CON05 (RK3308_DAC_ANA_OFFSET + 0x14) --#define RK3308_DAC_ANA_CON06 (RK3308_DAC_ANA_OFFSET + 0x18) --#define RK3308_DAC_ANA_CON07 (RK3308_DAC_ANA_OFFSET + 0x1c) --#define RK3308_DAC_ANA_CON08 (RK3308_DAC_ANA_OFFSET + 0x20) --#define RK3308_DAC_ANA_CON12 (RK3308_DAC_ANA_OFFSET + 0x30) --#define RK3308_DAC_ANA_CON13 (RK3308_DAC_ANA_OFFSET + 0x34) --#define RK3308_DAC_ANA_CON14 (RK3308_DAC_ANA_OFFSET + 0x38) --#define RK3308_DAC_ANA_CON15 (RK3308_DAC_ANA_OFFSET + 0x3c) -+#define RK3308_DAC_ANA_CON00 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL0) -+#define RK3308_DAC_ANA_CON01 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_POP_VOLT) -+#define RK3308_DAC_ANA_CON02 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL1) -+#define RK3308_DAC_ANA_CON03 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPOUT) -+#define RK3308_DAC_ANA_CON04 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT) -+#define RK3308_DAC_ANA_CON05 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_L_HPOUT_GAIN) -+#define RK3308_DAC_ANA_CON06 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_R_HPOUT_GAIN) -+#define RK3308_DAC_ANA_CON07 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_DRV_HPOUT) -+#define RK3308_DAC_ANA_CON08 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_DRV_LINEOUT) -+#define RK3308_DAC_ANA_CON12 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL0) -+#define RK3308_DAC_ANA_CON13 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL1) -+#define RK3308_DAC_ANA_CON14 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT_CTL0) -+#define RK3308_DAC_ANA_CON15 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT_CTL1) - - /* - * These are the bits for registers - */ - - /* RK3308_GLB_CON - REG: 0x0000 */ --#define RK3308_ADC_BIST_WORK BIT(7) --#define RK3308_DAC_BIST_WORK BIT(6) --#define RK3308_ADC_MCLK_GATING BIT(5) --#define RK3308_DAC_MCLK_GATING BIT(4) --#define RK3308_ADC_DIG_WORK BIT(2) --#define RK3308_DAC_DIG_WORK BIT(1) --#define RK3308_SYS_WORK BIT(0) -+#define RK3308_ADC_BIST_WORK (1 << 7) -+#define RK3308_ADC_BIST_RESET (0 << 7) -+#define RK3308_DAC_BIST_WORK (1 << 6) -+#define RK3308_DAC_BIST_RESET (0 << 6) -+#define RK3308_ADC_MCLK_MSK (1 << 5) -+#define RK3308_ADC_MCLK_DIS (1 << 5) -+#define RK3308_ADC_MCLK_EN (0 << 5) -+#define RK3308_DAC_MCLK_MSK (1 << 4) -+#define RK3308_DAC_MCLK_DIS (1 << 4) -+#define RK3308_DAC_MCLK_EN (0 << 4) -+#define RK3308_CODEC_RST_MSK (0x7 << 0) -+#define RK3308_ADC_DIG_WORK (1 << 2) -+#define RK3308_ADC_DIG_RESET (0 << 2) -+#define RK3308_DAC_DIG_WORK (1 << 1) -+#define RK3308_DAC_DIG_RESET (0 << 1) -+#define RK3308_SYS_WORK (1 << 0) -+#define RK3308_SYS_RESET (0 << 0) - - /* RK3308_ADC_DIG_CON01 - REG: 0x0004 */ --#define RK3308_ADC_I2S_LRC_POL_REVERSAL BIT(7) -+#define RK3308_ADC_I2S_LRC_POL_MSK (1 << 0) -+#define RK3308_ADC_I2S_LRC_POL_REVERSAL (1 << 0) -+#define RK3308_ADC_I2S_LRC_POL_NORMAL (0 << 0) - #define RK3308_ADC_I2S_VALID_LEN_SFT 5 - #define RK3308_ADC_I2S_VALID_LEN_MSK (0x3 << RK3308_ADC_I2S_VALID_LEN_SFT) - #define RK3308_ADC_I2S_VALID_LEN_32BITS (0x3 << RK3308_ADC_I2S_VALID_LEN_SFT) -@@ -132,20 +243,32 @@ - #define RK3308_ADC_I2S_MODE_I2S (0x2 << RK3308_ADC_I2S_MODE_SFT) - #define RK3308_ADC_I2S_MODE_LJ (0x1 << RK3308_ADC_I2S_MODE_SFT) - #define RK3308_ADC_I2S_MODE_RJ (0x0 << RK3308_ADC_I2S_MODE_SFT) --#define RK3308_ADC_I2S_LR_SWAP BIT(1) --#define RK3308_ADC_I2S_MONO BIT(0) -+#define RK3308_ADC_I2S_LR_MSK (1 << 1) -+#define RK3308_ADC_I2S_LR_SWAP (1 << 1) -+#define RK3308_ADC_I2S_LR_NORMAL (0 << 1) -+#define RK3308_ADC_I2S_TYPE_MSK (1 << 0) -+#define RK3308_ADC_I2S_MONO (1 << 0) -+#define RK3308_ADC_I2S_STEREO (0 << 0) - - /* RK3308_ADC_DIG_CON02 - REG: 0x0008 */ --#define RK3308_ADC_IO_MODE_MASTER BIT(5) --#define RK3308_ADC_MODE_MASTER BIT(4) -+#define RK3308_ADC_IO_MODE_MSK (1 << 5) -+#define RK3308_ADC_IO_MODE_MASTER (1 << 5) -+#define RK3308_ADC_IO_MODE_SLAVE (0 << 5) -+#define RK3308_ADC_MODE_MSK (1 << 4) -+#define RK3308_ADC_MODE_MASTER (1 << 4) -+#define RK3308_ADC_MODE_SLAVE (0 << 4) - #define RK3308_ADC_I2S_FRAME_LEN_SFT 2 - #define RK3308_ADC_I2S_FRAME_LEN_MSK (0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT) - #define RK3308_ADC_I2S_FRAME_32BITS (0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT) - #define RK3308_ADC_I2S_FRAME_24BITS (0x2 << RK3308_ADC_I2S_FRAME_LEN_SFT) - #define RK3308_ADC_I2S_FRAME_20BITS (0x1 << RK3308_ADC_I2S_FRAME_LEN_SFT) - #define RK3308_ADC_I2S_FRAME_16BITS (0x0 << RK3308_ADC_I2S_FRAME_LEN_SFT) --#define RK3308_ADC_I2S_WORK BIT(1) --#define RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL BIT(0) -+#define RK3308_ADC_I2S_MSK (0x1 << 1) -+#define RK3308_ADC_I2S_WORK (0x1 << 1) -+#define RK3308_ADC_I2S_RESET (0x0 << 1) -+#define RK3308_ADC_I2S_BIT_CLK_POL_MSK (0x1 << 0) -+#define RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL (0x1 << 0) -+#define RK3308_ADC_I2S_BIT_CLK_POL_NORMAL (0x0 << 0) - - /* RK3308_ADC_DIG_CON03 - REG: 0x000c */ - #define RK3308_ADC_L_CH_BIST_SFT 2 -@@ -162,7 +285,10 @@ - #define RK3308_ADC_R_CH_NORMAL_RIGHT (0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */ - - /* RK3308_ADC_DIG_CON04 - REG: 0x0010 */ --#define RK3308_ADC_HPF_PATH_DIS BIT(2) -+#define RK3308_ADC_HPF_PATH_SFT 2 -+#define RK3308_ADC_HPF_PATH_MSK (1 << RK3308_ADC_HPF_PATH_SFT) -+#define RK3308_ADC_HPF_PATH_DIS (1 << RK3308_ADC_HPF_PATH_SFT) -+#define RK3308_ADC_HPF_PATH_EN (0 << RK3308_ADC_HPF_PATH_SFT) - #define RK3308_ADC_HPF_CUTOFF_SFT 0 - #define RK3308_ADC_HPF_CUTOFF_MSK (0x3 << RK3308_ADC_HPF_CUTOFF_SFT) - #define RK3308_ADC_HPF_CUTOFF_612HZ (0x2 << RK3308_ADC_HPF_CUTOFF_SFT) -@@ -171,15 +297,20 @@ - - /* RK3308_ADC_DIG_CON07 - REG: 0x001c */ - #define RK3308_ADCL_DATA_SFT 4 -+#define RK3308_ADCL_DATA(x) (x << RK3308_ADCL_DATA_SFT) - #define RK3308_ADCR_DATA_SFT 2 --#define RK3308_ADCL_DATA_SEL_ADCL BIT(1) --#define RK3308_ADCR_DATA_SEL_ADCR BIT(0) -+#define RK3308_ADCR_DATA(x) (x << RK3308_ADCR_DATA_SFT) -+#define RK3308_ADCL_DATA_SEL_ADCL (0x1 << 1) -+#define RK3308_ADCL_DATA_SEL_NORMAL (0x0 << 1) -+#define RK3308_ADCR_DATA_SEL_ADCR (0x1 << 0) -+#define RK3308_ADCR_DATA_SEL_NORMAL (0x0 << 0) - - /* - * RK3308_ALC_L_DIG_CON00 - REG: 0x0040 + ch * 0xc0 - * RK3308_ALC_R_DIG_CON00 - REG: 0x0080 + ch * 0xc0 - */ --#define RK3308_GAIN_ATTACK_JACK BIT(6) -+#define RK3308_GAIN_ATTACK_JACK (0x1 << 6) -+#define RK3308_GAIN_ATTACK_NORMAL (0x0 << 6) - #define RK3308_CTRL_GEN_SFT 4 - #define RK3308_CTRL_GEN_MSK (0x3 << RK3308_ALC_CTRL_GEN_SFT) - #define RK3308_CTRL_GEN_JACK3 (0x3 << RK3308_ALC_CTRL_GEN_SFT) -@@ -205,36 +336,145 @@ - * RK3308_ALC_R_DIG_CON01 - REG: 0x0084 + ch * 0xc0 - */ - #define RK3308_AGC_DECAY_TIME_SFT 4 -+/* Normal mode (reg_agc_mode = 0) */ -+#define RK3308_AGC_DECAY_NORMAL_MSK (0xf << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_512MS (0xa << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_256MS (0x9 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_128MS (0x8 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_64MS (0x7 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_32MS (0x6 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_16MS (0x5 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_8MS (0x4 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_4MS (0x3 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_2MS (0x2 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_1MS (0x1 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_NORMAL_0MS (0x0 << RK3308_AGC_DECAY_TIME_SFT) -+/* Limiter mode (reg_agc_mode = 1) */ -+#define RK3308_AGC_DECAY_LIMITER_MSK (0xf << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_128MS (0xa << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_64MS (0x9 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_32MS (0x8 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_16MS (0x7 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_8MS (0x6 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_4MS (0x5 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_2MS (0x4 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_1MS (0x3 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_500US (0x2 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_250US (0x1 << RK3308_AGC_DECAY_TIME_SFT) -+#define RK3308_AGC_DECAY_LIMITER_125US (0x0 << RK3308_AGC_DECAY_TIME_SFT) -+ - #define RK3308_AGC_ATTACK_TIME_SFT 0 -+/* Normal mode (reg_agc_mode = 0) */ -+#define RK3308_AGC_ATTACK_NORMAL_MSK (0xf << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_128MS (0xa << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_64MS (0x9 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_32MS (0x8 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_16MS (0x7 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_8MS (0x6 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_4MS (0x5 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_2MS (0x4 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_1MS (0x3 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_500US (0x2 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_250US (0x1 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_NORMAL_125US (0x0 << RK3308_AGC_ATTACK_TIME_SFT) -+/* Limiter mode (reg_agc_mode = 1) */ -+#define RK3308_AGC_ATTACK_LIMITER_MSK (0xf << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_32MS (0xa << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_16MS (0x9 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_8MS (0x8 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_4MS (0x7 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_2MS (0x6 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_1MS (0x5 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_500US (0x4 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_250US (0x3 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_125US (0x2 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_64US (0x1 << RK3308_AGC_ATTACK_TIME_SFT) -+#define RK3308_AGC_ATTACK_LIMITER_32US (0x0 << RK3308_AGC_ATTACK_TIME_SFT) - - /* - * RK3308_ALC_L_DIG_CON02 - REG: 0x0048 + ch * 0xc0 - * RK3308_ALC_R_DIG_CON02 - REG: 0x0088 + ch * 0xc0 - */ --#define RK3308_AGC_MODE_LIMITER BIT(7) --#define RK3308_AGC_ZERO_CRO_EN BIT(6) --#define RK3308_AGC_AMP_RECOVER_GAIN BIT(5) --#define RK3308_AGC_FAST_DEC_EN BIT(4) --#define RK3308_AGC_NOISE_GATE_EN BIT(3) -+#define RK3308_AGC_MODE_LIMITER (0x1 << 7) -+#define RK3308_AGC_MODE_NORMAL (0x0 << 7) -+#define RK3308_AGC_ZERO_CRO_EN (0x1 << 6) -+#define RK3308_AGC_ZERO_CRO_DIS (0x0 << 6) -+#define RK3308_AGC_AMP_RECOVER_GAIN (0x1 << 5) -+#define RK3308_AGC_AMP_RECOVER_LVOL (0x0 << 5) -+#define RK3308_AGC_FAST_DEC_EN (0x1 << 4) -+#define RK3308_AGC_FAST_DEC_DIS (0x0 << 4) -+#define RK3308_AGC_NOISE_GATE_EN (0x1 << 3) -+#define RK3308_AGC_NOISE_GATE_DIS (0x0 << 3) - #define RK3308_AGC_NOISE_GATE_THRESH_SFT 0 - #define RK3308_AGC_NOISE_GATE_THRESH_MSK (0x7 << RK3308_AGC_NOISE_GATE_THRESH_SFT) -+#define RK3308_AGC_NOISE_GATE_THRESH_N81DB (0x7 << RK3308_AGC_NOISE_GATE_THRESH_SFT) -+#define RK3308_AGC_NOISE_GATE_THRESH_N75DB (0x6 << RK3308_AGC_NOISE_GATE_THRESH_SFT) -+#define RK3308_AGC_NOISE_GATE_THRESH_N69DB (0x5 << RK3308_AGC_NOISE_GATE_THRESH_SFT) -+#define RK3308_AGC_NOISE_GATE_THRESH_N63DB (0x4 << RK3308_AGC_NOISE_GATE_THRESH_SFT) -+#define RK3308_AGC_NOISE_GATE_THRESH_N57DB (0x3 << RK3308_AGC_NOISE_GATE_THRESH_SFT) -+#define RK3308_AGC_NOISE_GATE_THRESH_N51DB (0x2 << RK3308_AGC_NOISE_GATE_THRESH_SFT) -+#define RK3308_AGC_NOISE_GATE_THRESH_N45DB (0x1 << RK3308_AGC_NOISE_GATE_THRESH_SFT) -+#define RK3308_AGC_NOISE_GATE_THRESH_N39DB (0x0 << RK3308_AGC_NOISE_GATE_THRESH_SFT) - - /* - * RK3308_ALC_L_DIG_CON03 - REG: 0x004c + ch * 0xc0 - * RK3308_ALC_R_DIG_CON03 - REG: 0x008c + ch * 0xc0 - */ --#define RK3308_AGC_PGA_ZERO_CRO_EN BIT(5) -+#define RK3308_AGC_PGA_ZERO_CRO_EN (0x1 << 5) -+#define RK3308_AGC_PGA_ZERO_CRO_DIS (0x0 << 5) - #define RK3308_AGC_PGA_GAIN_MAX 0x1f - #define RK3308_AGC_PGA_GAIN_MIN 0 - #define RK3308_AGC_PGA_GAIN_SFT 0 -+#define RK3308_AGC_PGA_GAIN_MSK (0x1f << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_28_5 (0x1f << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_27 (0x1e << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_25_5 (0x1d << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_24 (0x1c << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_22_5 (0x1b << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_21 (0x1a << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_19_5 (0x19 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_18 (0x18 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_16_5 (0x17 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_15 (0x16 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_13_5 (0x15 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_12 (0x14 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_10_5 (0x13 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_9 (0x12 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_7_5 (0x11 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_6 (0x10 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_4_5 (0x0f << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_3 (0x0e << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_PDB_1_5 (0x0d << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_0DB (0x0c << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_1_5 (0x0b << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_3 (0x0a << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_4_5 (0x09 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_6 (0x08 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_7_5 (0x07 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_9 (0x06 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_10_5 (0x05 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_12 (0x04 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_13_5 (0x03 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_15 (0x02 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_16_5 (0x01 << RK3308_AGC_PGA_GAIN_SFT) -+#define RK3308_AGC_PGA_GAIN_NDB_18 (0x00 << RK3308_AGC_PGA_GAIN_SFT) - - /* - * RK3308_ALC_L_DIG_CON04 - REG: 0x0050 + ch * 0xc0 - * RK3308_ALC_R_DIG_CON04 - REG: 0x0090 + ch * 0xc0 - */ --#define RK3308_AGC_SLOW_CLK_EN BIT(3) -+#define RK3308_AGC_SLOW_CLK_EN (0x1 << 3) -+#define RK3308_AGC_SLOW_CLK_DIS (0x0 << 3) - #define RK3308_AGC_APPROX_RATE_SFT 0 - #define RK3308_AGC_APPROX_RATE_MSK (0x7 << RK3308_AGC_APPROX_RATE_SFT) -+#define RK3308_AGC_APPROX_RATE_8K (0x7 << RK3308_AGC_APPROX_RATE_SFT) -+#define RK3308_AGC_APPROX_RATE_12K (0x6 << RK3308_AGC_APPROX_RATE_SFT) -+#define RK3308_AGC_APPROX_RATE_16K (0x5 << RK3308_AGC_APPROX_RATE_SFT) -+#define RK3308_AGC_APPROX_RATE_24K (0x4 << RK3308_AGC_APPROX_RATE_SFT) -+#define RK3308_AGC_APPROX_RATE_32K (0x3 << RK3308_AGC_APPROX_RATE_SFT) -+#define RK3308_AGC_APPROX_RATE_44_1K (0x2 << RK3308_AGC_APPROX_RATE_SFT) -+#define RK3308_AGC_APPROX_RATE_48K (0x1 << RK3308_AGC_APPROX_RATE_SFT) -+#define RK3308_AGC_APPROX_RATE_96K (0x0 << RK3308_AGC_APPROX_RATE_SFT) - - /* - * RK3308_ALC_L_DIG_CON05 - REG: 0x0054 + ch * 0xc0 -@@ -264,15 +504,33 @@ - * RK3308_ALC_L_DIG_CON09 - REG: 0x0064 + ch * 0xc0 - * RK3308_ALC_R_DIG_CON09 - REG: 0x00a4 + ch * 0xc0 - */ --#define RK3308_AGC_FUNC_SEL BIT(6) -+#define RK3308_AGC_FUNC_SEL_MSK (0x1 << 6) -+#define RK3308_AGC_FUNC_SEL_EN (0x1 << 6) -+#define RK3308_AGC_FUNC_SEL_DIS (0x0 << 6) - #define RK3308_AGC_MAX_GAIN_PGA_MAX 0x7 - #define RK3308_AGC_MAX_GAIN_PGA_MIN 0 - #define RK3308_AGC_MAX_GAIN_PGA_SFT 3 - #define RK3308_AGC_MAX_GAIN_PGA_MSK (0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT) -+#define RK3308_AGC_MAX_GAIN_PGA_PDB_28_5 (0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT) -+#define RK3308_AGC_MAX_GAIN_PGA_PDB_22_5 (0x6 << RK3308_AGC_MAX_GAIN_PGA_SFT) -+#define RK3308_AGC_MAX_GAIN_PGA_PDB_16_5 (0x5 << RK3308_AGC_MAX_GAIN_PGA_SFT) -+#define RK3308_AGC_MAX_GAIN_PGA_PDB_10_5 (0x4 << RK3308_AGC_MAX_GAIN_PGA_SFT) -+#define RK3308_AGC_MAX_GAIN_PGA_PDB_4_5 (0x3 << RK3308_AGC_MAX_GAIN_PGA_SFT) -+#define RK3308_AGC_MAX_GAIN_PGA_NDB_1_5 (0x2 << RK3308_AGC_MAX_GAIN_PGA_SFT) -+#define RK3308_AGC_MAX_GAIN_PGA_NDB_7_5 (0x1 << RK3308_AGC_MAX_GAIN_PGA_SFT) -+#define RK3308_AGC_MAX_GAIN_PGA_NDB_13_5 (0x0 << RK3308_AGC_MAX_GAIN_PGA_SFT) - #define RK3308_AGC_MIN_GAIN_PGA_MAX 0x7 - #define RK3308_AGC_MIN_GAIN_PGA_MIN 0 - #define RK3308_AGC_MIN_GAIN_PGA_SFT 0 - #define RK3308_AGC_MIN_GAIN_PGA_MSK (0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT) -+#define RK3308_AGC_MIN_GAIN_PGA_PDB_24 (0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT) -+#define RK3308_AGC_MIN_GAIN_PGA_PDB_18 (0x6 << RK3308_AGC_MIN_GAIN_PGA_SFT) -+#define RK3308_AGC_MIN_GAIN_PGA_PDB_12 (0x5 << RK3308_AGC_MIN_GAIN_PGA_SFT) -+#define RK3308_AGC_MIN_GAIN_PGA_PDB_6 (0x4 << RK3308_AGC_MIN_GAIN_PGA_SFT) -+#define RK3308_AGC_MIN_GAIN_PGA_0DB (0x3 << RK3308_AGC_MIN_GAIN_PGA_SFT) -+#define RK3308_AGC_MIN_GAIN_PGA_NDB_6 (0x2 << RK3308_AGC_MIN_GAIN_PGA_SFT) -+#define RK3308_AGC_MIN_GAIN_PGA_NDB_12 (0x1 << RK3308_AGC_MIN_GAIN_PGA_SFT) -+#define RK3308_AGC_MIN_GAIN_PGA_NDB_18 (0x0 << RK3308_AGC_MIN_GAIN_PGA_SFT) - - /* - * RK3308_ALC_L_DIG_CON12 - REG: 0x0068 + ch * 0xc0 -@@ -281,7 +539,9 @@ - #define RK3308_AGC_GAIN_MSK 0x1f - - /* RK3308_DAC_DIG_CON01 - REG: 0x0304 */ --#define RK3308_DAC_I2S_LRC_POL_REVERSAL BIT(7) -+#define RK3308_DAC_I2S_LRC_POL_MSK (0x1 << 7) -+#define RK3308_DAC_I2S_LRC_POL_REVERSAL (0x1 << 7) -+#define RK3308_DAC_I2S_LRC_POL_NORMAL (0x0 << 7) - #define RK3308_DAC_I2S_VALID_LEN_SFT 5 - #define RK3308_DAC_I2S_VALID_LEN_MSK (0x3 << RK3308_DAC_I2S_VALID_LEN_SFT) - #define RK3308_DAC_I2S_VALID_LEN_32BITS (0x3 << RK3308_DAC_I2S_VALID_LEN_SFT) -@@ -294,21 +554,29 @@ - #define RK3308_DAC_I2S_MODE_I2S (0x2 << RK3308_DAC_I2S_MODE_SFT) - #define RK3308_DAC_I2S_MODE_LJ (0x1 << RK3308_DAC_I2S_MODE_SFT) - #define RK3308_DAC_I2S_MODE_RJ (0x0 << RK3308_DAC_I2S_MODE_SFT) --#define RK3308_DAC_I2S_LR_SWAP BIT(2) -+#define RK3308_DAC_I2S_LR_MSK (0x1 << 2) -+#define RK3308_DAC_I2S_LR_SWAP (0x1 << 2) -+#define RK3308_DAC_I2S_LR_NORMAL (0x0 << 2) - - /* RK3308_DAC_DIG_CON02 - REG: 0x0308 */ --#define RK3308BS_DAC_IO_MODE_MASTER BIT(7) --#define RK3308BS_DAC_MODE_MASTER BIT(6) --#define RK3308_DAC_IO_MODE_MASTER BIT(5) --#define RK3308_DAC_MODE_MASTER BIT(4) -+#define RK3308_DAC_IO_MODE_MSK (0x1 << 5) -+#define RK3308_DAC_IO_MODE_MASTER (0x1 << 5) -+#define RK3308_DAC_IO_MODE_SLAVE (0x0 << 5) -+#define RK3308_DAC_MODE_MSK (0x1 << 4) -+#define RK3308_DAC_MODE_MASTER (0x1 << 4) -+#define RK3308_DAC_MODE_SLAVE (0x0 << 4) - #define RK3308_DAC_I2S_FRAME_LEN_SFT 2 - #define RK3308_DAC_I2S_FRAME_LEN_MSK (0x3 << RK3308_DAC_I2S_FRAME_LEN_SFT) - #define RK3308_DAC_I2S_FRAME_32BITS (0x3 << RK3308_DAC_I2S_FRAME_LEN_SFT) - #define RK3308_DAC_I2S_FRAME_24BITS (0x2 << RK3308_DAC_I2S_FRAME_LEN_SFT) - #define RK3308_DAC_I2S_FRAME_20BITS (0x1 << RK3308_DAC_I2S_FRAME_LEN_SFT) - #define RK3308_DAC_I2S_FRAME_16BITS (0x0 << RK3308_DAC_I2S_FRAME_LEN_SFT) --#define RK3308_DAC_I2S_WORK BIT(1) --#define RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL BIT(0) -+#define RK3308_DAC_I2S_MSK (0x1 << 1) -+#define RK3308_DAC_I2S_WORK (0x1 << 1) -+#define RK3308_DAC_I2S_RESET (0x0 << 1) -+#define RK3308_DAC_I2S_BIT_CLK_POL_MSK (0x1 << 0) -+#define RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL (0x1 << 0) -+#define RK3308_DAC_I2S_BIT_CLK_POL_NORMAL (0x0 << 0) - - /* RK3308_DAC_DIG_CON03 - REG: 0x030C */ - #define RK3308_DAC_L_CH_BIST_SFT 2 -@@ -325,62 +593,64 @@ - #define RK3308_DAC_R_CH_BIST_RIGHT (0x0 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */ - - /* RK3308_DAC_DIG_CON04 - REG: 0x0310 */ --/* Versions up to B: */ - #define RK3308_DAC_MODULATOR_GAIN_SFT 4 - #define RK3308_DAC_MODULATOR_GAIN_MSK (0x7 << RK3308_DAC_MODULATOR_GAIN_SFT) -+#define RK3308_DAC_MODULATOR_GAIN_4_8DB (0x5 << RK3308_DAC_MODULATOR_GAIN_SFT) -+#define RK3308_DAC_MODULATOR_GAIN_4_2DB (0x4 << RK3308_DAC_MODULATOR_GAIN_SFT) -+#define RK3308_DAC_MODULATOR_GAIN_3_5DB (0x3 << RK3308_DAC_MODULATOR_GAIN_SFT) -+#define RK3308_DAC_MODULATOR_GAIN_2_8DB (0x2 << RK3308_DAC_MODULATOR_GAIN_SFT) -+#define RK3308_DAC_MODULATOR_GAIN_2DB (0x1 << RK3308_DAC_MODULATOR_GAIN_SFT) -+#define RK3308_DAC_MODULATOR_GAIN_0DB (0x0 << RK3308_DAC_MODULATOR_GAIN_SFT) - #define RK3308_DAC_CIC_IF_GAIN_SFT 0 - #define RK3308_DAC_CIC_IF_GAIN_MSK (0x7 << RK3308_DAC_CIC_IF_GAIN_SFT) --/* Version C: */ --#define RK3308BS_DAC_DIG_GAIN_SFT 0 --#define RK3308BS_DAC_DIG_GAIN_MSK (0xff << RK3308BS_DAC_DIG_GAIN_SFT) --#define RK3308BS_DAC_DIG_GAIN_0DB (0xed << RK3308BS_DAC_DIG_GAIN_SFT) -- --/* RK3308BS_ADC_DIG_CON05..06 (Version C only) */ --#define RK3308_ADC_DIG_VOL_CON_x_SFT 0 --#define RK3308_ADC_DIG_VOL_CON_x_MSK (0xff << RK3308_ADC_DIG_VOL_CON_x_SFT) --#define RK3308_ADC_DIG_VOL_CON_x_0DB (0xc2 << RK3308_ADC_DIG_VOL_CON_x_SFT) - - /* RK3308_DAC_DIG_CON05 - REG: 0x0314 */ --#define RK3308_DAC_L_REG_CTL_INDATA BIT(2) --#define RK3308_DAC_R_REG_CTL_INDATA BIT(1) -+#define RK3308_DAC_L_REG_CTL_INDATA (0x1 << 2) -+#define RK3308_DAC_L_NORMAL_DATA (0x0 << 2) -+#define RK3308_DAC_R_REG_CTL_INDATA (0x1 << 1) -+#define RK3308_DAC_R_NORMAL_DATA (0x0 << 1) - - /* RK3308_DAC_DIG_CON10 - REG: 0x0328 */ --#define RK3308_DAC_DATA_HI4(x) ((x) & 0xf) -+#define RK3308_DAC_DATA_HI4(x) (x & 0xf) /* Need to RK3308_DAC_x_REG_CTL_INDATA */ - - /* RK3308_DAC_DIG_CON11 - REG: 0x032c */ --#define RK3308_DAC_DATA_LO8(x) ((x) & 0xff) -+#define RK3308_DAC_DATA_LO8(x) (x & 0xff) /* Need to RK3308_DAC_x_REG_CTL_INDATA */ - - /* RK3308_ADC_ANA_CON00 - REG: 0x0340 */ - #define RK3308_ADC_CH1_CH2_MIC_ALL_MSK (0xff << 0) - #define RK3308_ADC_CH1_CH2_MIC_ALL 0xff --#define RK3308_ADC_CH2_MIC_UNMUTE BIT(7) --#define RK3308_ADC_CH2_MIC_WORK BIT(6) --#define RK3308_ADC_CH2_MIC_EN BIT(5) --#define RK3308_ADC_CH2_BUF_REF_EN BIT(4) --#define RK3308_ADC_CH1_MIC_UNMUTE BIT(3) --#define RK3308_ADC_CH1_MIC_WORK BIT(2) --#define RK3308_ADC_CH1_MIC_EN BIT(1) --#define RK3308_ADC_CH1_BUF_REF_EN BIT(0) -+#define RK3308_ADC_CH2_MIC_UNMUTE (0x1 << 7) -+#define RK3308_ADC_CH2_MIC_MUTE (0x0 << 7) -+#define RK3308_ADC_CH2_MIC_WORK (0x1 << 6) -+#define RK3308_ADC_CH2_MIC_INIT (0x0 << 6) -+#define RK3308_ADC_CH2_MIC_EN (0x1 << 5) -+#define RK3308_ADC_CH2_MIC_DIS (0x0 << 5) -+#define RK3308_ADC_CH2_BUF_REF_EN (0x1 << 4) -+#define RK3308_ADC_CH2_BUF_REF_DIS (0x0 << 4) -+#define RK3308_ADC_CH1_MIC_UNMUTE (0x1 << 3) -+#define RK3308_ADC_CH1_MIC_MUTE (0x0 << 3) -+#define RK3308_ADC_CH1_MIC_WORK (0x1 << 2) -+#define RK3308_ADC_CH1_MIC_INIT (0x0 << 2) -+#define RK3308_ADC_CH1_MIC_EN (0x1 << 1) -+#define RK3308_ADC_CH1_MIC_DIS (0x0 << 1) -+#define RK3308_ADC_CH1_BUF_REF_EN (0x1 << 0) -+#define RK3308_ADC_CH1_BUF_REF_DIS (0x0 << 0) - - /* RK3308_ADC_ANA_CON01 - REG: 0x0344 - * - * The PGA of MIC-INs: -- * - HW version A: -- * 0x0 - MIC1~MIC8 0 dB (recommended when ADC used as loopback) -- * 0x3 - MIC1~MIC8 20 dB (recommended when ADC used as MIC input) -- * - HW version B: -- * 0x0 - MIC1~MIC8 0 dB -- * 0x1 - MIC1~MIC8 6.6 dB -- * 0x2 - MIC1~MIC8 13 dB -- * 0x3 - MIC1~MIC8 20 dB -+ * 0x0 - MIC1~MIC8 0dB -+ * 0x1 - MIC1~MIC8 6.6dB -+ * 0x2 - MIC1~MIC8 13dB -+ * 0x3 - MIC1~MIC8 20dB - */ - #define RK3308_ADC_CH2_MIC_GAIN_MAX 0x3 - #define RK3308_ADC_CH2_MIC_GAIN_MIN 0 - #define RK3308_ADC_CH2_MIC_GAIN_SFT 4 - #define RK3308_ADC_CH2_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT) - #define RK3308_ADC_CH2_MIC_GAIN_20DB (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT) --#define RK3308_ADC_CH2_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT) --#define RK3308_ADC_CH2_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT) -+#define RK3308_ADC_CH2_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT) /* TRM: only used for version B */ -+#define RK3308_ADC_CH2_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT) /* TRM: only used for version B */ - #define RK3308_ADC_CH2_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH2_MIC_GAIN_SFT) - - #define RK3308_ADC_CH1_MIC_GAIN_MAX 0x3 -@@ -388,42 +658,124 @@ - #define RK3308_ADC_CH1_MIC_GAIN_SFT 0 - #define RK3308_ADC_CH1_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT) - #define RK3308_ADC_CH1_MIC_GAIN_20DB (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT) --#define RK3308_ADC_CH1_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT) --#define RK3308_ADC_CH1_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT) -+#define RK3308_ADC_CH1_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT) /* TRM: only used for version B */ -+#define RK3308_ADC_CH1_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT) /* TRM: only used for version B */ - #define RK3308_ADC_CH1_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH1_MIC_GAIN_SFT) - - /* RK3308_ADC_ANA_CON02 - REG: 0x0348 */ --#define RK3308_ADC_CH2_ZEROCROSS_DET_EN BIT(6) --#define RK3308_ADC_CH2_ALC_WORK BIT(5) --#define RK3308_ADC_CH2_ALC_EN BIT(4) --#define RK3308_ADC_CH1_ZEROCROSS_DET_EN BIT(2) --#define RK3308_ADC_CH1_ALC_WORK BIT(1) --#define RK3308_ADC_CH1_ALC_EN BIT(0) -+#define RK3308_ADC_CH2_ALC_ZC_MSK (0x7 << 4) -+#define RK3308_ADC_CH2_ZEROCROSS_DET_EN (0x1 << 6) -+#define RK3308_ADC_CH2_ZEROCROSS_DET_DIS (0x0 << 6) -+#define RK3308_ADC_CH2_ALC_WORK (0x1 << 5) -+#define RK3308_ADC_CH2_ALC_INIT (0x0 << 5) -+#define RK3308_ADC_CH2_ALC_EN (0x1 << 4) -+#define RK3308_ADC_CH2_ALC_DIS (0x0 << 4) -+ -+#define RK3308_ADC_CH1_ALC_ZC_MSK (0x7 << 0) -+#define RK3308_ADC_CH1_ZEROCROSS_DET_EN (0x1 << 2) -+#define RK3308_ADC_CH1_ZEROCROSS_DET_DIS (0x0 << 2) -+#define RK3308_ADC_CH1_ALC_WORK (0x1 << 1) -+#define RK3308_ADC_CH1_ALC_INIT (0x0 << 1) -+#define RK3308_ADC_CH1_ALC_EN (0x1 << 0) -+#define RK3308_ADC_CH1_ALC_DIS (0x0 << 0) - - /* RK3308_ADC_ANA_CON03 - REG: 0x034c */ - #define RK3308_ADC_CH1_ALC_GAIN_MAX 0x1f - #define RK3308_ADC_CH1_ALC_GAIN_MIN 0 - #define RK3308_ADC_CH1_ALC_GAIN_SFT 0 - #define RK3308_ADC_CH1_ALC_GAIN_MSK (0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_28_5 (0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_27 (0x1e << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_25_5 (0x1d << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_24 (0x1c << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_22_5 (0x1b << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_21 (0x1a << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_19_5 (0x19 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_18 (0x18 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_16_5 (0x17 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_15 (0x16 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_13_5 (0x15 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_12 (0x14 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_10_5 (0x13 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_9 (0x12 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_7_5 (0x11 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_6 (0x10 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_4_5 (0x0f << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_3 (0x0e << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_PDB_1_5 (0x0d << RK3308_ADC_CH1_ALC_GAIN_SFT) - #define RK3308_ADC_CH1_ALC_GAIN_0DB (0x0c << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_1_5 (0x0b << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_3 (0x0a << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_4_5 (0x09 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_6 (0x08 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_7_5 (0x07 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_9 (0x06 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_10_5 (0x05 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_12 (0x04 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_13_5 (0x03 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_15 (0x02 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_16_5 (0x01 << RK3308_ADC_CH1_ALC_GAIN_SFT) -+#define RK3308_ADC_CH1_ALC_GAIN_NDB_18 (0x00 << RK3308_ADC_CH1_ALC_GAIN_SFT) - - /* RK3308_ADC_ANA_CON04 - REG: 0x0350 */ - #define RK3308_ADC_CH2_ALC_GAIN_MAX 0x1f - #define RK3308_ADC_CH2_ALC_GAIN_MIN 0 - #define RK3308_ADC_CH2_ALC_GAIN_SFT 0 - #define RK3308_ADC_CH2_ALC_GAIN_MSK (0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_28_5 (0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_27 (0x1e << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_25_5 (0x1d << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_24 (0x1c << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_22_5 (0x1b << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_21 (0x1a << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_19_5 (0x19 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_18 (0x18 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_16_5 (0x17 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_15 (0x16 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_13_5 (0x15 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_12 (0x14 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_10_5 (0x13 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_9 (0x12 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_7_5 (0x11 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_6 (0x10 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_4_5 (0x0f << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_3 (0x0e << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_PDB_1_5 (0x0d << RK3308_ADC_CH2_ALC_GAIN_SFT) - #define RK3308_ADC_CH2_ALC_GAIN_0DB (0x0c << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_1_5 (0x0b << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_3 (0x0a << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_4_5 (0x09 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_6 (0x08 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_7_5 (0x07 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_9 (0x06 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_10_5 (0x05 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_12 (0x04 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_13_5 (0x03 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_15 (0x02 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_16_5 (0x01 << RK3308_ADC_CH2_ALC_GAIN_SFT) -+#define RK3308_ADC_CH2_ALC_GAIN_NDB_18 (0x00 << RK3308_ADC_CH2_ALC_GAIN_SFT) - - /* RK3308_ADC_ANA_CON05 - REG: 0x0354 */ --#define RK3308_ADC_CH2_ADC_WORK BIT(6) --#define RK3308_ADC_CH2_ADC_EN BIT(5) --#define RK3308_ADC_CH2_CLK_EN BIT(4) --#define RK3308_ADC_CH1_ADC_WORK BIT(2) --#define RK3308_ADC_CH1_ADC_EN BIT(1) --#define RK3308_ADC_CH1_CLK_EN BIT(0) -+#define RK3308_ADC_CH2_ADC_CLK_MSK (0x7 << 4) -+#define RK3308_ADC_CH2_ADC_WORK (0x1 << 6) -+#define RK3308_ADC_CH2_ADC_INIT (0x0 << 6) -+#define RK3308_ADC_CH2_ADC_EN (0x1 << 5) -+#define RK3308_ADC_CH2_ADC_DIS (0x0 << 5) -+#define RK3308_ADC_CH2_CLK_EN (0x1 << 4) -+#define RK3308_ADC_CH2_CLK_DIS (0x0 << 4) -+ -+#define RK3308_ADC_CH1_ADC_CLK_MSK (0x7 << 0) -+#define RK3308_ADC_CH1_ADC_WORK (0x1 << 2) -+#define RK3308_ADC_CH1_ADC_INIT (0x0 << 2) -+#define RK3308_ADC_CH1_ADC_EN (0x1 << 1) -+#define RK3308_ADC_CH1_ADC_DIS (0x0 << 1) -+#define RK3308_ADC_CH1_CLK_EN (0x1 << 0) -+#define RK3308_ADC_CH1_CLK_DIS (0x0 << 0) - - /* RK3308_ADC_ANA_CON06 - REG: 0x0358 */ --#define RK3308_ADC_CURRENT_EN BIT(0) -+#define RK3308_ADC_CURRENT_MSK (0x1 << 0) -+#define RK3308_ADC_CURRENT_EN (0x1 << 0) -+#define RK3308_ADC_CURRENT_DIS (0x0 << 0) - - /* RK3308_ADC_ANA_CON07 - REG: 0x035c */ - /* Note: The register configuration is only valid for ADC2 */ -@@ -440,80 +792,201 @@ - #define RK3308_ADC_CH1_IN_LINEIN (0x2 << RK3308_ADC_CH1_IN_SEL_SFT) - #define RK3308_ADC_CH1_IN_MIC (0x1 << RK3308_ADC_CH1_IN_SEL_SFT) - #define RK3308_ADC_CH1_IN_NONE (0x0 << RK3308_ADC_CH1_IN_SEL_SFT) --#define RK3308_ADC_MIC_BIAS_BUF_EN BIT(3) --#define RK3308_ADC_LEVEL_RANGE_MICBIAS_MAX 7 -+ -+#define RK3308_ADC_MIC_BIAS_BUF_SFT 3 -+#define RK3308_ADC_MIC_BIAS_BUF_EN (0x1 << RK3308_ADC_MIC_BIAS_BUF_SFT) -+#define RK3308_ADC_MIC_BIAS_BUF_DIS (0x0 << RK3308_ADC_MIC_BIAS_BUF_SFT) - #define RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT 0 - #define RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK (0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) -+/* -+ * The follow MICBIAS_VOLTs are based on the external reference voltage(Vref). -+ * For example, the Vref == 3.3V, the MICBIAS_VOLT_0_85 is equal: -+ * 3.3V * 0.85 = 2.805V. -+ */ -+#define RK3308_ADC_MICBIAS_VOLT_0_85 (0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) -+#define RK3308_ADC_MICBIAS_VOLT_0_8 (0x6 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) -+#define RK3308_ADC_MICBIAS_VOLT_0_75 (0x5 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) -+#define RK3308_ADC_MICBIAS_VOLT_0_7 (0x4 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) -+#define RK3308_ADC_MICBIAS_VOLT_0_65 (0x3 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) -+#define RK3308_ADC_MICBIAS_VOLT_0_6 (0x2 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) -+#define RK3308_ADC_MICBIAS_VOLT_0_55 (0x1 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) -+#define RK3308_ADC_MICBIAS_VOLT_0_5 (0x0 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) - - /* RK3308_ADC_ANA_CON08 - REG: 0x0360 */ --#define RK3308_ADC_MICBIAS_CURRENT_EN BIT(4) -+#define RK3308_ADC_MICBIAS_CURRENT_MSK (0x1 << 4) -+#define RK3308_ADC_MICBIAS_CURRENT_EN (0x1 << 4) -+#define RK3308_ADC_MICBIAS_CURRENT_DIS (0x0 << 4) - - /* RK3308_ADC_ANA_CON10 - REG: 0x0368 */ --#define RK3308_ADC_REF_EN BIT(7) -+#define RK3308_ADC_REF_EN (0x1 << 7) -+#define RK3308_ADC_REF_DIS (0x0 << 7) - #define RK3308_ADC_CURRENT_CHARGE_SFT 0 - #define RK3308_ADC_CURRENT_CHARGE_MSK (0x7f << RK3308_ADC_CURRENT_CHARGE_SFT) -+/* -+ * 1: Choose the current I -+ * 0: Don't choose the current I -+ */ -+#define RK3308_ADC_SEL_I(x) (x & 0x7f) - - /* RK3308_ADC_ANA_CON11 - REG: 0x036c */ --#define RK3308_ADC_ALCR_CON_GAIN_PGAR_EN BIT(1) --#define RK3308_ADC_ALCL_CON_GAIN_PGAL_EN BIT(0) -+#define RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK (0x1 << 1) -+#define RK3308_ADC_ALCR_CON_GAIN_PGAR_EN (0x1 << 1) -+#define RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS (0x0 << 1) -+#define RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK (0x1 << 0) -+#define RK3308_ADC_ALCL_CON_GAIN_PGAL_EN (0x1 << 0) -+#define RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS (0x0 << 0) - - /* RK3308_DAC_ANA_CON00 - REG: 0x0440 */ --#define RK3308_DAC_HEADPHONE_DET_EN BIT(1) --#define RK3308_DAC_CURRENT_EN BIT(0) -+#define RK3308_DAC_HEADPHONE_DET_MSK (0x1 << 1) -+#define RK3308_DAC_HEADPHONE_DET_EN (0x1 << 1) -+#define RK3308_DAC_HEADPHONE_DET_DIS (0x0 << 1) -+#define RK3308_DAC_CURRENT_MSK (0x1 << 0) -+#define RK3308_DAC_CURRENT_EN (0x1 << 0) -+#define RK3308_DAC_CURRENT_DIS (0x0 << 0) - - /* RK3308_DAC_ANA_CON01 - REG: 0x0444 */ --#define RK3308_DAC_BUF_REF_R_EN BIT(6) --#define RK3308_DAC_BUF_REF_L_EN BIT(2) -+#define RK3308_DAC_BUF_REF_R_MSK (0x1 << 6) -+#define RK3308_DAC_BUF_REF_R_EN (0x1 << 6) -+#define RK3308_DAC_BUF_REF_R_DIS (0x0 << 6) - #define RK3308_DAC_HPOUT_POP_SOUND_R_SFT 4 -+#define RK3308_DAC_HPOUT_POP_SOUND_R_MSK (0x3 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT) -+#define RK3308_DAC_HPOUT_POP_SOUND_R_WORK (0x2 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT) -+#define RK3308_DAC_HPOUT_POP_SOUND_R_INIT (0x1 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT) -+#define RK3308_DAC_BUF_REF_L_MSK (0x1 << 2) -+#define RK3308_DAC_BUF_REF_L_EN (0x1 << 2) -+#define RK3308_DAC_BUF_REF_L_DIS (0x0 << 2) - #define RK3308_DAC_HPOUT_POP_SOUND_L_SFT 0 --// unshifted values for both L and R: --#define RK3308_DAC_HPOUT_POP_SOUND_x_MSK 0x3 --#define RK3308_DAC_HPOUT_POP_SOUND_x_WORK 0x2 --#define RK3308_DAC_HPOUT_POP_SOUND_x_INIT 0x1 -+#define RK3308_DAC_HPOUT_POP_SOUND_L_MSK (0x3 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT) -+#define RK3308_DAC_HPOUT_POP_SOUND_L_WORK (0x2 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT) -+#define RK3308_DAC_HPOUT_POP_SOUND_L_INIT (0x1 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT) - - /* RK3308_DAC_ANA_CON02 - REG: 0x0448 */ --#define RK3308_DAC_R_DAC_WORK BIT(7) --#define RK3308_DAC_R_DAC_EN BIT(6) --#define RK3308_DAC_R_CLK_EN BIT(5) --#define RK3308_DAC_R_REF_EN BIT(4) --#define RK3308_DAC_L_DAC_WORK BIT(3) --#define RK3308_DAC_L_DAC_EN BIT(2) --#define RK3308_DAC_L_CLK_EN BIT(1) --#define RK3308_DAC_L_REF_EN BIT(0) -+#define RK3308_DAC_R_DAC_WORK (0x1 << 7) -+#define RK3308_DAC_R_DAC_INIT (0x0 << 7) -+#define RK3308_DAC_R_DAC_EN (0x1 << 6) -+#define RK3308_DAC_R_DAC_DIS (0x0 << 6) -+#define RK3308_DAC_R_CLK_EN (0x1 << 5) -+#define RK3308_DAC_R_CLK_DIS (0x0 << 5) -+#define RK3308_DAC_R_REF_EN (0x1 << 4) -+#define RK3308_DAC_R_REF_DIS (0x0 << 4) -+#define RK3308_DAC_L_DAC_WORK (0x1 << 3) -+#define RK3308_DAC_L_DAC_INIT (0x0 << 3) -+#define RK3308_DAC_L_DAC_EN (0x1 << 2) -+#define RK3308_DAC_L_DAC_DIS (0x0 << 2) -+#define RK3308_DAC_L_CLK_EN (0x1 << 1) -+#define RK3308_DAC_L_CLK_DIS (0x0 << 1) -+#define RK3308_DAC_L_REF_EN (0x1 << 0) -+#define RK3308_DAC_L_REF_DIS (0x0 << 0) - - /* RK3308_DAC_ANA_CON03 - REG: 0x044c */ --#define RK3308_DAC_R_HPOUT_WORK BIT(6) --#define RK3308_DAC_R_HPOUT_EN BIT(5) --#define RK3308_DAC_R_HPOUT_MUTE_SFT 4 --#define RK3308_DAC_L_HPOUT_WORK BIT(2) --#define RK3308_DAC_L_HPOUT_EN BIT(1) --#define RK3308_DAC_L_HPOUT_MUTE_SFT 0 -+#define RK3308_DAC_R_HPOUT_WORK (0x1 << 6) -+#define RK3308_DAC_R_HPOUT_INIT (0x0 << 6) -+#define RK3308_DAC_R_HPOUT_EN (0x1 << 5) -+#define RK3308_DAC_R_HPOUT_DIS (0x0 << 5) -+#define RK3308_DAC_R_HPOUT_UNMUTE (0x1 << 4) -+#define RK3308_DAC_R_HPOUT_MUTE (0x0 << 4) -+#define RK3308_DAC_L_HPOUT_WORK (0x1 << 2) -+#define RK3308_DAC_L_HPOUT_INIT (0x0 << 2) -+#define RK3308_DAC_L_HPOUT_EN (0x1 << 1) -+#define RK3308_DAC_L_HPOUT_DIS (0x0 << 1) -+#define RK3308_DAC_L_HPOUT_UNMUTE (0x1 << 0) -+#define RK3308_DAC_L_HPOUT_MUTE (0x0 << 0) - - /* RK3308_DAC_ANA_CON04 - REG: 0x0450 */ --#define RK3308_DAC_x_LINEOUT_GAIN_MAX 0x3 -+#define RK3308_DAC_R_LINEOUT_GAIN_MAX 0x3 - #define RK3308_DAC_R_LINEOUT_GAIN_SFT 6 - #define RK3308_DAC_R_LINEOUT_GAIN_MSK (0x3 << RK3308_DAC_R_LINEOUT_GAIN_SFT) - #define RK3308_DAC_R_LINEOUT_GAIN_0DB (0x3 << RK3308_DAC_R_LINEOUT_GAIN_SFT) - #define RK3308_DAC_R_LINEOUT_GAIN_NDB_1_5 (0x2 << RK3308_DAC_R_LINEOUT_GAIN_SFT) - #define RK3308_DAC_R_LINEOUT_GAIN_NDB_3 (0x1 << RK3308_DAC_R_LINEOUT_GAIN_SFT) - #define RK3308_DAC_R_LINEOUT_GAIN_NDB_6 (0x0 << RK3308_DAC_R_LINEOUT_GAIN_SFT) --#define RK3308_DAC_R_LINEOUT_MUTE_SFT 5 --#define RK3308_DAC_R_LINEOUT_EN BIT(4) -+#define RK3308_DAC_R_LINEOUT_UNMUTE (0x1 << 5) -+#define RK3308_DAC_R_LINEOUT_MUTE (0x0 << 5) -+#define RK3308_DAC_R_LINEOUT_EN (0x1 << 4) -+#define RK3308_DAC_R_LINEOUT_DIS (0x0 << 4) -+#define RK3308_DAC_L_LINEOUT_GAIN_MAX 0x3 - #define RK3308_DAC_L_LINEOUT_GAIN_SFT 2 - #define RK3308_DAC_L_LINEOUT_GAIN_MSK (0x3 << RK3308_DAC_L_LINEOUT_GAIN_SFT) - #define RK3308_DAC_L_LINEOUT_GAIN_0DB (0x3 << RK3308_DAC_L_LINEOUT_GAIN_SFT) - #define RK3308_DAC_L_LINEOUT_GAIN_NDB_1_5 (0x2 << RK3308_DAC_L_LINEOUT_GAIN_SFT) - #define RK3308_DAC_L_LINEOUT_GAIN_NDB_3 (0x1 << RK3308_DAC_L_LINEOUT_GAIN_SFT) - #define RK3308_DAC_L_LINEOUT_GAIN_NDB_6 (0x0 << RK3308_DAC_L_LINEOUT_GAIN_SFT) --#define RK3308_DAC_L_LINEOUT_MUTE_SFT 1 --#define RK3308_DAC_L_LINEOUT_EN BIT(0) -+#define RK3308_DAC_L_LINEOUT_UNMUTE (0x1 << 1) -+#define RK3308_DAC_L_LINEOUT_MUTE (0x0 << 1) -+#define RK3308_DAC_L_LINEOUT_EN (0x1 << 0) -+#define RK3308_DAC_L_LINEOUT_DIS (0x0 << 0) - - /* RK3308_DAC_ANA_CON05 - REG: 0x0454, step is 1.5db */ -+#define RK3308_DAC_L_HPOUT_GAIN_MAX 0x1e -+#define RK3308_DAC_L_HPOUT_GAIN_SFT 0 -+#define RK3308_DAC_L_HPOUT_GAIN_MSK (0x1f << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_PDB_6 (0x1e << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_PDB_4_5 (0x1d << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_PDB_3 (0x1c << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_PDB_1_5 (0x1b << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_0DB (0x1a << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_1_5 (0x19 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_3 (0x18 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_4_5 (0x17 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_6 (0x16 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_7_5 (0x15 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_9 (0x14 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_10_5 (0x13 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_12 (0x12 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_13_5 (0x11 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_15 (0x10 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_16_5 (0x0f << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_18 (0x0e << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_19_5 (0x0d << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_21 (0x0c << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_22_5 (0x0b << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_24 (0x0a << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_25_5 (0x09 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_27 (0x08 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_28_5 (0x07 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_30 (0x06 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_31_5 (0x05 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_33 (0x04 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_34_5 (0x03 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_36 (0x02 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_37_5 (0x01 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+#define RK3308_DAC_L_HPOUT_GAIN_NDB_39 (0x00 << RK3308_DAC_L_HPOUT_GAIN_SFT) -+ - /* RK3308_DAC_ANA_CON06 - REG: 0x0458, step is 1.5db */ --#define RK3308_DAC_x_HPOUT_GAIN_MAX 0x1e --#define RK3308_DAC_x_HPOUT_GAIN_SFT 0 --#define RK3308_DAC_x_HPOUT_GAIN_MSK (0x1f << RK3308_DAC_x_HPOUT_GAIN_SFT) --#define RK3308_DAC_x_HPOUT_GAIN_MIN (0x00 << RK3308_DAC_x_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_MAX 0x1e -+#define RK3308_DAC_R_HPOUT_GAIN_SFT 0 -+#define RK3308_DAC_R_HPOUT_GAIN_MSK (0x1f << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_PDB_6 (0x1e << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_PDB_4_5 (0x1d << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_PDB_3 (0x1c << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_PDB_1_5 (0x1b << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_0DB (0x1a << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_1_5 (0x19 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_3 (0x18 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_4_5 (0x17 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_6 (0x16 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_7_5 (0x15 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_9 (0x14 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_10_5 (0x13 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_12 (0x12 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_13_5 (0x11 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_15 (0x10 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_16_5 (0x0f << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_18 (0x0e << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_19_5 (0x0d << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_21 (0x0c << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_22_5 (0x0b << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_24 (0x0a << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_25_5 (0x09 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_27 (0x08 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_28_5 (0x07 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_30 (0x06 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_31_5 (0x05 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_33 (0x04 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_34_5 (0x03 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_36 (0x02 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_37_5 (0x01 << RK3308_DAC_R_HPOUT_GAIN_SFT) -+#define RK3308_DAC_R_HPOUT_GAIN_NDB_39 (0x00 << RK3308_DAC_R_HPOUT_GAIN_SFT) - - /* RK3308_DAC_ANA_CON07 - REG: 0x045c */ - #define RK3308_DAC_R_HPOUT_DRV_SFT 4 -@@ -534,36 +1007,51 @@ - #define RK3308_DAC_R_HPMIX_LINEIN (0x2 << RK3308_DAC_R_HPMIX_SEL_SFT) - #define RK3308_DAC_R_HPMIX_I2S (0x1 << RK3308_DAC_R_HPMIX_SEL_SFT) - #define RK3308_DAC_R_HPMIX_NONE (0x0 << RK3308_DAC_R_HPMIX_SEL_SFT) -+#define RK3308_DAC_R_HPMIX_GAIN_MIN 0x1 -+#define RK3308_DAC_R_HPMIX_GAIN_MAX 0x2 -+#define RK3308_DAC_R_HPMIX_GAIN_SFT 4 -+#define RK3308_DAC_R_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_R_HPMIX_GAIN_SFT) -+#define RK3308_DAC_R_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_R_HPMIX_GAIN_SFT) -+#define RK3308_DAC_R_HPMIX_GAIN_NDB_6 (0x1 << RK3308_DAC_R_HPMIX_GAIN_SFT) - #define RK3308_DAC_L_HPMIX_SEL_SFT 2 - #define RK3308_DAC_L_HPMIX_SEL_MSK (0x3 << RK3308_DAC_L_HPMIX_SEL_SFT) - #define RK3308_DAC_L_HPMIX_LINEIN_I2S (0x3 << RK3308_DAC_L_HPMIX_SEL_SFT) - #define RK3308_DAC_L_HPMIX_LINEIN (0x2 << RK3308_DAC_L_HPMIX_SEL_SFT) - #define RK3308_DAC_L_HPMIX_I2S (0x1 << RK3308_DAC_L_HPMIX_SEL_SFT) - #define RK3308_DAC_L_HPMIX_NONE (0x0 << RK3308_DAC_L_HPMIX_SEL_SFT) --#define RK3308_DAC_x_HPMIX_GAIN_MIN 0x1 /* 0x0 and 0x3 are reserved */ --#define RK3308_DAC_x_HPMIX_GAIN_MAX 0x2 --#define RK3308_DAC_R_HPMIX_GAIN_SFT 4 --#define RK3308_DAC_R_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_R_HPMIX_GAIN_SFT) --#define RK3308_DAC_R_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_R_HPMIX_GAIN_SFT) --#define RK3308_DAC_R_HPMIX_GAIN_NDB_6 (0x1 << RK3308_DAC_R_HPMIX_GAIN_SFT) -+#define RK3308_DAC_L_HPMIX_GAIN_MIN 0x1 -+#define RK3308_DAC_L_HPMIX_GAIN_MAX 0x2 - #define RK3308_DAC_L_HPMIX_GAIN_SFT 0 - #define RK3308_DAC_L_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_L_HPMIX_GAIN_SFT) - #define RK3308_DAC_L_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_L_HPMIX_GAIN_SFT) - #define RK3308_DAC_L_HPMIX_GAIN_NDB_6 (0x1 << RK3308_DAC_L_HPMIX_GAIN_SFT) - - /* RK3308_DAC_ANA_CON13 - REG: 0x0474 */ --#define RK3308_DAC_R_HPMIX_UNMUTE BIT(6) --#define RK3308_DAC_R_HPMIX_WORK BIT(5) --#define RK3308_DAC_R_HPMIX_EN BIT(4) --#define RK3308_DAC_L_HPMIX_UNMUTE BIT(2) --#define RK3308_DAC_L_HPMIX_WORK BIT(1) --#define RK3308_DAC_L_HPMIX_EN BIT(0) -+#define RK3308_DAC_R_HPMIX_UNMUTE (0x1 << 6) -+#define RK3308_DAC_R_HPMIX_MUTE (0x0 << 6) -+#define RK3308_DAC_R_HPMIX_WORK (0x1 << 5) -+#define RK3308_DAC_R_HPMIX_INIT (0x0 << 5) -+#define RK3308_DAC_R_HPMIX_EN (0x1 << 4) -+#define RK3308_DAC_R_HPMIX_DIS (0x0 << 4) -+#define RK3308_DAC_L_HPMIX_UNMUTE (0x1 << 2) -+#define RK3308_DAC_L_HPMIX_MUTE (0x0 << 2) -+#define RK3308_DAC_L_HPMIX_WORK (0x1 << 1) -+#define RK3308_DAC_L_HPMIX_INIT (0x0 << 1) -+#define RK3308_DAC_L_HPMIX_EN (0x1 << 0) -+#define RK3308_DAC_L_HPMIX_DIS (0x0 << 0) - - /* RK3308_DAC_ANA_CON14 - REG: 0x0478 */ - #define RK3308_DAC_VCM_LINEOUT_EN (0x1 << 4) -+#define RK3308_DAC_VCM_LINEOUT_DIS (0x0 << 4) - #define RK3308_DAC_CURRENT_CHARGE_SFT 0 - #define RK3308_DAC_CURRENT_CHARGE_MSK (0xf << RK3308_DAC_CURRENT_CHARGE_SFT) - -+/* -+ * 1: Choose the current I -+ * 0: Don't choose the current I -+ */ -+#define RK3308_DAC_SEL_I(x) (x & 0xf) -+ - /* RK3308_DAC_ANA_CON15 - REG: 0x047C */ - #define RK3308_DAC_LINEOUT_POP_SOUND_R_SFT 4 - #define RK3308_DAC_LINEOUT_POP_SOUND_R_MSK (0x3 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT) -@@ -576,4 +1064,6 @@ - #define RK3308_DAC_L_SEL_DC_FROM_VCM (0x1 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT) - #define RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL (0x0 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT) - -+#define RK3308_HIFI 0x0 -+ - #endif /* __RK3308_CODEC_H__ */ -diff --git a/sound/soc/codecs/rk3308_codec_provider.h b/sound/soc/codecs/rk3308_codec_provider.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/sound/soc/codecs/rk3308_codec_provider.h -@@ -0,0 +1,28 @@ -+/* -+ * rk3308_codec_provider.h -- RK3308 ALSA Soc Audio Driver -+ * -+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ * -+ */ -+ -+#ifndef __RK3308_CODEC_PROVIDER_H__ -+#define __RK3308_CODEC_PROVIDER_H__ -+ -+#ifdef CONFIG_SND_SOC_RK3308 -+extern void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_component *component, -+ struct snd_soc_jack *hpdet_jack); -+#endif -+ -+#endif /* __RK3308_CODEC_PROVIDER_H__ */ --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3308-add-gmac-alias.patch b/patch/kernel/rockchip64-6.14/rk3308-add-gmac-alias.patch deleted file mode 100644 index 0933f42..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-add-gmac-alias.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: ashthespy -Date: Thu, 16 Jan 2020 21:13:09 +0100 -Subject: arm64: dts: rk3308: Add mac node at dtsi level - ---- - arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -@@ -29,6 +29,7 @@ aliases { - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; -+ ethernet0 = &gmac; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3308-add-missing-i2s-controllers.patch b/patch/kernel/rockchip64-6.14/rk3308-add-missing-i2s-controllers.patch deleted file mode 100644 index f36b675..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-add-missing-i2s-controllers.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Sun, 21 Jul 2024 14:18:30 +0200 -Subject: add missing i2s controllers - ---- - arch/arm64/boot/dts/rockchip/rk3308.dtsi | 59 ++++++++++ - 1 file changed, 59 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -@@ -608,6 +608,65 @@ dmac1: dma-controller@ff2d0000 { - #dma-cells = <1>; - }; - -+ i2s_8ch_0: i2s@ff300000 { -+ compatible = "rockchip,rk3308-i2s-tdm"; -+ reg = <0x0 0xff300000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>, -+ <&cru SCLK_I2S0_8CH_TX_SRC>, -+ <&cru SCLK_I2S0_8CH_RX_SRC>, -+ <&cru PLL_VPLL0>, -+ <&cru PLL_VPLL1>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk", -+ "mclk_tx_src", "mclk_rx_src", -+ "mclk_root0", "mclk_root1"; -+ dmas = <&dmac1 0>, <&dmac1 1>; -+ dma-names = "tx", "rx"; -+ resets = <&cru SRST_I2S0_8CH_TX_M>, <&cru SRST_I2S0_8CH_RX_M>; -+ reset-names = "tx-m", "rx-m"; -+ rockchip,cru = <&cru>; -+ rockchip,grf = <&grf>; -+ rockchip,mclk-calibrate; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s_8ch_0_sclktx -+ &i2s_8ch_0_sclkrx -+ &i2s_8ch_0_lrcktx -+ &i2s_8ch_0_lrckrx -+ &i2s_8ch_0_sdi0 -+ &i2s_8ch_0_sdi1 -+ &i2s_8ch_0_sdi2 -+ &i2s_8ch_0_sdi3 -+ &i2s_8ch_0_sdo0 -+ &i2s_8ch_0_sdo1 -+ &i2s_8ch_0_sdo2 -+ &i2s_8ch_0_sdo3 -+ &i2s_8ch_0_mclk>; -+ status = "disabled"; -+ }; -+ -+ i2s_8ch_1: i2s@ff310000 { -+ compatible = "rockchip,rk3308-i2s-tdm"; -+ reg = <0x0 0xff310000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru SCLK_I2S1_8CH_TX>, <&cru SCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>, -+ <&cru SCLK_I2S1_8CH_TX_SRC>, -+ <&cru SCLK_I2S1_8CH_RX_SRC>, -+ <&cru PLL_VPLL0>, -+ <&cru PLL_VPLL1>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk", -+ "mclk_tx_src", "mclk_rx_src", -+ "mclk_root0", "mclk_root1"; -+ dmas = <&dmac1 2>, <&dmac1 3>; -+ dma-names = "tx", "rx"; -+ resets = <&cru SRST_I2S1_8CH_TX_M>, <&cru SRST_I2S1_8CH_RX_M>; -+ reset-names = "tx-m", "rx-m"; -+ rockchip,cru = <&cru>; -+ rockchip,grf = <&grf>; -+ rockchip,mclk-calibrate; -+ rockchip,io-multiplex; -+ status = "disabled"; -+ }; -+ - /* - * - can be clock producer or consumer - * - up to 8 capture channels and 2 playback channels --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3308-add-tsadc-driver.patch b/patch/kernel/rockchip64-6.14/rk3308-add-tsadc-driver.patch deleted file mode 100644 index 7ad4c27..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-add-tsadc-driver.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Rocky Hao -Date: Fri, 9 Mar 2018 17:36:39 +0800 -Subject: thermal: rockchip: add tsadc support for rk3308 - -Change-Id: Ibf1782ca471c8ad4b14d6fd64eeb123181903adc -Signed-off-by: Rocky Hao ---- - Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 1 + - drivers/thermal/rockchip_thermal.c | 26 ++++++++++ - 2 files changed, 27 insertions(+) - -diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml -+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml -@@ -17,6 +17,7 @@ properties: - - rockchip,px30-tsadc - - rockchip,rk3228-tsadc - - rockchip,rk3288-tsadc -+ - rockchip,rk3308-tsadc - - rockchip,rk3328-tsadc - - rockchip,rk3368-tsadc - - rockchip,rk3399-tsadc -diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c -index 111111111111..222222222222 100644 ---- a/drivers/thermal/rockchip_thermal.c -+++ b/drivers/thermal/rockchip_thermal.c -@@ -1060,6 +1060,28 @@ static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, - writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); - } - -+static const struct rockchip_tsadc_chip rk3308_tsadc_data = { -+ .chn_num = 2, /* 2 channels for tsadc */ -+ -+ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ -+ .tshut_temp = 95000, -+ -+ .initialize = rk_tsadcv4_initialize, -+ .irq_ack = rk_tsadcv3_irq_ack, -+ .control = rk_tsadcv3_control, -+ .get_temp = rk_tsadcv2_get_temp, -+ .set_alarm_temp = rk_tsadcv2_alarm_temp, -+ .set_tshut_temp = rk_tsadcv2_tshut_temp, -+ .set_tshut_mode = rk_tsadcv2_tshut_mode, -+ -+ .table = { -+ .id = rk3328_code_table, -+ .length = ARRAY_SIZE(rk3328_code_table), -+ .data_mask = TSADCV2_DATA_MASK, -+ .mode = ADC_INCREMENT, -+ }, -+}; -+ - static const struct rockchip_tsadc_chip px30_tsadc_data = { - /* cpu, gpu */ - .chn_offset = 0, -@@ -1321,6 +1343,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { - .compatible = "rockchip,rk3288-tsadc", - .data = (void *)&rk3288_tsadc_data, - }, -+ { -+ .compatible = "rockchip,rk3308-tsadc", -+ .data = (void *)&rk3308_tsadc_data, -+ }, - { - .compatible = "rockchip,rk3328-tsadc", - .data = (void *)&rk3328_tsadc_data, --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3308-dts-legacy-cryptov2.patch b/patch/kernel/rockchip64-6.14/rk3308-dts-legacy-cryptov2.patch deleted file mode 100644 index 6472841..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-dts-legacy-cryptov2.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Mon, 25 Nov 2024 17:23:22 +0100 -Subject: rk3308: add cryptov2 dts node - ---- - arch/arm64/boot/dts/rockchip/rk3308.dtsi | 15 ++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -@@ -170,6 +170,21 @@ xin24m: xin24m { - clock-output-names = "xin24m"; - }; - -+ rng: rng@ff2f0000 { -+ compatible = "rockchip,cryptov2-rng"; -+ reg = <0x0 0xff2f0000 0x0 0x4000>; -+ clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, -+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; -+ clock-names = "clk_crypto", "clk_crypto_apk", -+ "aclk_crypto", "hclk_crypto"; -+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, -+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; -+ assigned-clock-rates = <150000000>, <150000000>, -+ <200000000>, <100000000>; -+ resets = <&cru SRST_CRYPTO>; -+ reset-names = "reset"; -+ }; -+ - grf: grf@ff000000 { - compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x08000>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3308-dts-thermal-zones.patch b/patch/kernel/rockchip64-6.14/rk3308-dts-thermal-zones.patch deleted file mode 100644 index eae466f..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-dts-thermal-zones.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: ashthespy -Date: Fri, 17 Jan 2020 15:57:53 +0100 -Subject: arm64: dts: rockchip: add cpu's thermal config for rk3308 - ---- - arch/arm64/boot/dts/rockchip/rk3308.dtsi | 64 ++++++++++ - 1 file changed, 64 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -@@ -601,6 +601,70 @@ logic_leakage: logic-leakage@18 { - }; - }; - -+ thermal_zones: thermal-zones { -+ -+ soc_thermal: soc-thermal { -+ polling-delay-passive = <20>; -+ polling-delay = <1000>; -+ sustainable-power = <300>; -+ -+ thermal-sensors = <&tsadc 1>; -+ -+ trips { -+ threshold: trip-point-0 { -+ temperature = <70000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ target: trip-point-1 { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ soc_crit: soc-crit { -+ temperature = <115000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&target>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ contribution = <4096>; -+ }; -+ }; -+ -+ }; -+ -+ logic_thermal: logic-thermal { -+ polling-delay-passive = <100>; /* milliseconds */ -+ polling-delay = <1000>; /* milliseconds */ -+ -+ thermal-sensors = <&tsadc 0>; -+ }; -+ }; -+ -+ tsadc: tsadc@ff1f0000 { -+ compatible = "rockchip,rk3308-tsadc"; -+ reg = <0x0 0xff1f0000 0x0 0x100>; -+ interrupts = ; -+ rockchip,grf = <&grf>; -+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; -+ clock-names = "tsadc", "apb_pclk"; -+ assigned-clocks = <&cru SCLK_TSADC>; -+ assigned-clock-rates = <50000>; -+ resets = <&cru SRST_TSADC>; -+ reset-names = "tsadc-apb"; -+ pinctrl-names = "gpio", "otpout"; -+ pinctrl-0 = <&tsadc_otp_pin>; -+ pinctrl-1 = <&tsadc_otp_out>; -+ #thermal-sensor-cells = <1>; -+ rockchip,hw-tshut-temp = <120000>; -+ status = "disabled"; -+ }; -+ - dmac0: dma-controller@ff2c0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2c0000 0x0 0x4000>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3308-fix-uart-dma.patch b/patch/kernel/rockchip64-6.14/rk3308-fix-uart-dma.patch deleted file mode 100644 index 0185dc0..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-fix-uart-dma.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: ssp97 -Date: Fri, 11 Apr 2025 23:35:49 +0800 -Subject: rk3308: fix uart dma. - -Signed-off-by: ssp97 ---- - arch/arm64/boot/dts/rockchip/rk3308.dtsi | 10 ++++++++++ - drivers/soc/rockchip/grf.c | 14 ++++++++++ - 2 file changed, 24 insertions(+) - -diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c -index 5fd62046b..78138cee6 100644 ---- a/drivers/soc/rockchip/grf.c -+++ b/drivers/soc/rockchip/grf.c -@@ -84,10 +84,21 @@ static const struct rockchip_grf_value rk3328_defaults[] __initconst = { - static const struct rockchip_grf_info rk3328_grf __initconst = { - .values = rk3328_defaults, - .num_values = ARRAY_SIZE(rk3328_defaults), - }; - -+#define RK3308_GRF_SOC_CON3 0x30c -+ -+static const struct rockchip_grf_value rk3308_defaults[] __initconst = { -+ { "uart dma mask", RK3308_GRF_SOC_CON3, HIWORD_UPDATE(0, 0x1f, 10) }, -+}; -+ -+static const struct rockchip_grf_info rk3308_grf __initconst = { -+ .values = rk3308_defaults, -+ .num_values = ARRAY_SIZE(rk3308_defaults), -+}; -+ - #define RK3368_GRF_SOC_CON15 0x43c - - static const struct rockchip_grf_value rk3368_defaults[] __initconst = { - { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) }, - }; -@@ -147,10 +158,13 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = { - .compatible = "rockchip,rk3288-grf", - .data = (void *)&rk3288_grf, - }, { - .compatible = "rockchip,rk3328-grf", - .data = (void *)&rk3328_grf, -+ }, { -+ .compatible = "rockchip,rk3308-grf", -+ .data = (void *)&rk3308_grf, - }, { - .compatible = "rockchip,rk3368-grf", - .data = (void *)&rk3368_grf, - }, { - .compatible = "rockchip,rk3399-grf", -diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -index 7d1571e4f..a6b8dc8df 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -@@ -351,10 +351,12 @@ uart0: serial@ff0a0000 { - interrupts = ; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; -+ dmas = <&dmac0 4>, <&dmac0 5>; -+ dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - -@@ -364,10 +366,12 @@ uart1: serial@ff0b0000 { - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; -+ dmas = <&dmac0 6>, <&dmac0 7>; -+ dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; - status = "disabled"; - }; - -@@ -377,10 +381,12 @@ uart2: serial@ff0c0000 { - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; -+ dmas = <&dmac0 8>, <&dmac0 9>; -+ dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - -@@ -390,10 +396,12 @@ uart3: serial@ff0d0000 { - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; -+ dmas = <&dmac0 10>, <&dmac0 11>; -+ dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - -@@ -403,10 +411,12 @@ uart4: serial@ff0e0000 { - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; -+ dmas = <&dmac1 18>, <&dmac1 19>; -+ dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; - status = "disabled"; - }; - --- -Created with Armbian build tools https://github.com/armbian/build - diff --git a/patch/kernel/rockchip64-6.14/rk3308-internal-rgb-lcdc.patch b/patch/kernel/rockchip64-6.14/rk3308-internal-rgb-lcdc.patch deleted file mode 100755 index 4136459..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-internal-rgb-lcdc.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com> -Date: Sat, 22 Feb 2025 01:09:54 +0000 -Subject: rk3308: set pinmux for internal RGB output - -Signed-off-by: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com> ---- - drivers/gpu/drm/rockchip/rockchip_rgb.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_rgb.c -+++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -168,6 +169,8 @@ struct rockchip_rgb *rockchip_rgb_init(struct device *dev, - goto err_free_connector; - } - -+ pinctrl_pm_select_default_state(dev); -+ - return rgb; - - err_free_connector: --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3308-vop-output.patch b/patch/kernel/rockchip64-6.14/rk3308-vop-output.patch deleted file mode 100755 index ba95ba3..0000000 --- a/patch/kernel/rockchip64-6.14/rk3308-vop-output.patch +++ /dev/null @@ -1,338 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com> -Date: Sat, 22 Feb 2025 09:22:52 +0000 -Subject: rk3308: rk3308 vop output - -Signed-off-by: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com> ---- - arch/arm64/boot/dts/rockchip/rk3308.dtsi | 110 ++++++++++ - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 102 +++++++++ - drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 60 +++++ - 3 files changed, 272 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -@@ -143,6 +143,12 @@ arm-pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - -+ display_subsystem: display-subsystem { -+ compatible = "rockchip,display-subsystem"; -+ ports = <&vop_out>; -+ status = "disabled"; -+ }; -+ - mac_clkin: external-mac-clock { - compatible = "fixed-clock"; - clock-frequency = <50000000>; -@@ -687,6 +693,26 @@ dmac1: dma-controller@ff2d0000 { - #dma-cells = <1>; - }; - -+ vop: vop@ff2e0000 { -+ compatible = "rockchip,rk3308-vop"; -+ reg = <0x0 0xff2e0000 0x0 0x1fc>; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; -+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; -+ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; -+ reset-names = "axi", "ahb", "dclk"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lcdc_ctl>; -+ -+ status = "disabled"; -+ -+ vop_out: port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ - i2s_8ch_0: i2s@ff300000 { - compatible = "rockchip,rk3308-i2s-tdm"; - reg = <0x0 0xff300000 0x0 0x1000>; -@@ -2111,5 +2137,89 @@ uart4_rts_pin: uart4-rts-pin { - <4 RK_PA7 0 &pcfg_pull_none>; - }; - }; -+ -+ lcdc { -+ lcdc_ctl: lcdc-ctl { -+ rockchip,pins = -+ /* dclk */ -+ <1 RK_PA0 1 &pcfg_pull_none_12ma>, -+ /* hsync */ -+ <1 RK_PA1 1 &pcfg_pull_none>, -+ /* vsync */ -+ <1 RK_PA2 1 &pcfg_pull_none>, -+ /* den */ -+ <1 RK_PA3 1 &pcfg_pull_none>, -+ /* d0 */ -+ <1 RK_PA4 1 &pcfg_pull_none>, -+ /* d1 */ -+ <1 RK_PA5 1 &pcfg_pull_none>, -+ /* d2 */ -+ <1 RK_PA6 1 &pcfg_pull_none>, -+ /* d3 */ -+ <1 RK_PA7 1 &pcfg_pull_none>, -+ /* d4 */ -+ <1 RK_PB0 1 &pcfg_pull_none>, -+ /* d5 */ -+ <1 RK_PB1 1 &pcfg_pull_none>, -+ /* d6 */ -+ <1 RK_PB2 1 &pcfg_pull_none>, -+ /* d7 */ -+ <1 RK_PB3 1 &pcfg_pull_none>, -+ /* d8 */ -+ <1 RK_PB4 1 &pcfg_pull_none>, -+ /* d9 */ -+ <1 RK_PB5 1 &pcfg_pull_none>, -+ /* d10 */ -+ <1 RK_PB6 1 &pcfg_pull_none>, -+ /* d11 */ -+ <1 RK_PB7 1 &pcfg_pull_none>, -+ /* d12 */ -+ <1 RK_PC0 1 &pcfg_pull_none>, -+ /* d13 */ -+ <1 RK_PC1 1 &pcfg_pull_none>, -+ /* d14 */ -+ <1 RK_PC2 1 &pcfg_pull_none>, -+ /* d15 */ -+ <1 RK_PC3 1 &pcfg_pull_none>, -+ /* d16 */ -+ <1 RK_PC4 1 &pcfg_pull_none>, -+ /* d17 */ -+ <1 RK_PC5 1 &pcfg_pull_none>; -+ }; -+ -+ lcdc_rgb888_m0: lcdc-rgb888-m0 { -+ rockchip,pins = -+ /* d18 */ -+ <1 RK_PC6 6 &pcfg_pull_none>, -+ /* d19 */ -+ <1 RK_PC7 6 &pcfg_pull_none>, -+ /* d20 */ -+ <2 RK_PB1 3 &pcfg_pull_none>, -+ /* d21 */ -+ <2 RK_PB2 3 &pcfg_pull_none>, -+ /* d22 */ -+ <2 RK_PB7 3 &pcfg_pull_none>, -+ /* d23 */ -+ <2 RK_PC0 3 &pcfg_pull_none>; -+ }; -+ -+ lcdc_rgb888_m1: lcdc-rgb888-m1 { -+ rockchip,pins = -+ /* d18 */ -+ <3 RK_PA6 3 &pcfg_pull_none>, -+ /* d19 */ -+ <3 RK_PA7 3 &pcfg_pull_none>, -+ /* d20 */ -+ <3 RK_PB0 3 &pcfg_pull_none>, -+ /* d21 */ -+ <3 RK_PB1 3 &pcfg_pull_none>, -+ /* d22 */ -+ <3 RK_PB2 4 &pcfg_pull_none>, -+ /* d23 */ -+ <3 RK_PB3 4 &pcfg_pull_none>; -+ }; -+ }; -+ -+ - }; - }; -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -1186,6 +1186,106 @@ static const struct vop_data rk3328_vop = { - .max_output = { 4096, 2160 }, - }; - -+static const struct vop_intr rk3308_lit_intr = { -+ .intrs = rk3368_vop_intrs, -+ .nintrs = ARRAY_SIZE(rk3368_vop_intrs), -+ .line_flag_num[0] = VOP_REG(RK3308_LIT_LINE_FLAG, 0xfff, 0), -+ .line_flag_num[1] = VOP_REG(RK3308_LIT_LINE_FLAG, 0xfff, 16), -+ .status = VOP_REG_MASK_SYNC(RK3308_LIT_INTR_STATUS, 0xffff, 0), -+ .enable = VOP_REG_MASK_SYNC(RK3308_LIT_INTR_EN, 0xffff, 0), -+ .clear = VOP_REG_MASK_SYNC(RK3308_LIT_INTR_CLEAR, 0xffff, 0), -+}; -+ -+static const struct vop_output rk3308_ctrl_data = { -+ .rgb_en = VOP_REG(RK3308_LIT_DSP_CTRL0, 0x1, 0), -+ .rgb_pin_pol = VOP_REG(RK3308_LIT_DSP_CTRL0, 0x7, 2), -+ .rgb_dclk_pol = VOP_REG(RK3308_LIT_DSP_CTRL0, 0x1, 1), -+}; -+ -+static const struct vop_common rk3308_common = { -+ .standby = VOP_REG(RK3308_LIT_SYS_CTRL2, 0x1, 1), -+ .cfg_done = VOP_REG(RK3308_LIT_REG_CFG_DONE, 0x1, 0), -+ .dsp_blank = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 14), -+ .dither_down_en = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 8), -+ .dither_down_sel = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 7), -+ .dither_down_mode = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 6), -+ .dither_up = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 2), -+ .dsp_lut_en = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 5), -+ .gate_en = VOP_REG(RK3308_LIT_SYS_CTRL2, 0x1, 0), -+ .out_mode = VOP_REG(RK3308_LIT_DSP_CTRL2, 0xf, 16), -+}; -+ -+static const struct vop_scl_regs rk3308_lit_win_scl = { -+ .scale_yrgb_x = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), -+ .scale_yrgb_y = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), -+ .scale_cbcr_x = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), -+ .scale_cbcr_y = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16), -+}; -+ -+static const struct vop_win_phy rk3308_lit_win0_data = { -+ .scl = &rk3308_lit_win_scl, -+ .data_formats = formats_win_full, -+ .nformats = ARRAY_SIZE(formats_win_full), -+ -+ .enable = VOP_REG(RK3308_LIT_WIN0_CTRL0, 0x1, 0), -+ .format = VOP_REG(RK3308_LIT_WIN0_CTRL0, 0x7, 1), -+ .rb_swap = VOP_REG(RK3308_LIT_WIN0_CTRL0, 0x1, 12), -+ .act_info = VOP_REG(RK3308_LIT_WIN0_ACT_INFO, 0xffffffff, 0), -+ .dsp_info = VOP_REG(RK3308_LIT_WIN0_DSP_INFO, 0xffffffff, 0), -+ .dsp_st = VOP_REG(RK3308_LIT_WIN0_DSP_ST, 0xffffffff, 0), -+ .yrgb_mst = VOP_REG(RK3308_LIT_WIN0_YRGB_MST0, 0xffffffff, 0), -+ .uv_mst = VOP_REG(RK3308_LIT_WIN0_CBR_MST0, 0xffffffff, 0), -+ .yrgb_vir = VOP_REG(RK3308_LIT_WIN0_VIR, 0x1fff, 0), -+ .uv_vir = VOP_REG(RK3308_LIT_WIN0_VIR, 0x1fff, 16), -+ -+ .alpha_pre_mul = VOP_REG(RK3308_LIT_WIN0_ALPHA_CTRL, 0x1, 2), -+ .alpha_mode = VOP_REG(RK3308_LIT_WIN0_ALPHA_CTRL, 0x1, 1), -+ .alpha_en = VOP_REG(RK3308_LIT_WIN0_ALPHA_CTRL, 0x1, 0), -+}; -+ -+static const struct vop_win_phy rk3308_lit_win1_data = { -+ .data_formats = formats_win_lite, -+ .nformats = ARRAY_SIZE(formats_win_lite), -+ -+ .enable = VOP_REG(RK3308_LIT_WIN1_CTRL0, 0x1, 0), -+ .format = VOP_REG(RK3308_LIT_WIN1_CTRL0, 0x7, 4), -+ .rb_swap = VOP_REG(RK3308_LIT_WIN1_CTRL0, 0x1, 12), -+ .dsp_info = VOP_REG(RK3308_LIT_WIN1_DSP_INFO, 0xffffffff, 0), -+ .dsp_st = VOP_REG(RK3308_LIT_WIN1_DSP_ST, 0xffffffff, 0), -+ .yrgb_mst = VOP_REG(RK3308_LIT_WIN1_MST, 0xffffffff, 0), -+ .yrgb_vir = VOP_REG(RK3308_LIT_WIN1_VIR, 0x1fff, 0), -+ -+ .alpha_pre_mul = VOP_REG(RK3308_LIT_WIN1_ALPHA_CTRL, 0x1, 2), -+ .alpha_mode = VOP_REG(RK3308_LIT_WIN1_ALPHA_CTRL, 0x1, 1), -+ .alpha_en = VOP_REG(RK3308_LIT_WIN1_ALPHA_CTRL, 0x1, 0), -+}; -+ -+static const struct vop_win_data rk3308_vop_lit_win_data[] = { -+ { .base = 0x00, .phy = &rk3308_lit_win0_data, -+ .type = DRM_PLANE_TYPE_PRIMARY }, -+ { .base = 0x00, .phy = &rk3308_lit_win1_data, -+ .type = DRM_PLANE_TYPE_CURSOR }, -+}; -+ -+static const struct vop_modeset rk3308_modeset = { -+ .htotal_pw = VOP_REG(RK3308_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), -+ .hact_st_end = VOP_REG(RK3308_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), -+ .vtotal_pw = VOP_REG(RK3308_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), -+ .vact_st_end = VOP_REG(RK3308_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), -+}; -+ -+static const struct vop_data rk3308_vop = { -+ .version = VOP_VERSION(2, 7), -+ .output = &rk3308_ctrl_data, -+ .common = &rk3308_common, -+ .modeset = &rk3308_modeset, -+ .intr = &rk3308_lit_intr, -+ .win = rk3308_vop_lit_win_data, -+ .win_size = ARRAY_SIZE(rk3308_vop_lit_win_data), -+ .feature = VOP_FEATURE_INTERNAL_RGB, -+ .max_output = { 1280, 800 }, -+}; -+ - static const struct vop_common rv1126_common = { - .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), - .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), -@@ -1254,6 +1354,8 @@ static const struct of_device_id vop_driver_dt_match[] = { - .data = &rk3188_vop }, - { .compatible = "rockchip,rk3288-vop", - .data = &rk3288_vop }, -+ { .compatible = "rockchip,rk3308-vop", -+ .data = &rk3308_vop }, - { .compatible = "rockchip,rk3368-vop", - .data = &rk3368_vop }, - { .compatible = "rockchip,rk3366-vop", -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h -@@ -1033,4 +1033,64 @@ - #define RK3066_DSP_LUT_ADDR 0x800 - /* rk3066 register definition end */ - -+/* rk3308 register definition */ -+#define RK3308_LIT_REG_CFG_DONE 0x00000 -+#define RK3308_LIT_VERSION 0x00004 -+#define RK3308_LIT_DSP_BG 0x00008 -+#define RK3308_LIT_MCU_CTRL 0x0000c -+#define RK3308_LIT_SYS_CTRL0 0x00010 -+#define RK3308_LIT_SYS_CTRL1 0x00014 -+#define RK3308_LIT_SYS_CTRL2 0x00018 -+#define RK3308_LIT_DSP_CTRL0 0x00020 -+#define RK3308_LIT_DSP_CTRL2 0x00028 -+#define RK3308_LIT_VOP_STATUS 0x0002c -+#define RK3308_LIT_LINE_FLAG 0x00030 -+#define RK3308_LIT_INTR_EN 0x00034 -+#define RK3308_LIT_INTR_CLEAR 0x00038 -+#define RK3308_LIT_INTR_STATUS 0x0003c -+#define RK3308_LIT_WIN0_CTRL0 0x00050 -+#define RK3308_LIT_WIN0_CTRL1 0x00054 -+#define RK3308_LIT_WIN0_COLOR_KEY 0x00058 -+#define RK3308_LIT_WIN0_VIR 0x0005c -+#define RK3308_LIT_WIN0_YRGB_MST0 0x00060 -+#define RK3308_LIT_WIN0_CBR_MST0 0x00064 -+#define RK3308_LIT_WIN0_ACT_INFO 0x00068 -+#define RK3308_LIT_WIN0_DSP_INFO 0x0006c -+#define RK3308_LIT_WIN0_DSP_ST 0x00070 -+#define RK3308_LIT_WIN0_SCL_FACTOR_YRGB 0x00074 -+#define RK3308_LIT_WIN0_SCL_FACTOR_CBR 0x00078 -+#define RK3308_LIT_WIN0_SCL_OFFSET 0x0007c -+#define RK3308_LIT_WIN0_ALPHA_CTRL 0x00080 -+#define RK3308_LIT_WIN1_CTRL0 0x00090 -+#define RK3308_LIT_WIN1_CTRL1 0x00094 -+#define RK3308_LIT_WIN1_VIR 0x00098 -+#define RK3308_LIT_WIN1_MST 0x000a0 -+#define RK3308_LIT_WIN1_DSP_INFO 0x000a4 -+#define RK3308_LIT_WIN1_DSP_ST 0x000a8 -+#define RK3308_LIT_WIN1_COLOR_KEY 0x000ac -+#define RK3308_LIT_WIN1_ALPHA_CTRL 0x000bc -+#define RK3308_LIT_DSP_HTOTAL_HS_END 0x00100 -+#define RK3308_LIT_DSP_HACT_ST_END 0x00104 -+#define RK3308_LIT_DSP_VTOTAL_VS_END 0x00108 -+#define RK3308_LIT_DSP_VACT_ST_END 0x0010c -+#define RK3308_LIT_DSP_VS_ST_END_F1 0x00110 -+#define RK3308_LIT_DSP_VACT_ST_END_F1 0x00114 -+#define RK3308_LIT_BCSH_CTRL 0x00160 -+#define RK3308_LIT_BCSH_COL_BAR 0x00164 -+#define RK3308_LIT_BCSH_BCS 0x00168 -+#define RK3308_LIT_BCSH_H 0x0016c -+#define RK3308_LIT_FRC_LOWER01_0 0x00170 -+#define RK3308_LIT_FRC_LOWER01_1 0x00174 -+#define RK3308_LIT_FRC_LOWER10_0 0x00178 -+#define RK3308_LIT_FRC_LOWER10_1 0x0017c -+#define RK3308_LIT_FRC_LOWER11_0 0x00180 -+#define RK3308_LIT_FRC_LOWER11_1 0x00184 -+#define RK3308_LIT_MCU_RW_BYPASS_PORT 0x0018c -+#define RK3308_LIT_DBG_REG_000 0x00190 -+#define RK3308_LIT_BLANKING_VALUE 0x001f4 -+#define RK3308_LIT_FLAG_REG_FRM_VALID 0x001f8 -+#define RK3308_LIT_FLAG_REG 0x001fc -+#define RK3308_LIT_GAMMA_LUT_ADDR 0x00a00 -+/* rk3308 register definition end */ -+ - #endif /* _ROCKCHIP_VOP_REG_H */ --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3328-add-dmc-driver.patch b/patch/kernel/rockchip64-6.14/rk3328-add-dmc-driver.patch deleted file mode 100644 index 92debe4..0000000 --- a/patch/kernel/rockchip64-6.14/rk3328-add-dmc-driver.patch +++ /dev/null @@ -1,1899 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Tue, 12 Oct 2021 18:45:05 +0000 -Subject: rk3328 dmc driver - ---- - arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi | 311 ++++ - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 61 + - drivers/clk/rockchip/clk-ddr.c | 131 ++ - drivers/clk/rockchip/clk-rk3328.c | 13 +- - drivers/clk/rockchip/clk.h | 3 +- - drivers/devfreq/Kconfig | 12 + - drivers/devfreq/Makefile | 1 + - drivers/devfreq/event/rockchip-dfi.c | 77 +- - drivers/devfreq/rk3328_dmc.c | 836 ++++++++++ - include/dt-bindings/clock/rockchip-ddr.h | 63 + - include/dt-bindings/memory/rk3328-dram.h | 159 ++ - include/soc/rockchip/rk3228_grf.h | 14 + - include/soc/rockchip/rk3328_grf.h | 14 + - include/soc/rockchip/rockchip_sip.h | 11 + - 14 files changed, 1692 insertions(+), 14 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi -@@ -0,0 +1,311 @@ -+/* -+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+#include -+#include -+ -+/ { -+ ddr_timing: ddr_timing { -+ compatible = "rockchip,ddr-timing"; -+ ddr3_speed_bin = ; -+ ddr4_speed_bin = ; -+ pd_idle = <0>; -+ sr_idle = <0>; -+ sr_mc_gate_idle = <0>; -+ srpd_lite_idle = <0>; -+ standby_idle = <0>; -+ -+ auto_pd_dis_freq = <1066>; -+ auto_sr_dis_freq = <800>; -+ ddr3_dll_dis_freq = <300>; -+ ddr4_dll_dis_freq = <625>; -+ phy_dll_dis_freq = <400>; -+ -+ ddr3_odt_dis_freq = <100>; -+ phy_ddr3_odt_dis_freq = <100>; -+ ddr3_drv = ; -+ ddr3_odt = ; -+ phy_ddr3_ca_drv = ; -+ phy_ddr3_ck_drv = ; -+ phy_ddr3_dq_drv = ; -+ phy_ddr3_odt = ; -+ -+ lpddr3_odt_dis_freq = <666>; -+ phy_lpddr3_odt_dis_freq = <666>; -+ lpddr3_drv = ; -+ lpddr3_odt = ; -+ phy_lpddr3_ca_drv = ; -+ phy_lpddr3_ck_drv = ; -+ phy_lpddr3_dq_drv = ; -+ phy_lpddr3_odt = ; -+ -+ lpddr4_odt_dis_freq = <800>; -+ phy_lpddr4_odt_dis_freq = <800>; -+ lpddr4_drv = ; -+ lpddr4_dq_odt = ; -+ lpddr4_ca_odt = ; -+ phy_lpddr4_ca_drv = ; -+ phy_lpddr4_ck_cs_drv = ; -+ phy_lpddr4_dq_drv = ; -+ phy_lpddr4_odt = ; -+ -+ ddr4_odt_dis_freq = <666>; -+ phy_ddr4_odt_dis_freq = <666>; -+ ddr4_drv = ; -+ ddr4_odt = ; -+ phy_ddr4_ca_drv = ; -+ phy_ddr4_ck_drv = ; -+ phy_ddr4_dq_drv = ; -+ phy_ddr4_odt = ; -+ -+ /* CA de-skew, one step is 47.8ps, range 0-15 */ -+ ddr3a1_ddr4a9_de-skew = <7>; -+ ddr3a0_ddr4a10_de-skew = <7>; -+ ddr3a3_ddr4a6_de-skew = <8>; -+ ddr3a2_ddr4a4_de-skew = <8>; -+ ddr3a5_ddr4a8_de-skew = <7>; -+ ddr3a4_ddr4a5_de-skew = <9>; -+ ddr3a7_ddr4a11_de-skew = <7>; -+ ddr3a6_ddr4a7_de-skew = <9>; -+ ddr3a9_ddr4a0_de-skew = <8>; -+ ddr3a8_ddr4a13_de-skew = <7>; -+ ddr3a11_ddr4a3_de-skew = <9>; -+ ddr3a10_ddr4cs0_de-skew = <7>; -+ ddr3a13_ddr4a2_de-skew = <8>; -+ ddr3a12_ddr4ba1_de-skew = <7>; -+ ddr3a15_ddr4odt0_de-skew = <7>; -+ ddr3a14_ddr4a1_de-skew = <8>; -+ ddr3ba1_ddr4a15_de-skew = <7>; -+ ddr3ba0_ddr4bg0_de-skew = <7>; -+ ddr3ras_ddr4cke_de-skew = <7>; -+ ddr3ba2_ddr4ba0_de-skew = <8>; -+ ddr3we_ddr4bg1_de-skew = <8>; -+ ddr3cas_ddr4a12_de-skew = <7>; -+ ddr3ckn_ddr4ckn_de-skew = <8>; -+ ddr3ckp_ddr4ckp_de-skew = <8>; -+ ddr3cke_ddr4a16_de-skew = <8>; -+ ddr3odt0_ddr4a14_de-skew = <7>; -+ ddr3cs0_ddr4act_de-skew = <8>; -+ ddr3reset_ddr4reset_de-skew = <7>; -+ ddr3cs1_ddr4cs1_de-skew = <7>; -+ ddr3odt1_ddr4odt1_de-skew = <7>; -+ -+ /* DATA de-skew -+ * RX one step is 25.1ps, range 0-15 -+ * TX one step is 47.8ps, range 0-15 -+ */ -+ cs0_dm0_rx_de-skew = <7>; -+ cs0_dm0_tx_de-skew = <8>; -+ cs0_dq0_rx_de-skew = <7>; -+ cs0_dq0_tx_de-skew = <8>; -+ cs0_dq1_rx_de-skew = <7>; -+ cs0_dq1_tx_de-skew = <8>; -+ cs0_dq2_rx_de-skew = <7>; -+ cs0_dq2_tx_de-skew = <8>; -+ cs0_dq3_rx_de-skew = <7>; -+ cs0_dq3_tx_de-skew = <8>; -+ cs0_dq4_rx_de-skew = <7>; -+ cs0_dq4_tx_de-skew = <8>; -+ cs0_dq5_rx_de-skew = <7>; -+ cs0_dq5_tx_de-skew = <8>; -+ cs0_dq6_rx_de-skew = <7>; -+ cs0_dq6_tx_de-skew = <8>; -+ cs0_dq7_rx_de-skew = <7>; -+ cs0_dq7_tx_de-skew = <8>; -+ cs0_dqs0_rx_de-skew = <6>; -+ cs0_dqs0p_tx_de-skew = <9>; -+ cs0_dqs0n_tx_de-skew = <9>; -+ -+ cs0_dm1_rx_de-skew = <7>; -+ cs0_dm1_tx_de-skew = <7>; -+ cs0_dq8_rx_de-skew = <7>; -+ cs0_dq8_tx_de-skew = <8>; -+ cs0_dq9_rx_de-skew = <7>; -+ cs0_dq9_tx_de-skew = <7>; -+ cs0_dq10_rx_de-skew = <7>; -+ cs0_dq10_tx_de-skew = <8>; -+ cs0_dq11_rx_de-skew = <7>; -+ cs0_dq11_tx_de-skew = <7>; -+ cs0_dq12_rx_de-skew = <7>; -+ cs0_dq12_tx_de-skew = <8>; -+ cs0_dq13_rx_de-skew = <7>; -+ cs0_dq13_tx_de-skew = <7>; -+ cs0_dq14_rx_de-skew = <7>; -+ cs0_dq14_tx_de-skew = <8>; -+ cs0_dq15_rx_de-skew = <7>; -+ cs0_dq15_tx_de-skew = <7>; -+ cs0_dqs1_rx_de-skew = <7>; -+ cs0_dqs1p_tx_de-skew = <9>; -+ cs0_dqs1n_tx_de-skew = <9>; -+ -+ cs0_dm2_rx_de-skew = <7>; -+ cs0_dm2_tx_de-skew = <8>; -+ cs0_dq16_rx_de-skew = <7>; -+ cs0_dq16_tx_de-skew = <8>; -+ cs0_dq17_rx_de-skew = <7>; -+ cs0_dq17_tx_de-skew = <8>; -+ cs0_dq18_rx_de-skew = <7>; -+ cs0_dq18_tx_de-skew = <8>; -+ cs0_dq19_rx_de-skew = <7>; -+ cs0_dq19_tx_de-skew = <8>; -+ cs0_dq20_rx_de-skew = <7>; -+ cs0_dq20_tx_de-skew = <8>; -+ cs0_dq21_rx_de-skew = <7>; -+ cs0_dq21_tx_de-skew = <8>; -+ cs0_dq22_rx_de-skew = <7>; -+ cs0_dq22_tx_de-skew = <8>; -+ cs0_dq23_rx_de-skew = <7>; -+ cs0_dq23_tx_de-skew = <8>; -+ cs0_dqs2_rx_de-skew = <6>; -+ cs0_dqs2p_tx_de-skew = <9>; -+ cs0_dqs2n_tx_de-skew = <9>; -+ -+ cs0_dm3_rx_de-skew = <7>; -+ cs0_dm3_tx_de-skew = <7>; -+ cs0_dq24_rx_de-skew = <7>; -+ cs0_dq24_tx_de-skew = <8>; -+ cs0_dq25_rx_de-skew = <7>; -+ cs0_dq25_tx_de-skew = <7>; -+ cs0_dq26_rx_de-skew = <7>; -+ cs0_dq26_tx_de-skew = <7>; -+ cs0_dq27_rx_de-skew = <7>; -+ cs0_dq27_tx_de-skew = <7>; -+ cs0_dq28_rx_de-skew = <7>; -+ cs0_dq28_tx_de-skew = <7>; -+ cs0_dq29_rx_de-skew = <7>; -+ cs0_dq29_tx_de-skew = <7>; -+ cs0_dq30_rx_de-skew = <7>; -+ cs0_dq30_tx_de-skew = <7>; -+ cs0_dq31_rx_de-skew = <7>; -+ cs0_dq31_tx_de-skew = <7>; -+ cs0_dqs3_rx_de-skew = <7>; -+ cs0_dqs3p_tx_de-skew = <9>; -+ cs0_dqs3n_tx_de-skew = <9>; -+ -+ cs1_dm0_rx_de-skew = <7>; -+ cs1_dm0_tx_de-skew = <8>; -+ cs1_dq0_rx_de-skew = <7>; -+ cs1_dq0_tx_de-skew = <8>; -+ cs1_dq1_rx_de-skew = <7>; -+ cs1_dq1_tx_de-skew = <8>; -+ cs1_dq2_rx_de-skew = <7>; -+ cs1_dq2_tx_de-skew = <8>; -+ cs1_dq3_rx_de-skew = <7>; -+ cs1_dq3_tx_de-skew = <8>; -+ cs1_dq4_rx_de-skew = <7>; -+ cs1_dq4_tx_de-skew = <8>; -+ cs1_dq5_rx_de-skew = <7>; -+ cs1_dq5_tx_de-skew = <8>; -+ cs1_dq6_rx_de-skew = <7>; -+ cs1_dq6_tx_de-skew = <8>; -+ cs1_dq7_rx_de-skew = <7>; -+ cs1_dq7_tx_de-skew = <8>; -+ cs1_dqs0_rx_de-skew = <6>; -+ cs1_dqs0p_tx_de-skew = <9>; -+ cs1_dqs0n_tx_de-skew = <9>; -+ -+ cs1_dm1_rx_de-skew = <7>; -+ cs1_dm1_tx_de-skew = <7>; -+ cs1_dq8_rx_de-skew = <7>; -+ cs1_dq8_tx_de-skew = <8>; -+ cs1_dq9_rx_de-skew = <7>; -+ cs1_dq9_tx_de-skew = <7>; -+ cs1_dq10_rx_de-skew = <7>; -+ cs1_dq10_tx_de-skew = <8>; -+ cs1_dq11_rx_de-skew = <7>; -+ cs1_dq11_tx_de-skew = <7>; -+ cs1_dq12_rx_de-skew = <7>; -+ cs1_dq12_tx_de-skew = <8>; -+ cs1_dq13_rx_de-skew = <7>; -+ cs1_dq13_tx_de-skew = <7>; -+ cs1_dq14_rx_de-skew = <7>; -+ cs1_dq14_tx_de-skew = <8>; -+ cs1_dq15_rx_de-skew = <7>; -+ cs1_dq15_tx_de-skew = <7>; -+ cs1_dqs1_rx_de-skew = <7>; -+ cs1_dqs1p_tx_de-skew = <9>; -+ cs1_dqs1n_tx_de-skew = <9>; -+ -+ cs1_dm2_rx_de-skew = <7>; -+ cs1_dm2_tx_de-skew = <8>; -+ cs1_dq16_rx_de-skew = <7>; -+ cs1_dq16_tx_de-skew = <8>; -+ cs1_dq17_rx_de-skew = <7>; -+ cs1_dq17_tx_de-skew = <8>; -+ cs1_dq18_rx_de-skew = <7>; -+ cs1_dq18_tx_de-skew = <8>; -+ cs1_dq19_rx_de-skew = <7>; -+ cs1_dq19_tx_de-skew = <8>; -+ cs1_dq20_rx_de-skew = <7>; -+ cs1_dq20_tx_de-skew = <8>; -+ cs1_dq21_rx_de-skew = <7>; -+ cs1_dq21_tx_de-skew = <8>; -+ cs1_dq22_rx_de-skew = <7>; -+ cs1_dq22_tx_de-skew = <8>; -+ cs1_dq23_rx_de-skew = <7>; -+ cs1_dq23_tx_de-skew = <8>; -+ cs1_dqs2_rx_de-skew = <6>; -+ cs1_dqs2p_tx_de-skew = <9>; -+ cs1_dqs2n_tx_de-skew = <9>; -+ -+ cs1_dm3_rx_de-skew = <7>; -+ cs1_dm3_tx_de-skew = <7>; -+ cs1_dq24_rx_de-skew = <7>; -+ cs1_dq24_tx_de-skew = <8>; -+ cs1_dq25_rx_de-skew = <7>; -+ cs1_dq25_tx_de-skew = <7>; -+ cs1_dq26_rx_de-skew = <7>; -+ cs1_dq26_tx_de-skew = <7>; -+ cs1_dq27_rx_de-skew = <7>; -+ cs1_dq27_tx_de-skew = <7>; -+ cs1_dq28_rx_de-skew = <7>; -+ cs1_dq28_tx_de-skew = <7>; -+ cs1_dq29_rx_de-skew = <7>; -+ cs1_dq29_tx_de-skew = <7>; -+ cs1_dq30_rx_de-skew = <7>; -+ cs1_dq30_tx_de-skew = <7>; -+ cs1_dq31_rx_de-skew = <7>; -+ cs1_dq31_tx_de-skew = <7>; -+ cs1_dqs3_rx_de-skew = <7>; -+ cs1_dqs3p_tx_de-skew = <9>; -+ cs1_dqs3n_tx_de-skew = <9>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -595,6 +595,67 @@ tsadc: tsadc@ff250000 { - status = "disabled"; - }; - -+ dfi: dfi@ff790000 { -+ reg = <0x00 0xff790000 0x00 0x400>; -+ compatible = "rockchip,rk3328-dfi"; -+ rockchip,grf = <&grf>; -+ status = "okay"; -+ }; -+ -+ dmc: dmc@ff780000 { -+ reg = <0x00 0xff780000 0x00 0x400>; -+ compatible = "rockchip,rk3328-dmc"; -+ devfreq-events = <&dfi>; -+ clocks = <&cru SCLK_DDRCLK>; -+ clock-names = "dmc_clk"; -+ operating-points-v2 = <&dmc_opp_table>; -+ #cooling-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ dmc_opp_table: dmc-opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <1000000 1000000 1200000>; -+ }; -+ -+ opp-666000000 { -+ opp-hz = /bits/ 64 <666000000>; -+ opp-microvolt = <1025000 1025000 1200000>; -+ }; -+ -+ opp-786000000 { -+ opp-hz = /bits/ 64 <786000000>; -+ opp-microvolt = <1050000 1050000 1200000>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <1050000 1050000 1200000>; -+ status = "disabled"; -+ }; -+ -+ opp-850000000 { -+ opp-hz = /bits/ 64 <850000000>; -+ opp-microvolt = <1050000 1050000 1200000>; // Untested -+ status = "disabled"; -+ }; -+ -+ opp-933000000 { -+ opp-hz = /bits/ 64 <933000000>; -+ opp-microvolt = <1100000 1100000 1200000>; // Untested -+ status = "disabled"; -+ }; -+ -+ opp-1066000000 { -+ opp-hz = /bits/ 64 <1066000000>; -+ opp-microvolt = <1150000 1150000 1200000>; // Untested -+ status = "disabled"; -+ }; -+ }; -+ - efuse: efuse@ff260000 { - compatible = "rockchip,rk3328-efuse"; - reg = <0x0 0xff260000 0x0 0x50>; -diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c -index 111111111111..222222222222 100644 ---- a/drivers/clk/rockchip/clk-ddr.c -+++ b/drivers/clk/rockchip/clk-ddr.c -@@ -87,6 +87,134 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = { - .get_parent = rockchip_ddrclk_get_parent, - }; - -+/* See v4.4/include/dt-bindings/display/rk_fb.h */ -+#define SCREEN_NULL 0 -+#define SCREEN_HDMI 6 -+ -+static inline int rk_drm_get_lcdc_type(void) -+{ -+ return SCREEN_NULL; -+} -+ -+struct share_params { -+ u32 hz; -+ u32 lcdc_type; -+ u32 vop; -+ u32 vop_dclk_mode; -+ u32 sr_idle_en; -+ u32 addr_mcu_el3; -+ /* -+ * 1: need to wait flag1 -+ * 0: never wait flag1 -+ */ -+ u32 wait_flag1; -+ /* -+ * 1: need to wait flag1 -+ * 0: never wait flag1 -+ */ -+ u32 wait_flag0; -+ u32 complt_hwirq; -+ /* if need, add parameter after */ -+}; -+ -+struct rockchip_ddrclk_data { -+ u32 inited_flag; -+ void __iomem *share_memory; -+}; -+ -+static struct rockchip_ddrclk_data ddr_data; -+ -+static void rockchip_ddrclk_data_init(void) -+{ -+ struct arm_smccc_res res; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM, -+ 1, SHARE_PAGE_TYPE_DDR, 0, -+ 0, 0, 0, 0, &res); -+ -+ if (!res.a0) { -+ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12); -+ ddr_data.inited_flag = 1; -+ } -+} -+ -+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw, -+ unsigned long drate, -+ unsigned long prate) -+{ -+ struct share_params *p; -+ struct arm_smccc_res res; -+ -+ if (!ddr_data.inited_flag) -+ rockchip_ddrclk_data_init(); -+ -+ p = (struct share_params *)ddr_data.share_memory; -+ -+ p->hz = drate; -+ p->lcdc_type = rk_drm_get_lcdc_type(); -+ p->wait_flag1 = 1; -+ p->wait_flag0 = 1; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, -+ SHARE_PAGE_TYPE_DDR, 0, -+ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE, -+ 0, 0, 0, 0, &res); -+ -+ if ((int)res.a1 == -6) { -+ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000); -+ /* TODO: rockchip_dmcfreq_wait_complete(); */ -+ } -+ -+ return res.a0; -+} -+ -+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2 -+ (struct clk_hw *hw, unsigned long parent_rate) -+{ -+ struct arm_smccc_res res; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, -+ SHARE_PAGE_TYPE_DDR, 0, -+ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE, -+ 0, 0, 0, 0, &res); -+ if (!res.a0) -+ return res.a1; -+ else -+ return 0; -+} -+ -+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw, -+ unsigned long rate, -+ unsigned long *prate) -+{ -+ struct share_params *p; -+ struct arm_smccc_res res; -+ -+ if (!ddr_data.inited_flag) -+ rockchip_ddrclk_data_init(); -+ -+ p = (struct share_params *)ddr_data.share_memory; -+ -+ p->hz = rate; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, -+ SHARE_PAGE_TYPE_DDR, 0, -+ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE, -+ 0, 0, 0, 0, &res); -+ -+ if (!res.a0) -+ return res.a1; -+ else -+ return 0; -+} -+ -+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = { -+ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2, -+ .set_rate = rockchip_ddrclk_sip_set_rate_v2, -+ .round_rate = rockchip_ddrclk_sip_round_rate_v2, -+ .get_parent = rockchip_ddrclk_get_parent, -+}; -+ - struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, - const char *const *parent_names, - u8 num_parents, int mux_offset, -@@ -114,6 +242,9 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, - case ROCKCHIP_DDRCLK_SIP: - init.ops = &rockchip_ddrclk_sip_ops; - break; -+ case ROCKCHIP_DDRCLK_SIP_V2: -+ init.ops = &rockchip_ddrclk_sip_ops_v2; -+ break; - default: - pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag); - kfree(ddrclk); -diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c -index 111111111111..222222222222 100644 ---- a/drivers/clk/rockchip/clk-rk3328.c -+++ b/drivers/clk/rockchip/clk-rk3328.c -@@ -315,14 +315,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { - RK3328_CLKGATE_CON(14), 1, GFLAGS), - - /* PD_DDR */ -- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED, -- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, -- RK3328_CLKGATE_CON(0), 4, GFLAGS), -- GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED, -+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0, -+ RK3328_CLKSEL_CON(3), 8, 2, 0, 3, -+ ROCKCHIP_DDRCLK_SIP_V2), -+ -+ GATE(0, "clk_ddrmsch", "sclk_ddrc", CLK_IGNORE_UNUSED, - RK3328_CLKGATE_CON(18), 6, GFLAGS), -- GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, -+ GATE(0, "clk_ddrupctl", "sclk_ddrc", CLK_IGNORE_UNUSED, - RK3328_CLKGATE_CON(18), 5, GFLAGS), -- GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, -+ GATE(0, "aclk_ddrupctl", "sclk_ddrc", CLK_IGNORE_UNUSED, - RK3328_CLKGATE_CON(18), 4, GFLAGS), - GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED, - RK3328_CLKGATE_CON(0), 6, GFLAGS), -diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h -index 111111111111..222222222222 100644 ---- a/drivers/clk/rockchip/clk.h -+++ b/drivers/clk/rockchip/clk.h -@@ -539,7 +539,8 @@ struct clk *rockchip_clk_register_mmc(const char *name, - * DDRCLK flags, including method of setting the rate - * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. - */ --#define ROCKCHIP_DDRCLK_SIP BIT(0) -+#define ROCKCHIP_DDRCLK_SIP 0x01 -+#define ROCKCHIP_DDRCLK_SIP_V2 0x03 - - struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, - const char *const *parent_names, -diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/devfreq/Kconfig -+++ b/drivers/devfreq/Kconfig -@@ -129,6 +129,18 @@ config ARM_MEDIATEK_CCI_DEVFREQ - buck voltages and update a proper CCI frequency. Use the notification - to get the regulator status. - -+config ARM_RK3328_DMC_DEVFREQ -+ tristate "ARM RK3328 DMC DEVFREQ Driver" -+ depends on ARCH_ROCKCHIP -+ select DEVFREQ_EVENT_ROCKCHIP_DFI -+ select DEVFREQ_GOV_SIMPLE_ONDEMAND -+ select PM_DEVFREQ_EVENT -+ select PM_OPP -+ help -+ This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller). -+ It sets the frequency for the memory controller and reads the usage counts -+ from hardware. -+ - config ARM_RK3399_DMC_DEVFREQ - tristate "ARM RK3399 DMC DEVFREQ Driver" - depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \ -diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/devfreq/Makefile -+++ b/drivers/devfreq/Makefile -@@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o - obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o - obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o - obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o -+obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o - obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o - obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o - -diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c -index 111111111111..222222222222 100644 ---- a/drivers/devfreq/event/rockchip-dfi.c -+++ b/drivers/devfreq/event/rockchip-dfi.c -@@ -24,6 +24,8 @@ - #include - - #include -+#include -+#include - #include - #include - #include -@@ -99,6 +101,7 @@ struct rockchip_dfi { - - struct device *dev; - void __iomem *regs; -+ struct regmap *regmap_grf; - struct regmap *regmap_pmu; - struct clk *clk; - int usecount; -@@ -669,6 +672,46 @@ static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi) - } - #endif - -+static int rk3228_dfi_init(struct rockchip_dfi *dfi) -+{ -+ u32 val; -+ -+ regmap_read(dfi->regmap_grf, RK3228_GRF_OS_REG2, &val); -+ dfi->ddr_type = FIELD_GET(RK3228_GRF_OS_REG2_DDRTYPE, val); -+ -+ dfi->channel_mask = GENMASK(0, 0); -+ dfi->max_channels = 1; -+ -+ dfi->buswidth[0] = 2; // 16 bit bus width -+ -+ dfi->ddrmon_stride = 0x0; // single channel controller -+ dfi->ddrmon_ctrl_single = true; -+ -+ dfi->clk = NULL; -+ -+ return 0; -+} -+ -+static int rk3328_dfi_init(struct rockchip_dfi *dfi) -+{ -+ u32 val; -+ -+ regmap_read(dfi->regmap_grf, RK3328_GRF_OS_REG2, &val); -+ dfi->ddr_type = FIELD_GET(RK3328_GRF_OS_REG2_DDRTYPE, val); -+ -+ dfi->channel_mask = GENMASK(0, 0); -+ dfi->max_channels = 1; -+ -+ dfi->buswidth[0] = 2; // 16 bit bus width -+ -+ dfi->ddrmon_stride = 0x0; // single channel controller -+ dfi->ddrmon_ctrl_single = true; -+ -+ dfi->clk = NULL; -+ -+ return 0; -+} -+ - static int rk3399_dfi_init(struct rockchip_dfi *dfi) - { - struct regmap *regmap_pmu = dfi->regmap_pmu; -@@ -757,6 +800,8 @@ static int rk3588_dfi_init(struct rockchip_dfi *dfi) - }; - - static const struct of_device_id rockchip_dfi_id_match[] = { -+ { .compatible = "rockchip,rk3228-dfi", .data = rk3228_dfi_init }, -+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init }, - { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init }, - { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init }, - { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init }, -@@ -786,14 +831,30 @@ static int rockchip_dfi_probe(struct platform_device *pdev) - if (IS_ERR(dfi->regs)) - return PTR_ERR(dfi->regs); - -- node = of_parse_phandle(np, "rockchip,pmu", 0); -- if (!node) -- return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n"); -+ if (soc_init == rk3228_dfi_init || -+ soc_init == rk3328_dfi_init) { -+ node = of_parse_phandle(np, "rockchip,grf", 0); -+ if (!node) -+ return dev_err_probe(&pdev->dev, -ENODEV, "Can't find grf registers"); - -- dfi->regmap_pmu = syscon_node_to_regmap(node); -- of_node_put(node); -- if (IS_ERR(dfi->regmap_pmu)) -- return PTR_ERR(dfi->regmap_pmu); -+ dfi->regmap_grf = syscon_node_to_regmap(node); -+ of_node_put(node); -+ if (IS_ERR(dfi->regmap_grf)) -+ return PTR_ERR(dfi->regmap_grf); -+ } -+ -+ if (soc_init == rk3399_dfi_init || -+ soc_init == rk3568_dfi_init || -+ soc_init == rk3588_dfi_init) { -+ node = of_parse_phandle(np, "rockchip,pmu", 0); -+ if (!node) -+ return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n"); -+ -+ dfi->regmap_pmu = syscon_node_to_regmap(node); -+ of_node_put(node); -+ if (IS_ERR(dfi->regmap_pmu)) -+ return PTR_ERR(dfi->regmap_pmu); -+ } - - dfi->dev = dev; - mutex_init(&dfi->mutex); -@@ -818,6 +879,8 @@ static int rockchip_dfi_probe(struct platform_device *pdev) - if (ret) - return ret; - -+ dev_notice(dfi->dev, "dfi initialized, dram type: 0x%x, channels: %d\n", dfi->ddr_type, dfi->max_channels); -+ - platform_set_drvdata(pdev, dfi); - - return 0; -diff --git a/drivers/devfreq/rk3328_dmc.c b/drivers/devfreq/rk3328_dmc.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/devfreq/rk3328_dmc.c -@@ -0,0 +1,836 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd. -+ * Author: Lin Huang -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DTS_PAR_OFFSET (4096) -+ -+struct share_params { -+ u32 hz; -+ u32 lcdc_type; -+ u32 vop; -+ u32 vop_dclk_mode; -+ u32 sr_idle_en; -+ u32 addr_mcu_el3; -+ /* -+ * 1: need to wait flag1 -+ * 0: never wait flag1 -+ */ -+ u32 wait_flag1; -+ /* -+ * 1: need to wait flag1 -+ * 0: never wait flag1 -+ */ -+ u32 wait_flag0; -+ u32 complt_hwirq; -+ /* if need, add parameter after */ -+}; -+ -+static struct share_params *ddr_psci_param; -+ -+/* hope this define can adapt all future platform */ -+static const char * const rk3328_dts_timing[] = { -+ "ddr3_speed_bin", -+ "ddr4_speed_bin", -+ "pd_idle", -+ "sr_idle", -+ "sr_mc_gate_idle", -+ "srpd_lite_idle", -+ "standby_idle", -+ -+ "auto_pd_dis_freq", -+ "auto_sr_dis_freq", -+ "ddr3_dll_dis_freq", -+ "ddr4_dll_dis_freq", -+ "phy_dll_dis_freq", -+ -+ "ddr3_odt_dis_freq", -+ "phy_ddr3_odt_dis_freq", -+ "ddr3_drv", -+ "ddr3_odt", -+ "phy_ddr3_ca_drv", -+ "phy_ddr3_ck_drv", -+ "phy_ddr3_dq_drv", -+ "phy_ddr3_odt", -+ -+ "lpddr3_odt_dis_freq", -+ "phy_lpddr3_odt_dis_freq", -+ "lpddr3_drv", -+ "lpddr3_odt", -+ "phy_lpddr3_ca_drv", -+ "phy_lpddr3_ck_drv", -+ "phy_lpddr3_dq_drv", -+ "phy_lpddr3_odt", -+ -+ "lpddr4_odt_dis_freq", -+ "phy_lpddr4_odt_dis_freq", -+ "lpddr4_drv", -+ "lpddr4_dq_odt", -+ "lpddr4_ca_odt", -+ "phy_lpddr4_ca_drv", -+ "phy_lpddr4_ck_cs_drv", -+ "phy_lpddr4_dq_drv", -+ "phy_lpddr4_odt", -+ -+ "ddr4_odt_dis_freq", -+ "phy_ddr4_odt_dis_freq", -+ "ddr4_drv", -+ "ddr4_odt", -+ "phy_ddr4_ca_drv", -+ "phy_ddr4_ck_drv", -+ "phy_ddr4_dq_drv", -+ "phy_ddr4_odt", -+}; -+ -+static const char * const rk3328_dts_ca_timing[] = { -+ "ddr3a1_ddr4a9_de-skew", -+ "ddr3a0_ddr4a10_de-skew", -+ "ddr3a3_ddr4a6_de-skew", -+ "ddr3a2_ddr4a4_de-skew", -+ "ddr3a5_ddr4a8_de-skew", -+ "ddr3a4_ddr4a5_de-skew", -+ "ddr3a7_ddr4a11_de-skew", -+ "ddr3a6_ddr4a7_de-skew", -+ "ddr3a9_ddr4a0_de-skew", -+ "ddr3a8_ddr4a13_de-skew", -+ "ddr3a11_ddr4a3_de-skew", -+ "ddr3a10_ddr4cs0_de-skew", -+ "ddr3a13_ddr4a2_de-skew", -+ "ddr3a12_ddr4ba1_de-skew", -+ "ddr3a15_ddr4odt0_de-skew", -+ "ddr3a14_ddr4a1_de-skew", -+ "ddr3ba1_ddr4a15_de-skew", -+ "ddr3ba0_ddr4bg0_de-skew", -+ "ddr3ras_ddr4cke_de-skew", -+ "ddr3ba2_ddr4ba0_de-skew", -+ "ddr3we_ddr4bg1_de-skew", -+ "ddr3cas_ddr4a12_de-skew", -+ "ddr3ckn_ddr4ckn_de-skew", -+ "ddr3ckp_ddr4ckp_de-skew", -+ "ddr3cke_ddr4a16_de-skew", -+ "ddr3odt0_ddr4a14_de-skew", -+ "ddr3cs0_ddr4act_de-skew", -+ "ddr3reset_ddr4reset_de-skew", -+ "ddr3cs1_ddr4cs1_de-skew", -+ "ddr3odt1_ddr4odt1_de-skew", -+}; -+ -+static const char * const rk3328_dts_cs0_timing[] = { -+ "cs0_dm0_rx_de-skew", -+ "cs0_dm0_tx_de-skew", -+ "cs0_dq0_rx_de-skew", -+ "cs0_dq0_tx_de-skew", -+ "cs0_dq1_rx_de-skew", -+ "cs0_dq1_tx_de-skew", -+ "cs0_dq2_rx_de-skew", -+ "cs0_dq2_tx_de-skew", -+ "cs0_dq3_rx_de-skew", -+ "cs0_dq3_tx_de-skew", -+ "cs0_dq4_rx_de-skew", -+ "cs0_dq4_tx_de-skew", -+ "cs0_dq5_rx_de-skew", -+ "cs0_dq5_tx_de-skew", -+ "cs0_dq6_rx_de-skew", -+ "cs0_dq6_tx_de-skew", -+ "cs0_dq7_rx_de-skew", -+ "cs0_dq7_tx_de-skew", -+ "cs0_dqs0_rx_de-skew", -+ "cs0_dqs0p_tx_de-skew", -+ "cs0_dqs0n_tx_de-skew", -+ -+ "cs0_dm1_rx_de-skew", -+ "cs0_dm1_tx_de-skew", -+ "cs0_dq8_rx_de-skew", -+ "cs0_dq8_tx_de-skew", -+ "cs0_dq9_rx_de-skew", -+ "cs0_dq9_tx_de-skew", -+ "cs0_dq10_rx_de-skew", -+ "cs0_dq10_tx_de-skew", -+ "cs0_dq11_rx_de-skew", -+ "cs0_dq11_tx_de-skew", -+ "cs0_dq12_rx_de-skew", -+ "cs0_dq12_tx_de-skew", -+ "cs0_dq13_rx_de-skew", -+ "cs0_dq13_tx_de-skew", -+ "cs0_dq14_rx_de-skew", -+ "cs0_dq14_tx_de-skew", -+ "cs0_dq15_rx_de-skew", -+ "cs0_dq15_tx_de-skew", -+ "cs0_dqs1_rx_de-skew", -+ "cs0_dqs1p_tx_de-skew", -+ "cs0_dqs1n_tx_de-skew", -+ -+ "cs0_dm2_rx_de-skew", -+ "cs0_dm2_tx_de-skew", -+ "cs0_dq16_rx_de-skew", -+ "cs0_dq16_tx_de-skew", -+ "cs0_dq17_rx_de-skew", -+ "cs0_dq17_tx_de-skew", -+ "cs0_dq18_rx_de-skew", -+ "cs0_dq18_tx_de-skew", -+ "cs0_dq19_rx_de-skew", -+ "cs0_dq19_tx_de-skew", -+ "cs0_dq20_rx_de-skew", -+ "cs0_dq20_tx_de-skew", -+ "cs0_dq21_rx_de-skew", -+ "cs0_dq21_tx_de-skew", -+ "cs0_dq22_rx_de-skew", -+ "cs0_dq22_tx_de-skew", -+ "cs0_dq23_rx_de-skew", -+ "cs0_dq23_tx_de-skew", -+ "cs0_dqs2_rx_de-skew", -+ "cs0_dqs2p_tx_de-skew", -+ "cs0_dqs2n_tx_de-skew", -+ -+ "cs0_dm3_rx_de-skew", -+ "cs0_dm3_tx_de-skew", -+ "cs0_dq24_rx_de-skew", -+ "cs0_dq24_tx_de-skew", -+ "cs0_dq25_rx_de-skew", -+ "cs0_dq25_tx_de-skew", -+ "cs0_dq26_rx_de-skew", -+ "cs0_dq26_tx_de-skew", -+ "cs0_dq27_rx_de-skew", -+ "cs0_dq27_tx_de-skew", -+ "cs0_dq28_rx_de-skew", -+ "cs0_dq28_tx_de-skew", -+ "cs0_dq29_rx_de-skew", -+ "cs0_dq29_tx_de-skew", -+ "cs0_dq30_rx_de-skew", -+ "cs0_dq30_tx_de-skew", -+ "cs0_dq31_rx_de-skew", -+ "cs0_dq31_tx_de-skew", -+ "cs0_dqs3_rx_de-skew", -+ "cs0_dqs3p_tx_de-skew", -+ "cs0_dqs3n_tx_de-skew", -+}; -+ -+static const char * const rk3328_dts_cs1_timing[] = { -+ "cs1_dm0_rx_de-skew", -+ "cs1_dm0_tx_de-skew", -+ "cs1_dq0_rx_de-skew", -+ "cs1_dq0_tx_de-skew", -+ "cs1_dq1_rx_de-skew", -+ "cs1_dq1_tx_de-skew", -+ "cs1_dq2_rx_de-skew", -+ "cs1_dq2_tx_de-skew", -+ "cs1_dq3_rx_de-skew", -+ "cs1_dq3_tx_de-skew", -+ "cs1_dq4_rx_de-skew", -+ "cs1_dq4_tx_de-skew", -+ "cs1_dq5_rx_de-skew", -+ "cs1_dq5_tx_de-skew", -+ "cs1_dq6_rx_de-skew", -+ "cs1_dq6_tx_de-skew", -+ "cs1_dq7_rx_de-skew", -+ "cs1_dq7_tx_de-skew", -+ "cs1_dqs0_rx_de-skew", -+ "cs1_dqs0p_tx_de-skew", -+ "cs1_dqs0n_tx_de-skew", -+ -+ "cs1_dm1_rx_de-skew", -+ "cs1_dm1_tx_de-skew", -+ "cs1_dq8_rx_de-skew", -+ "cs1_dq8_tx_de-skew", -+ "cs1_dq9_rx_de-skew", -+ "cs1_dq9_tx_de-skew", -+ "cs1_dq10_rx_de-skew", -+ "cs1_dq10_tx_de-skew", -+ "cs1_dq11_rx_de-skew", -+ "cs1_dq11_tx_de-skew", -+ "cs1_dq12_rx_de-skew", -+ "cs1_dq12_tx_de-skew", -+ "cs1_dq13_rx_de-skew", -+ "cs1_dq13_tx_de-skew", -+ "cs1_dq14_rx_de-skew", -+ "cs1_dq14_tx_de-skew", -+ "cs1_dq15_rx_de-skew", -+ "cs1_dq15_tx_de-skew", -+ "cs1_dqs1_rx_de-skew", -+ "cs1_dqs1p_tx_de-skew", -+ "cs1_dqs1n_tx_de-skew", -+ -+ "cs1_dm2_rx_de-skew", -+ "cs1_dm2_tx_de-skew", -+ "cs1_dq16_rx_de-skew", -+ "cs1_dq16_tx_de-skew", -+ "cs1_dq17_rx_de-skew", -+ "cs1_dq17_tx_de-skew", -+ "cs1_dq18_rx_de-skew", -+ "cs1_dq18_tx_de-skew", -+ "cs1_dq19_rx_de-skew", -+ "cs1_dq19_tx_de-skew", -+ "cs1_dq20_rx_de-skew", -+ "cs1_dq20_tx_de-skew", -+ "cs1_dq21_rx_de-skew", -+ "cs1_dq21_tx_de-skew", -+ "cs1_dq22_rx_de-skew", -+ "cs1_dq22_tx_de-skew", -+ "cs1_dq23_rx_de-skew", -+ "cs1_dq23_tx_de-skew", -+ "cs1_dqs2_rx_de-skew", -+ "cs1_dqs2p_tx_de-skew", -+ "cs1_dqs2n_tx_de-skew", -+ -+ "cs1_dm3_rx_de-skew", -+ "cs1_dm3_tx_de-skew", -+ "cs1_dq24_rx_de-skew", -+ "cs1_dq24_tx_de-skew", -+ "cs1_dq25_rx_de-skew", -+ "cs1_dq25_tx_de-skew", -+ "cs1_dq26_rx_de-skew", -+ "cs1_dq26_tx_de-skew", -+ "cs1_dq27_rx_de-skew", -+ "cs1_dq27_tx_de-skew", -+ "cs1_dq28_rx_de-skew", -+ "cs1_dq28_tx_de-skew", -+ "cs1_dq29_rx_de-skew", -+ "cs1_dq29_tx_de-skew", -+ "cs1_dq30_rx_de-skew", -+ "cs1_dq30_tx_de-skew", -+ "cs1_dq31_rx_de-skew", -+ "cs1_dq31_tx_de-skew", -+ "cs1_dqs3_rx_de-skew", -+ "cs1_dqs3p_tx_de-skew", -+ "cs1_dqs3n_tx_de-skew", -+}; -+ -+struct rk3328_ddr_dts_config_timing { -+ unsigned int ddr3_speed_bin; -+ unsigned int ddr4_speed_bin; -+ unsigned int pd_idle; -+ unsigned int sr_idle; -+ unsigned int sr_mc_gate_idle; -+ unsigned int srpd_lite_idle; -+ unsigned int standby_idle; -+ -+ unsigned int auto_pd_dis_freq; -+ unsigned int auto_sr_dis_freq; -+ /* for ddr3 only */ -+ unsigned int ddr3_dll_dis_freq; -+ /* for ddr4 only */ -+ unsigned int ddr4_dll_dis_freq; -+ unsigned int phy_dll_dis_freq; -+ -+ unsigned int ddr3_odt_dis_freq; -+ unsigned int phy_ddr3_odt_dis_freq; -+ unsigned int ddr3_drv; -+ unsigned int ddr3_odt; -+ unsigned int phy_ddr3_ca_drv; -+ unsigned int phy_ddr3_ck_drv; -+ unsigned int phy_ddr3_dq_drv; -+ unsigned int phy_ddr3_odt; -+ -+ unsigned int lpddr3_odt_dis_freq; -+ unsigned int phy_lpddr3_odt_dis_freq; -+ unsigned int lpddr3_drv; -+ unsigned int lpddr3_odt; -+ unsigned int phy_lpddr3_ca_drv; -+ unsigned int phy_lpddr3_ck_drv; -+ unsigned int phy_lpddr3_dq_drv; -+ unsigned int phy_lpddr3_odt; -+ -+ unsigned int lpddr4_odt_dis_freq; -+ unsigned int phy_lpddr4_odt_dis_freq; -+ unsigned int lpddr4_drv; -+ unsigned int lpddr4_dq_odt; -+ unsigned int lpddr4_ca_odt; -+ unsigned int phy_lpddr4_ca_drv; -+ unsigned int phy_lpddr4_ck_cs_drv; -+ unsigned int phy_lpddr4_dq_drv; -+ unsigned int phy_lpddr4_odt; -+ -+ unsigned int ddr4_odt_dis_freq; -+ unsigned int phy_ddr4_odt_dis_freq; -+ unsigned int ddr4_drv; -+ unsigned int ddr4_odt; -+ unsigned int phy_ddr4_ca_drv; -+ unsigned int phy_ddr4_ck_drv; -+ unsigned int phy_ddr4_dq_drv; -+ unsigned int phy_ddr4_odt; -+ -+ unsigned int ca_skew[15]; -+ unsigned int cs0_skew[44]; -+ unsigned int cs1_skew[44]; -+ -+ unsigned int available; -+}; -+ -+struct rk3328_ddr_de_skew_setting { -+ unsigned int ca_de_skew[30]; -+ unsigned int cs0_de_skew[84]; -+ unsigned int cs1_de_skew[84]; -+}; -+ -+struct rk3328_devfreq { -+ struct devfreq *devfreq; -+ struct thermal_cooling_device *cooling; -+}; -+ -+struct rk3328_dmcfreq { -+ struct device *dev; -+ //struct devfreq *devfreq; -+ struct devfreq_simple_ondemand_data ondemand_data; -+ struct clk *dmc_clk; -+ struct devfreq_event_dev *edev; -+ struct mutex lock; -+ struct regulator *vdd_center; -+ struct rk3328_devfreq devfreq; -+ unsigned long rate, target_rate; -+ unsigned long volt, target_volt; -+ -+ int (*set_auto_self_refresh)(u32 en); -+}; -+ -+static void -+rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew, -+ struct rk3328_ddr_dts_config_timing *tim) -+{ -+ u32 n; -+ u32 offset; -+ u32 shift; -+ -+ memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew)); -+ memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew)); -+ memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew)); -+ -+ /* CA de-skew */ -+ for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) { -+ offset = n / 2; -+ shift = n % 2; -+ /* 0 => 4; 1 => 0 */ -+ shift = (shift == 0) ? 4 : 0; -+ tim->ca_skew[offset] &= ~(0xf << shift); -+ tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift); -+ } -+ -+ /* CS0 data de-skew */ -+ for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) { -+ offset = ((n / 21) * 11) + ((n % 21) / 2); -+ shift = ((n % 21) % 2); -+ if ((n % 21) == 20) -+ shift = 0; -+ else -+ /* 0 => 4; 1 => 0 */ -+ shift = (shift == 0) ? 4 : 0; -+ tim->cs0_skew[offset] &= ~(0xf << shift); -+ tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift); -+ } -+ -+ /* CS1 data de-skew */ -+ for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) { -+ offset = ((n / 21) * 11) + ((n % 21) / 2); -+ shift = ((n % 21) % 2); -+ if ((n % 21) == 20) -+ shift = 0; -+ else -+ /* 0 => 4; 1 => 0 */ -+ shift = (shift == 0) ? 4 : 0; -+ tim->cs1_skew[offset] &= ~(0xf << shift); -+ tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift); -+ } -+} -+ -+static void of_get_rk3328_timings(struct device *dev, -+ struct device_node *np, uint32_t *timing) -+{ -+ struct device_node *np_tim; -+ u32 *p; -+ struct rk3328_ddr_dts_config_timing *dts_timing; -+ struct rk3328_ddr_de_skew_setting *de_skew; -+ int ret = 0; -+ u32 i; -+ -+ dts_timing = -+ (struct rk3328_ddr_dts_config_timing *)(timing + -+ DTS_PAR_OFFSET / 4); -+ -+ np_tim = of_parse_phandle(np, "ddr_timing", 0); -+ if (!np_tim) { -+ ret = -EINVAL; -+ goto end; -+ } -+ de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL); -+ if (!de_skew) { -+ ret = -ENOMEM; -+ goto end; -+ } -+ -+ p = (u32 *)dts_timing; -+ for (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) { -+ ret |= of_property_read_u32(np_tim, rk3328_dts_timing[i], -+ p + i); -+ } -+ p = (u32 *)de_skew->ca_de_skew; -+ for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) { -+ ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i], -+ p + i); -+ } -+ p = (u32 *)de_skew->cs0_de_skew; -+ for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) { -+ ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i], -+ p + i); -+ } -+ p = (u32 *)de_skew->cs1_de_skew; -+ for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) { -+ ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i], -+ p + i); -+ } -+ if (!ret) -+ rk3328_de_skew_setting_2_register(de_skew, dts_timing); -+ -+ kfree(de_skew); -+end: -+ if (!ret) { -+ dts_timing->available = 1; -+ } else { -+ dts_timing->available = 0; -+ dev_err(dev, "of_get_ddr_timings: fail\n"); -+ } -+ -+ of_node_put(np_tim); -+} -+ -+static int rockchip_ddr_set_auto_self_refresh(uint32_t en) -+{ -+ struct arm_smccc_res res; -+ -+ ddr_psci_param->sr_idle_en = en; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, -+ SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR, -+ 0, 0, 0, 0, &res); -+ -+ return res.a0; -+} -+ -+static int rk3328_dmc_init(struct platform_device *pdev, -+ struct rk3328_dmcfreq *dmcfreq) -+{ -+ struct arm_smccc_res res; -+ u32 size, page_num; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, -+ 0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION, -+ 0, 0, 0, 0, &res); -+ if (res.a0 || (res.a1 < 0x101)) { -+ dev_err(&pdev->dev, -+ "trusted firmware need to update or is invalid\n"); -+ return -ENXIO; -+ } -+ -+ dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1); -+ -+ /* -+ * first 4KB is used for interface parameters -+ * after 4KB * N is dts parameters -+ */ -+ size = sizeof(struct rk3328_ddr_dts_config_timing); -+ page_num = DIV_ROUND_UP(size, 4096) + 1; -+ -+ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM, -+ page_num, SHARE_PAGE_TYPE_DDR, 0, -+ 0, 0, 0, 0, &res); -+ if (res.a0 != 0) { -+ dev_err(&pdev->dev, "no ATF memory for init\n"); -+ return -ENOMEM; -+ } -+ -+ ddr_psci_param = ioremap(res.a1, page_num << 12); -+ of_get_rk3328_timings(&pdev->dev, pdev->dev.of_node, -+ (uint32_t *)ddr_psci_param); -+ -+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, -+ SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT, -+ 0, 0, 0, 0, &res); -+ if (res.a0) { -+ dev_err(&pdev->dev, "Rockchip dram init error %lx\n", res.a0); -+ return -ENOMEM; -+ } -+ -+ dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh; -+ -+ return 0; -+} -+ -+static int rk3328_dmcfreq_target(struct device *dev, unsigned long *freq, -+ u32 flags) -+{ -+ struct rk3328_dmcfreq *rdev = dev_get_drvdata(dev); -+ struct dev_pm_opp *opp; -+ int err; -+ -+ opp = devfreq_recommended_opp(dev, freq, flags); -+ if (IS_ERR(opp)) -+ return PTR_ERR(opp); -+ dev_pm_opp_put(opp); -+ -+ err = dev_pm_opp_set_rate(dev, *freq); -+ if (err) -+ return err; -+ -+ rdev->rate = *freq; -+ -+ return 0; -+} -+ -+static int rk3328_dmcfreq_get_dev_status(struct device *dev, -+ struct devfreq_dev_status *stat) -+{ -+ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev); -+ struct devfreq_event_data edata; -+ int ret = 0; -+ -+ ret = devfreq_event_get_event(dmcfreq->edev, &edata); -+ if (ret < 0) -+ return ret; -+ -+ stat->current_frequency = dmcfreq->rate; -+ stat->busy_time = edata.load_count; -+ stat->total_time = edata.total_count; -+ -+ return ret; -+} -+ -+static int rk3328_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq) -+{ -+ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev); -+ -+ *freq = dmcfreq->rate; -+ -+ return 0; -+} -+ -+static struct devfreq_dev_profile rk3328_devfreq_dmc_profile = { -+ .polling_ms = 50, -+ .target = rk3328_dmcfreq_target, -+ .get_dev_status = rk3328_dmcfreq_get_dev_status, -+ .get_cur_freq = rk3328_dmcfreq_get_cur_freq, -+}; -+ -+static __maybe_unused int rk3328_dmcfreq_suspend(struct device *dev) -+{ -+ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev); -+ int ret = 0; -+ -+ ret = devfreq_event_disable_edev(dmcfreq->edev); -+ if (ret < 0) { -+ dev_err(dev, "failed to disable the devfreq-event devices\n"); -+ return ret; -+ } -+ -+ ret = devfreq_suspend_device(dmcfreq->devfreq.devfreq); -+ if (ret < 0) { -+ dev_err(dev, "failed to suspend the devfreq devices\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static __maybe_unused int rk3328_dmcfreq_resume(struct device *dev) -+{ -+ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev); -+ int ret = 0; -+ -+ ret = devfreq_event_enable_edev(dmcfreq->edev); -+ if (ret < 0) { -+ dev_err(dev, "failed to enable the devfreq-event devices\n"); -+ return ret; -+ } -+ -+ ret = devfreq_resume_device(dmcfreq->devfreq.devfreq); -+ if (ret < 0) { -+ dev_err(dev, "failed to resume the devfreq devices\n"); -+ return ret; -+ } -+ return ret; -+} -+ -+static SIMPLE_DEV_PM_OPS(rk3328_dmcfreq_pm, rk3328_dmcfreq_suspend, -+ rk3328_dmcfreq_resume); -+ -+void rk3328_devfreq_fini(struct rk3328_dmcfreq *rdev) -+{ -+ struct rk3328_devfreq *devfreq = &rdev->devfreq; -+ -+ if (devfreq->cooling) { -+ devfreq_cooling_unregister(devfreq->cooling); -+ devfreq->cooling = NULL; -+ } -+ -+ if (devfreq->devfreq) { -+ devm_devfreq_remove_device(rdev->dev, devfreq->devfreq); -+ devfreq->devfreq = NULL; -+ } -+ -+} -+ -+int rk3328_devfreq_init(struct rk3328_dmcfreq *rdev) -+{ -+ struct thermal_cooling_device *cooling; -+ struct device *dev = rdev->dev; -+ struct devfreq *devfreq; -+ struct rk3328_devfreq *rdevfreq = &rdev->devfreq; -+ const char *regulator_names[] = { "center", NULL }; -+ -+ struct dev_pm_opp *opp; -+ unsigned long cur_freq; -+ int ret; -+ -+ if (!device_property_present(dev, "operating-points-v2")) -+ /* Optional, continue without devfreq */ -+ return 0; -+ -+ ret= devm_pm_opp_set_clkname(dev, "dmc_clk"); -+ if (ret) -+ goto err_fini; -+ -+ ret = devm_pm_opp_set_regulators(dev, regulator_names); -+ -+ if (ret) { -+ /* Continue if the optional regulator is missing */ -+ if (ret != -ENODEV) -+ goto err_fini; -+ } -+ -+ ret = devm_pm_opp_of_add_table(dev); -+ if (ret) -+ goto err_fini; -+ -+ cur_freq = 0; -+ -+ opp = devfreq_recommended_opp(dev, &cur_freq, 0); -+ if (IS_ERR(opp)) { -+ ret = PTR_ERR(opp); -+ goto err_fini; -+ } -+ -+ rk3328_devfreq_dmc_profile.initial_freq = cur_freq; -+ dev_pm_opp_put(opp); -+ -+ rdev->ondemand_data.upthreshold = 15; -+ rdev->ondemand_data.downdifferential = 5; -+ -+ devfreq = devm_devfreq_add_device(dev, &rk3328_devfreq_dmc_profile, -+ DEVFREQ_GOV_SIMPLE_ONDEMAND, &rdev->ondemand_data); -+ if (IS_ERR(devfreq)) { -+ dev_err(dev, "Couldn't initialize rk3328-dmc devfreq\n"); -+ ret = PTR_ERR(devfreq); -+ goto err_fini; -+ } -+ -+ rdevfreq->devfreq = devfreq; -+ -+ cooling = of_devfreq_cooling_register(dev->of_node, devfreq); -+ if (IS_ERR(cooling)) -+ dev_warn(dev, "Failed to register cooling device\n"); -+ else -+ rdevfreq->cooling = cooling; -+ -+ return 0; -+ -+err_fini: -+ rk3328_devfreq_fini(rdev); -+ return ret; -+} -+ -+static int rk3328_dmcfreq_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct rk3328_dmcfreq *data; -+ int ret; -+ -+ data = devm_kzalloc(dev, sizeof(struct rk3328_dmcfreq), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ -+ mutex_init(&data->lock); -+ -+ data->dev = dev; -+ -+ data->dmc_clk = devm_clk_get(dev, "dmc_clk"); -+ if (IS_ERR(data->dmc_clk)) { -+ if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER) -+ return -EPROBE_DEFER; -+ -+ dev_err(dev, "Cannot get the clk dmc_clk\n"); -+ return PTR_ERR(data->dmc_clk); -+ } -+ -+ data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0); -+ if (IS_ERR(data->edev)) -+ return -EPROBE_DEFER; -+ -+ ret = devfreq_event_enable_edev(data->edev); -+ if (ret < 0) { -+ dev_err(dev, "failed to enable devfreq-event devices\n"); -+ return ret; -+ } -+ -+ ret = rk3328_dmc_init(pdev, data); -+ if (ret) -+ return ret; -+ -+ ret = rk3328_devfreq_init(data); -+ if (ret) -+ return ret; -+ -+ platform_set_drvdata(pdev, data); -+ -+ return 0; -+ -+} -+ -+static void rk3328_dmcfreq_remove(struct platform_device *pdev) -+{ -+ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev); -+ -+ /* -+ * Before remove the opp table we need to unregister the opp notifier. -+ */ -+ rk3328_devfreq_fini(dmcfreq); -+ -+ return; -+} -+ -+static const struct of_device_id rk3328dmc_devfreq_of_match[] = { -+ { .compatible = "rockchip,rk3328-dmc" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, rk3328dmc_devfreq_of_match); -+ -+static struct platform_driver rk3328_dmcfreq_driver = { -+ .probe = rk3328_dmcfreq_probe, -+ .remove = rk3328_dmcfreq_remove, -+ .driver = { -+ .name = "rk3328-dmc", -+ .pm = &rk3328_dmcfreq_pm, -+ .of_match_table = rk3328dmc_devfreq_of_match, -+ }, -+}; -+module_platform_driver(rk3328_dmcfreq_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Lin Huang "); -+MODULE_DESCRIPTION("RK3328 dmcfreq driver with devfreq framework"); -diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/include/dt-bindings/clock/rockchip-ddr.h -@@ -0,0 +1,63 @@ -+/* -+ * -+ * Copyright (C) 2017 ROCKCHIP, Inc. -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ */ -+ -+#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H -+#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H -+ -+#define DDR2_DEFAULT (0) -+ -+#define DDR3_800D (0) /* 5-5-5 */ -+#define DDR3_800E (1) /* 6-6-6 */ -+#define DDR3_1066E (2) /* 6-6-6 */ -+#define DDR3_1066F (3) /* 7-7-7 */ -+#define DDR3_1066G (4) /* 8-8-8 */ -+#define DDR3_1333F (5) /* 7-7-7 */ -+#define DDR3_1333G (6) /* 8-8-8 */ -+#define DDR3_1333H (7) /* 9-9-9 */ -+#define DDR3_1333J (8) /* 10-10-10 */ -+#define DDR3_1600G (9) /* 8-8-8 */ -+#define DDR3_1600H (10) /* 9-9-9 */ -+#define DDR3_1600J (11) /* 10-10-10 */ -+#define DDR3_1600K (12) /* 11-11-11 */ -+#define DDR3_1866J (13) /* 10-10-10 */ -+#define DDR3_1866K (14) /* 11-11-11 */ -+#define DDR3_1866L (15) /* 12-12-12 */ -+#define DDR3_1866M (16) /* 13-13-13 */ -+#define DDR3_2133K (17) /* 11-11-11 */ -+#define DDR3_2133L (18) /* 12-12-12 */ -+#define DDR3_2133M (19) /* 13-13-13 */ -+#define DDR3_2133N (20) /* 14-14-14 */ -+#define DDR3_DEFAULT (21) -+#define DDR_DDR2 (22) -+#define DDR_LPDDR (23) -+#define DDR_LPDDR2 (24) -+ -+#define DDR4_1600J (0) /* 10-10-10 */ -+#define DDR4_1600K (1) /* 11-11-11 */ -+#define DDR4_1600L (2) /* 12-12-12 */ -+#define DDR4_1866L (3) /* 12-12-12 */ -+#define DDR4_1866M (4) /* 13-13-13 */ -+#define DDR4_1866N (5) /* 14-14-14 */ -+#define DDR4_2133N (6) /* 14-14-14 */ -+#define DDR4_2133P (7) /* 15-15-15 */ -+#define DDR4_2133R (8) /* 16-16-16 */ -+#define DDR4_2400P (9) /* 15-15-15 */ -+#define DDR4_2400R (10) /* 16-16-16 */ -+#define DDR4_2400U (11) /* 18-18-18 */ -+#define DDR4_DEFAULT (12) -+ -+#define PAUSE_CPU_STACK_SIZE 16 -+ -+#endif -diff --git a/include/dt-bindings/memory/rk3328-dram.h b/include/dt-bindings/memory/rk3328-dram.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/include/dt-bindings/memory/rk3328-dram.h -@@ -0,0 +1,159 @@ -+/* -+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H -+#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H -+ -+#define DDR3_DS_34ohm (34) -+#define DDR3_DS_40ohm (40) -+ -+#define DDR3_ODT_DIS (0) -+#define DDR3_ODT_40ohm (40) -+#define DDR3_ODT_60ohm (60) -+#define DDR3_ODT_120ohm (120) -+ -+#define LP2_DS_34ohm (34) -+#define LP2_DS_40ohm (40) -+#define LP2_DS_48ohm (48) -+#define LP2_DS_60ohm (60) -+#define LP2_DS_68_6ohm (68) /* optional */ -+#define LP2_DS_80ohm (80) -+#define LP2_DS_120ohm (120) /* optional */ -+ -+#define LP3_DS_34ohm (34) -+#define LP3_DS_40ohm (40) -+#define LP3_DS_48ohm (48) -+#define LP3_DS_60ohm (60) -+#define LP3_DS_80ohm (80) -+#define LP3_DS_34D_40U (3440) -+#define LP3_DS_40D_48U (4048) -+#define LP3_DS_34D_48U (3448) -+ -+#define LP3_ODT_DIS (0) -+#define LP3_ODT_60ohm (60) -+#define LP3_ODT_120ohm (120) -+#define LP3_ODT_240ohm (240) -+ -+#define LP4_PDDS_40ohm (40) -+#define LP4_PDDS_48ohm (48) -+#define LP4_PDDS_60ohm (60) -+#define LP4_PDDS_80ohm (80) -+#define LP4_PDDS_120ohm (120) -+#define LP4_PDDS_240ohm (240) -+ -+#define LP4_DQ_ODT_40ohm (40) -+#define LP4_DQ_ODT_48ohm (48) -+#define LP4_DQ_ODT_60ohm (60) -+#define LP4_DQ_ODT_80ohm (80) -+#define LP4_DQ_ODT_120ohm (120) -+#define LP4_DQ_ODT_240ohm (240) -+#define LP4_DQ_ODT_DIS (0) -+ -+#define LP4_CA_ODT_40ohm (40) -+#define LP4_CA_ODT_48ohm (48) -+#define LP4_CA_ODT_60ohm (60) -+#define LP4_CA_ODT_80ohm (80) -+#define LP4_CA_ODT_120ohm (120) -+#define LP4_CA_ODT_240ohm (240) -+#define LP4_CA_ODT_DIS (0) -+ -+#define DDR4_DS_34ohm (34) -+#define DDR4_DS_48ohm (48) -+#define DDR4_RTT_NOM_DIS (0) -+#define DDR4_RTT_NOM_60ohm (60) -+#define DDR4_RTT_NOM_120ohm (120) -+#define DDR4_RTT_NOM_40ohm (40) -+#define DDR4_RTT_NOM_240ohm (240) -+#define DDR4_RTT_NOM_48ohm (48) -+#define DDR4_RTT_NOM_80ohm (80) -+#define DDR4_RTT_NOM_34ohm (34) -+ -+#define PHY_DDR3_RON_RTT_DISABLE (0) -+#define PHY_DDR3_RON_RTT_451ohm (1) -+#define PHY_DDR3_RON_RTT_225ohm (2) -+#define PHY_DDR3_RON_RTT_150ohm (3) -+#define PHY_DDR3_RON_RTT_112ohm (4) -+#define PHY_DDR3_RON_RTT_90ohm (5) -+#define PHY_DDR3_RON_RTT_75ohm (6) -+#define PHY_DDR3_RON_RTT_64ohm (7) -+#define PHY_DDR3_RON_RTT_56ohm (16) -+#define PHY_DDR3_RON_RTT_50ohm (17) -+#define PHY_DDR3_RON_RTT_45ohm (18) -+#define PHY_DDR3_RON_RTT_41ohm (19) -+#define PHY_DDR3_RON_RTT_37ohm (20) -+#define PHY_DDR3_RON_RTT_34ohm (21) -+#define PHY_DDR3_RON_RTT_33ohm (22) -+#define PHY_DDR3_RON_RTT_30ohm (23) -+#define PHY_DDR3_RON_RTT_28ohm (24) -+#define PHY_DDR3_RON_RTT_26ohm (25) -+#define PHY_DDR3_RON_RTT_25ohm (26) -+#define PHY_DDR3_RON_RTT_23ohm (27) -+#define PHY_DDR3_RON_RTT_22ohm (28) -+#define PHY_DDR3_RON_RTT_21ohm (29) -+#define PHY_DDR3_RON_RTT_20ohm (30) -+#define PHY_DDR3_RON_RTT_19ohm (31) -+ -+#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) -+#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) -+#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) -+#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) -+#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) -+#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) -+#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) -+#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) -+#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) -+#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) -+#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) -+#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) -+#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) -+#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) -+#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) -+#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) -+#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) -+#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) -+#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) -+#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) -+#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) -+#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) -+#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) -+#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) -+ -+#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/ -diff --git a/include/soc/rockchip/rk3228_grf.h b/include/soc/rockchip/rk3228_grf.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/include/soc/rockchip/rk3228_grf.h -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Rockchip General Register Files definitions for RK3228 -+ * -+ * Author: Paolo Sabatino -+ */ -+ -+#ifndef __SOC_RK3228_GRF_H -+#define __SOC_RK3228_GRF_H -+ -+#define RK3228_GRF_OS_REG2 0x5d0 -+#define RK3228_GRF_OS_REG2_DDRTYPE GENMASK(15, 13) -+ -+#endif -diff --git a/include/soc/rockchip/rk3328_grf.h b/include/soc/rockchip/rk3328_grf.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/include/soc/rockchip/rk3328_grf.h -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Rockchip General Register Files definitions for RK3328 -+ * -+ * Author: Paolo Sabatino -+ */ -+ -+#ifndef __SOC_RK3328_GRF_H -+#define __SOC_RK3328_GRF_H -+ -+#define RK3328_GRF_OS_REG2 0x5d0 -+#define RK3328_GRF_OS_REG2_DDRTYPE GENMASK(15, 13) -+ -+#endif -diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h -index 111111111111..222222222222 100644 ---- a/include/soc/rockchip/rockchip_sip.h -+++ b/include/soc/rockchip/rockchip_sip.h -@@ -16,5 +16,16 @@ - #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 - #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 - #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08 -+#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08 -+ -+#define ROCKCHIP_SIP_SHARE_MEM 0x82000009 -+ -+/* Share mem page types */ -+typedef enum { -+ SHARE_PAGE_TYPE_INVALID = 0, -+ SHARE_PAGE_TYPE_UARTDBG, -+ SHARE_PAGE_TYPE_DDR, -+ SHARE_PAGE_TYPE_MAX, -+} share_page_type_t; - - #endif --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3328-add-rga-node.patch b/patch/kernel/rockchip64-6.14/rk3328-add-rga-node.patch deleted file mode 100644 index a1fc378..0000000 --- a/patch/kernel/rockchip64-6.14/rk3328-add-rga-node.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Thu, 21 Oct 2021 18:04:17 +0000 -Subject: rk3328: add RGA node - ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -817,6 +817,20 @@ vop_mmu: iommu@ff373f00 { - status = "disabled"; - }; - -+ rga: rga@ff390000 { -+ compatible = "rockchip,rk3328-rga", "rockchip,rk3399-rga"; -+ reg = <0x0 0xff390000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru ACLK_RGA>, -+ <&cru HCLK_RGA>, -+ <&cru SCLK_RGA>; -+ clock-names = "aclk", "hclk", "sclk"; -+ resets = <&cru SRST_RGA>, -+ <&cru SRST_RGA_A>, -+ <&cru SRST_RGA_H>; -+ reset-names = "core", "axi", "ahb"; -+ }; -+ - iep: iep@ff3a0000 { - compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep"; - reg = <0x0 0xff3a0000 0x0 0x800>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3328-dtsi-mali-opp-table.patch b/patch/kernel/rockchip64-6.14/rk3328-dtsi-mali-opp-table.patch deleted file mode 100644 index a1ae4cf..0000000 --- a/patch/kernel/rockchip64-6.14/rk3328-dtsi-mali-opp-table.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Sat, 25 Sep 2021 15:26:41 +0000 -Subject: gpu operating points - ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 ++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -713,6 +713,31 @@ gpu: gpu@ff300000 { - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - resets = <&cru SRST_GPU_A>; -+ operating-points-v2 = <&gpu_opp_table>; -+ }; -+ -+ gpu_opp_table: gpu-opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-200000000 { -+ opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <1050000 950000 1200000>; -+ }; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <1050000 950000 1200000>; -+ }; -+ -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <1050000 950000 1200000>; -+ }; -+ -+ opp-500000000 { -+ opp-hz = /bits/ 64 <500000000>; -+ opp-microvolt = <1150000 950000 1200000>; -+ }; - }; - - h265e_mmu: iommu@ff330200 { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3328-dtsi-spdif.patch b/patch/kernel/rockchip64-6.14/rk3328-dtsi-spdif.patch deleted file mode 100644 index 3549f0f..0000000 --- a/patch/kernel/rockchip64-6.14/rk3328-dtsi-spdif.patch +++ /dev/null @@ -1,128 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Sun, 26 Sep 2021 08:35:58 +0000 -Subject: [ARCHEOLOGY] rockchip64: tidy up rk3328 patches - -> X-Git-Archeology: > recovered message: > * remove 0-rever-rk3328.dtsi-.patch -> X-Git-Archeology: > recovered message: > * split rk3328-dtsi-mmc-vdec-usb3-tweaks.patch into different specific patches (sdmmc-ext, mmc-reset, power domains, usb3 resets) -> X-Git-Archeology: > recovered message: > * split rk3328-audio-and-renegade-supplies.patch into specific roc-cc audio and supplies patch and general rk3328 spdif patch -> X-Git-Archeology: > recovered message: > * add "dtsi" infix to rk3328 patches that deal with dtsi files -> X-Git-Archeology: > recovered message: > * add back mali gpu operating points patch -> X-Git-Archeology: - Revision a71ef23575940b363e86a143d6ec781f95f1dbde: https://github.com/armbian/build/commit/a71ef23575940b363e86a143d6ec781f95f1dbde -> X-Git-Archeology: Date: Sun, 26 Sep 2021 08:35:58 +0000 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip64: tidy up rk3328 patches -> X-Git-Archeology: -> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e -> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -224,6 +224,26 @@ psci { - method = "smc"; - }; - -+ spdif_out: spdif-out { -+ compatible = "linux,spdif-dit"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ spdif_sound: spdif-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "SPDIF"; -+ status = "disabled"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&spdif>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&spdif_out>; -+ }; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupts = , -@@ -331,6 +351,10 @@ power: power-controller { - #address-cells = <1>; - #size-cells = <0>; - -+ power-domain@RK3328_PD_GPU { -+ reg = ; -+ clocks = <&cru ACLK_GPU>; -+ }; - power-domain@RK3328_PD_HEVC { - reg = ; - clocks = <&cru SCLK_VENC_CORE>; -@@ -712,6 +736,7 @@ gpu: gpu@ff300000 { - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; -+ power-domains = <&power RK3328_PD_GPU>; - resets = <&cru SRST_GPU_A>; - operating-points-v2 = <&gpu_opp_table>; - }; -@@ -969,6 +994,7 @@ cru: clock-controller@ff440000 { - <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, - <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>, -+ <&cru ACLK_GPU>, - <&cru SCLK_RTC32K>; - assigned-clock-parents = - <&cru HDMIPHY>, <&cru PLL_APLL>, -@@ -990,6 +1016,7 @@ cru: clock-controller@ff440000 { - <150000000>, <75000000>, - <75000000>, <150000000>, - <75000000>, <75000000>, -+ <500000000>, - <32768>; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3328-dtsi-usb3-reset-properties.patch b/patch/kernel/rockchip64-6.14/rk3328-dtsi-usb3-reset-properties.patch deleted file mode 100644 index 1be6463..0000000 --- a/patch/kernel/rockchip64-6.14/rk3328-dtsi-usb3-reset-properties.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Sat, 25 Sep 2021 13:39:40 +0000 -Subject: usb3 reset properties - ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -1220,6 +1220,8 @@ usbdrd3: usb@ff600000 { - <&cru ACLK_USB3OTG>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; -+ resets = <&cru SRST_USB3OTG>; -+ reset-names = "usb3-otg"; - dr_mode = "otg"; - phy_type = "utmi_wide"; - snps,dis-del-phy-power-chg-quirk; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3328-gpu-cooling-target.patch b/patch/kernel/rockchip64-6.14/rk3328-gpu-cooling-target.patch deleted file mode 100644 index 2f3353f..0000000 --- a/patch/kernel/rockchip64-6.14/rk3328-gpu-cooling-target.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: tonymac32 -Date: Wed, 4 Aug 2021 00:14:33 -0400 -Subject: rk3328-gpu-cooling-target - -Signed-off-by: tonymac32 ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -594,6 +594,11 @@ map0 { - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; -+ map1 { -+ trip = <&target>; -+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ contribution = <4096>; -+ }; - }; - }; - -@@ -739,6 +744,7 @@ gpu: gpu@ff300000 { - power-domains = <&power RK3328_PD_GPU>; - resets = <&cru SRST_GPU_A>; - operating-points-v2 = <&gpu_opp_table>; -+ #cooling-cells = <2>; - }; - - gpu_opp_table: gpu-opp-table { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3328-roc-cc-add-missing-nodes.patch b/patch/kernel/rockchip64-6.14/rk3328-roc-cc-add-missing-nodes.patch deleted file mode 100644 index 068efbb..0000000 --- a/patch/kernel/rockchip64-6.14/rk3328-roc-cc-add-missing-nodes.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: tonymac32 -Date: Sat, 28 Jan 2023 17:07:35 -0500 -Subject: rk3328-roc-cc add missing nodes - -Signed-off-by: tonymac32 ---- - arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi | 32 ++++++++++ - 1 file changed, 32 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi -old mode 100644 -new mode 100755 -index 111111111111..222222222222 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi -@@ -128,6 +128,14 @@ user_led: led-1 { - default-state = "off"; - }; - }; -+ -+ ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&ir_int>; -+ pinctrl-names = "default"; -+ }; -+ - }; - - &analog_sound { -@@ -198,6 +206,10 @@ &gmac2io { - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_logic>; -+}; -+ - &hdmi { - status = "okay"; - }; -@@ -338,6 +350,13 @@ &io_domains { - }; - - &pinctrl { -+ -+ ir { -+ ir_int: ir-int { -+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -@@ -368,6 +387,19 @@ &sdmmc { - status = "okay"; - }; - -+&spdif { -+ pinctrl-0 = <&spdifm0_tx>; -+ status = "okay"; -+}; -+ -+&spdif_out { -+ status = "okay"; -+}; -+ -+&spdif_sound { -+ status = "okay"; -+}; -+ - &tsadc { - status = "okay"; - }; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3399-add-sclk-i2sout-src-clock.patch b/patch/kernel/rockchip64-6.14/rk3399-add-sclk-i2sout-src-clock.patch deleted file mode 100644 index 6d31e57..0000000 --- a/patch/kernel/rockchip64-6.14/rk3399-add-sclk-i2sout-src-clock.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Piotr Szczepanik -Date: Sun, 5 Apr 2020 18:15:06 +0200 -Subject: [ARCHEOLOGY] Fixed sound from rt5651 on OrangePi 4 (#1870) - -> X-Git-Archeology: - Revision e14a61c229db1216fedc397e351c4bed15df820e: https://github.com/armbian/build/commit/e14a61c229db1216fedc397e351c4bed15df820e -> X-Git-Archeology: Date: Sun, 05 Apr 2020 18:15:06 +0200 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Fixed sound from rt5651 on OrangePi 4 (#1870) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 -> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 -> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) -> X-Git-Archeology: -> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e -> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - drivers/clk/rockchip/clk-rk3399.c | 2 +- - include/dt-bindings/clock/rk3399-cru.h | 1 + - 2 files changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c -index 111111111111..222222222222 100644 ---- a/drivers/clk/rockchip/clk-rk3399.c -+++ b/drivers/clk/rockchip/clk-rk3399.c -@@ -659,7 +659,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { - GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, - RK3399_CLKGATE_CON(8), 11, GFLAGS), - -- MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, -+ MUX(SCLK_I2SOUT_SRC, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, - RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), - COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, - RK3399_CLKSEL_CON(31), 2, 1, MFLAGS, -diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h -index 111111111111..222222222222 100644 ---- a/include/dt-bindings/clock/rk3399-cru.h -+++ b/include/dt-bindings/clock/rk3399-cru.h -@@ -19,6 +19,7 @@ - #define ARMCLKB 9 - - /* sclk gates (special clocks) */ -+#define SCLK_I2SOUT_SRC 64 - #define SCLK_I2C1 65 - #define SCLK_I2C2 66 - #define SCLK_I2C3 67 --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3399-dmc-polling-rate.patch b/patch/kernel/rockchip64-6.14/rk3399-dmc-polling-rate.patch deleted file mode 100644 index 71f5a81..0000000 --- a/patch/kernel/rockchip64-6.14/rk3399-dmc-polling-rate.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Wed, 8 Mar 2023 11:12:41 +0100 -Subject: [ARCHEOLOGY] rockchip64: set poll rate 50ms for rk3399 dmc driver - -> X-Git-Archeology: - Revision 03a00c5ce49dadd0dd579980114b8595f144b763: https://github.com/armbian/build/commit/03a00c5ce49dadd0dd579980114b8595f144b763 -> X-Git-Archeology: Date: Wed, 08 Mar 2023 11:12:41 +0100 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip64: set poll rate 50ms for rk3399 dmc driver -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - drivers/devfreq/rk3399_dmc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c -index 111111111111..222222222222 100644 ---- a/drivers/devfreq/rk3399_dmc.c -+++ b/drivers/devfreq/rk3399_dmc.c -@@ -430,7 +430,7 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) - dev_pm_opp_put(opp); - - data->profile = (struct devfreq_dev_profile) { -- .polling_ms = 200, -+ .polling_ms = 50, - .target = rk3399_dmcfreq_target, - .get_dev_status = rk3399_dmcfreq_get_dev_status, - .get_cur_freq = rk3399_dmcfreq_get_cur_freq, --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/rockchip64-6.14/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch deleted file mode 100644 index 2316170..0000000 --- a/patch/kernel/rockchip64-6.14/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch +++ /dev/null @@ -1,119 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Aditya Prayoga -Date: Fri, 22 Jan 2021 13:12:09 +0100 -Subject: [ARCHEOLOGY] Fix 2.5G Ethernet on Helios64 Mainline kernel (#2567) - -> X-Git-Archeology: > recovered message: > * rockchip64: Added XHCI HCD USB TRB ENT quirk -> X-Git-Archeology: > recovered message: > On some xHCI controllers (e.g. Rockchip RK3399/RK3328/RK1808), they need -> X-Git-Archeology: > recovered message: > to enable the ENT flag in the TRB data structure to force xHC to -> X-Git-Archeology: > recovered message: > prefetch the next TRB of a TD. -> X-Git-Archeology: > recovered message: > Enable the quirk on RK3399 through device tree node properties. -> X-Git-Archeology: > recovered message: > Ported from Rockchip Linux 4.19 -> X-Git-Archeology: > recovered message: > * add to dev branch -> X-Git-Archeology: - Revision 568d8472b3c2ab406fd3897e6b952c7a71a8165b: https://github.com/armbian/build/commit/568d8472b3c2ab406fd3897e6b952c7a71a8165b -> X-Git-Archeology: Date: Fri, 22 Jan 2021 13:12:09 +0100 -> X-Git-Archeology: From: Aditya Prayoga -> X-Git-Archeology: Subject: Fix 2.5G Ethernet on Helios64 Mainline kernel (#2567) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 3b3d85e25c2ecde30df7b5274fc6f1b9c0299ea2: https://github.com/armbian/build/commit/3b3d85e25c2ecde30df7b5274fc6f1b9c0299ea2 -> X-Git-Archeology: Date: Sat, 22 May 2021 17:08:44 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Upgrade EDGE to 5.12.y (#2825) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 -> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 -> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) -> X-Git-Archeology: -> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e -> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4 -> X-Git-Archeology: Date: Tue, 11 Jan 2022 15:26:11 +0100 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: move kernel edge to 5.16 (#3387) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41 -> X-Git-Archeology: Date: Sun, 20 Mar 2022 22:58:21 +0100 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: Adding Pine64 Quartz64a as WIP target (#3539) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c -> X-Git-Archeology: Date: Sun, 24 Apr 2022 22:33:47 +0200 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: move kernel media edge to 5.17 (#3704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -@@ -558,6 +558,7 @@ usbdrd_dwc3_0: usb@fe800000 { - snps,dis_u2_susphy_quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; -+ snps,xhci-trb-ent-quirk; - power-domains = <&power RK3399_PD_USB3>; - status = "disabled"; - }; -@@ -594,6 +595,7 @@ usbdrd_dwc3_1: usb@fe900000 { - snps,dis_u2_susphy_quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; -+ snps,xhci-trb-ent-quirk; - power-domains = <&power RK3399_PD_USB3>; - status = "disabled"; - }; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3399-fix-pci-lanes.patch b/patch/kernel/rockchip64-6.14/rk3399-fix-pci-lanes.patch deleted file mode 100644 index 3226922..0000000 --- a/patch/kernel/rockchip64-6.14/rk3399-fix-pci-lanes.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Valmantas Paliksa -Date: Thu, 12 Dec 2024 12:24:33 +0200 -Subject: Disable PHY_LANE_IDLE_OFF for each instance of - rockchip_pcie_phy_power_one - -Previously PHY_LANE_IDLE_OFF was only disabled for the first lane ---- - drivers/phy/rockchip/phy-rockchip-pcie.c | 12 +++++----- - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c -index 111111111111..222222222222 100644 ---- a/drivers/phy/rockchip/phy-rockchip-pcie.c -+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c -@@ -160,6 +160,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) - - guard(mutex)(&rk_phy->pcie_mutex); - -+ regmap_write(rk_phy->reg_base, -+ rk_phy->phy_data->pcie_laneoff, -+ HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, -+ PHY_LANE_IDLE_MASK, -+ PHY_LANE_IDLE_A_SHIFT + inst->index)); -+ - if (rk_phy->pwr_cnt++) { - return 0; - } -@@ -176,12 +182,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) - PHY_CFG_ADDR_MASK, - PHY_CFG_ADDR_SHIFT)); - -- regmap_write(rk_phy->reg_base, -- rk_phy->phy_data->pcie_laneoff, -- HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, -- PHY_LANE_IDLE_MASK, -- PHY_LANE_IDLE_A_SHIFT + inst->index)); -- - /* - * No documented timeout value for phy operation below, - * so we make it large enough here. And we use loop-break --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3399-fix-pci-phy.patch b/patch/kernel/rockchip64-6.14/rk3399-fix-pci-phy.patch deleted file mode 100644 index f5c7d1c..0000000 --- a/patch/kernel/rockchip64-6.14/rk3399-fix-pci-phy.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrey Safonov -Date: Sat, 16 Dec 2023 22:46:35 +0300 -Subject: rk3399 PCIE PHY reset on probe - -Signed-off-by: Andrey Safonov ---- - drivers/phy/rockchip/phy-rockchip-pcie.c | 16 ++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c -index 111111111111..222222222222 100644 ---- a/drivers/phy/rockchip/phy-rockchip-pcie.c -+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c -@@ -293,6 +293,20 @@ static const struct of_device_id rockchip_pcie_phy_dt_ids[] = { - - MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids); - -+static void rockchip_pcie_phy_reset(struct rockchip_pcie_phy *rk_phy) -+{ -+ int i; -+ -+ for (i = 0; i < PHY_MAX_LANE_NUM; i++) -+ regmap_write(rk_phy->reg_base, -+ rk_phy->phy_data->pcie_laneoff, -+ HIWORD_UPDATE(PHY_LANE_IDLE_OFF, -+ PHY_LANE_IDLE_MASK, -+ PHY_LANE_IDLE_A_SHIFT + i)); -+ -+ reset_control_assert(rk_phy->phy_rst); -+} -+ - static int rockchip_pcie_phy_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -337,6 +351,8 @@ static int rockchip_pcie_phy_probe(struct platform_device *pdev) - phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM; - dev_dbg(dev, "phy number is %d\n", phy_num); - -+ rockchip_pcie_phy_reset(rk_phy); -+ - for (i = 0; i < phy_num; i++) { - rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops); - if (IS_ERR(rk_phy->phys[i].phy)) { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3399-fix-usb-phy.patch b/patch/kernel/rockchip64-6.14/rk3399-fix-usb-phy.patch deleted file mode 100644 index 1849e4f..0000000 --- a/patch/kernel/rockchip64-6.14/rk3399-fix-usb-phy.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Mon, 4 Sep 2023 14:55:50 +0200 -Subject: increase timeout for usb3 type C phy init - -rockchip64: increase timeout for usb3 type C phy init ---- - drivers/phy/rockchip/phy-rockchip-typec.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c -index 111111111111..222222222222 100644 ---- a/drivers/phy/rockchip/phy-rockchip-typec.c -+++ b/drivers/phy/rockchip/phy-rockchip-typec.c -@@ -904,7 +904,7 @@ static int rockchip_usb3_phy_power_on(struct phy *phy) - tcphy_cfg_usb3_to_usb2_only(tcphy, false); - goto unlock_ret; - } -- usleep_range(10, 20); -+ usleep_range(100, 200); - } - - if (tcphy->mode == MODE_DISCONNECT) --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch b/patch/kernel/rockchip64-6.14/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch deleted file mode 100644 index 92aed7a..0000000 --- a/patch/kernel/rockchip64-6.14/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Dan Pasanen -Date: Thu, 16 Dec 2021 05:17:33 -0500 -Subject: add pcie hack bus-scan-delay-ms - -* build: kernel: rockchip64-[current,edge]: add pcie bus scan delay patches -These are needed for cards like the LSI SAS2008 which needs a little -extra time to initialize or they'll cause a kernel panic. -References: -https://gitlab.manjaro.org/manjaro-arm/packages/core/linux/-/blob/master/0013-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch -https://gitlab.manjaro.org/manjaro-arm/packages/core/linux/-/blob/master/0022-arm64-dts-rockchip-Add-pcie-bus-scan-delay-to-rockpr.patch ---- - Documentation/admin-guide/kernel-parameters.txt | 8 +++ - drivers/pci/controller/pcie-rockchip-host.c | 25 ++++++++++ - drivers/pci/controller/pcie-rockchip.c | 6 +++ - drivers/pci/controller/pcie-rockchip.h | 2 + - 4 files changed, 41 insertions(+) - -diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt -index 111111111111..222222222222 100644 ---- a/Documentation/admin-guide/kernel-parameters.txt -+++ b/Documentation/admin-guide/kernel-parameters.txt -@@ -4877,6 +4877,14 @@ - nomsi Do not use MSI for native PCIe PME signaling (this makes - all PCIe root ports use INTx for all services). - -+ pcie_rockchip_host.bus_scan_delay= [PCIE] Delay in ms before -+ scanning PCIe bus in Rockchip PCIe host driver. Some PCIe -+ cards seem to need delays that can be several hundred ms. -+ If set to greater than or equal to 0 this parameter will -+ override delay that can be set in device tree. -+ Values less than 0 mean that this parameter is ignored. -+ default=-1 -+ - pcmv= [HW,PCMCIA] BadgePAD 4 - - pd_ignore_unused -diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c -index 111111111111..222222222222 100644 ---- a/drivers/pci/controller/pcie-rockchip-host.c -+++ b/drivers/pci/controller/pcie-rockchip-host.c -@@ -32,10 +32,14 @@ - #include - #include - #include -+#include - - #include "../pci.h" - #include "pcie-rockchip.h" - -+static int bus_scan_delay = -1; -+module_param_named(bus_scan_delay, bus_scan_delay, int, S_IRUGO); -+ - static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) - { - u32 status; -@@ -933,6 +937,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev) - struct device *dev = &pdev->dev; - struct pci_host_bridge *bridge; - int err; -+ u32 delay = 0; - - if (!dev->of_node) - return -ENODEV; -@@ -982,6 +987,26 @@ static int rockchip_pcie_probe(struct platform_device *pdev) - bridge->sysdata = rockchip; - bridge->ops = &rockchip_pcie_ops; - -+ /* Checking if bus scan delay was given from command line and prefer -+ * that over the value in device tree (which defaults to 0 if not set). -+ */ -+ if (bus_scan_delay >= 0) { -+ delay = bus_scan_delay; -+ dev_info(dev, "wait %u ms (from command-line) before bus scan\n", delay); -+ } else { -+ delay = rockchip->bus_scan_delay; -+ dev_info(dev, "wait %u ms (from device tree) before bus scan\n", delay); -+ } -+ /* Workaround for some devices crashing on pci_host_probe / pci_scan_root_bus_bridge -+ * calls: sleep a bit before bus scan. Call trace gets to rockchip_pcie_rd_conf when -+ * trying to read vendor id (pci_bus_generic_read_dev_vendor_id is in call stack) -+ * before panicing. I have no idea why this works or what causes the panic. I just -+ * found this hack by luck when trying to "make it break differently if possible". -+ */ -+ if (delay > 0) { -+ msleep(delay); -+ } -+ - err = rockchip_pcie_setup_irq(rockchip); - if (err) - goto err_remove_irq_domain; -diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c -index 111111111111..222222222222 100644 ---- a/drivers/pci/controller/pcie-rockchip.c -+++ b/drivers/pci/controller/pcie-rockchip.c -@@ -102,6 +102,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) - return dev_err_probe(dev, rockchip->num_clks, - "failed to get clocks\n"); - -+ err = of_property_read_u32(node, "bus-scan-delay-ms", &rockchip->bus_scan_delay); -+ if (err) { -+ dev_info(dev, "no bus scan delay, default to 0 ms\n"); -+ rockchip->bus_scan_delay = 0; -+ } -+ - return 0; - } - EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt); -diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h -index 111111111111..222222222222 100644 ---- a/drivers/pci/controller/pcie-rockchip.h -+++ b/drivers/pci/controller/pcie-rockchip.h -@@ -351,6 +351,8 @@ struct rockchip_pcie { - phys_addr_t msg_bus_addr; - bool is_rc; - struct resource *mem_res; -+ /* Bus scan delay is a workaround for some pcie devices causing crashes */ -+ u32 bus_scan_delay; - }; - - static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg) --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3399-sd-drive-level-8ma.patch b/patch/kernel/rockchip64-6.14/rk3399-sd-drive-level-8ma.patch deleted file mode 100644 index 4f2a66e..0000000 --- a/patch/kernel/rockchip64-6.14/rk3399-sd-drive-level-8ma.patch +++ /dev/null @@ -1,159 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Martin Ayotte -Date: Thu, 3 Jan 2019 11:04:17 -0500 -Subject: [ARCHEOLOGY] add better strength on SDCard and put back previous - speed setting - -> X-Git-Archeology: - Revision 211c802f7cfedaac75a35f65d427910011c29242: https://github.com/armbian/build/commit/211c802f7cfedaac75a35f65d427910011c29242 -> X-Git-Archeology: Date: Thu, 03 Jan 2019 11:04:17 -0500 -> X-Git-Archeology: From: Martin Ayotte -> X-Git-Archeology: Subject: add better strength on SDCard and put back previous speed setting -> X-Git-Archeology: -> X-Git-Archeology: - Revision f2e71dbc730eaf7f1e586dfd5951bc149cb827d2: https://github.com/armbian/build/commit/f2e71dbc730eaf7f1e586dfd5951bc149cb827d2 -> X-Git-Archeology: Date: Fri, 04 Jan 2019 10:04:19 -0500 -> X-Git-Archeology: From: Martin Ayotte -> X-Git-Archeology: Subject: fix sdmmc-bus1 pin -> X-Git-Archeology: -> X-Git-Archeology: - Revision 005e8cf9fcba2922685f5ee49cef833be1465ec1: https://github.com/armbian/build/commit/005e8cf9fcba2922685f5ee49cef833be1465ec1 -> X-Git-Archeology: Date: Sun, 27 Jan 2019 15:37:40 -0500 -> X-Git-Archeology: From: Martin Ayotte -> X-Git-Archeology: Subject: fxi SD-CD pullup -> X-Git-Archeology: -> X-Git-Archeology: - Revision 885111ab0e166f97338df63714ea47a5b554b698: https://github.com/armbian/build/commit/885111ab0e166f97338df63714ea47a5b554b698 -> X-Git-Archeology: Date: Sat, 13 Jul 2019 11:25:27 -0400 -> X-Git-Archeology: From: Martin Ayotte -> X-Git-Archeology: Subject: switch rockchip64-dev and rk3399-dev to 5.2.y -> X-Git-Archeology: -> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3 -> X-Git-Archeology: Date: Tue, 19 Nov 2019 23:25:39 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Remove K<4, change branches, new features (#1586) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5: https://github.com/armbian/build/commit/4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5 -> X-Git-Archeology: Date: Wed, 02 Sep 2020 23:22:09 +0200 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switched rockchip64 curent to kernel 5.8.y (#2175) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 -> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 -> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) -> X-Git-Archeology: -> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e -> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4 -> X-Git-Archeology: Date: Tue, 11 Jan 2022 15:26:11 +0100 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: move kernel edge to 5.16 (#3387) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41 -> X-Git-Archeology: Date: Sun, 20 Mar 2022 22:58:21 +0100 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: Adding Pine64 Quartz64a as WIP target (#3539) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c -> X-Git-Archeology: Date: Sun, 24 Apr 2022 22:33:47 +0200 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: move kernel media edge to 5.17 (#3704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 16 +++++----- - 1 file changed, 8 insertions(+), 8 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -@@ -2662,25 +2662,25 @@ sdio0_int: sdio0-int { - sdmmc { - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = -- <4 RK_PB0 1 &pcfg_pull_up>; -+ <4 RK_PB0 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = -- <4 RK_PB0 1 &pcfg_pull_up>, -- <4 RK_PB1 1 &pcfg_pull_up>, -- <4 RK_PB2 1 &pcfg_pull_up>, -- <4 RK_PB3 1 &pcfg_pull_up>; -+ <4 RK_PB0 1 &pcfg_pull_up_8ma>, -+ <4 RK_PB1 1 &pcfg_pull_up_8ma>, -+ <4 RK_PB2 1 &pcfg_pull_up_8ma>, -+ <4 RK_PB3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = -- <4 RK_PB4 1 &pcfg_pull_none>; -+ <4 RK_PB4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = -- <4 RK_PB5 1 &pcfg_pull_up>; -+ <4 RK_PB5 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_cd: sdmmc-cd { -@@ -2690,7 +2690,7 @@ sdmmc_cd: sdmmc-cd { - - sdmmc_wp: sdmmc-wp { - rockchip,pins = -- <0 RK_PB0 1 &pcfg_pull_up>; -+ <0 RK_PB0 1 &pcfg_pull_up_8ma>; - }; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3399-sd-pwr-pinctrl.patch b/patch/kernel/rockchip64-6.14/rk3399-sd-pwr-pinctrl.patch deleted file mode 100644 index 55a8f2d..0000000 --- a/patch/kernel/rockchip64-6.14/rk3399-sd-pwr-pinctrl.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Sun, 21 May 2023 13:14:26 +0200 -Subject: rk3399: add sd power pin to pinctrl node - ---- - arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -@@ -2657,6 +2657,11 @@ sdio0_int: sdio0-int { - rockchip,pins = - <0 RK_PA4 1 &pcfg_pull_up>; - }; -+ -+ sdmmc_pwr: sdmmc-pwr { -+ rockchip,pins = -+ <0 RK_PA1 1 &pcfg_pull_up>; -+ }; - }; - - sdmmc { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3399-unlock-temperature.patch b/patch/kernel/rockchip64-6.14/rk3399-unlock-temperature.patch deleted file mode 100644 index 989d2b7..0000000 --- a/patch/kernel/rockchip64-6.14/rk3399-unlock-temperature.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: ThomasKaiser -Date: Sat, 13 Oct 2018 16:35:07 +0200 -Subject: [ARCHEOLOGY] Increase performance with rk3399-dev - -> X-Git-Archeology: - Revision b28fa47aa8b9864ccae8b90ebb3d46ae55103d6e: https://github.com/armbian/build/commit/b28fa47aa8b9864ccae8b90ebb3d46ae55103d6e -> X-Git-Archeology: Date: Sat, 13 Oct 2018 16:35:07 +0200 -> X-Git-Archeology: From: ThomasKaiser -> X-Git-Archeology: Subject: Increase performance with rk3399-dev -> X-Git-Archeology: -> X-Git-Archeology: - Revision f18360d1ef5d6487392ff4079301bca97945e704: https://github.com/armbian/build/commit/f18360d1ef5d6487392ff4079301bca97945e704 -> X-Git-Archeology: Date: Wed, 24 Oct 2018 17:03:35 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: [rk3399-dev] Merging rk3399-DEV with rockchip64-DEV on sources, patches and config level. Leave family intact, add 1.5 OPP for RK3328, add upstream patch for rk3399-default -> X-Git-Archeology: -> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3 -> X-Git-Archeology: Date: Tue, 19 Nov 2019 23:25:39 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Remove K<4, change branches, new features (#1586) -> X-Git-Archeology: -> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070 -> X-Git-Archeology: Date: Sun, 13 Dec 2020 22:13:03 -0500 -> X-Git-Archeology: From: tonymac32 -> X-Git-Archeology: Subject: [ rockchip64 ] Clean up patchset -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 -> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 -> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) -> X-Git-Archeology: -> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e -> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4 -> X-Git-Archeology: Date: Tue, 11 Jan 2022 15:26:11 +0100 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: move kernel edge to 5.16 (#3387) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41 -> X-Git-Archeology: Date: Sun, 20 Mar 2022 22:58:21 +0100 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: Adding Pine64 Quartz64a as WIP target (#3539) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c -> X-Git-Archeology: Date: Sun, 24 Apr 2022 22:33:47 +0200 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: move kernel media edge to 5.17 (#3704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi -@@ -928,17 +928,17 @@ cpu_thermal: cpu-thermal { - - trips { - cpu_alert0: cpu_alert0 { -- temperature = <70000>; -+ temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_alert1: cpu_alert1 { -- temperature = <75000>; -+ temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu_crit { -- temperature = <95000>; -+ temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-0011-irqchip-fix-its-timeout-issue.patch.bak b/patch/kernel/rockchip64-6.14/rk3588-0011-irqchip-fix-its-timeout-issue.patch.bak deleted file mode 100644 index 2c6b3c3..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-0011-irqchip-fix-its-timeout-issue.patch.bak +++ /dev/null @@ -1,214 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Fri, 11 Aug 2023 17:56:00 +0300 -Subject: irqchip/irq-gic-v3-its: fix its timeout issue for rk35xx boards - ---- - drivers/irqchip/irq-gic-v3-its.c | 79 +++++++++- - 1 file changed, 72 insertions(+), 7 deletions(-) - -diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c -index 111111111111..222222222222 100644 ---- a/drivers/irqchip/irq-gic-v3-its.c -+++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -164,6 +164,7 @@ struct its_device { - struct its_node *its; - struct event_lpi_map event_map; - void *itt; -+ u32 itt_sz; - u32 nr_ites; - u32 device_id; - bool shared; -@@ -2180,6 +2181,9 @@ static void gic_reset_prop_table(void *va) - static struct page *its_allocate_prop_table(gfp_t gfp_flags) - { - struct page *prop_page; -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ gfp_flags |= GFP_DMA32; - - prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); - if (!prop_page) -@@ -2304,6 +2308,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, - u32 alloc_pages, psz; - struct page *page; - void *base; -+ gfp_t gfp_flags; - - psz = baser->psz; - alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); -@@ -2315,7 +2320,11 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, - order = get_order(GITS_BASER_PAGES_MAX * psz); - } - -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); -+ gfp_flags = GFP_KERNEL | __GFP_ZERO; -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ gfp_flags |= GFP_DMA32; -+ -+ page = alloc_pages_node(its->numa_node, gfp_flags, order); - if (!page) - return -ENOMEM; - -@@ -2365,6 +2374,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, - its_write_baser(its, baser, val); - tmp = baser->val; - -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || -+ of_machine_is_compatible("rockchip,rk3588")) { -+ if (tmp & GITS_BASER_SHAREABILITY_MASK) -+ tmp &= ~GITS_BASER_SHAREABILITY_MASK; -+ else -+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); -+ } -+ - if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { - /* - * Shareability didn't stick. Just use -@@ -2954,7 +2972,9 @@ static int its_alloc_collections(struct its_node *its) - static struct page *its_allocate_pending_table(gfp_t gfp_flags) - { - struct page *pend_page; -- -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ gfp_flags |= GFP_DMA32; - pend_page = alloc_pages(gfp_flags | __GFP_ZERO, - get_order(LPI_PENDBASE_SZ)); - if (!pend_page) -@@ -3113,6 +3133,11 @@ static void its_cpu_init_lpis(void) - if (!rdists_support_shareable()) - tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; - -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || -+ of_machine_is_compatible("rockchip,rk3588")) -+ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; -+ - if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { - if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { - /* -@@ -3140,6 +3165,11 @@ static void its_cpu_init_lpis(void) - if (!rdists_support_shareable()) - tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; - -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || -+ of_machine_is_compatible("rockchip,rk3588")) -+ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; -+ - if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { - /* - * The HW reports non-shareable, we must remove the -@@ -3303,7 +3333,11 @@ static bool its_alloc_table_entry(struct its_node *its, - - /* Allocate memory for 2nd level table */ - if (!table[idx]) { -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, -+ gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ gfp_flags |= GFP_DMA32; -+ page = alloc_pages_node(its->numa_node, gfp_flags, - get_order(baser->psz)); - if (!page) - return false; -@@ -3392,6 +3426,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, - int nr_lpis; - int nr_ites; - int sz; -+ gfp_t gfp_flags; - - if (!its_alloc_device_table(its, dev_id)) - return NULL; -@@ -3407,7 +3442,15 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, - nr_ites = max(2, nvecs); - sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); - sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; -- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); -+ gfp_flags = GFP_KERNEL; -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) { -+ gfp_flags |= GFP_DMA32; -+ itt = (void *)__get_free_pages(gfp_flags, get_order(sz)); -+ } else { -+ itt = kzalloc_node(sz, gfp_flags, its->numa_node); -+ } -+ - if (alloc_lpis) { - lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); - if (lpi_map) -@@ -3421,7 +3464,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, - - if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { - kfree(dev); -- kfree(itt); -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ free_pages((unsigned long)itt, get_order(sz)); -+ else -+ kfree(itt); -+ - bitmap_free(lpi_map); - kfree(col_map); - return NULL; -@@ -3431,6 +3480,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, - - dev->its = its; - dev->itt = itt; -+ dev->itt_sz = sz; - dev->nr_ites = nr_ites; - dev->event_map.lpi_map = lpi_map; - dev->event_map.col_map = col_map; -@@ -3458,7 +3508,13 @@ static void its_free_device(struct its_device *its_dev) - list_del(&its_dev->entry); - raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); - kfree(its_dev->event_map.col_map); -- kfree(its_dev->itt); -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz)); -+ else -+ kfree(its_dev->itt); -+ - kfree(its_dev); - } - -@@ -5099,6 +5155,7 @@ static int __init its_probe_one(struct its_node *its) - struct page *page; - u32 ctlr; - int err; -+ gfp_t gfp_flags; - - its_enable_quirks(its); - -@@ -5132,7 +5189,10 @@ static int __init its_probe_one(struct its_node *its) - } - } - -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, -+ gfp_flags = GFP_KERNEL | __GFP_ZERO; -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ gfp_flags |= GFP_DMA32; -+ page = alloc_pages_node(its->numa_node, gfp_flags, - get_order(ITS_CMD_QUEUE_SZ)); - if (!page) { - err = -ENOMEM; -@@ -5161,6 +5221,11 @@ static int __init its_probe_one(struct its_node *its) - if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) - tmp &= ~GITS_CBASER_SHAREABILITY_MASK; - -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || -+ of_machine_is_compatible("rockchip,rk3588")) -+ tmp &= ~GITS_CBASER_SHAREABILITY_MASK; -+ - if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { - if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { - /* --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-0025-add-missing-op-nodes.patch b/patch/kernel/rockchip64-6.14/rk3588-0025-add-missing-op-nodes.patch deleted file mode 100644 index 292e493..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-0025-add-missing-op-nodes.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: SuperKali -Date: Thu, 3 Apr 2025 05:59:12 +0000 -Subject: Rockchip RK3588 adding missing opp nodes - -Signed-off-by: SuperKali ---- - arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 58 ++++++++++ - 1 file changed, 58 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi -@@ -5,6 +5,22 @@ cluster0_opp_table: opp-table-cluster0 { - compatible = "operating-points-v2"; - opp-shared; - -+ opp-408000000 { -+ opp-hz = /bits/ 64 <408000000>; -+ opp-microvolt = <675000 675000 950000>; -+ clock-latency-ns = <40000>; -+ opp-suspend; -+ }; -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <675000 675000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-816000000 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <675000 675000 950000>; -+ clock-latency-ns = <40000>; -+ }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <675000 675000 950000>; -@@ -37,6 +53,27 @@ cluster1_opp_table: opp-table-cluster1 { - compatible = "operating-points-v2"; - opp-shared; - -+ opp-408000000 { -+ opp-hz = /bits/ 64 <408000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ opp-suspend; -+ }; -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-816000000 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1008000000 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <675000 675000 1000000>; -@@ -78,6 +115,27 @@ cluster2_opp_table: opp-table-cluster2 { - compatible = "operating-points-v2"; - opp-shared; - -+ opp-408000000 { -+ opp-hz = /bits/ 64 <408000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ opp-suspend; -+ }; -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-816000000 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1008000000 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <675000 675000 1000000>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-0113-add-synopsys-designware-hdmi-rx-controller.patch b/patch/kernel/rockchip64-6.14/rk3588-0113-add-synopsys-designware-hdmi-rx-controller.patch deleted file mode 100644 index 23f0415..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-0113-add-synopsys-designware-hdmi-rx-controller.patch +++ /dev/null @@ -1,4117 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Fri, 19 Jul 2024 18:10:30 +0530 -Subject: dt-bindings: media: Document bindings for HDMI RX Controller - -Document bindings for the Synopsys DesignWare HDMI RX Controller. - -Reviewed-by: Rob Herring -Reviewed-by: Dmitry Osipenko -Signed-off-by: Shreeya Patel -Reviewed-by: Sebastian Reichel -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20240719124032.26852-3-shreeya.patel@collabora.com -Signed-off-by: Sebastian Reichel ---- - Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml | 132 ++++++++++ - 1 file changed, 132 insertions(+) - -diff --git a/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml -@@ -0,0 +1,132 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+# Device Tree bindings for Synopsys DesignWare HDMI RX Controller -+ -+--- -+$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Synopsys DesignWare HDMI RX Controller -+ -+maintainers: -+ - Shreeya Patel -+ -+description: -+ Synopsys DesignWare HDMI Input Controller preset on RK3588 SoCs -+ allowing devices to receive and decode high-resolution video streams -+ from external sources like media players, cameras, laptops, etc. -+ -+properties: -+ compatible: -+ items: -+ - const: rockchip,rk3588-hdmirx-ctrler -+ - const: snps,dw-hdmi-rx -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 3 -+ -+ interrupt-names: -+ items: -+ - const: cec -+ - const: hdmi -+ - const: dma -+ -+ clocks: -+ maxItems: 7 -+ -+ clock-names: -+ items: -+ - const: aclk -+ - const: audio -+ - const: cr_para -+ - const: pclk -+ - const: ref -+ - const: hclk_s_hdmirx -+ - const: hclk_vo1 -+ -+ power-domains: -+ maxItems: 1 -+ -+ resets: -+ maxItems: 4 -+ -+ reset-names: -+ items: -+ - const: axi -+ - const: apb -+ - const: ref -+ - const: biu -+ -+ memory-region: -+ maxItems: 1 -+ -+ hpd-gpios: -+ description: GPIO specifier for HPD. -+ maxItems: 1 -+ -+ rockchip,grf: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: -+ The phandle of the syscon node for the general register file -+ containing HDMIRX PHY status bits. -+ -+ rockchip,vo1-grf: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: -+ The phandle of the syscon node for the Video Output GRF register -+ to enable EDID transfer through SDAIN and SCLIN. -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - interrupt-names -+ - clocks -+ - clock-names -+ - power-domains -+ - resets -+ - pinctrl-0 -+ - hpd-gpios -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ #include -+ #include -+ #include -+ hdmi_receiver: hdmi-receiver@fdee0000 { -+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; -+ reg = <0xfdee0000 0x6000>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "cec", "hdmi", "dma"; -+ clocks = <&cru ACLK_HDMIRX>, -+ <&cru CLK_HDMIRX_AUD>, -+ <&cru CLK_CR_PARA>, -+ <&cru PCLK_HDMIRX>, -+ <&cru CLK_HDMIRX_REF>, -+ <&cru PCLK_S_HDMIRX>, -+ <&cru HCLK_VO1>; -+ clock-names = "aclk", -+ "audio", -+ "cr_para", -+ "pclk", -+ "ref", -+ "hclk_s_hdmirx", -+ "hclk_vo1"; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, -+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; -+ reset-names = "axi", "apb", "ref", "biu"; -+ memory-region = <&hdmi_receiver_cma>; -+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>; -+ pinctrl-names = "default"; -+ hpd-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; -+ }; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Fri, 19 Jul 2024 18:10:31 +0530 -Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller - -Add device tree support for Synopsys DesignWare HDMI RX -Controller. - -Reviewed-by: Dmitry Osipenko -Tested-by: Dmitry Osipenko -Co-developed-by: Dingxian Wen -Signed-off-by: Dingxian Wen -Signed-off-by: Shreeya Patel -Link: https://lore.kernel.org/r/20240719124032.26852-4-shreeya.patel@collabora.com -Signed-off-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi | 14 +++ - arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 56 ++++++++++ - 2 files changed, 70 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi -@@ -594,6 +594,20 @@ hdmim0_tx1_hpd: hdmim0-tx1-hpd { - /* hdmim0_tx1_hpd */ - <1 RK_PA6 5 &pcfg_pull_none>; - }; -+ -+ /omit-if-no-ref/ -+ hdmim1_rx: hdmim1-rx { -+ rockchip,pins = -+ /* hdmim1_rx_cec */ -+ <3 RK_PD1 5 &pcfg_pull_none>, -+ /* hdmim1_rx_scl */ -+ <3 RK_PD2 5 &pcfg_pull_none_smt>, -+ /* hdmim1_rx_sda */ -+ <3 RK_PD3 5 &pcfg_pull_none_smt>, -+ /* hdmim1_rx_hpdin */ -+ <3 RK_PD4 5 &pcfg_pull_none>; -+ }; -+ - /omit-if-no-ref/ - hdmim1_rx_cec: hdmim1-rx-cec { - rockchip,pins = -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -7,6 +7,29 @@ - #include "rk3588-extra-pinctrl.dtsi" - - / { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* -+ * The 4k HDMI capture controller works only with 32bit -+ * phys addresses and doesn't support IOMMU. HDMI RX CMA -+ * must be reserved below 4GB. -+ * The size of 160MB was determined as follows: -+ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB -+ * To ensure sufficient support for practical use-cases, -+ * we doubled the 66MB value. -+ */ -+ hdmi_receiver_cma: hdmi-receiver-cma { -+ compatible = "shared-dma-pool"; -+ alloc-ranges = <0x0 0x0 0x0 0xffffffff>; -+ size = <0x0 (160 * 0x100000)>; /* 160MiB */ -+ no-map; -+ status = "disabled"; -+ }; -+ }; -+ - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; -@@ -135,6 +158,39 @@ i2s10_8ch: i2s@fde00000 { - status = "disabled"; - }; - -+ hdmi_receiver: hdmi_receiver@fdee0000 { -+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; -+ reg = <0x0 0xfdee0000 0x0 0x6000>; -+ power-domains = <&power RK3588_PD_VO1>; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vo1-grf = <&vo1_grf>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "cec", "hdmi", "dma"; -+ clocks = <&cru ACLK_HDMIRX>, -+ <&cru CLK_HDMIRX_AUD>, -+ <&cru CLK_CR_PARA>, -+ <&cru PCLK_HDMIRX>, -+ <&cru CLK_HDMIRX_REF>, -+ <&cru PCLK_S_HDMIRX>, -+ <&cru HCLK_VO1>; -+ clock-names = "aclk", -+ "audio", -+ "cr_para", -+ "pclk", -+ "ref", -+ "hclk_s_hdmirx", -+ "hclk_vo1"; -+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, -+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; -+ reset-names = "axi", "apb", "ref", "biu"; -+ memory-region = <&hdmi_receiver_cma>; -+ pinctrl-0 = <&hdmim1_rx>; -+ pinctrl-names = "default"; -+ status = "disabled"; -+ }; -+ - pcie3x4: pcie@fe150000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Fri, 19 Jul 2024 18:10:32 +0530 -Subject: media: platform: synopsys: Add support for hdmi input driver - -Add initial support for the Synopsys DesignWare HDMI RX -Controller Driver used by Rockchip RK3588. The driver -supports: - - HDMI 1.4b and 2.0 modes (HDMI 4k@60Hz) - - RGB888, YUV422, YUV444 and YCC420 pixel formats - - CEC - - EDID configuration - -The hardware also has Audio and HDCP capabilities, but these are -not yet supported by the driver. - -Reviewed-by: Dmitry Osipenko -Tested-by: Dmitry Osipenko -Co-developed-by: Dingxian Wen -Signed-off-by: Dingxian Wen -Signed-off-by: Shreeya Patel -Link: https://lore.kernel.org/r/20240719124032.26852-5-shreeya.patel@collabora.com -Signed-off-by: Sebastian Reichel ---- - drivers/media/platform/Kconfig | 1 + - drivers/media/platform/Makefile | 1 + - drivers/media/platform/synopsys/Kconfig | 3 + - drivers/media/platform/synopsys/Makefile | 2 + - drivers/media/platform/synopsys/hdmirx/Kconfig | 27 + - drivers/media/platform/synopsys/hdmirx/Makefile | 4 + - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 2763 ++++++++++ - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h | 394 ++ - drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c | 285 + - drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h | 44 + - 10 files changed, 3524 insertions(+) - -diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/Kconfig -+++ b/drivers/media/platform/Kconfig -@@ -85,6 +85,7 @@ source "drivers/media/platform/rockchip/Kconfig" - source "drivers/media/platform/samsung/Kconfig" - source "drivers/media/platform/st/Kconfig" - source "drivers/media/platform/sunxi/Kconfig" -+source "drivers/media/platform/synopsys/Kconfig" - source "drivers/media/platform/ti/Kconfig" - source "drivers/media/platform/verisilicon/Kconfig" - source "drivers/media/platform/via/Kconfig" -diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/Makefile -+++ b/drivers/media/platform/Makefile -@@ -28,6 +28,7 @@ obj-y += rockchip/ - obj-y += samsung/ - obj-y += st/ - obj-y += sunxi/ -+obj-y += synopsys/ - obj-y += ti/ - obj-y += verisilicon/ - obj-y += via/ -diff --git a/drivers/media/platform/synopsys/Kconfig b/drivers/media/platform/synopsys/Kconfig -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/Kconfig -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+source "drivers/media/platform/synopsys/hdmirx/Kconfig" -diff --git a/drivers/media/platform/synopsys/Makefile b/drivers/media/platform/synopsys/Makefile -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+obj-y += hdmirx/ -diff --git a/drivers/media/platform/synopsys/hdmirx/Kconfig b/drivers/media/platform/synopsys/hdmirx/Kconfig -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/Kconfig -@@ -0,0 +1,27 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+config VIDEO_SYNOPSYS_HDMIRX -+ tristate "Synopsys DesignWare HDMI Receiver driver" -+ depends on VIDEO_DEV -+ depends on ARCH_ROCKCHIP -+ select MEDIA_CONTROLLER -+ select VIDEO_V4L2_SUBDEV_API -+ select VIDEOBUF2_DMA_CONTIG -+ select CEC_CORE -+ select CEC_NOTIFIER -+ select HDMI -+ help -+ Support for Synopsys HDMI HDMI RX Controller. -+ This driver supports HDMI 2.0 version. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called synopsys_hdmirx. -+ -+config HDMIRX_LOAD_DEFAULT_EDID -+ bool "Load default EDID" -+ depends on VIDEO_SYNOPSYS_HDMIRX -+ default "y" -+ help -+ Preload the default EDID (Extended Display Identification Data). -+ EDID contains information about the capabilities of the display, -+ such as supported resolutions, refresh rates, and audio formats. -diff --git a/drivers/media/platform/synopsys/hdmirx/Makefile b/drivers/media/platform/synopsys/hdmirx/Makefile -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0 -+synopsys-hdmirx-objs := snps_hdmirx.o snps_hdmirx_cec.o -+ -+obj-$(CONFIG_VIDEO_SYNOPSYS_HDMIRX) += synopsys-hdmirx.o -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -@@ -0,0 +1,2763 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2024 Collabora, Ltd. -+ * Author: Shreeya Patel -+ * -+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. -+ * Author: Dingxian Wen -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "snps_hdmirx.h" -+#include "snps_hdmirx_cec.h" -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "debug level (0-3)"); -+ -+#define EDID_NUM_BLOCKS_MAX 2 -+#define EDID_BLOCK_SIZE 128 -+#define HDMIRX_STORED_BIT_WIDTH 8 -+#define IREF_CLK_FREQ_HZ 428571429 -+#define MEMORY_ALIGN_ROUND_UP_BYTES 64 -+#define HDMIRX_PLANE_Y 0 -+#define HDMIRX_PLANE_CBCR 1 -+#define RK_IRQ_HDMIRX_HDMI 210 -+#define FILTER_FRAME_CNT 6 -+#define RK_SIP_FIQ_CTRL 0x82000024 -+#define SIP_WDT_CFG 0x82000026 -+#define DETECTION_THRESHOLD 7 -+ -+/* fiq control sub func */ -+enum { -+ RK_SIP_FIQ_CTRL_FIQ_EN = 1, -+ RK_SIP_FIQ_CTRL_FIQ_DIS, -+ RK_SIP_FIQ_CTRL_SET_AFF -+}; -+ -+/* SIP_WDT_CONFIG call types */ -+enum { -+ WDT_START = 0, -+ WDT_STOP = 1, -+ WDT_PING = 2, -+}; -+ -+enum hdmirx_pix_fmt { -+ HDMIRX_RGB888 = 0, -+ HDMIRX_YUV422 = 1, -+ HDMIRX_YUV444 = 2, -+ HDMIRX_YUV420 = 3, -+}; -+ -+enum ddr_store_fmt { -+ STORE_RGB888 = 0, -+ STORE_RGBA_ARGB, -+ STORE_YUV420_8BIT, -+ STORE_YUV420_10BIT, -+ STORE_YUV422_8BIT, -+ STORE_YUV422_10BIT, -+ STORE_YUV444_8BIT, -+ STORE_YUV420_16BIT = 8, -+ STORE_YUV422_16BIT = 9, -+}; -+ -+enum hdmirx_reg_attr { -+ HDMIRX_ATTR_RW = 0, -+ HDMIRX_ATTR_RO = 1, -+ HDMIRX_ATTR_WO = 2, -+ HDMIRX_ATTR_RE = 3, -+}; -+ -+enum { -+ HDMIRX_RST_A, -+ HDMIRX_RST_P, -+ HDMIRX_RST_REF, -+ HDMIRX_RST_BIU, -+ HDMIRX_NUM_RST, -+}; -+ -+static const char * const pix_fmt_str[] = { -+ "RGB888", -+ "YUV422", -+ "YUV444", -+ "YUV420", -+}; -+ -+struct hdmirx_buffer { -+ struct vb2_v4l2_buffer vb; -+ struct list_head queue; -+ u32 buff_addr[VIDEO_MAX_PLANES]; -+}; -+ -+struct hdmirx_stream { -+ struct snps_hdmirx_dev *hdmirx_dev; -+ struct video_device vdev; -+ struct vb2_queue buf_queue; -+ struct list_head buf_head; -+ struct hdmirx_buffer *curr_buf; -+ struct hdmirx_buffer *next_buf; -+ struct v4l2_pix_format_mplane pixm; -+ const struct v4l2_format_info *out_finfo; -+ struct mutex vlock; /* to lock resources associated with video buffer and video device */ -+ spinlock_t vbq_lock; /* to lock video buffer queue */ -+ bool stopping; -+ wait_queue_head_t wq_stopped; -+ u32 frame_idx; -+ u32 line_flag_int_cnt; -+ u32 irq_stat; -+}; -+ -+struct snps_hdmirx_dev { -+ struct device *dev; -+ struct device *codec_dev; -+ struct hdmirx_stream stream; -+ struct v4l2_device v4l2_dev; -+ struct v4l2_ctrl_handler hdl; -+ struct v4l2_ctrl *detect_tx_5v_ctrl; -+ struct v4l2_ctrl *rgb_range; -+ struct v4l2_dv_timings timings; -+ struct gpio_desc *detect_5v_gpio; -+ struct work_struct work_wdt_config; -+ struct delayed_work delayed_work_hotplug; -+ struct delayed_work delayed_work_res_change; -+ struct delayed_work delayed_work_heartbeat; -+ struct cec_notifier *cec_notifier; -+ struct hdmirx_cec *cec; -+ struct mutex stream_lock; /* to lock video stream capture */ -+ struct mutex work_lock; /* to lock the critical section of hotplug event */ -+ struct reset_control_bulk_data resets[HDMIRX_NUM_RST]; -+ struct clk_bulk_data *clks; -+ struct regmap *grf; -+ struct regmap *vo1_grf; -+ struct completion cr_write_done; -+ struct completion timer_base_lock; -+ struct completion avi_pkt_rcv; -+ enum hdmirx_pix_fmt pix_fmt; -+ void __iomem *regs; -+ int hdmi_irq; -+ int dma_irq; -+ int det_irq; -+ bool hpd_trigger_level; -+ bool tmds_clk_ratio; -+ bool is_dvi_mode; -+ bool got_timing; -+ u32 num_clks; -+ u32 edid_blocks_written; -+ u32 cur_vic; -+ u32 cur_fmt_fourcc; -+ u32 color_depth; -+ u8 edid[EDID_BLOCK_SIZE * 2]; -+ hdmi_codec_plugged_cb plugged_cb; -+ spinlock_t rst_lock; /* to lock register access */ -+}; -+ -+static u8 edid_init_data_340M[] = { -+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00, -+ 0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78, -+ 0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23, -+ 0x09, 0x48, 0x4C, 0x21, 0x08, 0x00, 0x61, 0x40, -+ 0x01, 0x01, 0x81, 0x00, 0x95, 0x00, 0xA9, 0xC0, -+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A, -+ 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C, -+ 0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E, -+ 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, -+ 0x6E, 0x28, 0x55, 0x00, 0x20, 0xC2, 0x31, 0x00, -+ 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52, -+ 0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20, -+ 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD, -+ 0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A, -+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xA7, -+ -+ 0x02, 0x03, 0x2F, 0xD1, 0x51, 0x07, 0x16, 0x14, -+ 0x05, 0x01, 0x03, 0x12, 0x13, 0x84, 0x22, 0x1F, -+ 0x90, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x23, 0x09, -+ 0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03, -+ 0x0C, 0x00, 0x30, 0x00, 0x10, 0x44, 0xE3, 0x05, -+ 0x03, 0x01, 0xE4, 0x0F, 0x00, 0x80, 0x01, 0x02, -+ 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, -+ 0x2C, 0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, -+ 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, -+}; -+ -+static const struct v4l2_dv_timings cea640x480 = V4L2_DV_BT_CEA_640X480P59_94; -+ -+static const struct v4l2_dv_timings_cap hdmirx_timings_cap = { -+ .type = V4L2_DV_BT_656_1120, -+ .reserved = { 0 }, -+ V4L2_INIT_BT_TIMINGS(640, 4096, /* min/max width */ -+ 480, 2160, /* min/max height */ -+ 20000000, 600000000, /* min/max pixelclock */ -+ /* standards */ -+ V4L2_DV_BT_STD_CEA861, -+ /* capabilities */ -+ V4L2_DV_BT_CAP_PROGRESSIVE | -+ V4L2_DV_BT_CAP_INTERLACED) -+}; -+ -+static void hdmirx_writel(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val) -+{ -+ unsigned long lock_flags = 0; -+ -+ spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags); -+ writel(val, hdmirx_dev->regs + reg); -+ spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags); -+} -+ -+static u32 hdmirx_readl(struct snps_hdmirx_dev *hdmirx_dev, int reg) -+{ -+ unsigned long lock_flags = 0; -+ u32 val; -+ -+ spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags); -+ val = readl(hdmirx_dev->regs + reg); -+ spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags); -+ return val; -+} -+ -+static void hdmirx_reset_dma(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ unsigned long lock_flags = 0; -+ -+ spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags); -+ reset_control_reset(hdmirx_dev->resets[0].rstc); -+ spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags); -+} -+ -+static void hdmirx_update_bits(struct snps_hdmirx_dev *hdmirx_dev, int reg, -+ u32 mask, u32 data) -+{ -+ unsigned long lock_flags = 0; -+ u32 val; -+ -+ spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags); -+ val = readl(hdmirx_dev->regs + reg) & ~mask; -+ val |= (data & mask); -+ writel(val, hdmirx_dev->regs + reg); -+ spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags); -+} -+ -+static int hdmirx_subscribe_event(struct v4l2_fh *fh, -+ const struct v4l2_event_subscription *sub) -+{ -+ switch (sub->type) { -+ case V4L2_EVENT_SOURCE_CHANGE: -+ if (fh->vdev->vfl_dir == VFL_DIR_RX) -+ return v4l2_src_change_event_subscribe(fh, sub); -+ break; -+ case V4L2_EVENT_CTRL: -+ return v4l2_ctrl_subscribe_event(fh, sub); -+ default: -+ break; -+ } -+ -+ return -EINVAL; -+} -+ -+static bool tx_5v_power_present(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ bool ret; -+ int val, i, cnt; -+ -+ cnt = 0; -+ for (i = 0; i < 10; i++) { -+ usleep_range(1000, 1100); -+ val = gpiod_get_value(hdmirx_dev->detect_5v_gpio); -+ if (val > 0) -+ cnt++; -+ if (cnt >= DETECTION_THRESHOLD) -+ break; -+ } -+ -+ ret = (cnt >= DETECTION_THRESHOLD) ? true : false; -+ v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: %d\n", __func__, ret); -+ -+ return ret; -+} -+ -+static bool signal_not_lock(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ u32 mu_status, dma_st10, cmu_st; -+ -+ mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS); -+ dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10); -+ cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS); -+ -+ if ((mu_status & TMDSVALID_STABLE_ST) && -+ (dma_st10 & HDMIRX_LOCK) && -+ (cmu_st & TMDSQPCLK_LOCKED_ST)) -+ return false; -+ -+ return true; -+} -+ -+static void hdmirx_get_colordepth(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 val, color_depth_reg; -+ -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS11); -+ color_depth_reg = (val & HDMIRX_COLOR_DEPTH_MASK) >> 3; -+ -+ switch (color_depth_reg) { -+ case 0x4: -+ hdmirx_dev->color_depth = 24; -+ break; -+ case 0x5: -+ hdmirx_dev->color_depth = 30; -+ break; -+ case 0x6: -+ hdmirx_dev->color_depth = 36; -+ break; -+ case 0x7: -+ hdmirx_dev->color_depth = 48; -+ break; -+ default: -+ hdmirx_dev->color_depth = 24; -+ break; -+ } -+ -+ v4l2_dbg(1, debug, v4l2_dev, "%s: color_depth: %d, reg_val:%d\n", -+ __func__, hdmirx_dev->color_depth, color_depth_reg); -+} -+ -+static void hdmirx_get_pix_fmt(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 val; -+ -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS11); -+ hdmirx_dev->pix_fmt = val & HDMIRX_FORMAT_MASK; -+ -+ switch (hdmirx_dev->pix_fmt) { -+ case HDMIRX_RGB888: -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24; -+ break; -+ case HDMIRX_YUV422: -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV16; -+ break; -+ case HDMIRX_YUV444: -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV24; -+ break; -+ case HDMIRX_YUV420: -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV12; -+ break; -+ default: -+ v4l2_err(v4l2_dev, -+ "%s: err pix_fmt: %d, set RGB888 as default\n", -+ __func__, hdmirx_dev->pix_fmt); -+ hdmirx_dev->pix_fmt = HDMIRX_RGB888; -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24; -+ break; -+ } -+ -+ v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s\n", __func__, -+ pix_fmt_str[hdmirx_dev->pix_fmt]); -+} -+ -+static void hdmirx_get_timings(struct snps_hdmirx_dev *hdmirx_dev, -+ struct v4l2_bt_timings *bt, bool from_dma) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 hact, vact, htotal, vtotal, fps; -+ u32 hfp, hs, hbp, vfp, vs, vbp; -+ u32 val; -+ -+ if (from_dma) { -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS2); -+ hact = (val >> 16) & 0xffff; -+ vact = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS3); -+ htotal = (val >> 16) & 0xffff; -+ vtotal = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS4); -+ hs = (val >> 16) & 0xffff; -+ vs = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS5); -+ hbp = (val >> 16) & 0xffff; -+ vbp = val & 0xffff; -+ hfp = htotal - hact - hs - hbp; -+ vfp = vtotal - vact - vs - vbp; -+ } else { -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS1); -+ hs = (val >> 16) & 0xffff; -+ hfp = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS2); -+ hbp = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS3); -+ htotal = (val >> 16) & 0xffff; -+ hact = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS4); -+ vs = (val >> 16) & 0xffff; -+ vfp = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS5); -+ vbp = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS6); -+ vtotal = (val >> 16) & 0xffff; -+ vact = val & 0xffff; -+ if (hdmirx_dev->pix_fmt == HDMIRX_YUV420) -+ hact *= 2; -+ } -+ if (hdmirx_dev->pix_fmt == HDMIRX_YUV420) -+ htotal *= 2; -+ fps = (bt->pixelclock + (htotal * vtotal) / 2) / (htotal * vtotal); -+ if (hdmirx_dev->pix_fmt == HDMIRX_YUV420) -+ fps *= 2; -+ bt->width = hact; -+ bt->height = vact; -+ bt->hfrontporch = hfp; -+ bt->hsync = hs; -+ bt->hbackporch = hbp; -+ bt->vfrontporch = vfp; -+ bt->vsync = vs; -+ bt->vbackporch = vbp; -+ -+ v4l2_dbg(1, debug, v4l2_dev, "get timings from %s\n", from_dma ? "dma" : "ctrl"); -+ v4l2_dbg(1, debug, v4l2_dev, "act:%ux%u, total:%ux%u, fps:%u, pixclk:%llu\n", -+ bt->width, bt->height, htotal, vtotal, fps, bt->pixelclock); -+ -+ v4l2_dbg(2, debug, v4l2_dev, "hfp:%u, hs:%u, hbp:%u, vfp:%u, vs:%u, vbp:%u\n", -+ bt->hfrontporch, bt->hsync, bt->hbackporch, -+ bt->vfrontporch, bt->vsync, bt->vbackporch); -+} -+ -+static bool hdmirx_check_timing_valid(struct v4l2_bt_timings *bt) -+{ -+ if (bt->width < 100 || bt->width > 5000 || -+ bt->height < 100 || bt->height > 5000) -+ return false; -+ -+ if (!bt->hsync || bt->hsync > 200 || -+ !bt->vsync || bt->vsync > 100) -+ return false; -+ -+ if (!bt->hbackporch || bt->hbackporch > 2000 || -+ !bt->vbackporch || bt->vbackporch > 2000) -+ return false; -+ -+ if (!bt->hfrontporch || bt->hfrontporch > 2000 || -+ !bt->vfrontporch || bt->vfrontporch > 2000) -+ return false; -+ -+ return true; -+} -+ -+static void hdmirx_get_avi_infoframe(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ union hdmi_infoframe frame = {}; -+ int err, i, b, itr = 0; -+ u8 aviif[3 + 7 * 4]; -+ u32 val; -+ -+ aviif[itr++] = HDMI_INFOFRAME_TYPE_AVI; -+ val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1); -+ aviif[itr++] = val & 0xff; -+ aviif[itr++] = (val >> 8) & 0xff; -+ -+ for (i = 0; i < 7; i++) { -+ val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB3_0 + 4 * i); -+ -+ for (b = 0; b < 4; b++) -+ aviif[itr++] = (val >> (8 * b)) & 0xff; -+ } -+ -+ err = hdmi_infoframe_unpack(&frame, aviif, sizeof(aviif)); -+ if (err) { -+ v4l2_err(v4l2_dev, "failed to unpack AVI infoframe\n"); -+ return; -+ } -+ -+ v4l2_ctrl_s_ctrl(hdmirx_dev->rgb_range, frame.avi.quantization_range); -+} -+ -+/* -+ * When querying DV timings during preview, if the DMA's timing is stable, -+ * we retrieve the timings directly from the DMA. However, if the current -+ * resolution is negative, obtaining the timing from CTRL may require a -+ * change in the sync polarity, potentially leading to DMA errors. -+ */ -+static int hdmirx_get_detected_timings(struct snps_hdmirx_dev *hdmirx_dev, -+ struct v4l2_dv_timings *timings, -+ bool from_dma) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct v4l2_bt_timings *bt = &timings->bt; -+ u32 field_type, color_depth, deframer_st; -+ u32 val, tmdsqpclk_freq, pix_clk; -+ u64 tmp_data, tmds_clk; -+ -+ memset(timings, 0, sizeof(struct v4l2_dv_timings)); -+ timings->type = V4L2_DV_BT_656_1120; -+ -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS11); -+ field_type = (val & HDMIRX_TYPE_MASK) >> 7; -+ hdmirx_get_pix_fmt(hdmirx_dev); -+ bt->interlaced = field_type & BIT(0) ? V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; -+ val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB7_4); -+ hdmirx_dev->cur_vic = val | VIC_VAL_MASK; -+ hdmirx_get_colordepth(hdmirx_dev); -+ color_depth = hdmirx_dev->color_depth; -+ deframer_st = hdmirx_readl(hdmirx_dev, DEFRAMER_STATUS); -+ hdmirx_dev->is_dvi_mode = deframer_st & OPMODE_STS_MASK ? false : true; -+ tmdsqpclk_freq = hdmirx_readl(hdmirx_dev, CMU_TMDSQPCLK_FREQ); -+ tmds_clk = tmdsqpclk_freq * 4 * 1000; -+ tmp_data = tmds_clk * 24; -+ do_div(tmp_data, color_depth); -+ pix_clk = tmp_data; -+ bt->pixelclock = pix_clk; -+ -+ hdmirx_get_avi_infoframe(hdmirx_dev); -+ -+ hdmirx_get_timings(hdmirx_dev, bt, from_dma); -+ if (bt->interlaced == V4L2_DV_INTERLACED) { -+ bt->height *= 2; -+ bt->il_vsync = bt->vsync + 1; -+ } -+ -+ v4l2_dbg(2, debug, v4l2_dev, "tmds_clk:%llu\n", tmds_clk); -+ v4l2_dbg(1, debug, v4l2_dev, "interlace:%d, fmt:%d, vic:%d, color:%d, mode:%s\n", -+ bt->interlaced, hdmirx_dev->pix_fmt, -+ hdmirx_dev->cur_vic, hdmirx_dev->color_depth, -+ hdmirx_dev->is_dvi_mode ? "dvi" : "hdmi"); -+ v4l2_dbg(2, debug, v4l2_dev, "deframer_st:%#x\n", deframer_st); -+ -+ if (!hdmirx_check_timing_valid(bt)) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static bool port_no_link(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ return !tx_5v_power_present(hdmirx_dev); -+} -+ -+static int hdmirx_query_dv_timings(struct file *file, void *_fh, -+ struct v4l2_dv_timings *timings) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ int ret; -+ -+ if (port_no_link(hdmirx_dev)) { -+ v4l2_err(v4l2_dev, "%s: port has no link\n", __func__); -+ return -ENOLINK; -+ } -+ -+ if (signal_not_lock(hdmirx_dev)) { -+ v4l2_err(v4l2_dev, "%s: signal is not locked\n", __func__); -+ return -ENOLCK; -+ } -+ -+ ret = hdmirx_get_detected_timings(hdmirx_dev, timings, true); -+ if (ret) -+ return ret; -+ -+ if (debug) -+ v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name, -+ "query_dv_timings: ", timings, false); -+ -+ if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) { -+ v4l2_dbg(1, debug, v4l2_dev, "%s: timings out of range\n", __func__); -+ return -ERANGE; -+ } -+ -+ return 0; -+} -+ -+static void hdmirx_hpd_ctrl(struct snps_hdmirx_dev *hdmirx_dev, bool en) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ v4l2_dbg(1, debug, v4l2_dev, "%s: %sable, hpd_trigger_level:%d\n", -+ __func__, en ? "en" : "dis", -+ hdmirx_dev->hpd_trigger_level); -+ hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, HPDLOW, en ? 0 : HPDLOW); -+ en = hdmirx_dev->hpd_trigger_level ? en : !en; -+ hdmirx_writel(hdmirx_dev, CORE_CONFIG, en); -+} -+ -+static int hdmirx_write_edid(struct snps_hdmirx_dev *hdmirx_dev, -+ struct v4l2_edid *edid, bool hpd_up) -+{ -+ u32 edid_len = edid->blocks * EDID_BLOCK_SIZE; -+ char data[300]; -+ u32 i; -+ -+ memset(edid->reserved, 0, sizeof(edid->reserved)); -+ if (edid->pad) -+ return -EINVAL; -+ -+ if (edid->start_block) -+ return -EINVAL; -+ -+ if (edid->blocks > EDID_NUM_BLOCKS_MAX) { -+ edid->blocks = EDID_NUM_BLOCKS_MAX; -+ return -E2BIG; -+ } -+ -+ if (!edid->blocks) { -+ hdmirx_dev->edid_blocks_written = 0; -+ return 0; -+ } -+ -+ cec_s_phys_addr_from_edid(hdmirx_dev->cec->adap, -+ (const struct edid *)edid->edid); -+ -+ memset(&hdmirx_dev->edid, 0, sizeof(hdmirx_dev->edid)); -+ hdmirx_hpd_ctrl(hdmirx_dev, false); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11, -+ EDID_READ_EN_MASK | -+ EDID_WRITE_EN_MASK | -+ EDID_SLAVE_ADDR_MASK, -+ EDID_READ_EN(0) | -+ EDID_WRITE_EN(1) | -+ EDID_SLAVE_ADDR(0x50)); -+ for (i = 0; i < edid_len; i++) -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG10, edid->edid[i]); -+ -+ /* read out for debug */ -+ if (debug >= 2) { -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11, -+ EDID_READ_EN_MASK | -+ EDID_WRITE_EN_MASK, -+ EDID_READ_EN(1) | -+ EDID_WRITE_EN(0)); -+ edid_len = edid_len > sizeof(data) ? sizeof(data) : edid_len; -+ memset(data, 0, sizeof(data)); -+ for (i = 0; i < edid_len; i++) -+ data[i] = hdmirx_readl(hdmirx_dev, DMA_STATUS14); -+ -+ print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, data, -+ edid_len, false); -+ } -+ -+ /* -+ * You must set EDID_READ_EN & EDID_WRITE_EN bit to 0, -+ * when the read/write edid operation is completed.Otherwise, it -+ * will affect the reading and writing of other registers -+ */ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11, -+ EDID_READ_EN_MASK | EDID_WRITE_EN_MASK, -+ EDID_READ_EN(0) | EDID_WRITE_EN(0)); -+ -+ hdmirx_dev->edid_blocks_written = edid->blocks; -+ memcpy(&hdmirx_dev->edid, edid->edid, edid->blocks * EDID_BLOCK_SIZE); -+ if (hpd_up) { -+ if (tx_5v_power_present(hdmirx_dev)) { -+ /* Add 100ms delay after updating the EDID as per HDMI specs */ -+ msleep(100); -+ hdmirx_hpd_ctrl(hdmirx_dev, true); -+ } -+ } -+ -+ return 0; -+} -+ -+/* -+ * Before clearing interrupt, we need to read the interrupt status. -+ */ -+static inline void hdmirx_clear_interrupt(struct snps_hdmirx_dev *hdmirx_dev, -+ u32 reg, u32 val) -+{ -+ /* (interrupt status register) = (interrupt clear register) - 0x8 */ -+ hdmirx_readl(hdmirx_dev, reg - 0x8); -+ hdmirx_writel(hdmirx_dev, reg, val); -+} -+ -+static void hdmirx_interrupts_setup(struct snps_hdmirx_dev *hdmirx_dev, bool en) -+{ -+ v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: %sable\n", -+ __func__, en ? "en" : "dis"); -+ -+ /* Note: In DVI mode, it needs to be written twice to take effect. */ -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff); -+ -+ if (en) { -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N, -+ TMDSQPCLK_OFF_CHG | TMDSQPCLK_LOCKED_CHG, -+ TMDSQPCLK_OFF_CHG | TMDSQPCLK_LOCKED_CHG); -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N, -+ TMDSVALID_STABLE_CHG, TMDSVALID_STABLE_CHG); -+ hdmirx_update_bits(hdmirx_dev, AVPUNIT_0_INT_MASK_N, -+ CED_DYN_CNT_CH2_IRQ | -+ CED_DYN_CNT_CH1_IRQ | -+ CED_DYN_CNT_CH0_IRQ, -+ CED_DYN_CNT_CH2_IRQ | -+ CED_DYN_CNT_CH1_IRQ | -+ CED_DYN_CNT_CH0_IRQ); -+ } else { -+ hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0); -+ } -+} -+ -+static void hdmirx_plugout(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct arm_smccc_res res; -+ -+ hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, 0); -+ hdmirx_interrupts_setup(hdmirx_dev, false); -+ hdmirx_hpd_ctrl(hdmirx_dev, false); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, -+ LINE_FLAG_INT_EN | -+ HDMIRX_DMA_IDLE_INT | -+ HDMIRX_LOCK_DISABLE_INT | -+ LAST_FRAME_AXI_UNFINISH_INT_EN | -+ FIFO_OVERFLOW_INT_EN | -+ FIFO_UNDERFLOW_INT_EN | -+ HDMIRX_AXI_ERROR_INT_EN, 0); -+ hdmirx_reset_dma(hdmirx_dev); -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE | PHY_RESET | -+ PHY_PDDQ, HDMI_DISABLE); -+ hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x0); -+ cancel_delayed_work(&hdmirx_dev->delayed_work_res_change); -+ cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat); -+ flush_work(&hdmirx_dev->work_wdt_config); -+ arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res); -+} -+ -+static int hdmirx_set_edid(struct file *file, void *fh, struct v4l2_edid *edid) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct arm_smccc_res res; -+ int ret; -+ -+ disable_irq(hdmirx_dev->hdmi_irq); -+ disable_irq(hdmirx_dev->dma_irq); -+ arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_DIS, -+ RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res); -+ -+ if (tx_5v_power_present(hdmirx_dev)) -+ hdmirx_plugout(hdmirx_dev); -+ ret = hdmirx_write_edid(hdmirx_dev, edid, false); -+ if (ret) -+ return ret; -+ -+ enable_irq(hdmirx_dev->hdmi_irq); -+ enable_irq(hdmirx_dev->dma_irq); -+ arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN, -+ RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res); -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(500)); -+ return 0; -+} -+ -+static int hdmirx_get_edid(struct file *file, void *fh, struct v4l2_edid *edid) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ memset(edid->reserved, 0, sizeof(edid->reserved)); -+ -+ if (edid->pad) -+ return -EINVAL; -+ -+ if (!edid->start_block && !edid->blocks) { -+ edid->blocks = hdmirx_dev->edid_blocks_written; -+ return 0; -+ } -+ -+ if (!hdmirx_dev->edid_blocks_written) -+ return -ENODATA; -+ -+ if (edid->start_block >= hdmirx_dev->edid_blocks_written || !edid->blocks) -+ return -EINVAL; -+ -+ if (edid->start_block + edid->blocks > hdmirx_dev->edid_blocks_written) -+ edid->blocks = hdmirx_dev->edid_blocks_written - edid->start_block; -+ -+ memcpy(edid->edid, &hdmirx_dev->edid, edid->blocks * EDID_BLOCK_SIZE); -+ -+ v4l2_dbg(1, debug, v4l2_dev, "%s: read EDID:\n", __func__); -+ if (debug > 0) -+ print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, -+ edid->edid, edid->blocks * EDID_BLOCK_SIZE, false); -+ -+ return 0; -+} -+ -+static int hdmirx_g_parm(struct file *file, void *priv, -+ struct v4l2_streamparm *parm) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_fract fps; -+ -+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) -+ return -EINVAL; -+ -+ fps = v4l2_calc_timeperframe(&hdmirx_dev->timings); -+ parm->parm.capture.timeperframe.numerator = fps.numerator; -+ parm->parm.capture.timeperframe.denominator = fps.denominator; -+ -+ return 0; -+} -+ -+static int hdmirx_dv_timings_cap(struct file *file, void *fh, -+ struct v4l2_dv_timings_cap *cap) -+{ -+ *cap = hdmirx_timings_cap; -+ return 0; -+} -+ -+static int hdmirx_enum_dv_timings(struct file *file, void *_fh, -+ struct v4l2_enum_dv_timings *timings) -+{ -+ return v4l2_enum_dv_timings_cap(timings, &hdmirx_timings_cap, NULL, NULL); -+} -+ -+static void hdmirx_scdc_init(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ hdmirx_update_bits(hdmirx_dev, I2C_SLAVE_CONFIG1, -+ I2C_SDA_OUT_HOLD_VALUE_QST_MASK | -+ I2C_SDA_IN_HOLD_VALUE_QST_MASK, -+ I2C_SDA_OUT_HOLD_VALUE_QST(0x80) | -+ I2C_SDA_IN_HOLD_VALUE_QST(0x15)); -+ hdmirx_update_bits(hdmirx_dev, SCDC_REGBANK_CONFIG0, -+ SCDC_SINKVERSION_QST_MASK, -+ SCDC_SINKVERSION_QST(1)); -+} -+ -+static int wait_reg_bit_status(struct snps_hdmirx_dev *hdmirx_dev, u32 reg, -+ u32 bit_mask, u32 expect_val, bool is_grf, -+ u32 ms) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 i, val; -+ -+ for (i = 0; i < ms; i++) { -+ if (is_grf) -+ regmap_read(hdmirx_dev->grf, reg, &val); -+ else -+ val = hdmirx_readl(hdmirx_dev, reg); -+ -+ if ((val & bit_mask) == expect_val) { -+ v4l2_dbg(2, debug, v4l2_dev, -+ "%s: i:%d, time: %dms\n", __func__, i, ms); -+ break; -+ } -+ usleep_range(1000, 1010); -+ } -+ -+ if (i == ms) -+ return -1; -+ -+ return 0; -+} -+ -+static int hdmirx_phy_register_write(struct snps_hdmirx_dev *hdmirx_dev, -+ u32 phy_reg, u32 val) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ -+ reinit_completion(&hdmirx_dev->cr_write_done); -+ /* clear irq status */ -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); -+ /* en irq */ -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N, -+ PHYCREG_CR_WRITE_DONE, PHYCREG_CR_WRITE_DONE); -+ /* write phy reg addr */ -+ hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG1, phy_reg); -+ /* write phy reg val */ -+ hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG2, val); -+ /* config write enable */ -+ hdmirx_writel(hdmirx_dev, PHYCREG_CONTROL, PHYCREG_CR_PARA_WRITE_P); -+ -+ if (!wait_for_completion_timeout(&hdmirx_dev->cr_write_done, -+ msecs_to_jiffies(20))) { -+ dev_err(dev, "%s wait cr write done failed\n", __func__); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static void hdmirx_tmds_clk_ratio_config(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 val; -+ -+ val = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS1); -+ v4l2_dbg(3, debug, v4l2_dev, "%s: scdc_regbank_st:%#x\n", __func__, val); -+ hdmirx_dev->tmds_clk_ratio = (val & SCDC_TMDSBITCLKRATIO) > 0; -+ -+ if (hdmirx_dev->tmds_clk_ratio) { -+ v4l2_dbg(3, debug, v4l2_dev, "%s: HDMITX greater than 3.4Gbps\n", __func__); -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, -+ TMDS_CLOCK_RATIO, TMDS_CLOCK_RATIO); -+ } else { -+ v4l2_dbg(3, debug, v4l2_dev, "%s: HDMITX less than 3.4Gbps\n", __func__); -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, -+ TMDS_CLOCK_RATIO, 0); -+ } -+} -+ -+static void hdmirx_phy_config(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ -+ hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff); -+ hdmirx_update_bits(hdmirx_dev, SCDC_INT_MASK_N, SCDCTMDSCCFG_CHG, -+ SCDCTMDSCCFG_CHG); -+ /* cr_para_clk 24M */ -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, REFFREQ_SEL_MASK, REFFREQ_SEL(0)); -+ /* rx data width 40bit valid */ -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, RXDATA_WIDTH, RXDATA_WIDTH); -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, PHY_RESET); -+ usleep_range(100, 110); -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, 0); -+ usleep_range(100, 110); -+ /* select cr para interface */ -+ hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x3); -+ -+ if (wait_reg_bit_status(hdmirx_dev, SYS_GRF_SOC_STATUS1, -+ HDMIRXPHY_SRAM_INIT_DONE, -+ HDMIRXPHY_SRAM_INIT_DONE, true, 10)) -+ dev_err(dev, "%s: phy SRAM init failed\n", __func__); -+ -+ regmap_write(hdmirx_dev->grf, SYS_GRF_SOC_CON1, -+ (HDMIRXPHY_SRAM_EXT_LD_DONE << 16) | -+ HDMIRXPHY_SRAM_EXT_LD_DONE); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 3); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 3); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 1); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0); -+ -+ hdmirx_phy_register_write(hdmirx_dev, -+ HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG, -+ CDR_SETTING_BOUNDARY_3_DEFAULT); -+ hdmirx_phy_register_write(hdmirx_dev, -+ HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG, -+ CDR_SETTING_BOUNDARY_4_DEFAULT); -+ hdmirx_phy_register_write(hdmirx_dev, -+ HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG, -+ CDR_SETTING_BOUNDARY_5_DEFAULT); -+ hdmirx_phy_register_write(hdmirx_dev, -+ HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG, -+ CDR_SETTING_BOUNDARY_6_DEFAULT); -+ hdmirx_phy_register_write(hdmirx_dev, -+ HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG, -+ CDR_SETTING_BOUNDARY_7_DEFAULT); -+ -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_PDDQ, 0); -+ if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, PDDQ_ACK, 0, false, 10)) -+ dev_err(dev, "%s: wait pddq ack failed\n", __func__); -+ -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE, 0); -+ if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, HDMI_DISABLE_ACK, 0, -+ false, 50)) -+ dev_err(dev, "%s: wait hdmi disable ack failed\n", __func__); -+ -+ hdmirx_tmds_clk_ratio_config(hdmirx_dev); -+} -+ -+static void hdmirx_controller_init(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ -+ reinit_completion(&hdmirx_dev->timer_base_lock); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff); -+ /* en irq */ -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N, -+ TIMER_BASE_LOCKED_IRQ, TIMER_BASE_LOCKED_IRQ); -+ /* write irefclk freq */ -+ hdmirx_writel(hdmirx_dev, GLOBAL_TIMER_REF_BASE, IREF_CLK_FREQ_HZ); -+ -+ if (!wait_for_completion_timeout(&hdmirx_dev->timer_base_lock, -+ msecs_to_jiffies(20))) -+ dev_err(dev, "%s wait timer base lock failed\n", __func__); -+ -+ hdmirx_update_bits(hdmirx_dev, CMU_CONFIG0, -+ TMDSQPCLK_STABLE_FREQ_MARGIN_MASK | -+ AUDCLK_STABLE_FREQ_MARGIN_MASK, -+ TMDSQPCLK_STABLE_FREQ_MARGIN(2) | -+ AUDCLK_STABLE_FREQ_MARGIN(1)); -+ hdmirx_update_bits(hdmirx_dev, DESCRAND_EN_CONTROL, -+ SCRAMB_EN_SEL_QST_MASK, SCRAMB_EN_SEL_QST(1)); -+ hdmirx_update_bits(hdmirx_dev, CED_CONFIG, -+ CED_VIDDATACHECKEN_QST | -+ CED_DATAISCHECKEN_QST | -+ CED_GBCHECKEN_QST | -+ CED_CTRLCHECKEN_QST | -+ CED_CHLOCKMAXER_QST_MASK, -+ CED_VIDDATACHECKEN_QST | -+ CED_GBCHECKEN_QST | -+ CED_CTRLCHECKEN_QST | -+ CED_CHLOCKMAXER_QST(0x10)); -+ hdmirx_update_bits(hdmirx_dev, DEFRAMER_CONFIG0, -+ VS_REMAPFILTER_EN_QST | VS_FILTER_ORDER_QST_MASK, -+ VS_REMAPFILTER_EN_QST | VS_FILTER_ORDER_QST(0x3)); -+} -+ -+static void hdmirx_set_negative_pol(struct snps_hdmirx_dev *hdmirx_dev, bool en) -+{ -+ if (en) { -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, -+ VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN, -+ VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN); -+ hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2, -+ VPROC_VSYNC_POL_OVR_VALUE | -+ VPROC_VSYNC_POL_OVR_EN | -+ VPROC_HSYNC_POL_OVR_VALUE | -+ VPROC_HSYNC_POL_OVR_EN, -+ VPROC_VSYNC_POL_OVR_EN | -+ VPROC_HSYNC_POL_OVR_EN); -+ return; -+ } -+ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, -+ VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN, 0); -+ -+ hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2, -+ VPROC_VSYNC_POL_OVR_VALUE | -+ VPROC_VSYNC_POL_OVR_EN | -+ VPROC_HSYNC_POL_OVR_VALUE | -+ VPROC_HSYNC_POL_OVR_EN, 0); -+} -+ -+static int hdmirx_try_to_get_timings(struct snps_hdmirx_dev *hdmirx_dev, -+ struct v4l2_dv_timings *timings, -+ int try_cnt) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ int i, cnt = 0, fail_cnt = 0, ret = 0; -+ bool from_dma = false; -+ -+ hdmirx_set_negative_pol(hdmirx_dev, false); -+ for (i = 0; i < try_cnt; i++) { -+ ret = hdmirx_get_detected_timings(hdmirx_dev, timings, from_dma); -+ if (ret) { -+ cnt = 0; -+ fail_cnt++; -+ if (fail_cnt > 3) { -+ hdmirx_set_negative_pol(hdmirx_dev, true); -+ from_dma = true; -+ } -+ } else { -+ cnt++; -+ } -+ if (cnt >= 5) -+ break; -+ -+ usleep_range(10 * 1000, 10 * 1100); -+ } -+ -+ if (try_cnt > 8 && cnt < 5) -+ v4l2_dbg(1, debug, v4l2_dev, "%s: res not stable\n", __func__); -+ -+ return ret; -+} -+ -+static void hdmirx_format_change(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_dv_timings timings; -+ struct hdmirx_stream *stream = &hdmirx_dev->stream; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ const struct v4l2_event ev_src_chg = { -+ .type = V4L2_EVENT_SOURCE_CHANGE, -+ .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, -+ }; -+ -+ if (hdmirx_try_to_get_timings(hdmirx_dev, &timings, 20)) { -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(20)); -+ return; -+ } -+ -+ hdmirx_dev->got_timing = true; -+ v4l2_dbg(1, debug, v4l2_dev, "%s: queue res_chg_event\n", __func__); -+ v4l2_event_queue(&stream->vdev, &ev_src_chg); -+} -+ -+static void hdmirx_set_ddr_store_fmt(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ enum ddr_store_fmt store_fmt; -+ u32 dma_cfg1; -+ -+ switch (hdmirx_dev->pix_fmt) { -+ case HDMIRX_RGB888: -+ store_fmt = STORE_RGB888; -+ break; -+ case HDMIRX_YUV444: -+ store_fmt = STORE_YUV444_8BIT; -+ break; -+ case HDMIRX_YUV422: -+ store_fmt = STORE_YUV422_8BIT; -+ break; -+ case HDMIRX_YUV420: -+ store_fmt = STORE_YUV420_8BIT; -+ break; -+ default: -+ store_fmt = STORE_RGB888; -+ break; -+ } -+ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG1, -+ DDR_STORE_FORMAT_MASK, DDR_STORE_FORMAT(store_fmt)); -+ dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1); -+ v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n", -+ __func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1); -+} -+ -+static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 mu_status, scdc_status, dma_st10, cmu_st; -+ u32 i; -+ -+ for (i = 0; i < 300; i++) { -+ mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS); -+ scdc_status = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS3); -+ dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10); -+ cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS); -+ -+ if ((mu_status & TMDSVALID_STABLE_ST) && -+ (dma_st10 & HDMIRX_LOCK) && -+ (cmu_st & TMDSQPCLK_LOCKED_ST)) -+ break; -+ -+ if (!tx_5v_power_present(hdmirx_dev)) { -+ v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__); -+ return -1; -+ } -+ -+ hdmirx_tmds_clk_ratio_config(hdmirx_dev); -+ } -+ -+ if (i == 300) { -+ v4l2_err(v4l2_dev, "%s: signal not lock, tmds_clk_ratio:%d\n", -+ __func__, hdmirx_dev->tmds_clk_ratio); -+ v4l2_err(v4l2_dev, "%s: mu_st:%#x, scdc_st:%#x, dma_st10:%#x\n", -+ __func__, mu_status, scdc_status, dma_st10); -+ return -1; -+ } -+ -+ v4l2_info(v4l2_dev, "%s: signal lock ok, i:%d\n", __func__, i); -+ hdmirx_writel(hdmirx_dev, GLOBAL_SWRESET_REQUEST, DATAPATH_SWRESETREQ); -+ -+ reinit_completion(&hdmirx_dev->avi_pkt_rcv); -+ hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N, -+ PKTDEC_AVIIF_RCV_IRQ, PKTDEC_AVIIF_RCV_IRQ); -+ -+ if (!wait_for_completion_timeout(&hdmirx_dev->avi_pkt_rcv, -+ msecs_to_jiffies(300))) { -+ v4l2_err(v4l2_dev, "%s wait avi_pkt_rcv failed\n", __func__); -+ hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N, -+ PKTDEC_AVIIF_RCV_IRQ, 0); -+ } -+ -+ usleep_range(50 * 1000, 50 * 1010); -+ hdmirx_format_change(hdmirx_dev); -+ -+ return 0; -+} -+ -+static void hdmirx_dma_config(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ hdmirx_set_ddr_store_fmt(hdmirx_dev); -+ -+ /* Note: uv_swap, rb can not swap, doc err*/ -+ if (hdmirx_dev->cur_fmt_fourcc != V4L2_PIX_FMT_NV16) -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, RB_SWAP_EN, RB_SWAP_EN); -+ else -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, RB_SWAP_EN, 0); -+ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG7, -+ LOCK_FRAME_NUM_MASK, -+ LOCK_FRAME_NUM(2)); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG1, -+ UV_WID_MASK | Y_WID_MASK | ABANDON_EN, -+ UV_WID(1) | Y_WID(2) | ABANDON_EN); -+} -+ -+static void hdmirx_submodule_init(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ /* Note: if not config HDCP2_CONFIG, there will be some errors; */ -+ hdmirx_update_bits(hdmirx_dev, HDCP2_CONFIG, -+ HDCP2_SWITCH_OVR_VALUE | -+ HDCP2_SWITCH_OVR_EN, -+ HDCP2_SWITCH_OVR_EN); -+ hdmirx_scdc_init(hdmirx_dev); -+ hdmirx_controller_init(hdmirx_dev); -+} -+ -+static int hdmirx_enum_input(struct file *file, void *priv, -+ struct v4l2_input *input) -+{ -+ if (input->index > 0) -+ return -EINVAL; -+ -+ input->type = V4L2_INPUT_TYPE_CAMERA; -+ input->std = 0; -+ strscpy(input->name, "HDMI IN", sizeof(input->name)); -+ input->capabilities = V4L2_IN_CAP_DV_TIMINGS; -+ -+ return 0; -+} -+ -+static int hdmirx_get_input(struct file *file, void *priv, unsigned int *i) -+{ -+ *i = 0; -+ return 0; -+} -+ -+static int hdmirx_set_input(struct file *file, void *priv, unsigned int i) -+{ -+ if (i) -+ return -EINVAL; -+ return 0; -+} -+ -+static void hdmirx_set_fmt(struct hdmirx_stream *stream, -+ struct v4l2_pix_format_mplane *pixm, bool try) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct v4l2_bt_timings *bt = &hdmirx_dev->timings.bt; -+ const struct v4l2_format_info *finfo; -+ unsigned int imagesize = 0; -+ int i; -+ -+ memset(&pixm->plane_fmt[0], 0, sizeof(struct v4l2_plane_pix_format)); -+ finfo = v4l2_format_info(pixm->pixelformat); -+ if (!finfo) { -+ finfo = v4l2_format_info(V4L2_PIX_FMT_BGR24); -+ v4l2_dbg(1, debug, v4l2_dev, -+ "%s: set_fmt:%#x not supported, use def_fmt:%x\n", -+ __func__, pixm->pixelformat, finfo->format); -+ } -+ -+ if (!bt->width || !bt->height) -+ v4l2_dbg(1, debug, v4l2_dev, "%s: invalid resolution:%#xx%#x\n", -+ __func__, bt->width, bt->height); -+ -+ pixm->pixelformat = finfo->format; -+ pixm->width = bt->width; -+ pixm->height = bt->height; -+ pixm->num_planes = finfo->mem_planes; -+ pixm->quantization = V4L2_QUANTIZATION_DEFAULT; -+ pixm->colorspace = V4L2_COLORSPACE_SRGB; -+ pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; -+ -+ if (bt->interlaced == V4L2_DV_INTERLACED) -+ pixm->field = V4L2_FIELD_INTERLACED_TB; -+ else -+ pixm->field = V4L2_FIELD_NONE; -+ -+ memset(pixm->reserved, 0, sizeof(pixm->reserved)); -+ -+ v4l2_fill_pixfmt_mp(pixm, finfo->format, pixm->width, pixm->height); -+ -+ for (i = 0; i < pixm->num_planes; i++) { -+ struct v4l2_plane_pix_format *plane_fmt; -+ int width, height, bpl, size, bpp = 0; -+ -+ if (!i) { -+ width = pixm->width; -+ height = pixm->height; -+ } else { -+ width = pixm->width / finfo->hdiv; -+ height = pixm->height / finfo->vdiv; -+ } -+ -+ switch (finfo->format) { -+ case V4L2_PIX_FMT_NV24: -+ case V4L2_PIX_FMT_NV16: -+ case V4L2_PIX_FMT_NV12: -+ case V4L2_PIX_FMT_BGR24: -+ bpp = finfo->bpp[i]; -+ break; -+ default: -+ v4l2_dbg(1, debug, v4l2_dev, -+ "fourcc: %#x is not supported\n", -+ finfo->format); -+ break; -+ } -+ -+ bpl = ALIGN(width * bpp, MEMORY_ALIGN_ROUND_UP_BYTES); -+ size = bpl * height; -+ imagesize += size; -+ -+ if (finfo->mem_planes > i) { -+ /* Set bpl and size for each mplane */ -+ plane_fmt = pixm->plane_fmt + i; -+ plane_fmt->bytesperline = bpl; -+ plane_fmt->sizeimage = size; -+ } -+ -+ v4l2_dbg(1, debug, v4l2_dev, -+ "C-Plane %i size: %d, Total imagesize: %d\n", -+ i, size, imagesize); -+ } -+ -+ /* Convert to non-MPLANE format as we want to unify non-MPLANE and MPLANE */ -+ if (finfo->mem_planes == 1) -+ pixm->plane_fmt[0].sizeimage = imagesize; -+ -+ if (!try) { -+ stream->out_finfo = finfo; -+ stream->pixm = *pixm; -+ v4l2_dbg(1, debug, v4l2_dev, -+ "%s: req(%d, %d), out(%d, %d), fmt:%#x\n", __func__, -+ pixm->width, pixm->height, stream->pixm.width, -+ stream->pixm.height, finfo->format); -+ } -+} -+ -+static int hdmirx_enum_fmt_vid_cap_mplane(struct file *file, void *priv, -+ struct v4l2_fmtdesc *f) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ -+ if (f->index >= 1) -+ return -EINVAL; -+ -+ f->pixelformat = hdmirx_dev->cur_fmt_fourcc; -+ -+ return 0; -+} -+ -+static int hdmirx_s_fmt_vid_cap_mplane(struct file *file, -+ void *priv, struct v4l2_format *f) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ if (vb2_is_busy(&stream->buf_queue)) { -+ v4l2_err(v4l2_dev, "%s: queue busy\n", __func__); -+ return -EBUSY; -+ } -+ -+ hdmirx_set_fmt(stream, &f->fmt.pix_mp, false); -+ -+ return 0; -+} -+ -+static int hdmirx_g_fmt_vid_cap_mplane(struct file *file, void *fh, -+ struct v4l2_format *f) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_pix_format_mplane pixm = {}; -+ -+ pixm.pixelformat = hdmirx_dev->cur_fmt_fourcc; -+ hdmirx_set_fmt(stream, &pixm, true); -+ f->fmt.pix_mp = pixm; -+ -+ return 0; -+} -+ -+static int hdmirx_g_dv_timings(struct file *file, void *_fh, -+ struct v4l2_dv_timings *timings) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 dma_cfg1; -+ -+ *timings = hdmirx_dev->timings; -+ dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1); -+ v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n", -+ __func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1); -+ -+ return 0; -+} -+ -+static int hdmirx_s_dv_timings(struct file *file, void *_fh, -+ struct v4l2_dv_timings *timings) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ if (!timings) -+ return -EINVAL; -+ -+ if (debug) -+ v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name, -+ "s_dv_timings: ", timings, false); -+ -+ if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) { -+ v4l2_dbg(1, debug, v4l2_dev, -+ "%s: timings out of range\n", __func__); -+ return -ERANGE; -+ } -+ -+ /* Check if the timings are part of the CEA-861 timings. */ -+ v4l2_find_dv_timings_cap(timings, &hdmirx_timings_cap, 0, NULL, NULL); -+ -+ if (v4l2_match_dv_timings(&hdmirx_dev->timings, timings, 0, false)) { -+ v4l2_dbg(1, debug, v4l2_dev, "%s: no change\n", __func__); -+ return 0; -+ } -+ -+ /* -+ * Changing the timings implies a format change, which is not allowed -+ * while buffers for use with streaming have already been allocated. -+ */ -+ if (vb2_is_busy(&stream->buf_queue)) -+ return -EBUSY; -+ -+ hdmirx_dev->timings = *timings; -+ /* Update the internal format */ -+ hdmirx_set_fmt(stream, &stream->pixm, false); -+ -+ return 0; -+} -+ -+static int hdmirx_querycap(struct file *file, void *priv, -+ struct v4l2_capability *cap) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct device *dev = stream->hdmirx_dev->dev; -+ -+ strscpy(cap->driver, dev->driver->name, sizeof(cap->driver)); -+ strscpy(cap->card, dev->driver->name, sizeof(cap->card)); -+ -+ return 0; -+} -+ -+static int hdmirx_queue_setup(struct vb2_queue *queue, -+ unsigned int *num_buffers, -+ unsigned int *num_planes, -+ unsigned int sizes[], -+ struct device *alloc_ctxs[]) -+{ -+ struct hdmirx_stream *stream = vb2_get_drv_priv(queue); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ const struct v4l2_pix_format_mplane *pixm = NULL; -+ const struct v4l2_format_info *out_finfo; -+ u32 i, height; -+ -+ pixm = &stream->pixm; -+ out_finfo = stream->out_finfo; -+ -+ if (!num_planes || !out_finfo) { -+ v4l2_err(v4l2_dev, "%s: out_fmt not set\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (*num_planes) { -+ if (*num_planes != pixm->num_planes) -+ return -EINVAL; -+ -+ for (i = 0; i < *num_planes; i++) -+ if (sizes[i] < pixm->plane_fmt[i].sizeimage) -+ return -EINVAL; -+ return 0; -+ } -+ -+ *num_planes = out_finfo->mem_planes; -+ height = pixm->height; -+ -+ for (i = 0; i < out_finfo->mem_planes; i++) -+ sizes[i] = pixm->plane_fmt[i].sizeimage; -+ -+ v4l2_dbg(1, debug, v4l2_dev, "%s: count %d, size %d\n", -+ v4l2_type_names[queue->type], *num_buffers, sizes[0]); -+ -+ return 0; -+} -+ -+/* -+ * The vb2_buffer are stored in hdmirx_buffer, in order to unify -+ * mplane buffer and none-mplane buffer. -+ */ -+static void hdmirx_buf_queue(struct vb2_buffer *vb) -+{ -+ const struct v4l2_format_info *out_finfo; -+ struct vb2_v4l2_buffer *vbuf; -+ struct hdmirx_buffer *hdmirx_buf; -+ struct vb2_queue *queue; -+ struct hdmirx_stream *stream; -+ const struct v4l2_pix_format_mplane *pixm; -+ unsigned long lock_flags = 0; -+ int i; -+ -+ vbuf = to_vb2_v4l2_buffer(vb); -+ hdmirx_buf = container_of(vbuf, struct hdmirx_buffer, vb); -+ queue = vb->vb2_queue; -+ stream = vb2_get_drv_priv(queue); -+ pixm = &stream->pixm; -+ out_finfo = stream->out_finfo; -+ -+ memset(hdmirx_buf->buff_addr, 0, sizeof(hdmirx_buf->buff_addr)); -+ -+ /* -+ * If mplanes > 1, every c-plane has its own m-plane, -+ * otherwise, multiple c-planes are in the same m-plane -+ */ -+ for (i = 0; i < out_finfo->mem_planes; i++) -+ hdmirx_buf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i); -+ -+ if (out_finfo->mem_planes == 1) { -+ if (out_finfo->comp_planes == 1) { -+ hdmirx_buf->buff_addr[HDMIRX_PLANE_CBCR] = -+ hdmirx_buf->buff_addr[HDMIRX_PLANE_Y]; -+ } else { -+ for (i = 0; i < out_finfo->comp_planes - 1; i++) -+ hdmirx_buf->buff_addr[i + 1] = -+ hdmirx_buf->buff_addr[i] + -+ pixm->plane_fmt[i].bytesperline * -+ pixm->height; -+ } -+ } -+ -+ spin_lock_irqsave(&stream->vbq_lock, lock_flags); -+ list_add_tail(&hdmirx_buf->queue, &stream->buf_head); -+ spin_unlock_irqrestore(&stream->vbq_lock, lock_flags); -+} -+ -+static void return_all_buffers(struct hdmirx_stream *stream, -+ enum vb2_buffer_state state) -+{ -+ struct hdmirx_buffer *buf; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&stream->vbq_lock, flags); -+ if (stream->curr_buf) -+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head); -+ if (stream->next_buf && stream->next_buf != stream->curr_buf) -+ list_add_tail(&stream->next_buf->queue, &stream->buf_head); -+ stream->curr_buf = NULL; -+ stream->next_buf = NULL; -+ -+ while (!list_empty(&stream->buf_head)) { -+ buf = list_first_entry(&stream->buf_head, -+ struct hdmirx_buffer, queue); -+ list_del(&buf->queue); -+ spin_unlock_irqrestore(&stream->vbq_lock, flags); -+ vb2_buffer_done(&buf->vb.vb2_buf, state); -+ spin_lock_irqsave(&stream->vbq_lock, flags); -+ } -+ spin_unlock_irqrestore(&stream->vbq_lock, flags); -+} -+ -+static void hdmirx_stop_streaming(struct vb2_queue *queue) -+{ -+ struct hdmirx_stream *stream = vb2_get_drv_priv(queue); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ int ret; -+ -+ v4l2_info(v4l2_dev, "stream start stopping\n"); -+ mutex_lock(&hdmirx_dev->stream_lock); -+ WRITE_ONCE(stream->stopping, true); -+ -+ /* wait last irq to return the buffer */ -+ ret = wait_event_timeout(stream->wq_stopped, !stream->stopping, -+ msecs_to_jiffies(500)); -+ if (!ret) { -+ v4l2_err(v4l2_dev, "%s: timeout waiting last irq\n", -+ __func__); -+ WRITE_ONCE(stream->stopping, false); -+ } -+ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0); -+ return_all_buffers(stream, VB2_BUF_STATE_ERROR); -+ mutex_unlock(&hdmirx_dev->stream_lock); -+ v4l2_info(v4l2_dev, "stream stopping finished\n"); -+} -+ -+static int hdmirx_start_streaming(struct vb2_queue *queue, unsigned int count) -+{ -+ struct hdmirx_stream *stream = vb2_get_drv_priv(queue); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct v4l2_dv_timings timings = hdmirx_dev->timings; -+ struct v4l2_bt_timings *bt = &timings.bt; -+ unsigned long lock_flags = 0; -+ int line_flag; -+ -+ if (!hdmirx_dev->got_timing) { -+ v4l2_dbg(1, debug, v4l2_dev, "timing is invalid\n"); -+ return 0; -+ } -+ -+ mutex_lock(&hdmirx_dev->stream_lock); -+ stream->frame_idx = 0; -+ stream->line_flag_int_cnt = 0; -+ stream->curr_buf = NULL; -+ stream->next_buf = NULL; -+ stream->irq_stat = 0; -+ queue->min_queued_buffers = 1; -+ -+ WRITE_ONCE(stream->stopping, false); -+ -+ spin_lock_irqsave(&stream->vbq_lock, lock_flags); -+ if (!stream->curr_buf) { -+ if (!list_empty(&stream->buf_head)) { -+ stream->curr_buf = list_first_entry(&stream->buf_head, -+ struct hdmirx_buffer, -+ queue); -+ list_del(&stream->curr_buf->queue); -+ } else { -+ stream->curr_buf = NULL; -+ } -+ } -+ spin_unlock_irqrestore(&stream->vbq_lock, lock_flags); -+ -+ v4l2_dbg(2, debug, v4l2_dev, -+ "%s: start_stream cur_buf y_addr:%#x, uv_addr:%#x\n", -+ __func__, stream->curr_buf->buff_addr[HDMIRX_PLANE_Y], -+ stream->curr_buf->buff_addr[HDMIRX_PLANE_CBCR]); -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG2, -+ stream->curr_buf->buff_addr[HDMIRX_PLANE_Y]); -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG3, -+ stream->curr_buf->buff_addr[HDMIRX_PLANE_CBCR]); -+ -+ if (bt->height) { -+ if (bt->interlaced == V4L2_DV_INTERLACED) -+ line_flag = bt->height / 4; -+ else -+ line_flag = bt->height / 2; -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG7, -+ LINE_FLAG_NUM_MASK, -+ LINE_FLAG_NUM(line_flag)); -+ } else { -+ v4l2_err(v4l2_dev, "height err: %d\n", bt->height); -+ } -+ -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff); -+ hdmirx_writel(hdmirx_dev, CED_DYN_CONTROL, 0x1); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, -+ LINE_FLAG_INT_EN | -+ HDMIRX_DMA_IDLE_INT | -+ HDMIRX_LOCK_DISABLE_INT | -+ LAST_FRAME_AXI_UNFINISH_INT_EN | -+ FIFO_OVERFLOW_INT_EN | -+ FIFO_UNDERFLOW_INT_EN | -+ HDMIRX_AXI_ERROR_INT_EN, -+ LINE_FLAG_INT_EN | -+ HDMIRX_DMA_IDLE_INT | -+ HDMIRX_LOCK_DISABLE_INT | -+ LAST_FRAME_AXI_UNFINISH_INT_EN | -+ FIFO_OVERFLOW_INT_EN | -+ FIFO_UNDERFLOW_INT_EN | -+ HDMIRX_AXI_ERROR_INT_EN); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, HDMIRX_DMA_EN); -+ v4l2_dbg(1, debug, v4l2_dev, "%s: enable dma", __func__); -+ mutex_unlock(&hdmirx_dev->stream_lock); -+ -+ return 0; -+} -+ -+/* vb2 queue */ -+static const struct vb2_ops hdmirx_vb2_ops = { -+ .queue_setup = hdmirx_queue_setup, -+ .buf_queue = hdmirx_buf_queue, -+ .wait_prepare = vb2_ops_wait_prepare, -+ .wait_finish = vb2_ops_wait_finish, -+ .stop_streaming = hdmirx_stop_streaming, -+ .start_streaming = hdmirx_start_streaming, -+}; -+ -+static int hdmirx_init_vb2_queue(struct vb2_queue *q, -+ struct hdmirx_stream *stream, -+ enum v4l2_buf_type buf_type) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ -+ q->type = buf_type; -+ q->io_modes = VB2_MMAP | VB2_DMABUF; -+ q->drv_priv = stream; -+ q->ops = &hdmirx_vb2_ops; -+ q->mem_ops = &vb2_dma_contig_memops; -+ q->buf_struct_size = sizeof(struct hdmirx_buffer); -+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; -+ q->lock = &stream->vlock; -+ q->dev = hdmirx_dev->dev; -+ /* -+ * rk3588 doesn't use iommu and works only with dma buffers -+ * that are physically contiguous in memory. -+ */ -+ q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; -+ return vb2_queue_init(q); -+} -+ -+/* video device */ -+static const struct v4l2_ioctl_ops hdmirx_v4l2_ioctl_ops = { -+ .vidioc_querycap = hdmirx_querycap, -+ .vidioc_try_fmt_vid_cap_mplane = hdmirx_g_fmt_vid_cap_mplane, -+ .vidioc_s_fmt_vid_cap_mplane = hdmirx_s_fmt_vid_cap_mplane, -+ .vidioc_g_fmt_vid_cap_mplane = hdmirx_g_fmt_vid_cap_mplane, -+ .vidioc_enum_fmt_vid_cap = hdmirx_enum_fmt_vid_cap_mplane, -+ -+ .vidioc_s_dv_timings = hdmirx_s_dv_timings, -+ .vidioc_g_dv_timings = hdmirx_g_dv_timings, -+ .vidioc_enum_dv_timings = hdmirx_enum_dv_timings, -+ .vidioc_query_dv_timings = hdmirx_query_dv_timings, -+ .vidioc_dv_timings_cap = hdmirx_dv_timings_cap, -+ .vidioc_enum_input = hdmirx_enum_input, -+ .vidioc_g_input = hdmirx_get_input, -+ .vidioc_s_input = hdmirx_set_input, -+ .vidioc_g_edid = hdmirx_get_edid, -+ .vidioc_s_edid = hdmirx_set_edid, -+ .vidioc_g_parm = hdmirx_g_parm, -+ -+ .vidioc_reqbufs = vb2_ioctl_reqbufs, -+ .vidioc_querybuf = vb2_ioctl_querybuf, -+ .vidioc_create_bufs = vb2_ioctl_create_bufs, -+ .vidioc_qbuf = vb2_ioctl_qbuf, -+ .vidioc_expbuf = vb2_ioctl_expbuf, -+ .vidioc_dqbuf = vb2_ioctl_dqbuf, -+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf, -+ .vidioc_streamon = vb2_ioctl_streamon, -+ .vidioc_streamoff = vb2_ioctl_streamoff, -+ -+ .vidioc_log_status = v4l2_ctrl_log_status, -+ .vidioc_subscribe_event = hdmirx_subscribe_event, -+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, -+}; -+ -+static const struct v4l2_file_operations hdmirx_fops = { -+ .owner = THIS_MODULE, -+ .open = v4l2_fh_open, -+ .release = vb2_fop_release, -+ .unlocked_ioctl = video_ioctl2, -+ .poll = vb2_fop_poll, -+ .mmap = vb2_fop_mmap, -+}; -+ -+static int hdmirx_register_stream_vdev(struct hdmirx_stream *stream) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct video_device *vdev = &stream->vdev; -+ int ret = 0; -+ -+ strscpy(vdev->name, "stream_hdmirx", sizeof(vdev->name)); -+ INIT_LIST_HEAD(&stream->buf_head); -+ spin_lock_init(&stream->vbq_lock); -+ mutex_init(&stream->vlock); -+ init_waitqueue_head(&stream->wq_stopped); -+ stream->curr_buf = NULL; -+ stream->next_buf = NULL; -+ -+ vdev->ioctl_ops = &hdmirx_v4l2_ioctl_ops; -+ vdev->release = video_device_release_empty; -+ vdev->fops = &hdmirx_fops; -+ vdev->minor = -1; -+ vdev->v4l2_dev = v4l2_dev; -+ vdev->lock = &stream->vlock; -+ vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | -+ V4L2_CAP_STREAMING; -+ video_set_drvdata(vdev, stream); -+ vdev->vfl_dir = VFL_DIR_RX; -+ -+ hdmirx_init_vb2_queue(&stream->buf_queue, stream, -+ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); -+ vdev->queue = &stream->buf_queue; -+ -+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); -+ if (ret < 0) { -+ v4l2_err(v4l2_dev, "video_register_device failed: %d\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void process_signal_change(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, -+ LINE_FLAG_INT_EN | -+ HDMIRX_DMA_IDLE_INT | -+ HDMIRX_LOCK_DISABLE_INT | -+ LAST_FRAME_AXI_UNFINISH_INT_EN | -+ FIFO_OVERFLOW_INT_EN | -+ FIFO_UNDERFLOW_INT_EN | -+ HDMIRX_AXI_ERROR_INT_EN, 0); -+ hdmirx_reset_dma(hdmirx_dev); -+ hdmirx_dev->got_timing = false; -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_res_change, -+ msecs_to_jiffies(50)); -+} -+ -+static void avpunit_0_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ if (status & (CED_DYN_CNT_CH2_IRQ | -+ CED_DYN_CNT_CH1_IRQ | -+ CED_DYN_CNT_CH0_IRQ)) { -+ process_signal_change(hdmirx_dev); -+ v4l2_dbg(2, debug, v4l2_dev, "%s: avp0_st:%#x\n", -+ __func__, status); -+ *handled = true; -+ } -+ -+ hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_FORCE, 0x0); -+} -+ -+static void avpunit_1_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ if (status & DEFRAMER_VSYNC_THR_REACHED_IRQ) { -+ v4l2_info(v4l2_dev, "Vertical Sync threshold reached interrupt %#x", status); -+ hdmirx_update_bits(hdmirx_dev, AVPUNIT_1_INT_MASK_N, -+ DEFRAMER_VSYNC_THR_REACHED_MASK_N, 0); -+ *handled = true; -+ } -+} -+ -+static void mainunit_0_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ v4l2_dbg(2, debug, v4l2_dev, "mu0_st:%#x\n", status); -+ if (status & TIMER_BASE_LOCKED_IRQ) { -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N, -+ TIMER_BASE_LOCKED_IRQ, 0); -+ complete(&hdmirx_dev->timer_base_lock); -+ *handled = true; -+ } -+ -+ if (status & TMDSQPCLK_OFF_CHG) { -+ process_signal_change(hdmirx_dev); -+ v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSQPCLK_OFF_CHG\n", __func__); -+ *handled = true; -+ } -+ -+ if (status & TMDSQPCLK_LOCKED_CHG) { -+ process_signal_change(hdmirx_dev); -+ v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSQPCLK_LOCKED_CHG\n", __func__); -+ *handled = true; -+ } -+ -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_FORCE, 0x0); -+} -+ -+static void mainunit_2_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ v4l2_dbg(2, debug, v4l2_dev, "mu2_st:%#x\n", status); -+ if (status & PHYCREG_CR_WRITE_DONE) { -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N, -+ PHYCREG_CR_WRITE_DONE, 0); -+ complete(&hdmirx_dev->cr_write_done); -+ *handled = true; -+ } -+ -+ if (status & TMDSVALID_STABLE_CHG) { -+ process_signal_change(hdmirx_dev); -+ v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSVALID_STABLE_CHG\n", __func__); -+ *handled = true; -+ } -+ -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_FORCE, 0x0); -+} -+ -+static void pkt_2_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ v4l2_dbg(2, debug, v4l2_dev, "%s: pk2_st:%#x\n", __func__, status); -+ if (status & PKTDEC_AVIIF_RCV_IRQ) { -+ hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N, -+ PKTDEC_AVIIF_RCV_IRQ, 0); -+ complete(&hdmirx_dev->avi_pkt_rcv); -+ v4l2_dbg(2, debug, v4l2_dev, "%s: AVIIF_RCV_IRQ\n", __func__); -+ *handled = true; -+ } -+ -+ hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff); -+} -+ -+static void scdc_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ v4l2_dbg(2, debug, v4l2_dev, "%s: scdc_st:%#x\n", __func__, status); -+ if (status & SCDCTMDSCCFG_CHG) { -+ hdmirx_tmds_clk_ratio_config(hdmirx_dev); -+ *handled = true; -+ } -+ -+ hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff); -+} -+ -+static irqreturn_t hdmirx_hdmi_irq_handler(int irq, void *dev_id) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_id; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct arm_smccc_res res; -+ u32 mu0_st, mu2_st, pk2_st, scdc_st, avp1_st, avp0_st; -+ u32 mu0_mask, mu2_mask, pk2_mask, scdc_mask, avp1_msk, avp0_msk; -+ bool handled = false; -+ -+ mu0_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_MASK_N); -+ mu2_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_MASK_N); -+ pk2_mask = hdmirx_readl(hdmirx_dev, PKT_2_INT_MASK_N); -+ scdc_mask = hdmirx_readl(hdmirx_dev, SCDC_INT_MASK_N); -+ mu0_st = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_STATUS); -+ mu2_st = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_STATUS); -+ pk2_st = hdmirx_readl(hdmirx_dev, PKT_2_INT_STATUS); -+ scdc_st = hdmirx_readl(hdmirx_dev, SCDC_INT_STATUS); -+ avp0_st = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_STATUS); -+ avp1_st = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_STATUS); -+ avp0_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_MASK_N); -+ avp1_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_MASK_N); -+ mu0_st &= mu0_mask; -+ mu2_st &= mu2_mask; -+ pk2_st &= pk2_mask; -+ avp1_st &= avp1_msk; -+ avp0_st &= avp0_msk; -+ scdc_st &= scdc_mask; -+ -+ if (avp0_st) -+ avpunit_0_int_handler(hdmirx_dev, avp0_st, &handled); -+ if (avp1_st) -+ avpunit_1_int_handler(hdmirx_dev, avp1_st, &handled); -+ if (mu0_st) -+ mainunit_0_int_handler(hdmirx_dev, mu0_st, &handled); -+ if (mu2_st) -+ mainunit_2_int_handler(hdmirx_dev, mu2_st, &handled); -+ if (pk2_st) -+ pkt_2_int_handler(hdmirx_dev, pk2_st, &handled); -+ if (scdc_st) -+ scdc_int_handler(hdmirx_dev, scdc_st, &handled); -+ -+ if (!handled) { -+ v4l2_dbg(2, debug, v4l2_dev, "%s: hdmi irq not handled", __func__); -+ v4l2_dbg(2, debug, v4l2_dev, -+ "avp0:%#x, avp1:%#x, mu0:%#x, mu2:%#x, pk2:%#x, scdc:%#x\n", -+ avp0_st, avp1_st, mu0_st, mu2_st, pk2_st, scdc_st); -+ } -+ -+ v4l2_dbg(2, debug, v4l2_dev, "%s: en_fiq", __func__); -+ arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN, -+ RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res); -+ -+ return handled ? IRQ_HANDLED : IRQ_NONE; -+} -+ -+static void hdmirx_vb_done(struct hdmirx_stream *stream, -+ struct vb2_v4l2_buffer *vb_done) -+{ -+ const struct v4l2_format_info *finfo = stream->out_finfo; -+ u32 i; -+ -+ /* Dequeue a filled buffer */ -+ for (i = 0; i < finfo->mem_planes; i++) { -+ vb2_set_plane_payload(&vb_done->vb2_buf, i, -+ stream->pixm.plane_fmt[i].sizeimage); -+ } -+ -+ vb_done->vb2_buf.timestamp = ktime_get_ns(); -+ vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE); -+} -+ -+static void dma_idle_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ bool *handled) -+{ -+ struct hdmirx_stream *stream = &hdmirx_dev->stream; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct v4l2_dv_timings timings = hdmirx_dev->timings; -+ struct v4l2_bt_timings *bt = &timings.bt; -+ struct vb2_v4l2_buffer *vb_done = NULL; -+ -+ if (!(stream->irq_stat) && !(stream->irq_stat & LINE_FLAG_INT_EN)) -+ v4l2_dbg(1, debug, v4l2_dev, -+ "%s: last time have no line_flag_irq\n", __func__); -+ -+ if (stream->line_flag_int_cnt <= FILTER_FRAME_CNT) -+ goto DMA_IDLE_OUT; -+ -+ if (bt->interlaced != V4L2_DV_INTERLACED || -+ !(stream->line_flag_int_cnt % 2)) { -+ if (stream->next_buf) { -+ if (stream->curr_buf) -+ vb_done = &stream->curr_buf->vb; -+ -+ if (vb_done) { -+ vb_done->vb2_buf.timestamp = ktime_get_ns(); -+ vb_done->sequence = stream->frame_idx; -+ hdmirx_vb_done(stream, vb_done); -+ stream->frame_idx++; -+ if (stream->frame_idx == 30) -+ v4l2_info(v4l2_dev, "rcv frames\n"); -+ } -+ -+ stream->curr_buf = NULL; -+ if (stream->next_buf) { -+ stream->curr_buf = stream->next_buf; -+ stream->next_buf = NULL; -+ } -+ } else { -+ v4l2_dbg(3, debug, v4l2_dev, -+ "%s: next_buf NULL, skip vb_done\n", __func__); -+ } -+ } -+ -+DMA_IDLE_OUT: -+ *handled = true; -+} -+ -+static void line_flag_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ bool *handled) -+{ -+ struct hdmirx_stream *stream = &hdmirx_dev->stream; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct v4l2_dv_timings timings = hdmirx_dev->timings; -+ struct v4l2_bt_timings *bt = &timings.bt; -+ u32 dma_cfg6; -+ -+ stream->line_flag_int_cnt++; -+ if (!(stream->irq_stat) && !(stream->irq_stat & HDMIRX_DMA_IDLE_INT)) -+ v4l2_dbg(1, debug, v4l2_dev, -+ "%s: last have no dma_idle_irq\n", __func__); -+ dma_cfg6 = hdmirx_readl(hdmirx_dev, DMA_CONFIG6); -+ if (!(dma_cfg6 & HDMIRX_DMA_EN)) { -+ v4l2_dbg(2, debug, v4l2_dev, "%s: dma not on\n", __func__); -+ goto LINE_FLAG_OUT; -+ } -+ -+ if (stream->line_flag_int_cnt <= FILTER_FRAME_CNT) -+ goto LINE_FLAG_OUT; -+ -+ if (bt->interlaced != V4L2_DV_INTERLACED || -+ !(stream->line_flag_int_cnt % 2)) { -+ if (!stream->next_buf) { -+ spin_lock(&stream->vbq_lock); -+ if (!list_empty(&stream->buf_head)) { -+ stream->next_buf = list_first_entry(&stream->buf_head, -+ struct hdmirx_buffer, -+ queue); -+ list_del(&stream->next_buf->queue); -+ } else { -+ stream->next_buf = NULL; -+ } -+ spin_unlock(&stream->vbq_lock); -+ -+ if (stream->next_buf) { -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG2, -+ stream->next_buf->buff_addr[HDMIRX_PLANE_Y]); -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG3, -+ stream->next_buf->buff_addr[HDMIRX_PLANE_CBCR]); -+ } else { -+ v4l2_dbg(3, debug, v4l2_dev, -+ "%s: no buffer is available\n", __func__); -+ } -+ } -+ } else { -+ v4l2_dbg(3, debug, v4l2_dev, "%s: interlace:%d, line_flag_int_cnt:%d\n", -+ __func__, bt->interlaced, stream->line_flag_int_cnt); -+ } -+ -+LINE_FLAG_OUT: -+ *handled = true; -+} -+ -+static irqreturn_t hdmirx_dma_irq_handler(int irq, void *dev_id) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_id; -+ struct hdmirx_stream *stream = &hdmirx_dev->stream; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 dma_stat1, dma_stat13; -+ bool handled = false; -+ -+ dma_stat1 = hdmirx_readl(hdmirx_dev, DMA_STATUS1); -+ dma_stat13 = hdmirx_readl(hdmirx_dev, DMA_STATUS13); -+ v4l2_dbg(3, debug, v4l2_dev, "dma_irq st1:%#x, st13:%d\n", -+ dma_stat1, dma_stat13); -+ -+ if (READ_ONCE(stream->stopping)) { -+ v4l2_dbg(1, debug, v4l2_dev, "%s: stop stream\n", __func__); -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, -+ LINE_FLAG_INT_EN | -+ HDMIRX_DMA_IDLE_INT | -+ HDMIRX_LOCK_DISABLE_INT | -+ LAST_FRAME_AXI_UNFINISH_INT_EN | -+ FIFO_OVERFLOW_INT_EN | -+ FIFO_UNDERFLOW_INT_EN | -+ HDMIRX_AXI_ERROR_INT_EN, 0); -+ WRITE_ONCE(stream->stopping, false); -+ wake_up(&stream->wq_stopped); -+ return IRQ_HANDLED; -+ } -+ -+ if (dma_stat1 & HDMIRX_DMA_IDLE_INT) -+ dma_idle_int_handler(hdmirx_dev, &handled); -+ -+ if (dma_stat1 & LINE_FLAG_INT_EN) -+ line_flag_int_handler(hdmirx_dev, &handled); -+ -+ if (!handled) -+ v4l2_dbg(3, debug, v4l2_dev, -+ "%s: dma irq not handled, dma_stat1:%#x\n", -+ __func__, dma_stat1); -+ -+ stream->irq_stat = dma_stat1; -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff); -+ -+ return IRQ_HANDLED; -+} -+ -+static void hdmirx_plugin(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct arm_smccc_res res; -+ int ret; -+ -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_heartbeat, -+ msecs_to_jiffies(10)); -+ arm_smccc_smc(SIP_WDT_CFG, WDT_START, 0, 0, 0, 0, 0, 0, &res); -+ hdmirx_submodule_init(hdmirx_dev); -+ hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, -+ POWERPROVIDED); -+ hdmirx_hpd_ctrl(hdmirx_dev, true); -+ hdmirx_phy_config(hdmirx_dev); -+ ret = hdmirx_wait_lock_and_get_timing(hdmirx_dev); -+ if (ret) { -+ hdmirx_plugout(hdmirx_dev); -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(200)); -+ return; -+ } -+ hdmirx_dma_config(hdmirx_dev); -+ hdmirx_interrupts_setup(hdmirx_dev, true); -+} -+ -+static void hdmirx_delayed_work_hotplug(struct work_struct *work) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev; -+ bool plugin; -+ -+ hdmirx_dev = container_of(work, struct snps_hdmirx_dev, -+ delayed_work_hotplug.work); -+ -+ mutex_lock(&hdmirx_dev->work_lock); -+ hdmirx_dev->got_timing = false; -+ plugin = tx_5v_power_present(hdmirx_dev); -+ v4l2_ctrl_s_ctrl(hdmirx_dev->detect_tx_5v_ctrl, plugin); -+ v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: plugin:%d\n", -+ __func__, plugin); -+ -+ if (plugin) -+ hdmirx_plugin(hdmirx_dev); -+ else -+ hdmirx_plugout(hdmirx_dev); -+ -+ mutex_unlock(&hdmirx_dev->work_lock); -+} -+ -+static void hdmirx_delayed_work_res_change(struct work_struct *work) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev; -+ bool plugin; -+ -+ hdmirx_dev = container_of(work, struct snps_hdmirx_dev, -+ delayed_work_res_change.work); -+ -+ mutex_lock(&hdmirx_dev->work_lock); -+ plugin = tx_5v_power_present(hdmirx_dev); -+ v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: plugin:%d\n", -+ __func__, plugin); -+ if (plugin) { -+ hdmirx_interrupts_setup(hdmirx_dev, false); -+ hdmirx_submodule_init(hdmirx_dev); -+ hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, -+ POWERPROVIDED); -+ hdmirx_hpd_ctrl(hdmirx_dev, true); -+ hdmirx_phy_config(hdmirx_dev); -+ -+ if (hdmirx_wait_lock_and_get_timing(hdmirx_dev)) { -+ hdmirx_plugout(hdmirx_dev); -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(200)); -+ } else { -+ hdmirx_dma_config(hdmirx_dev); -+ hdmirx_interrupts_setup(hdmirx_dev, true); -+ } -+ } -+ mutex_unlock(&hdmirx_dev->work_lock); -+} -+ -+static void hdmirx_delayed_work_heartbeat(struct work_struct *work) -+{ -+ struct delayed_work *dwork = to_delayed_work(work); -+ struct snps_hdmirx_dev *hdmirx_dev = container_of(dwork, -+ struct snps_hdmirx_dev, -+ delayed_work_heartbeat); -+ -+ queue_work(system_highpri_wq, &hdmirx_dev->work_wdt_config); -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_heartbeat, HZ); -+} -+ -+static void hdmirx_work_wdt_config(struct work_struct *work) -+{ -+ struct arm_smccc_res res; -+ struct snps_hdmirx_dev *hdmirx_dev = container_of(work, -+ struct snps_hdmirx_dev, -+ work_wdt_config); -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ arm_smccc_smc(SIP_WDT_CFG, WDT_PING, 0, 0, 0, 0, 0, 0, &res); -+ v4l2_dbg(3, debug, v4l2_dev, "hb\n"); -+} -+ -+static irqreturn_t hdmirx_5v_det_irq_handler(int irq, void *dev_id) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_id; -+ u32 val; -+ -+ val = gpiod_get_value(hdmirx_dev->detect_5v_gpio); -+ v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: 5v:%d\n", __func__, val); -+ -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(10)); -+ -+ return IRQ_HANDLED; -+} -+ -+static const struct hdmirx_cec_ops hdmirx_cec_ops = { -+ .write = hdmirx_writel, -+ .read = hdmirx_readl, -+}; -+ -+static int hdmirx_parse_dt(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ int ret; -+ -+ hdmirx_dev->num_clks = devm_clk_bulk_get_all(dev, &hdmirx_dev->clks); -+ if (hdmirx_dev->num_clks < 1) -+ return -ENODEV; -+ -+ hdmirx_dev->resets[HDMIRX_RST_A].id = "axi"; -+ hdmirx_dev->resets[HDMIRX_RST_P].id = "apb"; -+ hdmirx_dev->resets[HDMIRX_RST_REF].id = "ref"; -+ hdmirx_dev->resets[HDMIRX_RST_BIU].id = "biu"; -+ -+ ret = devm_reset_control_bulk_get_exclusive(dev, HDMIRX_NUM_RST, -+ hdmirx_dev->resets); -+ if (ret < 0) { -+ dev_err(dev, "failed to get reset controls\n"); -+ return ret; -+ } -+ -+ hdmirx_dev->detect_5v_gpio = -+ devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); -+ -+ if (IS_ERR(hdmirx_dev->detect_5v_gpio)) { -+ dev_err(dev, "failed to get hdmirx hot plug detection gpio\n"); -+ return PTR_ERR(hdmirx_dev->detect_5v_gpio); -+ } -+ -+ hdmirx_dev->grf = syscon_regmap_lookup_by_phandle(dev->of_node, -+ "rockchip,grf"); -+ if (IS_ERR(hdmirx_dev->grf)) { -+ dev_err(dev, "failed to get rockchip,grf\n"); -+ return PTR_ERR(hdmirx_dev->grf); -+ } -+ -+ hdmirx_dev->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, -+ "rockchip,vo1-grf"); -+ if (IS_ERR(hdmirx_dev->vo1_grf)) { -+ dev_err(dev, "failed to get rockchip,vo1-grf\n"); -+ return PTR_ERR(hdmirx_dev->vo1_grf); -+ } -+ -+ hdmirx_dev->hpd_trigger_level = !device_property_read_bool(dev, "hpd-is-active-low"); -+ -+ ret = of_reserved_mem_device_init(dev); -+ if (ret) -+ dev_warn(dev, "No reserved memory for HDMIRX, use default CMA\n"); -+ -+ return 0; -+} -+ -+static void hdmirx_disable_all_interrupts(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, MAINUNIT_1_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, AVPUNIT_1_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, PKT_0_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, PKT_1_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, PKT_2_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, SCDC_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, CEC_INT_MASK_N, 0); -+ -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_1_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_1_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, PKT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, PKT_1_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, HDCP_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, HDCP_1_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, CEC_INT_CLEAR, 0xffffffff); -+} -+ -+static int hdmirx_init(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET | PHY_PDDQ, 0); -+ -+ regmap_write(hdmirx_dev->vo1_grf, VO1_GRF_VO1_CON2, -+ (HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) | -+ ((HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) << 16)); -+ /* -+ * Some interrupts are enabled by default, so we disable -+ * all interrupts and clear interrupts status first. -+ */ -+ hdmirx_disable_all_interrupts(hdmirx_dev); -+ -+ return 0; -+} -+ -+static void hdmirx_load_default_edid(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ int ret; -+ struct v4l2_edid def_edid; -+ -+ hdmirx_hpd_ctrl(hdmirx_dev, false); -+ -+ /* disable hpd and write edid */ -+ def_edid.pad = 0; -+ def_edid.start_block = 0; -+ def_edid.blocks = EDID_NUM_BLOCKS_MAX; -+ -+ if (IS_ENABLED(CONFIG_HDMIRX_LOAD_DEFAULT_EDID)) -+ def_edid.edid = edid_init_data_340M; -+ else -+ def_edid.edid = hdmirx_dev->edid; -+ -+ ret = hdmirx_write_edid(hdmirx_dev, &def_edid, true); -+ if (ret) -+ dev_err(hdmirx_dev->dev, "%s: write edid failed\n", __func__); -+} -+ -+static void hdmirx_disable_irq(struct device *dev) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev); -+ struct arm_smccc_res res; -+ -+ disable_irq(hdmirx_dev->hdmi_irq); -+ disable_irq(hdmirx_dev->dma_irq); -+ disable_irq(hdmirx_dev->det_irq); -+ -+ arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_DIS, -+ RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res); -+ -+ cancel_delayed_work_sync(&hdmirx_dev->delayed_work_hotplug); -+ cancel_delayed_work_sync(&hdmirx_dev->delayed_work_res_change); -+ cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat); -+ flush_work(&hdmirx_dev->work_wdt_config); -+ -+ arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res); -+} -+ -+static int hdmirx_disable(struct device *dev) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev); -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ clk_bulk_disable_unprepare(hdmirx_dev->num_clks, hdmirx_dev->clks); -+ -+ v4l2_dbg(2, debug, v4l2_dev, "%s: suspend\n", __func__); -+ -+ return pinctrl_pm_select_sleep_state(dev); -+} -+ -+static void hdmirx_enable_irq(struct device *dev) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev); -+ struct arm_smccc_res res; -+ -+ enable_irq(hdmirx_dev->hdmi_irq); -+ enable_irq(hdmirx_dev->dma_irq); -+ enable_irq(hdmirx_dev->det_irq); -+ -+ arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN, -+ RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res); -+ -+ queue_delayed_work(system_unbound_wq, &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(20)); -+} -+ -+static int hdmirx_enable(struct device *dev) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev); -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ int ret; -+ -+ v4l2_dbg(2, debug, v4l2_dev, "%s: resume\n", __func__); -+ ret = pinctrl_pm_select_default_state(dev); -+ if (ret < 0) -+ return ret; -+ -+ ret = clk_bulk_prepare_enable(hdmirx_dev->num_clks, hdmirx_dev->clks); -+ if (ret) { -+ dev_err(dev, "failed to enable hdmirx bulk clks: %d\n", ret); -+ return ret; -+ } -+ -+ reset_control_bulk_assert(HDMIRX_NUM_RST, hdmirx_dev->resets); -+ usleep_range(150, 160); -+ reset_control_bulk_deassert(HDMIRX_NUM_RST, hdmirx_dev->resets); -+ usleep_range(150, 160); -+ -+ return 0; -+} -+ -+static int hdmirx_suspend(struct device *dev) -+{ -+ hdmirx_disable_irq(dev); -+ -+ return hdmirx_disable(dev); -+} -+ -+static int hdmirx_resume(struct device *dev) -+{ -+ int ret = hdmirx_enable(dev); -+ -+ if (ret) -+ return ret; -+ -+ hdmirx_enable_irq(dev); -+ -+ return 0; -+} -+ -+static const struct dev_pm_ops snps_hdmirx_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(hdmirx_suspend, hdmirx_resume) -+}; -+ -+static int hdmirx_setup_irq(struct snps_hdmirx_dev *hdmirx_dev, -+ struct platform_device *pdev) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ int ret, irq; -+ -+ irq = platform_get_irq_byname(pdev, "hdmi"); -+ if (irq < 0) { -+ dev_err_probe(dev, irq, "failed to get hdmi irq\n"); -+ return irq; -+ } -+ -+ irq_set_status_flags(irq, IRQ_NOAUTOEN); -+ -+ hdmirx_dev->hdmi_irq = irq; -+ ret = devm_request_irq(dev, irq, hdmirx_hdmi_irq_handler, 0, -+ "rk_hdmirx-hdmi", hdmirx_dev); -+ if (ret) { -+ dev_err_probe(dev, ret, "failed to request hdmi irq\n"); -+ return ret; -+ } -+ -+ irq = platform_get_irq_byname(pdev, "dma"); -+ if (irq < 0) { -+ dev_err_probe(dev, irq, "failed to get dma irq\n"); -+ return irq; -+ } -+ -+ irq_set_status_flags(irq, IRQ_NOAUTOEN); -+ -+ hdmirx_dev->dma_irq = irq; -+ ret = devm_request_threaded_irq(dev, irq, NULL, hdmirx_dma_irq_handler, -+ IRQF_ONESHOT, "rk_hdmirx-dma", -+ hdmirx_dev); -+ if (ret) { -+ dev_err_probe(dev, ret, "failed to request dma irq\n"); -+ return ret; -+ } -+ -+ irq = gpiod_to_irq(hdmirx_dev->detect_5v_gpio); -+ if (irq < 0) { -+ dev_err_probe(dev, irq, "failed to get hdmirx-5v irq\n"); -+ return irq; -+ } -+ -+ irq_set_status_flags(irq, IRQ_NOAUTOEN); -+ -+ hdmirx_dev->det_irq = irq; -+ ret = devm_request_irq(dev, irq, hdmirx_5v_det_irq_handler, -+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, -+ "rk_hdmirx-5v", hdmirx_dev); -+ if (ret) { -+ dev_err_probe(dev, ret, "failed to request hdmirx-5v irq\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int hdmirx_register_cec(struct snps_hdmirx_dev *hdmirx_dev, -+ struct platform_device *pdev) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ struct hdmirx_cec_data cec_data; -+ int irq; -+ -+ irq = platform_get_irq_byname(pdev, "cec"); -+ if (irq < 0) { -+ dev_err_probe(dev, irq, "failed to get cec irq\n"); -+ return irq; -+ } -+ -+ hdmirx_dev->cec_notifier = cec_notifier_conn_register(dev, NULL, NULL); -+ if (!hdmirx_dev->cec_notifier) -+ return -EINVAL; -+ -+ cec_data.hdmirx = hdmirx_dev; -+ cec_data.dev = hdmirx_dev->dev; -+ cec_data.ops = &hdmirx_cec_ops; -+ cec_data.irq = irq; -+ -+ hdmirx_dev->cec = snps_hdmirx_cec_register(&cec_data); -+ if (!hdmirx_dev->cec) { -+ cec_notifier_conn_unregister(hdmirx_dev->cec_notifier); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int hdmirx_probe(struct platform_device *pdev) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev; -+ struct device *dev = &pdev->dev; -+ struct v4l2_ctrl_handler *hdl; -+ struct hdmirx_stream *stream; -+ struct v4l2_device *v4l2_dev; -+ int ret; -+ -+ hdmirx_dev = devm_kzalloc(dev, sizeof(*hdmirx_dev), GFP_KERNEL); -+ if (!hdmirx_dev) -+ return -ENOMEM; -+ -+ ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); -+ if (ret) -+ return ret; -+ -+ hdmirx_dev->dev = dev; -+ dev_set_drvdata(dev, hdmirx_dev); -+ -+ ret = hdmirx_parse_dt(hdmirx_dev); -+ if (ret) -+ return ret; -+ -+ ret = hdmirx_setup_irq(hdmirx_dev, pdev); -+ if (ret) -+ return ret; -+ -+ hdmirx_dev->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(hdmirx_dev->regs)) -+ return dev_err_probe(dev, PTR_ERR(hdmirx_dev->regs), -+ "failed to remap regs resource\n"); -+ -+ mutex_init(&hdmirx_dev->stream_lock); -+ mutex_init(&hdmirx_dev->work_lock); -+ spin_lock_init(&hdmirx_dev->rst_lock); -+ -+ init_completion(&hdmirx_dev->cr_write_done); -+ init_completion(&hdmirx_dev->timer_base_lock); -+ init_completion(&hdmirx_dev->avi_pkt_rcv); -+ -+ INIT_WORK(&hdmirx_dev->work_wdt_config, hdmirx_work_wdt_config); -+ INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_hotplug, -+ hdmirx_delayed_work_hotplug); -+ INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_res_change, -+ hdmirx_delayed_work_res_change); -+ INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_heartbeat, -+ hdmirx_delayed_work_heartbeat); -+ -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24; -+ hdmirx_dev->timings = cea640x480; -+ -+ hdmirx_enable(dev); -+ hdmirx_init(hdmirx_dev); -+ -+ v4l2_dev = &hdmirx_dev->v4l2_dev; -+ strscpy(v4l2_dev->name, dev_name(dev), sizeof(v4l2_dev->name)); -+ -+ hdl = &hdmirx_dev->hdl; -+ v4l2_ctrl_handler_init(hdl, 1); -+ -+ hdmirx_dev->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, -+ V4L2_CID_DV_RX_POWER_PRESENT, -+ 0, 1, 0, 0); -+ -+ hdmirx_dev->rgb_range = v4l2_ctrl_new_std_menu(hdl, 0, -+ V4L2_CID_DV_RX_RGB_RANGE, -+ V4L2_DV_RGB_RANGE_FULL, 0, -+ V4L2_DV_RGB_RANGE_AUTO); -+ -+ hdmirx_dev->rgb_range->flags |= V4L2_CTRL_FLAG_READ_ONLY; -+ -+ if (hdl->error) { -+ dev_err(dev, "v4l2 ctrl handler init failed\n"); -+ ret = hdl->error; -+ goto err_pm; -+ } -+ hdmirx_dev->v4l2_dev.ctrl_handler = hdl; -+ -+ ret = v4l2_device_register(dev, &hdmirx_dev->v4l2_dev); -+ if (ret < 0) { -+ dev_err(dev, "register v4l2 device failed\n"); -+ goto err_hdl; -+ } -+ -+ stream = &hdmirx_dev->stream; -+ stream->hdmirx_dev = hdmirx_dev; -+ ret = hdmirx_register_stream_vdev(stream); -+ if (ret < 0) { -+ dev_err(dev, "register video device failed\n"); -+ goto err_unreg_v4l2_dev; -+ } -+ -+ ret = hdmirx_register_cec(hdmirx_dev, pdev); -+ if (ret) -+ goto err_unreg_video_dev; -+ -+ hdmirx_load_default_edid(hdmirx_dev); -+ -+ hdmirx_enable_irq(dev); -+ -+ return 0; -+ -+err_unreg_video_dev: -+ video_unregister_device(&hdmirx_dev->stream.vdev); -+err_unreg_v4l2_dev: -+ v4l2_device_unregister(&hdmirx_dev->v4l2_dev); -+err_hdl: -+ v4l2_ctrl_handler_free(&hdmirx_dev->hdl); -+err_pm: -+ hdmirx_disable(dev); -+ -+ return ret; -+} -+ -+static void hdmirx_remove(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev); -+ -+ snps_hdmirx_cec_unregister(hdmirx_dev->cec); -+ cec_notifier_conn_unregister(hdmirx_dev->cec_notifier); -+ -+ hdmirx_disable_irq(dev); -+ -+ video_unregister_device(&hdmirx_dev->stream.vdev); -+ v4l2_ctrl_handler_free(&hdmirx_dev->hdl); -+ v4l2_device_unregister(&hdmirx_dev->v4l2_dev); -+ -+ hdmirx_disable(dev); -+ -+ reset_control_bulk_assert(HDMIRX_NUM_RST, hdmirx_dev->resets); -+ -+ of_reserved_mem_device_release(dev); -+} -+ -+static const struct of_device_id hdmirx_id[] = { -+ { .compatible = "rockchip,rk3588-hdmirx-ctrler" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, hdmirx_id); -+ -+static struct platform_driver hdmirx_driver = { -+ .probe = hdmirx_probe, -+ .remove = hdmirx_remove, -+ .driver = { -+ .name = "snps_hdmirx", -+ .of_match_table = hdmirx_id, -+ .pm = &snps_hdmirx_pm_ops, -+ } -+}; -+module_platform_driver(hdmirx_driver); -+ -+MODULE_DESCRIPTION("Rockchip HDMI Receiver Driver"); -+MODULE_AUTHOR("Dingxian Wen "); -+MODULE_AUTHOR("Shreeya Patel "); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h -@@ -0,0 +1,394 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. -+ * -+ * Author: Dingxian Wen -+ */ -+ -+#ifndef DW_HDMIRX_H -+#define DW_HDMIRX_H -+ -+#include -+ -+#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) -+#define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) -+ -+/* SYS_GRF */ -+#define SYS_GRF_SOC_CON1 0x0304 -+#define HDMIRXPHY_SRAM_EXT_LD_DONE BIT(1) -+#define HDMIRXPHY_SRAM_BYPASS BIT(0) -+#define SYS_GRF_SOC_STATUS1 0x0384 -+#define HDMIRXPHY_SRAM_INIT_DONE BIT(10) -+#define SYS_GRF_CHIP_ID 0x0600 -+ -+/* VO1_GRF */ -+#define VO1_GRF_VO1_CON2 0x0008 -+#define HDMIRX_SDAIN_MSK BIT(2) -+#define HDMIRX_SCLIN_MSK BIT(1) -+ -+/* HDMIRX PHY */ -+#define SUP_DIG_ANA_CREGS_SUP_ANA_NC 0x004f -+ -+#define LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f -+#define LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f -+#define LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f -+#define LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f -+#define ASIC_ACK_OVRD_EN BIT(1) -+#define ASIC_ACK BIT(0) -+ -+#define LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x104a -+#define LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a -+#define LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a -+#define LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x134a -+#define FREQ_TUNE_START_VAL_MASK GENMASK(9, 0) -+#define FREQ_TUNE_START_VAL(x) UPDATE(x, 9, 0) -+ -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG 0x20c4 -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM 0x20c7 -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG 0x20e9 -+#define CDR_SETTING_BOUNDARY_3_DEFAULT 0x52da -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG 0x20ea -+#define CDR_SETTING_BOUNDARY_4_DEFAULT 0x43cd -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG 0x20eb -+#define CDR_SETTING_BOUNDARY_5_DEFAULT 0x35b3 -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG 0x20fb -+#define CDR_SETTING_BOUNDARY_6_DEFAULT 0x2799 -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG 0x20fc -+#define CDR_SETTING_BOUNDARY_7_DEFAULT 0x1b65 -+ -+#define RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e -+#define RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e -+#define RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e -+#define RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e -+#define PCS_ACK_WRITE_SELECT BIT(14) -+#define PCS_EN_CTL BIT(1) -+#define PCS_ACK BIT(0) -+ -+#define RAWLANE0_DIG_AON_FAST_FLAGS 0x305c -+#define RAWLANE1_DIG_AON_FAST_FLAGS 0x315c -+#define RAWLANE2_DIG_AON_FAST_FLAGS 0x325c -+#define RAWLANE3_DIG_AON_FAST_FLAGS 0x335c -+ -+/* HDMIRX Ctrler */ -+#define GLOBAL_SWRESET_REQUEST 0x0020 -+#define DATAPATH_SWRESETREQ BIT(12) -+#define GLOBAL_SWENABLE 0x0024 -+#define PHYCTRL_ENABLE BIT(21) -+#define CEC_ENABLE BIT(16) -+#define TMDS_ENABLE BIT(13) -+#define DATAPATH_ENABLE BIT(12) -+#define PKTFIFO_ENABLE BIT(11) -+#define AVPUNIT_ENABLE BIT(8) -+#define MAIN_ENABLE BIT(0) -+#define GLOBAL_TIMER_REF_BASE 0x0028 -+#define CORE_CONFIG 0x0050 -+#define CMU_CONFIG0 0x0060 -+#define TMDSQPCLK_STABLE_FREQ_MARGIN_MASK GENMASK(30, 16) -+#define TMDSQPCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 30, 16) -+#define AUDCLK_STABLE_FREQ_MARGIN_MASK GENMASK(11, 9) -+#define AUDCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 11, 9) -+#define CMU_STATUS 0x007c -+#define TMDSQPCLK_LOCKED_ST BIT(4) -+#define CMU_TMDSQPCLK_FREQ 0x0084 -+#define PHY_CONFIG 0x00c0 -+#define LDO_AFE_PROG_MASK GENMASK(24, 23) -+#define LDO_AFE_PROG(x) UPDATE(x, 24, 23) -+#define LDO_PWRDN BIT(21) -+#define TMDS_CLOCK_RATIO BIT(16) -+#define RXDATA_WIDTH BIT(15) -+#define REFFREQ_SEL_MASK GENMASK(11, 9) -+#define REFFREQ_SEL(x) UPDATE(x, 11, 9) -+#define HDMI_DISABLE BIT(8) -+#define PHY_PDDQ BIT(1) -+#define PHY_RESET BIT(0) -+#define PHY_STATUS 0x00c8 -+#define HDMI_DISABLE_ACK BIT(1) -+#define PDDQ_ACK BIT(0) -+#define PHYCREG_CONFIG0 0x00e0 -+#define PHYCREG_CR_PARA_SELECTION_MODE_MASK GENMASK(1, 0) -+#define PHYCREG_CR_PARA_SELECTION_MODE(x) UPDATE(x, 1, 0) -+#define PHYCREG_CONFIG1 0x00e4 -+#define PHYCREG_CONFIG2 0x00e8 -+#define PHYCREG_CONFIG3 0x00ec -+#define PHYCREG_CONTROL 0x00f0 -+#define PHYCREG_CR_PARA_WRITE_P BIT(1) -+#define PHYCREG_CR_PARA_READ_P BIT(0) -+#define PHYCREG_STATUS 0x00f4 -+ -+#define MAINUNIT_STATUS 0x0150 -+#define TMDSVALID_STABLE_ST BIT(1) -+#define DESCRAND_EN_CONTROL 0x0210 -+#define SCRAMB_EN_SEL_QST_MASK GENMASK(1, 0) -+#define SCRAMB_EN_SEL_QST(x) UPDATE(x, 1, 0) -+#define DESCRAND_SYNC_CONTROL 0x0214 -+#define RECOVER_UNSYNC_STREAM_QST BIT(0) -+#define DESCRAND_SYNC_SEQ_CONFIG 0x022c -+#define DESCRAND_SYNC_SEQ_ERR_CNT_EN BIT(0) -+#define DESCRAND_SYNC_SEQ_STATUS 0x0234 -+#define DEFRAMER_CONFIG0 0x0270 -+#define VS_CNT_THR_QST_MASK GENMASK(27, 20) -+#define VS_CNT_THR_QST(x) UPDATE(x, 27, 20) -+#define HS_POL_QST_MASK GENMASK(19, 18) -+#define HS_POL_QST(x) UPDATE(x, 19, 18) -+#define VS_POL_QST_MASK GENMASK(17, 16) -+#define VS_POL_QST(x) UPDATE(x, 17, 16) -+#define VS_REMAPFILTER_EN_QST BIT(8) -+#define VS_FILTER_ORDER_QST_MASK GENMASK(1, 0) -+#define VS_FILTER_ORDER_QST(x) UPDATE(x, 1, 0) -+#define DEFRAMER_VSYNC_CNT_CLEAR 0x0278 -+#define VSYNC_CNT_CLR_P BIT(0) -+#define DEFRAMER_STATUS 0x027c -+#define OPMODE_STS_MASK GENMASK(6, 4) -+#define I2C_SLAVE_CONFIG1 0x0164 -+#define I2C_SDA_OUT_HOLD_VALUE_QST_MASK GENMASK(15, 8) -+#define I2C_SDA_OUT_HOLD_VALUE_QST(x) UPDATE(x, 15, 8) -+#define I2C_SDA_IN_HOLD_VALUE_QST_MASK GENMASK(7, 0) -+#define I2C_SDA_IN_HOLD_VALUE_QST(x) UPDATE(x, 7, 0) -+#define OPMODE_STS_MASK GENMASK(6, 4) -+#define REPEATER_QST BIT(28) -+#define FASTREAUTH_QST BIT(27) -+#define FEATURES_1DOT1_QST BIT(26) -+#define FASTI2C_QST BIT(25) -+#define EESS_CTL_THR_QST_MASK GENMASK(19, 16) -+#define EESS_CTL_THR_QST(x) UPDATE(x, 19, 16) -+#define OESS_CTL3_THR_QST_MASK GENMASK(11, 8) -+#define OESS_CTL3_THR_QST(x) UPDATE(x, 11, 8) -+#define EESS_OESS_SEL_QST_MASK GENMASK(5, 4) -+#define EESS_OESS_SEL_QST(x) UPDATE(x, 5, 4) -+#define KEY_DECRYPT_EN_QST BIT(0) -+#define KEY_DECRYPT_SEED_QST_MASK GENMASK(15, 0) -+#define KEY_DECRYPT_SEED_QST(x) UPDATE(x, 15, 0) -+#define HDCP_INT_CLEAR 0x50d8 -+#define HDCP_1_INT_CLEAR 0x50e8 -+#define HDCP2_CONFIG 0x02f0 -+#define HDCP2_SWITCH_OVR_VALUE BIT(2) -+#define HDCP2_SWITCH_OVR_EN BIT(1) -+ -+#define VIDEO_CONFIG2 0x042c -+#define VPROC_VSYNC_POL_OVR_VALUE BIT(19) -+#define VPROC_VSYNC_POL_OVR_EN BIT(18) -+#define VPROC_HSYNC_POL_OVR_VALUE BIT(17) -+#define VPROC_HSYNC_POL_OVR_EN BIT(16) -+#define VPROC_FMT_OVR_VALUE_MASK GENMASK(6, 4) -+#define VPROC_FMT_OVR_VALUE(x) UPDATE(x, 6, 4) -+#define VPROC_FMT_OVR_EN BIT(0) -+ -+#define AFIFO_FILL_RESTART BIT(0) -+#define AFIFO_INIT_P BIT(0) -+#define AFIFO_THR_LOW_QST_MASK GENMASK(25, 16) -+#define AFIFO_THR_LOW_QST(x) UPDATE(x, 25, 16) -+#define AFIFO_THR_HIGH_QST_MASK GENMASK(9, 0) -+#define AFIFO_THR_HIGH_QST(x) UPDATE(x, 9, 0) -+#define AFIFO_THR_MUTE_LOW_QST_MASK GENMASK(25, 16) -+#define AFIFO_THR_MUTE_LOW_QST(x) UPDATE(x, 25, 16) -+#define AFIFO_THR_MUTE_HIGH_QST_MASK GENMASK(9, 0) -+#define AFIFO_THR_MUTE_HIGH_QST(x) UPDATE(x, 9, 0) -+ -+#define AFIFO_UNDERFLOW_ST BIT(25) -+#define AFIFO_OVERFLOW_ST BIT(24) -+ -+#define SPEAKER_ALLOC_OVR_EN BIT(16) -+#define I2S_BPCUV_EN BIT(4) -+#define SPDIF_EN BIT(2) -+#define I2S_EN BIT(1) -+#define AFIFO_THR_PASS_DEMUTEMASK_N BIT(24) -+#define AVMUTE_DEMUTEMASK_N BIT(16) -+#define AFIFO_THR_MUTE_LOW_MUTEMASK_N BIT(9) -+#define AFIFO_THR_MUTE_HIGH_MUTEMASK_N BIT(8) -+#define AVMUTE_MUTEMASK_N BIT(0) -+#define SCDC_CONFIG 0x0580 -+#define HPDLOW BIT(1) -+#define POWERPROVIDED BIT(0) -+#define SCDC_REGBANK_STATUS1 0x058c -+#define SCDC_TMDSBITCLKRATIO BIT(1) -+#define SCDC_REGBANK_STATUS3 0x0594 -+#define SCDC_REGBANK_CONFIG0 0x05c0 -+#define SCDC_SINKVERSION_QST_MASK GENMASK(7, 0) -+#define SCDC_SINKVERSION_QST(x) UPDATE(x, 7, 0) -+#define AGEN_LAYOUT BIT(4) -+#define AGEN_SPEAKER_ALLOC GENMASK(15, 8) -+ -+#define CED_CONFIG 0x0760 -+#define CED_VIDDATACHECKEN_QST BIT(27) -+#define CED_DATAISCHECKEN_QST BIT(26) -+#define CED_GBCHECKEN_QST BIT(25) -+#define CED_CTRLCHECKEN_QST BIT(24) -+#define CED_CHLOCKMAXER_QST_MASK GENMASK(14, 0) -+#define CED_CHLOCKMAXER_QST(x) UPDATE(x, 14, 0) -+#define CED_DYN_CONFIG 0x0768 -+#define CED_DYN_CONTROL 0x076c -+#define PKTEX_BCH_ERRFILT_CONFIG 0x07c4 -+#define PKTEX_CHKSUM_ERRFILT_CONFIG 0x07c8 -+ -+#define PKTDEC_ACR_PH2_1 0x1100 -+#define PKTDEC_ACR_PB3_0 0x1104 -+#define PKTDEC_ACR_PB7_4 0x1108 -+#define PKTDEC_AVIIF_PH2_1 0x1200 -+#define PKTDEC_AVIIF_PB3_0 0x1204 -+#define PKTDEC_AVIIF_PB7_4 0x1208 -+#define VIC_VAL_MASK GENMASK(6, 0) -+#define PKTDEC_AVIIF_PB11_8 0x120c -+#define PKTDEC_AVIIF_PB15_12 0x1210 -+#define PKTDEC_AVIIF_PB19_16 0x1214 -+#define PKTDEC_AVIIF_PB23_20 0x1218 -+#define PKTDEC_AVIIF_PB27_24 0x121c -+ -+#define PKTFIFO_CONFIG 0x1500 -+#define PKTFIFO_STORE_FILT_CONFIG 0x1504 -+#define PKTFIFO_THR_CONFIG0 0x1508 -+#define PKTFIFO_THR_CONFIG1 0x150c -+#define PKTFIFO_CONTROL 0x1510 -+ -+#define VMON_STATUS1 0x1580 -+#define VMON_STATUS2 0x1584 -+#define VMON_STATUS3 0x1588 -+#define VMON_STATUS4 0x158c -+#define VMON_STATUS5 0x1590 -+#define VMON_STATUS6 0x1594 -+#define VMON_STATUS7 0x1598 -+#define VMON_ILACE_DETECT BIT(4) -+ -+#define CEC_TX_CONTROL 0x2000 -+#define CEC_STATUS 0x2004 -+#define CEC_CONFIG 0x2008 -+#define RX_AUTO_DRIVE_ACKNOWLEDGE BIT(9) -+#define CEC_ADDR 0x200c -+#define CEC_TX_COUNT 0x2020 -+#define CEC_TX_DATA3_0 0x2024 -+#define CEC_RX_COUNT_STATUS 0x2040 -+#define CEC_RX_DATA3_0 0x2044 -+#define CEC_LOCK_CONTROL 0x2054 -+#define CEC_RXQUAL_BITTIME_CONFIG 0x2060 -+#define CEC_RX_BITTIME_CONFIG 0x2064 -+#define CEC_TX_BITTIME_CONFIG 0x2068 -+ -+#define DMA_CONFIG1 0x4400 -+#define UV_WID_MASK GENMASK(31, 28) -+#define UV_WID(x) UPDATE(x, 31, 28) -+#define Y_WID_MASK GENMASK(27, 24) -+#define Y_WID(x) UPDATE(x, 27, 24) -+#define DDR_STORE_FORMAT_MASK GENMASK(15, 12) -+#define DDR_STORE_FORMAT(x) UPDATE(x, 15, 12) -+#define ABANDON_EN BIT(0) -+#define DMA_CONFIG2 0x4404 -+#define DMA_CONFIG3 0x4408 -+#define DMA_CONFIG4 0x440c // dma irq en -+#define DMA_CONFIG5 0x4410 // dma irq clear status -+#define LINE_FLAG_INT_EN BIT(8) -+#define HDMIRX_DMA_IDLE_INT BIT(7) -+#define HDMIRX_LOCK_DISABLE_INT BIT(6) -+#define LAST_FRAME_AXI_UNFINISH_INT_EN BIT(5) -+#define FIFO_OVERFLOW_INT_EN BIT(2) -+#define FIFO_UNDERFLOW_INT_EN BIT(1) -+#define HDMIRX_AXI_ERROR_INT_EN BIT(0) -+#define DMA_CONFIG6 0x4414 -+#define RB_SWAP_EN BIT(9) -+#define HSYNC_TOGGLE_EN BIT(5) -+#define VSYNC_TOGGLE_EN BIT(4) -+#define HDMIRX_DMA_EN BIT(1) -+#define DMA_CONFIG7 0x4418 -+#define LINE_FLAG_NUM_MASK GENMASK(31, 16) -+#define LINE_FLAG_NUM(x) UPDATE(x, 31, 16) -+#define LOCK_FRAME_NUM_MASK GENMASK(11, 0) -+#define LOCK_FRAME_NUM(x) UPDATE(x, 11, 0) -+#define DMA_CONFIG8 0x441c -+#define REG_MIRROR_EN BIT(0) -+#define DMA_CONFIG9 0x4420 -+#define DMA_CONFIG10 0x4424 -+#define DMA_CONFIG11 0x4428 -+#define EDID_READ_EN_MASK BIT(8) -+#define EDID_READ_EN(x) UPDATE(x, 8, 8) -+#define EDID_WRITE_EN_MASK BIT(7) -+#define EDID_WRITE_EN(x) UPDATE(x, 7, 7) -+#define EDID_SLAVE_ADDR_MASK GENMASK(6, 0) -+#define EDID_SLAVE_ADDR(x) UPDATE(x, 6, 0) -+#define DMA_STATUS1 0x4430 // dma irq status -+#define DMA_STATUS2 0x4434 -+#define DMA_STATUS3 0x4438 -+#define DMA_STATUS4 0x443c -+#define DMA_STATUS5 0x4440 -+#define DMA_STATUS6 0x4444 -+#define DMA_STATUS7 0x4448 -+#define DMA_STATUS8 0x444c -+#define DMA_STATUS9 0x4450 -+#define DMA_STATUS10 0x4454 -+#define HDMIRX_LOCK BIT(3) -+#define DMA_STATUS11 0x4458 -+#define HDMIRX_TYPE_MASK GENMASK(8, 7) -+#define HDMIRX_COLOR_DEPTH_MASK GENMASK(6, 3) -+#define HDMIRX_FORMAT_MASK GENMASK(2, 0) -+#define DMA_STATUS12 0x445c -+#define DMA_STATUS13 0x4460 -+#define DMA_STATUS14 0x4464 -+ -+#define MAINUNIT_INTVEC_INDEX 0x5000 -+#define MAINUNIT_0_INT_STATUS 0x5010 -+#define CECRX_NOTIFY_ERR BIT(12) -+#define CECRX_EOM BIT(11) -+#define CECTX_DRIVE_ERR BIT(10) -+#define CECRX_BUSY BIT(9) -+#define CECTX_BUSY BIT(8) -+#define CECTX_FRAME_DISCARDED BIT(5) -+#define CECTX_NRETRANSMIT_FAIL BIT(4) -+#define CECTX_LINE_ERR BIT(3) -+#define CECTX_ARBLOST BIT(2) -+#define CECTX_NACK BIT(1) -+#define CECTX_DONE BIT(0) -+#define MAINUNIT_0_INT_MASK_N 0x5014 -+#define MAINUNIT_0_INT_CLEAR 0x5018 -+#define MAINUNIT_0_INT_FORCE 0x501c -+#define TIMER_BASE_LOCKED_IRQ BIT(26) -+#define TMDSQPCLK_OFF_CHG BIT(5) -+#define TMDSQPCLK_LOCKED_CHG BIT(4) -+#define MAINUNIT_1_INT_STATUS 0x5020 -+#define MAINUNIT_1_INT_MASK_N 0x5024 -+#define MAINUNIT_1_INT_CLEAR 0x5028 -+#define MAINUNIT_1_INT_FORCE 0x502c -+#define MAINUNIT_2_INT_STATUS 0x5030 -+#define MAINUNIT_2_INT_MASK_N 0x5034 -+#define MAINUNIT_2_INT_CLEAR 0x5038 -+#define MAINUNIT_2_INT_FORCE 0x503c -+#define PHYCREG_CR_READ_DONE BIT(11) -+#define PHYCREG_CR_WRITE_DONE BIT(10) -+#define TMDSVALID_STABLE_CHG BIT(1) -+ -+#define AVPUNIT_0_INT_STATUS 0x5040 -+#define AVPUNIT_0_INT_MASK_N 0x5044 -+#define AVPUNIT_0_INT_CLEAR 0x5048 -+#define AVPUNIT_0_INT_FORCE 0x504c -+#define CED_DYN_CNT_CH2_IRQ BIT(22) -+#define CED_DYN_CNT_CH1_IRQ BIT(21) -+#define CED_DYN_CNT_CH0_IRQ BIT(20) -+#define AVPUNIT_1_INT_STATUS 0x5050 -+#define DEFRAMER_VSYNC_THR_REACHED_IRQ BIT(1) -+#define AVPUNIT_1_INT_MASK_N 0x5054 -+#define DEFRAMER_VSYNC_THR_REACHED_MASK_N BIT(1) -+#define DEFRAMER_VSYNC_MASK_N BIT(0) -+#define AVPUNIT_1_INT_CLEAR 0x5058 -+#define DEFRAMER_VSYNC_THR_REACHED_CLEAR BIT(1) -+#define PKT_0_INT_STATUS 0x5080 -+#define PKTDEC_ACR_CHG_IRQ BIT(3) -+#define PKT_0_INT_MASK_N 0x5084 -+#define PKTDEC_ACR_CHG_MASK_N BIT(3) -+#define PKT_0_INT_CLEAR 0x5088 -+#define PKT_1_INT_STATUS 0x5090 -+#define PKT_1_INT_MASK_N 0x5094 -+#define PKT_1_INT_CLEAR 0x5098 -+#define PKT_2_INT_STATUS 0x50a0 -+#define PKTDEC_ACR_RCV_IRQ BIT(3) -+#define PKT_2_INT_MASK_N 0x50a4 -+#define PKTDEC_AVIIF_RCV_IRQ BIT(11) -+#define PKTDEC_ACR_RCV_MASK_N BIT(3) -+#define PKT_2_INT_CLEAR 0x50a8 -+#define PKTDEC_AVIIF_RCV_CLEAR BIT(11) -+#define PKTDEC_ACR_RCV_CLEAR BIT(3) -+#define SCDC_INT_STATUS 0x50c0 -+#define SCDC_INT_MASK_N 0x50c4 -+#define SCDC_INT_CLEAR 0x50c8 -+#define SCDCTMDSCCFG_CHG BIT(2) -+ -+#define CEC_INT_STATUS 0x5100 -+#define CEC_INT_MASK_N 0x5104 -+#define CEC_INT_CLEAR 0x5108 -+ -+#endif -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c -@@ -0,0 +1,285 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. -+ * -+ * Author: Shunqing Chen -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "snps_hdmirx.h" -+#include "snps_hdmirx_cec.h" -+ -+static void hdmirx_cec_write(struct hdmirx_cec *cec, int reg, u32 val) -+{ -+ cec->ops->write(cec->hdmirx, reg, val); -+} -+ -+static u32 hdmirx_cec_read(struct hdmirx_cec *cec, int reg) -+{ -+ return cec->ops->read(cec->hdmirx, reg); -+} -+ -+static void hdmirx_cec_update_bits(struct hdmirx_cec *cec, int reg, u32 mask, -+ u32 data) -+{ -+ u32 val = hdmirx_cec_read(cec, reg) & ~mask; -+ -+ val |= (data & mask); -+ hdmirx_cec_write(cec, reg, val); -+} -+ -+static int hdmirx_cec_log_addr(struct cec_adapter *adap, u8 logical_addr) -+{ -+ struct hdmirx_cec *cec = cec_get_drvdata(adap); -+ -+ if (logical_addr == CEC_LOG_ADDR_INVALID) -+ cec->addresses = 0; -+ else -+ cec->addresses |= BIT(logical_addr) | BIT(15); -+ -+ hdmirx_cec_write(cec, CEC_ADDR, cec->addresses); -+ -+ return 0; -+} -+ -+/* signal_free_time is handled by the Synopsys Designware -+ * HDMIRX Controller hardware. -+ */ -+static int hdmirx_cec_transmit(struct cec_adapter *adap, u8 attempts, -+ u32 signal_free_time, struct cec_msg *msg) -+{ -+ struct hdmirx_cec *cec = cec_get_drvdata(adap); -+ u32 data[4] = {0}; -+ int i, data_len, msg_len; -+ -+ msg_len = msg->len; -+ -+ hdmirx_cec_write(cec, CEC_TX_COUNT, msg_len - 1); -+ for (i = 0; i < msg_len; i++) -+ data[i / 4] |= msg->msg[i] << (i % 4) * 8; -+ -+ data_len = DIV_ROUND_UP(msg_len, 4); -+ -+ for (i = 0; i < data_len; i++) -+ hdmirx_cec_write(cec, CEC_TX_DATA3_0 + i * 4, data[i]); -+ -+ hdmirx_cec_write(cec, CEC_TX_CONTROL, 0x1); -+ -+ return 0; -+} -+ -+static irqreturn_t hdmirx_cec_hardirq(int irq, void *data) -+{ -+ struct cec_adapter *adap = data; -+ struct hdmirx_cec *cec = cec_get_drvdata(adap); -+ u32 stat = hdmirx_cec_read(cec, CEC_INT_STATUS); -+ irqreturn_t ret = IRQ_HANDLED; -+ u32 val; -+ -+ if (!stat) -+ return IRQ_NONE; -+ -+ hdmirx_cec_write(cec, CEC_INT_CLEAR, stat); -+ -+ if (stat & CECTX_LINE_ERR) { -+ cec->tx_status = CEC_TX_STATUS_ERROR; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; -+ } else if (stat & CECTX_DONE) { -+ cec->tx_status = CEC_TX_STATUS_OK; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; -+ } else if (stat & CECTX_NACK) { -+ cec->tx_status = CEC_TX_STATUS_NACK; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; -+ } else if (stat & CECTX_ARBLOST) { -+ cec->tx_status = CEC_TX_STATUS_ARB_LOST; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; -+ } -+ -+ if (stat & CECRX_EOM) { -+ unsigned int len, i; -+ -+ val = hdmirx_cec_read(cec, CEC_RX_COUNT_STATUS); -+ /* rxbuffer locked status */ -+ if ((val & 0x80)) -+ return ret; -+ -+ len = (val & 0xf) + 1; -+ if (len > sizeof(cec->rx_msg.msg)) -+ len = sizeof(cec->rx_msg.msg); -+ -+ for (i = 0; i < len; i++) { -+ if (!(i % 4)) -+ val = hdmirx_cec_read(cec, CEC_RX_DATA3_0 + i / 4 * 4); -+ cec->rx_msg.msg[i] = (val >> ((i % 4) * 8)) & 0xff; -+ } -+ -+ cec->rx_msg.len = len; -+ smp_wmb(); /* receive RX msg */ -+ cec->rx_done = true; -+ hdmirx_cec_write(cec, CEC_LOCK_CONTROL, 0x1); -+ -+ ret = IRQ_WAKE_THREAD; -+ } -+ -+ return ret; -+} -+ -+static irqreturn_t hdmirx_cec_thread(int irq, void *data) -+{ -+ struct cec_adapter *adap = data; -+ struct hdmirx_cec *cec = cec_get_drvdata(adap); -+ -+ if (cec->tx_done) { -+ cec->tx_done = false; -+ cec_transmit_attempt_done(adap, cec->tx_status); -+ } -+ if (cec->rx_done) { -+ cec->rx_done = false; -+ smp_rmb(); /* RX msg has been received */ -+ cec_received_msg(adap, &cec->rx_msg); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int hdmirx_cec_enable(struct cec_adapter *adap, bool enable) -+{ -+ struct hdmirx_cec *cec = cec_get_drvdata(adap); -+ -+ if (!enable) { -+ hdmirx_cec_write(cec, CEC_INT_MASK_N, 0); -+ hdmirx_cec_write(cec, CEC_INT_CLEAR, 0); -+ if (cec->ops->disable) -+ cec->ops->disable(cec->hdmirx); -+ } else { -+ unsigned int irqs; -+ -+ hdmirx_cec_log_addr(cec->adap, CEC_LOG_ADDR_INVALID); -+ if (cec->ops->enable) -+ cec->ops->enable(cec->hdmirx); -+ hdmirx_cec_update_bits(cec, GLOBAL_SWENABLE, CEC_ENABLE, CEC_ENABLE); -+ -+ irqs = CECTX_LINE_ERR | CECTX_NACK | CECRX_EOM | CECTX_DONE; -+ hdmirx_cec_write(cec, CEC_INT_MASK_N, irqs); -+ } -+ -+ return 0; -+} -+ -+static const struct cec_adap_ops hdmirx_cec_ops = { -+ .adap_enable = hdmirx_cec_enable, -+ .adap_log_addr = hdmirx_cec_log_addr, -+ .adap_transmit = hdmirx_cec_transmit, -+}; -+ -+static void hdmirx_cec_del(void *data) -+{ -+ struct hdmirx_cec *cec = data; -+ -+ cec_delete_adapter(cec->adap); -+} -+ -+struct hdmirx_cec *snps_hdmirx_cec_register(struct hdmirx_cec_data *data) -+{ -+ struct hdmirx_cec *cec; -+ unsigned int irqs; -+ int ret; -+ -+ /* -+ * Our device is just a convenience - we want to link to the real -+ * hardware device here, so that userspace can see the association -+ * between the HDMI hardware and its associated CEC chardev. -+ */ -+ cec = devm_kzalloc(data->dev, sizeof(*cec), GFP_KERNEL); -+ if (!cec) -+ return NULL; -+ -+ cec->dev = data->dev; -+ cec->irq = data->irq; -+ cec->ops = data->ops; -+ cec->hdmirx = data->hdmirx; -+ -+ hdmirx_cec_update_bits(cec, GLOBAL_SWENABLE, CEC_ENABLE, CEC_ENABLE); -+ hdmirx_cec_update_bits(cec, CEC_CONFIG, RX_AUTO_DRIVE_ACKNOWLEDGE, -+ RX_AUTO_DRIVE_ACKNOWLEDGE); -+ -+ hdmirx_cec_write(cec, CEC_TX_COUNT, 0); -+ hdmirx_cec_write(cec, CEC_INT_MASK_N, 0); -+ hdmirx_cec_write(cec, CEC_INT_CLEAR, ~0); -+ -+ cec->adap = cec_allocate_adapter(&hdmirx_cec_ops, cec, "snps-hdmirx", -+ CEC_CAP_LOG_ADDRS | CEC_CAP_TRANSMIT | -+ CEC_CAP_RC | CEC_CAP_PASSTHROUGH | -+ CEC_CAP_MONITOR_ALL, -+ CEC_MAX_LOG_ADDRS); -+ if (IS_ERR(cec->adap)) { -+ dev_err(cec->dev, "cec adap allocate failed\n"); -+ return NULL; -+ } -+ -+ /* override the module pointer */ -+ cec->adap->owner = THIS_MODULE; -+ -+ ret = devm_add_action(cec->dev, hdmirx_cec_del, cec); -+ if (ret) { -+ cec_delete_adapter(cec->adap); -+ return NULL; -+ } -+ -+ irq_set_status_flags(cec->irq, IRQ_NOAUTOEN); -+ -+ ret = devm_request_threaded_irq(cec->dev, cec->irq, -+ hdmirx_cec_hardirq, -+ hdmirx_cec_thread, IRQF_ONESHOT, -+ "rk_hdmirx_cec", cec->adap); -+ if (ret) { -+ dev_err(cec->dev, "cec irq request failed\n"); -+ return NULL; -+ } -+ -+ cec->notify = cec_notifier_cec_adap_register(cec->dev, -+ NULL, cec->adap); -+ if (!cec->notify) { -+ dev_err(cec->dev, "cec notify register failed\n"); -+ return NULL; -+ } -+ -+ ret = cec_register_adapter(cec->adap, cec->dev); -+ if (ret < 0) { -+ dev_err(cec->dev, "cec register adapter failed\n"); -+ cec_unregister_adapter(cec->adap); -+ return NULL; -+ } -+ -+ irqs = CECTX_LINE_ERR | CECTX_NACK | CECRX_EOM | CECTX_DONE; -+ hdmirx_cec_write(cec, CEC_INT_MASK_N, irqs); -+ -+ /* -+ * CEC documentation says we must not call cec_delete_adapter -+ * after a successful call to cec_register_adapter(). -+ */ -+ devm_remove_action(cec->dev, hdmirx_cec_del, cec); -+ -+ enable_irq(cec->irq); -+ -+ return cec; -+} -+ -+void snps_hdmirx_cec_unregister(struct hdmirx_cec *cec) -+{ -+ disable_irq(cec->irq); -+ -+ cec_unregister_adapter(cec->adap); -+} -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h -@@ -0,0 +1,44 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. -+ * -+ * Author: Shunqing Chen -+ */ -+ -+#ifndef DW_HDMI_RX_CEC_H -+#define DW_HDMI_RX_CEC_H -+ -+struct snps_hdmirx_dev; -+ -+struct hdmirx_cec_ops { -+ void (*write)(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val); -+ u32 (*read)(struct snps_hdmirx_dev *hdmirx_dev, int reg); -+ void (*enable)(struct snps_hdmirx_dev *hdmirx); -+ void (*disable)(struct snps_hdmirx_dev *hdmirx); -+}; -+ -+struct hdmirx_cec_data { -+ struct snps_hdmirx_dev *hdmirx; -+ const struct hdmirx_cec_ops *ops; -+ struct device *dev; -+ int irq; -+}; -+ -+struct hdmirx_cec { -+ struct snps_hdmirx_dev *hdmirx; -+ struct device *dev; -+ const struct hdmirx_cec_ops *ops; -+ u32 addresses; -+ struct cec_adapter *adap; -+ struct cec_msg rx_msg; -+ unsigned int tx_status; -+ bool tx_done; -+ bool rx_done; -+ struct cec_notifier *notify; -+ int irq; -+}; -+ -+struct hdmirx_cec *snps_hdmirx_cec_register(struct hdmirx_cec_data *data); -+void snps_hdmirx_cec_unregister(struct hdmirx_cec *cec); -+ -+#endif /* DW_HDMI_RX_CEC_H */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 29 Jul 2024 17:29:46 +0200 -Subject: arm64: defconfig: Enable Synopsys HDMI receiver - -The Rockchip RK3588 has a built-in HDMI receiver block from -Synopsys. Let's enable the driver for it. - -Signed-off-by: Sebastian Reichel ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 111111111111..222222222222 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -860,6 +860,7 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m - CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m - CONFIG_VIDEO_SAMSUNG_S5P_MFC=m - CONFIG_VIDEO_SUN6I_CSI=m -+CONFIG_VIDEO_SYNOPSYS_HDMIRX=m - CONFIG_VIDEO_TI_J721E_CSI2RX=m - CONFIG_VIDEO_HANTRO=m - CONFIG_VIDEO_IMX219=m --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Thu, 1 Aug 2024 16:47:35 +0300 -Subject: comment v4l2 error on hdmirx - ---- - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -@@ -1180,7 +1180,7 @@ static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev) - break; - - if (!tx_5v_power_present(hdmirx_dev)) { -- v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__); -+ //v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__); - return -1; - } - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ben Hoff -Date: Sun, 15 Sep 2024 14:52:17 -0400 -Subject: fix spurious triggering of irq 5v while plugout code is running - ---- - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 12 ++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -@@ -745,10 +745,17 @@ static void hdmirx_interrupts_setup(struct snps_hdmirx_dev *hdmirx_dev, bool en) - static void hdmirx_plugout(struct snps_hdmirx_dev *hdmirx_dev) - { - struct arm_smccc_res res; -+ int irq; - - hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, 0); - hdmirx_interrupts_setup(hdmirx_dev, false); - hdmirx_hpd_ctrl(hdmirx_dev, false); -+ irq = gpiod_to_irq(hdmirx_dev->detect_5v_gpio); -+ -+ if (irq >= 0) { -+ disable_irq(irq); -+ } -+ - hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0); - hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, - LINE_FLAG_INT_EN | -@@ -766,6 +773,11 @@ static void hdmirx_plugout(struct snps_hdmirx_dev *hdmirx_dev) - cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat); - flush_work(&hdmirx_dev->work_wdt_config); - arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res); -+ -+ hdmirx_hpd_ctrl(hdmirx_dev, true); -+ if (irq >= 0) { -+ enable_irq(irq); -+ } - } - - static int hdmirx_set_edid(struct file *file, void *fh, struct v4l2_edid *edid) --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ben Hoff -Date: Sun, 15 Sep 2024 14:53:25 -0400 -Subject: remove timing handling from plug in function - ---- - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 7 ------- - 1 file changed, 7 deletions(-) - -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -@@ -2202,13 +2202,6 @@ static void hdmirx_plugin(struct snps_hdmirx_dev *hdmirx_dev) - hdmirx_hpd_ctrl(hdmirx_dev, true); - hdmirx_phy_config(hdmirx_dev); - ret = hdmirx_wait_lock_and_get_timing(hdmirx_dev); -- if (ret) { -- hdmirx_plugout(hdmirx_dev); -- queue_delayed_work(system_unbound_wq, -- &hdmirx_dev->delayed_work_hotplug, -- msecs_to_jiffies(200)); -- return; -- } - hdmirx_dma_config(hdmirx_dev); - hdmirx_interrupts_setup(hdmirx_dev, true); - } --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ben Hoff -Date: Mon, 23 Sep 2024 09:43:38 -0400 -Subject: expose itc type to v4l2 in synopsys hdmir rx - ---- - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 16 +++++++++- - 1 file changed, 15 insertions(+), 1 deletion(-) - -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -@@ -151,6 +151,7 @@ struct snps_hdmirx_dev { - struct v4l2_ctrl_handler hdl; - struct v4l2_ctrl *detect_tx_5v_ctrl; - struct v4l2_ctrl *rgb_range; -+ struct v4l2_ctrl *content_type; - struct v4l2_dv_timings timings; - struct gpio_desc *detect_5v_gpio; - struct work_struct work_wdt_config; -@@ -512,6 +513,11 @@ static void hdmirx_get_avi_infoframe(struct snps_hdmirx_dev *hdmirx_dev) - } - - v4l2_ctrl_s_ctrl(hdmirx_dev->rgb_range, frame.avi.quantization_range); -+ if (frame.avi.itc) { -+ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, frame.avi.content_type); -+ } else { -+ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); -+ } - } - - /* -@@ -1192,6 +1198,7 @@ static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev) - break; - - if (!tx_5v_power_present(hdmirx_dev)) { -+ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); - //v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__); - return -1; - } -@@ -1204,6 +1211,7 @@ static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev) - __func__, hdmirx_dev->tmds_clk_ratio); - v4l2_err(v4l2_dev, "%s: mu_st:%#x, scdc_st:%#x, dma_st10:%#x\n", - __func__, mu_status, scdc_status, dma_st10); -+ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); - return -1; - } - -@@ -2668,7 +2676,7 @@ static int hdmirx_probe(struct platform_device *pdev) - strscpy(v4l2_dev->name, dev_name(dev), sizeof(v4l2_dev->name)); - - hdl = &hdmirx_dev->hdl; -- v4l2_ctrl_handler_init(hdl, 1); -+ v4l2_ctrl_handler_init(hdl, 3); - - hdmirx_dev->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, - V4L2_CID_DV_RX_POWER_PRESENT, -@@ -2681,6 +2689,12 @@ static int hdmirx_probe(struct platform_device *pdev) - - hdmirx_dev->rgb_range->flags |= V4L2_CTRL_FLAG_READ_ONLY; - -+ hdmirx_dev->content_type = v4l2_ctrl_new_std_menu(hdl, NULL, -+ V4L2_CID_DV_RX_IT_CONTENT_TYPE, -+ V4L2_DV_IT_CONTENT_TYPE_NO_ITC, -+ 0, -+ V4L2_DV_IT_CONTENT_TYPE_NO_ITC); -+ - if (hdl->error) { - dev_err(dev, "v4l2 ctrl handler init failed\n"); - ret = hdl->error; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-0130-add-hdmi1-support.patch b/patch/kernel/rockchip64-6.14/rk3588-0130-add-hdmi1-support.patch deleted file mode 100644 index e137612..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-0130-add-hdmi1-support.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sat, 7 Dec 2024 21:45:12 +0200 -Subject: arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588 - -In preparation to enable the second HDMI output port found on RK3588 -SoC, add the related PHY node. This requires a GRF, hence add the -dependent node as well. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 21 ++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -90,6 +90,11 @@ u2phy1_otg: otg-port { - }; - }; - -+ hdptxphy1_grf: syscon@fd5e4000 { -+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; -+ reg = <0x0 0xfd5e4000 0x0 0x100>; -+ }; -+ - i2s8_8ch: i2s@fddc8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc8000 0x0 0x1000>; -@@ -454,6 +459,22 @@ sata-port@0 { - }; - }; - -+ hdptxphy1: phy@fed70000 { -+ compatible = "rockchip,rk3588-hdptx-phy"; -+ reg = <0x0 0xfed70000 0x0 0x2000>; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; -+ clock-names = "ref", "apb"; -+ #phy-cells = <0>; -+ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, -+ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, -+ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, -+ <&cru SRST_HDPTX1_LCPLL>; -+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", -+ "lcpll"; -+ rockchip,grf = <&hdptxphy1_grf>; -+ status = "disabled"; -+ }; -+ - usbdp_phy1: phy@fed90000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed90000 0x0 0x10000>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sat, 7 Dec 2024 21:53:07 +0200 -Subject: arm64: dts: rockchip: Add HDMI1 node on RK3588 - -Add support for the second HDMI TX port found on RK3588 SoC. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 41 ++++++++++ - 1 file changed, 41 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -196,6 +196,47 @@ hdmi_receiver: hdmi_receiver@fdee0000 { - status = "disabled"; - }; - -+ hdmi1: hdmi@fdea0000 { -+ compatible = "rockchip,rk3588-dw-hdmi-qp"; -+ reg = <0x0 0xfdea0000 0x0 0x20000>; -+ clocks = <&cru PCLK_HDMITX1>, -+ <&cru CLK_HDMITX1_EARC>, -+ <&cru CLK_HDMITX1_REF>, -+ <&cru MCLK_I2S6_8CH_TX>, -+ <&cru CLK_HDMIHDP1>, -+ <&cru HCLK_VO1>; -+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "avp", "cec", "earc", "main", "hpd"; -+ phys = <&hdptxphy1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd -+ &hdmim1_tx1_scl &hdmim1_tx1_sda>; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; -+ reset-names = "ref", "hdp"; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vo-grf = <&vo1_grf>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hdmi1_in: port@0 { -+ reg = <0>; -+ }; -+ -+ hdmi1_out: port@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ - pcie3x4: pcie@fe150000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-0131-vop2-hdmi0-disp-modes-support.patch b/patch/kernel/rockchip64-6.14/rk3588-0131-vop2-hdmi0-disp-modes-support.patch deleted file mode 100644 index c5f0cac..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-0131-vop2-hdmi0-disp-modes-support.patch +++ /dev/null @@ -1,252 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sat, 16 Nov 2024 03:19:43 +0200 -Subject: dt-bindings: display: vop2: Add optional PLL clock properties - -On RK3588, HDMI PHY PLL can be used as an alternative and more accurate -pixel clock source for VOP2 video ports 0, 1 and 2. - -Document the optional PLL clock properties corresponding to the two HDMI -PHYs available on the SoC. - -Signed-off-by: Cristian Ciocaltea ---- - Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -@@ -53,6 +53,8 @@ properties: - - description: Pixel clock for video port 2. - - description: Pixel clock for video port 3. - - description: Peripheral(vop grf/dsi) clock. -+ - description: Alternative pixel clock provided by HDMI0 PHY PLL. -+ - description: Alternative pixel clock provided by HDMI1 PHY PLL. - - clock-names: - minItems: 5 -@@ -64,6 +66,8 @@ properties: - - const: dclk_vp2 - - const: dclk_vp3 - - const: pclk_vop -+ - const: pll_hdmiphy0 -+ - const: pll_hdmiphy1 - - rockchip,grf: - $ref: /schemas/types.yaml#/definitions/phandle --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Tue, 12 Nov 2024 02:27:35 +0200 -Subject: drm/rockchip: vop2: Drop unnecessary if_pixclk_rate computation - -The if_pixclk_rate variable is not being used outside of the if-block in -rk3588_calc_cru_cfg(), hence move the superfluous assignment from the -first branch to the inner comment-block. - -Signed-off-by: Cristian Ciocaltea ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -1905,8 +1905,8 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id, - K = 2; - } - -- if_pixclk_rate = (dclk_core_rate << 1) / K; - /* -+ * if_pixclk_rate = (dclk_core_rate << 1) / K; - * if_dclk_rate = dclk_core_rate / K; - * *if_pixclk_div = dclk_rate / if_pixclk_rate; - * *if_dclk_div = dclk_rate / if_dclk_rate; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Fri, 3 Nov 2023 19:58:02 +0200 -Subject: drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0 - -The RK3588 specific implementation is currently quite limited in terms -of handling the full range of display modes supported by the connected -screens, e.g. 2560x1440@75Hz, 2048x1152@60Hz, 1024x768@60Hz are just a -few of them. - -Additionally, it doesn't cope well with non-integer refresh rates like -59.94, 29.97, 23.98, etc. - -Make use of HDMI0 PHY PLL as a more accurate DCLK source to handle -all display modes up to 4K@60Hz. - -Signed-off-by: Cristian Ciocaltea ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 34 ++++++++++ - 1 file changed, 34 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -159,6 +159,7 @@ struct vop2_video_port { - struct drm_crtc crtc; - struct vop2 *vop2; - struct clk *dclk; -+ struct clk *dclk_src; - unsigned int id; - const struct vop2_video_port_data *data; - -@@ -214,6 +215,7 @@ struct vop2 { - struct clk *hclk; - struct clk *aclk; - struct clk *pclk; -+ struct clk *pll_hdmiphy0; - - /* optional internal rgb encoder */ - struct rockchip_rgb *rgb; -@@ -222,6 +224,8 @@ struct vop2 { - struct vop2_win win[]; - }; - -+#define VOP2_MAX_DCLK_RATE 600000000 -+ - #define vop2_output_if_is_hdmi(x) ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \ - (x) == ROCKCHIP_VOP2_EP_HDMI1) - -@@ -1155,6 +1159,9 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, - - vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); - -+ if (vp->dclk_src) -+ clk_set_parent(vp->dclk, vp->dclk_src); -+ - clk_disable_unprepare(vp->dclk); - - vop2->enable_count--; -@@ -2259,6 +2266,27 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - - vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); - -+ /* -+ * Switch to HDMI PHY PLL as DCLK source for display modes up -+ * to 4K@60Hz, if available, otherwise keep using the system CRU. -+ */ -+ if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) { -+ drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { -+ if (!vp->dclk_src) -+ vp->dclk_src = clk_get_parent(vp->dclk); -+ -+ ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); -+ if (ret < 0) -+ drm_warn(vop2->drm, -+ "Could not switch to HDMI0 PHY PLL: %d\n", ret); -+ break; -+ } -+ } -+ } -+ - clk_set_rate(vp->dclk, clock); - - vop2_post_config(crtc); -@@ -3699,6 +3727,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) - return PTR_ERR(vop2->pclk); - } - -+ vop2->pll_hdmiphy0 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy0"); -+ if (IS_ERR(vop2->pll_hdmiphy0)) { -+ drm_err(vop2->drm, "failed to get pll_hdmiphy0\n"); -+ return PTR_ERR(vop2->pll_hdmiphy0); -+ } -+ - vop2->irq = platform_get_irq(pdev, 0); - if (vop2->irq < 0) { - drm_err(vop2->drm, "cannot find irq for vop2\n"); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Tue, 16 Jan 2024 03:13:38 +0200 -Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 - -Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock -provider support"), the HDMI PHY PLL can be used as an alternative and -more accurate pixel clock source for VOP2 to improve display modes -handling on RK3588 SoC. - -Add the missing #clock-cells property to allow using the clock provider -functionality of HDMI0 PHY. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -2812,6 +2812,7 @@ hdptxphy_hdmi0: phy@fed60000 { - reg = <0x0 0xfed60000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; - clock-names = "ref", "apb"; -+ #clock-cells = <0>; - #phy-cells = <0>; - resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, - <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sat, 16 Nov 2024 04:33:46 +0200 -Subject: arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on - RK3588 - -VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and -more accurate pixel clock source to improve handling of display modes up -to 4K@60Hz on video ports 0, 1 and 2. - -For now only HDMI0 output is supported, hence add the related PLL clock. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1261,14 +1261,16 @@ vop: vop@fdd90000 { - <&cru DCLK_VOP1>, - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, -- <&cru PCLK_VOP_ROOT>; -+ <&cru PCLK_VOP_ROOT>, -+ <&hdptxphy_hdmi0>; - clock-names = "aclk", - "hclk", - "dclk_vp0", - "dclk_vp1", - "dclk_vp2", - "dclk_vp3", -- "pclk_vop"; -+ "pclk_vop", -+ "pll_hdmiphy0"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; - rockchip,grf = <&sys_grf>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-0132-Fix-label-name-of-hdptxphy-for-RK3588.patch b/patch/kernel/rockchip64-6.14/rk3588-0132-Fix-label-name-of-hdptxphy-for-RK3588.patch deleted file mode 100644 index d0be509..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-0132-Fix-label-name-of-hdptxphy-for-RK3588.patch +++ /dev/null @@ -1,318 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Damon Ding -Date: Thu, 6 Feb 2025 11:03:30 +0800 -Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588 - -The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP -and eDP Link. Therefore, it is better to name it hdptxphy0 other than -hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes. - -Signed-off-by: Damon Ding -Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com -[added armsom-sige7, where hdmi-support was added recently and also - the hdptxphy0-as-dclk source I just added] -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 +++--- - arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 2 +- - arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 2 +- - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts | 2 +- - 20 files changed, 22 insertions(+), 22 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1262,7 +1262,7 @@ vop: vop@fdd90000 { - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>, -- <&hdptxphy_hdmi0>; -+ <&hdptxphy0>; - clock-names = "aclk", - "hclk", - "dclk_vp0", -@@ -1387,7 +1387,7 @@ hdmi0: hdmi@fde80000 { - , - ; - interrupt-names = "avp", "cec", "earc", "main", "hpd"; -- phys = <&hdptxphy_hdmi0>; -+ phys = <&hdptxphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd - &hdmim0_tx0_scl &hdmim0_tx0_sda>; -@@ -2809,7 +2809,7 @@ dmac2: dma-controller@fed10000 { - #dma-cells = <1>; - }; - -- hdptxphy_hdmi0: phy@fed60000 { -+ hdptxphy0: phy@fed60000 { - compatible = "rockchip,rk3588-hdptx-phy"; - reg = <0x0 0xfed60000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts -@@ -129,7 +129,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts -@@ -166,7 +166,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -@@ -364,7 +364,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts -@@ -337,7 +337,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts -@@ -335,7 +335,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts -@@ -207,7 +207,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts -@@ -303,7 +303,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -360,7 +360,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts -@@ -39,7 +39,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -@@ -125,7 +125,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -220,7 +220,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts -@@ -189,7 +189,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts -@@ -236,7 +236,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts -@@ -278,7 +278,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi -@@ -251,7 +251,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts -@@ -266,7 +266,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi -@@ -197,7 +197,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -334,7 +334,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts -@@ -278,7 +278,7 @@ hdmi0_out_con: endpoint { - }; - }; - --&hdptxphy_hdmi0 { -+&hdptxphy0 { - status = "okay"; - }; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-0133-vop2-hdmi1-disp-modes-support.patch b/patch/kernel/rockchip64-6.14/rk3588-0133-vop2-hdmi1-disp-modes-support.patch deleted file mode 100644 index 5e87f24..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-0133-vop2-hdmi1-disp-modes-support.patch +++ /dev/null @@ -1,173 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sat, 15 Feb 2025 02:55:37 +0200 -Subject: drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI1 - -The RK3588 specific implementation is currently quite limited in terms -of handling the full range of display modes supported by the connected -screens, e.g. 2560x1440@75Hz, 2048x1152@60Hz, 1024x768@60Hz are just a -few of them. - -Additionally, it doesn't cope well with non-integer refresh rates like -59.94, 29.97, 23.98, etc. - -Make use of HDMI1 PHY PLL as a more accurate DCLK source to handle -all display modes up to 4K@60Hz. - -Signed-off-by: Cristian Ciocaltea ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 26 +++++++++- - 1 file changed, 25 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -216,6 +216,7 @@ struct vop2 { - struct clk *aclk; - struct clk *pclk; - struct clk *pll_hdmiphy0; -+ struct clk *pll_hdmiphy1; - - /* optional internal rgb encoder */ - struct rockchip_rgb *rgb; -@@ -2270,11 +2271,14 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - * Switch to HDMI PHY PLL as DCLK source for display modes up - * to 4K@60Hz, if available, otherwise keep using the system CRU. - */ -- if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) { -+ if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <= VOP2_MAX_DCLK_RATE) { - drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { - struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); - - if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { -+ if (!vop2->pll_hdmiphy0) -+ break; -+ - if (!vp->dclk_src) - vp->dclk_src = clk_get_parent(vp->dclk); - -@@ -2284,6 +2288,20 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - "Could not switch to HDMI0 PHY PLL: %d\n", ret); - break; - } -+ -+ if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI1) { -+ if (!vop2->pll_hdmiphy1) -+ break; -+ -+ if (!vp->dclk_src) -+ vp->dclk_src = clk_get_parent(vp->dclk); -+ -+ ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); -+ if (ret < 0) -+ drm_warn(vop2->drm, -+ "Could not switch to HDMI1 PHY PLL: %d\n", ret); -+ break; -+ } - } - } - -@@ -3733,6 +3751,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) - return PTR_ERR(vop2->pll_hdmiphy0); - } - -+ vop2->pll_hdmiphy1 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy1"); -+ if (IS_ERR(vop2->pll_hdmiphy1)) { -+ drm_err(vop2->drm, "failed to get pll_hdmiphy1\n"); -+ return PTR_ERR(vop2->pll_hdmiphy1); -+ } -+ - vop2->irq = platform_get_irq(pdev, 0); - if (vop2->irq < 0) { - drm_err(vop2->drm, "cannot find irq for vop2\n"); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sat, 15 Feb 2025 02:55:38 +0200 -Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 - -Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock -provider support"), the HDMI PHY PLL can be used as an alternative and -more accurate pixel clock source for VOP2 to improve display modes -handling on RK3588 SoC. - -Add the missing #clock-cells property to allow using the clock provider -functionality of HDMI1 PHY. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -505,6 +505,7 @@ hdptxphy1: phy@fed70000 { - reg = <0x0 0xfed70000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; - clock-names = "ref", "apb"; -+ #clock-cells = <0>; - #phy-cells = <0>; - resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, - <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sat, 15 Feb 2025 02:55:39 +0200 -Subject: arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on - RK3588 - -VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and -more accurate pixel clock source to improve handling of display modes up -to 4K@60Hz on video ports 0, 1 and 2. - -The HDMI1 PHY PLL clock source cannot be added directly to vop node in -rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an -optional feature and its PHY node belongs to a separate (extra) DT file. - -Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its -clocks & clock-names properties in the extra DT file. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 21 ++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -568,3 +568,24 @@ pcie30phy: phy@fee80000 { - status = "disabled"; - }; - }; -+ -+&vop { -+ clocks = <&cru ACLK_VOP>, -+ <&cru HCLK_VOP>, -+ <&cru DCLK_VOP0>, -+ <&cru DCLK_VOP1>, -+ <&cru DCLK_VOP2>, -+ <&cru DCLK_VOP3>, -+ <&cru PCLK_VOP_ROOT>, -+ <&hdptxphy0>, -+ <&hdptxphy1>; -+ clock-names = "aclk", -+ "hclk", -+ "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2", -+ "dclk_vp3", -+ "pclk_vop", -+ "pll_hdmiphy0", -+ "pll_hdmiphy1"; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-0170-drm-rockchip-vop2-add-clocks-reset-support.patch b/patch/kernel/rockchip64-6.14/rk3588-0170-drm-rockchip-vop2-add-clocks-reset-support.patch deleted file mode 100644 index f551867..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-0170-drm-rockchip-vop2-add-clocks-reset-support.patch +++ /dev/null @@ -1,187 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Fri, 3 May 2024 14:27:39 -0400 -Subject: vop2: Add clock resets support - -At the end of initialization, each VP clock needs to be reset before -they can be used. - -Failing to do so can put the VOP in an undefined state where the -generated HDMI signal is either lost or not matching the selected mode. - -Signed-off-by: Detlev Casanova ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 30 ++++++++++ - 1 file changed, 30 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -158,6 +159,7 @@ struct vop2_win { - struct vop2_video_port { - struct drm_crtc crtc; - struct vop2 *vop2; -+ struct reset_control *dclk_rst; - struct clk *dclk; - struct clk *dclk_src; - unsigned int id; -@@ -2135,6 +2137,26 @@ static int us_to_vertical_line(struct drm_display_mode *mode, int us) - return us * mode->clock / mode->htotal / 1000; - } - -+static int vop2_clk_reset(struct vop2_video_port *vp) -+{ -+ struct reset_control *rstc = vp->dclk_rst; -+ struct vop2 *vop2 = vp->vop2; -+ int ret; -+ -+ if (!rstc) -+ return 0; -+ -+ ret = reset_control_assert(rstc); -+ if (ret < 0) -+ drm_warn(vop2->drm, "failed to assert reset\n"); -+ udelay(10); -+ ret = reset_control_deassert(rstc); -+ if (ret < 0) -+ drm_warn(vop2->drm, "failed to deassert reset\n"); -+ -+ return ret; -+} -+ - static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) - { -@@ -2315,6 +2337,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - - vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state); - -+ vop2_clk_reset(vp); -+ - drm_crtc_vblank_on(crtc); - - vop2_unlock(vop2); -@@ -3272,6 +3296,12 @@ static int vop2_create_crtcs(struct vop2 *vop2) - vp->data = vp_data; - - snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); -+ vp->dclk_rst = devm_reset_control_get_optional(vop2->dev, dclk_name); -+ if (IS_ERR(vp->dclk_rst)) { -+ drm_err(vop2->drm, "failed to get %s reset\n", dclk_name); -+ return PTR_ERR(vp->dclk_rst); -+ } -+ - vp->dclk = devm_clk_get(vop2->dev, dclk_name); - if (IS_ERR(vp->dclk)) { - drm_err(vop2->drm, "failed to get %s\n", dclk_name); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Mon, 6 May 2024 13:54:01 -0400 -Subject: dt-bindings: display: vop2: Add VP clock resets - -Add the documentation for VOP2 video ports reset clocks. -One reset can be set per video port. - -Signed-off-by: Detlev Casanova ---- - Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 27 ++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -@@ -69,6 +69,22 @@ properties: - - const: pll_hdmiphy0 - - const: pll_hdmiphy1 - -+ resets: -+ minItems: 3 -+ items: -+ - description: Pixel clock reset for video port 0. -+ - description: Pixel clock reset for video port 1. -+ - description: Pixel clock reset for video port 2. -+ - description: Pixel clock reset for video port 3. -+ -+ reset-names: -+ minItems: 3 -+ items: -+ - const: dclk_vp0 -+ - const: dclk_vp1 -+ - const: dclk_vp2 -+ - const: dclk_vp3 -+ - rockchip,grf: - $ref: /schemas/types.yaml#/definitions/phandle - description: -@@ -132,6 +148,11 @@ allOf: - clock-names: - minItems: 7 - -+ resets: -+ minItems: 4 -+ reset-names: -+ minItems: 4 -+ - ports: - required: - - port@0 -@@ -187,6 +208,12 @@ examples: - "dclk_vp0", - "dclk_vp1", - "dclk_vp2"; -+ resets = <&cru SRST_VOP0>, -+ <&cru SRST_VOP1>, -+ <&cru SRST_VOP2>; -+ reset-names = "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2"; - power-domains = <&power RK3568_PD_VO>; - iommus = <&vop_mmu>; - vop_out: ports { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Fri, 2 Aug 2024 00:13:32 +0300 -Subject: arm64: dts: rockchip: rk3588: add VOP2 clock resets - ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1273,6 +1273,14 @@ vop: vop@fdd90000 { - "pll_hdmiphy0"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; -+ resets = <&cru SRST_D_VOP0>, -+ <&cru SRST_D_VOP1>, -+ <&cru SRST_D_VOP2>, -+ <&cru SRST_D_VOP3>; -+ reset-names = "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2", -+ "dclk_vp3"; - rockchip,grf = <&sys_grf>; - rockchip,vop-grf = <&vop_grf>; - rockchip,vo1-grf = <&vo1_grf>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-0180-drm-bridge-dw-hdmi-qp.patch b/patch/kernel/rockchip64-6.14/rk3588-0180-drm-bridge-dw-hdmi-qp.patch deleted file mode 100644 index bce285c..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-0180-drm-bridge-dw-hdmi-qp.patch +++ /dev/null @@ -1,580 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: palachzzz <7zzzzzzz@mail.ru> -Date: Thu, 27 Feb 2025 23:06:51 +0800 -Subject: [ARCHEOLOGY] RK3588 add HDMI sound, add support for OPi5 Max #7884 - -> X-Git-Archeology: - Revision 0b88561ec332114404ff8075ab6bc2419ca66a47: https://github.com/armbian/build/commit/0b88561ec332114404ff8075ab6bc2419ca66a47 -> X-Git-Archeology: Date: Thu, 27 Feb 2025 23:06:51 +0800 -> X-Git-Archeology: From: palachzzz <7zzzzzzz@mail.ru> -> X-Git-Archeology: Subject: RK3588 add HDMI sound, add support for OPi5 Max #7884 -> X-Git-Archeology: ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 489 ++++++++++ - 1 file changed, 489 insertions(+) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -@@ -36,6 +36,88 @@ - - #define SCRAMB_POLL_DELAY_MS 3000 - -+/* -+ * Unless otherwise noted, entries in this table are 100% optimization. -+ * Values can be obtained from dw_hdmi_qp_compute_n() but that function is -+ * slow so we pre-compute values we expect to see. -+ * -+ * The values for TMDS 25175, 25200, 27000, 54000, 74250 and 148500 kHz are -+ * the recommended N values specified in the Audio chapter of the HDMI -+ * specification. -+ */ -+static const struct dw_hdmi_audio_tmds_n { -+ unsigned long tmds; -+ unsigned int n_32k; -+ unsigned int n_44k1; -+ unsigned int n_48k; -+} common_tmds_n_table[] = { -+ { .tmds = 25175000, .n_32k = 4576, .n_44k1 = 7007, .n_48k = 6864, }, -+ { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, -+ { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, -+ { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, -+ { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, -+ { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, -+ { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, -+ { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, -+ { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, -+ { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, -+ { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, -+ { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, -+ { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, -+ { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, -+ { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, -+ { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, -+ { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, -+ { .tmds = 73250000, .n_32k = 11648, .n_44k1 = 14112, .n_48k = 6144, }, -+ { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, -+ { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, -+ { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, -+ { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, -+ { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, -+ { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, -+ { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, -+ { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, -+ { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, -+ { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, -+ { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, -+ { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, -+ { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, -+ { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, -+ { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, -+ { .tmds = 146250000, .n_32k = 11648, .n_44k1 = 6272, .n_48k = 6144, }, -+ { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, -+ { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, -+ { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, -+ -+ /* For 297 MHz+ HDMI spec have some other rule for setting N */ -+ { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, -+ { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240,}, -+ -+ /* End of table */ -+ { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, -+}; -+ -+/* -+ * These are the CTS values as recommended in the Audio chapter of the HDMI -+ * specification. -+ */ -+static const struct dw_hdmi_audio_tmds_cts { -+ unsigned long tmds; -+ unsigned int cts_32k; -+ unsigned int cts_44k1; -+ unsigned int cts_48k; -+} common_tmds_cts_table[] = { -+ { .tmds = 25175000, .cts_32k = 28125, .cts_44k1 = 31250, .cts_48k = 28125, }, -+ { .tmds = 25200000, .cts_32k = 25200, .cts_44k1 = 28000, .cts_48k = 25200, }, -+ { .tmds = 27000000, .cts_32k = 27000, .cts_44k1 = 30000, .cts_48k = 27000, }, -+ { .tmds = 54000000, .cts_32k = 54000, .cts_44k1 = 60000, .cts_48k = 54000, }, -+ { .tmds = 74250000, .cts_32k = 74250, .cts_44k1 = 82500, .cts_48k = 74250, }, -+ { .tmds = 148500000, .cts_32k = 148500, .cts_44k1 = 165000, .cts_48k = 148500, }, -+ -+ /* End of table */ -+ { .tmds = 0, .cts_32k = 0, .cts_44k1 = 0, .cts_48k = 0, }, -+}; -+ - struct dw_hdmi_qp_i2c { - struct i2c_adapter adap; - -@@ -60,6 +142,8 @@ struct dw_hdmi_qp { - } phy; - - struct regmap *regm; -+ -+ unsigned long tmds_char_rate; - }; - - static void dw_hdmi_qp_write(struct dw_hdmi_qp *hdmi, unsigned int val, -@@ -83,6 +167,346 @@ static void dw_hdmi_qp_mod(struct dw_hdmi_qp *hdmi, unsigned int data, - regmap_update_bits(hdmi->regm, reg, mask, data); - } - -+static struct dw_hdmi_qp *dw_hdmi_qp_from_bridge(struct drm_bridge *bridge) -+{ -+ return container_of(bridge, struct dw_hdmi_qp, bridge); -+} -+ -+static void dw_hdmi_qp_set_cts_n(struct dw_hdmi_qp *hdmi, unsigned int cts, -+ unsigned int n) -+{ -+ /* Set N */ -+ dw_hdmi_qp_mod(hdmi, n, AUDPKT_ACR_N_VALUE, AUDPKT_ACR_CONTROL0); -+ -+ /* Set CTS */ -+ if (cts) -+ dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_EN, AUDPKT_ACR_CTS_OVR_EN_MSK, -+ AUDPKT_ACR_CONTROL1); -+ else -+ dw_hdmi_qp_mod(hdmi, 0, AUDPKT_ACR_CTS_OVR_EN_MSK, -+ AUDPKT_ACR_CONTROL1); -+ -+ dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_VAL(cts), AUDPKT_ACR_CTS_OVR_VAL_MSK, -+ AUDPKT_ACR_CONTROL1); -+} -+ -+static int dw_hdmi_qp_match_tmds_n_table(struct dw_hdmi_qp *hdmi, -+ unsigned long pixel_clk, -+ unsigned long freq) -+{ -+ const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; -+ int i; -+ -+ for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { -+ if (pixel_clk == common_tmds_n_table[i].tmds) { -+ tmds_n = &common_tmds_n_table[i]; -+ break; -+ } -+ } -+ -+ if (!tmds_n) -+ return -ENOENT; -+ -+ switch (freq) { -+ case 32000: -+ return tmds_n->n_32k; -+ case 44100: -+ case 88200: -+ case 176400: -+ return (freq / 44100) * tmds_n->n_44k1; -+ case 48000: -+ case 96000: -+ case 192000: -+ return (freq / 48000) * tmds_n->n_48k; -+ default: -+ return -ENOENT; -+ } -+} -+ -+static u32 dw_hdmi_qp_audio_math_diff(unsigned int freq, unsigned int n, -+ unsigned int pixel_clk) -+{ -+ u64 cts = mul_u32_u32(pixel_clk, n); -+ -+ return do_div(cts, 128 * freq); -+} -+ -+static unsigned int dw_hdmi_qp_compute_n(struct dw_hdmi_qp *hdmi, -+ unsigned long pixel_clk, -+ unsigned long freq) -+{ -+ unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); -+ unsigned int max_n = (128 * freq) / 300; -+ unsigned int ideal_n = (128 * freq) / 1000; -+ unsigned int best_n_distance = ideal_n; -+ unsigned int best_n = 0; -+ u64 best_diff = U64_MAX; -+ int n; -+ -+ /* If the ideal N could satisfy the audio math, then just take it */ -+ if (dw_hdmi_qp_audio_math_diff(freq, ideal_n, pixel_clk) == 0) -+ return ideal_n; -+ -+ for (n = min_n; n <= max_n; n++) { -+ u64 diff = dw_hdmi_qp_audio_math_diff(freq, n, pixel_clk); -+ -+ if (diff < best_diff || -+ (diff == best_diff && abs(n - ideal_n) < best_n_distance)) { -+ best_n = n; -+ best_diff = diff; -+ best_n_distance = abs(best_n - ideal_n); -+ } -+ -+ /* -+ * The best N already satisfy the audio math, and also be -+ * the closest value to ideal N, so just cut the loop. -+ */ -+ if (best_diff == 0 && (abs(n - ideal_n) > best_n_distance)) -+ break; -+ } -+ -+ return best_n; -+} -+ -+static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, -+ unsigned long sample_rate) -+{ -+ int n = dw_hdmi_qp_match_tmds_n_table(hdmi, pixel_clk, sample_rate); -+ -+ if (n > 0) -+ return n; -+ -+ dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n", -+ pixel_clk); -+ -+ return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate); -+} -+ -+static unsigned int dw_hdmi_qp_find_cts(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, -+ unsigned long sample_rate) -+{ -+ const struct dw_hdmi_audio_tmds_cts *tmds_cts = NULL; -+ int i; -+ -+ for (i = 0; common_tmds_cts_table[i].tmds != 0; i++) { -+ if (pixel_clk == common_tmds_cts_table[i].tmds) { -+ tmds_cts = &common_tmds_cts_table[i]; -+ break; -+ } -+ } -+ -+ if (!tmds_cts) -+ return 0; -+ -+ switch (sample_rate) { -+ case 32000: -+ return tmds_cts->cts_32k; -+ case 44100: -+ case 88200: -+ case 176400: -+ return tmds_cts->cts_44k1; -+ case 48000: -+ case 96000: -+ case 192000: -+ return tmds_cts->cts_48k; -+ default: -+ return -ENOENT; -+ } -+} -+ -+static void dw_hdmi_qp_set_audio_interface(struct dw_hdmi_qp *hdmi, -+ struct hdmi_codec_daifmt *fmt, -+ struct hdmi_codec_params *hparms) -+{ -+ u32 conf0 = 0; -+ -+ /* Reset the audio data path of the AVP */ -+ dw_hdmi_qp_write(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWINIT_P, GLOBAL_SWRESET_REQUEST); -+ -+ /* Disable AUDS, ACR, AUDI */ -+ dw_hdmi_qp_mod(hdmi, 0, -+ PKTSCHED_ACR_TX_EN | PKTSCHED_AUDS_TX_EN | PKTSCHED_AUDI_TX_EN, -+ PKTSCHED_PKT_EN); -+ -+ /* Clear the audio FIFO */ -+ dw_hdmi_qp_write(hdmi, AUDIO_FIFO_CLR_P, AUDIO_INTERFACE_CONTROL0); -+ -+ /* Select I2S interface as the audio source */ -+ dw_hdmi_qp_mod(hdmi, AUD_IF_I2S, AUD_IF_SEL_MSK, AUDIO_INTERFACE_CONFIG0); -+ -+ /* Enable the active i2s lanes */ -+ switch (hparms->channels) { -+ case 7 ... 8: -+ conf0 |= I2S_LINES_EN(3); -+ fallthrough; -+ case 5 ... 6: -+ conf0 |= I2S_LINES_EN(2); -+ fallthrough; -+ case 3 ... 4: -+ conf0 |= I2S_LINES_EN(1); -+ fallthrough; -+ default: -+ conf0 |= I2S_LINES_EN(0); -+ break; -+ } -+ -+ dw_hdmi_qp_mod(hdmi, conf0, I2S_LINES_EN_MSK, AUDIO_INTERFACE_CONFIG0); -+ -+ /* -+ * Enable bpcuv generated internally for L-PCM, or received -+ * from stream for NLPCM/HBR. -+ */ -+ switch (fmt->bit_fmt) { -+ case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: -+ conf0 = (hparms->channels == 8) ? AUD_HBR : AUD_ASP; -+ conf0 |= I2S_BPCUV_RCV_EN; -+ break; -+ default: -+ conf0 = AUD_ASP | I2S_BPCUV_RCV_DIS; -+ break; -+ } -+ -+ dw_hdmi_qp_mod(hdmi, conf0, I2S_BPCUV_RCV_MSK | AUD_FORMAT_MSK, -+ AUDIO_INTERFACE_CONFIG0); -+ -+ /* Enable audio FIFO auto clear when overflow */ -+ dw_hdmi_qp_mod(hdmi, AUD_FIFO_INIT_ON_OVF_EN, AUD_FIFO_INIT_ON_OVF_MSK, -+ AUDIO_INTERFACE_CONFIG0); -+} -+ -+/* -+ * When transmitting IEC60958 linear PCM audio, these registers allow to -+ * configure the channel status information of all the channel status -+ * bits in the IEC60958 frame. For the moment this configuration is only -+ * used when the I2S audio interface, General Purpose Audio (GPA), -+ * or AHB audio DMA (AHBAUDDMA) interface is active -+ * (for S/PDIF interface this information comes from the stream). -+ */ -+static void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi, -+ u8 *channel_status, bool ref2stream) -+{ -+ /* -+ * AUDPKT_CHSTATUS_OVR0: { RSV, RSV, CS1, CS0 } -+ * AUDPKT_CHSTATUS_OVR1: { CS6, CS5, CS4, CS3 } -+ * -+ * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | -+ * CS0: | Mode | d | c | b | a | -+ * CS1: | Category Code | -+ * CS2: | Channel Number | Source Number | -+ * CS3: | Clock Accuracy | Sample Freq | -+ * CS4: | Ori Sample Freq | Word Length | -+ * CS5: | | CGMS-A | -+ * CS6~CS23: Reserved -+ * -+ * a: use of channel status block -+ * b: linear PCM identification: 0 for lpcm, 1 for nlpcm -+ * c: copyright information -+ * d: additional format information -+ */ -+ -+ if (ref2stream) -+ channel_status[0] |= IEC958_AES0_NONAUDIO; -+ -+ if ((dw_hdmi_qp_read(hdmi, AUDIO_INTERFACE_CONFIG0) & GENMASK(25, 24)) == AUD_HBR) { -+ /* fixup cs for HBR */ -+ channel_status[3] = (channel_status[3] & 0xf0) | IEC958_AES3_CON_FS_768000; -+ channel_status[4] = (channel_status[4] & 0x0f) | IEC958_AES4_CON_ORIGFS_NOTID; -+ } -+ -+ dw_hdmi_qp_write(hdmi, channel_status[0] | (channel_status[1] << 8), -+ AUDPKT_CHSTATUS_OVR0); -+ -+ regmap_bulk_write(hdmi->regm, AUDPKT_CHSTATUS_OVR1, &channel_status[3], 1); -+ -+ if (ref2stream) -+ dw_hdmi_qp_mod(hdmi, 0, -+ AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, -+ AUDPKT_CONTROL0); -+ else -+ dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN, -+ AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, -+ AUDPKT_CONTROL0); -+} -+ -+static void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned long long tmds_char_rate, -+ unsigned int sample_rate) -+{ -+ unsigned int n, cts; -+ -+ n = dw_hdmi_qp_find_n(hdmi, tmds_char_rate, sample_rate); -+ cts = dw_hdmi_qp_find_cts(hdmi, tmds_char_rate, sample_rate); -+ -+ dw_hdmi_qp_set_cts_n(hdmi, cts, n); -+} -+ -+static int dw_hdmi_qp_audio_enable(struct drm_connector *connector, -+ struct drm_bridge *bridge) -+{ -+ struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); -+ -+ if (hdmi->tmds_char_rate) -+ dw_hdmi_qp_mod(hdmi, 0, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE); -+ -+ return 0; -+} -+ -+static int dw_hdmi_qp_audio_prepare(struct drm_connector *connector, -+ struct drm_bridge *bridge, -+ struct hdmi_codec_daifmt *fmt, -+ struct hdmi_codec_params *hparms) -+{ -+ struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); -+ bool ref2stream = false; -+ -+ if (!hdmi->tmds_char_rate) -+ return -ENODEV; -+ -+ if (fmt->bit_clk_provider | fmt->frame_clk_provider) { -+ dev_err(hdmi->dev, "unsupported clock settings\n"); -+ return -EINVAL; -+ } -+ -+ if (fmt->bit_fmt == SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE) -+ ref2stream = true; -+ -+ dw_hdmi_qp_set_audio_interface(hdmi, fmt, hparms); -+ dw_hdmi_qp_set_sample_rate(hdmi, hdmi->tmds_char_rate, hparms->sample_rate); -+ dw_hdmi_qp_set_channel_status(hdmi, hparms->iec.status, ref2stream); -+ drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, &hparms->cea); -+ -+ return 0; -+} -+ -+static void dw_hdmi_qp_audio_disable_regs(struct dw_hdmi_qp *hdmi) -+{ -+ /* -+ * Keep ACR, AUDI, AUDS packet always on to make SINK device -+ * active for better compatibility and user experience. -+ * -+ * This also fix POP sound on some SINK devices which wakeup -+ * from suspend to active. -+ */ -+ dw_hdmi_qp_mod(hdmi, I2S_BPCUV_RCV_DIS, I2S_BPCUV_RCV_MSK, -+ AUDIO_INTERFACE_CONFIG0); -+ dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN, -+ AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, -+ AUDPKT_CONTROL0); -+ -+ dw_hdmi_qp_mod(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, -+ AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE); -+} -+ -+static void dw_hdmi_qp_audio_disable(struct drm_connector *connector, -+ struct drm_bridge *bridge) -+{ -+ struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); -+ -+ drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector); -+ -+ if (hdmi->tmds_char_rate) -+ dw_hdmi_qp_audio_disable_regs(hdmi); -+} -+ - static int dw_hdmi_qp_i2c_read(struct dw_hdmi_qp *hdmi, - unsigned char *buf, unsigned int length) - { -@@ -361,6 +785,51 @@ static int dw_hdmi_qp_config_drm_infoframe(struct dw_hdmi_qp *hdmi, - return 0; - } - -+/* -+ * Static values documented in the TRM -+ * Different values are only used for debug purposes -+ */ -+#define DW_HDMI_QP_AUDIO_INFOFRAME_HB1 0x1 -+#define DW_HDMI_QP_AUDIO_INFOFRAME_HB2 0xa -+ -+static int dw_hdmi_qp_config_audio_infoframe(struct dw_hdmi_qp *hdmi, -+ const u8 *buffer, size_t len) -+{ -+ /* -+ * AUDI_CONTENTS0: { RSV, HB2, HB1, RSV } -+ * AUDI_CONTENTS1: { PB3, PB2, PB1, PB0 } -+ * AUDI_CONTENTS2: { PB7, PB6, PB5, PB4 } -+ * -+ * PB0: CheckSum -+ * PB1: | CT3 | CT2 | CT1 | CT0 | F13 | CC2 | CC1 | CC0 | -+ * PB2: | F27 | F26 | F25 | SF2 | SF1 | SF0 | SS1 | SS0 | -+ * PB3: | F37 | F36 | F35 | F34 | F33 | F32 | F31 | F30 | -+ * PB4: | CA7 | CA6 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 | -+ * PB5: | DM_INH | LSV3 | LSV2 | LSV1 | LSV0 | F52 | F51 | F50 | -+ * PB6~PB10: Reserved -+ * -+ * AUDI_CONTENTS0 default value defined by HDMI specification, -+ * and shall only be changed for debug purposes. -+ */ -+ u32 header_bytes = (DW_HDMI_QP_AUDIO_INFOFRAME_HB1 << 8) | -+ (DW_HDMI_QP_AUDIO_INFOFRAME_HB2 << 16); -+ -+ regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS0, &header_bytes, 1); -+ regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS1, &buffer[3], 1); -+ regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS2, &buffer[4], 1); -+ -+ /* Enable ACR, AUDI, AMD */ -+ dw_hdmi_qp_mod(hdmi, -+ PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN, -+ PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN, -+ PKTSCHED_PKT_EN); -+ -+ /* Enable AUDS */ -+ dw_hdmi_qp_mod(hdmi, PKTSCHED_AUDS_TX_EN, PKTSCHED_AUDS_TX_EN, PKTSCHED_PKT_EN); -+ -+ return 0; -+} -+ - static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_bridge_state *old_state) - { -@@ -382,6 +851,7 @@ static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, - dev_dbg(hdmi->dev, "%s mode=HDMI rate=%llu\n", - __func__, conn_state->hdmi.tmds_char_rate); - op_mode = 0; -+ hdmi->tmds_char_rate = conn_state->hdmi.tmds_char_rate; - } else { - dev_dbg(hdmi->dev, "%s mode=DVI\n", __func__); - op_mode = OPMODE_DVI; -@@ -400,6 +870,8 @@ static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge, - { - struct dw_hdmi_qp *hdmi = bridge->driver_private; - -+ hdmi->tmds_char_rate = 0; -+ - hdmi->phy.ops->disable(hdmi, hdmi->phy.data); - } - -@@ -455,6 +927,13 @@ static int dw_hdmi_qp_bridge_clear_infoframe(struct drm_bridge *bridge, - dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); - break; - -+ case HDMI_INFOFRAME_TYPE_AUDIO: -+ dw_hdmi_qp_mod(hdmi, 0, -+ PKTSCHED_ACR_TX_EN | -+ PKTSCHED_AUDS_TX_EN | -+ PKTSCHED_AUDI_TX_EN, -+ PKTSCHED_PKT_EN); -+ break; - default: - dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type); - } -@@ -477,6 +956,9 @@ static int dw_hdmi_qp_bridge_write_infoframe(struct drm_bridge *bridge, - case HDMI_INFOFRAME_TYPE_DRM: - return dw_hdmi_qp_config_drm_infoframe(hdmi, buffer, len); - -+ case HDMI_INFOFRAME_TYPE_AUDIO: -+ return dw_hdmi_qp_config_audio_infoframe(hdmi, buffer, len); -+ - default: - dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type); - return 0; -@@ -494,6 +976,9 @@ static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs = { - .hdmi_tmds_char_rate_valid = dw_hdmi_qp_bridge_tmds_char_rate_valid, - .hdmi_clear_infoframe = dw_hdmi_qp_bridge_clear_infoframe, - .hdmi_write_infoframe = dw_hdmi_qp_bridge_write_infoframe, -+ .hdmi_audio_startup = dw_hdmi_qp_audio_enable, -+ .hdmi_audio_shutdown = dw_hdmi_qp_audio_disable, -+ .hdmi_audio_prepare = dw_hdmi_qp_audio_prepare, - }; - - static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) -@@ -603,6 +1088,10 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, - if (IS_ERR(hdmi->bridge.ddc)) - return ERR_CAST(hdmi->bridge.ddc); - -+ hdmi->bridge.hdmi_audio_max_i2s_playback_channels = 8; -+ hdmi->bridge.hdmi_audio_dev = dev; -+ hdmi->bridge.hdmi_audio_dai_port = 1; -+ - ret = devm_drm_bridge_add(dev, &hdmi->bridge); - if (ret) - return ERR_PTR(ret); --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-0181-arm64-dts-rockchip-extra-sound.patch b/patch/kernel/rockchip64-6.14/rk3588-0181-arm64-dts-rockchip-extra-sound.patch deleted file mode 100644 index 8643f1d..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-0181-arm64-dts-rockchip-extra-sound.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: palachzzz <7zzzzzzz@mail.ru> -Date: Thu, 27 Feb 2025 23:06:51 +0800 -Subject: [ARCHEOLOGY] RK3588 add HDMI sound, add support for OPi5 Max #7884 - -> X-Git-Archeology: - Revision 0b88561ec332114404ff8075ab6bc2419ca66a47: https://github.com/armbian/build/commit/0b88561ec332114404ff8075ab6bc2419ca66a47 -> X-Git-Archeology: Date: Thu, 27 Feb 2025 23:06:51 +0800 -> X-Git-Archeology: From: palachzzz <7zzzzzzz@mail.ru> -> X-Git-Archeology: Subject: RK3588 add HDMI sound, add support for OPi5 Max #7884 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 17 ++++++++++ - arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 17 ++++++++++ - 2 files changed, 34 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -382,6 +382,22 @@ scmi_reset: protocol@16 { - }; - }; - -+ hdmi0_sound: hdmi0-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <128>; -+ simple-audio-card,name = "hdmi0"; -+ status = "disabled"; -+ -+ simple-audio-card,codec { -+ sound-dai = <&hdmi0>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s5_8ch>; -+ }; -+ }; -+ - pmu-a55 { - compatible = "arm,cortex-a55-pmu"; - interrupts = ; -@@ -1404,6 +1420,7 @@ hdmi0: hdmi@fde80000 { - reset-names = "ref", "hdp"; - rockchip,grf = <&sys_grf>; - rockchip,vo-grf = <&vo1_grf>; -+ #sound-dai-cells = <0>; - status = "disabled"; - - ports { -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi -@@ -30,6 +30,22 @@ hdmi_receiver_cma: hdmi-receiver-cma { - }; - }; - -+ hdmi1_sound: hdmi1-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <128>; -+ simple-audio-card,name = "hdmi1"; -+ status = "disabled"; -+ -+ simple-audio-card,codec { -+ sound-dai = <&hdmi1>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s6_8ch>; -+ }; -+ }; -+ - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; -@@ -221,6 +237,7 @@ hdmi1: hdmi@fdea0000 { - reset-names = "ref", "hdp"; - rockchip,grf = <&sys_grf>; - rockchip,vo-grf = <&vo1_grf>; -+ #sound-dai-cells = <0>; - status = "disabled"; - - ports { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch b/patch/kernel/rockchip64-6.14/rk3588-1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch deleted file mode 100644 index da67392..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Wed, 27 Dec 2023 15:03:57 +0800 -Subject: arm64: dts: rock-5b: Slow down emmc freq and add tsadc node - ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -440,6 +440,7 @@ &sdhci { - no-sdio; - no-sd; - non-removable; -+ max-frequency = <150000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -@@ -495,6 +496,10 @@ flash@0 { - }; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1011-rock5b-hdmi1.patch b/patch/kernel/rockchip64-6.14/rk3588-1011-rock5b-hdmi1.patch deleted file mode 100644 index 1417729..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1011-rock5b-hdmi1.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Thu, 26 Dec 2024 21:47:15 +0100 -Subject: [ARCHEOLOGY] rockchip64-6.13: add hdmi1 support to rock5b - -> X-Git-Archeology: - Revision 12bb4ea7dfd695901aba31ae4b5260398c932a17: https://github.com/armbian/build/commit/12bb4ea7dfd695901aba31ae4b5260398c932a17 -> X-Git-Archeology: Date: Thu, 26 Dec 2024 21:47:15 +0100 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: rockchip64-6.13: add hdmi1 support to rock5b -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 44 +++++++++- - 1 file changed, 42 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -49,6 +49,17 @@ hdmi0_con_in: endpoint { - }; - }; - -+ hdmi1-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi1_con_in: endpoint { -+ remote-endpoint = <&hdmi1_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; -@@ -220,10 +231,32 @@ hdmi0_out_con: endpoint { - }; - }; - -+&hdmi1 { -+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd -+ &hdmim1_tx1_scl &hdmim1_tx1_sda>; -+ status = "okay"; -+}; -+ -+&hdmi1_in { -+ hdmi1_in_vp1: endpoint { -+ remote-endpoint = <&vp1_out_hdmi1>; -+ }; -+}; -+ -+&hdmi1_out { -+ hdmi1_out_con: endpoint { -+ remote-endpoint = <&hdmi1_con_in>; -+ }; -+}; -+ - &hdptxphy0 { - status = "okay"; - }; - -+&hdptxphy1 { -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -@@ -896,11 +929,11 @@ &usb_host2_xhci { - status = "okay"; - }; - --&vop_mmu { -+&vop { - status = "okay"; - }; - --&vop { -+&vop_mmu { - status = "okay"; - }; - -@@ -910,3 +943,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - remote-endpoint = <&hdmi0_in_vp0>; - }; - }; -+ -+&vp1 { -+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -+ reg = ; -+ remote-endpoint = <&hdmi1_in_vp1>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1012-arm64-dts-rockchip-add-hdmi1-support-to-ROCK-5-ITX.patch b/patch/kernel/rockchip64-6.14/rk3588-1012-arm64-dts-rockchip-add-hdmi1-support-to-ROCK-5-ITX.patch deleted file mode 100644 index 4abccfd..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1012-arm64-dts-rockchip-add-hdmi1-support-to-ROCK-5-ITX.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Sat, 15 Feb 2025 23:10:42 +0800 -Subject: arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX - -Enable the HDMI port next to ethernet port. - -Signed-off-by: Jianfeng Liu ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 49 ++++++++++ - 1 file changed, 49 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include "dt-bindings/usb/pd.h" - #include "rk3588.dtsi" - -@@ -89,6 +90,17 @@ fan0: pwm-fan { - pwms = <&pwm14 0 10000 0>; - }; - -+ hdmi1-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi1_con_in: endpoint { -+ remote-endpoint = <&hdmi1_out_con>; -+ }; -+ }; -+ }; -+ - /* M.2 E-KEY */ - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; -@@ -261,6 +273,28 @@ &gpu { - status = "okay"; - }; - -+&hdmi1 { -+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd -+ &hdmim1_tx1_scl &hdmim1_tx1_sda>; -+ status = "okay"; -+}; -+ -+&hdmi1_in { -+ hdmi1_in_vp1: endpoint { -+ remote-endpoint = <&vp1_out_hdmi1>; -+ }; -+}; -+ -+&hdmi1_out { -+ hdmi1_out_con: endpoint { -+ remote-endpoint = <&hdmi1_con_in>; -+ }; -+}; -+ -+&hdptxphy1 { -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -@@ -1208,3 +1242,18 @@ &usbdp_phy1 { - rockchip,dp-lane-mux = <2 3>; - status = "okay"; - }; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp1 { -+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -+ reg = ; -+ remote-endpoint = <&hdmi1_in_vp1>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch b/patch/kernel/rockchip64-6.14/rk3588-1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch deleted file mode 100644 index 2906ea4..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Thu, 6 Jun 2024 23:28:01 +0800 -Subject: arm64: dts: rockchip: Add HDMI support to ArmSoM Sige7 - ---- - arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 30 ++++++++++ - 1 file changed, 30 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3588.dtsi" - - / { -@@ -164,6 +165,20 @@ &gpu { - status = "okay"; - }; - -+&hdmi0 { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdptxphy0 { -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -@@ -723,3 +738,18 @@ &usb_host1_xhci { - dr_mode = "host"; - status = "okay"; - }; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch b/patch/kernel/rockchip64-6.14/rk3588-1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch deleted file mode 100644 index 3cfaee0..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Thu, 6 Jun 2024 23:29:39 +0800 -Subject: arm64: dts: rockchip: Add ap6275p wireless support to ArmSoM Sige7 - ---- - arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 16 ++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -283,6 +283,22 @@ &pcie2x1l0 { - &pcie2x1l1 { - reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x300000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ device_type = "pci"; -+ bus-range = <0x30 0x3f>; -+ -+ wifi: wifi@0,0 { -+ compatible = "pci14e4,449d"; -+ reg = <0x310000 0 0 0 0>; -+ clocks = <&hym8563>; -+ clock-names = "lpo"; -+ }; -+ }; - }; - - /* phy0 - left ethernet port */ --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1040-board-khadas-edge2-add-nodes.patch b/patch/kernel/rockchip64-6.14/rk3588-1040-board-khadas-edge2-add-nodes.patch deleted file mode 100644 index be3c89e..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1040-board-khadas-edge2-add-nodes.patch +++ /dev/null @@ -1,310 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 10 Dec 2024 20:54:33 +0300 -Subject: arm64: dts: rockchip: Add USB-C to Khadas Edge 2 - -Khadas Edge 2 has 2x Type-C port. One just supports PD and -controlled by MCU. The other one supports PD, DP Alt mode and DRD. This -commit adds support for DRD. ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 119 ++++++++++ - 1 file changed, 119 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -6,6 +6,7 @@ - #include - #include - #include -+#include - #include "rk3588s.dtsi" - - / { -@@ -76,6 +77,18 @@ blue_led: led-2 { - }; - }; - -+ vbus5v0_typec: vbus5v0-typec-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vbus5v0_typec"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; -+ vin-supply = <&vcc5v0_sys>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&typec5v_pwren>; -+ }; -+ - vcc3v3_pcie_wl: regulator-vcc3v3-pcie-wl { - compatible = "regulator-fixed"; - enable-active-high; -@@ -224,6 +237,56 @@ regulator-state-mem { - &i2c2 { - status = "okay"; - -+ usbc0: usb-typec@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usbc0_int>; -+ vbus-supply = <&vbus5v0_typec>; -+ status = "okay"; -+ -+ usb_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ data-role = "dual"; -+ power-role = "dual"; -+ try-power-role = "source"; -+ op-sink-microwatt = <1000000>; -+ sink-pdos = ; -+ source-pdos = ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usbc0_orien_sw: endpoint { -+ remote-endpoint = <&usbdp_phy0_orientation_switch>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ usbc0_role_sw: endpoint { -+ remote-endpoint = <&dwc3_0_role_switch>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ dp_altmode_mux: endpoint { -+ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; -+ }; -+ }; -+ }; -+ }; -+ }; -+ - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; -@@ -256,6 +319,16 @@ vcc5v0_host_en: vcc5v0-host-en { - }; - }; - -+ usb-typec { -+ usbc0_int: usbc0-int { -+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ typec5v_pwren: typec5v-pwren { -+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - ir-receiver { - ir_receiver_pin: ir-receiver-pin { - rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -697,6 +770,14 @@ &uart9 { - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ - &u2phy2 { - status = "okay"; - }; -@@ -723,6 +804,44 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usbdp_phy0 { -+ orientation-switch; -+ mode-switch; -+ sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; -+ sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usbdp_phy0_orientation_switch: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_orien_sw>; -+ }; -+ -+ usbdp_phy0_dp_altmode_mux: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&dp_altmode_mux>; -+ }; -+ }; -+}; -+ -+&usb_host0_xhci { -+ usb-role-switch; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ dwc3_0_role_switch: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_role_sw>; -+ }; -+ }; -+}; -+ -+ - &usb_host1_ehci { - status = "okay"; - }; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 10 Dec 2024 20:57:42 +0300 -Subject: arm64: dts: rockchip: Add bluetooth support to Khadas Edge 2 - ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 18 +++++++++- - 1 file changed, 17 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -766,8 +766,24 @@ &uart2 { - - &uart9 { - pinctrl-names = "default"; -- pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; -+ pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn &uart9m2_rtsn>; - status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ clocks = <&hym8563>; -+ clock-names = "lpo"; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ interrupt-names = "host-wakeup"; -+ device-wakeup-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ max-speed = <1500000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_wake_host_irq &bt_wake_pin &bt_reset_pin>; -+ vbat-supply = <&vcc_3v3_s3>; -+ vddio-supply = <&vcc_1v8_s3>; -+ }; - }; - - &u2phy0 { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 10 Dec 2024 21:00:25 +0300 -Subject: arm64: dts: rockchip: Add HDMI & VOP2 to Khadas Edge 2 - ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 47 ++++++++++ - 1 file changed, 47 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -6,6 +6,7 @@ - #include - #include - #include -+#include - #include - #include "rk3588s.dtsi" - -@@ -43,6 +44,17 @@ ir-receiver { - pinctrl-0 = <&ir_receiver_pin>; - }; - -+ hdmi0-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi0_con_in: endpoint { -+ remote-endpoint = <&hdmi0_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "pwm-leds"; - -@@ -194,6 +206,26 @@ &gpu { - status = "okay"; - }; - -+&hdmi0 { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdmi0_out { -+ hdmi0_out_con: endpoint { -+ remote-endpoint = <&hdmi0_con_in>; -+ }; -+}; -+ -+&hdptxphy0 { -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -@@ -869,3 +901,18 @@ &usb_host1_ohci { - &usb_host2_xhci { - status = "okay"; - }; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1041-board-khadas-edge2-mcu.patch b/patch/kernel/rockchip64-6.14/rk3588-1041-board-khadas-edge2-mcu.patch deleted file mode 100644 index 73dc9c5..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1041-board-khadas-edge2-mcu.patch +++ /dev/null @@ -1,441 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 6 Mar 2024 00:09:25 +0300 -Subject: mfd: khadas-mcu: add Edge2 registers - ---- - drivers/mfd/khadas-mcu.c | 8 +++- - include/linux/mfd/khadas-mcu.h | 24 ++++++++++ - 2 files changed, 30 insertions(+), 2 deletions(-) - -diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c -index 111111111111..222222222222 100644 ---- a/drivers/mfd/khadas-mcu.c -+++ b/drivers/mfd/khadas-mcu.c -@@ -26,6 +26,10 @@ static bool khadas_mcu_reg_volatile(struct device *dev, unsigned int reg) - case KHADAS_MCU_CHECK_USER_PASSWD_REG: - case KHADAS_MCU_WOL_INIT_START_REG: - case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG: -+ case KHADAS_MCU_LED_ON_RAM_REG: -+ case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2: -+ case KHADAS_MCU_WDT_EN_REG: -+ case KHADAS_MCU_SYS_RST_REG: - return true; - default: - return false; -@@ -69,14 +73,14 @@ static const struct regmap_config khadas_mcu_regmap_config = { - .reg_bits = 8, - .reg_stride = 1, - .val_bits = 8, -- .max_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG, -+ .max_register = KHADAS_MCU_SYS_RST_REG, - .volatile_reg = khadas_mcu_reg_volatile, - .writeable_reg = khadas_mcu_reg_writeable, - .cache_type = REGCACHE_MAPLE, - }; - - static struct mfd_cell khadas_mcu_fan_cells[] = { -- /* VIM1/2 Rev13+ and VIM3 only */ -+ /* VIM1/2 Rev13+, VIM3 and Edge2 only */ - { .name = "khadas-mcu-fan-ctrl", }, - }; - -diff --git a/include/linux/mfd/khadas-mcu.h b/include/linux/mfd/khadas-mcu.h -index 111111111111..222222222222 100644 ---- a/include/linux/mfd/khadas-mcu.h -+++ b/include/linux/mfd/khadas-mcu.h -@@ -35,26 +35,45 @@ - #define KHADAS_MCU_FACTORY_TEST_REG 0x16 /* R */ - #define KHADAS_MCU_BOOT_MODE_REG 0x20 /* RW */ - #define KHADAS_MCU_BOOT_EN_WOL_REG 0x21 /* RW */ -+#define KHADAS_MCU_BOOT_EN_DCIN_REG_V2 0x21 /* RW */ - #define KHADAS_MCU_BOOT_EN_RTC_REG 0x22 /* RW */ - #define KHADAS_MCU_BOOT_EN_EXP_REG 0x23 /* RW */ -+#define KHADAS_MCU_LED_MODE_ON_REG_V2 0x23 /* RW */ -+#define KHADAS_MCU_LED_MODE_OFF_REG_V2 0x24 /* RW */ - #define KHADAS_MCU_BOOT_EN_IR_REG 0x24 /* RW */ - #define KHADAS_MCU_BOOT_EN_DCIN_REG 0x25 /* RW */ -+#define KHADAS_MCU_RGB_ON_R_REG 0x25 /* RW */ -+#define KHADAS_MCU_RGB_ON_G_REG 0x26 /* RW */ - #define KHADAS_MCU_BOOT_EN_KEY_REG 0x26 /* RW */ -+#define KHADAS_MCU_RGB_ON_B_REG 0x27 /* RW */ - #define KHADAS_MCU_KEY_MODE_REG 0x27 /* RW */ -+#define KHADAS_MCU_RGB_OFF_R_REG 0x28 /* RW */ - #define KHADAS_MCU_LED_MODE_ON_REG 0x28 /* RW */ -+#define KHADAS_MCU_RGB_OFF_G_REG 0x29 /* RW */ - #define KHADAS_MCU_LED_MODE_OFF_REG 0x29 /* RW */ -+#define KHADAS_MCU_RGB_OFF_B_REG 0x2a /* RW */ - #define KHADAS_MCU_SHUTDOWN_NORMAL_REG 0x2c /* RW */ - #define KHADAS_MCU_MAC_SWITCH_REG 0x2d /* RW */ -+#define KHADAS_MCU_REST_CONF_REG 0x2e /* RW */ - #define KHADAS_MCU_MCU_SLEEP_MODE_REG 0x2e /* RW */ -+#define KHADAS_MCU_BOOT_EN_IR_REG_V2 0x2f /* RW */ - #define KHADAS_MCU_IR_CODE1_0_REG 0x2f /* RW */ - #define KHADAS_MCU_IR_CODE1_1_REG 0x30 /* RW */ -+#define KHADAS_MCU_IR1_CUST1_REG 0x30 /* RW */ - #define KHADAS_MCU_IR_CODE1_2_REG 0x31 /* RW */ -+#define KHADAS_MCU_IR1_CUST2_REG 0x31 /* RW */ - #define KHADAS_MCU_IR_CODE1_3_REG 0x32 /* RW */ -+#define KHADAS_MCU_IR1_ORDER1_REG 0x32 /* RW */ - #define KHADAS_MCU_USB_PCIE_SWITCH_REG 0x33 /* RW */ -+#define KHADAS_MCU_IR1_ORDER2_REG 0x33 /* RW */ -+#define KHADAS_MCU_IR2_CUST1_REG 0x34 /* RW */ - #define KHADAS_MCU_IR_CODE2_0_REG 0x34 /* RW */ - #define KHADAS_MCU_IR_CODE2_1_REG 0x35 /* RW */ -+#define KHADAS_MCU_IR2_CUST2_REG 0x35 /* RW */ - #define KHADAS_MCU_IR_CODE2_2_REG 0x36 /* RW */ -+#define KHADAS_MCU_IR2_ORDER1_REG 0x36 /* RW */ - #define KHADAS_MCU_IR_CODE2_3_REG 0x37 /* RW */ -+#define KHADAS_MCU_IR2_ORDER2_REG 0x36 /* RW */ - #define KHADAS_MCU_PASSWD_USER_0_REG 0x40 /* RW */ - #define KHADAS_MCU_PASSWD_USER_1_REG 0x41 /* RW */ - #define KHADAS_MCU_PASSWD_USER_2_REG 0x42 /* RW */ -@@ -69,6 +88,10 @@ - #define KHADAS_MCU_SHUTDOWN_NORMAL_STATUS_REG 0x86 /* RO */ - #define KHADAS_MCU_WOL_INIT_START_REG 0x87 /* WO */ - #define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG 0x88 /* WO */ -+#define KHADAS_MCU_LED_ON_RAM_REG 0x89 /* WO */ -+#define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2 0x8A /* WO */ -+#define KHADAS_MCU_WDT_EN_REG 0x8B /* WO */ -+#define KHADAS_MCU_SYS_RST_REG 0x91 /* WO */ - - enum { - KHADAS_BOARD_VIM1 = 0x1, -@@ -76,6 +99,7 @@ enum { - KHADAS_BOARD_VIM3, - KHADAS_BOARD_EDGE = 0x11, - KHADAS_BOARD_EDGE_V, -+ KHADAS_BOARD_EDGE2, - }; - - /** --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 6 Mar 2024 00:09:58 +0300 -Subject: mfd: khadas-mcu: drop unused code - ---- - drivers/mfd/khadas-mcu.c | 11 ---------- - 1 file changed, 11 deletions(-) - -diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c -index 111111111111..222222222222 100644 ---- a/drivers/mfd/khadas-mcu.c -+++ b/drivers/mfd/khadas-mcu.c -@@ -84,10 +84,6 @@ static struct mfd_cell khadas_mcu_fan_cells[] = { - { .name = "khadas-mcu-fan-ctrl", }, - }; - --static struct mfd_cell khadas_mcu_cells[] = { -- { .name = "khadas-mcu-user-mem", }, --}; -- - static int khadas_mcu_probe(struct i2c_client *client) - { - struct device *dev = &client->dev; -@@ -109,13 +105,6 @@ static int khadas_mcu_probe(struct i2c_client *client) - return ret; - } - -- ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, -- khadas_mcu_cells, -- ARRAY_SIZE(khadas_mcu_cells), -- NULL, 0, NULL); -- if (ret) -- return ret; -- - if (of_property_present(dev->of_node, "#cooling-cells")) - return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, - khadas_mcu_fan_cells, --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 6 Mar 2024 00:13:10 +0300 -Subject: thermal: khadas_mcu_fan: add support for Khadas Edge 2 - ---- - drivers/thermal/khadas_mcu_fan.c | 77 +++++++++- - 1 file changed, 73 insertions(+), 4 deletions(-) - -diff --git a/drivers/thermal/khadas_mcu_fan.c b/drivers/thermal/khadas_mcu_fan.c -index 111111111111..222222222222 100644 ---- a/drivers/thermal/khadas_mcu_fan.c -+++ b/drivers/thermal/khadas_mcu_fan.c -@@ -15,10 +15,16 @@ - #include - - #define MAX_LEVEL 3 -+#define MAX_SPEED 0x64 - - struct khadas_mcu_fan_ctx { - struct khadas_mcu *mcu; - unsigned int level; -+ -+ unsigned int fan_max_level; -+ unsigned int fan_register; -+ unsigned int *fan_cooling_levels; -+ - struct thermal_cooling_device *cdev; - }; - -@@ -26,9 +32,21 @@ static int khadas_mcu_fan_set_level(struct khadas_mcu_fan_ctx *ctx, - unsigned int level) - { - int ret; -+ unsigned int write_level = level; -+ -+ if (level > ctx->fan_max_level) -+ return -EINVAL; -+ -+ if (ctx->fan_cooling_levels != NULL) { -+ write_level = ctx->fan_cooling_levels[level]; -+ -+ if (write_level > MAX_SPEED) -+ return -EINVAL; -+ } -+ -+ ret = regmap_write(ctx->mcu->regmap, ctx->fan_register, -+ write_level); - -- ret = regmap_write(ctx->mcu->regmap, KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG, -- level); - if (ret) - return ret; - -@@ -40,7 +58,9 @@ static int khadas_mcu_fan_set_level(struct khadas_mcu_fan_ctx *ctx, - static int khadas_mcu_fan_get_max_state(struct thermal_cooling_device *cdev, - unsigned long *state) - { -- *state = MAX_LEVEL; -+ struct khadas_mcu_fan_ctx *ctx = cdev->devdata; -+ -+ *state = ctx->fan_max_level; - - return 0; - } -@@ -61,7 +81,7 @@ khadas_mcu_fan_set_cur_state(struct thermal_cooling_device *cdev, - { - struct khadas_mcu_fan_ctx *ctx = cdev->devdata; - -- if (state > MAX_LEVEL) -+ if (state > ctx->fan_max_level) - return -EINVAL; - - if (state == ctx->level) -@@ -76,6 +96,48 @@ static const struct thermal_cooling_device_ops khadas_mcu_fan_cooling_ops = { - .set_cur_state = khadas_mcu_fan_set_cur_state, - }; - -+// Khadas Edge 2 sets fan level by passing fan speed(0-100). So we need different logic here like pwm-fan cooling-levels. -+// This is optional and just necessary for Edge 2. -+static int khadas_mcu_fan_get_cooling_data_edge2(struct khadas_mcu_fan_ctx *ctx, struct device *dev) { -+ struct device_node *np = ctx->mcu->dev->of_node; -+ int num, i, ret; -+ -+ if (!of_property_present(np, "cooling-levels")) -+ return 0; -+ -+ ret = of_property_count_u32_elems(np, "cooling-levels"); -+ if (ret <= 0) { -+ dev_err(dev, "Wrong data!\n"); -+ return ret ? : -EINVAL; -+ } -+ -+ num = ret; -+ ctx->fan_cooling_levels = devm_kcalloc(dev, num, sizeof(u32), -+ GFP_KERNEL); -+ if (!ctx->fan_cooling_levels) -+ return -ENOMEM; -+ -+ ret = of_property_read_u32_array(np, "cooling-levels", -+ ctx->fan_cooling_levels, num); -+ if (ret) { -+ dev_err(dev, "Property 'cooling-levels' cannot be read!\n"); -+ return ret; -+ } -+ -+ for (i = 0; i < num; i++) { -+ if (ctx->fan_cooling_levels[i] > MAX_SPEED) { -+ dev_err(dev, "PWM fan state[%d]:%d > %d\n", i, -+ ctx->fan_cooling_levels[i], MAX_SPEED); -+ return -EINVAL; -+ } -+ } -+ -+ ctx->fan_max_level = num - 1; -+ ctx->fan_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2; -+ -+ return 0; -+} -+ - static int khadas_mcu_fan_probe(struct platform_device *pdev) - { - struct khadas_mcu *mcu = dev_get_drvdata(pdev->dev.parent); -@@ -90,6 +152,13 @@ static int khadas_mcu_fan_probe(struct platform_device *pdev) - ctx->mcu = mcu; - platform_set_drvdata(pdev, ctx); - -+ ctx->fan_max_level = MAX_LEVEL; -+ ctx->fan_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG; -+ -+ ret = khadas_mcu_fan_get_cooling_data_edge2(ctx, dev); -+ if (ret) -+ return ret; -+ - cdev = devm_thermal_of_cooling_device_register(dev->parent, - dev->parent->of_node, "khadas-mcu-fan", ctx, - &khadas_mcu_fan_cooling_ops); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 6 Mar 2024 00:14:58 +0300 -Subject: dt-bindings: mfd: khadas-mcu: add cooling-levels property - ---- - Documentation/devicetree/bindings/mfd/khadas,mcu.yaml | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml -+++ b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml -@@ -11,7 +11,7 @@ maintainers: - - description: | - Khadas embeds a microcontroller on their VIM and Edge boards adding some -- system feature as PWM Fan control (for VIM2 rev14 or VIM3), User memory -+ system feature as PWM Fan control (for VIM2 rev14, VIM3, Edge2), User memory - storage, IR/Key resume control, system power LED control and more. - - properties: -@@ -22,6 +22,11 @@ properties: - "#cooling-cells": # Only needed for boards having FAN control feature - const: 2 - -+ cooling-levels: -+ description: Max speed of PWM fan. This property is necessary for Khadas Edge 2. -+ items: -+ maximum: 100 -+ - reg: - maxItems: 1 - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 6 Mar 2024 00:17:58 +0300 -Subject: arm64: dts: rockchip: Add MCU to Khadas Edge 2 - ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -326,6 +326,13 @@ hym8563: rtc@51 { - clock-output-names = "hym8563"; - wakeup-source; - }; -+ -+ khadas_mcu: system-controller@18 { -+ compatible = "khadas,mcu"; -+ reg = <0x18>; -+ cooling-levels = <0 50 72 100>; -+ #cooling-cells = <2>; -+ }; - }; - - &pinctrl { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Mon, 25 Mar 2024 22:41:26 +0300 -Subject: arm64: dts: rockchip: Add automatic fan control to Khadas Edge 2 - ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 56 ++++++++++ - 1 file changed, 56 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -335,6 +335,62 @@ khadas_mcu: system-controller@18 { - }; - }; - -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <45000>; -+ hysteresis = <5000>; -+ type = "active"; -+ }; -+ -+ package_fan1: package-fan1 { -+ temperature = <55000>; -+ hysteresis = <5000>; -+ type = "active"; -+ }; -+ -+ package_fan2: package-fan2 { -+ temperature = <60000>; -+ hysteresis = <5000>; -+ type = "active"; -+ }; -+ -+ package_fan3: package-fan3 { -+ temperature = <70000>; -+ hysteresis = <5000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&package_fan0>; -+ cooling-device = <&khadas_mcu 0 1>; -+ contribution = <1024>; -+ }; -+ -+ map1 { -+ trip = <&package_fan1>; -+ cooling-device = <&khadas_mcu 1 2>; -+ contribution = <1024>; -+ }; -+ -+ map2 { -+ trip = <&package_fan2>; -+ cooling-device = <&khadas_mcu 2 3>; -+ contribution = <1024>; -+ }; -+ -+ map3 { -+ trip = <&package_fan3>; -+ cooling-device = <&khadas_mcu 3 THERMAL_NO_LIMIT>; -+ contribution = <1024>; -+ }; -+ }; -+}; -+ - &pinctrl { - vdd_sd { - vdd_sd_en: vdd-sd-en { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1051-board-nanopc-t6-fan-support.patch b/patch/kernel/rockchip64-6.14/rk3588-1051-board-nanopc-t6-fan-support.patch deleted file mode 100644 index 2c26691..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1051-board-nanopc-t6-fan-support.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: SuperKali -Date: Thu, 20 Mar 2025 19:46:09 +0000 -Subject: Adding FAN support for NanoPC T6 & LTS - -Signed-off-by: SuperKali ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 36 ++++++++++ - 1 file changed, 36 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -78,6 +78,14 @@ usr_led: led-1 { - }; - }; - -+ fan0: pwm-fan { -+ compatible = "pwm-fan"; -+ #cooling-cells = <2>; -+ cooling-levels = <100 160 190 200 215 235 255>; -+ pwms = <&pwm1 0 50000 0>; -+ fan-supply = <&vcc5v0_sys>; -+ }; -+ - sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; -@@ -531,6 +539,34 @@ i2s0_8ch_p0_0: endpoint { - }; - }; - -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ package_fan1: package-fan1 { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map1 { -+ trip = <&package_fan0>; -+ cooling-device = <&fan0 THERMAL_NO_LIMIT 1>; -+ }; -+ map2 { -+ trip = <&package_fan1>; -+ cooling-device = <&fan0 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ - &pcie2x1l0 { - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1052-board-nanopc-t6-fix-usb3-a.patch b/patch/kernel/rockchip64-6.14/rk3588-1052-board-nanopc-t6-fix-usb3-a.patch deleted file mode 100644 index 2b7268b..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1052-board-nanopc-t6-fix-usb3-a.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: SuperKali -Date: Thu, 20 Mar 2025 19:58:19 +0000 -Subject: Fixing USB-A 3.0 on NanoPC T6 - -Signed-off-by: SuperKali ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -1056,6 +1056,7 @@ &u2phy0 { - }; - - &u2phy0_otg { -+ phy-supply = <&vbus5v0_usb>; - status = "okay"; - }; - -@@ -1121,6 +1122,7 @@ &usb_host0_ohci { - - &usb_host0_xhci { - dr_mode = "host"; -+ extcon = <&u2phy0>; - status = "okay"; - usb-role-switch; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1053-board-nanopc-t6-hdmi1-and-audio-support.patch b/patch/kernel/rockchip64-6.14/rk3588-1053-board-nanopc-t6-hdmi1-and-audio-support.patch deleted file mode 100644 index e690e57..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1053-board-nanopc-t6-hdmi1-and-audio-support.patch +++ /dev/null @@ -1,109 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: SuperKali -Date: Thu, 20 Mar 2025 19:51:46 +0000 -Subject: Add HDMI1 support and Audio for NanoPC T6 & LTS - -Signed-off-by: SuperKali ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 56 ++++++++++ - 1 file changed, 56 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -52,6 +52,18 @@ hdmi0_con_in: endpoint { - }; - }; - -+ hdmi1-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi1_con_in: endpoint { -+ remote-endpoint = <&hdmi1_out_con>; -+ }; -+ }; -+ }; -+ -+ - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; -@@ -356,6 +368,10 @@ &hdmi0 { - status = "okay"; - }; - -+&hdmi0_sound { -+ status = "okay"; -+}; -+ - &hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; -@@ -368,10 +384,34 @@ hdmi0_out_con: endpoint { - }; - }; - -+&hdmi1 { -+ status = "okay"; -+}; -+ -+&hdmi1_in { -+ hdmi1_in_vp1: endpoint { -+ remote-endpoint = <&vp1_out_hdmi1>; -+ }; -+}; -+ -+&hdmi1_out { -+ hdmi1_out_con: endpoint { -+ remote-endpoint = <&hdmi1_con_in>; -+ }; -+}; -+ -+&hdmi1_sound { -+ status = "okay"; -+}; -+ - &hdptxphy0 { - status = "okay"; - }; - -+&hdptxphy1 { -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -@@ -539,6 +579,15 @@ i2s0_8ch_p0_0: endpoint { - }; - }; - -+&i2s5_8ch { -+ status = "okay"; -+}; -+ -+&i2s6_8ch { -+ status = "okay"; -+}; -+ -+ - &package_thermal { - polling-delay = <1000>; - -@@ -1160,3 +1209,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - remote-endpoint = <&hdmi0_in_vp0>; - }; - }; -+ -+&vp1 { -+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -+ reg = ; -+ remote-endpoint = <&hdmi1_in_vp1>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch b/patch/kernel/rockchip64-6.14/rk3588-1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch deleted file mode 100644 index 83a88e0..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Joshua Riek -Date: Thu, 22 Aug 2024 22:32:47 -0400 -Subject: arm64: dts: rockchip: Enable automatic fan control on the Turing RK1 - ---- - arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 32 +++++++++- - 1 file changed, 31 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -@@ -23,7 +23,7 @@ aliases { - - fan: pwm-fan { - compatible = "pwm-fan"; -- cooling-levels = <0 25 95 145 195 255>; -+ cooling-levels = <0 120 150 180 210 240 255>; - fan-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0m2_pins &fan_int>; -@@ -266,6 +266,36 @@ map5 { - }; - }; - -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ package_fan1: package-fan1 { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map1 { -+ trip = <&package_fan0>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map2 { -+ trip = <&package_fan1>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ - &pcie2x1l1 { - linux,pci-domain = <1>; - pinctrl-names = "default"; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch b/patch/kernel/rockchip64-6.14/rk3588-1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch deleted file mode 100644 index ebd9b0f..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Joshua Riek -Date: Wed, 7 Aug 2024 14:12:21 -0400 -Subject: arm64: dts: rockchip: Add missing hym8563 clock-frequency for Turing - RK1 - -Signed-off-by: Joshua Riek ---- - arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -@@ -191,6 +191,7 @@ hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; -+ clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1071-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch b/patch/kernel/rockchip64-6.14/rk3588-1071-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch deleted file mode 100644 index e813522..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1071-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch +++ /dev/null @@ -1,157 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 10 Dec 2024 21:10:02 +0300 -Subject: arm64: dts: rockchip: mark led as heartbeat indicator for Orange Pi - 5+ - ---- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi -@@ -93,7 +93,7 @@ led_blue_pwm: led-1 { - - led_green_pwm: led-2 { - color = ; -- function = LED_FUNCTION_INDICATOR; -+ function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <2>; - max-brightness = <255>; - }; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 10 Dec 2024 21:11:02 +0300 -Subject: arm64: dts: rockchip: add bluetooth rfkill node for Orange Pi 5+ - ---- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -@@ -238,6 +238,13 @@ ir_receiver_pin: ir-receiver-pin { - }; - }; - -+ rfkill-bt { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-m2-bt"; -+ radio-type = "bluetooth"; -+ shutdown-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ }; -+ - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 10 Dec 2024 21:11:43 +0300 -Subject: arm64: dts: rockchip: fix hym8563 pinctrl for Orange Pi 5+ - ---- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -@@ -222,7 +222,7 @@ &pcie2x1l2 { - &pinctrl { - hym8563 { - hym8563_int: hym8563-int { -- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Thu, 26 Dec 2024 23:45:39 +0300 -Subject: arm64: dts: rockchip: add support for HDMI1 port to OPi5+ - ---- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 38 ++++++++++ - 1 file changed, 38 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -@@ -26,6 +26,17 @@ hdmi0_con_in: endpoint { - }; - }; - -+ hdmi1-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi1_con_in: endpoint { -+ remote-endpoint = <&hdmi1_out_con>; -+ }; -+ }; -+ }; -+ - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; -@@ -125,10 +136,30 @@ hdmi0_out_con: endpoint { - }; - }; - -+&hdmi1 { -+ status = "okay"; -+}; -+ -+&hdmi1_in { -+ hdmi1_in_vp1: endpoint { -+ remote-endpoint = <&vp1_out_hdmi1>; -+ }; -+}; -+ -+&hdmi1_out { -+ hdmi1_out_con: endpoint { -+ remote-endpoint = <&hdmi1_con_in>; -+ }; -+}; -+ - &hdptxphy0 { - status = "okay"; - }; - -+&hdptxphy1 { -+ status = "okay"; -+}; -+ - &hym8563 { - interrupt-parent = <&gpio0>; - interrupts = ; -@@ -349,3 +380,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - remote-endpoint = <&hdmi0_in_vp0>; - }; - }; -+ -+&vp1 { -+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -+ reg = ; -+ remote-endpoint = <&hdmi1_in_vp1>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1072-arm64-dts-rockchip-add-AP6275P-wifi-to-Orange-Pi-5B.patch b/patch/kernel/rockchip64-6.14/rk3588-1072-arm64-dts-rockchip-add-AP6275P-wifi-to-Orange-Pi-5B.patch deleted file mode 100644 index 4e97ad9..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1072-arm64-dts-rockchip-add-AP6275P-wifi-to-Orange-Pi-5B.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 10 Dec 2024 21:56:10 +0300 -Subject: arm64: dts: rockchip: add AP6275P wifi to Orange Pi 5B - ---- - arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts | 33 ++++++++++ - 1 file changed, 33 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts -@@ -12,6 +12,39 @@ aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - }; -+ -+ vcc3v3_pcie20: regulator-vcc3v3-pcie20 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc3v3_pcie20"; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&pcie2x1l2 { -+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie20>; -+ status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x400000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ device_type = "pci"; -+ bus-range = <0x40 0x4f>; -+ wifi: wifi@0,0 { -+ compatible = "pci14e4,449d"; -+ reg = <0x410000 0 0 0 0>; -+ clocks = <&hym8563>; -+ clock-names = "lpo"; -+ }; -+ }; - }; - - &sdhci { --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1080-arm64-dts-rockchip-add-USB3-support-to-NanoPi-R6-ser.patch b/patch/kernel/rockchip64-6.14/rk3588-1080-arm64-dts-rockchip-add-USB3-support-to-NanoPi-R6-ser.patch deleted file mode 100644 index 5364c06..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1080-arm64-dts-rockchip-add-USB3-support-to-NanoPi-R6-ser.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 10 Dec 2024 22:03:19 +0300 -Subject: arm64: dts: rockchip: add USB3 support to NanoPi R6 series boards - ---- - arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 19 ++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi -@@ -784,6 +784,15 @@ &u2phy0_otg { - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ phy-supply = <&vcc5v0_usb_otg0>; -+ status = "okay"; -+}; -+ - &u2phy2 { - status = "okay"; - }; -@@ -815,6 +824,16 @@ &usbdp_phy0 { - status = "okay"; - }; - -+&usb_host0_xhci { -+ dr_mode = "host"; -+ extcon = <&u2phy0>; -+ status = "okay"; -+}; -+ -+&usbdp_phy0 { -+ status = "okay"; -+}; -+ - &vop { - status = "okay"; - }; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1090-arm64-dts-rockchip-Add-HDMI-RX-config-to-FriendlyElec-CM3588.patch b/patch/kernel/rockchip64-6.14/rk3588-1090-arm64-dts-rockchip-Add-HDMI-RX-config-to-FriendlyElec-CM3588.patch deleted file mode 100644 index 33dd1da..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1090-arm64-dts-rockchip-Add-HDMI-RX-config-to-FriendlyElec-CM3588.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Tim Surber -Date: Fri, 3 Jan 2025 23:12:26 +0100 -Subject: Add HDMI-RX configuration for friendlyelec-cm3588 - -Signed-off-by: Tim Surber ---- - arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts | 14 ++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts -@@ -101,6 +101,13 @@ hdmi0_con_in: endpoint { - }; - }; - -+ hdmi_receiver@fdee0000 { -+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; -+ power-domains = <&power RK3588_PD_VO1>; -+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; -+ hpd-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; -+ }; -+ - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; -@@ -478,6 +485,13 @@ key1_pin: key1-pin { - }; - }; - -+ -+ hdmirx { -+ hdmirx_hpd: hdmirx-5v-detection { -+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pcie { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1100-arm64-dts-rockchip-opi5-max-add-2nd-hdmi.patch b/patch/kernel/rockchip64-6.14/rk3588-1100-arm64-dts-rockchip-opi5-max-add-2nd-hdmi.patch deleted file mode 100644 index d0451f1..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1100-arm64-dts-rockchip-opi5-max-add-2nd-hdmi.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: palachzzz <7zzzzzzz@mail.ru> -Date: Thu, 27 Feb 2025 23:06:51 +0800 -Subject: [ARCHEOLOGY] RK3588 add HDMI sound, add support for OPi5 Max #7884 - -> X-Git-Archeology: - Revision 0b88561ec332114404ff8075ab6bc2419ca66a47: https://github.com/armbian/build/commit/0b88561ec332114404ff8075ab6bc2419ca66a47 -> X-Git-Archeology: Date: Thu, 27 Feb 2025 23:06:51 +0800 -> X-Git-Archeology: From: palachzzz <7zzzzzzz@mail.ru> -> X-Git-Archeology: Subject: RK3588 add HDMI sound, add support for OPi5 Max #7884 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts | 42 ++++++++++ - 1 file changed, 42 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts -@@ -21,6 +21,17 @@ hdmi0_con_in: endpoint { - }; - }; - }; -+ -+ hdmi1-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi1_con_in: endpoint { -+ remote-endpoint = <&hdmi1_out_con>; -+ }; -+ }; -+ }; - }; - - &hdmi0 { -@@ -58,3 +69,34 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - remote-endpoint = <&hdmi0_in_vp0>; - }; - }; -+ -+&hdmi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd -+ &hdmim1_tx1_scl &hdmim1_tx1_sda>; -+ status = "okay"; -+}; -+ -+&hdmi1_in { -+ hdmi1_in_vp1: endpoint { -+ remote-endpoint = <&vp1_out_hdmi1>; -+ }; -+}; -+ -+&hdmi1_out { -+ hdmi1_out_con: endpoint { -+ remote-endpoint = <&hdmi1_con_in>; -+ }; -+}; -+ -+&hdptxphy1 { -+ status = "okay"; -+}; -+ -+ -+&vp1 { -+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { -+ reg = ; -+ remote-endpoint = <&hdmi1_in_vp1>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1101-arm64-dts-rockchip-opi5-max-add-hdmi-sound.patch b/patch/kernel/rockchip64-6.14/rk3588-1101-arm64-dts-rockchip-opi5-max-add-hdmi-sound.patch deleted file mode 100644 index e37e5f1..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1101-arm64-dts-rockchip-opi5-max-add-hdmi-sound.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: palachzzz <7zzzzzzz@mail.ru> -Date: Thu, 27 Feb 2025 23:06:51 +0800 -Subject: [ARCHEOLOGY] RK3588 add HDMI sound, add support for OPi5 Max #7884 - -> X-Git-Archeology: - Revision 0b88561ec332114404ff8075ab6bc2419ca66a47: https://github.com/armbian/build/commit/0b88561ec332114404ff8075ab6bc2419ca66a47 -> X-Git-Archeology: Date: Thu, 27 Feb 2025 23:06:51 +0800 -> X-Git-Archeology: From: palachzzz <7zzzzzzz@mail.ru> -> X-Git-Archeology: Subject: RK3588 add HDMI sound, add support for OPi5 Max #7884 -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts | 16 ++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts -@@ -38,6 +38,22 @@ &hdmi0 { - status = "okay"; - }; - -+&hdmi0_sound { -+ status = "okay"; -+}; -+ -+&hdmi1_sound { -+ status = "okay"; -+}; -+ -+&i2s5_8ch { -+ status = "okay"; -+}; -+ -+&i2s6_8ch { -+ status = "okay"; -+}; -+ - &hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/rk3588-1102-arm64-dts-rockchip-Rock-5B-add-hdmi-sound.patch b/patch/kernel/rockchip64-6.14/rk3588-1102-arm64-dts-rockchip-Rock-5B-add-hdmi-sound.patch deleted file mode 100644 index fc3c04f..0000000 --- a/patch/kernel/rockchip64-6.14/rk3588-1102-arm64-dts-rockchip-Rock-5B-add-hdmi-sound.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Aleksey Komarov -Date: Sat, 8 Mar 2025 19:43:05 +0100 -Subject: [ARCHEOLOGY] Enable HDMI audio outputs for Rock 5B by - detlev.casanova@collabora.com - -> X-Git-Archeology: > recovered message: > https://lore.kernel.org/all/20250217215641.372723-4-detlev.casanova@collabora.com/ -> X-Git-Archeology: - Revision bf9ffa6eedd5df804e3f9a86c84e00607289cd59: https://github.com/armbian/build/commit/bf9ffa6eedd5df804e3f9a86c84e00607289cd59 -> X-Git-Archeology: Date: Sat, 08 Mar 2025 19:43:05 +0100 -> X-Git-Archeology: From: Aleksey Komarov -> X-Git-Archeology: Subject: Enable HDMI audio outputs for Rock 5B by detlev.casanova@collabora.com -> X-Git-Archeology: ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 16 ++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -231,6 +231,10 @@ hdmi0_out_con: endpoint { - }; - }; - -+&hdmi0_sound { -+ status = "okay"; -+}; -+ - &hdmi1 { - pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd - &hdmim1_tx1_scl &hdmim1_tx1_sda>; -@@ -249,6 +253,10 @@ hdmi1_out_con: endpoint { - }; - }; - -+&hdmi1_sound { -+ status = "okay"; -+}; -+ - &hdptxphy0 { - status = "okay"; - }; -@@ -351,6 +359,14 @@ i2s0_8ch_p0_0: endpoint { - }; - }; - -+&i2s5_8ch { -+ status = "okay"; -+}; -+ -+&i2s6_8ch { -+ status = "okay"; -+}; -+ - &package_thermal { - polling-delay = <1000>; - --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/wifi-4003-ssv-6051-driver.patch b/patch/kernel/rockchip64-6.14/wifi-4003-ssv-6051-driver.patch deleted file mode 100644 index d7c9891..0000000 --- a/patch/kernel/rockchip64-6.14/wifi-4003-ssv-6051-driver.patch +++ /dev/null @@ -1,49424 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Wed, 2 Nov 2022 15:40:06 +0000 -Subject: add ssv6xxx wifi driver - ---- - drivers/net/wireless/Kconfig | 1 + - drivers/net/wireless/Makefile | 1 + - drivers/net/wireless/ssv6051/Kconfig | 11 + - drivers/net/wireless/ssv6051/Makefile | 26 + - drivers/net/wireless/ssv6051/Makefile.bak | 107 + - drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg | 91 + - drivers/net/wireless/ssv6051/hci/hctrl.h | 178 + - drivers/net/wireless/ssv6051/hci/ssv_hci.c | 967 + - drivers/net/wireless/ssv6051/hci/ssv_hci.h | 77 + - drivers/net/wireless/ssv6051/hwif/hwif.h | 84 + - drivers/net/wireless/ssv6051/hwif/sdio/sdio.c | 1254 + - drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h | 80 + - drivers/net/wireless/ssv6051/include/cabrio.h | 28 + - drivers/net/wireless/ssv6051/include/ssv6200.h | 76 + - drivers/net/wireless/ssv6051/include/ssv6200_aux.h | 18221 ++++++++++ - drivers/net/wireless/ssv6051/include/ssv6200_common.h | 452 + - drivers/net/wireless/ssv6051/include/ssv6200_configuration.h | 317 + - drivers/net/wireless/ssv6051/include/ssv6200_reg.h | 9694 +++++ - drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h | 176 + - drivers/net/wireless/ssv6051/include/ssv_cfg.h | 60 + - drivers/net/wireless/ssv6051/include/ssv_firmware_version.h | 25 + - drivers/net/wireless/ssv6051/include/ssv_version.h | 12 + - drivers/net/wireless/ssv6051/platform-config.mak | 97 + - drivers/net/wireless/ssv6051/rules.mak | 19 + - drivers/net/wireless/ssv6051/smac/ampdu.c | 2111 ++ - drivers/net/wireless/ssv6051/smac/ampdu.h | 215 + - drivers/net/wireless/ssv6051/smac/ap.c | 598 + - drivers/net/wireless/ssv6051/smac/ap.h | 41 + - drivers/net/wireless/ssv6051/smac/dev.c | 3881 ++ - drivers/net/wireless/ssv6051/smac/dev.h | 445 + - drivers/net/wireless/ssv6051/smac/dev_tbl.h | 141 + - drivers/net/wireless/ssv6051/smac/drv_comm.h | 61 + - drivers/net/wireless/ssv6051/smac/efuse.c | 334 + - drivers/net/wireless/ssv6051/smac/efuse.h | 40 + - drivers/net/wireless/ssv6051/smac/init.c | 1347 + - drivers/net/wireless/ssv6051/smac/init.h | 23 + - drivers/net/wireless/ssv6051/smac/lib.c | 33 + - drivers/net/wireless/ssv6051/smac/lib.h | 23 + - drivers/net/wireless/ssv6051/smac/linux_80211.h | 24 + - drivers/net/wireless/ssv6051/smac/p2p.c | 305 + - drivers/net/wireless/ssv6051/smac/p2p.h | 58 + - drivers/net/wireless/ssv6051/smac/sar.c | 208 + - drivers/net/wireless/ssv6051/smac/sar.h | 63 + - drivers/net/wireless/ssv6051/smac/sec.h | 52 + - drivers/net/wireless/ssv6051/smac/smartlink.c | 340 + - drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c | 223 + - drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h | 27 + - drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c | 1384 + - drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h | 247 + - drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c | 546 + - drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h | 31 + - drivers/net/wireless/ssv6051/smac/ssv_pm.c | 19 + - drivers/net/wireless/ssv6051/smac/ssv_pm.h | 20 + - drivers/net/wireless/ssv6051/smac/ssv_rc.c | 1716 + - drivers/net/wireless/ssv6051/smac/ssv_rc.h | 50 + - drivers/net/wireless/ssv6051/smac/ssv_rc_common.h | 175 + - drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c | 76 + - drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c | 1765 + - drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h | 50 + - drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c | 256 + - 60 files changed, 48982 insertions(+) - -diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/net/wireless/Kconfig -+++ b/drivers/net/wireless/Kconfig -@@ -18,6 +18,7 @@ menuconfig WLAN - - if WLAN - -+source "drivers/net/wireless/ssv6051/Kconfig" - source "drivers/net/wireless/admtek/Kconfig" - source "drivers/net/wireless/ath/Kconfig" - source "drivers/net/wireless/atmel/Kconfig" -diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/net/wireless/Makefile -+++ b/drivers/net/wireless/Makefile -@@ -3,6 +3,7 @@ - # Makefile for the Linux Wireless network device drivers. - # - -+obj-$(CONFIG_SSV6051) += ssv6051/ - obj-$(CONFIG_WLAN_VENDOR_ADMTEK) += admtek/ - obj-$(CONFIG_WLAN_VENDOR_ATH) += ath/ - obj-$(CONFIG_WLAN_VENDOR_ATMEL) += atmel/ -diff --git a/drivers/net/wireless/ssv6051/Kconfig b/drivers/net/wireless/ssv6051/Kconfig -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/Kconfig -@@ -0,0 +1,11 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+config SSV6051 -+ tristate "South Silicon Valley (ssv) 6051 family WLAN support" -+ depends on MAC80211 -+ depends on (MMC = y) -+ default n -+ select FW_LOADER -+ help -+ Enable South Silicon Valley (SSV) 6051 family support. -+ -+ -diff --git a/drivers/net/wireless/ssv6051/Makefile b/drivers/net/wireless/ssv6051/Makefile -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/Makefile -@@ -0,0 +1,26 @@ -+# SPDX-License-Identifier: ISC -+ -+include $(src)/platform-config.mak -+ -+ccflags-y += \ -+ -I $(src) \ -+ -I $(src)/include -+ -+obj-$(CONFIG_SSV6051) += ssv6051.o -+ssv6051-objs += \ -+ ssv6051-generic-wlan.o \ -+ ssvdevice/ssvdevice.o \ -+ ssvdevice/ssv_cmd.o \ -+ hci/ssv_hci.o \ -+ smac/init.o \ -+ smac/dev.o \ -+ smac/ssv_rc.o \ -+ smac/ssv_ht_rc.o \ -+ smac/ap.o \ -+ smac/ampdu.o \ -+ smac/efuse.o \ -+ smac/ssv_pm.o \ -+ smac/sar.o \ -+ smac/ssv_cfgvendor.o \ -+ hwif/sdio/sdio.o -+ -diff --git a/drivers/net/wireless/ssv6051/Makefile.bak b/drivers/net/wireless/ssv6051/Makefile.bak -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/Makefile.bak -@@ -0,0 +1,107 @@ -+KMODULE_NAME=ssv6051 -+ -+KBUILD_TOP := $(PWD) -+ -+ifeq ($(KERNELRELEASE),) -+ -+KVERS_UNAME ?= $(shell uname -r) -+KVERS_ARCH ?= $(shell arch) -+ -+KBUILD ?= $(shell readlink -f /lib/modules/$(KVERS_UNAME)/build) -+ -+ifeq (,$(KBUILD)) -+$(error kernel build tree not found - set KBUILD to configured kernel) -+endif -+ -+#KCONFIG := $(KBUILD)/config -+#ifeq (,$(wildcard $(KCONFIG))) -+#$(error No .config found in $(KBUILD), set KBUILD to configured kernel) -+#endif -+ -+ifneq (,$(wildcard $(KBUILD)/include/linux/version.h)) -+ifneq (,$(wildcard $(KBUILD)/include/generated/uapi/linux/version.h)) -+$(error Multiple copied of version.h found, clean build tree) -+endif -+endif -+ -+# Kernel Makefile doesn't always know the exact kernel version, so we -+# get it from the kernel headers instead and pass it to make. -+VERSION_H := $(KBUILD)/include/generated/utsrelease.h -+ifeq (,$(wildcard $(VERSION_H))) -+VERSION_H := $(KBUILD)/include/linux/utsrelease.h -+endif -+ifeq (,$(wildcard $(VERSION_H))) -+VERSION_H := $(KBUILD)/include/linux/version.h -+endif -+ifeq (,$(wildcard $(VERSION_H))) -+$(error Please run 'make modules_prepare' in $(KBUILD)) -+endif -+ -+KVERS := $(shell sed -ne 's/"//g;s/^\#define UTS_RELEASE //p' $(VERSION_H)) -+ -+ifeq (,$(KVERS)) -+$(error Cannot find UTS_RELEASE in $(VERSION_H), please report) -+endif -+ -+INST_DIR = /lib/modules/$(KVERS)/misc -+ -+#include $(KCONFIG) -+ -+endif -+ -+include $(KBUILD_TOP)/platform-config.mak -+ -+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include #-Wno-error=missing-attributes -+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h -+ -+OBJS := ssvdevice/ssvdevice.c \ -+ ssvdevice/ssv_cmd.c \ -+ hci/ssv_hci.c \ -+ smac/init.c \ -+ smac/dev.c \ -+ smac/ssv_rc.c \ -+ smac/ssv_ht_rc.c \ -+ smac/ap.c \ -+ smac/ampdu.c \ -+ smac/efuse.c \ -+ smac/ssv_pm.c \ -+ smac/sar.c \ -+ hwif/sdio/sdio.c \ -+ ssv6051-generic-wlan.c -+ -+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS) -+OBJS += smac/ssv6xxx_debugfs.c -+endif -+ -+ifeq ($(findstring -DCONFIG_SSV_VENDOR_EXT_SUPPORT, $(ccflags-y)), -DCONFIG_SSV_VENDOR_EXT_SUPPORT) -+OBJS += smac/ssv_cfgvendor.c -+endif -+ -+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK) -+OBJS += smac/smartlink.c -+endif -+ -+$(KMODULE_NAME)-y += $(ASMS:.S=.o) -+$(KMODULE_NAME)-y += $(OBJS:.c=.o) -+ -+obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o -+ -+all: modules -+ -+modules: -+ ARCH=arm $(MAKE) -C $(KBUILD) M=$(KBUILD_TOP) -+ -+clean: -+ find -type f -iname '*.o' -exec rm {} \; -+ find -type f -iname '*.o.cmd' -exec rm {} \; -+ rm -f *.o *.ko .*.cmd *.mod.c *.symvers modules.order -+ rm -rf .tmp_versions -+ -+install: modules -+ mkdir -p -m 755 $(DESTDIR)$(INST_DIR) -+ install -m 0644 $(KMODULE_NAME).ko $(DESTDIR)$(INST_DIR) -+ifndef DESTDIR -+ -/sbin/depmod -a $(KVERS) -+endif -+ -+.PHONY: all modules clean install -diff --git a/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg -@@ -0,0 +1,91 @@ -+############################################################ -+# ROCKCHIP RK3X28 & RK322X -+# WIFI-CONFIGURATION -+################################################## -+ -+################################################## -+# Firmware setting -+# Priority.1 insmod parameter "cfgfirmwarepath" -+# Priority.2 firmware_path -+# Priority.3 default firmware -+################################################## -+firmware_path = /vendor/etc/firmware/ -+ -+############################################################ -+# MAC address -+# -+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ] -+# -+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg] -+# -+# Priority 3. From insert module parameter -+# -+# Priority 4. From external file path -+# path only support some special charater "_" ":" "/" "." "-" -+# -+# Priority 5. Default[Software mode] -+# -+# 0. => 00:33:33:33:33:33 -+# 1. => Always random -+# 2. => First random and write to file[Default path mac_output_path] -+# -+############################################################ -+ignore_efuse_mac = 0 -+#mac_address_path = /xxxx/xxxx -+mac_address_mode = 2 -+mac_output_path = /data/wifimac -+ -+################################################## -+# Hardware setting -+# -+#volt regulator(DCDC-0 LDO-1) -+# -+################################################## -+xtal_clock = 24 -+volt_regulator = 1 -+ -+################################################## -+# Default channel after wifi on -+# value range: [1 ~ 14] -+################################################## -+def_chan = 6 -+################################################## -+# Hardware Capability Settings: -+################################################## -+hw_cap_ht = on -+hw_cap_gf = off -+hw_cap_2ghz = on -+hw_cap_5ghz = off -+hw_cap_security = on -+hw_cap_sgi_20 = on -+hw_cap_sgi_40 = off -+hw_cap_ap = on -+hw_cap_p2p = on -+hw_cap_ampdu_rx = on -+hw_cap_ampdu_tx = on -+use_wpa2_only = 1 -+################################################## -+# TX power level setting [0-14] -+# The larger the number the smaller the TX power -+# 0 - The maximum power -+# 1 level = -0.5db -+# -+# 6051Z .. 4 or 4 -+# 6051Q .. 2 or 5 -+# 6051P .. 0 or 0 -+# -+################################################## -+#wifi_tx_gain_level_b = 2 -+#wifi_tx_gain_level_gn = 5 -+################################################ -+# Signal strength control -+# rssi control -+#rssi_ctl = 10 -+ -+ -+################################################## -+# Import extenal configuration(UP to 64 groups) -+# example: -+# register = CE010010:91919191 -+# register = 00CC0010:00091919 -+################################################## -diff --git a/drivers/net/wireless/ssv6051/hci/hctrl.h b/drivers/net/wireless/ssv6051/hci/hctrl.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/hci/hctrl.h -@@ -0,0 +1,178 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _HCTRL_H_ -+#define _HCTRL_H_ -+#define MAX_FRAME_SIZE 4096 -+#define SSV6XXX_INT_RX 0x00000001 -+#define SSV6XXX_INT_TX 0x00000002 -+#define SSV6XXX_INT_SOC 0x00000004 -+#define SSV6XXX_INT_LOW_EDCA_0 0x00000008 -+#define SSV6XXX_INT_LOW_EDCA_1 0x00000010 -+#define SSV6XXX_INT_LOW_EDCA_2 0x00000020 -+#define SSV6XXX_INT_LOW_EDCA_3 0x00000040 -+#define SSV6XXX_INT_RESOURCE_LOW 0x00000080 -+#define IFDEV(_ct) ((_ct)->shi->dev) -+#define IFOPS(_ct) ((_ct)->shi->if_ops) -+#define HCI_REG_READ(_ct,_adr,_val) IFOPS(_ct)->readreg(IFDEV(_ct), _adr, _val) -+#define HCI_REG_WRITE(_ct,_adr,_val) IFOPS(_ct)->writereg(IFDEV(_ct), _adr, _val) -+#define HCI_REG_SET_BITS(_ct,_reg,_set,_clr) \ -+{ \ -+ u32 _regval; \ -+ if(HCI_REG_READ(_ct, _reg, &_regval)); \ -+ _regval &= ~(_clr); \ -+ _regval |= (_set); \ -+ if(HCI_REG_WRITE(_ct, _reg, _regval)); \ -+} -+#define IF_SEND(_ct,_bf,_len,_qid) IFOPS(_ct)->write(IFDEV(_ct), _bf, _len, _qid) -+#define IF_RECV(ct,bf,len) IFOPS(ct)->read(IFDEV(ct), bf, len) -+#define HCI_LOAD_FW(ct,_bf,open) IFOPS(ct)->load_fw(IFDEV(ct), _bf, open) -+#define HCI_IFC_RESET(ct) IFOPS(ct)->interface_reset(IFDEV(ct)) -+struct ssv6xxx_hci_ctrl { -+ struct ssv6xxx_hci_info *shi; -+ spinlock_t int_lock; -+ u32 int_status; -+ u32 int_mask; -+ struct mutex txq_mask_lock; -+ u32 txq_mask; -+ struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM]; -+ struct mutex hci_mutex; -+ bool hci_start; -+ struct sk_buff *rx_buf; -+ u32 rx_pkt; -+ struct workqueue_struct *hci_work_queue; -+ struct work_struct hci_rx_work; -+ struct work_struct hci_tx_work; -+ u32 read_rs0_info_fail; -+ u32 read_rs1_info_fail; -+ u32 rx_work_running; -+ u32 isr_running; -+ u32 xmit_running; -+ u32 isr_summary_eable; -+ u32 isr_routine_time; -+ u32 isr_tx_time; -+ u32 isr_rx_time; -+ u32 isr_idle_time; -+ u32 isr_rx_idle_time; -+ u32 isr_miss_cnt; -+ unsigned long prev_isr_jiffes; -+ unsigned long prev_rx_isr_jiffes; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct dentry *debugfs_dir; -+ u32 isr_mib_enable; -+ u32 isr_mib_reset; -+ long long isr_total_time; -+ long long isr_tx_io_time; -+ long long isr_rx_io_time; -+ u32 isr_rx_io_count; -+ u32 isr_tx_io_count; -+ long long isr_rx_proc_time; -+#ifdef CONFIG_IRQ_DEBUG_COUNT -+ bool irq_enable; -+ u32 irq_count; -+ u32 invalid_irq_count; -+ u32 tx_irq_count; -+ u32 real_tx_irq_count; -+ u32 rx_irq_count; -+ u32 irq_rx_pkt_count; -+ u32 irq_tx_pkt_count; -+#endif -+#endif -+}; -+struct ssv6xxx_hci_txq_info { -+ u32 tx_use_page:8; -+ u32 tx_use_id:6; -+ u32 txq0_size:4; -+ u32 txq1_size:4; -+ u32 txq2_size:5; -+ u32 txq3_size:5; -+}; -+struct ssv6xxx_hci_txq_info2 { -+ u32 tx_use_page:9; -+ u32 tx_use_id:8; -+ u32 txq4_size:4; -+ u32 rsvd:11; -+}; -+struct ssv6xxx_hw_resource { -+ u32 free_tx_page; -+ u32 free_tx_id; -+ int max_tx_frame[SSV_HW_TXQ_NUM]; -+}; -+static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl, -+ irq_handler_t irq_handler) -+{ -+ if (hctrl->shi->if_ops->irq_request) -+ hctrl->shi->if_ops->irq_request(IFDEV(hctrl), irq_handler, -+ hctrl); -+} -+ -+static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl) -+{ -+ if (hctrl->shi->if_ops->irq_enable) -+ hctrl->shi->if_ops->irq_enable(IFDEV(hctrl)); -+} -+ -+static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl) -+{ -+ if (hctrl->shi->if_ops->irq_disable) -+ hctrl->shi->if_ops->irq_disable(IFDEV(hctrl), false); -+} -+ -+static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl, -+ int *status) -+{ -+ if (hctrl->shi->if_ops->irq_getstatus) -+ return hctrl->shi->if_ops->irq_getstatus(IFDEV(hctrl), status); -+ return 0; -+} -+ -+static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl, -+ int mask) -+{ -+ if (hctrl->shi->if_ops->irq_setmask) -+ hctrl->shi->if_ops->irq_setmask(IFDEV(hctrl), mask); -+} -+ -+static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl) -+{ -+ if (hctrl->shi->if_ops->irq_trigger) -+ hctrl->shi->if_ops->irq_trigger(IFDEV(hctrl)); -+} -+ -+static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl) -+{ -+ if (hctrl->shi->if_ops->pmu_wakeup) -+ hctrl->shi->if_ops->pmu_wakeup(IFDEV(hctrl)); -+} -+ -+static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl, -+ u32 addr, u8 * data, u32 size) -+{ -+ if (hctrl->shi->if_ops->write_sram) -+ return hctrl->shi->if_ops->write_sram(IFDEV(hctrl), addr, data, -+ size); -+ return 0; -+} -+ -+#define HCI_IRQ_REQUEST(ct,hdle) ssv6xxx_hwif_irq_request(ct, hdle) -+#define HCI_IRQ_ENABLE(ct) ssv6xxx_hwif_irq_enable(ct) -+#define HCI_IRQ_DISABLE(ct) ssv6xxx_hwif_irq_disable(ct) -+#define HCI_IRQ_STATUS(ct,sts) ssv6xxx_hwif_irq_getstatus(ct, sts) -+#define HCI_IRQ_SET_MASK(ct,mk) ssv6xxx_hwif_irq_setmask(ct, mk) -+#define HCI_IRQ_TRIGGER(ct) ssv6xxx_hwif_irq_trigger(ct) -+#define HCI_PMU_WAKEUP(ct) ssv6xxx_hwif_pmu_wakeup(ct) -+#define HCI_SRAM_WRITE(_ct,_adr,_dat,_size) ssv6xxx_hwif_write_sram(_ct, _adr, _dat, _size); -+#endif -diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.c b/drivers/net/wireless/ssv6051/hci/ssv_hci.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.c -@@ -0,0 +1,967 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "hctrl.h" -+ -+static struct ssv6xxx_hci_ctrl *ctrl_hci = NULL; -+ -+struct sk_buff *ssv_skb_alloc(s32 len) -+{ -+ struct sk_buff *skb; -+ skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL); -+ if (skb != NULL) { -+ skb_reserve(skb, SSV_SKB_info_size); -+ } -+ return skb; -+} -+ -+void ssv_skb_free(struct sk_buff *skb) -+{ -+ dev_kfree_skb_any(skb); -+} -+ -+static int ssv6xxx_hci_irq_enable(void) -+{ -+ HCI_IRQ_SET_MASK(ctrl_hci, ~(ctrl_hci->int_mask)); -+ HCI_IRQ_ENABLE(ctrl_hci); -+ return 0; -+} -+ -+static int ssv6xxx_hci_irq_disable(void) -+{ -+ HCI_IRQ_SET_MASK(ctrl_hci, 0xffffffff); -+ HCI_IRQ_DISABLE(ctrl_hci); -+ return 0; -+} -+ -+static void ssv6xxx_hci_irq_register(u32 irq_mask) -+{ -+ unsigned long flags; -+ u32 regval; -+ mutex_lock(&ctrl_hci->hci_mutex); -+ spin_lock_irqsave(&ctrl_hci->int_lock, flags); -+ ctrl_hci->int_mask |= irq_mask; -+ regval = ~ctrl_hci->int_mask; -+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags); -+ smp_mb(); -+ HCI_IRQ_SET_MASK(ctrl_hci, regval); -+ mutex_unlock(&ctrl_hci->hci_mutex); -+} -+ -+static inline u32 ssv6xxx_hci_get_int_bitno(int txqid) -+{ -+ if (txqid == SSV_HW_TXQ_NUM - 1) -+ return 1; -+ else -+ return txqid + 3; -+} -+ -+static int ssv6xxx_hci_start(void) -+{ -+ ssv6xxx_hci_irq_enable(); -+ ctrl_hci->hci_start = true; -+ HCI_IRQ_TRIGGER(ctrl_hci); -+ return 0; -+} -+ -+static int ssv6xxx_hci_stop(void) -+{ -+ ssv6xxx_hci_irq_disable(); -+ ctrl_hci->hci_start = false; -+ return 0; -+} -+ -+static int ssv6xxx_hci_read_word(u32 addr, u32 * regval) -+{ -+ int ret = HCI_REG_READ(ctrl_hci, addr, regval); -+ return ret; -+} -+ -+static int ssv6xxx_hci_write_word(u32 addr, u32 regval) -+{ -+ return HCI_REG_WRITE(ctrl_hci, addr, regval); -+} -+ -+static int ssv6xxx_hci_load_fw(u8 * firmware_name, u8 openfile) -+{ -+ return HCI_LOAD_FW(ctrl_hci, firmware_name, openfile); -+} -+ -+static int ssv6xxx_hci_write_sram(u32 addr, u8 * data, u32 size) -+{ -+ return HCI_SRAM_WRITE(ctrl_hci, addr, data, size); -+} -+ -+static int ssv6xxx_hci_pmu_wakeup(void) -+{ -+ HCI_PMU_WAKEUP(ctrl_hci); -+ return 0; -+} -+ -+static int ssv6xxx_hci_interface_reset(void) -+{ -+ HCI_IFC_RESET(ctrl_hci); -+ return 0; -+} -+ -+static int ssv6xxx_hci_send_cmd(struct sk_buff *skb) -+{ -+ int ret; -+ ret = IF_SEND(ctrl_hci, (void *)skb->data, skb->len, 0); -+ -+ if (ret < 0) -+ pr_warn("ssv6xxx_hci_send_cmd failed, ret=%d\n", ret); -+ -+ return ret; -+} -+ -+static int ssv6xxx_hci_enqueue(struct sk_buff *skb, int txqid, u32 tx_flags) -+{ -+ struct ssv_hw_txq *hw_txq; -+ unsigned long flags; -+ u32 status; -+ int qlen = 0; -+ BUG_ON(txqid >= SSV_HW_TXQ_NUM || txqid < 0); -+ if (txqid >= SSV_HW_TXQ_NUM || txqid < 0) -+ return -1; -+ hw_txq = &ctrl_hci->hw_txq[txqid]; -+ hw_txq->tx_flags = tx_flags; -+ if (tx_flags & HCI_FLAGS_ENQUEUE_HEAD) -+ skb_queue_head(&hw_txq->qhead, skb); -+ else -+ skb_queue_tail(&hw_txq->qhead, skb); -+ qlen = (int)skb_queue_len(&hw_txq->qhead); -+ if (!(tx_flags & HCI_FLAGS_NO_FLOWCTRL)) { -+ if (skb_queue_len(&hw_txq->qhead) >= hw_txq->max_qsize) { -+ ctrl_hci->shi->hci_tx_flow_ctrl_cb(ctrl_hci-> -+ shi->tx_fctrl_cb_args, -+ hw_txq->txq_no, true, -+ 2000); -+ } -+ } -+ -+ mutex_lock(&ctrl_hci->hci_mutex); -+ spin_lock_irqsave(&ctrl_hci->int_lock, flags); -+ status = ctrl_hci->int_mask; -+ -+ if ((ctrl_hci->int_mask & SSV6XXX_INT_RESOURCE_LOW) == 0) { -+ if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) { -+ u32 regval; -+ ctrl_hci->int_mask |= SSV6XXX_INT_RESOURCE_LOW; -+ regval = ~ctrl_hci->int_mask; -+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags); -+ HCI_IRQ_SET_MASK(ctrl_hci, regval); -+ mutex_unlock(&ctrl_hci->hci_mutex); -+ } else { -+ ctrl_hci->int_status |= SSV6XXX_INT_RESOURCE_LOW; -+ smp_mb(); -+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags); -+ mutex_unlock(&ctrl_hci->hci_mutex); -+ ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci-> -+ shi->dev); -+ } -+ } else { -+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags); -+ mutex_unlock(&ctrl_hci->hci_mutex); -+ } -+ -+ return qlen; -+} -+ -+static bool ssv6xxx_hci_is_txq_empty(int txqid) -+{ -+ struct ssv_hw_txq *hw_txq; -+ BUG_ON(txqid >= SSV_HW_TXQ_NUM); -+ if (txqid >= SSV_HW_TXQ_NUM) -+ return false; -+ hw_txq = &ctrl_hci->hw_txq[txqid]; -+ if (skb_queue_len(&hw_txq->qhead) <= 0) -+ return true; -+ return false; -+} -+ -+static int ssv6xxx_hci_txq_flush(u32 txq_mask) -+{ -+ struct ssv_hw_txq *hw_txq; -+ struct sk_buff *skb = NULL; -+ int txqid; -+ for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) { -+ if ((txq_mask & (1 << txqid)) != 0) -+ continue; -+ hw_txq = &ctrl_hci->hw_txq[txqid]; -+ while ((skb = skb_dequeue(&hw_txq->qhead))) { -+ ctrl_hci->shi->hci_tx_buf_free_cb(skb, -+ ctrl_hci-> -+ shi->tx_buf_free_args); -+ } -+ } -+ return 0; -+} -+ -+static int ssv6xxx_hci_txq_flush_by_sta(int aid) -+{ -+ return 0; -+} -+ -+static int ssv6xxx_hci_txq_pause(u32 txq_mask) -+{ -+ struct ssv_hw_txq *hw_txq; -+ int txqid; -+ mutex_lock(&ctrl_hci->txq_mask_lock); -+ ctrl_hci->txq_mask |= (txq_mask & 0x1F); -+ for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) { -+ if ((ctrl_hci->txq_mask & (1 << txqid)) == 0) -+ continue; -+ hw_txq = &ctrl_hci->hw_txq[txqid]; -+ hw_txq->paused = true; -+ } -+ HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN, -+ (ctrl_hci->txq_mask << 16), (0x1F << 16)); -+ mutex_unlock(&ctrl_hci->txq_mask_lock); -+ return 0; -+} -+ -+static int ssv6xxx_hci_txq_resume(u32 txq_mask) -+{ -+ struct ssv_hw_txq *hw_txq; -+ int txqid; -+ mutex_lock(&ctrl_hci->txq_mask_lock); -+ ctrl_hci->txq_mask &= ~(txq_mask & 0x1F); -+ for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) { -+ if ((ctrl_hci->txq_mask & (1 << txqid)) != 0) -+ continue; -+ hw_txq = &ctrl_hci->hw_txq[txqid]; -+ hw_txq->paused = false; -+ } -+ HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN, -+ (ctrl_hci->txq_mask << 16), (0x1F << 16)); -+ mutex_unlock(&ctrl_hci->txq_mask_lock); -+ return 0; -+} -+ -+static int ssv6xxx_hci_xmit(struct ssv_hw_txq *hw_txq, int max_count, -+ struct ssv6xxx_hw_resource *phw_resource) -+{ -+ struct sk_buff_head tx_cb_list; -+ struct sk_buff *skb = NULL; -+ int tx_count, ret, page_count; -+ struct ssv6200_tx_desc *tx_desc = NULL; -+ ctrl_hci->xmit_running = 1; -+ skb_queue_head_init(&tx_cb_list); -+ for (tx_count = 0; tx_count < max_count; tx_count++) { -+ if (ctrl_hci->hci_start == false) { -+ pr_debug("ssv6xxx_hci_xmit - hci_start = false\n"); -+ goto xmit_out; -+ } -+ skb = skb_dequeue(&hw_txq->qhead); -+ if (!skb) { -+ pr_debug("ssv6xxx_hci_xmit - queue empty\n"); -+ goto xmit_out; -+ } -+ page_count = (skb->len + SSV6200_ALLOC_RSVD); -+ if (page_count & HW_MMU_PAGE_MASK) -+ page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1; -+ else -+ page_count = page_count >> HW_MMU_PAGE_SHIFT; -+ if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2)) -+ pr_err("Asking page %d(%d) exceeds resource limit %d.\n", -+ page_count, skb->len, -+ (SSV6200_PAGE_TX_THRESHOLD / 2)); -+ if ((phw_resource->free_tx_page < page_count) -+ || (phw_resource->free_tx_id <= 0) -+ || (phw_resource->max_tx_frame[hw_txq->txq_no] <= 0)) { -+ skb_queue_head(&hw_txq->qhead, skb); -+ break; -+ } -+ phw_resource->free_tx_page -= page_count; -+ phw_resource->free_tx_id--; -+ phw_resource->max_tx_frame[hw_txq->txq_no]--; -+ tx_desc = (struct ssv6200_tx_desc *)skb->data; -+ -+ if (ctrl_hci->shi->hci_skb_update_cb != NULL -+ && tx_desc->reason != ID_TRAP_SW_TXTPUT) { -+ ctrl_hci->shi->hci_skb_update_cb(skb, -+ ctrl_hci-> -+ shi->skb_update_args); -+ } -+ -+ ret = -+ IF_SEND(ctrl_hci, (void *)skb->data, skb->len, -+ hw_txq->txq_no); -+ if (ret < 0) { -+ pr_err("ssv6xxx_hci_xmit failure\n"); -+ skb_queue_head(&hw_txq->qhead, skb); -+ break; -+ } -+ if (tx_desc->reason != ID_TRAP_SW_TXTPUT) -+ skb_queue_tail(&tx_cb_list, skb); -+ else -+ ssv_skb_free(skb); -+ hw_txq->tx_pkt++; -+ -+ if (!(hw_txq->tx_flags & HCI_FLAGS_NO_FLOWCTRL)) { -+ if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) { -+ ctrl_hci->shi-> -+ hci_tx_flow_ctrl_cb -+ (ctrl_hci->shi->tx_fctrl_cb_args, -+ hw_txq->txq_no, false, 2000); -+ } -+ } -+ } -+ xmit_out: -+ if (ctrl_hci->shi->hci_tx_cb && tx_desc -+ && tx_desc->reason != ID_TRAP_SW_TXTPUT) { -+ ctrl_hci->shi->hci_tx_cb(&tx_cb_list, -+ ctrl_hci->shi->tx_cb_args); -+ } -+ ctrl_hci->xmit_running = 0; -+ return tx_count; -+} -+ -+static int ssv6xxx_hci_tx_handler(void *dev, int max_count) -+{ -+ struct ssv6xxx_hci_txq_info txq_info; -+ struct ssv6xxx_hci_txq_info2 txq_info2; -+ struct ssv6xxx_hw_resource hw_resource; -+ struct ssv_hw_txq *hw_txq = dev; -+ int ret, tx_count = 0; -+ max_count = skb_queue_len(&hw_txq->qhead); -+ if (max_count == 0) -+ return 0; -+ if (hw_txq->txq_no == 4) { -+ ret = -+ HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2, -+ (u32 *) & txq_info2); -+ if (ret < 0) { -+ ctrl_hci->read_rs1_info_fail++; -+ return 0; -+ } -+ //BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page); -+ //BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_id); -+ if (SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page) -+ return 0; -+ if (SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_page) -+ return 0; -+ hw_resource.free_tx_page = -+ SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page; -+ hw_resource.free_tx_id = -+ SSV6200_ID_TX_THRESHOLD - txq_info2.tx_use_id; -+ hw_resource.max_tx_frame[4] = -+ SSV6200_ID_MANAGER_QUEUE - txq_info2.txq4_size; -+ } else { -+ ret = -+ HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO, -+ (u32 *) & txq_info); -+ if (ret < 0) { -+ ctrl_hci->read_rs0_info_fail++; -+ return 0; -+ } -+ //BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page); -+ //BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_id); -+ if (SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page) -+ return 0; -+ if (SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_page) -+ return 0; -+ hw_resource.free_tx_page = -+ SSV6200_PAGE_TX_THRESHOLD - txq_info.tx_use_page; -+ hw_resource.free_tx_id = -+ SSV6200_ID_TX_THRESHOLD - txq_info.tx_use_id; -+ hw_resource.max_tx_frame[0] = -+ SSV6200_ID_AC_BK_OUT_QUEUE - txq_info.txq0_size; -+ hw_resource.max_tx_frame[1] = -+ SSV6200_ID_AC_BE_OUT_QUEUE - txq_info.txq1_size; -+ hw_resource.max_tx_frame[2] = -+ SSV6200_ID_AC_VI_OUT_QUEUE - txq_info.txq2_size; -+ hw_resource.max_tx_frame[3] = -+ SSV6200_ID_AC_VO_OUT_QUEUE - txq_info.txq3_size; -+ BUG_ON(hw_resource.max_tx_frame[3] < 0); -+ BUG_ON(hw_resource.max_tx_frame[2] < 0); -+ BUG_ON(hw_resource.max_tx_frame[1] < 0); -+ BUG_ON(hw_resource.max_tx_frame[0] < 0); -+ } -+ { -+ tx_count = ssv6xxx_hci_xmit(hw_txq, max_count, &hw_resource); -+ } -+ if ((ctrl_hci->shi->hci_tx_q_empty_cb != NULL) -+ && (skb_queue_len(&hw_txq->qhead) == 0)) { -+ ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no, -+ ctrl_hci-> -+ shi->tx_q_empty_args); -+ } -+ return tx_count; -+} -+ -+void ssv6xxx_hci_tx_work(struct work_struct *work) -+{ -+ ssv6xxx_hci_irq_register(SSV6XXX_INT_RESOURCE_LOW); -+} -+ -+static int _do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status) -+{ -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+ struct sk_buff_head rx_list; -+#endif -+ struct sk_buff *rx_mpdu; -+ int rx_cnt, ret = 0; -+ size_t dlen; -+ u32 status = isr_status; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time; -+ struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time; -+#endif -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+ skb_queue_head_init(&rx_list); -+#endif -+ for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) { -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (hctl->isr_mib_enable) -+ getnstimeofday(&rx_io_start_time); -+#endif -+ ret = IF_RECV(hctl, hctl->rx_buf->data, &dlen); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (hctl->isr_mib_enable) -+ getnstimeofday(&rx_io_end_time); -+#endif -+ if (ret < 0 || dlen <= 0) { -+ pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n", -+ __FUNCTION__, ret, (int)dlen); -+ if (ret != -84 || dlen > MAX_FRAME_SIZE) -+ break; -+ } -+ rx_mpdu = hctl->rx_buf; -+ hctl->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE); -+ if (hctl->rx_buf == NULL) { -+ pr_err("RX buffer allocation failure!\n"); -+ hctl->rx_buf = rx_mpdu; -+ break; -+ } -+ hctl->rx_pkt++; -+ skb_put(rx_mpdu, dlen); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (hctl->isr_mib_enable) -+ getnstimeofday(&rx_proc_start_time); -+#endif -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+ __skb_queue_tail(&rx_list, rx_mpdu); -+#else -+ hctl->shi->hci_rx_cb(rx_mpdu, hctl->shi->rx_cb_args); -+#endif -+ HCI_IRQ_STATUS(hctl, &status); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (hctl->isr_mib_enable) { -+ getnstimeofday(&rx_proc_end_time); -+ hctl->isr_rx_io_count++; -+ rx_io_diff_time = -+ timespec_sub(rx_io_end_time, rx_io_start_time); -+ hctl->isr_rx_io_time += -+ timespec_to_ns(&rx_io_diff_time); -+ rx_proc_diff_time = -+ timespec_sub(rx_proc_end_time, rx_proc_start_time); -+ hctl->isr_rx_proc_time += -+ timespec_to_ns(&rx_proc_diff_time); -+ } -+#endif -+ } -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (hctl->isr_mib_enable) -+ getnstimeofday(&rx_proc_start_time); -+#endif -+ hctl->shi->hci_rx_cb(&rx_list, hctl->shi->rx_cb_args); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (hctl->isr_mib_enable) { -+ getnstimeofday(&rx_proc_end_time); -+ rx_proc_diff_time = -+ timespec_sub(rx_proc_end_time, rx_proc_start_time); -+ hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time); -+ } -+#endif -+#endif -+ return ret; -+} -+ -+static void ssv6xxx_hci_rx_work(struct work_struct *work) -+{ -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+ struct sk_buff_head rx_list; -+#endif -+ struct sk_buff *rx_mpdu; -+ int rx_cnt, ret; -+ size_t dlen; -+ u32 status; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time; -+ struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time; -+#endif -+ ctrl_hci->rx_work_running = 1; -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+ skb_queue_head_init(&rx_list); -+#endif -+ status = SSV6XXX_INT_RX; -+ for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) { -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (ctrl_hci->isr_mib_enable) -+ getnstimeofday(&rx_io_start_time); -+#endif -+ ret = IF_RECV(ctrl_hci, ctrl_hci->rx_buf->data, &dlen); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (ctrl_hci->isr_mib_enable) -+ getnstimeofday(&rx_io_end_time); -+#endif -+ if (ret < 0 || dlen <= 0) { -+ pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n", -+ __FUNCTION__, ret, (int)dlen); -+ if (ret != -84 || dlen > MAX_FRAME_SIZE) -+ break; -+ } -+ rx_mpdu = ctrl_hci->rx_buf; -+ ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE); -+ if (ctrl_hci->rx_buf == NULL) { -+ pr_err("RX buffer allocation failure!\n"); -+ ctrl_hci->rx_buf = rx_mpdu; -+ break; -+ } -+ ctrl_hci->rx_pkt++; -+ skb_put(rx_mpdu, dlen); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (ctrl_hci->isr_mib_enable) -+ getnstimeofday(&rx_proc_start_time); -+#endif -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+ __skb_queue_tail(&rx_list, rx_mpdu); -+#else -+ ctrl_hci->shi->hci_rx_cb(rx_mpdu, ctrl_hci->shi->rx_cb_args); -+#endif -+ HCI_IRQ_STATUS(ctrl_hci, &status); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (ctrl_hci->isr_mib_enable) { -+ getnstimeofday(&rx_proc_end_time); -+ ctrl_hci->isr_rx_io_count++; -+ rx_io_diff_time = -+ timespec_sub(rx_io_end_time, rx_io_start_time); -+ ctrl_hci->isr_rx_io_time += -+ timespec_to_ns(&rx_io_diff_time); -+ rx_proc_diff_time = -+ timespec_sub(rx_proc_end_time, rx_proc_start_time); -+ ctrl_hci->isr_rx_proc_time += -+ timespec_to_ns(&rx_proc_diff_time); -+ } -+#endif -+ } -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (ctrl_hci->isr_mib_enable) -+ getnstimeofday(&rx_proc_start_time); -+#endif -+ ctrl_hci->shi->hci_rx_cb(&rx_list, ctrl_hci->shi->rx_cb_args); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (ctrl_hci->isr_mib_enable) { -+ getnstimeofday(&rx_proc_end_time); -+ rx_proc_diff_time = -+ timespec_sub(rx_proc_end_time, rx_proc_start_time); -+ ctrl_hci->isr_rx_proc_time += -+ timespec_to_ns(&rx_proc_diff_time); -+ } -+#endif -+#endif -+ ctrl_hci->rx_work_running = 0; -+} -+ -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+static void ssv6xxx_isr_mib_reset(void) -+{ -+ ctrl_hci->isr_mib_reset = 0; -+ ctrl_hci->isr_total_time = 0; -+ ctrl_hci->isr_rx_io_time = 0; -+ ctrl_hci->isr_tx_io_time = 0; -+ ctrl_hci->isr_rx_io_count = 0; -+ ctrl_hci->isr_tx_io_count = 0; -+ ctrl_hci->isr_rx_proc_time = 0; -+} -+ -+static int hw_txq_len_open(struct inode *inode, struct file *filp) -+{ -+ filp->private_data = inode->i_private; -+ return 0; -+} -+ -+static ssize_t hw_txq_len_read(struct file *filp, char __user * buffer, -+ size_t count, loff_t * ppos) -+{ -+ ssize_t ret; -+ struct ssv6xxx_hci_ctrl *hctl = -+ (struct ssv6xxx_hci_ctrl *)filp->private_data; -+ char *summary_buf = kzalloc(1024, GFP_KERNEL); -+ char *prn_ptr = summary_buf; -+ int prt_size; -+ int buf_size = 1024; -+ int i = 0; -+ if (!summary_buf) -+ return -ENOMEM; -+ for (i = 0; i < SSV_HW_TXQ_NUM; i++) { -+ prt_size = -+ snprintf(prn_ptr, buf_size, "\n\rhw_txq%d_len: %d", i, -+ skb_queue_len(&hctl->hw_txq[i].qhead)); -+ prn_ptr += prt_size; -+ buf_size -= prt_size; -+ } -+ buf_size = 1024 - buf_size; -+ ret = -+ simple_read_from_buffer(buffer, count, ppos, summary_buf, buf_size); -+ kfree(summary_buf); -+ return ret; -+} -+ -+struct file_operations hw_txq_len_fops = { -+ .owner = THIS_MODULE, -+ .open = hw_txq_len_open, -+ .read = hw_txq_len_read, -+}; -+ -+bool ssv6xxx_hci_init_debugfs(struct dentry *dev_deugfs_dir) -+{ -+ ctrl_hci->debugfs_dir = debugfs_create_dir("hci", dev_deugfs_dir); -+ if (ctrl_hci->debugfs_dir == NULL) { -+ dev_err(ctrl_hci->shi->dev, -+ "Failed to create HCI debugfs directory.\n"); -+ return false; -+ } -+ debugfs_create_u32("TXQ_mask", 00444, ctrl_hci->debugfs_dir, -+ &ctrl_hci->txq_mask); -+ debugfs_create_u32("hci_isr_mib_enable", 00644, ctrl_hci->debugfs_dir, -+ &ctrl_hci->isr_mib_enable); -+ debugfs_create_u32("hci_isr_mib_reset", 00644, ctrl_hci->debugfs_dir, -+ &ctrl_hci->isr_mib_reset); -+ debugfs_create_u64("isr_total_time", 00444, ctrl_hci->debugfs_dir, -+ &ctrl_hci->isr_total_time); -+ debugfs_create_u64("tx_io_time", 00444, ctrl_hci->debugfs_dir, -+ &ctrl_hci->isr_tx_io_time); -+ debugfs_create_u64("rx_io_time", 00444, ctrl_hci->debugfs_dir, -+ &ctrl_hci->isr_rx_io_time); -+ debugfs_create_u32("tx_io_count", 00444, ctrl_hci->debugfs_dir, -+ &ctrl_hci->isr_tx_io_count); -+ debugfs_create_u32("rx_io_count", 00444, ctrl_hci->debugfs_dir, -+ &ctrl_hci->isr_rx_io_count); -+ debugfs_create_u64("rx_proc_time", 00444, ctrl_hci->debugfs_dir, -+ &ctrl_hci->isr_rx_proc_time); -+ debugfs_create_file("hw_txq_len", 00444, ctrl_hci->debugfs_dir, -+ ctrl_hci, &hw_txq_len_fops); -+ return true; -+} -+ -+void ssv6xxx_hci_deinit_debugfs(void) -+{ -+ if (ctrl_hci->debugfs_dir == NULL) -+ return; -+ ctrl_hci->debugfs_dir = NULL; -+} -+#endif -+static int _isr_do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status) -+{ -+ int status; -+ u32 before = jiffies; -+ -+ if (hctl->isr_summary_eable && hctl->prev_rx_isr_jiffes) { -+ if (hctl->isr_rx_idle_time) { -+ hctl->isr_rx_idle_time += -+ (jiffies - hctl->prev_rx_isr_jiffes); -+ hctl->isr_rx_idle_time = hctl->isr_rx_idle_time >> 1; -+ } else { -+ hctl->isr_rx_idle_time += -+ (jiffies - hctl->prev_rx_isr_jiffes); -+ } -+ } -+ status = _do_rx(hctl, isr_status); -+ if (hctl->isr_summary_eable) { -+ if (hctl->isr_rx_time) { -+ hctl->isr_rx_time += (jiffies - before); -+ hctl->isr_rx_time = hctl->isr_rx_time >> 1; -+ } else { -+ hctl->isr_rx_time += (jiffies - before); -+ } -+ hctl->prev_rx_isr_jiffes = jiffies; -+ } -+ return status; -+} -+ -+static int _do_tx(struct ssv6xxx_hci_ctrl *hctl, u32 status) -+{ -+ int q_num; -+ int tx_count = 0; -+ u32 to_disable_int = 1; -+ unsigned long flags; -+ struct ssv_hw_txq *hw_txq; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time; -+#endif -+#ifdef CONFIG_IRQ_DEBUG_COUNT -+ if ((!(status & SSV6XXX_INT_RX)) && htcl->irq_enable) -+ hctl->tx_irq_count++; -+#endif -+ if ((status & SSV6XXX_INT_RESOURCE_LOW) == 0) -+ return 0; -+ for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) { -+ u32 before = jiffies; -+ hw_txq = &hctl->hw_txq[q_num]; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (hctl->isr_mib_enable) -+ getnstimeofday(&tx_io_start_time); -+#endif -+ tx_count += ssv6xxx_hci_tx_handler(hw_txq, 999); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (hctl->isr_mib_enable) { -+ getnstimeofday(&tx_io_end_time); -+ tx_io_diff_time = -+ timespec_sub(tx_io_end_time, tx_io_start_time); -+ hctl->isr_tx_io_time += -+ timespec_to_ns(&tx_io_diff_time); -+ } -+#endif -+ if (hctl->isr_summary_eable) { -+ if (hctl->isr_tx_time) { -+ hctl->isr_tx_time += (jiffies - before); -+ hctl->isr_tx_time = hctl->isr_tx_time >> 1; -+ } else { -+ hctl->isr_tx_time += (jiffies - before); -+ } -+ } -+ } -+ mutex_lock(&hctl->hci_mutex); -+ spin_lock_irqsave(&hctl->int_lock, flags); -+ for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) { -+ hw_txq = &hctl->hw_txq[q_num]; -+ if (skb_queue_len(&hw_txq->qhead) > 0) { -+ to_disable_int = 0; -+ break; -+ } -+ } -+ if (to_disable_int) { -+ u32 reg_val; -+ hctl->int_mask &= ~(SSV6XXX_INT_RESOURCE_LOW | SSV6XXX_INT_TX); -+ reg_val = ~hctl->int_mask; -+ spin_unlock_irqrestore(&hctl->int_lock, flags); -+ HCI_IRQ_SET_MASK(hctl, reg_val); -+ } else { -+ spin_unlock_irqrestore(&hctl->int_lock, flags); -+ } -+ mutex_unlock(&hctl->hci_mutex); -+ return tx_count; -+} -+ -+irqreturn_t ssv6xxx_hci_isr(int irq, void *args) -+{ -+ struct ssv6xxx_hci_ctrl *hctl = args; -+ u32 status; -+ unsigned long flags; -+ int ret = IRQ_HANDLED; -+ bool dbg_isr_miss = true; -+ if (ctrl_hci->isr_summary_eable && ctrl_hci->prev_isr_jiffes) { -+ if (ctrl_hci->isr_idle_time) { -+ ctrl_hci->isr_idle_time += -+ (jiffies - ctrl_hci->prev_isr_jiffes); -+ ctrl_hci->isr_idle_time = ctrl_hci->isr_idle_time >> 1; -+ } else { -+ ctrl_hci->isr_idle_time += -+ (jiffies - ctrl_hci->prev_isr_jiffes); -+ } -+ } -+ BUG_ON(!args); -+ do { -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct timespec start_time, end_time, diff_time; -+ if (hctl->isr_mib_reset) -+ ssv6xxx_isr_mib_reset(); -+ if (hctl->isr_mib_enable) -+ getnstimeofday(&start_time); -+#endif -+#ifdef CONFIG_IRQ_DEBUG_COUNT -+ if (ctrl_hci->irq_enable) -+ ctrl_hci->irq_count++; -+#endif -+ mutex_lock(&hctl->hci_mutex); -+ if (hctl->int_status) { -+ u32 regval; -+ spin_lock_irqsave(&hctl->int_lock, flags); -+ hctl->int_mask |= hctl->int_status; -+ hctl->int_status = 0; -+ regval = ~ctrl_hci->int_mask; -+ smp_mb(); -+ spin_unlock_irqrestore(&hctl->int_lock, flags); -+ HCI_IRQ_SET_MASK(hctl, regval); -+ } -+ ret = HCI_IRQ_STATUS(hctl, &status); -+ if ((ret < 0) || ((status & hctl->int_mask) == 0)) { -+#ifdef CONFIG_IRQ_DEBUG_COUNT -+ if (ctrl_hci->irq_enable) -+ ctrl_hci->invalid_irq_count++; -+#endif -+ mutex_unlock(&hctl->hci_mutex); -+ ret = IRQ_NONE; -+ break; -+ } -+ spin_lock_irqsave(&hctl->int_lock, flags); -+ status &= hctl->int_mask; -+ spin_unlock_irqrestore(&hctl->int_lock, flags); -+ mutex_unlock(&hctl->hci_mutex); -+ ctrl_hci->isr_running = 1; -+ if (status & SSV6XXX_INT_RX) { -+ ret = _isr_do_rx(hctl, status); -+ if (ret < 0) { -+ ret = IRQ_NONE; -+ break; -+ } -+ dbg_isr_miss = false; -+ } -+ if (_do_tx(hctl, status)) { -+ dbg_isr_miss = false; -+ } -+ ctrl_hci->isr_running = 0; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (ctrl_hci->isr_mib_enable) { -+ getnstimeofday(&end_time); -+ diff_time = timespec_sub(end_time, start_time); -+ ctrl_hci->isr_total_time += timespec_to_ns(&diff_time); -+ } -+#endif -+ } while (1); -+ if (ctrl_hci->isr_summary_eable) { -+ if (dbg_isr_miss) -+ ctrl_hci->isr_miss_cnt++; -+ ctrl_hci->prev_isr_jiffes = jiffies; -+ } -+ return ret; -+} -+ -+static struct ssv6xxx_hci_ops hci_ops = { -+ .hci_start = ssv6xxx_hci_start, -+ .hci_stop = ssv6xxx_hci_stop, -+ .hci_read_word = ssv6xxx_hci_read_word, -+ .hci_write_word = ssv6xxx_hci_write_word, -+ .hci_tx = ssv6xxx_hci_enqueue, -+ .hci_tx_pause = ssv6xxx_hci_txq_pause, -+ .hci_tx_resume = ssv6xxx_hci_txq_resume, -+ .hci_txq_flush = ssv6xxx_hci_txq_flush, -+ .hci_txq_flush_by_sta = ssv6xxx_hci_txq_flush_by_sta, -+ .hci_txq_empty = ssv6xxx_hci_is_txq_empty, -+ .hci_load_fw = ssv6xxx_hci_load_fw, -+ .hci_pmu_wakeup = ssv6xxx_hci_pmu_wakeup, -+ .hci_send_cmd = ssv6xxx_hci_send_cmd, -+ .hci_write_sram = ssv6xxx_hci_write_sram, -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ .hci_init_debugfs = ssv6xxx_hci_init_debugfs, -+ .hci_deinit_debugfs = ssv6xxx_hci_deinit_debugfs, -+#endif -+ .hci_interface_reset = ssv6xxx_hci_interface_reset, -+}; -+ -+int ssv6xxx_hci_deregister(void) -+{ -+ u32 regval; -+ pr_debug("%s(): \n", __FUNCTION__); -+ if (ctrl_hci->shi == NULL) -+ return -1; -+ regval = 1; -+ ssv6xxx_hci_irq_disable(); -+ flush_workqueue(ctrl_hci->hci_work_queue); -+ destroy_workqueue(ctrl_hci->hci_work_queue); -+ ctrl_hci->shi = NULL; -+ return 0; -+} -+ -+EXPORT_SYMBOL(ssv6xxx_hci_deregister); -+int ssv6xxx_hci_register(struct ssv6xxx_hci_info *shi) -+{ -+ int i; -+ if (shi == NULL || ctrl_hci->shi) -+ return -1; -+ shi->hci_ops = &hci_ops; -+ ctrl_hci->shi = shi; -+ ctrl_hci->txq_mask = 0; -+ mutex_init(&ctrl_hci->txq_mask_lock); -+ mutex_init(&ctrl_hci->hci_mutex); -+ spin_lock_init(&ctrl_hci->int_lock); -+ -+ for (i = 0; i < SSV_HW_TXQ_NUM; i++) { -+ memset(&ctrl_hci->hw_txq[i], 0, sizeof(struct ssv_hw_txq)); -+ skb_queue_head_init(&ctrl_hci->hw_txq[i].qhead); -+ ctrl_hci->hw_txq[i].txq_no = (u32) i; -+ ctrl_hci->hw_txq[i].max_qsize = SSV_HW_TXQ_MAX_SIZE; -+ ctrl_hci->hw_txq[i].resum_thres = SSV_HW_TXQ_RESUME_THRES; -+ } -+ ctrl_hci->hci_work_queue = -+ create_singlethread_workqueue("ssv6xxx_hci_wq"); -+ INIT_WORK(&ctrl_hci->hci_rx_work, ssv6xxx_hci_rx_work); -+ INIT_WORK(&ctrl_hci->hci_tx_work, ssv6xxx_hci_tx_work); -+ ctrl_hci->int_mask = SSV6XXX_INT_RX | SSV6XXX_INT_RESOURCE_LOW; -+ ctrl_hci->int_status = 0; -+ HCI_IRQ_SET_MASK(ctrl_hci, 0xFFFFFFFF); -+ ssv6xxx_hci_irq_disable(); -+ HCI_IRQ_REQUEST(ctrl_hci, ssv6xxx_hci_isr); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ ctrl_hci->debugfs_dir = NULL; -+ ctrl_hci->isr_mib_enable = false; -+ ctrl_hci->isr_mib_reset = 0; -+ ctrl_hci->isr_total_time = 0; -+ ctrl_hci->isr_rx_io_time = 0; -+ ctrl_hci->isr_tx_io_time = 0; -+ ctrl_hci->isr_rx_io_count = 0; -+ ctrl_hci->isr_tx_io_count = 0; -+ ctrl_hci->isr_rx_proc_time = 0; -+#endif -+ return 0; -+} -+ -+EXPORT_SYMBOL(ssv6xxx_hci_register); -+int ssv6xxx_hci_init(void) -+{ -+#ifdef CONFIG_SSV6200_CLI_ENABLE -+ extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci; -+#endif -+ ctrl_hci = kzalloc(sizeof(*ctrl_hci), GFP_KERNEL); -+ if (ctrl_hci == NULL) -+ return -ENOMEM; -+ memset((void *)ctrl_hci, 0, sizeof(*ctrl_hci)); -+ ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE); -+ if (ctrl_hci->rx_buf == NULL) { -+ kfree(ctrl_hci); -+ return -ENOMEM; -+ } -+#ifdef CONFIG_SSV6200_CLI_ENABLE -+ ssv_dbg_ctrl_hci = ctrl_hci; -+#endif -+ return 0; -+} -+ -+void ssv6xxx_hci_exit(void) -+{ -+#ifdef CONFIG_SSV6200_CLI_ENABLE -+ extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci; -+#endif -+ kfree(ctrl_hci); -+ ctrl_hci = NULL; -+#ifdef CONFIG_SSV6200_CLI_ENABLE -+ ssv_dbg_ctrl_hci = NULL; -+#endif -+} -+ -+EXPORT_SYMBOL(ssv6xxx_hci_init); -+EXPORT_SYMBOL(ssv6xxx_hci_exit); -diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.h b/drivers/net/wireless/ssv6051/hci/ssv_hci.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.h -@@ -0,0 +1,77 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV_HCI_H_ -+#define _SSV_HCI_H_ -+#define SSV_HW_TXQ_NUM 5 -+#define SSV_HW_TXQ_MAX_SIZE 64 -+#define SSV_HW_TXQ_RESUME_THRES ((SSV_HW_TXQ_MAX_SIZE >> 2) *3) -+#define HCI_FLAGS_ENQUEUE_HEAD 0x00000001 -+#define HCI_FLAGS_NO_FLOWCTRL 0x00000002 -+struct ssv_hw_txq { -+ u32 txq_no; -+ struct sk_buff_head qhead; -+ int max_qsize; -+ int resum_thres; -+ bool paused; -+ u32 tx_pkt; -+ u32 tx_flags; -+}; -+struct ssv6xxx_hci_ops { -+ int (*hci_start)(void); -+ int (*hci_stop)(void); -+ int (*hci_read_word)(u32 addr, u32 * regval); -+ int (*hci_write_word)(u32 addr, u32 regval); -+ int (*hci_load_fw)(u8 * firmware_name, u8 openfile); -+ int (*hci_tx)(struct sk_buff *, int, u32); -+ int (*hci_tx_pause)(u32 txq_mask); -+ int (*hci_tx_resume)(u32 txq_mask); -+ int (*hci_txq_flush)(u32 txq_mask); -+ int (*hci_txq_flush_by_sta)(int aid); -+ bool (*hci_txq_empty)(int txqid); -+ int (*hci_pmu_wakeup)(void); -+ int (*hci_send_cmd)(struct sk_buff *); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ bool (*hci_init_debugfs)(struct dentry * dev_deugfs_dir); -+ void (*hci_deinit_debugfs)(void); -+#endif -+ int (*hci_write_sram)(u32 addr, u8 * data, u32 size); -+ int (*hci_interface_reset)(void); -+}; -+struct ssv6xxx_hci_info { -+ struct device *dev; -+ struct ssv6xxx_hwif_ops *if_ops; -+ struct ssv6xxx_hci_ops *hci_ops; -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+ int (*hci_rx_cb)(struct sk_buff_head *, void *); -+#else -+ int (*hci_rx_cb)(struct sk_buff *, void *); -+#endif -+ void *rx_cb_args; -+ void (*hci_tx_cb)(struct sk_buff_head *, void *); -+ void *tx_cb_args; -+ int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug); -+ void *tx_fctrl_cb_args; -+ void (*hci_tx_buf_free_cb)(struct sk_buff *, void *); -+ void *tx_buf_free_args; -+ void (*hci_skb_update_cb)(struct sk_buff *, void *); -+ void *skb_update_args; -+ void (*hci_tx_q_empty_cb)(u32 txq_no, void *); -+ void *tx_q_empty_args; -+}; -+int ssv6xxx_hci_deregister(void); -+int ssv6xxx_hci_register(struct ssv6xxx_hci_info *); -+#endif -diff --git a/drivers/net/wireless/ssv6051/hwif/hwif.h b/drivers/net/wireless/ssv6051/hwif/hwif.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/hwif/hwif.h -@@ -0,0 +1,84 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _LINUX_SSVCABRIO_PLATFORM_H -+#define _LINUX_SSVCABRIO_PLATFORM_H -+#include -+#include -+#define SSVCABRIO_PLAT_EEP_MAX_WORDS 2048 -+#define SSV_REG_WRITE(dev,reg,val) \ -+ (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val)) -+#define SSV_REG_READ(dev,reg,buf) \ -+ (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf)) -+#if 0 -+#define SSV_REG_WRITE(sh,reg,val) \ -+ (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val)) -+#define SSV_REG_READ(sh,reg,buf) \ -+ (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf)) -+#define SSV_REG_CONFIRM(sh,reg,val) \ -+{ \ -+ u32 regval; \ -+ SSV_REG_READ(sh, reg, ®val); \ -+ if (regval != (val)) { \ -+ printk("[0x%08x]: 0x%08x!=0x%08x\n",\ -+ (reg), (val), regval); \ -+ return -1; \ -+ } \ -+} -+#define SSV_REG_SET_BITS(sh,reg,set,clr) \ -+{ \ -+ u32 reg_val; \ -+ SSV_REG_READ(sh, reg, ®_val); \ -+ reg_val &= ~(clr); \ -+ reg_val |= (set); \ -+ SSV_REG_WRITE(sh, reg, reg_val); \ -+} -+#endif -+struct ssv6xxx_hwif_ops { -+ int __must_check (*read)(struct device *child, void *buf,size_t *size); -+ int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num); -+ int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf); -+ int __must_check (*writereg)(struct device *child, u32 addr, u32 buf); -+ int (*trigger_tx_rx)(struct device *child); -+ int (*irq_getmask)(struct device *child, u32 *mask); -+ void (*irq_setmask)(struct device *child,int mask); -+ void (*irq_enable)(struct device *child); -+ void (*irq_disable)(struct device *child,bool iswaitirq); -+ int (*irq_getstatus)(struct device *child,int *status); -+ void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev); -+ void (*irq_trigger)(struct device *child); -+ void (*pmu_wakeup)(struct device *child); -+ int __must_check (*load_fw)(struct device *child, u8 *firmware_name, u8 openfile); -+ int (*cmd52_read)(struct device *child, u32 addr, u32 *value); -+ int (*cmd52_write)(struct device *child, u32 addr, u32 value); -+ bool (*support_scatter)(struct device *child); -+ int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req); -+ bool (*is_ready)(struct device *child); -+ int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size); -+ void (*interface_reset)(struct device *child); -+}; -+struct ssv6xxx_if_debug { -+ struct device *dev; -+ struct platform_device *pdev; -+}; -+struct ssv6xxx_platform_data { -+ atomic_t irq_handling; -+ bool is_enabled; -+ unsigned short vendor; -+ unsigned short device; -+ struct ssv6xxx_hwif_ops *ops; -+}; -+#endif -diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c -@@ -0,0 +1,1254 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "sdio_def.h" -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define LOW_SPEED_SDIO_CLOCK (25000000) -+#define HIGH_SPEED_SDIO_CLOCK (37500000) -+#define MAX_RX_FRAME_SIZE 0x900 -+#define SSV_VENDOR_ID 0x3030 -+#define SSV_CABRIO_DEVID 0x3030 -+#define ENABLE_FW_SELF_CHECK 1 -+#define FW_BLOCK_SIZE 0x8000 -+#define CHECKSUM_BLOCK_SIZE 1024 -+#define FW_CHECKSUM_INIT (0x12345678) -+#define FW_STATUS_REG ADR_TX_SEG -+#define FW_STATUS_MASK (0x00FF0000) -+ -+#define ret_if_not_ready(value) \ -+ do { \ -+ if ((wlan_data.is_enabled == false) || \ -+ (glue == NULL) || (glue->dev_ready == false)) { \ -+ pr_warn("ret_if_not_ready() called when not ready"); \ -+ return value; }\ -+ } while(0) -+ -+static int ssv6xxx_sdio_trigger_pmu(struct device *dev); -+static void ssv6xxx_sdio_reset(struct device *child); -+ -+static void ssv6xxx_high_sdio_clk(struct sdio_func *func); -+static void ssv6xxx_low_sdio_clk(struct sdio_func *func); -+extern void *ssv6xxx_ifdebug_info[]; -+extern int ssv_devicetype; -+extern void ssv6xxx_deinit_prepare(void); -+ -+static struct ssv6xxx_platform_data wlan_data; -+ -+static int ssv6xxx_sdio_status = 0; -+u32 sdio_sr_bhvr = SUSPEND_RESUME_0; -+EXPORT_SYMBOL(sdio_sr_bhvr); -+ -+u32 shutdown_flags = SSV_SYS_REBOOT; -+ -+struct ssv6xxx_sdio_glue { -+ struct device *dev; -+ struct platform_device *core; -+ struct sk_buff *dma_skb; -+#ifdef CONFIG_PM -+ struct sk_buff *cmd_skb; -+#endif -+ unsigned int ioport_data; -+ unsigned int ioport_reg; -+ irq_handler_t irq_handler; -+ void *irq_dev; -+ bool dev_ready; -+}; -+ -+static const struct sdio_device_id ssv6xxx_sdio_devices[] = { -+ {SDIO_DEVICE(SSV_VENDOR_ID, SSV_CABRIO_DEVID)}, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(sdio, ssv6xxx_sdio_devices); -+ -+static bool ssv6xxx_is_ready(struct device *child) -+{ -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ -+ ret_if_not_ready(false); -+ -+ return true; -+} -+ -+static int ssv6xxx_sdio_cmd52_read(struct device *child, u32 addr, u32 * value) -+{ -+ int ret; -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ -+ ret_if_not_ready(-1); -+ -+ func = dev_to_sdio_func(glue->dev); -+ sdio_claim_host(func); -+ *value = sdio_readb(func, addr, &ret); -+ sdio_release_host(func); -+ -+ return ret; -+} -+ -+static int ssv6xxx_sdio_cmd52_write(struct device *child, u32 addr, u32 value) -+{ -+ int ret; -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ -+ ret_if_not_ready(-1); -+ -+ func = dev_to_sdio_func(glue->dev); -+ sdio_claim_host(func); -+ sdio_writeb(func, value, addr, &ret); -+ sdio_release_host(func); -+ -+ return ret; -+} -+ -+static int __must_check -+ssv6xxx_sdio_read_reg(struct device *child, u32 addr, u32 * buf) -+{ -+ int ret; -+ -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ u32 data; -+ -+ ret_if_not_ready(-1); -+ -+ func = dev_to_sdio_func(glue->dev); -+ -+ sdio_claim_host(func); -+ -+ data = addr; -+ -+ sdio_writel(func, addr, glue->ioport_reg, &ret); -+ -+ if (unlikely(ret)) { -+ dev_err(child->parent, "sdio read reg write address failed (%d)\n", ret); -+ goto io_err; -+ } -+ -+ data = sdio_readl(func, glue->ioport_reg, &ret); -+ -+ if (unlikely(ret)) { -+ *buf = 0xffffffff; -+ dev_err(child->parent, "sdio read reg from I/O failed (%d)\n", ret); -+ goto io_err; -+ } -+ -+ *buf = data; -+ -+io_err: -+ sdio_release_host(func); -+ -+ return ret; -+} -+ -+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE -+static int ssv6xxx_sdio_trigger_tx_rx(struct device *child) -+{ -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ struct mmc_host *host; -+ -+ if (glue == NULL) -+ return -1; -+ -+ func = dev_to_sdio_func(glue->dev); -+ host = func->card->host; -+ mmc_signal_sdio_irq(host); -+ -+ return 0; -+ -+} -+#endif -+ -+static int __must_check -+ssv6xxx_sdio_write_reg(struct device *child, u32 addr, u32 buf) -+{ -+ int ret; -+ -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ -+ u32 data[2]; -+ -+ ret_if_not_ready(-1); -+ -+ func = dev_to_sdio_func(glue->dev); -+ -+ sdio_claim_host(func); -+ data[0] = addr; -+ data[1] = buf; -+ -+ ret = sdio_memcpy_toio(func, glue->ioport_reg, data, sizeof(data)); -+ sdio_release_host(func); -+ -+ return ret; -+} -+ -+static int -+ssv6xxx_sdio_write_sram(struct device *child, u32 addr, u8 * data, u32 size) -+{ -+ int ret = 0; -+ struct ssv6xxx_sdio_glue *glue; -+ struct sdio_func *func = NULL; -+ glue = dev_get_drvdata(child->parent); -+ -+ ret_if_not_ready(-1); -+ -+ func = dev_to_sdio_func(glue->dev); -+ sdio_claim_host(func); -+ -+ ret |= ssv6xxx_sdio_write_reg(child, 0xc0000860, addr); -+ if (unlikely(ret)) -+ goto out; -+ -+ sdio_writeb(func, 0x2, REG_Fn1_STATUS, &ret); -+ if (unlikely(ret)) -+ goto out; -+ -+ ret = sdio_memcpy_toio(func, glue->ioport_data, data, size); -+ if (unlikely(ret)) -+ goto out; -+ -+ sdio_writeb(func, 0, REG_Fn1_STATUS, &ret); -+ if (unlikely(ret)) -+ goto out; -+ -+out: -+ sdio_release_host(func); -+ return ret; -+ -+} -+ -+struct file *ssv6xxx_open_firmware(char *user_mainfw) -+{ -+ struct file *fp; -+ fp = filp_open(user_mainfw, O_RDONLY, 0); -+ -+ if (IS_ERR(fp)) -+ fp = NULL; -+ -+ return fp; -+} -+ -+int ssv6xxx_read_fw_block(char *buf, int len, struct file *fp) -+{ -+ -+ int read; -+ loff_t pos; -+ -+ pos = fp->f_pos; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0) -+ read = kernel_read(fp, (void *)buf, len, &pos); -+#else -+ read = kernel_read(fp, pos, buf, len); -+#endif -+ -+ if (read > 0) -+ fp->f_pos += read; -+ -+ return read; -+ -+} -+ -+void ssv6xxx_close_firmware(struct file *fp) -+{ -+ if (fp) -+ filp_close(fp, NULL); -+} -+ -+static int -+ssv6xxx_sdio_upload_firmware(struct device *child, const u8 *firmware, u32 firmware_length) -+{ -+ int ret; -+ u32 clk_en; -+ u32 word_count, i; -+ u32 block_size; -+ u8 *buffer; -+ u32 sram_ptr = 0; -+ u32 block_count = 0; -+ u32 firmware_ptr = 0; -+ -+ u32 checksum = FW_CHECKSUM_INIT; -+ u32 fw_checksum, fw_blkcnt; -+ -+ struct ssv6xxx_sdio_glue *glue; -+ -+ glue = dev_get_drvdata(child->parent); -+ -+ if ((wlan_data.is_enabled == false) && -+ (glue == NULL) && -+ (glue->dev_ready == false)) -+ goto out; -+ -+ buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL); -+ if (buffer == NULL) { -+ dev_err(child, "Failed to allocate buffer for firmware.\n"); -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ dev_dbg(child, "preparing registers and clock for firmware upload\n"); -+ -+ ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x0); -+ if (unlikely(ret)) -+ goto out; -+ -+ ret = ssv6xxx_sdio_write_reg(child, ADR_BOOT, 0x01); -+ if (unlikely(ret)) -+ goto out; -+ -+ ret = ssv6xxx_sdio_read_reg(child, ADR_PLATFORM_CLOCK_ENABLE, &clk_en); -+ if (unlikely(ret)) -+ goto out; -+ -+ ret = ssv6xxx_sdio_write_reg(child, ADR_PLATFORM_CLOCK_ENABLE, clk_en | (1 << 2)); -+ if (unlikely(ret)) -+ goto out; -+ -+ dev_dbg(child, "begin writing firmware\n"); -+ -+ while (firmware_length > 0) { -+ -+ memset(buffer, 0xA5, FW_BLOCK_SIZE); -+ -+ block_size = firmware_length; -+ if (block_size > FW_BLOCK_SIZE) -+ block_size = FW_BLOCK_SIZE; -+ -+ memcpy(buffer, &firmware[firmware_ptr], block_size); -+ -+ firmware_ptr += block_size; -+ firmware_length -= block_size; -+ -+ /* -+ * Uploading to chip sram and checksumming happens in chunks of CHECKSUM_BLOCK_SIZE, -+ * so we round the block size accordingly and use that valueù -+ */ -+ block_size = DIV_ROUND_UP(block_size, CHECKSUM_BLOCK_SIZE) * CHECKSUM_BLOCK_SIZE; -+ ret = ssv6xxx_sdio_write_sram(child, sram_ptr, (u8 *)buffer, block_size); -+ -+ if (ret) { -+ dev_err(child, "firmware upload failed\n"); -+ goto out; -+ } -+ -+ sram_ptr += block_size; -+ -+ word_count = block_size / sizeof(u32); -+ for (i = 0; i < word_count; i++) -+ checksum += ((u32 *)buffer)[i]; -+ -+ } -+ -+ checksum = ((checksum >> 24) + -+ (checksum >> 16) + -+ (checksum >> 8) + -+ checksum) & 0x0FF; -+ checksum <<= 16; -+ -+ block_count = DIV_ROUND_UP(sram_ptr, CHECKSUM_BLOCK_SIZE); -+ ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (block_count << 16)); -+ if (unlikely(ret)) -+ goto out; -+ -+ ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_blkcnt); -+ if (unlikely(ret)) -+ goto out; -+ -+ ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x1); -+ if (unlikely(ret)) -+ goto out; -+ -+ dev_info(child, "firmware upload complete (wrote %d blocks, verified %d blocks)\n", block_count, fw_blkcnt >> 16); -+ -+ msleep(50); -+ -+ ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_checksum); -+ fw_checksum = fw_checksum & FW_STATUS_MASK; -+ -+ if (fw_checksum == checksum) { -+ dev_dbg(child, "firmware check ok, checksum=0x%x\n", checksum); -+ ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (~checksum & FW_STATUS_MASK)); -+ if (unlikely(ret)) -+ dev_warn(child, "could not clear checksum condition"); -+ } else { -+ dev_err(child, "firmware checksum mismatch, local=0x%x, sram=0x%x\n", checksum, fw_checksum); -+ } -+ -+ msleep(50); -+ -+ ret = 0; -+ -+ out: -+ -+ if (buffer) -+ kfree(buffer); -+ -+ return ret; -+ -+} -+ -+static int -+ssv6xxx_sdio_load_firmware(struct device *child, u8 *firmware_name, u8 openfile) -+{ -+ -+ int ret; -+ const struct firmware *firmware = NULL; -+ struct sdio_func *func; -+ struct ssv6xxx_sdio_glue *glue; -+ -+ glue = dev_get_drvdata(child->parent); -+ -+ ret = request_firmware(&firmware, firmware_name, glue->dev); -+ -+ if (ret) { -+ dev_err(child, "could not find firmware file %s, err=%d\n", firmware_name, ret); -+ goto out; -+ } -+ -+ ret = ssv6xxx_sdio_upload_firmware(child, firmware->data, firmware->size); -+ -+ if (ret) { -+ dev_err(child, "could not upload firmware to device, err=%d\n", ret); -+ goto out; -+ } -+ -+ if (glue != NULL) { -+ func = dev_to_sdio_func(glue->dev); -+ ssv6xxx_high_sdio_clk(func); -+ } -+ -+out: -+ if (firmware != NULL) -+ release_firmware(firmware); -+ -+ return ret; -+ -+} -+ -+static int ssv6xxx_sdio_irq_getstatus(struct device *child, int *status) -+{ -+ int ret = (-1); -+ struct ssv6xxx_sdio_glue *glue; -+ struct sdio_func *func; -+ glue = dev_get_drvdata(child->parent); -+ -+ ret_if_not_ready(-1); -+ -+ func = dev_to_sdio_func(glue->dev); -+ sdio_claim_host(func); -+ *status = sdio_readb(func, REG_INT_STATUS, &ret); -+ sdio_release_host(func); -+ -+ return ret; -+ -+} -+ -+static int __must_check -+ssv6xxx_sdio_read(struct device *child, void *buf, size_t *size) -+{ -+ -+ int ret; -+ u32 data_size; -+ -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ -+ ret_if_not_ready(-1); -+ -+ func = dev_to_sdio_func(glue->dev); -+ sdio_claim_host(func); -+ -+ data_size = sdio_readb(func, REG_CARD_PKT_LEN_0, &ret); -+ -+ if (unlikely(ret)) { -+ dev_err(child->parent, "sdio read high byte len failed, ret=%d\n", ret); -+ goto out; -+ } -+ -+ data_size = data_size | (sdio_readb(func, REG_CARD_PKT_LEN_1, &ret) << 0x8); -+ -+ if (unlikely(ret)) { -+ dev_err(child->parent, "sdio read low len failed ret[%d]\n", ret); -+ goto out; -+ } -+ -+ ret = sdio_memcpy_fromio(func, buf, glue->ioport_data, sdio_align_size(func, data_size)); -+ -+ if (unlikely(ret)) { -+ dev_err(child->parent, "sdio read failed size ret[%d]\n", ret); -+ goto out; -+ } -+ -+ *size = data_size; -+ -+out: -+ -+ sdio_release_host(func); -+ -+ return ret; -+} -+ -+static int __must_check -+ssv6xxx_sdio_write(struct device *child, void *buf, size_t len, u8 queue_num) -+{ -+ int ret; -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ void *ptr; -+ -+ ret_if_not_ready(-1); -+ -+#ifdef CONFIG_ARM64 -+ if (((u64) buf) & 3) { -+#else -+ if (((u32) buf) & 3) { -+#endif -+ memcpy(glue->dma_skb->data, buf, len); -+ ptr = glue->dma_skb->data; -+ } else -+ ptr = buf; -+ -+ func = dev_to_sdio_func(glue->dev); -+ -+ sdio_claim_host(func); -+ -+ len = sdio_align_size(func, len); -+ ret = sdio_memcpy_toio(func, glue->ioport_data, ptr, len); -+ -+ if (unlikely(ret)) -+ dev_err(glue->dev, "sdio write failed, ret=%d\n", ret); -+ -+ sdio_release_host(func); -+ -+ return ret; -+ -+} -+ -+static void ssv6xxx_sdio_irq_handler(struct sdio_func *func) -+{ -+ int status; -+ struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func); -+ struct ssv6xxx_platform_data *pwlan_data = &wlan_data; -+ -+ ret_if_not_ready(); -+ -+ if (glue->irq_handler == NULL) -+ return; -+ -+ atomic_set(&pwlan_data->irq_handling, 1); -+ sdio_release_host(func); -+ if (glue->irq_handler != NULL) -+ status = glue->irq_handler(0, glue->irq_dev); -+ sdio_claim_host(func); -+ atomic_set(&pwlan_data->irq_handling, 0); -+ -+} -+ -+static void ssv6xxx_sdio_irq_setmask(struct device *child, int mask) -+{ -+ int err_ret; -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ -+ ret_if_not_ready(); -+ -+ func = dev_to_sdio_func(glue->dev); -+ sdio_claim_host(func); -+ sdio_writeb(func, mask, REG_INT_MASK, &err_ret); -+ sdio_release_host(func); -+ -+} -+ -+static void ssv6xxx_sdio_irq_trigger(struct device *child) -+{ -+ int err_ret; -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ -+ ret_if_not_ready(); -+ -+ func = dev_to_sdio_func(glue->dev); -+ sdio_claim_host(func); -+ sdio_writeb(func, 0x2, REG_INT_TRIGGER, &err_ret); -+ sdio_release_host(func); -+ -+} -+ -+static int ssv6xxx_sdio_irq_getmask(struct device *child, u32 * mask) -+{ -+ u8 imask = 0; -+ int ret = (-1); -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ -+ ret_if_not_ready(-1); -+ -+ func = dev_to_sdio_func(glue->dev); -+ sdio_claim_host(func); -+ imask = sdio_readb(func, REG_INT_MASK, &ret); -+ *mask = imask; -+ sdio_release_host(func); -+ -+ return ret; -+ -+} -+ -+static void ssv6xxx_sdio_irq_enable(struct device *child) -+{ -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ int ret; -+ struct ssv6xxx_platform_data *pwlan_data = &wlan_data; -+ if ((pwlan_data->is_enabled == false) -+ || (glue == NULL) || (glue->dev_ready == false)) -+ return; -+ -+ func = dev_to_sdio_func(glue->dev); -+ sdio_claim_host(func); -+ ret = sdio_claim_irq(func, ssv6xxx_sdio_irq_handler); -+ if (ret) -+ dev_err(child->parent, "Failed to claim sdio irq: %d\n", -+ ret); -+ sdio_release_host(func); -+ -+ dev_dbg(child, "ssv6xxx_sdio_irq_enable\n"); -+ -+} -+ -+static void ssv6xxx_sdio_irq_disable(struct device *child, bool iswaitirq) -+{ -+ struct ssv6xxx_sdio_glue *glue = NULL; -+ struct sdio_func *func; -+ struct ssv6xxx_platform_data *pwlan_data = &wlan_data; -+ int ret; -+ -+ dev_dbg(child, "ssv6xxx_sdio_irq_disable\n"); -+ -+ if ((wlan_data.is_enabled == false) || (child->parent == NULL)) -+ return; -+ -+ glue = dev_get_drvdata(child->parent); -+ -+ -+ if ((glue == NULL) || (glue->dev_ready == false) -+ || (glue->dev == NULL)) -+ return; -+ -+ func = dev_to_sdio_func(glue->dev); -+ -+ if (func == NULL) { -+ dev_dbg(child, "sdio func == NULL\n"); -+ return; -+ } -+ -+ sdio_claim_host(func); -+ while (atomic_read(&pwlan_data->irq_handling)) { -+ sdio_release_host(func); -+ schedule_timeout(HZ / 10); -+ sdio_claim_host(func); -+ } -+ ret = sdio_release_irq(func); -+ -+ if (ret) -+ dev_err(child->parent, -+ "Failed to release sdio irq: %d\n", ret); -+ -+ sdio_release_host(func); -+ -+} -+ -+static void -+ssv6xxx_sdio_irq_request(struct device *child, irq_handler_t irq_handler, -+ void *irq_dev) -+{ -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ bool isIrqEn = false; -+ -+ ret_if_not_ready(); -+ -+ func = dev_to_sdio_func(glue->dev); -+ glue->irq_handler = irq_handler; -+ glue->irq_dev = irq_dev; -+ if (isIrqEn) { -+ ssv6xxx_sdio_irq_enable(child); -+ } -+ -+} -+ -+static void -+ssv6xxx_sdio_read_parameter(struct sdio_func *func, -+ struct ssv6xxx_sdio_glue *glue) -+{ -+ int err_ret; -+ sdio_claim_host(func); -+ glue->ioport_data = 0; -+ glue->ioport_data = -+ glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret) -+ << (8 * 0)); -+ glue->ioport_data = -+ glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret) -+ << (8 * 1)); -+ glue->ioport_data = -+ glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret) -+ << (8 * 2)); -+ glue->ioport_reg = 0; -+ glue->ioport_reg = -+ glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) << -+ (8 * 0)); -+ glue->ioport_reg = -+ glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) << -+ (8 * 1)); -+ glue->ioport_reg = -+ glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) << -+ (8 * 2)); -+ dev_dbg(&func->dev, "ioport_data=0x%x ioport_reg=0x%x\n", -+ glue->ioport_data, glue->ioport_reg); -+ err_ret = sdio_set_block_size(func, CONFIG_PLATFORM_SDIO_BLOCK_SIZE); -+ if (err_ret != 0) { -+ dev_warn(&func->dev, "SDIO setting SDIO_DEF_BLOCK_SIZE fail!!\n"); -+ } -+ sdio_writeb(func, CONFIG_PLATFORM_SDIO_OUTPUT_TIMING, -+ REG_OUTPUT_TIMING_REG, &err_ret); -+ sdio_writeb(func, 0x00, REG_Fn1_STATUS, &err_ret); -+ sdio_release_host(func); -+} -+ -+static void ssv6xxx_do_sdio_wakeup(struct sdio_func *func) -+{ -+ int err_ret; -+ if (func != NULL) { -+ sdio_claim_host(func); -+ sdio_writeb(func, 0x01, REG_PMU_WAKEUP, &err_ret); -+ mdelay(10); -+ sdio_writeb(func, 0x00, REG_PMU_WAKEUP, &err_ret); -+ sdio_release_host(func); -+ } -+} -+ -+static void ssv6xxx_sdio_pmu_wakeup(struct device *child) -+{ -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ if (glue != NULL) { -+ func = dev_to_sdio_func(glue->dev); -+ ssv6xxx_do_sdio_wakeup(func); -+ } -+} -+ -+static bool ssv6xxx_sdio_support_scatter(struct device *child) -+{ -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ -+ if (!glue) { -+ dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n"); -+ return false; -+ } -+ -+ func = dev_to_sdio_func(glue->dev); -+ -+ if (func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) { -+ dev_err(child->parent, -+ "host controller only supports scatter of :%d entries, driver need: %d\n", -+ func->card->host->max_segs, -+ MAX_SCATTER_ENTRIES_PER_REQ); -+ return false; -+ } -+ -+ return true; -+ -+} -+ -+static void -+ssv6xxx_sdio_setup_scat_data(struct sdio_scatter_req *scat_req, -+ struct mmc_data *data) -+{ -+ struct scatterlist *sg; -+ int i; -+ data->blksz = SDIO_DEF_BLOCK_SIZE; -+ data->blocks = scat_req->len / SDIO_DEF_BLOCK_SIZE; -+ pr_debug -+ ("scatter: (%s) (block len: %d, block count: %d) , (tot:%d,sg:%d)\n", -+ (scat_req->req & SDIO_WRITE) ? "WR" : "RD", data->blksz, -+ data->blocks, scat_req->len, scat_req->scat_entries); -+ data->flags = -+ (scat_req->req & SDIO_WRITE) ? MMC_DATA_WRITE : MMC_DATA_READ; -+ sg = scat_req->sgentries; -+ sg_init_table(sg, scat_req->scat_entries); -+ for (i = 0; i < scat_req->scat_entries; i++, sg++) { -+ pr_debug("%d: addr:0x%p, len:%d\n", -+ i, scat_req->scat_list[i].buf, -+ scat_req->scat_list[i].len); -+ sg_set_buf(sg, scat_req->scat_list[i].buf, -+ scat_req->scat_list[i].len); -+ } -+ data->sg = scat_req->sgentries; -+ data->sg_len = scat_req->scat_entries; -+} -+ -+static inline void -+ssv6xxx_sdio_set_cmd53_arg(u32 * arg, u8 rw, u8 func, -+ u8 mode, u8 opcode, u32 addr, u16 blksz) -+{ -+ *arg = (((rw & 1) << 31) | -+ ((func & 0x7) << 28) | -+ ((mode & 1) << 27) | -+ ((opcode & 1) << 26) | ((addr & 0x1FFFF) << 9) | (blksz & -+ 0x1FF)); -+} -+ -+static int -+ssv6xxx_sdio_rw_scatter(struct device *child, struct sdio_scatter_req *scat_req) -+{ -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func; -+ struct mmc_request mmc_req; -+ struct mmc_command cmd; -+ struct mmc_data data; -+ u8 opcode, rw; -+ int status = 1; -+ -+ if (!glue) { -+ dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n"); -+ return 1; -+ } -+ -+ func = dev_to_sdio_func(glue->dev); -+ memset(&mmc_req, 0, sizeof(struct mmc_request)); -+ memset(&cmd, 0, sizeof(struct mmc_command)); -+ memset(&data, 0, sizeof(struct mmc_data)); -+ ssv6xxx_sdio_setup_scat_data(scat_req, &data); -+ opcode = 0; -+ rw = (scat_req->req & SDIO_WRITE) ? CMD53_ARG_WRITE : -+ CMD53_ARG_READ; -+ ssv6xxx_sdio_set_cmd53_arg(&cmd.arg, rw, func->num, -+ CMD53_ARG_BLOCK_BASIS, opcode, -+ glue->ioport_data, data.blocks); -+ cmd.opcode = SD_IO_RW_EXTENDED; -+ cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC; -+ mmc_req.cmd = &cmd; -+ mmc_req.data = &data; -+ mmc_set_data_timeout(&data, func->card); -+ mmc_wait_for_req(func->card->host, &mmc_req); -+ -+ status = cmd.error ? cmd.error : data.error; -+ -+ if (cmd.error) -+ return cmd.error; -+ -+ if (data.error) -+ return data.error; -+ -+ return status; -+ -+} -+ -+static void ssv6xxx_set_sdio_clk(struct sdio_func *func, u32 sdio_hz) -+{ -+ struct mmc_host *host; -+ host = func->card->host; -+ if (sdio_hz < host->f_min) -+ sdio_hz = host->f_min; -+ else if (sdio_hz > host->f_max) -+ sdio_hz = host->f_max; -+ dev_dbg(&func->dev, "%s:set sdio clk %dHz\n", __FUNCTION__, sdio_hz); -+ sdio_claim_host(func); -+ host->ios.clock = sdio_hz; -+ host->ops->set_ios(host, &host->ios); -+ mdelay(20); -+ sdio_release_host(func); -+} -+ -+static void ssv6xxx_low_sdio_clk(struct sdio_func *func) -+{ -+ ssv6xxx_set_sdio_clk(func, LOW_SPEED_SDIO_CLOCK); -+} -+ -+static void ssv6xxx_high_sdio_clk(struct sdio_func *func) -+{ -+#ifndef SDIO_USE_SLOW_CLOCK -+ ssv6xxx_set_sdio_clk(func, HIGH_SPEED_SDIO_CLOCK); -+#endif -+} -+ -+static struct ssv6xxx_hwif_ops sdio_ops = { -+ .read = ssv6xxx_sdio_read, -+ .write = ssv6xxx_sdio_write, -+ .readreg = ssv6xxx_sdio_read_reg, -+ .writereg = ssv6xxx_sdio_write_reg, -+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE -+ .trigger_tx_rx = ssv6xxx_sdio_trigger_tx_rx, -+#endif -+ .irq_getmask = ssv6xxx_sdio_irq_getmask, -+ .irq_setmask = ssv6xxx_sdio_irq_setmask, -+ .irq_enable = ssv6xxx_sdio_irq_enable, -+ .irq_disable = ssv6xxx_sdio_irq_disable, -+ .irq_getstatus = ssv6xxx_sdio_irq_getstatus, -+ .irq_request = ssv6xxx_sdio_irq_request, -+ .irq_trigger = ssv6xxx_sdio_irq_trigger, -+ .pmu_wakeup = ssv6xxx_sdio_pmu_wakeup, -+ .load_fw = ssv6xxx_sdio_load_firmware, -+ .cmd52_read = ssv6xxx_sdio_cmd52_read, -+ .cmd52_write = ssv6xxx_sdio_cmd52_write, -+ .support_scatter = ssv6xxx_sdio_support_scatter, -+ .rw_scatter = ssv6xxx_sdio_rw_scatter, -+ .is_ready = ssv6xxx_is_ready, -+ .write_sram = ssv6xxx_sdio_write_sram, -+ .interface_reset = ssv6xxx_sdio_reset, -+}; -+ -+static int -+ssv6xxx_sdio_power_on(struct ssv6xxx_platform_data *pdata, -+ struct sdio_func *func) -+{ -+ int ret = 0; -+ if (pdata->is_enabled == true) -+ return 0; -+ -+ dev_dbg(&func->dev, "ssv6xxx_sdio_power_on\n"); -+ -+ sdio_claim_host(func); -+ ret = sdio_enable_func(func); -+ sdio_release_host(func); -+ -+ if (ret) { -+ dev_err(&func->dev, "Unable to enable sdio func: %d)\n", ret); -+ return ret; -+ } -+ -+ msleep(10); -+ pdata->is_enabled = true; -+ -+ return ret; -+} -+ -+static int -+ssv6xxx_sdio_power_off(struct ssv6xxx_platform_data *pdata, -+ struct sdio_func *func) -+{ -+ int ret; -+ if (pdata->is_enabled == false) -+ return 0; -+ dev_dbg(&func->dev, "ssv6xxx_sdio_power_off\n"); -+ sdio_claim_host(func); -+ ret = sdio_disable_func(func); -+ sdio_release_host(func); -+ if (ret) -+ return ret; -+ pdata->is_enabled = false; -+ return ret; -+} -+ -+int ssv6xxx_get_dev_status(void) -+{ -+ return ssv6xxx_sdio_status; -+} -+ -+EXPORT_SYMBOL(ssv6xxx_get_dev_status); -+ -+static int -+ssv6xxx_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id) -+{ -+ struct ssv6xxx_platform_data *pwlan_data = &wlan_data; -+ struct ssv6xxx_sdio_glue *glue; -+ int ret; -+ const char *chip_family = "ssv6200"; -+ -+ if (ssv_devicetype != 0) { -+ dev_info(&func->dev, "Not using SSV6200 normal SDIO driver.\n"); -+ return -ENODEV; -+ } -+ -+ if (func->num != 0x01) -+ return -ENODEV; -+ -+ glue = kzalloc(sizeof(*glue), GFP_KERNEL); -+ -+ if (!glue) { -+ dev_err(&func->dev, "can't allocate glue\n"); -+ return -ENOMEM; -+ } -+ -+ ssv6xxx_sdio_status = 1; -+ ssv6xxx_low_sdio_clk(func); -+ -+ glue->dma_skb = __dev_alloc_skb(SDIO_DMA_BUFFER_LEN, GFP_KERNEL); -+ -+#ifdef CONFIG_PM -+ glue->cmd_skb = __dev_alloc_skb(SDIO_COMMAND_BUFFER_LEN, GFP_KERNEL); -+#endif -+ memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data)); -+ atomic_set(&pwlan_data->irq_handling, 0); -+ glue->dev = &func->dev; -+ func->card->quirks |= MMC_QUIRK_LENIENT_FN0; -+ func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE; -+ glue->dev_ready = true; -+ pwlan_data->vendor = func->vendor; -+ pwlan_data->device = func->device; -+ dev_info(glue->dev, "device id: %x:%x\n", pwlan_data->vendor, -+ pwlan_data->device); -+ pwlan_data->ops = &sdio_ops; -+ sdio_set_drvdata(func, glue); -+#ifdef CONFIG_PM -+ ssv6xxx_do_sdio_wakeup(func); -+#endif -+ ssv6xxx_sdio_power_on(pwlan_data, func); -+ ssv6xxx_sdio_read_parameter(func, glue); -+ glue->core = platform_device_alloc(chip_family, -1); -+ -+ if (!glue->core) { -+ dev_err(glue->dev, "can't allocate platform_device"); -+ ret = -ENOMEM; -+ goto out_free_glue; -+ } -+ -+ glue->core->dev.parent = &func->dev; -+ -+ ret = platform_device_add_data(glue->core, pwlan_data, -+ sizeof(*pwlan_data)); -+ -+ if (ret) { -+ dev_err(glue->dev, "can't add platform data\n"); -+ goto out_dev_put; -+ } -+ -+ ret = platform_device_add(glue->core); -+ -+ if (ret) { -+ dev_err(glue->dev, "can't add platform device\n"); -+ goto out_dev_put; -+ } -+ -+ ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff); -+ -+ ssv6xxx_ifdebug_info[0] = (void *)&glue->core->dev; -+ ssv6xxx_ifdebug_info[1] = (void *)glue->core; -+ ssv6xxx_ifdebug_info[2] = (void *)&sdio_ops; -+ return 0; -+ -+ out_dev_put: -+ platform_device_put(glue->core); -+ out_free_glue: -+ kfree(glue); -+ -+ return ret; -+ -+} -+ -+static void ssv6xxx_sdio_remove(struct sdio_func *func) -+{ -+ struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func); -+ struct ssv6xxx_platform_data *pwlan_data = &wlan_data; -+ -+ dev_dbg(&func->dev, "ssv6xxx_sdio_remove enter\n"); -+ -+ ssv6xxx_sdio_status = 0; -+ -+ if (glue) { -+ dev_dbg(&func->dev, "ssv6xxx_sdio_remove - ssv6xxx_sdio_irq_disable\n"); -+ ssv6xxx_sdio_irq_disable(&glue->core->dev, false); -+ glue->dev_ready = false; -+ ssv6xxx_low_sdio_clk(func); -+ -+ if (glue->dma_skb != NULL) -+ dev_kfree_skb(glue->dma_skb); -+ -+ dev_dbg(&func->dev, "ssv6xxx_sdio_remove - disable mask\n"); -+ ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff); -+#ifdef CONFIG_PM -+ ssv6xxx_sdio_trigger_pmu(glue->dev); -+ if (glue->cmd_skb != NULL) -+ dev_kfree_skb(glue->cmd_skb); -+#endif -+ ssv6xxx_sdio_power_off(pwlan_data, func); -+ dev_dbg(&func->dev, "platform_device_del \n"); -+ platform_device_del(glue->core); -+ dev_dbg(&func->dev, "platform_device_put \n"); -+ platform_device_put(glue->core); -+ kfree(glue); -+ } -+ -+ sdio_set_drvdata(func, NULL); -+ dev_dbg(&func->dev, "ssv6xxx_sdio_remove leave\n"); -+ -+} -+ -+static int ssv6xxx_sdio_trigger_pmu(struct device *dev) -+{ -+ -+ int ret = 0; -+ -+#ifdef CONFIG_PM -+ struct sdio_func *func = dev_to_sdio_func(dev); -+ struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func); -+ struct cfg_host_cmd *host_cmd; -+ int writesize; -+ void *tempPointer; -+ -+ if (ssv6xxx_sdio_write_reg -+ (dev, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ; -+ if (ssv6xxx_sdio_write_reg -+ (dev, ADR_RX_FLOW_DATA, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ; -+ if (ssv6xxx_sdio_write_reg -+ (dev, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ; -+ -+ host_cmd = (struct cfg_host_cmd *)glue->cmd_skb->data; -+ host_cmd->c_type = HOST_CMD; -+ host_cmd->RSVD0 = 0; -+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS; -+ host_cmd->len = sizeof(struct cfg_host_cmd); -+ -+ host_cmd->dummy = 0; -+ -+ { -+ tempPointer = glue->cmd_skb->data; -+ sdio_claim_host(func); -+ writesize = sdio_align_size(func, sizeof(struct cfg_host_cmd)); -+ do { -+ ret = -+ sdio_memcpy_toio(func, glue->ioport_data, -+ tempPointer, writesize); -+ if (ret == -EILSEQ || ret == -ETIMEDOUT) { -+ ret = -1; -+ break; -+ } else { -+ if (ret) -+ dev_err(glue->dev, -+ "Unexpected return value ret=[%d]\n", -+ ret); -+ } -+ } -+ while (ret == -EILSEQ || ret == -ETIMEDOUT); -+ sdio_release_host(func); -+ if (ret) -+ dev_err(glue->dev, "sdio write failed (%d)\n", ret); -+ } -+ -+#endif -+ -+ return ret; -+ -+} -+ -+static void ssv6xxx_sdio_reset(struct device *child) -+{ -+ -+#ifdef CONFIG_PM -+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent); -+ struct sdio_func *func = dev_to_sdio_func(glue->dev); -+ dev_dbg(child, "%s\n", __FUNCTION__); -+ if (glue == NULL || glue->dev == NULL || func == NULL) -+ return; -+ ssv6xxx_sdio_trigger_pmu(glue->dev); -+ ssv6xxx_do_sdio_wakeup(func); -+#endif -+ -+ return; -+ -+} -+ -+#ifdef CONFIG_PM -+static int ssv6xxx_sdio_suspend(struct device *dev) -+{ -+ struct sdio_func *func = dev_to_sdio_func(dev); -+ mmc_pm_flag_t flags = sdio_get_host_pm_caps(func); -+ { -+ int ret = 0; -+ dev_info(dev, "%s: suspend: PM flags = 0x%x\n", -+ sdio_func_id(func), flags); -+ ssv6xxx_low_sdio_clk(func); -+ ret = ssv6xxx_sdio_trigger_pmu(dev); -+ if (ret) -+ dev_warn(dev, "ssv6xxx_sdio_trigger_pmu fail!!\n"); -+ if (!(flags & MMC_PM_KEEP_POWER)) { -+ dev_err(dev, -+ "%s: cannot remain alive while host is suspended\n", -+ sdio_func_id(func)); -+ } -+ ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); -+ if (ret) -+ return ret; -+ mdelay(10); -+ return ret; -+ } -+} -+ -+static int ssv6xxx_sdio_resume(struct device *dev) -+{ -+ struct sdio_func *func = dev_to_sdio_func(dev); -+ { -+ dev_dbg(dev, "ssv6xxx_sdio_resume\n"); -+ { -+ ssv6xxx_do_sdio_wakeup(func); -+ mdelay(10); -+ ssv6xxx_high_sdio_clk(func); -+ mdelay(10); -+ } -+ } -+ return 0; -+} -+ -+static const struct dev_pm_ops ssv6xxx_sdio_pm_ops = { -+ .suspend = ssv6xxx_sdio_suspend, -+ .resume = ssv6xxx_sdio_resume, -+}; -+#endif -+ -+struct sdio_driver ssv6xxx_sdio_driver = { -+ .name = "ssv6051", -+ .id_table = ssv6xxx_sdio_devices, -+ .probe = ssv6xxx_sdio_probe, -+ .remove = ssv6xxx_sdio_remove, -+#ifdef CONFIG_PM -+ .drv = { -+ .pm = &ssv6xxx_sdio_pm_ops, -+ }, -+#endif -+}; -+ -+EXPORT_SYMBOL(ssv6xxx_sdio_driver); -+ -+int ssv6xxx_sdio_init(void) -+{ -+ return sdio_register_driver(&ssv6xxx_sdio_driver); -+} -+ -+void ssv6xxx_sdio_exit(void) -+{ -+ pr_info("ssv6xxx_sdio_exit\n"); -+ sdio_unregister_driver(&ssv6xxx_sdio_driver); -+} -+ -+EXPORT_SYMBOL(ssv6xxx_sdio_init); -+EXPORT_SYMBOL(ssv6xxx_sdio_exit); -diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h -@@ -0,0 +1,80 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SDIO_DEF_H_ -+#define _SDIO_DEF_H_ -+#include -+#define BASE_SDIO 0 -+#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00) -+#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01) -+#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02) -+#define REG_INT_MASK (BASE_SDIO + 0x04) -+#define REG_INT_STATUS (BASE_SDIO + 0x08) -+#define REG_INT_TRIGGER (BASE_SDIO + 0x09) -+#define REG_Fn1_STATUS (BASE_SDIO + 0x0c) -+#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10) -+#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11) -+#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12) -+#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13) -+#define REG_CARD_RCA_0 (BASE_SDIO + 0x20) -+#define REG_CARD_RCA_1 (BASE_SDIO + 0x21) -+#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24) -+#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25) -+#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55) -+#define REG_PMU_WAKEUP (BASE_SDIO + 0x67) -+#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70) -+#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71) -+#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72) -+#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98) -+#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99) -+#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a) -+#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c) -+#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d) -+#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e) -+#define SDIO_DEF_BLOCK_SIZE 0x80 -+#if (SDIO_DEF_BLOCK_SIZE % 8) -+#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!! -+#endif -+#define SDIO_DEF_OUTPUT_TIMING 0 -+#define SDIO_DEF_BLOCK_MODE_THRD 128 -+#if (SDIO_DEF_BLOCK_MODE_THRD % 8) -+#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!! -+#endif -+#define SDIO_DEF_FORCE_BLOCK_MODE 0 -+#define MAX_SCATTER_ENTRIES_PER_REQ 8 -+struct sdio_scatter_item { -+ u8 *buf; -+ int len; -+}; -+struct sdio_scatter_req { -+ u32 req; -+ u32 len; -+ int scat_entries; -+ struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ]; -+ struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ]; -+}; -+#define SDIO_READ 0x00000001 -+#define SDIO_WRITE 0x00000002 -+#define CMD53_ARG_READ 0 -+#define CMD53_ARG_WRITE 1 -+#define CMD53_ARG_BLOCK_BASIS 1 -+#define CMD53_ARG_FIXED_ADDRESS 0 -+#define CMD53_ARG_INCR_ADDRESS 1 -+#define SDIO_DMA_BUFFER_LEN 2048 -+#ifdef CONFIG_PM -+#define SDIO_COMMAND_BUFFER_LEN 256 -+#endif -+#endif -diff --git a/drivers/net/wireless/ssv6051/include/cabrio.h b/drivers/net/wireless/ssv6051/include/cabrio.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/include/cabrio.h -@@ -0,0 +1,28 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef CABRIO_H -+#define CABRIO_H -+#define SSV_VENDOR_ID 0x3030 -+#define SSV_CABRIO_DEVID 0x3030 -+#define SSV_SUBVENDOR_ID_NOG 0x0e11 -+#define SSV_SUBVENDOR_ID_NEW_A 0x7065 -+#define SSV_CABRIO_MAGIC 0x19641014 -+#define SSV_AMPDU_LIMIT_MAX (64 * 1024 - 1) -+#define SSV_DEFAULT_NOISE_FLOOR -95 -+#define SSVCABRIO_RSSI_BAD -128 -+#define SSVCABRIO_NUM_CHANNELS 38 -+#endif -diff --git a/drivers/net/wireless/ssv6051/include/ssv6200.h b/drivers/net/wireless/ssv6051/include/ssv6200.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/include/ssv6200.h -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV6200_H_ -+#define _SSV6200_H_ -+#include -+#include -+#include -+#ifdef ECLIPSE -+#include -+#endif -+#include -+#include -+#include -+#include -+#include "ssv6200_common.h" -+#define SSV6200_TOTAL_ID 128 -+#ifndef HUW_DRV -+#define SSV6200_ID_TX_THRESHOLD 19 -+#define SSV6200_ID_RX_THRESHOLD 60 -+#define SSV6200_PAGE_TX_THRESHOLD 115 -+#define SSV6200_PAGE_RX_THRESHOLD 115 -+#define SSV6XXX_AMPDU_DIVIDER (2) -+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6XXX_AMPDU_DIVIDER)) -+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2 -+#else -+#undef SSV6200_ID_TX_THRESHOLD -+#undef SSV6200_ID_RX_THRESHOLD -+#undef SSV6200_PAGE_TX_THRESHOLD -+#undef SSV6200_PAGE_RX_THRESHOLD -+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER -+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER -+#define SSV6200_ID_TX_THRESHOLD 31 -+#define SSV6200_ID_RX_THRESHOLD 31 -+#define SSV6200_PAGE_TX_THRESHOLD 61 -+#define SSV6200_PAGE_RX_THRESHOLD 61 -+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45 -+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2 -+#endif -+#define SSV6200_ID_NUMBER (128) -+#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F) -+#define SSV6200_ID_AC_RESERVED 1 -+#define SSV6200_ID_AC_BK_OUT_QUEUE 8 -+#define SSV6200_ID_AC_BE_OUT_QUEUE 15 -+#define SSV6200_ID_AC_VI_OUT_QUEUE 16 -+#define SSV6200_ID_AC_VO_OUT_QUEUE 16 -+#define SSV6200_ID_MANAGER_QUEUE 8 -+#define HW_MMU_PAGE_SHIFT 0x8 -+#define HW_MMU_PAGE_MASK 0xff -+#define SSV6200_BT_PRI_SMP_TIME 0 -+#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0) -+#define SSV6200_WLAN_REMAIN_TIME 0 -+#define BT_2WIRE_EN_MSK 0x00000400 -+struct txResourceControl { -+ u32 txUsePage:8; -+ u32 txUseID:6; -+ u32 edca0:4; -+ u32 edca1:4; -+ u32 edca2:5; -+ u32 edca3:5; -+}; -+#include -+#endif -diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_aux.h b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h -@@ -0,0 +1,18221 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#define MCU_ENABLE_MSK 0x00000001 -+#define MCU_ENABLE_I_MSK 0xfffffffe -+#define MCU_ENABLE_SFT 0 -+#define MCU_ENABLE_HI 0 -+#define MCU_ENABLE_SZ 1 -+#define MAC_SW_RST_MSK 0x00000002 -+#define MAC_SW_RST_I_MSK 0xfffffffd -+#define MAC_SW_RST_SFT 1 -+#define MAC_SW_RST_HI 1 -+#define MAC_SW_RST_SZ 1 -+#define MCU_SW_RST_MSK 0x00000004 -+#define MCU_SW_RST_I_MSK 0xfffffffb -+#define MCU_SW_RST_SFT 2 -+#define MCU_SW_RST_HI 2 -+#define MCU_SW_RST_SZ 1 -+#define SDIO_SW_RST_MSK 0x00000008 -+#define SDIO_SW_RST_I_MSK 0xfffffff7 -+#define SDIO_SW_RST_SFT 3 -+#define SDIO_SW_RST_HI 3 -+#define SDIO_SW_RST_SZ 1 -+#define SPI_SLV_SW_RST_MSK 0x00000010 -+#define SPI_SLV_SW_RST_I_MSK 0xffffffef -+#define SPI_SLV_SW_RST_SFT 4 -+#define SPI_SLV_SW_RST_HI 4 -+#define SPI_SLV_SW_RST_SZ 1 -+#define UART_SW_RST_MSK 0x00000020 -+#define UART_SW_RST_I_MSK 0xffffffdf -+#define UART_SW_RST_SFT 5 -+#define UART_SW_RST_HI 5 -+#define UART_SW_RST_SZ 1 -+#define DMA_SW_RST_MSK 0x00000040 -+#define DMA_SW_RST_I_MSK 0xffffffbf -+#define DMA_SW_RST_SFT 6 -+#define DMA_SW_RST_HI 6 -+#define DMA_SW_RST_SZ 1 -+#define WDT_SW_RST_MSK 0x00000080 -+#define WDT_SW_RST_I_MSK 0xffffff7f -+#define WDT_SW_RST_SFT 7 -+#define WDT_SW_RST_HI 7 -+#define WDT_SW_RST_SZ 1 -+#define I2C_SLV_SW_RST_MSK 0x00000100 -+#define I2C_SLV_SW_RST_I_MSK 0xfffffeff -+#define I2C_SLV_SW_RST_SFT 8 -+#define I2C_SLV_SW_RST_HI 8 -+#define I2C_SLV_SW_RST_SZ 1 -+#define INT_CTL_SW_RST_MSK 0x00000200 -+#define INT_CTL_SW_RST_I_MSK 0xfffffdff -+#define INT_CTL_SW_RST_SFT 9 -+#define INT_CTL_SW_RST_HI 9 -+#define INT_CTL_SW_RST_SZ 1 -+#define BTCX_SW_RST_MSK 0x00000400 -+#define BTCX_SW_RST_I_MSK 0xfffffbff -+#define BTCX_SW_RST_SFT 10 -+#define BTCX_SW_RST_HI 10 -+#define BTCX_SW_RST_SZ 1 -+#define GPIO_SW_RST_MSK 0x00000800 -+#define GPIO_SW_RST_I_MSK 0xfffff7ff -+#define GPIO_SW_RST_SFT 11 -+#define GPIO_SW_RST_HI 11 -+#define GPIO_SW_RST_SZ 1 -+#define US0TMR_SW_RST_MSK 0x00001000 -+#define US0TMR_SW_RST_I_MSK 0xffffefff -+#define US0TMR_SW_RST_SFT 12 -+#define US0TMR_SW_RST_HI 12 -+#define US0TMR_SW_RST_SZ 1 -+#define US1TMR_SW_RST_MSK 0x00002000 -+#define US1TMR_SW_RST_I_MSK 0xffffdfff -+#define US1TMR_SW_RST_SFT 13 -+#define US1TMR_SW_RST_HI 13 -+#define US1TMR_SW_RST_SZ 1 -+#define US2TMR_SW_RST_MSK 0x00004000 -+#define US2TMR_SW_RST_I_MSK 0xffffbfff -+#define US2TMR_SW_RST_SFT 14 -+#define US2TMR_SW_RST_HI 14 -+#define US2TMR_SW_RST_SZ 1 -+#define US3TMR_SW_RST_MSK 0x00008000 -+#define US3TMR_SW_RST_I_MSK 0xffff7fff -+#define US3TMR_SW_RST_SFT 15 -+#define US3TMR_SW_RST_HI 15 -+#define US3TMR_SW_RST_SZ 1 -+#define MS0TMR_SW_RST_MSK 0x00010000 -+#define MS0TMR_SW_RST_I_MSK 0xfffeffff -+#define MS0TMR_SW_RST_SFT 16 -+#define MS0TMR_SW_RST_HI 16 -+#define MS0TMR_SW_RST_SZ 1 -+#define MS1TMR_SW_RST_MSK 0x00020000 -+#define MS1TMR_SW_RST_I_MSK 0xfffdffff -+#define MS1TMR_SW_RST_SFT 17 -+#define MS1TMR_SW_RST_HI 17 -+#define MS1TMR_SW_RST_SZ 1 -+#define MS2TMR_SW_RST_MSK 0x00040000 -+#define MS2TMR_SW_RST_I_MSK 0xfffbffff -+#define MS2TMR_SW_RST_SFT 18 -+#define MS2TMR_SW_RST_HI 18 -+#define MS2TMR_SW_RST_SZ 1 -+#define MS3TMR_SW_RST_MSK 0x00080000 -+#define MS3TMR_SW_RST_I_MSK 0xfff7ffff -+#define MS3TMR_SW_RST_SFT 19 -+#define MS3TMR_SW_RST_HI 19 -+#define MS3TMR_SW_RST_SZ 1 -+#define RF_BB_SW_RST_MSK 0x00100000 -+#define RF_BB_SW_RST_I_MSK 0xffefffff -+#define RF_BB_SW_RST_SFT 20 -+#define RF_BB_SW_RST_HI 20 -+#define RF_BB_SW_RST_SZ 1 -+#define SYS_ALL_RST_MSK 0x00200000 -+#define SYS_ALL_RST_I_MSK 0xffdfffff -+#define SYS_ALL_RST_SFT 21 -+#define SYS_ALL_RST_HI 21 -+#define SYS_ALL_RST_SZ 1 -+#define DAT_UART_SW_RST_MSK 0x00400000 -+#define DAT_UART_SW_RST_I_MSK 0xffbfffff -+#define DAT_UART_SW_RST_SFT 22 -+#define DAT_UART_SW_RST_HI 22 -+#define DAT_UART_SW_RST_SZ 1 -+#define I2C_MST_SW_RST_MSK 0x00800000 -+#define I2C_MST_SW_RST_I_MSK 0xff7fffff -+#define I2C_MST_SW_RST_SFT 23 -+#define I2C_MST_SW_RST_HI 23 -+#define I2C_MST_SW_RST_SZ 1 -+#define RG_REBOOT_MSK 0x00000001 -+#define RG_REBOOT_I_MSK 0xfffffffe -+#define RG_REBOOT_SFT 0 -+#define RG_REBOOT_HI 0 -+#define RG_REBOOT_SZ 1 -+#define TRAP_IMG_FLS_MSK 0x00010000 -+#define TRAP_IMG_FLS_I_MSK 0xfffeffff -+#define TRAP_IMG_FLS_SFT 16 -+#define TRAP_IMG_FLS_HI 16 -+#define TRAP_IMG_FLS_SZ 1 -+#define TRAP_REBOOT_MSK 0x00020000 -+#define TRAP_REBOOT_I_MSK 0xfffdffff -+#define TRAP_REBOOT_SFT 17 -+#define TRAP_REBOOT_HI 17 -+#define TRAP_REBOOT_SZ 1 -+#define TRAP_BOOT_FLS_MSK 0x00040000 -+#define TRAP_BOOT_FLS_I_MSK 0xfffbffff -+#define TRAP_BOOT_FLS_SFT 18 -+#define TRAP_BOOT_FLS_HI 18 -+#define TRAP_BOOT_FLS_SZ 1 -+#define CHIP_ID_31_0_MSK 0xffffffff -+#define CHIP_ID_31_0_I_MSK 0x00000000 -+#define CHIP_ID_31_0_SFT 0 -+#define CHIP_ID_31_0_HI 31 -+#define CHIP_ID_31_0_SZ 32 -+#define CHIP_ID_63_32_MSK 0xffffffff -+#define CHIP_ID_63_32_I_MSK 0x00000000 -+#define CHIP_ID_63_32_SFT 0 -+#define CHIP_ID_63_32_HI 31 -+#define CHIP_ID_63_32_SZ 32 -+#define CHIP_ID_95_64_MSK 0xffffffff -+#define CHIP_ID_95_64_I_MSK 0x00000000 -+#define CHIP_ID_95_64_SFT 0 -+#define CHIP_ID_95_64_HI 31 -+#define CHIP_ID_95_64_SZ 32 -+#define CHIP_ID_127_96_MSK 0xffffffff -+#define CHIP_ID_127_96_I_MSK 0x00000000 -+#define CHIP_ID_127_96_SFT 0 -+#define CHIP_ID_127_96_HI 31 -+#define CHIP_ID_127_96_SZ 32 -+#define CK_SEL_1_0_MSK 0x00000003 -+#define CK_SEL_1_0_I_MSK 0xfffffffc -+#define CK_SEL_1_0_SFT 0 -+#define CK_SEL_1_0_HI 1 -+#define CK_SEL_1_0_SZ 2 -+#define CK_SEL_2_MSK 0x00000004 -+#define CK_SEL_2_I_MSK 0xfffffffb -+#define CK_SEL_2_SFT 2 -+#define CK_SEL_2_HI 2 -+#define CK_SEL_2_SZ 1 -+#define SYS_CLK_EN_MSK 0x00000001 -+#define SYS_CLK_EN_I_MSK 0xfffffffe -+#define SYS_CLK_EN_SFT 0 -+#define SYS_CLK_EN_HI 0 -+#define SYS_CLK_EN_SZ 1 -+#define MAC_CLK_EN_MSK 0x00000002 -+#define MAC_CLK_EN_I_MSK 0xfffffffd -+#define MAC_CLK_EN_SFT 1 -+#define MAC_CLK_EN_HI 1 -+#define MAC_CLK_EN_SZ 1 -+#define MCU_CLK_EN_MSK 0x00000004 -+#define MCU_CLK_EN_I_MSK 0xfffffffb -+#define MCU_CLK_EN_SFT 2 -+#define MCU_CLK_EN_HI 2 -+#define MCU_CLK_EN_SZ 1 -+#define SDIO_CLK_EN_MSK 0x00000008 -+#define SDIO_CLK_EN_I_MSK 0xfffffff7 -+#define SDIO_CLK_EN_SFT 3 -+#define SDIO_CLK_EN_HI 3 -+#define SDIO_CLK_EN_SZ 1 -+#define SPI_SLV_CLK_EN_MSK 0x00000010 -+#define SPI_SLV_CLK_EN_I_MSK 0xffffffef -+#define SPI_SLV_CLK_EN_SFT 4 -+#define SPI_SLV_CLK_EN_HI 4 -+#define SPI_SLV_CLK_EN_SZ 1 -+#define UART_CLK_EN_MSK 0x00000020 -+#define UART_CLK_EN_I_MSK 0xffffffdf -+#define UART_CLK_EN_SFT 5 -+#define UART_CLK_EN_HI 5 -+#define UART_CLK_EN_SZ 1 -+#define DMA_CLK_EN_MSK 0x00000040 -+#define DMA_CLK_EN_I_MSK 0xffffffbf -+#define DMA_CLK_EN_SFT 6 -+#define DMA_CLK_EN_HI 6 -+#define DMA_CLK_EN_SZ 1 -+#define WDT_CLK_EN_MSK 0x00000080 -+#define WDT_CLK_EN_I_MSK 0xffffff7f -+#define WDT_CLK_EN_SFT 7 -+#define WDT_CLK_EN_HI 7 -+#define WDT_CLK_EN_SZ 1 -+#define I2C_SLV_CLK_EN_MSK 0x00000100 -+#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff -+#define I2C_SLV_CLK_EN_SFT 8 -+#define I2C_SLV_CLK_EN_HI 8 -+#define I2C_SLV_CLK_EN_SZ 1 -+#define INT_CTL_CLK_EN_MSK 0x00000200 -+#define INT_CTL_CLK_EN_I_MSK 0xfffffdff -+#define INT_CTL_CLK_EN_SFT 9 -+#define INT_CTL_CLK_EN_HI 9 -+#define INT_CTL_CLK_EN_SZ 1 -+#define BTCX_CLK_EN_MSK 0x00000400 -+#define BTCX_CLK_EN_I_MSK 0xfffffbff -+#define BTCX_CLK_EN_SFT 10 -+#define BTCX_CLK_EN_HI 10 -+#define BTCX_CLK_EN_SZ 1 -+#define GPIO_CLK_EN_MSK 0x00000800 -+#define GPIO_CLK_EN_I_MSK 0xfffff7ff -+#define GPIO_CLK_EN_SFT 11 -+#define GPIO_CLK_EN_HI 11 -+#define GPIO_CLK_EN_SZ 1 -+#define US0TMR_CLK_EN_MSK 0x00001000 -+#define US0TMR_CLK_EN_I_MSK 0xffffefff -+#define US0TMR_CLK_EN_SFT 12 -+#define US0TMR_CLK_EN_HI 12 -+#define US0TMR_CLK_EN_SZ 1 -+#define US1TMR_CLK_EN_MSK 0x00002000 -+#define US1TMR_CLK_EN_I_MSK 0xffffdfff -+#define US1TMR_CLK_EN_SFT 13 -+#define US1TMR_CLK_EN_HI 13 -+#define US1TMR_CLK_EN_SZ 1 -+#define US2TMR_CLK_EN_MSK 0x00004000 -+#define US2TMR_CLK_EN_I_MSK 0xffffbfff -+#define US2TMR_CLK_EN_SFT 14 -+#define US2TMR_CLK_EN_HI 14 -+#define US2TMR_CLK_EN_SZ 1 -+#define US3TMR_CLK_EN_MSK 0x00008000 -+#define US3TMR_CLK_EN_I_MSK 0xffff7fff -+#define US3TMR_CLK_EN_SFT 15 -+#define US3TMR_CLK_EN_HI 15 -+#define US3TMR_CLK_EN_SZ 1 -+#define MS0TMR_CLK_EN_MSK 0x00010000 -+#define MS0TMR_CLK_EN_I_MSK 0xfffeffff -+#define MS0TMR_CLK_EN_SFT 16 -+#define MS0TMR_CLK_EN_HI 16 -+#define MS0TMR_CLK_EN_SZ 1 -+#define MS1TMR_CLK_EN_MSK 0x00020000 -+#define MS1TMR_CLK_EN_I_MSK 0xfffdffff -+#define MS1TMR_CLK_EN_SFT 17 -+#define MS1TMR_CLK_EN_HI 17 -+#define MS1TMR_CLK_EN_SZ 1 -+#define MS2TMR_CLK_EN_MSK 0x00040000 -+#define MS2TMR_CLK_EN_I_MSK 0xfffbffff -+#define MS2TMR_CLK_EN_SFT 18 -+#define MS2TMR_CLK_EN_HI 18 -+#define MS2TMR_CLK_EN_SZ 1 -+#define MS3TMR_CLK_EN_MSK 0x00080000 -+#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff -+#define MS3TMR_CLK_EN_SFT 19 -+#define MS3TMR_CLK_EN_HI 19 -+#define MS3TMR_CLK_EN_SZ 1 -+#define BIST_CLK_EN_MSK 0x00100000 -+#define BIST_CLK_EN_I_MSK 0xffefffff -+#define BIST_CLK_EN_SFT 20 -+#define BIST_CLK_EN_HI 20 -+#define BIST_CLK_EN_SZ 1 -+#define I2C_MST_CLK_EN_MSK 0x00800000 -+#define I2C_MST_CLK_EN_I_MSK 0xff7fffff -+#define I2C_MST_CLK_EN_SFT 23 -+#define I2C_MST_CLK_EN_HI 23 -+#define I2C_MST_CLK_EN_SZ 1 -+#define BTCX_CSR_CLK_EN_MSK 0x00000400 -+#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff -+#define BTCX_CSR_CLK_EN_SFT 10 -+#define BTCX_CSR_CLK_EN_HI 10 -+#define BTCX_CSR_CLK_EN_SZ 1 -+#define MCU_DBG_SEL_MSK 0x0000003f -+#define MCU_DBG_SEL_I_MSK 0xffffffc0 -+#define MCU_DBG_SEL_SFT 0 -+#define MCU_DBG_SEL_HI 5 -+#define MCU_DBG_SEL_SZ 6 -+#define MCU_STOP_NOGRANT_MSK 0x00000100 -+#define MCU_STOP_NOGRANT_I_MSK 0xfffffeff -+#define MCU_STOP_NOGRANT_SFT 8 -+#define MCU_STOP_NOGRANT_HI 8 -+#define MCU_STOP_NOGRANT_SZ 1 -+#define MCU_STOP_ANYTIME_MSK 0x00000200 -+#define MCU_STOP_ANYTIME_I_MSK 0xfffffdff -+#define MCU_STOP_ANYTIME_SFT 9 -+#define MCU_STOP_ANYTIME_HI 9 -+#define MCU_STOP_ANYTIME_SZ 1 -+#define MCU_DBG_DATA_MSK 0xffffffff -+#define MCU_DBG_DATA_I_MSK 0x00000000 -+#define MCU_DBG_DATA_SFT 0 -+#define MCU_DBG_DATA_HI 31 -+#define MCU_DBG_DATA_SZ 32 -+#define AHB_SW_RST_MSK 0x00000001 -+#define AHB_SW_RST_I_MSK 0xfffffffe -+#define AHB_SW_RST_SFT 0 -+#define AHB_SW_RST_HI 0 -+#define AHB_SW_RST_SZ 1 -+#define AHB_ERR_RST_MSK 0x00000002 -+#define AHB_ERR_RST_I_MSK 0xfffffffd -+#define AHB_ERR_RST_SFT 1 -+#define AHB_ERR_RST_HI 1 -+#define AHB_ERR_RST_SZ 1 -+#define REG_AHB_DEBUG_MX_MSK 0x00000030 -+#define REG_AHB_DEBUG_MX_I_MSK 0xffffffcf -+#define REG_AHB_DEBUG_MX_SFT 4 -+#define REG_AHB_DEBUG_MX_HI 5 -+#define REG_AHB_DEBUG_MX_SZ 2 -+#define REG_PKT_W_NBRT_MSK 0x00000100 -+#define REG_PKT_W_NBRT_I_MSK 0xfffffeff -+#define REG_PKT_W_NBRT_SFT 8 -+#define REG_PKT_W_NBRT_HI 8 -+#define REG_PKT_W_NBRT_SZ 1 -+#define REG_PKT_R_NBRT_MSK 0x00000200 -+#define REG_PKT_R_NBRT_I_MSK 0xfffffdff -+#define REG_PKT_R_NBRT_SFT 9 -+#define REG_PKT_R_NBRT_HI 9 -+#define REG_PKT_R_NBRT_SZ 1 -+#define IQ_SRAM_SEL_0_MSK 0x00001000 -+#define IQ_SRAM_SEL_0_I_MSK 0xffffefff -+#define IQ_SRAM_SEL_0_SFT 12 -+#define IQ_SRAM_SEL_0_HI 12 -+#define IQ_SRAM_SEL_0_SZ 1 -+#define IQ_SRAM_SEL_1_MSK 0x00002000 -+#define IQ_SRAM_SEL_1_I_MSK 0xffffdfff -+#define IQ_SRAM_SEL_1_SFT 13 -+#define IQ_SRAM_SEL_1_HI 13 -+#define IQ_SRAM_SEL_1_SZ 1 -+#define IQ_SRAM_SEL_2_MSK 0x00004000 -+#define IQ_SRAM_SEL_2_I_MSK 0xffffbfff -+#define IQ_SRAM_SEL_2_SFT 14 -+#define IQ_SRAM_SEL_2_HI 14 -+#define IQ_SRAM_SEL_2_SZ 1 -+#define AHB_STATUS_MSK 0xffff0000 -+#define AHB_STATUS_I_MSK 0x0000ffff -+#define AHB_STATUS_SFT 16 -+#define AHB_STATUS_HI 31 -+#define AHB_STATUS_SZ 16 -+#define PARALLEL_DR_MSK 0x00000001 -+#define PARALLEL_DR_I_MSK 0xfffffffe -+#define PARALLEL_DR_SFT 0 -+#define PARALLEL_DR_HI 0 -+#define PARALLEL_DR_SZ 1 -+#define MBRUN_MSK 0x00000010 -+#define MBRUN_I_MSK 0xffffffef -+#define MBRUN_SFT 4 -+#define MBRUN_HI 4 -+#define MBRUN_SZ 1 -+#define SHIFT_DR_MSK 0x00000100 -+#define SHIFT_DR_I_MSK 0xfffffeff -+#define SHIFT_DR_SFT 8 -+#define SHIFT_DR_HI 8 -+#define SHIFT_DR_SZ 1 -+#define MODE_REG_SI_MSK 0x00000200 -+#define MODE_REG_SI_I_MSK 0xfffffdff -+#define MODE_REG_SI_SFT 9 -+#define MODE_REG_SI_HI 9 -+#define MODE_REG_SI_SZ 1 -+#define SIMULATION_MODE_MSK 0x00000400 -+#define SIMULATION_MODE_I_MSK 0xfffffbff -+#define SIMULATION_MODE_SFT 10 -+#define SIMULATION_MODE_HI 10 -+#define SIMULATION_MODE_SZ 1 -+#define DBIST_MODE_MSK 0x00000800 -+#define DBIST_MODE_I_MSK 0xfffff7ff -+#define DBIST_MODE_SFT 11 -+#define DBIST_MODE_HI 11 -+#define DBIST_MODE_SZ 1 -+#define MODE_REG_IN_MSK 0x001fffff -+#define MODE_REG_IN_I_MSK 0xffe00000 -+#define MODE_REG_IN_SFT 0 -+#define MODE_REG_IN_HI 20 -+#define MODE_REG_IN_SZ 21 -+#define MODE_REG_OUT_MCU_MSK 0x001fffff -+#define MODE_REG_OUT_MCU_I_MSK 0xffe00000 -+#define MODE_REG_OUT_MCU_SFT 0 -+#define MODE_REG_OUT_MCU_HI 20 -+#define MODE_REG_OUT_MCU_SZ 21 -+#define MODE_REG_SO_MCU_MSK 0x80000000 -+#define MODE_REG_SO_MCU_I_MSK 0x7fffffff -+#define MODE_REG_SO_MCU_SFT 31 -+#define MODE_REG_SO_MCU_HI 31 -+#define MODE_REG_SO_MCU_SZ 1 -+#define MONITOR_BUS_MCU_31_0_MSK 0xffffffff -+#define MONITOR_BUS_MCU_31_0_I_MSK 0x00000000 -+#define MONITOR_BUS_MCU_31_0_SFT 0 -+#define MONITOR_BUS_MCU_31_0_HI 31 -+#define MONITOR_BUS_MCU_31_0_SZ 32 -+#define MONITOR_BUS_MCU_33_32_MSK 0x00000003 -+#define MONITOR_BUS_MCU_33_32_I_MSK 0xfffffffc -+#define MONITOR_BUS_MCU_33_32_SFT 0 -+#define MONITOR_BUS_MCU_33_32_HI 1 -+#define MONITOR_BUS_MCU_33_32_SZ 2 -+#define TB_ADR_SEL_MSK 0x0000ffff -+#define TB_ADR_SEL_I_MSK 0xffff0000 -+#define TB_ADR_SEL_SFT 0 -+#define TB_ADR_SEL_HI 15 -+#define TB_ADR_SEL_SZ 16 -+#define TB_CS_MSK 0x80000000 -+#define TB_CS_I_MSK 0x7fffffff -+#define TB_CS_SFT 31 -+#define TB_CS_HI 31 -+#define TB_CS_SZ 1 -+#define TB_RDATA_MSK 0xffffffff -+#define TB_RDATA_I_MSK 0x00000000 -+#define TB_RDATA_SFT 0 -+#define TB_RDATA_HI 31 -+#define TB_RDATA_SZ 32 -+#define UART_W2B_EN_MSK 0x00000001 -+#define UART_W2B_EN_I_MSK 0xfffffffe -+#define UART_W2B_EN_SFT 0 -+#define UART_W2B_EN_HI 0 -+#define UART_W2B_EN_SZ 1 -+#define DATA_UART_W2B_EN_MSK 0x00000010 -+#define DATA_UART_W2B_EN_I_MSK 0xffffffef -+#define DATA_UART_W2B_EN_SFT 4 -+#define DATA_UART_W2B_EN_HI 4 -+#define DATA_UART_W2B_EN_SZ 1 -+#define AHB_ILL_ADDR_MSK 0xffffffff -+#define AHB_ILL_ADDR_I_MSK 0x00000000 -+#define AHB_ILL_ADDR_SFT 0 -+#define AHB_ILL_ADDR_HI 31 -+#define AHB_ILL_ADDR_SZ 32 -+#define AHB_FEN_ADDR_MSK 0xffffffff -+#define AHB_FEN_ADDR_I_MSK 0x00000000 -+#define AHB_FEN_ADDR_SFT 0 -+#define AHB_FEN_ADDR_HI 31 -+#define AHB_FEN_ADDR_SZ 32 -+#define ILL_ADDR_CLR_MSK 0x00000001 -+#define ILL_ADDR_CLR_I_MSK 0xfffffffe -+#define ILL_ADDR_CLR_SFT 0 -+#define ILL_ADDR_CLR_HI 0 -+#define ILL_ADDR_CLR_SZ 1 -+#define FENCE_HIT_CLR_MSK 0x00000002 -+#define FENCE_HIT_CLR_I_MSK 0xfffffffd -+#define FENCE_HIT_CLR_SFT 1 -+#define FENCE_HIT_CLR_HI 1 -+#define FENCE_HIT_CLR_SZ 1 -+#define ILL_ADDR_INT_MSK 0x00000010 -+#define ILL_ADDR_INT_I_MSK 0xffffffef -+#define ILL_ADDR_INT_SFT 4 -+#define ILL_ADDR_INT_HI 4 -+#define ILL_ADDR_INT_SZ 1 -+#define FENCE_HIT_INT_MSK 0x00000020 -+#define FENCE_HIT_INT_I_MSK 0xffffffdf -+#define FENCE_HIT_INT_SFT 5 -+#define FENCE_HIT_INT_HI 5 -+#define FENCE_HIT_INT_SZ 1 -+#define PWM_INI_VALUE_P_A_MSK 0x000000ff -+#define PWM_INI_VALUE_P_A_I_MSK 0xffffff00 -+#define PWM_INI_VALUE_P_A_SFT 0 -+#define PWM_INI_VALUE_P_A_HI 7 -+#define PWM_INI_VALUE_P_A_SZ 8 -+#define PWM_INI_VALUE_N_A_MSK 0x0000ff00 -+#define PWM_INI_VALUE_N_A_I_MSK 0xffff00ff -+#define PWM_INI_VALUE_N_A_SFT 8 -+#define PWM_INI_VALUE_N_A_HI 15 -+#define PWM_INI_VALUE_N_A_SZ 8 -+#define PWM_POST_SCALER_A_MSK 0x000f0000 -+#define PWM_POST_SCALER_A_I_MSK 0xfff0ffff -+#define PWM_POST_SCALER_A_SFT 16 -+#define PWM_POST_SCALER_A_HI 19 -+#define PWM_POST_SCALER_A_SZ 4 -+#define PWM_ALWAYSON_A_MSK 0x20000000 -+#define PWM_ALWAYSON_A_I_MSK 0xdfffffff -+#define PWM_ALWAYSON_A_SFT 29 -+#define PWM_ALWAYSON_A_HI 29 -+#define PWM_ALWAYSON_A_SZ 1 -+#define PWM_INVERT_A_MSK 0x40000000 -+#define PWM_INVERT_A_I_MSK 0xbfffffff -+#define PWM_INVERT_A_SFT 30 -+#define PWM_INVERT_A_HI 30 -+#define PWM_INVERT_A_SZ 1 -+#define PWM_ENABLE_A_MSK 0x80000000 -+#define PWM_ENABLE_A_I_MSK 0x7fffffff -+#define PWM_ENABLE_A_SFT 31 -+#define PWM_ENABLE_A_HI 31 -+#define PWM_ENABLE_A_SZ 1 -+#define PWM_INI_VALUE_P_B_MSK 0x000000ff -+#define PWM_INI_VALUE_P_B_I_MSK 0xffffff00 -+#define PWM_INI_VALUE_P_B_SFT 0 -+#define PWM_INI_VALUE_P_B_HI 7 -+#define PWM_INI_VALUE_P_B_SZ 8 -+#define PWM_INI_VALUE_N_B_MSK 0x0000ff00 -+#define PWM_INI_VALUE_N_B_I_MSK 0xffff00ff -+#define PWM_INI_VALUE_N_B_SFT 8 -+#define PWM_INI_VALUE_N_B_HI 15 -+#define PWM_INI_VALUE_N_B_SZ 8 -+#define PWM_POST_SCALER_B_MSK 0x000f0000 -+#define PWM_POST_SCALER_B_I_MSK 0xfff0ffff -+#define PWM_POST_SCALER_B_SFT 16 -+#define PWM_POST_SCALER_B_HI 19 -+#define PWM_POST_SCALER_B_SZ 4 -+#define PWM_ALWAYSON_B_MSK 0x20000000 -+#define PWM_ALWAYSON_B_I_MSK 0xdfffffff -+#define PWM_ALWAYSON_B_SFT 29 -+#define PWM_ALWAYSON_B_HI 29 -+#define PWM_ALWAYSON_B_SZ 1 -+#define PWM_INVERT_B_MSK 0x40000000 -+#define PWM_INVERT_B_I_MSK 0xbfffffff -+#define PWM_INVERT_B_SFT 30 -+#define PWM_INVERT_B_HI 30 -+#define PWM_INVERT_B_SZ 1 -+#define PWM_ENABLE_B_MSK 0x80000000 -+#define PWM_ENABLE_B_I_MSK 0x7fffffff -+#define PWM_ENABLE_B_SFT 31 -+#define PWM_ENABLE_B_HI 31 -+#define PWM_ENABLE_B_SZ 1 -+#define HBUSREQ_LOCK_MSK 0x00001fff -+#define HBUSREQ_LOCK_I_MSK 0xffffe000 -+#define HBUSREQ_LOCK_SFT 0 -+#define HBUSREQ_LOCK_HI 12 -+#define HBUSREQ_LOCK_SZ 13 -+#define HBURST_LOCK_MSK 0x00001fff -+#define HBURST_LOCK_I_MSK 0xffffe000 -+#define HBURST_LOCK_SFT 0 -+#define HBURST_LOCK_HI 12 -+#define HBURST_LOCK_SZ 13 -+#define PRESCALER_USTIMER_MSK 0x000001ff -+#define PRESCALER_USTIMER_I_MSK 0xfffffe00 -+#define PRESCALER_USTIMER_SFT 0 -+#define PRESCALER_USTIMER_HI 8 -+#define PRESCALER_USTIMER_SZ 9 -+#define MODE_REG_IN_MMU_MSK 0x0000ffff -+#define MODE_REG_IN_MMU_I_MSK 0xffff0000 -+#define MODE_REG_IN_MMU_SFT 0 -+#define MODE_REG_IN_MMU_HI 15 -+#define MODE_REG_IN_MMU_SZ 16 -+#define MODE_REG_OUT_MMU_MSK 0x0000ffff -+#define MODE_REG_OUT_MMU_I_MSK 0xffff0000 -+#define MODE_REG_OUT_MMU_SFT 0 -+#define MODE_REG_OUT_MMU_HI 15 -+#define MODE_REG_OUT_MMU_SZ 16 -+#define MODE_REG_SO_MMU_MSK 0x80000000 -+#define MODE_REG_SO_MMU_I_MSK 0x7fffffff -+#define MODE_REG_SO_MMU_SFT 31 -+#define MODE_REG_SO_MMU_HI 31 -+#define MODE_REG_SO_MMU_SZ 1 -+#define MONITOR_BUS_MMU_MSK 0x0007ffff -+#define MONITOR_BUS_MMU_I_MSK 0xfff80000 -+#define MONITOR_BUS_MMU_SFT 0 -+#define MONITOR_BUS_MMU_HI 18 -+#define MONITOR_BUS_MMU_SZ 19 -+#define TEST_MODE0_MSK 0x00000001 -+#define TEST_MODE0_I_MSK 0xfffffffe -+#define TEST_MODE0_SFT 0 -+#define TEST_MODE0_HI 0 -+#define TEST_MODE0_SZ 1 -+#define TEST_MODE1_MSK 0x00000002 -+#define TEST_MODE1_I_MSK 0xfffffffd -+#define TEST_MODE1_SFT 1 -+#define TEST_MODE1_HI 1 -+#define TEST_MODE1_SZ 1 -+#define TEST_MODE2_MSK 0x00000004 -+#define TEST_MODE2_I_MSK 0xfffffffb -+#define TEST_MODE2_SFT 2 -+#define TEST_MODE2_HI 2 -+#define TEST_MODE2_SZ 1 -+#define TEST_MODE3_MSK 0x00000008 -+#define TEST_MODE3_I_MSK 0xfffffff7 -+#define TEST_MODE3_SFT 3 -+#define TEST_MODE3_HI 3 -+#define TEST_MODE3_SZ 1 -+#define TEST_MODE4_MSK 0x00000010 -+#define TEST_MODE4_I_MSK 0xffffffef -+#define TEST_MODE4_SFT 4 -+#define TEST_MODE4_HI 4 -+#define TEST_MODE4_SZ 1 -+#define TEST_MODE_ALL_MSK 0x00000020 -+#define TEST_MODE_ALL_I_MSK 0xffffffdf -+#define TEST_MODE_ALL_SFT 5 -+#define TEST_MODE_ALL_HI 5 -+#define TEST_MODE_ALL_SZ 1 -+#define WDT_INIT_MSK 0x00000001 -+#define WDT_INIT_I_MSK 0xfffffffe -+#define WDT_INIT_SFT 0 -+#define WDT_INIT_HI 0 -+#define WDT_INIT_SZ 1 -+#define SD_HOST_INIT_MSK 0x00000002 -+#define SD_HOST_INIT_I_MSK 0xfffffffd -+#define SD_HOST_INIT_SFT 1 -+#define SD_HOST_INIT_HI 1 -+#define SD_HOST_INIT_SZ 1 -+#define ALLOW_SD_RESET_MSK 0x00000001 -+#define ALLOW_SD_RESET_I_MSK 0xfffffffe -+#define ALLOW_SD_RESET_SFT 0 -+#define ALLOW_SD_RESET_HI 0 -+#define ALLOW_SD_RESET_SZ 1 -+#define UART_NRTS_MSK 0x00000001 -+#define UART_NRTS_I_MSK 0xfffffffe -+#define UART_NRTS_SFT 0 -+#define UART_NRTS_HI 0 -+#define UART_NRTS_SZ 1 -+#define UART_NCTS_MSK 0x00000002 -+#define UART_NCTS_I_MSK 0xfffffffd -+#define UART_NCTS_SFT 1 -+#define UART_NCTS_HI 1 -+#define UART_NCTS_SZ 1 -+#define TU0_TM_INIT_VALUE_MSK 0x0000ffff -+#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000 -+#define TU0_TM_INIT_VALUE_SFT 0 -+#define TU0_TM_INIT_VALUE_HI 15 -+#define TU0_TM_INIT_VALUE_SZ 16 -+#define TU0_TM_MODE_MSK 0x00010000 -+#define TU0_TM_MODE_I_MSK 0xfffeffff -+#define TU0_TM_MODE_SFT 16 -+#define TU0_TM_MODE_HI 16 -+#define TU0_TM_MODE_SZ 1 -+#define TU0_TM_INT_STS_DONE_MSK 0x00020000 -+#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff -+#define TU0_TM_INT_STS_DONE_SFT 17 -+#define TU0_TM_INT_STS_DONE_HI 17 -+#define TU0_TM_INT_STS_DONE_SZ 1 -+#define TU0_TM_INT_MASK_MSK 0x00040000 -+#define TU0_TM_INT_MASK_I_MSK 0xfffbffff -+#define TU0_TM_INT_MASK_SFT 18 -+#define TU0_TM_INT_MASK_HI 18 -+#define TU0_TM_INT_MASK_SZ 1 -+#define TU0_TM_CUR_VALUE_MSK 0x0000ffff -+#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000 -+#define TU0_TM_CUR_VALUE_SFT 0 -+#define TU0_TM_CUR_VALUE_HI 15 -+#define TU0_TM_CUR_VALUE_SZ 16 -+#define TU1_TM_INIT_VALUE_MSK 0x0000ffff -+#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000 -+#define TU1_TM_INIT_VALUE_SFT 0 -+#define TU1_TM_INIT_VALUE_HI 15 -+#define TU1_TM_INIT_VALUE_SZ 16 -+#define TU1_TM_MODE_MSK 0x00010000 -+#define TU1_TM_MODE_I_MSK 0xfffeffff -+#define TU1_TM_MODE_SFT 16 -+#define TU1_TM_MODE_HI 16 -+#define TU1_TM_MODE_SZ 1 -+#define TU1_TM_INT_STS_DONE_MSK 0x00020000 -+#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff -+#define TU1_TM_INT_STS_DONE_SFT 17 -+#define TU1_TM_INT_STS_DONE_HI 17 -+#define TU1_TM_INT_STS_DONE_SZ 1 -+#define TU1_TM_INT_MASK_MSK 0x00040000 -+#define TU1_TM_INT_MASK_I_MSK 0xfffbffff -+#define TU1_TM_INT_MASK_SFT 18 -+#define TU1_TM_INT_MASK_HI 18 -+#define TU1_TM_INT_MASK_SZ 1 -+#define TU1_TM_CUR_VALUE_MSK 0x0000ffff -+#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000 -+#define TU1_TM_CUR_VALUE_SFT 0 -+#define TU1_TM_CUR_VALUE_HI 15 -+#define TU1_TM_CUR_VALUE_SZ 16 -+#define TU2_TM_INIT_VALUE_MSK 0x0000ffff -+#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000 -+#define TU2_TM_INIT_VALUE_SFT 0 -+#define TU2_TM_INIT_VALUE_HI 15 -+#define TU2_TM_INIT_VALUE_SZ 16 -+#define TU2_TM_MODE_MSK 0x00010000 -+#define TU2_TM_MODE_I_MSK 0xfffeffff -+#define TU2_TM_MODE_SFT 16 -+#define TU2_TM_MODE_HI 16 -+#define TU2_TM_MODE_SZ 1 -+#define TU2_TM_INT_STS_DONE_MSK 0x00020000 -+#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff -+#define TU2_TM_INT_STS_DONE_SFT 17 -+#define TU2_TM_INT_STS_DONE_HI 17 -+#define TU2_TM_INT_STS_DONE_SZ 1 -+#define TU2_TM_INT_MASK_MSK 0x00040000 -+#define TU2_TM_INT_MASK_I_MSK 0xfffbffff -+#define TU2_TM_INT_MASK_SFT 18 -+#define TU2_TM_INT_MASK_HI 18 -+#define TU2_TM_INT_MASK_SZ 1 -+#define TU2_TM_CUR_VALUE_MSK 0x0000ffff -+#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000 -+#define TU2_TM_CUR_VALUE_SFT 0 -+#define TU2_TM_CUR_VALUE_HI 15 -+#define TU2_TM_CUR_VALUE_SZ 16 -+#define TU3_TM_INIT_VALUE_MSK 0x0000ffff -+#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000 -+#define TU3_TM_INIT_VALUE_SFT 0 -+#define TU3_TM_INIT_VALUE_HI 15 -+#define TU3_TM_INIT_VALUE_SZ 16 -+#define TU3_TM_MODE_MSK 0x00010000 -+#define TU3_TM_MODE_I_MSK 0xfffeffff -+#define TU3_TM_MODE_SFT 16 -+#define TU3_TM_MODE_HI 16 -+#define TU3_TM_MODE_SZ 1 -+#define TU3_TM_INT_STS_DONE_MSK 0x00020000 -+#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff -+#define TU3_TM_INT_STS_DONE_SFT 17 -+#define TU3_TM_INT_STS_DONE_HI 17 -+#define TU3_TM_INT_STS_DONE_SZ 1 -+#define TU3_TM_INT_MASK_MSK 0x00040000 -+#define TU3_TM_INT_MASK_I_MSK 0xfffbffff -+#define TU3_TM_INT_MASK_SFT 18 -+#define TU3_TM_INT_MASK_HI 18 -+#define TU3_TM_INT_MASK_SZ 1 -+#define TU3_TM_CUR_VALUE_MSK 0x0000ffff -+#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000 -+#define TU3_TM_CUR_VALUE_SFT 0 -+#define TU3_TM_CUR_VALUE_HI 15 -+#define TU3_TM_CUR_VALUE_SZ 16 -+#define TM0_TM_INIT_VALUE_MSK 0x0000ffff -+#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000 -+#define TM0_TM_INIT_VALUE_SFT 0 -+#define TM0_TM_INIT_VALUE_HI 15 -+#define TM0_TM_INIT_VALUE_SZ 16 -+#define TM0_TM_MODE_MSK 0x00010000 -+#define TM0_TM_MODE_I_MSK 0xfffeffff -+#define TM0_TM_MODE_SFT 16 -+#define TM0_TM_MODE_HI 16 -+#define TM0_TM_MODE_SZ 1 -+#define TM0_TM_INT_STS_DONE_MSK 0x00020000 -+#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff -+#define TM0_TM_INT_STS_DONE_SFT 17 -+#define TM0_TM_INT_STS_DONE_HI 17 -+#define TM0_TM_INT_STS_DONE_SZ 1 -+#define TM0_TM_INT_MASK_MSK 0x00040000 -+#define TM0_TM_INT_MASK_I_MSK 0xfffbffff -+#define TM0_TM_INT_MASK_SFT 18 -+#define TM0_TM_INT_MASK_HI 18 -+#define TM0_TM_INT_MASK_SZ 1 -+#define TM0_TM_CUR_VALUE_MSK 0x0000ffff -+#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000 -+#define TM0_TM_CUR_VALUE_SFT 0 -+#define TM0_TM_CUR_VALUE_HI 15 -+#define TM0_TM_CUR_VALUE_SZ 16 -+#define TM1_TM_INIT_VALUE_MSK 0x0000ffff -+#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000 -+#define TM1_TM_INIT_VALUE_SFT 0 -+#define TM1_TM_INIT_VALUE_HI 15 -+#define TM1_TM_INIT_VALUE_SZ 16 -+#define TM1_TM_MODE_MSK 0x00010000 -+#define TM1_TM_MODE_I_MSK 0xfffeffff -+#define TM1_TM_MODE_SFT 16 -+#define TM1_TM_MODE_HI 16 -+#define TM1_TM_MODE_SZ 1 -+#define TM1_TM_INT_STS_DONE_MSK 0x00020000 -+#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff -+#define TM1_TM_INT_STS_DONE_SFT 17 -+#define TM1_TM_INT_STS_DONE_HI 17 -+#define TM1_TM_INT_STS_DONE_SZ 1 -+#define TM1_TM_INT_MASK_MSK 0x00040000 -+#define TM1_TM_INT_MASK_I_MSK 0xfffbffff -+#define TM1_TM_INT_MASK_SFT 18 -+#define TM1_TM_INT_MASK_HI 18 -+#define TM1_TM_INT_MASK_SZ 1 -+#define TM1_TM_CUR_VALUE_MSK 0x0000ffff -+#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000 -+#define TM1_TM_CUR_VALUE_SFT 0 -+#define TM1_TM_CUR_VALUE_HI 15 -+#define TM1_TM_CUR_VALUE_SZ 16 -+#define TM2_TM_INIT_VALUE_MSK 0x0000ffff -+#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000 -+#define TM2_TM_INIT_VALUE_SFT 0 -+#define TM2_TM_INIT_VALUE_HI 15 -+#define TM2_TM_INIT_VALUE_SZ 16 -+#define TM2_TM_MODE_MSK 0x00010000 -+#define TM2_TM_MODE_I_MSK 0xfffeffff -+#define TM2_TM_MODE_SFT 16 -+#define TM2_TM_MODE_HI 16 -+#define TM2_TM_MODE_SZ 1 -+#define TM2_TM_INT_STS_DONE_MSK 0x00020000 -+#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff -+#define TM2_TM_INT_STS_DONE_SFT 17 -+#define TM2_TM_INT_STS_DONE_HI 17 -+#define TM2_TM_INT_STS_DONE_SZ 1 -+#define TM2_TM_INT_MASK_MSK 0x00040000 -+#define TM2_TM_INT_MASK_I_MSK 0xfffbffff -+#define TM2_TM_INT_MASK_SFT 18 -+#define TM2_TM_INT_MASK_HI 18 -+#define TM2_TM_INT_MASK_SZ 1 -+#define TM2_TM_CUR_VALUE_MSK 0x0000ffff -+#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000 -+#define TM2_TM_CUR_VALUE_SFT 0 -+#define TM2_TM_CUR_VALUE_HI 15 -+#define TM2_TM_CUR_VALUE_SZ 16 -+#define TM3_TM_INIT_VALUE_MSK 0x0000ffff -+#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000 -+#define TM3_TM_INIT_VALUE_SFT 0 -+#define TM3_TM_INIT_VALUE_HI 15 -+#define TM3_TM_INIT_VALUE_SZ 16 -+#define TM3_TM_MODE_MSK 0x00010000 -+#define TM3_TM_MODE_I_MSK 0xfffeffff -+#define TM3_TM_MODE_SFT 16 -+#define TM3_TM_MODE_HI 16 -+#define TM3_TM_MODE_SZ 1 -+#define TM3_TM_INT_STS_DONE_MSK 0x00020000 -+#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff -+#define TM3_TM_INT_STS_DONE_SFT 17 -+#define TM3_TM_INT_STS_DONE_HI 17 -+#define TM3_TM_INT_STS_DONE_SZ 1 -+#define TM3_TM_INT_MASK_MSK 0x00040000 -+#define TM3_TM_INT_MASK_I_MSK 0xfffbffff -+#define TM3_TM_INT_MASK_SFT 18 -+#define TM3_TM_INT_MASK_HI 18 -+#define TM3_TM_INT_MASK_SZ 1 -+#define TM3_TM_CUR_VALUE_MSK 0x0000ffff -+#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000 -+#define TM3_TM_CUR_VALUE_SFT 0 -+#define TM3_TM_CUR_VALUE_HI 15 -+#define TM3_TM_CUR_VALUE_SZ 16 -+#define MCU_WDT_TIME_CNT_MSK 0x0000ffff -+#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000 -+#define MCU_WDT_TIME_CNT_SFT 0 -+#define MCU_WDT_TIME_CNT_HI 15 -+#define MCU_WDT_TIME_CNT_SZ 16 -+#define MCU_WDT_STATUS_MSK 0x00020000 -+#define MCU_WDT_STATUS_I_MSK 0xfffdffff -+#define MCU_WDT_STATUS_SFT 17 -+#define MCU_WDT_STATUS_HI 17 -+#define MCU_WDT_STATUS_SZ 1 -+#define MCU_WDOG_ENA_MSK 0x80000000 -+#define MCU_WDOG_ENA_I_MSK 0x7fffffff -+#define MCU_WDOG_ENA_SFT 31 -+#define MCU_WDOG_ENA_HI 31 -+#define MCU_WDOG_ENA_SZ 1 -+#define SYS_WDT_TIME_CNT_MSK 0x0000ffff -+#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000 -+#define SYS_WDT_TIME_CNT_SFT 0 -+#define SYS_WDT_TIME_CNT_HI 15 -+#define SYS_WDT_TIME_CNT_SZ 16 -+#define SYS_WDT_STATUS_MSK 0x00020000 -+#define SYS_WDT_STATUS_I_MSK 0xfffdffff -+#define SYS_WDT_STATUS_SFT 17 -+#define SYS_WDT_STATUS_HI 17 -+#define SYS_WDT_STATUS_SZ 1 -+#define SYS_WDOG_ENA_MSK 0x80000000 -+#define SYS_WDOG_ENA_I_MSK 0x7fffffff -+#define SYS_WDOG_ENA_SFT 31 -+#define SYS_WDOG_ENA_HI 31 -+#define SYS_WDOG_ENA_SZ 1 -+#define XLNA_EN_O_OE_MSK 0x00000001 -+#define XLNA_EN_O_OE_I_MSK 0xfffffffe -+#define XLNA_EN_O_OE_SFT 0 -+#define XLNA_EN_O_OE_HI 0 -+#define XLNA_EN_O_OE_SZ 1 -+#define XLNA_EN_O_PE_MSK 0x00000002 -+#define XLNA_EN_O_PE_I_MSK 0xfffffffd -+#define XLNA_EN_O_PE_SFT 1 -+#define XLNA_EN_O_PE_HI 1 -+#define XLNA_EN_O_PE_SZ 1 -+#define PAD6_IE_MSK 0x00000008 -+#define PAD6_IE_I_MSK 0xfffffff7 -+#define PAD6_IE_SFT 3 -+#define PAD6_IE_HI 3 -+#define PAD6_IE_SZ 1 -+#define PAD6_SEL_I_MSK 0x00000030 -+#define PAD6_SEL_I_I_MSK 0xffffffcf -+#define PAD6_SEL_I_SFT 4 -+#define PAD6_SEL_I_HI 5 -+#define PAD6_SEL_I_SZ 2 -+#define PAD6_OD_MSK 0x00000100 -+#define PAD6_OD_I_MSK 0xfffffeff -+#define PAD6_OD_SFT 8 -+#define PAD6_OD_HI 8 -+#define PAD6_OD_SZ 1 -+#define PAD6_SEL_O_MSK 0x00001000 -+#define PAD6_SEL_O_I_MSK 0xffffefff -+#define PAD6_SEL_O_SFT 12 -+#define PAD6_SEL_O_HI 12 -+#define PAD6_SEL_O_SZ 1 -+#define XLNA_EN_O_C_MSK 0x10000000 -+#define XLNA_EN_O_C_I_MSK 0xefffffff -+#define XLNA_EN_O_C_SFT 28 -+#define XLNA_EN_O_C_HI 28 -+#define XLNA_EN_O_C_SZ 1 -+#define WIFI_TX_SW_O_OE_MSK 0x00000001 -+#define WIFI_TX_SW_O_OE_I_MSK 0xfffffffe -+#define WIFI_TX_SW_O_OE_SFT 0 -+#define WIFI_TX_SW_O_OE_HI 0 -+#define WIFI_TX_SW_O_OE_SZ 1 -+#define WIFI_TX_SW_O_PE_MSK 0x00000002 -+#define WIFI_TX_SW_O_PE_I_MSK 0xfffffffd -+#define WIFI_TX_SW_O_PE_SFT 1 -+#define WIFI_TX_SW_O_PE_HI 1 -+#define WIFI_TX_SW_O_PE_SZ 1 -+#define PAD7_IE_MSK 0x00000008 -+#define PAD7_IE_I_MSK 0xfffffff7 -+#define PAD7_IE_SFT 3 -+#define PAD7_IE_HI 3 -+#define PAD7_IE_SZ 1 -+#define PAD7_SEL_I_MSK 0x00000030 -+#define PAD7_SEL_I_I_MSK 0xffffffcf -+#define PAD7_SEL_I_SFT 4 -+#define PAD7_SEL_I_HI 5 -+#define PAD7_SEL_I_SZ 2 -+#define PAD7_OD_MSK 0x00000100 -+#define PAD7_OD_I_MSK 0xfffffeff -+#define PAD7_OD_SFT 8 -+#define PAD7_OD_HI 8 -+#define PAD7_OD_SZ 1 -+#define PAD7_SEL_O_MSK 0x00001000 -+#define PAD7_SEL_O_I_MSK 0xffffefff -+#define PAD7_SEL_O_SFT 12 -+#define PAD7_SEL_O_HI 12 -+#define PAD7_SEL_O_SZ 1 -+#define WIFI_TX_SW_O_C_MSK 0x10000000 -+#define WIFI_TX_SW_O_C_I_MSK 0xefffffff -+#define WIFI_TX_SW_O_C_SFT 28 -+#define WIFI_TX_SW_O_C_HI 28 -+#define WIFI_TX_SW_O_C_SZ 1 -+#define WIFI_RX_SW_O_OE_MSK 0x00000001 -+#define WIFI_RX_SW_O_OE_I_MSK 0xfffffffe -+#define WIFI_RX_SW_O_OE_SFT 0 -+#define WIFI_RX_SW_O_OE_HI 0 -+#define WIFI_RX_SW_O_OE_SZ 1 -+#define WIFI_RX_SW_O_PE_MSK 0x00000002 -+#define WIFI_RX_SW_O_PE_I_MSK 0xfffffffd -+#define WIFI_RX_SW_O_PE_SFT 1 -+#define WIFI_RX_SW_O_PE_HI 1 -+#define WIFI_RX_SW_O_PE_SZ 1 -+#define PAD8_IE_MSK 0x00000008 -+#define PAD8_IE_I_MSK 0xfffffff7 -+#define PAD8_IE_SFT 3 -+#define PAD8_IE_HI 3 -+#define PAD8_IE_SZ 1 -+#define PAD8_SEL_I_MSK 0x00000030 -+#define PAD8_SEL_I_I_MSK 0xffffffcf -+#define PAD8_SEL_I_SFT 4 -+#define PAD8_SEL_I_HI 5 -+#define PAD8_SEL_I_SZ 2 -+#define PAD8_OD_MSK 0x00000100 -+#define PAD8_OD_I_MSK 0xfffffeff -+#define PAD8_OD_SFT 8 -+#define PAD8_OD_HI 8 -+#define PAD8_OD_SZ 1 -+#define WIFI_RX_SW_O_C_MSK 0x10000000 -+#define WIFI_RX_SW_O_C_I_MSK 0xefffffff -+#define WIFI_RX_SW_O_C_SFT 28 -+#define WIFI_RX_SW_O_C_HI 28 -+#define WIFI_RX_SW_O_C_SZ 1 -+#define BT_SW_O_OE_MSK 0x00000001 -+#define BT_SW_O_OE_I_MSK 0xfffffffe -+#define BT_SW_O_OE_SFT 0 -+#define BT_SW_O_OE_HI 0 -+#define BT_SW_O_OE_SZ 1 -+#define BT_SW_O_PE_MSK 0x00000002 -+#define BT_SW_O_PE_I_MSK 0xfffffffd -+#define BT_SW_O_PE_SFT 1 -+#define BT_SW_O_PE_HI 1 -+#define BT_SW_O_PE_SZ 1 -+#define PAD9_IE_MSK 0x00000008 -+#define PAD9_IE_I_MSK 0xfffffff7 -+#define PAD9_IE_SFT 3 -+#define PAD9_IE_HI 3 -+#define PAD9_IE_SZ 1 -+#define PAD9_SEL_I_MSK 0x00000030 -+#define PAD9_SEL_I_I_MSK 0xffffffcf -+#define PAD9_SEL_I_SFT 4 -+#define PAD9_SEL_I_HI 5 -+#define PAD9_SEL_I_SZ 2 -+#define PAD9_OD_MSK 0x00000100 -+#define PAD9_OD_I_MSK 0xfffffeff -+#define PAD9_OD_SFT 8 -+#define PAD9_OD_HI 8 -+#define PAD9_OD_SZ 1 -+#define PAD9_SEL_O_MSK 0x00001000 -+#define PAD9_SEL_O_I_MSK 0xffffefff -+#define PAD9_SEL_O_SFT 12 -+#define PAD9_SEL_O_HI 12 -+#define PAD9_SEL_O_SZ 1 -+#define BT_SW_O_C_MSK 0x10000000 -+#define BT_SW_O_C_I_MSK 0xefffffff -+#define BT_SW_O_C_SFT 28 -+#define BT_SW_O_C_HI 28 -+#define BT_SW_O_C_SZ 1 -+#define XPA_EN_O_OE_MSK 0x00000001 -+#define XPA_EN_O_OE_I_MSK 0xfffffffe -+#define XPA_EN_O_OE_SFT 0 -+#define XPA_EN_O_OE_HI 0 -+#define XPA_EN_O_OE_SZ 1 -+#define XPA_EN_O_PE_MSK 0x00000002 -+#define XPA_EN_O_PE_I_MSK 0xfffffffd -+#define XPA_EN_O_PE_SFT 1 -+#define XPA_EN_O_PE_HI 1 -+#define XPA_EN_O_PE_SZ 1 -+#define PAD11_IE_MSK 0x00000008 -+#define PAD11_IE_I_MSK 0xfffffff7 -+#define PAD11_IE_SFT 3 -+#define PAD11_IE_HI 3 -+#define PAD11_IE_SZ 1 -+#define PAD11_SEL_I_MSK 0x00000030 -+#define PAD11_SEL_I_I_MSK 0xffffffcf -+#define PAD11_SEL_I_SFT 4 -+#define PAD11_SEL_I_HI 5 -+#define PAD11_SEL_I_SZ 2 -+#define PAD11_OD_MSK 0x00000100 -+#define PAD11_OD_I_MSK 0xfffffeff -+#define PAD11_OD_SFT 8 -+#define PAD11_OD_HI 8 -+#define PAD11_OD_SZ 1 -+#define PAD11_SEL_O_MSK 0x00001000 -+#define PAD11_SEL_O_I_MSK 0xffffefff -+#define PAD11_SEL_O_SFT 12 -+#define PAD11_SEL_O_HI 12 -+#define PAD11_SEL_O_SZ 1 -+#define XPA_EN_O_C_MSK 0x10000000 -+#define XPA_EN_O_C_I_MSK 0xefffffff -+#define XPA_EN_O_C_SFT 28 -+#define XPA_EN_O_C_HI 28 -+#define XPA_EN_O_C_SZ 1 -+#define PAD15_OE_MSK 0x00000001 -+#define PAD15_OE_I_MSK 0xfffffffe -+#define PAD15_OE_SFT 0 -+#define PAD15_OE_HI 0 -+#define PAD15_OE_SZ 1 -+#define PAD15_PE_MSK 0x00000002 -+#define PAD15_PE_I_MSK 0xfffffffd -+#define PAD15_PE_SFT 1 -+#define PAD15_PE_HI 1 -+#define PAD15_PE_SZ 1 -+#define PAD15_DS_MSK 0x00000004 -+#define PAD15_DS_I_MSK 0xfffffffb -+#define PAD15_DS_SFT 2 -+#define PAD15_DS_HI 2 -+#define PAD15_DS_SZ 1 -+#define PAD15_IE_MSK 0x00000008 -+#define PAD15_IE_I_MSK 0xfffffff7 -+#define PAD15_IE_SFT 3 -+#define PAD15_IE_HI 3 -+#define PAD15_IE_SZ 1 -+#define PAD15_SEL_I_MSK 0x00000030 -+#define PAD15_SEL_I_I_MSK 0xffffffcf -+#define PAD15_SEL_I_SFT 4 -+#define PAD15_SEL_I_HI 5 -+#define PAD15_SEL_I_SZ 2 -+#define PAD15_OD_MSK 0x00000100 -+#define PAD15_OD_I_MSK 0xfffffeff -+#define PAD15_OD_SFT 8 -+#define PAD15_OD_HI 8 -+#define PAD15_OD_SZ 1 -+#define PAD15_SEL_O_MSK 0x00001000 -+#define PAD15_SEL_O_I_MSK 0xffffefff -+#define PAD15_SEL_O_SFT 12 -+#define PAD15_SEL_O_HI 12 -+#define PAD15_SEL_O_SZ 1 -+#define TEST_1_ID_MSK 0x10000000 -+#define TEST_1_ID_I_MSK 0xefffffff -+#define TEST_1_ID_SFT 28 -+#define TEST_1_ID_HI 28 -+#define TEST_1_ID_SZ 1 -+#define PAD16_OE_MSK 0x00000001 -+#define PAD16_OE_I_MSK 0xfffffffe -+#define PAD16_OE_SFT 0 -+#define PAD16_OE_HI 0 -+#define PAD16_OE_SZ 1 -+#define PAD16_PE_MSK 0x00000002 -+#define PAD16_PE_I_MSK 0xfffffffd -+#define PAD16_PE_SFT 1 -+#define PAD16_PE_HI 1 -+#define PAD16_PE_SZ 1 -+#define PAD16_DS_MSK 0x00000004 -+#define PAD16_DS_I_MSK 0xfffffffb -+#define PAD16_DS_SFT 2 -+#define PAD16_DS_HI 2 -+#define PAD16_DS_SZ 1 -+#define PAD16_IE_MSK 0x00000008 -+#define PAD16_IE_I_MSK 0xfffffff7 -+#define PAD16_IE_SFT 3 -+#define PAD16_IE_HI 3 -+#define PAD16_IE_SZ 1 -+#define PAD16_SEL_I_MSK 0x00000030 -+#define PAD16_SEL_I_I_MSK 0xffffffcf -+#define PAD16_SEL_I_SFT 4 -+#define PAD16_SEL_I_HI 5 -+#define PAD16_SEL_I_SZ 2 -+#define PAD16_OD_MSK 0x00000100 -+#define PAD16_OD_I_MSK 0xfffffeff -+#define PAD16_OD_SFT 8 -+#define PAD16_OD_HI 8 -+#define PAD16_OD_SZ 1 -+#define PAD16_SEL_O_MSK 0x00001000 -+#define PAD16_SEL_O_I_MSK 0xffffefff -+#define PAD16_SEL_O_SFT 12 -+#define PAD16_SEL_O_HI 12 -+#define PAD16_SEL_O_SZ 1 -+#define TEST_2_ID_MSK 0x10000000 -+#define TEST_2_ID_I_MSK 0xefffffff -+#define TEST_2_ID_SFT 28 -+#define TEST_2_ID_HI 28 -+#define TEST_2_ID_SZ 1 -+#define PAD17_OE_MSK 0x00000001 -+#define PAD17_OE_I_MSK 0xfffffffe -+#define PAD17_OE_SFT 0 -+#define PAD17_OE_HI 0 -+#define PAD17_OE_SZ 1 -+#define PAD17_PE_MSK 0x00000002 -+#define PAD17_PE_I_MSK 0xfffffffd -+#define PAD17_PE_SFT 1 -+#define PAD17_PE_HI 1 -+#define PAD17_PE_SZ 1 -+#define PAD17_DS_MSK 0x00000004 -+#define PAD17_DS_I_MSK 0xfffffffb -+#define PAD17_DS_SFT 2 -+#define PAD17_DS_HI 2 -+#define PAD17_DS_SZ 1 -+#define PAD17_IE_MSK 0x00000008 -+#define PAD17_IE_I_MSK 0xfffffff7 -+#define PAD17_IE_SFT 3 -+#define PAD17_IE_HI 3 -+#define PAD17_IE_SZ 1 -+#define PAD17_SEL_I_MSK 0x00000030 -+#define PAD17_SEL_I_I_MSK 0xffffffcf -+#define PAD17_SEL_I_SFT 4 -+#define PAD17_SEL_I_HI 5 -+#define PAD17_SEL_I_SZ 2 -+#define PAD17_OD_MSK 0x00000100 -+#define PAD17_OD_I_MSK 0xfffffeff -+#define PAD17_OD_SFT 8 -+#define PAD17_OD_HI 8 -+#define PAD17_OD_SZ 1 -+#define PAD17_SEL_O_MSK 0x00001000 -+#define PAD17_SEL_O_I_MSK 0xffffefff -+#define PAD17_SEL_O_SFT 12 -+#define PAD17_SEL_O_HI 12 -+#define PAD17_SEL_O_SZ 1 -+#define TEST_3_ID_MSK 0x10000000 -+#define TEST_3_ID_I_MSK 0xefffffff -+#define TEST_3_ID_SFT 28 -+#define TEST_3_ID_HI 28 -+#define TEST_3_ID_SZ 1 -+#define PAD18_OE_MSK 0x00000001 -+#define PAD18_OE_I_MSK 0xfffffffe -+#define PAD18_OE_SFT 0 -+#define PAD18_OE_HI 0 -+#define PAD18_OE_SZ 1 -+#define PAD18_PE_MSK 0x00000002 -+#define PAD18_PE_I_MSK 0xfffffffd -+#define PAD18_PE_SFT 1 -+#define PAD18_PE_HI 1 -+#define PAD18_PE_SZ 1 -+#define PAD18_DS_MSK 0x00000004 -+#define PAD18_DS_I_MSK 0xfffffffb -+#define PAD18_DS_SFT 2 -+#define PAD18_DS_HI 2 -+#define PAD18_DS_SZ 1 -+#define PAD18_IE_MSK 0x00000008 -+#define PAD18_IE_I_MSK 0xfffffff7 -+#define PAD18_IE_SFT 3 -+#define PAD18_IE_HI 3 -+#define PAD18_IE_SZ 1 -+#define PAD18_SEL_I_MSK 0x00000030 -+#define PAD18_SEL_I_I_MSK 0xffffffcf -+#define PAD18_SEL_I_SFT 4 -+#define PAD18_SEL_I_HI 5 -+#define PAD18_SEL_I_SZ 2 -+#define PAD18_OD_MSK 0x00000100 -+#define PAD18_OD_I_MSK 0xfffffeff -+#define PAD18_OD_SFT 8 -+#define PAD18_OD_HI 8 -+#define PAD18_OD_SZ 1 -+#define PAD18_SEL_O_MSK 0x00003000 -+#define PAD18_SEL_O_I_MSK 0xffffcfff -+#define PAD18_SEL_O_SFT 12 -+#define PAD18_SEL_O_HI 13 -+#define PAD18_SEL_O_SZ 2 -+#define TEST_4_ID_MSK 0x10000000 -+#define TEST_4_ID_I_MSK 0xefffffff -+#define TEST_4_ID_SFT 28 -+#define TEST_4_ID_HI 28 -+#define TEST_4_ID_SZ 1 -+#define PAD19_OE_MSK 0x00000001 -+#define PAD19_OE_I_MSK 0xfffffffe -+#define PAD19_OE_SFT 0 -+#define PAD19_OE_HI 0 -+#define PAD19_OE_SZ 1 -+#define PAD19_PE_MSK 0x00000002 -+#define PAD19_PE_I_MSK 0xfffffffd -+#define PAD19_PE_SFT 1 -+#define PAD19_PE_HI 1 -+#define PAD19_PE_SZ 1 -+#define PAD19_DS_MSK 0x00000004 -+#define PAD19_DS_I_MSK 0xfffffffb -+#define PAD19_DS_SFT 2 -+#define PAD19_DS_HI 2 -+#define PAD19_DS_SZ 1 -+#define PAD19_IE_MSK 0x00000008 -+#define PAD19_IE_I_MSK 0xfffffff7 -+#define PAD19_IE_SFT 3 -+#define PAD19_IE_HI 3 -+#define PAD19_IE_SZ 1 -+#define PAD19_SEL_I_MSK 0x00000030 -+#define PAD19_SEL_I_I_MSK 0xffffffcf -+#define PAD19_SEL_I_SFT 4 -+#define PAD19_SEL_I_HI 5 -+#define PAD19_SEL_I_SZ 2 -+#define PAD19_OD_MSK 0x00000100 -+#define PAD19_OD_I_MSK 0xfffffeff -+#define PAD19_OD_SFT 8 -+#define PAD19_OD_HI 8 -+#define PAD19_OD_SZ 1 -+#define PAD19_SEL_O_MSK 0x00007000 -+#define PAD19_SEL_O_I_MSK 0xffff8fff -+#define PAD19_SEL_O_SFT 12 -+#define PAD19_SEL_O_HI 14 -+#define PAD19_SEL_O_SZ 3 -+#define SHORT_TO_20_ID_MSK 0x10000000 -+#define SHORT_TO_20_ID_I_MSK 0xefffffff -+#define SHORT_TO_20_ID_SFT 28 -+#define SHORT_TO_20_ID_HI 28 -+#define SHORT_TO_20_ID_SZ 1 -+#define PAD20_OE_MSK 0x00000001 -+#define PAD20_OE_I_MSK 0xfffffffe -+#define PAD20_OE_SFT 0 -+#define PAD20_OE_HI 0 -+#define PAD20_OE_SZ 1 -+#define PAD20_PE_MSK 0x00000002 -+#define PAD20_PE_I_MSK 0xfffffffd -+#define PAD20_PE_SFT 1 -+#define PAD20_PE_HI 1 -+#define PAD20_PE_SZ 1 -+#define PAD20_DS_MSK 0x00000004 -+#define PAD20_DS_I_MSK 0xfffffffb -+#define PAD20_DS_SFT 2 -+#define PAD20_DS_HI 2 -+#define PAD20_DS_SZ 1 -+#define PAD20_IE_MSK 0x00000008 -+#define PAD20_IE_I_MSK 0xfffffff7 -+#define PAD20_IE_SFT 3 -+#define PAD20_IE_HI 3 -+#define PAD20_IE_SZ 1 -+#define PAD20_SEL_I_MSK 0x000000f0 -+#define PAD20_SEL_I_I_MSK 0xffffff0f -+#define PAD20_SEL_I_SFT 4 -+#define PAD20_SEL_I_HI 7 -+#define PAD20_SEL_I_SZ 4 -+#define PAD20_OD_MSK 0x00000100 -+#define PAD20_OD_I_MSK 0xfffffeff -+#define PAD20_OD_SFT 8 -+#define PAD20_OD_HI 8 -+#define PAD20_OD_SZ 1 -+#define PAD20_SEL_O_MSK 0x00003000 -+#define PAD20_SEL_O_I_MSK 0xffffcfff -+#define PAD20_SEL_O_SFT 12 -+#define PAD20_SEL_O_HI 13 -+#define PAD20_SEL_O_SZ 2 -+#define STRAP0_MSK 0x08000000 -+#define STRAP0_I_MSK 0xf7ffffff -+#define STRAP0_SFT 27 -+#define STRAP0_HI 27 -+#define STRAP0_SZ 1 -+#define GPIO_TEST_1_ID_MSK 0x10000000 -+#define GPIO_TEST_1_ID_I_MSK 0xefffffff -+#define GPIO_TEST_1_ID_SFT 28 -+#define GPIO_TEST_1_ID_HI 28 -+#define GPIO_TEST_1_ID_SZ 1 -+#define PAD21_OE_MSK 0x00000001 -+#define PAD21_OE_I_MSK 0xfffffffe -+#define PAD21_OE_SFT 0 -+#define PAD21_OE_HI 0 -+#define PAD21_OE_SZ 1 -+#define PAD21_PE_MSK 0x00000002 -+#define PAD21_PE_I_MSK 0xfffffffd -+#define PAD21_PE_SFT 1 -+#define PAD21_PE_HI 1 -+#define PAD21_PE_SZ 1 -+#define PAD21_DS_MSK 0x00000004 -+#define PAD21_DS_I_MSK 0xfffffffb -+#define PAD21_DS_SFT 2 -+#define PAD21_DS_HI 2 -+#define PAD21_DS_SZ 1 -+#define PAD21_IE_MSK 0x00000008 -+#define PAD21_IE_I_MSK 0xfffffff7 -+#define PAD21_IE_SFT 3 -+#define PAD21_IE_HI 3 -+#define PAD21_IE_SZ 1 -+#define PAD21_SEL_I_MSK 0x00000070 -+#define PAD21_SEL_I_I_MSK 0xffffff8f -+#define PAD21_SEL_I_SFT 4 -+#define PAD21_SEL_I_HI 6 -+#define PAD21_SEL_I_SZ 3 -+#define PAD21_OD_MSK 0x00000100 -+#define PAD21_OD_I_MSK 0xfffffeff -+#define PAD21_OD_SFT 8 -+#define PAD21_OD_HI 8 -+#define PAD21_OD_SZ 1 -+#define PAD21_SEL_O_MSK 0x00003000 -+#define PAD21_SEL_O_I_MSK 0xffffcfff -+#define PAD21_SEL_O_SFT 12 -+#define PAD21_SEL_O_HI 13 -+#define PAD21_SEL_O_SZ 2 -+#define STRAP3_MSK 0x08000000 -+#define STRAP3_I_MSK 0xf7ffffff -+#define STRAP3_SFT 27 -+#define STRAP3_HI 27 -+#define STRAP3_SZ 1 -+#define GPIO_TEST_2_ID_MSK 0x10000000 -+#define GPIO_TEST_2_ID_I_MSK 0xefffffff -+#define GPIO_TEST_2_ID_SFT 28 -+#define GPIO_TEST_2_ID_HI 28 -+#define GPIO_TEST_2_ID_SZ 1 -+#define PAD22_OE_MSK 0x00000001 -+#define PAD22_OE_I_MSK 0xfffffffe -+#define PAD22_OE_SFT 0 -+#define PAD22_OE_HI 0 -+#define PAD22_OE_SZ 1 -+#define PAD22_PE_MSK 0x00000002 -+#define PAD22_PE_I_MSK 0xfffffffd -+#define PAD22_PE_SFT 1 -+#define PAD22_PE_HI 1 -+#define PAD22_PE_SZ 1 -+#define PAD22_DS_MSK 0x00000004 -+#define PAD22_DS_I_MSK 0xfffffffb -+#define PAD22_DS_SFT 2 -+#define PAD22_DS_HI 2 -+#define PAD22_DS_SZ 1 -+#define PAD22_IE_MSK 0x00000008 -+#define PAD22_IE_I_MSK 0xfffffff7 -+#define PAD22_IE_SFT 3 -+#define PAD22_IE_HI 3 -+#define PAD22_IE_SZ 1 -+#define PAD22_SEL_I_MSK 0x00000070 -+#define PAD22_SEL_I_I_MSK 0xffffff8f -+#define PAD22_SEL_I_SFT 4 -+#define PAD22_SEL_I_HI 6 -+#define PAD22_SEL_I_SZ 3 -+#define PAD22_OD_MSK 0x00000100 -+#define PAD22_OD_I_MSK 0xfffffeff -+#define PAD22_OD_SFT 8 -+#define PAD22_OD_HI 8 -+#define PAD22_OD_SZ 1 -+#define PAD22_SEL_O_MSK 0x00007000 -+#define PAD22_SEL_O_I_MSK 0xffff8fff -+#define PAD22_SEL_O_SFT 12 -+#define PAD22_SEL_O_HI 14 -+#define PAD22_SEL_O_SZ 3 -+#define PAD22_SEL_OE_MSK 0x00100000 -+#define PAD22_SEL_OE_I_MSK 0xffefffff -+#define PAD22_SEL_OE_SFT 20 -+#define PAD22_SEL_OE_HI 20 -+#define PAD22_SEL_OE_SZ 1 -+#define GPIO_TEST_3_ID_MSK 0x10000000 -+#define GPIO_TEST_3_ID_I_MSK 0xefffffff -+#define GPIO_TEST_3_ID_SFT 28 -+#define GPIO_TEST_3_ID_HI 28 -+#define GPIO_TEST_3_ID_SZ 1 -+#define PAD24_OE_MSK 0x00000001 -+#define PAD24_OE_I_MSK 0xfffffffe -+#define PAD24_OE_SFT 0 -+#define PAD24_OE_HI 0 -+#define PAD24_OE_SZ 1 -+#define PAD24_PE_MSK 0x00000002 -+#define PAD24_PE_I_MSK 0xfffffffd -+#define PAD24_PE_SFT 1 -+#define PAD24_PE_HI 1 -+#define PAD24_PE_SZ 1 -+#define PAD24_DS_MSK 0x00000004 -+#define PAD24_DS_I_MSK 0xfffffffb -+#define PAD24_DS_SFT 2 -+#define PAD24_DS_HI 2 -+#define PAD24_DS_SZ 1 -+#define PAD24_IE_MSK 0x00000008 -+#define PAD24_IE_I_MSK 0xfffffff7 -+#define PAD24_IE_SFT 3 -+#define PAD24_IE_HI 3 -+#define PAD24_IE_SZ 1 -+#define PAD24_SEL_I_MSK 0x00000030 -+#define PAD24_SEL_I_I_MSK 0xffffffcf -+#define PAD24_SEL_I_SFT 4 -+#define PAD24_SEL_I_HI 5 -+#define PAD24_SEL_I_SZ 2 -+#define PAD24_OD_MSK 0x00000100 -+#define PAD24_OD_I_MSK 0xfffffeff -+#define PAD24_OD_SFT 8 -+#define PAD24_OD_HI 8 -+#define PAD24_OD_SZ 1 -+#define PAD24_SEL_O_MSK 0x00007000 -+#define PAD24_SEL_O_I_MSK 0xffff8fff -+#define PAD24_SEL_O_SFT 12 -+#define PAD24_SEL_O_HI 14 -+#define PAD24_SEL_O_SZ 3 -+#define GPIO_TEST_4_ID_MSK 0x10000000 -+#define GPIO_TEST_4_ID_I_MSK 0xefffffff -+#define GPIO_TEST_4_ID_SFT 28 -+#define GPIO_TEST_4_ID_HI 28 -+#define GPIO_TEST_4_ID_SZ 1 -+#define PAD25_OE_MSK 0x00000001 -+#define PAD25_OE_I_MSK 0xfffffffe -+#define PAD25_OE_SFT 0 -+#define PAD25_OE_HI 0 -+#define PAD25_OE_SZ 1 -+#define PAD25_PE_MSK 0x00000002 -+#define PAD25_PE_I_MSK 0xfffffffd -+#define PAD25_PE_SFT 1 -+#define PAD25_PE_HI 1 -+#define PAD25_PE_SZ 1 -+#define PAD25_DS_MSK 0x00000004 -+#define PAD25_DS_I_MSK 0xfffffffb -+#define PAD25_DS_SFT 2 -+#define PAD25_DS_HI 2 -+#define PAD25_DS_SZ 1 -+#define PAD25_IE_MSK 0x00000008 -+#define PAD25_IE_I_MSK 0xfffffff7 -+#define PAD25_IE_SFT 3 -+#define PAD25_IE_HI 3 -+#define PAD25_IE_SZ 1 -+#define PAD25_SEL_I_MSK 0x00000070 -+#define PAD25_SEL_I_I_MSK 0xffffff8f -+#define PAD25_SEL_I_SFT 4 -+#define PAD25_SEL_I_HI 6 -+#define PAD25_SEL_I_SZ 3 -+#define PAD25_OD_MSK 0x00000100 -+#define PAD25_OD_I_MSK 0xfffffeff -+#define PAD25_OD_SFT 8 -+#define PAD25_OD_HI 8 -+#define PAD25_OD_SZ 1 -+#define PAD25_SEL_O_MSK 0x00007000 -+#define PAD25_SEL_O_I_MSK 0xffff8fff -+#define PAD25_SEL_O_SFT 12 -+#define PAD25_SEL_O_HI 14 -+#define PAD25_SEL_O_SZ 3 -+#define PAD25_SEL_OE_MSK 0x00100000 -+#define PAD25_SEL_OE_I_MSK 0xffefffff -+#define PAD25_SEL_OE_SFT 20 -+#define PAD25_SEL_OE_HI 20 -+#define PAD25_SEL_OE_SZ 1 -+#define STRAP1_MSK 0x08000000 -+#define STRAP1_I_MSK 0xf7ffffff -+#define STRAP1_SFT 27 -+#define STRAP1_HI 27 -+#define STRAP1_SZ 1 -+#define GPIO_1_ID_MSK 0x10000000 -+#define GPIO_1_ID_I_MSK 0xefffffff -+#define GPIO_1_ID_SFT 28 -+#define GPIO_1_ID_HI 28 -+#define GPIO_1_ID_SZ 1 -+#define PAD27_OE_MSK 0x00000001 -+#define PAD27_OE_I_MSK 0xfffffffe -+#define PAD27_OE_SFT 0 -+#define PAD27_OE_HI 0 -+#define PAD27_OE_SZ 1 -+#define PAD27_PE_MSK 0x00000002 -+#define PAD27_PE_I_MSK 0xfffffffd -+#define PAD27_PE_SFT 1 -+#define PAD27_PE_HI 1 -+#define PAD27_PE_SZ 1 -+#define PAD27_DS_MSK 0x00000004 -+#define PAD27_DS_I_MSK 0xfffffffb -+#define PAD27_DS_SFT 2 -+#define PAD27_DS_HI 2 -+#define PAD27_DS_SZ 1 -+#define PAD27_IE_MSK 0x00000008 -+#define PAD27_IE_I_MSK 0xfffffff7 -+#define PAD27_IE_SFT 3 -+#define PAD27_IE_HI 3 -+#define PAD27_IE_SZ 1 -+#define PAD27_SEL_I_MSK 0x00000070 -+#define PAD27_SEL_I_I_MSK 0xffffff8f -+#define PAD27_SEL_I_SFT 4 -+#define PAD27_SEL_I_HI 6 -+#define PAD27_SEL_I_SZ 3 -+#define PAD27_OD_MSK 0x00000100 -+#define PAD27_OD_I_MSK 0xfffffeff -+#define PAD27_OD_SFT 8 -+#define PAD27_OD_HI 8 -+#define PAD27_OD_SZ 1 -+#define PAD27_SEL_O_MSK 0x00007000 -+#define PAD27_SEL_O_I_MSK 0xffff8fff -+#define PAD27_SEL_O_SFT 12 -+#define PAD27_SEL_O_HI 14 -+#define PAD27_SEL_O_SZ 3 -+#define GPIO_2_ID_MSK 0x10000000 -+#define GPIO_2_ID_I_MSK 0xefffffff -+#define GPIO_2_ID_SFT 28 -+#define GPIO_2_ID_HI 28 -+#define GPIO_2_ID_SZ 1 -+#define PAD28_OE_MSK 0x00000001 -+#define PAD28_OE_I_MSK 0xfffffffe -+#define PAD28_OE_SFT 0 -+#define PAD28_OE_HI 0 -+#define PAD28_OE_SZ 1 -+#define PAD28_PE_MSK 0x00000002 -+#define PAD28_PE_I_MSK 0xfffffffd -+#define PAD28_PE_SFT 1 -+#define PAD28_PE_HI 1 -+#define PAD28_PE_SZ 1 -+#define PAD28_DS_MSK 0x00000004 -+#define PAD28_DS_I_MSK 0xfffffffb -+#define PAD28_DS_SFT 2 -+#define PAD28_DS_HI 2 -+#define PAD28_DS_SZ 1 -+#define PAD28_IE_MSK 0x00000008 -+#define PAD28_IE_I_MSK 0xfffffff7 -+#define PAD28_IE_SFT 3 -+#define PAD28_IE_HI 3 -+#define PAD28_IE_SZ 1 -+#define PAD28_SEL_I_MSK 0x00000070 -+#define PAD28_SEL_I_I_MSK 0xffffff8f -+#define PAD28_SEL_I_SFT 4 -+#define PAD28_SEL_I_HI 6 -+#define PAD28_SEL_I_SZ 3 -+#define PAD28_OD_MSK 0x00000100 -+#define PAD28_OD_I_MSK 0xfffffeff -+#define PAD28_OD_SFT 8 -+#define PAD28_OD_HI 8 -+#define PAD28_OD_SZ 1 -+#define PAD28_SEL_O_MSK 0x0000f000 -+#define PAD28_SEL_O_I_MSK 0xffff0fff -+#define PAD28_SEL_O_SFT 12 -+#define PAD28_SEL_O_HI 15 -+#define PAD28_SEL_O_SZ 4 -+#define PAD28_SEL_OE_MSK 0x00100000 -+#define PAD28_SEL_OE_I_MSK 0xffefffff -+#define PAD28_SEL_OE_SFT 20 -+#define PAD28_SEL_OE_HI 20 -+#define PAD28_SEL_OE_SZ 1 -+#define GPIO_3_ID_MSK 0x10000000 -+#define GPIO_3_ID_I_MSK 0xefffffff -+#define GPIO_3_ID_SFT 28 -+#define GPIO_3_ID_HI 28 -+#define GPIO_3_ID_SZ 1 -+#define PAD29_OE_MSK 0x00000001 -+#define PAD29_OE_I_MSK 0xfffffffe -+#define PAD29_OE_SFT 0 -+#define PAD29_OE_HI 0 -+#define PAD29_OE_SZ 1 -+#define PAD29_PE_MSK 0x00000002 -+#define PAD29_PE_I_MSK 0xfffffffd -+#define PAD29_PE_SFT 1 -+#define PAD29_PE_HI 1 -+#define PAD29_PE_SZ 1 -+#define PAD29_DS_MSK 0x00000004 -+#define PAD29_DS_I_MSK 0xfffffffb -+#define PAD29_DS_SFT 2 -+#define PAD29_DS_HI 2 -+#define PAD29_DS_SZ 1 -+#define PAD29_IE_MSK 0x00000008 -+#define PAD29_IE_I_MSK 0xfffffff7 -+#define PAD29_IE_SFT 3 -+#define PAD29_IE_HI 3 -+#define PAD29_IE_SZ 1 -+#define PAD29_SEL_I_MSK 0x00000070 -+#define PAD29_SEL_I_I_MSK 0xffffff8f -+#define PAD29_SEL_I_SFT 4 -+#define PAD29_SEL_I_HI 6 -+#define PAD29_SEL_I_SZ 3 -+#define PAD29_OD_MSK 0x00000100 -+#define PAD29_OD_I_MSK 0xfffffeff -+#define PAD29_OD_SFT 8 -+#define PAD29_OD_HI 8 -+#define PAD29_OD_SZ 1 -+#define PAD29_SEL_O_MSK 0x00007000 -+#define PAD29_SEL_O_I_MSK 0xffff8fff -+#define PAD29_SEL_O_SFT 12 -+#define PAD29_SEL_O_HI 14 -+#define PAD29_SEL_O_SZ 3 -+#define GPIO_TEST_5_ID_MSK 0x10000000 -+#define GPIO_TEST_5_ID_I_MSK 0xefffffff -+#define GPIO_TEST_5_ID_SFT 28 -+#define GPIO_TEST_5_ID_HI 28 -+#define GPIO_TEST_5_ID_SZ 1 -+#define PAD30_OE_MSK 0x00000001 -+#define PAD30_OE_I_MSK 0xfffffffe -+#define PAD30_OE_SFT 0 -+#define PAD30_OE_HI 0 -+#define PAD30_OE_SZ 1 -+#define PAD30_PE_MSK 0x00000002 -+#define PAD30_PE_I_MSK 0xfffffffd -+#define PAD30_PE_SFT 1 -+#define PAD30_PE_HI 1 -+#define PAD30_PE_SZ 1 -+#define PAD30_DS_MSK 0x00000004 -+#define PAD30_DS_I_MSK 0xfffffffb -+#define PAD30_DS_SFT 2 -+#define PAD30_DS_HI 2 -+#define PAD30_DS_SZ 1 -+#define PAD30_IE_MSK 0x00000008 -+#define PAD30_IE_I_MSK 0xfffffff7 -+#define PAD30_IE_SFT 3 -+#define PAD30_IE_HI 3 -+#define PAD30_IE_SZ 1 -+#define PAD30_SEL_I_MSK 0x00000030 -+#define PAD30_SEL_I_I_MSK 0xffffffcf -+#define PAD30_SEL_I_SFT 4 -+#define PAD30_SEL_I_HI 5 -+#define PAD30_SEL_I_SZ 2 -+#define PAD30_OD_MSK 0x00000100 -+#define PAD30_OD_I_MSK 0xfffffeff -+#define PAD30_OD_SFT 8 -+#define PAD30_OD_HI 8 -+#define PAD30_OD_SZ 1 -+#define PAD30_SEL_O_MSK 0x00003000 -+#define PAD30_SEL_O_I_MSK 0xffffcfff -+#define PAD30_SEL_O_SFT 12 -+#define PAD30_SEL_O_HI 13 -+#define PAD30_SEL_O_SZ 2 -+#define TEST_6_ID_MSK 0x10000000 -+#define TEST_6_ID_I_MSK 0xefffffff -+#define TEST_6_ID_SFT 28 -+#define TEST_6_ID_HI 28 -+#define TEST_6_ID_SZ 1 -+#define PAD31_OE_MSK 0x00000001 -+#define PAD31_OE_I_MSK 0xfffffffe -+#define PAD31_OE_SFT 0 -+#define PAD31_OE_HI 0 -+#define PAD31_OE_SZ 1 -+#define PAD31_PE_MSK 0x00000002 -+#define PAD31_PE_I_MSK 0xfffffffd -+#define PAD31_PE_SFT 1 -+#define PAD31_PE_HI 1 -+#define PAD31_PE_SZ 1 -+#define PAD31_DS_MSK 0x00000004 -+#define PAD31_DS_I_MSK 0xfffffffb -+#define PAD31_DS_SFT 2 -+#define PAD31_DS_HI 2 -+#define PAD31_DS_SZ 1 -+#define PAD31_IE_MSK 0x00000008 -+#define PAD31_IE_I_MSK 0xfffffff7 -+#define PAD31_IE_SFT 3 -+#define PAD31_IE_HI 3 -+#define PAD31_IE_SZ 1 -+#define PAD31_SEL_I_MSK 0x00000030 -+#define PAD31_SEL_I_I_MSK 0xffffffcf -+#define PAD31_SEL_I_SFT 4 -+#define PAD31_SEL_I_HI 5 -+#define PAD31_SEL_I_SZ 2 -+#define PAD31_OD_MSK 0x00000100 -+#define PAD31_OD_I_MSK 0xfffffeff -+#define PAD31_OD_SFT 8 -+#define PAD31_OD_HI 8 -+#define PAD31_OD_SZ 1 -+#define PAD31_SEL_O_MSK 0x00003000 -+#define PAD31_SEL_O_I_MSK 0xffffcfff -+#define PAD31_SEL_O_SFT 12 -+#define PAD31_SEL_O_HI 13 -+#define PAD31_SEL_O_SZ 2 -+#define TEST_7_ID_MSK 0x10000000 -+#define TEST_7_ID_I_MSK 0xefffffff -+#define TEST_7_ID_SFT 28 -+#define TEST_7_ID_HI 28 -+#define TEST_7_ID_SZ 1 -+#define PAD32_OE_MSK 0x00000001 -+#define PAD32_OE_I_MSK 0xfffffffe -+#define PAD32_OE_SFT 0 -+#define PAD32_OE_HI 0 -+#define PAD32_OE_SZ 1 -+#define PAD32_PE_MSK 0x00000002 -+#define PAD32_PE_I_MSK 0xfffffffd -+#define PAD32_PE_SFT 1 -+#define PAD32_PE_HI 1 -+#define PAD32_PE_SZ 1 -+#define PAD32_DS_MSK 0x00000004 -+#define PAD32_DS_I_MSK 0xfffffffb -+#define PAD32_DS_SFT 2 -+#define PAD32_DS_HI 2 -+#define PAD32_DS_SZ 1 -+#define PAD32_IE_MSK 0x00000008 -+#define PAD32_IE_I_MSK 0xfffffff7 -+#define PAD32_IE_SFT 3 -+#define PAD32_IE_HI 3 -+#define PAD32_IE_SZ 1 -+#define PAD32_SEL_I_MSK 0x00000030 -+#define PAD32_SEL_I_I_MSK 0xffffffcf -+#define PAD32_SEL_I_SFT 4 -+#define PAD32_SEL_I_HI 5 -+#define PAD32_SEL_I_SZ 2 -+#define PAD32_OD_MSK 0x00000100 -+#define PAD32_OD_I_MSK 0xfffffeff -+#define PAD32_OD_SFT 8 -+#define PAD32_OD_HI 8 -+#define PAD32_OD_SZ 1 -+#define PAD32_SEL_O_MSK 0x00003000 -+#define PAD32_SEL_O_I_MSK 0xffffcfff -+#define PAD32_SEL_O_SFT 12 -+#define PAD32_SEL_O_HI 13 -+#define PAD32_SEL_O_SZ 2 -+#define TEST_8_ID_MSK 0x10000000 -+#define TEST_8_ID_I_MSK 0xefffffff -+#define TEST_8_ID_SFT 28 -+#define TEST_8_ID_HI 28 -+#define TEST_8_ID_SZ 1 -+#define PAD33_OE_MSK 0x00000001 -+#define PAD33_OE_I_MSK 0xfffffffe -+#define PAD33_OE_SFT 0 -+#define PAD33_OE_HI 0 -+#define PAD33_OE_SZ 1 -+#define PAD33_PE_MSK 0x00000002 -+#define PAD33_PE_I_MSK 0xfffffffd -+#define PAD33_PE_SFT 1 -+#define PAD33_PE_HI 1 -+#define PAD33_PE_SZ 1 -+#define PAD33_DS_MSK 0x00000004 -+#define PAD33_DS_I_MSK 0xfffffffb -+#define PAD33_DS_SFT 2 -+#define PAD33_DS_HI 2 -+#define PAD33_DS_SZ 1 -+#define PAD33_IE_MSK 0x00000008 -+#define PAD33_IE_I_MSK 0xfffffff7 -+#define PAD33_IE_SFT 3 -+#define PAD33_IE_HI 3 -+#define PAD33_IE_SZ 1 -+#define PAD33_SEL_I_MSK 0x00000030 -+#define PAD33_SEL_I_I_MSK 0xffffffcf -+#define PAD33_SEL_I_SFT 4 -+#define PAD33_SEL_I_HI 5 -+#define PAD33_SEL_I_SZ 2 -+#define PAD33_OD_MSK 0x00000100 -+#define PAD33_OD_I_MSK 0xfffffeff -+#define PAD33_OD_SFT 8 -+#define PAD33_OD_HI 8 -+#define PAD33_OD_SZ 1 -+#define PAD33_SEL_O_MSK 0x00003000 -+#define PAD33_SEL_O_I_MSK 0xffffcfff -+#define PAD33_SEL_O_SFT 12 -+#define PAD33_SEL_O_HI 13 -+#define PAD33_SEL_O_SZ 2 -+#define TEST_9_ID_MSK 0x10000000 -+#define TEST_9_ID_I_MSK 0xefffffff -+#define TEST_9_ID_SFT 28 -+#define TEST_9_ID_HI 28 -+#define TEST_9_ID_SZ 1 -+#define PAD34_OE_MSK 0x00000001 -+#define PAD34_OE_I_MSK 0xfffffffe -+#define PAD34_OE_SFT 0 -+#define PAD34_OE_HI 0 -+#define PAD34_OE_SZ 1 -+#define PAD34_PE_MSK 0x00000002 -+#define PAD34_PE_I_MSK 0xfffffffd -+#define PAD34_PE_SFT 1 -+#define PAD34_PE_HI 1 -+#define PAD34_PE_SZ 1 -+#define PAD34_DS_MSK 0x00000004 -+#define PAD34_DS_I_MSK 0xfffffffb -+#define PAD34_DS_SFT 2 -+#define PAD34_DS_HI 2 -+#define PAD34_DS_SZ 1 -+#define PAD34_IE_MSK 0x00000008 -+#define PAD34_IE_I_MSK 0xfffffff7 -+#define PAD34_IE_SFT 3 -+#define PAD34_IE_HI 3 -+#define PAD34_IE_SZ 1 -+#define PAD34_SEL_I_MSK 0x00000030 -+#define PAD34_SEL_I_I_MSK 0xffffffcf -+#define PAD34_SEL_I_SFT 4 -+#define PAD34_SEL_I_HI 5 -+#define PAD34_SEL_I_SZ 2 -+#define PAD34_OD_MSK 0x00000100 -+#define PAD34_OD_I_MSK 0xfffffeff -+#define PAD34_OD_SFT 8 -+#define PAD34_OD_HI 8 -+#define PAD34_OD_SZ 1 -+#define PAD34_SEL_O_MSK 0x00003000 -+#define PAD34_SEL_O_I_MSK 0xffffcfff -+#define PAD34_SEL_O_SFT 12 -+#define PAD34_SEL_O_HI 13 -+#define PAD34_SEL_O_SZ 2 -+#define TEST_10_ID_MSK 0x10000000 -+#define TEST_10_ID_I_MSK 0xefffffff -+#define TEST_10_ID_SFT 28 -+#define TEST_10_ID_HI 28 -+#define TEST_10_ID_SZ 1 -+#define PAD42_OE_MSK 0x00000001 -+#define PAD42_OE_I_MSK 0xfffffffe -+#define PAD42_OE_SFT 0 -+#define PAD42_OE_HI 0 -+#define PAD42_OE_SZ 1 -+#define PAD42_PE_MSK 0x00000002 -+#define PAD42_PE_I_MSK 0xfffffffd -+#define PAD42_PE_SFT 1 -+#define PAD42_PE_HI 1 -+#define PAD42_PE_SZ 1 -+#define PAD42_DS_MSK 0x00000004 -+#define PAD42_DS_I_MSK 0xfffffffb -+#define PAD42_DS_SFT 2 -+#define PAD42_DS_HI 2 -+#define PAD42_DS_SZ 1 -+#define PAD42_IE_MSK 0x00000008 -+#define PAD42_IE_I_MSK 0xfffffff7 -+#define PAD42_IE_SFT 3 -+#define PAD42_IE_HI 3 -+#define PAD42_IE_SZ 1 -+#define PAD42_SEL_I_MSK 0x00000030 -+#define PAD42_SEL_I_I_MSK 0xffffffcf -+#define PAD42_SEL_I_SFT 4 -+#define PAD42_SEL_I_HI 5 -+#define PAD42_SEL_I_SZ 2 -+#define PAD42_OD_MSK 0x00000100 -+#define PAD42_OD_I_MSK 0xfffffeff -+#define PAD42_OD_SFT 8 -+#define PAD42_OD_HI 8 -+#define PAD42_OD_SZ 1 -+#define PAD42_SEL_O_MSK 0x00001000 -+#define PAD42_SEL_O_I_MSK 0xffffefff -+#define PAD42_SEL_O_SFT 12 -+#define PAD42_SEL_O_HI 12 -+#define PAD42_SEL_O_SZ 1 -+#define TEST_11_ID_MSK 0x10000000 -+#define TEST_11_ID_I_MSK 0xefffffff -+#define TEST_11_ID_SFT 28 -+#define TEST_11_ID_HI 28 -+#define TEST_11_ID_SZ 1 -+#define PAD43_OE_MSK 0x00000001 -+#define PAD43_OE_I_MSK 0xfffffffe -+#define PAD43_OE_SFT 0 -+#define PAD43_OE_HI 0 -+#define PAD43_OE_SZ 1 -+#define PAD43_PE_MSK 0x00000002 -+#define PAD43_PE_I_MSK 0xfffffffd -+#define PAD43_PE_SFT 1 -+#define PAD43_PE_HI 1 -+#define PAD43_PE_SZ 1 -+#define PAD43_DS_MSK 0x00000004 -+#define PAD43_DS_I_MSK 0xfffffffb -+#define PAD43_DS_SFT 2 -+#define PAD43_DS_HI 2 -+#define PAD43_DS_SZ 1 -+#define PAD43_IE_MSK 0x00000008 -+#define PAD43_IE_I_MSK 0xfffffff7 -+#define PAD43_IE_SFT 3 -+#define PAD43_IE_HI 3 -+#define PAD43_IE_SZ 1 -+#define PAD43_SEL_I_MSK 0x00000030 -+#define PAD43_SEL_I_I_MSK 0xffffffcf -+#define PAD43_SEL_I_SFT 4 -+#define PAD43_SEL_I_HI 5 -+#define PAD43_SEL_I_SZ 2 -+#define PAD43_OD_MSK 0x00000100 -+#define PAD43_OD_I_MSK 0xfffffeff -+#define PAD43_OD_SFT 8 -+#define PAD43_OD_HI 8 -+#define PAD43_OD_SZ 1 -+#define PAD43_SEL_O_MSK 0x00001000 -+#define PAD43_SEL_O_I_MSK 0xffffefff -+#define PAD43_SEL_O_SFT 12 -+#define PAD43_SEL_O_HI 12 -+#define PAD43_SEL_O_SZ 1 -+#define TEST_12_ID_MSK 0x10000000 -+#define TEST_12_ID_I_MSK 0xefffffff -+#define TEST_12_ID_SFT 28 -+#define TEST_12_ID_HI 28 -+#define TEST_12_ID_SZ 1 -+#define PAD44_OE_MSK 0x00000001 -+#define PAD44_OE_I_MSK 0xfffffffe -+#define PAD44_OE_SFT 0 -+#define PAD44_OE_HI 0 -+#define PAD44_OE_SZ 1 -+#define PAD44_PE_MSK 0x00000002 -+#define PAD44_PE_I_MSK 0xfffffffd -+#define PAD44_PE_SFT 1 -+#define PAD44_PE_HI 1 -+#define PAD44_PE_SZ 1 -+#define PAD44_DS_MSK 0x00000004 -+#define PAD44_DS_I_MSK 0xfffffffb -+#define PAD44_DS_SFT 2 -+#define PAD44_DS_HI 2 -+#define PAD44_DS_SZ 1 -+#define PAD44_IE_MSK 0x00000008 -+#define PAD44_IE_I_MSK 0xfffffff7 -+#define PAD44_IE_SFT 3 -+#define PAD44_IE_HI 3 -+#define PAD44_IE_SZ 1 -+#define PAD44_SEL_I_MSK 0x00000030 -+#define PAD44_SEL_I_I_MSK 0xffffffcf -+#define PAD44_SEL_I_SFT 4 -+#define PAD44_SEL_I_HI 5 -+#define PAD44_SEL_I_SZ 2 -+#define PAD44_OD_MSK 0x00000100 -+#define PAD44_OD_I_MSK 0xfffffeff -+#define PAD44_OD_SFT 8 -+#define PAD44_OD_HI 8 -+#define PAD44_OD_SZ 1 -+#define PAD44_SEL_O_MSK 0x00003000 -+#define PAD44_SEL_O_I_MSK 0xffffcfff -+#define PAD44_SEL_O_SFT 12 -+#define PAD44_SEL_O_HI 13 -+#define PAD44_SEL_O_SZ 2 -+#define TEST_13_ID_MSK 0x10000000 -+#define TEST_13_ID_I_MSK 0xefffffff -+#define TEST_13_ID_SFT 28 -+#define TEST_13_ID_HI 28 -+#define TEST_13_ID_SZ 1 -+#define PAD45_OE_MSK 0x00000001 -+#define PAD45_OE_I_MSK 0xfffffffe -+#define PAD45_OE_SFT 0 -+#define PAD45_OE_HI 0 -+#define PAD45_OE_SZ 1 -+#define PAD45_PE_MSK 0x00000002 -+#define PAD45_PE_I_MSK 0xfffffffd -+#define PAD45_PE_SFT 1 -+#define PAD45_PE_HI 1 -+#define PAD45_PE_SZ 1 -+#define PAD45_DS_MSK 0x00000004 -+#define PAD45_DS_I_MSK 0xfffffffb -+#define PAD45_DS_SFT 2 -+#define PAD45_DS_HI 2 -+#define PAD45_DS_SZ 1 -+#define PAD45_IE_MSK 0x00000008 -+#define PAD45_IE_I_MSK 0xfffffff7 -+#define PAD45_IE_SFT 3 -+#define PAD45_IE_HI 3 -+#define PAD45_IE_SZ 1 -+#define PAD45_SEL_I_MSK 0x00000030 -+#define PAD45_SEL_I_I_MSK 0xffffffcf -+#define PAD45_SEL_I_SFT 4 -+#define PAD45_SEL_I_HI 5 -+#define PAD45_SEL_I_SZ 2 -+#define PAD45_OD_MSK 0x00000100 -+#define PAD45_OD_I_MSK 0xfffffeff -+#define PAD45_OD_SFT 8 -+#define PAD45_OD_HI 8 -+#define PAD45_OD_SZ 1 -+#define PAD45_SEL_O_MSK 0x00003000 -+#define PAD45_SEL_O_I_MSK 0xffffcfff -+#define PAD45_SEL_O_SFT 12 -+#define PAD45_SEL_O_HI 13 -+#define PAD45_SEL_O_SZ 2 -+#define TEST_14_ID_MSK 0x10000000 -+#define TEST_14_ID_I_MSK 0xefffffff -+#define TEST_14_ID_SFT 28 -+#define TEST_14_ID_HI 28 -+#define TEST_14_ID_SZ 1 -+#define PAD46_OE_MSK 0x00000001 -+#define PAD46_OE_I_MSK 0xfffffffe -+#define PAD46_OE_SFT 0 -+#define PAD46_OE_HI 0 -+#define PAD46_OE_SZ 1 -+#define PAD46_PE_MSK 0x00000002 -+#define PAD46_PE_I_MSK 0xfffffffd -+#define PAD46_PE_SFT 1 -+#define PAD46_PE_HI 1 -+#define PAD46_PE_SZ 1 -+#define PAD46_DS_MSK 0x00000004 -+#define PAD46_DS_I_MSK 0xfffffffb -+#define PAD46_DS_SFT 2 -+#define PAD46_DS_HI 2 -+#define PAD46_DS_SZ 1 -+#define PAD46_IE_MSK 0x00000008 -+#define PAD46_IE_I_MSK 0xfffffff7 -+#define PAD46_IE_SFT 3 -+#define PAD46_IE_HI 3 -+#define PAD46_IE_SZ 1 -+#define PAD46_SEL_I_MSK 0x00000030 -+#define PAD46_SEL_I_I_MSK 0xffffffcf -+#define PAD46_SEL_I_SFT 4 -+#define PAD46_SEL_I_HI 5 -+#define PAD46_SEL_I_SZ 2 -+#define PAD46_OD_MSK 0x00000100 -+#define PAD46_OD_I_MSK 0xfffffeff -+#define PAD46_OD_SFT 8 -+#define PAD46_OD_HI 8 -+#define PAD46_OD_SZ 1 -+#define PAD46_SEL_O_MSK 0x00003000 -+#define PAD46_SEL_O_I_MSK 0xffffcfff -+#define PAD46_SEL_O_SFT 12 -+#define PAD46_SEL_O_HI 13 -+#define PAD46_SEL_O_SZ 2 -+#define TEST_15_ID_MSK 0x10000000 -+#define TEST_15_ID_I_MSK 0xefffffff -+#define TEST_15_ID_SFT 28 -+#define TEST_15_ID_HI 28 -+#define TEST_15_ID_SZ 1 -+#define PAD47_OE_MSK 0x00000001 -+#define PAD47_OE_I_MSK 0xfffffffe -+#define PAD47_OE_SFT 0 -+#define PAD47_OE_HI 0 -+#define PAD47_OE_SZ 1 -+#define PAD47_PE_MSK 0x00000002 -+#define PAD47_PE_I_MSK 0xfffffffd -+#define PAD47_PE_SFT 1 -+#define PAD47_PE_HI 1 -+#define PAD47_PE_SZ 1 -+#define PAD47_DS_MSK 0x00000004 -+#define PAD47_DS_I_MSK 0xfffffffb -+#define PAD47_DS_SFT 2 -+#define PAD47_DS_HI 2 -+#define PAD47_DS_SZ 1 -+#define PAD47_SEL_I_MSK 0x00000030 -+#define PAD47_SEL_I_I_MSK 0xffffffcf -+#define PAD47_SEL_I_SFT 4 -+#define PAD47_SEL_I_HI 5 -+#define PAD47_SEL_I_SZ 2 -+#define PAD47_OD_MSK 0x00000100 -+#define PAD47_OD_I_MSK 0xfffffeff -+#define PAD47_OD_SFT 8 -+#define PAD47_OD_HI 8 -+#define PAD47_OD_SZ 1 -+#define PAD47_SEL_O_MSK 0x00003000 -+#define PAD47_SEL_O_I_MSK 0xffffcfff -+#define PAD47_SEL_O_SFT 12 -+#define PAD47_SEL_O_HI 13 -+#define PAD47_SEL_O_SZ 2 -+#define PAD47_SEL_OE_MSK 0x00100000 -+#define PAD47_SEL_OE_I_MSK 0xffefffff -+#define PAD47_SEL_OE_SFT 20 -+#define PAD47_SEL_OE_HI 20 -+#define PAD47_SEL_OE_SZ 1 -+#define GPIO_9_ID_MSK 0x10000000 -+#define GPIO_9_ID_I_MSK 0xefffffff -+#define GPIO_9_ID_SFT 28 -+#define GPIO_9_ID_HI 28 -+#define GPIO_9_ID_SZ 1 -+#define PAD48_OE_MSK 0x00000001 -+#define PAD48_OE_I_MSK 0xfffffffe -+#define PAD48_OE_SFT 0 -+#define PAD48_OE_HI 0 -+#define PAD48_OE_SZ 1 -+#define PAD48_PE_MSK 0x00000002 -+#define PAD48_PE_I_MSK 0xfffffffd -+#define PAD48_PE_SFT 1 -+#define PAD48_PE_HI 1 -+#define PAD48_PE_SZ 1 -+#define PAD48_DS_MSK 0x00000004 -+#define PAD48_DS_I_MSK 0xfffffffb -+#define PAD48_DS_SFT 2 -+#define PAD48_DS_HI 2 -+#define PAD48_DS_SZ 1 -+#define PAD48_IE_MSK 0x00000008 -+#define PAD48_IE_I_MSK 0xfffffff7 -+#define PAD48_IE_SFT 3 -+#define PAD48_IE_HI 3 -+#define PAD48_IE_SZ 1 -+#define PAD48_SEL_I_MSK 0x00000070 -+#define PAD48_SEL_I_I_MSK 0xffffff8f -+#define PAD48_SEL_I_SFT 4 -+#define PAD48_SEL_I_HI 6 -+#define PAD48_SEL_I_SZ 3 -+#define PAD48_OD_MSK 0x00000100 -+#define PAD48_OD_I_MSK 0xfffffeff -+#define PAD48_OD_SFT 8 -+#define PAD48_OD_HI 8 -+#define PAD48_OD_SZ 1 -+#define PAD48_PE_SEL_MSK 0x00000800 -+#define PAD48_PE_SEL_I_MSK 0xfffff7ff -+#define PAD48_PE_SEL_SFT 11 -+#define PAD48_PE_SEL_HI 11 -+#define PAD48_PE_SEL_SZ 1 -+#define PAD48_SEL_O_MSK 0x00003000 -+#define PAD48_SEL_O_I_MSK 0xffffcfff -+#define PAD48_SEL_O_SFT 12 -+#define PAD48_SEL_O_HI 13 -+#define PAD48_SEL_O_SZ 2 -+#define PAD48_SEL_OE_MSK 0x00100000 -+#define PAD48_SEL_OE_I_MSK 0xffefffff -+#define PAD48_SEL_OE_SFT 20 -+#define PAD48_SEL_OE_HI 20 -+#define PAD48_SEL_OE_SZ 1 -+#define GPIO_10_ID_MSK 0x10000000 -+#define GPIO_10_ID_I_MSK 0xefffffff -+#define GPIO_10_ID_SFT 28 -+#define GPIO_10_ID_HI 28 -+#define GPIO_10_ID_SZ 1 -+#define PAD49_OE_MSK 0x00000001 -+#define PAD49_OE_I_MSK 0xfffffffe -+#define PAD49_OE_SFT 0 -+#define PAD49_OE_HI 0 -+#define PAD49_OE_SZ 1 -+#define PAD49_PE_MSK 0x00000002 -+#define PAD49_PE_I_MSK 0xfffffffd -+#define PAD49_PE_SFT 1 -+#define PAD49_PE_HI 1 -+#define PAD49_PE_SZ 1 -+#define PAD49_DS_MSK 0x00000004 -+#define PAD49_DS_I_MSK 0xfffffffb -+#define PAD49_DS_SFT 2 -+#define PAD49_DS_HI 2 -+#define PAD49_DS_SZ 1 -+#define PAD49_IE_MSK 0x00000008 -+#define PAD49_IE_I_MSK 0xfffffff7 -+#define PAD49_IE_SFT 3 -+#define PAD49_IE_HI 3 -+#define PAD49_IE_SZ 1 -+#define PAD49_SEL_I_MSK 0x00000070 -+#define PAD49_SEL_I_I_MSK 0xffffff8f -+#define PAD49_SEL_I_SFT 4 -+#define PAD49_SEL_I_HI 6 -+#define PAD49_SEL_I_SZ 3 -+#define PAD49_OD_MSK 0x00000100 -+#define PAD49_OD_I_MSK 0xfffffeff -+#define PAD49_OD_SFT 8 -+#define PAD49_OD_HI 8 -+#define PAD49_OD_SZ 1 -+#define PAD49_SEL_O_MSK 0x00003000 -+#define PAD49_SEL_O_I_MSK 0xffffcfff -+#define PAD49_SEL_O_SFT 12 -+#define PAD49_SEL_O_HI 13 -+#define PAD49_SEL_O_SZ 2 -+#define PAD49_SEL_OE_MSK 0x00100000 -+#define PAD49_SEL_OE_I_MSK 0xffefffff -+#define PAD49_SEL_OE_SFT 20 -+#define PAD49_SEL_OE_HI 20 -+#define PAD49_SEL_OE_SZ 1 -+#define GPIO_11_ID_MSK 0x10000000 -+#define GPIO_11_ID_I_MSK 0xefffffff -+#define GPIO_11_ID_SFT 28 -+#define GPIO_11_ID_HI 28 -+#define GPIO_11_ID_SZ 1 -+#define PAD50_OE_MSK 0x00000001 -+#define PAD50_OE_I_MSK 0xfffffffe -+#define PAD50_OE_SFT 0 -+#define PAD50_OE_HI 0 -+#define PAD50_OE_SZ 1 -+#define PAD50_PE_MSK 0x00000002 -+#define PAD50_PE_I_MSK 0xfffffffd -+#define PAD50_PE_SFT 1 -+#define PAD50_PE_HI 1 -+#define PAD50_PE_SZ 1 -+#define PAD50_DS_MSK 0x00000004 -+#define PAD50_DS_I_MSK 0xfffffffb -+#define PAD50_DS_SFT 2 -+#define PAD50_DS_HI 2 -+#define PAD50_DS_SZ 1 -+#define PAD50_IE_MSK 0x00000008 -+#define PAD50_IE_I_MSK 0xfffffff7 -+#define PAD50_IE_SFT 3 -+#define PAD50_IE_HI 3 -+#define PAD50_IE_SZ 1 -+#define PAD50_SEL_I_MSK 0x00000070 -+#define PAD50_SEL_I_I_MSK 0xffffff8f -+#define PAD50_SEL_I_SFT 4 -+#define PAD50_SEL_I_HI 6 -+#define PAD50_SEL_I_SZ 3 -+#define PAD50_OD_MSK 0x00000100 -+#define PAD50_OD_I_MSK 0xfffffeff -+#define PAD50_OD_SFT 8 -+#define PAD50_OD_HI 8 -+#define PAD50_OD_SZ 1 -+#define PAD50_SEL_O_MSK 0x00003000 -+#define PAD50_SEL_O_I_MSK 0xffffcfff -+#define PAD50_SEL_O_SFT 12 -+#define PAD50_SEL_O_HI 13 -+#define PAD50_SEL_O_SZ 2 -+#define PAD50_SEL_OE_MSK 0x00100000 -+#define PAD50_SEL_OE_I_MSK 0xffefffff -+#define PAD50_SEL_OE_SFT 20 -+#define PAD50_SEL_OE_HI 20 -+#define PAD50_SEL_OE_SZ 1 -+#define GPIO_12_ID_MSK 0x10000000 -+#define GPIO_12_ID_I_MSK 0xefffffff -+#define GPIO_12_ID_SFT 28 -+#define GPIO_12_ID_HI 28 -+#define GPIO_12_ID_SZ 1 -+#define PAD51_OE_MSK 0x00000001 -+#define PAD51_OE_I_MSK 0xfffffffe -+#define PAD51_OE_SFT 0 -+#define PAD51_OE_HI 0 -+#define PAD51_OE_SZ 1 -+#define PAD51_PE_MSK 0x00000002 -+#define PAD51_PE_I_MSK 0xfffffffd -+#define PAD51_PE_SFT 1 -+#define PAD51_PE_HI 1 -+#define PAD51_PE_SZ 1 -+#define PAD51_DS_MSK 0x00000004 -+#define PAD51_DS_I_MSK 0xfffffffb -+#define PAD51_DS_SFT 2 -+#define PAD51_DS_HI 2 -+#define PAD51_DS_SZ 1 -+#define PAD51_IE_MSK 0x00000008 -+#define PAD51_IE_I_MSK 0xfffffff7 -+#define PAD51_IE_SFT 3 -+#define PAD51_IE_HI 3 -+#define PAD51_IE_SZ 1 -+#define PAD51_SEL_I_MSK 0x00000030 -+#define PAD51_SEL_I_I_MSK 0xffffffcf -+#define PAD51_SEL_I_SFT 4 -+#define PAD51_SEL_I_HI 5 -+#define PAD51_SEL_I_SZ 2 -+#define PAD51_OD_MSK 0x00000100 -+#define PAD51_OD_I_MSK 0xfffffeff -+#define PAD51_OD_SFT 8 -+#define PAD51_OD_HI 8 -+#define PAD51_OD_SZ 1 -+#define PAD51_SEL_O_MSK 0x00001000 -+#define PAD51_SEL_O_I_MSK 0xffffefff -+#define PAD51_SEL_O_SFT 12 -+#define PAD51_SEL_O_HI 12 -+#define PAD51_SEL_O_SZ 1 -+#define PAD51_SEL_OE_MSK 0x00100000 -+#define PAD51_SEL_OE_I_MSK 0xffefffff -+#define PAD51_SEL_OE_SFT 20 -+#define PAD51_SEL_OE_HI 20 -+#define PAD51_SEL_OE_SZ 1 -+#define GPIO_13_ID_MSK 0x10000000 -+#define GPIO_13_ID_I_MSK 0xefffffff -+#define GPIO_13_ID_SFT 28 -+#define GPIO_13_ID_HI 28 -+#define GPIO_13_ID_SZ 1 -+#define PAD52_OE_MSK 0x00000001 -+#define PAD52_OE_I_MSK 0xfffffffe -+#define PAD52_OE_SFT 0 -+#define PAD52_OE_HI 0 -+#define PAD52_OE_SZ 1 -+#define PAD52_PE_MSK 0x00000002 -+#define PAD52_PE_I_MSK 0xfffffffd -+#define PAD52_PE_SFT 1 -+#define PAD52_PE_HI 1 -+#define PAD52_PE_SZ 1 -+#define PAD52_DS_MSK 0x00000004 -+#define PAD52_DS_I_MSK 0xfffffffb -+#define PAD52_DS_SFT 2 -+#define PAD52_DS_HI 2 -+#define PAD52_DS_SZ 1 -+#define PAD52_SEL_I_MSK 0x00000030 -+#define PAD52_SEL_I_I_MSK 0xffffffcf -+#define PAD52_SEL_I_SFT 4 -+#define PAD52_SEL_I_HI 5 -+#define PAD52_SEL_I_SZ 2 -+#define PAD52_OD_MSK 0x00000100 -+#define PAD52_OD_I_MSK 0xfffffeff -+#define PAD52_OD_SFT 8 -+#define PAD52_OD_HI 8 -+#define PAD52_OD_SZ 1 -+#define PAD52_SEL_O_MSK 0x00001000 -+#define PAD52_SEL_O_I_MSK 0xffffefff -+#define PAD52_SEL_O_SFT 12 -+#define PAD52_SEL_O_HI 12 -+#define PAD52_SEL_O_SZ 1 -+#define PAD52_SEL_OE_MSK 0x00100000 -+#define PAD52_SEL_OE_I_MSK 0xffefffff -+#define PAD52_SEL_OE_SFT 20 -+#define PAD52_SEL_OE_HI 20 -+#define PAD52_SEL_OE_SZ 1 -+#define GPIO_14_ID_MSK 0x10000000 -+#define GPIO_14_ID_I_MSK 0xefffffff -+#define GPIO_14_ID_SFT 28 -+#define GPIO_14_ID_HI 28 -+#define GPIO_14_ID_SZ 1 -+#define PAD53_OE_MSK 0x00000001 -+#define PAD53_OE_I_MSK 0xfffffffe -+#define PAD53_OE_SFT 0 -+#define PAD53_OE_HI 0 -+#define PAD53_OE_SZ 1 -+#define PAD53_PE_MSK 0x00000002 -+#define PAD53_PE_I_MSK 0xfffffffd -+#define PAD53_PE_SFT 1 -+#define PAD53_PE_HI 1 -+#define PAD53_PE_SZ 1 -+#define PAD53_DS_MSK 0x00000004 -+#define PAD53_DS_I_MSK 0xfffffffb -+#define PAD53_DS_SFT 2 -+#define PAD53_DS_HI 2 -+#define PAD53_DS_SZ 1 -+#define PAD53_IE_MSK 0x00000008 -+#define PAD53_IE_I_MSK 0xfffffff7 -+#define PAD53_IE_SFT 3 -+#define PAD53_IE_HI 3 -+#define PAD53_IE_SZ 1 -+#define PAD53_SEL_I_MSK 0x00000030 -+#define PAD53_SEL_I_I_MSK 0xffffffcf -+#define PAD53_SEL_I_SFT 4 -+#define PAD53_SEL_I_HI 5 -+#define PAD53_SEL_I_SZ 2 -+#define PAD53_OD_MSK 0x00000100 -+#define PAD53_OD_I_MSK 0xfffffeff -+#define PAD53_OD_SFT 8 -+#define PAD53_OD_HI 8 -+#define PAD53_OD_SZ 1 -+#define PAD53_SEL_O_MSK 0x00001000 -+#define PAD53_SEL_O_I_MSK 0xffffefff -+#define PAD53_SEL_O_SFT 12 -+#define PAD53_SEL_O_HI 12 -+#define PAD53_SEL_O_SZ 1 -+#define JTAG_TMS_ID_MSK 0x10000000 -+#define JTAG_TMS_ID_I_MSK 0xefffffff -+#define JTAG_TMS_ID_SFT 28 -+#define JTAG_TMS_ID_HI 28 -+#define JTAG_TMS_ID_SZ 1 -+#define PAD54_OE_MSK 0x00000001 -+#define PAD54_OE_I_MSK 0xfffffffe -+#define PAD54_OE_SFT 0 -+#define PAD54_OE_HI 0 -+#define PAD54_OE_SZ 1 -+#define PAD54_PE_MSK 0x00000002 -+#define PAD54_PE_I_MSK 0xfffffffd -+#define PAD54_PE_SFT 1 -+#define PAD54_PE_HI 1 -+#define PAD54_PE_SZ 1 -+#define PAD54_DS_MSK 0x00000004 -+#define PAD54_DS_I_MSK 0xfffffffb -+#define PAD54_DS_SFT 2 -+#define PAD54_DS_HI 2 -+#define PAD54_DS_SZ 1 -+#define PAD54_OD_MSK 0x00000100 -+#define PAD54_OD_I_MSK 0xfffffeff -+#define PAD54_OD_SFT 8 -+#define PAD54_OD_HI 8 -+#define PAD54_OD_SZ 1 -+#define PAD54_SEL_O_MSK 0x00003000 -+#define PAD54_SEL_O_I_MSK 0xffffcfff -+#define PAD54_SEL_O_SFT 12 -+#define PAD54_SEL_O_HI 13 -+#define PAD54_SEL_O_SZ 2 -+#define JTAG_TCK_ID_MSK 0x10000000 -+#define JTAG_TCK_ID_I_MSK 0xefffffff -+#define JTAG_TCK_ID_SFT 28 -+#define JTAG_TCK_ID_HI 28 -+#define JTAG_TCK_ID_SZ 1 -+#define PAD56_PE_MSK 0x00000002 -+#define PAD56_PE_I_MSK 0xfffffffd -+#define PAD56_PE_SFT 1 -+#define PAD56_PE_HI 1 -+#define PAD56_PE_SZ 1 -+#define PAD56_DS_MSK 0x00000004 -+#define PAD56_DS_I_MSK 0xfffffffb -+#define PAD56_DS_SFT 2 -+#define PAD56_DS_HI 2 -+#define PAD56_DS_SZ 1 -+#define PAD56_SEL_I_MSK 0x00000010 -+#define PAD56_SEL_I_I_MSK 0xffffffef -+#define PAD56_SEL_I_SFT 4 -+#define PAD56_SEL_I_HI 4 -+#define PAD56_SEL_I_SZ 1 -+#define PAD56_OD_MSK 0x00000100 -+#define PAD56_OD_I_MSK 0xfffffeff -+#define PAD56_OD_SFT 8 -+#define PAD56_OD_HI 8 -+#define PAD56_OD_SZ 1 -+#define JTAG_TDI_ID_MSK 0x10000000 -+#define JTAG_TDI_ID_I_MSK 0xefffffff -+#define JTAG_TDI_ID_SFT 28 -+#define JTAG_TDI_ID_HI 28 -+#define JTAG_TDI_ID_SZ 1 -+#define PAD57_OE_MSK 0x00000001 -+#define PAD57_OE_I_MSK 0xfffffffe -+#define PAD57_OE_SFT 0 -+#define PAD57_OE_HI 0 -+#define PAD57_OE_SZ 1 -+#define PAD57_PE_MSK 0x00000002 -+#define PAD57_PE_I_MSK 0xfffffffd -+#define PAD57_PE_SFT 1 -+#define PAD57_PE_HI 1 -+#define PAD57_PE_SZ 1 -+#define PAD57_DS_MSK 0x00000004 -+#define PAD57_DS_I_MSK 0xfffffffb -+#define PAD57_DS_SFT 2 -+#define PAD57_DS_HI 2 -+#define PAD57_DS_SZ 1 -+#define PAD57_IE_MSK 0x00000008 -+#define PAD57_IE_I_MSK 0xfffffff7 -+#define PAD57_IE_SFT 3 -+#define PAD57_IE_HI 3 -+#define PAD57_IE_SZ 1 -+#define PAD57_SEL_I_MSK 0x00000030 -+#define PAD57_SEL_I_I_MSK 0xffffffcf -+#define PAD57_SEL_I_SFT 4 -+#define PAD57_SEL_I_HI 5 -+#define PAD57_SEL_I_SZ 2 -+#define PAD57_OD_MSK 0x00000100 -+#define PAD57_OD_I_MSK 0xfffffeff -+#define PAD57_OD_SFT 8 -+#define PAD57_OD_HI 8 -+#define PAD57_OD_SZ 1 -+#define PAD57_SEL_O_MSK 0x00003000 -+#define PAD57_SEL_O_I_MSK 0xffffcfff -+#define PAD57_SEL_O_SFT 12 -+#define PAD57_SEL_O_HI 13 -+#define PAD57_SEL_O_SZ 2 -+#define PAD57_SEL_OE_MSK 0x00100000 -+#define PAD57_SEL_OE_I_MSK 0xffefffff -+#define PAD57_SEL_OE_SFT 20 -+#define PAD57_SEL_OE_HI 20 -+#define PAD57_SEL_OE_SZ 1 -+#define JTAG_TDO_ID_MSK 0x10000000 -+#define JTAG_TDO_ID_I_MSK 0xefffffff -+#define JTAG_TDO_ID_SFT 28 -+#define JTAG_TDO_ID_HI 28 -+#define JTAG_TDO_ID_SZ 1 -+#define PAD58_OE_MSK 0x00000001 -+#define PAD58_OE_I_MSK 0xfffffffe -+#define PAD58_OE_SFT 0 -+#define PAD58_OE_HI 0 -+#define PAD58_OE_SZ 1 -+#define PAD58_PE_MSK 0x00000002 -+#define PAD58_PE_I_MSK 0xfffffffd -+#define PAD58_PE_SFT 1 -+#define PAD58_PE_HI 1 -+#define PAD58_PE_SZ 1 -+#define PAD58_DS_MSK 0x00000004 -+#define PAD58_DS_I_MSK 0xfffffffb -+#define PAD58_DS_SFT 2 -+#define PAD58_DS_HI 2 -+#define PAD58_DS_SZ 1 -+#define PAD58_IE_MSK 0x00000008 -+#define PAD58_IE_I_MSK 0xfffffff7 -+#define PAD58_IE_SFT 3 -+#define PAD58_IE_HI 3 -+#define PAD58_IE_SZ 1 -+#define PAD58_SEL_I_MSK 0x00000030 -+#define PAD58_SEL_I_I_MSK 0xffffffcf -+#define PAD58_SEL_I_SFT 4 -+#define PAD58_SEL_I_HI 5 -+#define PAD58_SEL_I_SZ 2 -+#define PAD58_OD_MSK 0x00000100 -+#define PAD58_OD_I_MSK 0xfffffeff -+#define PAD58_OD_SFT 8 -+#define PAD58_OD_HI 8 -+#define PAD58_OD_SZ 1 -+#define PAD58_SEL_O_MSK 0x00001000 -+#define PAD58_SEL_O_I_MSK 0xffffefff -+#define PAD58_SEL_O_SFT 12 -+#define PAD58_SEL_O_HI 12 -+#define PAD58_SEL_O_SZ 1 -+#define TEST_16_ID_MSK 0x10000000 -+#define TEST_16_ID_I_MSK 0xefffffff -+#define TEST_16_ID_SFT 28 -+#define TEST_16_ID_HI 28 -+#define TEST_16_ID_SZ 1 -+#define PAD59_OE_MSK 0x00000001 -+#define PAD59_OE_I_MSK 0xfffffffe -+#define PAD59_OE_SFT 0 -+#define PAD59_OE_HI 0 -+#define PAD59_OE_SZ 1 -+#define PAD59_PE_MSK 0x00000002 -+#define PAD59_PE_I_MSK 0xfffffffd -+#define PAD59_PE_SFT 1 -+#define PAD59_PE_HI 1 -+#define PAD59_PE_SZ 1 -+#define PAD59_DS_MSK 0x00000004 -+#define PAD59_DS_I_MSK 0xfffffffb -+#define PAD59_DS_SFT 2 -+#define PAD59_DS_HI 2 -+#define PAD59_DS_SZ 1 -+#define PAD59_IE_MSK 0x00000008 -+#define PAD59_IE_I_MSK 0xfffffff7 -+#define PAD59_IE_SFT 3 -+#define PAD59_IE_HI 3 -+#define PAD59_IE_SZ 1 -+#define PAD59_SEL_I_MSK 0x00000030 -+#define PAD59_SEL_I_I_MSK 0xffffffcf -+#define PAD59_SEL_I_SFT 4 -+#define PAD59_SEL_I_HI 5 -+#define PAD59_SEL_I_SZ 2 -+#define PAD59_OD_MSK 0x00000100 -+#define PAD59_OD_I_MSK 0xfffffeff -+#define PAD59_OD_SFT 8 -+#define PAD59_OD_HI 8 -+#define PAD59_OD_SZ 1 -+#define PAD59_SEL_O_MSK 0x00001000 -+#define PAD59_SEL_O_I_MSK 0xffffefff -+#define PAD59_SEL_O_SFT 12 -+#define PAD59_SEL_O_HI 12 -+#define PAD59_SEL_O_SZ 1 -+#define TEST_17_ID_MSK 0x10000000 -+#define TEST_17_ID_I_MSK 0xefffffff -+#define TEST_17_ID_SFT 28 -+#define TEST_17_ID_HI 28 -+#define TEST_17_ID_SZ 1 -+#define PAD60_OE_MSK 0x00000001 -+#define PAD60_OE_I_MSK 0xfffffffe -+#define PAD60_OE_SFT 0 -+#define PAD60_OE_HI 0 -+#define PAD60_OE_SZ 1 -+#define PAD60_PE_MSK 0x00000002 -+#define PAD60_PE_I_MSK 0xfffffffd -+#define PAD60_PE_SFT 1 -+#define PAD60_PE_HI 1 -+#define PAD60_PE_SZ 1 -+#define PAD60_DS_MSK 0x00000004 -+#define PAD60_DS_I_MSK 0xfffffffb -+#define PAD60_DS_SFT 2 -+#define PAD60_DS_HI 2 -+#define PAD60_DS_SZ 1 -+#define PAD60_IE_MSK 0x00000008 -+#define PAD60_IE_I_MSK 0xfffffff7 -+#define PAD60_IE_SFT 3 -+#define PAD60_IE_HI 3 -+#define PAD60_IE_SZ 1 -+#define PAD60_SEL_I_MSK 0x00000030 -+#define PAD60_SEL_I_I_MSK 0xffffffcf -+#define PAD60_SEL_I_SFT 4 -+#define PAD60_SEL_I_HI 5 -+#define PAD60_SEL_I_SZ 2 -+#define PAD60_OD_MSK 0x00000100 -+#define PAD60_OD_I_MSK 0xfffffeff -+#define PAD60_OD_SFT 8 -+#define PAD60_OD_HI 8 -+#define PAD60_OD_SZ 1 -+#define PAD60_SEL_O_MSK 0x00001000 -+#define PAD60_SEL_O_I_MSK 0xffffefff -+#define PAD60_SEL_O_SFT 12 -+#define PAD60_SEL_O_HI 12 -+#define PAD60_SEL_O_SZ 1 -+#define TEST_18_ID_MSK 0x10000000 -+#define TEST_18_ID_I_MSK 0xefffffff -+#define TEST_18_ID_SFT 28 -+#define TEST_18_ID_HI 28 -+#define TEST_18_ID_SZ 1 -+#define PAD61_OE_MSK 0x00000001 -+#define PAD61_OE_I_MSK 0xfffffffe -+#define PAD61_OE_SFT 0 -+#define PAD61_OE_HI 0 -+#define PAD61_OE_SZ 1 -+#define PAD61_PE_MSK 0x00000002 -+#define PAD61_PE_I_MSK 0xfffffffd -+#define PAD61_PE_SFT 1 -+#define PAD61_PE_HI 1 -+#define PAD61_PE_SZ 1 -+#define PAD61_DS_MSK 0x00000004 -+#define PAD61_DS_I_MSK 0xfffffffb -+#define PAD61_DS_SFT 2 -+#define PAD61_DS_HI 2 -+#define PAD61_DS_SZ 1 -+#define PAD61_IE_MSK 0x00000008 -+#define PAD61_IE_I_MSK 0xfffffff7 -+#define PAD61_IE_SFT 3 -+#define PAD61_IE_HI 3 -+#define PAD61_IE_SZ 1 -+#define PAD61_SEL_I_MSK 0x00000010 -+#define PAD61_SEL_I_I_MSK 0xffffffef -+#define PAD61_SEL_I_SFT 4 -+#define PAD61_SEL_I_HI 4 -+#define PAD61_SEL_I_SZ 1 -+#define PAD61_OD_MSK 0x00000100 -+#define PAD61_OD_I_MSK 0xfffffeff -+#define PAD61_OD_SFT 8 -+#define PAD61_OD_HI 8 -+#define PAD61_OD_SZ 1 -+#define PAD61_SEL_O_MSK 0x00003000 -+#define PAD61_SEL_O_I_MSK 0xffffcfff -+#define PAD61_SEL_O_SFT 12 -+#define PAD61_SEL_O_HI 13 -+#define PAD61_SEL_O_SZ 2 -+#define TEST_19_ID_MSK 0x10000000 -+#define TEST_19_ID_I_MSK 0xefffffff -+#define TEST_19_ID_SFT 28 -+#define TEST_19_ID_HI 28 -+#define TEST_19_ID_SZ 1 -+#define PAD62_OE_MSK 0x00000001 -+#define PAD62_OE_I_MSK 0xfffffffe -+#define PAD62_OE_SFT 0 -+#define PAD62_OE_HI 0 -+#define PAD62_OE_SZ 1 -+#define PAD62_PE_MSK 0x00000002 -+#define PAD62_PE_I_MSK 0xfffffffd -+#define PAD62_PE_SFT 1 -+#define PAD62_PE_HI 1 -+#define PAD62_PE_SZ 1 -+#define PAD62_DS_MSK 0x00000004 -+#define PAD62_DS_I_MSK 0xfffffffb -+#define PAD62_DS_SFT 2 -+#define PAD62_DS_HI 2 -+#define PAD62_DS_SZ 1 -+#define PAD62_IE_MSK 0x00000008 -+#define PAD62_IE_I_MSK 0xfffffff7 -+#define PAD62_IE_SFT 3 -+#define PAD62_IE_HI 3 -+#define PAD62_IE_SZ 1 -+#define PAD62_SEL_I_MSK 0x00000010 -+#define PAD62_SEL_I_I_MSK 0xffffffef -+#define PAD62_SEL_I_SFT 4 -+#define PAD62_SEL_I_HI 4 -+#define PAD62_SEL_I_SZ 1 -+#define PAD62_OD_MSK 0x00000100 -+#define PAD62_OD_I_MSK 0xfffffeff -+#define PAD62_OD_SFT 8 -+#define PAD62_OD_HI 8 -+#define PAD62_OD_SZ 1 -+#define PAD62_SEL_O_MSK 0x00001000 -+#define PAD62_SEL_O_I_MSK 0xffffefff -+#define PAD62_SEL_O_SFT 12 -+#define PAD62_SEL_O_HI 12 -+#define PAD62_SEL_O_SZ 1 -+#define TEST_20_ID_MSK 0x10000000 -+#define TEST_20_ID_I_MSK 0xefffffff -+#define TEST_20_ID_SFT 28 -+#define TEST_20_ID_HI 28 -+#define TEST_20_ID_SZ 1 -+#define PAD64_OE_MSK 0x00000001 -+#define PAD64_OE_I_MSK 0xfffffffe -+#define PAD64_OE_SFT 0 -+#define PAD64_OE_HI 0 -+#define PAD64_OE_SZ 1 -+#define PAD64_PE_MSK 0x00000002 -+#define PAD64_PE_I_MSK 0xfffffffd -+#define PAD64_PE_SFT 1 -+#define PAD64_PE_HI 1 -+#define PAD64_PE_SZ 1 -+#define PAD64_DS_MSK 0x00000004 -+#define PAD64_DS_I_MSK 0xfffffffb -+#define PAD64_DS_SFT 2 -+#define PAD64_DS_HI 2 -+#define PAD64_DS_SZ 1 -+#define PAD64_IE_MSK 0x00000008 -+#define PAD64_IE_I_MSK 0xfffffff7 -+#define PAD64_IE_SFT 3 -+#define PAD64_IE_HI 3 -+#define PAD64_IE_SZ 1 -+#define PAD64_SEL_I_MSK 0x00000070 -+#define PAD64_SEL_I_I_MSK 0xffffff8f -+#define PAD64_SEL_I_SFT 4 -+#define PAD64_SEL_I_HI 6 -+#define PAD64_SEL_I_SZ 3 -+#define PAD64_OD_MSK 0x00000100 -+#define PAD64_OD_I_MSK 0xfffffeff -+#define PAD64_OD_SFT 8 -+#define PAD64_OD_HI 8 -+#define PAD64_OD_SZ 1 -+#define PAD64_SEL_O_MSK 0x00003000 -+#define PAD64_SEL_O_I_MSK 0xffffcfff -+#define PAD64_SEL_O_SFT 12 -+#define PAD64_SEL_O_HI 13 -+#define PAD64_SEL_O_SZ 2 -+#define PAD64_SEL_OE_MSK 0x00100000 -+#define PAD64_SEL_OE_I_MSK 0xffefffff -+#define PAD64_SEL_OE_SFT 20 -+#define PAD64_SEL_OE_HI 20 -+#define PAD64_SEL_OE_SZ 1 -+#define GPIO_15_IP_ID_MSK 0x10000000 -+#define GPIO_15_IP_ID_I_MSK 0xefffffff -+#define GPIO_15_IP_ID_SFT 28 -+#define GPIO_15_IP_ID_HI 28 -+#define GPIO_15_IP_ID_SZ 1 -+#define PAD65_OE_MSK 0x00000001 -+#define PAD65_OE_I_MSK 0xfffffffe -+#define PAD65_OE_SFT 0 -+#define PAD65_OE_HI 0 -+#define PAD65_OE_SZ 1 -+#define PAD65_PE_MSK 0x00000002 -+#define PAD65_PE_I_MSK 0xfffffffd -+#define PAD65_PE_SFT 1 -+#define PAD65_PE_HI 1 -+#define PAD65_PE_SZ 1 -+#define PAD65_DS_MSK 0x00000004 -+#define PAD65_DS_I_MSK 0xfffffffb -+#define PAD65_DS_SFT 2 -+#define PAD65_DS_HI 2 -+#define PAD65_DS_SZ 1 -+#define PAD65_IE_MSK 0x00000008 -+#define PAD65_IE_I_MSK 0xfffffff7 -+#define PAD65_IE_SFT 3 -+#define PAD65_IE_HI 3 -+#define PAD65_IE_SZ 1 -+#define PAD65_SEL_I_MSK 0x00000070 -+#define PAD65_SEL_I_I_MSK 0xffffff8f -+#define PAD65_SEL_I_SFT 4 -+#define PAD65_SEL_I_HI 6 -+#define PAD65_SEL_I_SZ 3 -+#define PAD65_OD_MSK 0x00000100 -+#define PAD65_OD_I_MSK 0xfffffeff -+#define PAD65_OD_SFT 8 -+#define PAD65_OD_HI 8 -+#define PAD65_OD_SZ 1 -+#define PAD65_SEL_O_MSK 0x00001000 -+#define PAD65_SEL_O_I_MSK 0xffffefff -+#define PAD65_SEL_O_SFT 12 -+#define PAD65_SEL_O_HI 12 -+#define PAD65_SEL_O_SZ 1 -+#define GPIO_TEST_7_IN_ID_MSK 0x10000000 -+#define GPIO_TEST_7_IN_ID_I_MSK 0xefffffff -+#define GPIO_TEST_7_IN_ID_SFT 28 -+#define GPIO_TEST_7_IN_ID_HI 28 -+#define GPIO_TEST_7_IN_ID_SZ 1 -+#define PAD66_OE_MSK 0x00000001 -+#define PAD66_OE_I_MSK 0xfffffffe -+#define PAD66_OE_SFT 0 -+#define PAD66_OE_HI 0 -+#define PAD66_OE_SZ 1 -+#define PAD66_PE_MSK 0x00000002 -+#define PAD66_PE_I_MSK 0xfffffffd -+#define PAD66_PE_SFT 1 -+#define PAD66_PE_HI 1 -+#define PAD66_PE_SZ 1 -+#define PAD66_DS_MSK 0x00000004 -+#define PAD66_DS_I_MSK 0xfffffffb -+#define PAD66_DS_SFT 2 -+#define PAD66_DS_HI 2 -+#define PAD66_DS_SZ 1 -+#define PAD66_IE_MSK 0x00000008 -+#define PAD66_IE_I_MSK 0xfffffff7 -+#define PAD66_IE_SFT 3 -+#define PAD66_IE_HI 3 -+#define PAD66_IE_SZ 1 -+#define PAD66_SEL_I_MSK 0x00000030 -+#define PAD66_SEL_I_I_MSK 0xffffffcf -+#define PAD66_SEL_I_SFT 4 -+#define PAD66_SEL_I_HI 5 -+#define PAD66_SEL_I_SZ 2 -+#define PAD66_OD_MSK 0x00000100 -+#define PAD66_OD_I_MSK 0xfffffeff -+#define PAD66_OD_SFT 8 -+#define PAD66_OD_HI 8 -+#define PAD66_OD_SZ 1 -+#define PAD66_SEL_O_MSK 0x00003000 -+#define PAD66_SEL_O_I_MSK 0xffffcfff -+#define PAD66_SEL_O_SFT 12 -+#define PAD66_SEL_O_HI 13 -+#define PAD66_SEL_O_SZ 2 -+#define GPIO_17_QP_ID_MSK 0x10000000 -+#define GPIO_17_QP_ID_I_MSK 0xefffffff -+#define GPIO_17_QP_ID_SFT 28 -+#define GPIO_17_QP_ID_HI 28 -+#define GPIO_17_QP_ID_SZ 1 -+#define PAD68_OE_MSK 0x00000001 -+#define PAD68_OE_I_MSK 0xfffffffe -+#define PAD68_OE_SFT 0 -+#define PAD68_OE_HI 0 -+#define PAD68_OE_SZ 1 -+#define PAD68_PE_MSK 0x00000002 -+#define PAD68_PE_I_MSK 0xfffffffd -+#define PAD68_PE_SFT 1 -+#define PAD68_PE_HI 1 -+#define PAD68_PE_SZ 1 -+#define PAD68_DS_MSK 0x00000004 -+#define PAD68_DS_I_MSK 0xfffffffb -+#define PAD68_DS_SFT 2 -+#define PAD68_DS_HI 2 -+#define PAD68_DS_SZ 1 -+#define PAD68_IE_MSK 0x00000008 -+#define PAD68_IE_I_MSK 0xfffffff7 -+#define PAD68_IE_SFT 3 -+#define PAD68_IE_HI 3 -+#define PAD68_IE_SZ 1 -+#define PAD68_OD_MSK 0x00000100 -+#define PAD68_OD_I_MSK 0xfffffeff -+#define PAD68_OD_SFT 8 -+#define PAD68_OD_HI 8 -+#define PAD68_OD_SZ 1 -+#define PAD68_SEL_O_MSK 0x00001000 -+#define PAD68_SEL_O_I_MSK 0xffffefff -+#define PAD68_SEL_O_SFT 12 -+#define PAD68_SEL_O_HI 12 -+#define PAD68_SEL_O_SZ 1 -+#define GPIO_19_ID_MSK 0x10000000 -+#define GPIO_19_ID_I_MSK 0xefffffff -+#define GPIO_19_ID_SFT 28 -+#define GPIO_19_ID_HI 28 -+#define GPIO_19_ID_SZ 1 -+#define PAD67_OE_MSK 0x00000001 -+#define PAD67_OE_I_MSK 0xfffffffe -+#define PAD67_OE_SFT 0 -+#define PAD67_OE_HI 0 -+#define PAD67_OE_SZ 1 -+#define PAD67_PE_MSK 0x00000002 -+#define PAD67_PE_I_MSK 0xfffffffd -+#define PAD67_PE_SFT 1 -+#define PAD67_PE_HI 1 -+#define PAD67_PE_SZ 1 -+#define PAD67_DS_MSK 0x00000004 -+#define PAD67_DS_I_MSK 0xfffffffb -+#define PAD67_DS_SFT 2 -+#define PAD67_DS_HI 2 -+#define PAD67_DS_SZ 1 -+#define PAD67_IE_MSK 0x00000008 -+#define PAD67_IE_I_MSK 0xfffffff7 -+#define PAD67_IE_SFT 3 -+#define PAD67_IE_HI 3 -+#define PAD67_IE_SZ 1 -+#define PAD67_SEL_I_MSK 0x00000070 -+#define PAD67_SEL_I_I_MSK 0xffffff8f -+#define PAD67_SEL_I_SFT 4 -+#define PAD67_SEL_I_HI 6 -+#define PAD67_SEL_I_SZ 3 -+#define PAD67_OD_MSK 0x00000100 -+#define PAD67_OD_I_MSK 0xfffffeff -+#define PAD67_OD_SFT 8 -+#define PAD67_OD_HI 8 -+#define PAD67_OD_SZ 1 -+#define PAD67_SEL_O_MSK 0x00003000 -+#define PAD67_SEL_O_I_MSK 0xffffcfff -+#define PAD67_SEL_O_SFT 12 -+#define PAD67_SEL_O_HI 13 -+#define PAD67_SEL_O_SZ 2 -+#define GPIO_TEST_8_QN_ID_MSK 0x10000000 -+#define GPIO_TEST_8_QN_ID_I_MSK 0xefffffff -+#define GPIO_TEST_8_QN_ID_SFT 28 -+#define GPIO_TEST_8_QN_ID_HI 28 -+#define GPIO_TEST_8_QN_ID_SZ 1 -+#define PAD69_OE_MSK 0x00000001 -+#define PAD69_OE_I_MSK 0xfffffffe -+#define PAD69_OE_SFT 0 -+#define PAD69_OE_HI 0 -+#define PAD69_OE_SZ 1 -+#define PAD69_PE_MSK 0x00000002 -+#define PAD69_PE_I_MSK 0xfffffffd -+#define PAD69_PE_SFT 1 -+#define PAD69_PE_HI 1 -+#define PAD69_PE_SZ 1 -+#define PAD69_DS_MSK 0x00000004 -+#define PAD69_DS_I_MSK 0xfffffffb -+#define PAD69_DS_SFT 2 -+#define PAD69_DS_HI 2 -+#define PAD69_DS_SZ 1 -+#define PAD69_IE_MSK 0x00000008 -+#define PAD69_IE_I_MSK 0xfffffff7 -+#define PAD69_IE_SFT 3 -+#define PAD69_IE_HI 3 -+#define PAD69_IE_SZ 1 -+#define PAD69_SEL_I_MSK 0x00000030 -+#define PAD69_SEL_I_I_MSK 0xffffffcf -+#define PAD69_SEL_I_SFT 4 -+#define PAD69_SEL_I_HI 5 -+#define PAD69_SEL_I_SZ 2 -+#define PAD69_OD_MSK 0x00000100 -+#define PAD69_OD_I_MSK 0xfffffeff -+#define PAD69_OD_SFT 8 -+#define PAD69_OD_HI 8 -+#define PAD69_OD_SZ 1 -+#define PAD69_SEL_O_MSK 0x00001000 -+#define PAD69_SEL_O_I_MSK 0xffffefff -+#define PAD69_SEL_O_SFT 12 -+#define PAD69_SEL_O_HI 12 -+#define PAD69_SEL_O_SZ 1 -+#define STRAP2_MSK 0x08000000 -+#define STRAP2_I_MSK 0xf7ffffff -+#define STRAP2_SFT 27 -+#define STRAP2_HI 27 -+#define STRAP2_SZ 1 -+#define GPIO_20_ID_MSK 0x10000000 -+#define GPIO_20_ID_I_MSK 0xefffffff -+#define GPIO_20_ID_SFT 28 -+#define GPIO_20_ID_HI 28 -+#define GPIO_20_ID_SZ 1 -+#define PAD70_OE_MSK 0x00000001 -+#define PAD70_OE_I_MSK 0xfffffffe -+#define PAD70_OE_SFT 0 -+#define PAD70_OE_HI 0 -+#define PAD70_OE_SZ 1 -+#define PAD70_PE_MSK 0x00000002 -+#define PAD70_PE_I_MSK 0xfffffffd -+#define PAD70_PE_SFT 1 -+#define PAD70_PE_HI 1 -+#define PAD70_PE_SZ 1 -+#define PAD70_DS_MSK 0x00000004 -+#define PAD70_DS_I_MSK 0xfffffffb -+#define PAD70_DS_SFT 2 -+#define PAD70_DS_HI 2 -+#define PAD70_DS_SZ 1 -+#define PAD70_IE_MSK 0x00000008 -+#define PAD70_IE_I_MSK 0xfffffff7 -+#define PAD70_IE_SFT 3 -+#define PAD70_IE_HI 3 -+#define PAD70_IE_SZ 1 -+#define PAD70_SEL_I_MSK 0x00000030 -+#define PAD70_SEL_I_I_MSK 0xffffffcf -+#define PAD70_SEL_I_SFT 4 -+#define PAD70_SEL_I_HI 5 -+#define PAD70_SEL_I_SZ 2 -+#define PAD70_OD_MSK 0x00000100 -+#define PAD70_OD_I_MSK 0xfffffeff -+#define PAD70_OD_SFT 8 -+#define PAD70_OD_HI 8 -+#define PAD70_OD_SZ 1 -+#define PAD70_SEL_O_MSK 0x00007000 -+#define PAD70_SEL_O_I_MSK 0xffff8fff -+#define PAD70_SEL_O_SFT 12 -+#define PAD70_SEL_O_HI 14 -+#define PAD70_SEL_O_SZ 3 -+#define GPIO_21_ID_MSK 0x10000000 -+#define GPIO_21_ID_I_MSK 0xefffffff -+#define GPIO_21_ID_SFT 28 -+#define GPIO_21_ID_HI 28 -+#define GPIO_21_ID_SZ 1 -+#define PAD231_OE_MSK 0x00000001 -+#define PAD231_OE_I_MSK 0xfffffffe -+#define PAD231_OE_SFT 0 -+#define PAD231_OE_HI 0 -+#define PAD231_OE_SZ 1 -+#define PAD231_PE_MSK 0x00000002 -+#define PAD231_PE_I_MSK 0xfffffffd -+#define PAD231_PE_SFT 1 -+#define PAD231_PE_HI 1 -+#define PAD231_PE_SZ 1 -+#define PAD231_DS_MSK 0x00000004 -+#define PAD231_DS_I_MSK 0xfffffffb -+#define PAD231_DS_SFT 2 -+#define PAD231_DS_HI 2 -+#define PAD231_DS_SZ 1 -+#define PAD231_IE_MSK 0x00000008 -+#define PAD231_IE_I_MSK 0xfffffff7 -+#define PAD231_IE_SFT 3 -+#define PAD231_IE_HI 3 -+#define PAD231_IE_SZ 1 -+#define PAD231_OD_MSK 0x00000100 -+#define PAD231_OD_I_MSK 0xfffffeff -+#define PAD231_OD_SFT 8 -+#define PAD231_OD_HI 8 -+#define PAD231_OD_SZ 1 -+#define PIN_40_OR_56_ID_MSK 0x10000000 -+#define PIN_40_OR_56_ID_I_MSK 0xefffffff -+#define PIN_40_OR_56_ID_SFT 28 -+#define PIN_40_OR_56_ID_HI 28 -+#define PIN_40_OR_56_ID_SZ 1 -+#define MP_PHY2RX_DATA__0_SEL_MSK 0x00000001 -+#define MP_PHY2RX_DATA__0_SEL_I_MSK 0xfffffffe -+#define MP_PHY2RX_DATA__0_SEL_SFT 0 -+#define MP_PHY2RX_DATA__0_SEL_HI 0 -+#define MP_PHY2RX_DATA__0_SEL_SZ 1 -+#define MP_PHY2RX_DATA__1_SEL_MSK 0x00000002 -+#define MP_PHY2RX_DATA__1_SEL_I_MSK 0xfffffffd -+#define MP_PHY2RX_DATA__1_SEL_SFT 1 -+#define MP_PHY2RX_DATA__1_SEL_HI 1 -+#define MP_PHY2RX_DATA__1_SEL_SZ 1 -+#define MP_TX_FF_RPTR__1_SEL_MSK 0x00000004 -+#define MP_TX_FF_RPTR__1_SEL_I_MSK 0xfffffffb -+#define MP_TX_FF_RPTR__1_SEL_SFT 2 -+#define MP_TX_FF_RPTR__1_SEL_HI 2 -+#define MP_TX_FF_RPTR__1_SEL_SZ 1 -+#define MP_RX_FF_WPTR__2_SEL_MSK 0x00000008 -+#define MP_RX_FF_WPTR__2_SEL_I_MSK 0xfffffff7 -+#define MP_RX_FF_WPTR__2_SEL_SFT 3 -+#define MP_RX_FF_WPTR__2_SEL_HI 3 -+#define MP_RX_FF_WPTR__2_SEL_SZ 1 -+#define MP_RX_FF_WPTR__1_SEL_MSK 0x00000010 -+#define MP_RX_FF_WPTR__1_SEL_I_MSK 0xffffffef -+#define MP_RX_FF_WPTR__1_SEL_SFT 4 -+#define MP_RX_FF_WPTR__1_SEL_HI 4 -+#define MP_RX_FF_WPTR__1_SEL_SZ 1 -+#define MP_RX_FF_WPTR__0_SEL_MSK 0x00000020 -+#define MP_RX_FF_WPTR__0_SEL_I_MSK 0xffffffdf -+#define MP_RX_FF_WPTR__0_SEL_SFT 5 -+#define MP_RX_FF_WPTR__0_SEL_HI 5 -+#define MP_RX_FF_WPTR__0_SEL_SZ 1 -+#define MP_PHY2RX_DATA__2_SEL_MSK 0x00000040 -+#define MP_PHY2RX_DATA__2_SEL_I_MSK 0xffffffbf -+#define MP_PHY2RX_DATA__2_SEL_SFT 6 -+#define MP_PHY2RX_DATA__2_SEL_HI 6 -+#define MP_PHY2RX_DATA__2_SEL_SZ 1 -+#define MP_PHY2RX_DATA__4_SEL_MSK 0x00000080 -+#define MP_PHY2RX_DATA__4_SEL_I_MSK 0xffffff7f -+#define MP_PHY2RX_DATA__4_SEL_SFT 7 -+#define MP_PHY2RX_DATA__4_SEL_HI 7 -+#define MP_PHY2RX_DATA__4_SEL_SZ 1 -+#define I2CM_SDA_ID_SEL_MSK 0x00000300 -+#define I2CM_SDA_ID_SEL_I_MSK 0xfffffcff -+#define I2CM_SDA_ID_SEL_SFT 8 -+#define I2CM_SDA_ID_SEL_HI 9 -+#define I2CM_SDA_ID_SEL_SZ 2 -+#define CRYSTAL_OUT_REQ_SEL_MSK 0x00000400 -+#define CRYSTAL_OUT_REQ_SEL_I_MSK 0xfffffbff -+#define CRYSTAL_OUT_REQ_SEL_SFT 10 -+#define CRYSTAL_OUT_REQ_SEL_HI 10 -+#define CRYSTAL_OUT_REQ_SEL_SZ 1 -+#define MP_PHY2RX_DATA__5_SEL_MSK 0x00000800 -+#define MP_PHY2RX_DATA__5_SEL_I_MSK 0xfffff7ff -+#define MP_PHY2RX_DATA__5_SEL_SFT 11 -+#define MP_PHY2RX_DATA__5_SEL_HI 11 -+#define MP_PHY2RX_DATA__5_SEL_SZ 1 -+#define MP_PHY2RX_DATA__3_SEL_MSK 0x00001000 -+#define MP_PHY2RX_DATA__3_SEL_I_MSK 0xffffefff -+#define MP_PHY2RX_DATA__3_SEL_SFT 12 -+#define MP_PHY2RX_DATA__3_SEL_HI 12 -+#define MP_PHY2RX_DATA__3_SEL_SZ 1 -+#define UART_RXD_SEL_MSK 0x00006000 -+#define UART_RXD_SEL_I_MSK 0xffff9fff -+#define UART_RXD_SEL_SFT 13 -+#define UART_RXD_SEL_HI 14 -+#define UART_RXD_SEL_SZ 2 -+#define MP_PHY2RX_DATA__6_SEL_MSK 0x00008000 -+#define MP_PHY2RX_DATA__6_SEL_I_MSK 0xffff7fff -+#define MP_PHY2RX_DATA__6_SEL_SFT 15 -+#define MP_PHY2RX_DATA__6_SEL_HI 15 -+#define MP_PHY2RX_DATA__6_SEL_SZ 1 -+#define DAT_UART_NCTS_SEL_MSK 0x00010000 -+#define DAT_UART_NCTS_SEL_I_MSK 0xfffeffff -+#define DAT_UART_NCTS_SEL_SFT 16 -+#define DAT_UART_NCTS_SEL_HI 16 -+#define DAT_UART_NCTS_SEL_SZ 1 -+#define GPIO_LOG_STOP_SEL_MSK 0x000e0000 -+#define GPIO_LOG_STOP_SEL_I_MSK 0xfff1ffff -+#define GPIO_LOG_STOP_SEL_SFT 17 -+#define GPIO_LOG_STOP_SEL_HI 19 -+#define GPIO_LOG_STOP_SEL_SZ 3 -+#define MP_TX_FF_RPTR__0_SEL_MSK 0x00100000 -+#define MP_TX_FF_RPTR__0_SEL_I_MSK 0xffefffff -+#define MP_TX_FF_RPTR__0_SEL_SFT 20 -+#define MP_TX_FF_RPTR__0_SEL_HI 20 -+#define MP_TX_FF_RPTR__0_SEL_SZ 1 -+#define MP_PHY_RX_WRST_N_SEL_MSK 0x00200000 -+#define MP_PHY_RX_WRST_N_SEL_I_MSK 0xffdfffff -+#define MP_PHY_RX_WRST_N_SEL_SFT 21 -+#define MP_PHY_RX_WRST_N_SEL_HI 21 -+#define MP_PHY_RX_WRST_N_SEL_SZ 1 -+#define EXT_32K_SEL_MSK 0x00c00000 -+#define EXT_32K_SEL_I_MSK 0xff3fffff -+#define EXT_32K_SEL_SFT 22 -+#define EXT_32K_SEL_HI 23 -+#define EXT_32K_SEL_SZ 2 -+#define MP_PHY2RX_DATA__7_SEL_MSK 0x01000000 -+#define MP_PHY2RX_DATA__7_SEL_I_MSK 0xfeffffff -+#define MP_PHY2RX_DATA__7_SEL_SFT 24 -+#define MP_PHY2RX_DATA__7_SEL_HI 24 -+#define MP_PHY2RX_DATA__7_SEL_SZ 1 -+#define MP_TX_FF_RPTR__2_SEL_MSK 0x02000000 -+#define MP_TX_FF_RPTR__2_SEL_I_MSK 0xfdffffff -+#define MP_TX_FF_RPTR__2_SEL_SFT 25 -+#define MP_TX_FF_RPTR__2_SEL_HI 25 -+#define MP_TX_FF_RPTR__2_SEL_SZ 1 -+#define PMUINT_WAKE_SEL_MSK 0x1c000000 -+#define PMUINT_WAKE_SEL_I_MSK 0xe3ffffff -+#define PMUINT_WAKE_SEL_SFT 26 -+#define PMUINT_WAKE_SEL_HI 28 -+#define PMUINT_WAKE_SEL_SZ 3 -+#define I2CM_SCL_ID_SEL_MSK 0x20000000 -+#define I2CM_SCL_ID_SEL_I_MSK 0xdfffffff -+#define I2CM_SCL_ID_SEL_SFT 29 -+#define I2CM_SCL_ID_SEL_HI 29 -+#define I2CM_SCL_ID_SEL_SZ 1 -+#define MP_MRX_RX_EN_SEL_MSK 0x40000000 -+#define MP_MRX_RX_EN_SEL_I_MSK 0xbfffffff -+#define MP_MRX_RX_EN_SEL_SFT 30 -+#define MP_MRX_RX_EN_SEL_HI 30 -+#define MP_MRX_RX_EN_SEL_SZ 1 -+#define DAT_UART_RXD_SEL_0_MSK 0x80000000 -+#define DAT_UART_RXD_SEL_0_I_MSK 0x7fffffff -+#define DAT_UART_RXD_SEL_0_SFT 31 -+#define DAT_UART_RXD_SEL_0_HI 31 -+#define DAT_UART_RXD_SEL_0_SZ 1 -+#define DAT_UART_RXD_SEL_1_MSK 0x00000001 -+#define DAT_UART_RXD_SEL_1_I_MSK 0xfffffffe -+#define DAT_UART_RXD_SEL_1_SFT 0 -+#define DAT_UART_RXD_SEL_1_HI 0 -+#define DAT_UART_RXD_SEL_1_SZ 1 -+#define SPI_DI_SEL_MSK 0x00000002 -+#define SPI_DI_SEL_I_MSK 0xfffffffd -+#define SPI_DI_SEL_SFT 1 -+#define SPI_DI_SEL_HI 1 -+#define SPI_DI_SEL_SZ 1 -+#define IO_PORT_REG_MSK 0x0001ffff -+#define IO_PORT_REG_I_MSK 0xfffe0000 -+#define IO_PORT_REG_SFT 0 -+#define IO_PORT_REG_HI 16 -+#define IO_PORT_REG_SZ 17 -+#define MASK_RX_INT_MSK 0x00000001 -+#define MASK_RX_INT_I_MSK 0xfffffffe -+#define MASK_RX_INT_SFT 0 -+#define MASK_RX_INT_HI 0 -+#define MASK_RX_INT_SZ 1 -+#define MASK_TX_INT_MSK 0x00000002 -+#define MASK_TX_INT_I_MSK 0xfffffffd -+#define MASK_TX_INT_SFT 1 -+#define MASK_TX_INT_HI 1 -+#define MASK_TX_INT_SZ 1 -+#define MASK_SOC_SYSTEM_INT_MSK 0x00000004 -+#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb -+#define MASK_SOC_SYSTEM_INT_SFT 2 -+#define MASK_SOC_SYSTEM_INT_HI 2 -+#define MASK_SOC_SYSTEM_INT_SZ 1 -+#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008 -+#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7 -+#define EDCA0_LOW_THR_INT_MASK_SFT 3 -+#define EDCA0_LOW_THR_INT_MASK_HI 3 -+#define EDCA0_LOW_THR_INT_MASK_SZ 1 -+#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010 -+#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef -+#define EDCA1_LOW_THR_INT_MASK_SFT 4 -+#define EDCA1_LOW_THR_INT_MASK_HI 4 -+#define EDCA1_LOW_THR_INT_MASK_SZ 1 -+#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020 -+#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf -+#define EDCA2_LOW_THR_INT_MASK_SFT 5 -+#define EDCA2_LOW_THR_INT_MASK_HI 5 -+#define EDCA2_LOW_THR_INT_MASK_SZ 1 -+#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040 -+#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf -+#define EDCA3_LOW_THR_INT_MASK_SFT 6 -+#define EDCA3_LOW_THR_INT_MASK_HI 6 -+#define EDCA3_LOW_THR_INT_MASK_SZ 1 -+#define TX_LIMIT_INT_MASK_MSK 0x00000080 -+#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f -+#define TX_LIMIT_INT_MASK_SFT 7 -+#define TX_LIMIT_INT_MASK_HI 7 -+#define TX_LIMIT_INT_MASK_SZ 1 -+#define RX_INT_MSK 0x00000001 -+#define RX_INT_I_MSK 0xfffffffe -+#define RX_INT_SFT 0 -+#define RX_INT_HI 0 -+#define RX_INT_SZ 1 -+#define TX_COMPLETE_INT_MSK 0x00000002 -+#define TX_COMPLETE_INT_I_MSK 0xfffffffd -+#define TX_COMPLETE_INT_SFT 1 -+#define TX_COMPLETE_INT_HI 1 -+#define TX_COMPLETE_INT_SZ 1 -+#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004 -+#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb -+#define SOC_SYSTEM_INT_STATUS_SFT 2 -+#define SOC_SYSTEM_INT_STATUS_HI 2 -+#define SOC_SYSTEM_INT_STATUS_SZ 1 -+#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008 -+#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7 -+#define EDCA0_LOW_THR_INT_STS_SFT 3 -+#define EDCA0_LOW_THR_INT_STS_HI 3 -+#define EDCA0_LOW_THR_INT_STS_SZ 1 -+#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010 -+#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef -+#define EDCA1_LOW_THR_INT_STS_SFT 4 -+#define EDCA1_LOW_THR_INT_STS_HI 4 -+#define EDCA1_LOW_THR_INT_STS_SZ 1 -+#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020 -+#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf -+#define EDCA2_LOW_THR_INT_STS_SFT 5 -+#define EDCA2_LOW_THR_INT_STS_HI 5 -+#define EDCA2_LOW_THR_INT_STS_SZ 1 -+#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040 -+#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf -+#define EDCA3_LOW_THR_INT_STS_SFT 6 -+#define EDCA3_LOW_THR_INT_STS_HI 6 -+#define EDCA3_LOW_THR_INT_STS_SZ 1 -+#define TX_LIMIT_INT_STS_MSK 0x00000080 -+#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f -+#define TX_LIMIT_INT_STS_SFT 7 -+#define TX_LIMIT_INT_STS_HI 7 -+#define TX_LIMIT_INT_STS_SZ 1 -+#define HOST_TRIGGERED_RX_INT_MSK 0x00000100 -+#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff -+#define HOST_TRIGGERED_RX_INT_SFT 8 -+#define HOST_TRIGGERED_RX_INT_HI 8 -+#define HOST_TRIGGERED_RX_INT_SZ 1 -+#define HOST_TRIGGERED_TX_INT_MSK 0x00000200 -+#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff -+#define HOST_TRIGGERED_TX_INT_SFT 9 -+#define HOST_TRIGGERED_TX_INT_HI 9 -+#define HOST_TRIGGERED_TX_INT_SZ 1 -+#define SOC_TRIGGER_RX_INT_MSK 0x00000400 -+#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff -+#define SOC_TRIGGER_RX_INT_SFT 10 -+#define SOC_TRIGGER_RX_INT_HI 10 -+#define SOC_TRIGGER_RX_INT_SZ 1 -+#define SOC_TRIGGER_TX_INT_MSK 0x00000800 -+#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff -+#define SOC_TRIGGER_TX_INT_SFT 11 -+#define SOC_TRIGGER_TX_INT_HI 11 -+#define SOC_TRIGGER_TX_INT_SZ 1 -+#define RDY_FOR_TX_RX_MSK 0x00000001 -+#define RDY_FOR_TX_RX_I_MSK 0xfffffffe -+#define RDY_FOR_TX_RX_SFT 0 -+#define RDY_FOR_TX_RX_HI 0 -+#define RDY_FOR_TX_RX_SZ 1 -+#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002 -+#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd -+#define RDY_FOR_FW_DOWNLOAD_SFT 1 -+#define RDY_FOR_FW_DOWNLOAD_HI 1 -+#define RDY_FOR_FW_DOWNLOAD_SZ 1 -+#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004 -+#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb -+#define ILLEGAL_CMD_RESP_OPTION_SFT 2 -+#define ILLEGAL_CMD_RESP_OPTION_HI 2 -+#define ILLEGAL_CMD_RESP_OPTION_SZ 1 -+#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008 -+#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7 -+#define SDIO_TRX_DATA_SEQUENCE_SFT 3 -+#define SDIO_TRX_DATA_SEQUENCE_HI 3 -+#define SDIO_TRX_DATA_SEQUENCE_SZ 1 -+#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010 -+#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef -+#define GPIO_INT_TRIGGER_OPTION_SFT 4 -+#define GPIO_INT_TRIGGER_OPTION_HI 4 -+#define GPIO_INT_TRIGGER_OPTION_SZ 1 -+#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060 -+#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f -+#define TRIGGER_FUNCTION_SETTING_SFT 5 -+#define TRIGGER_FUNCTION_SETTING_HI 6 -+#define TRIGGER_FUNCTION_SETTING_SZ 2 -+#define CMD52_ABORT_RESPONSE_MSK 0x00000080 -+#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f -+#define CMD52_ABORT_RESPONSE_SFT 7 -+#define CMD52_ABORT_RESPONSE_HI 7 -+#define CMD52_ABORT_RESPONSE_SZ 1 -+#define RX_PACKET_LENGTH_MSK 0x0000ffff -+#define RX_PACKET_LENGTH_I_MSK 0xffff0000 -+#define RX_PACKET_LENGTH_SFT 0 -+#define RX_PACKET_LENGTH_HI 15 -+#define RX_PACKET_LENGTH_SZ 16 -+#define CARD_FW_DL_STATUS_MSK 0x00ff0000 -+#define CARD_FW_DL_STATUS_I_MSK 0xff00ffff -+#define CARD_FW_DL_STATUS_SFT 16 -+#define CARD_FW_DL_STATUS_HI 23 -+#define CARD_FW_DL_STATUS_SZ 8 -+#define TX_RX_LOOP_BACK_TEST_MSK 0x01000000 -+#define TX_RX_LOOP_BACK_TEST_I_MSK 0xfeffffff -+#define TX_RX_LOOP_BACK_TEST_SFT 24 -+#define TX_RX_LOOP_BACK_TEST_HI 24 -+#define TX_RX_LOOP_BACK_TEST_SZ 1 -+#define SDIO_LOOP_BACK_TEST_MSK 0x02000000 -+#define SDIO_LOOP_BACK_TEST_I_MSK 0xfdffffff -+#define SDIO_LOOP_BACK_TEST_SFT 25 -+#define SDIO_LOOP_BACK_TEST_HI 25 -+#define SDIO_LOOP_BACK_TEST_SZ 1 -+#define CMD52_ABORT_ACTIVE_MSK 0x10000000 -+#define CMD52_ABORT_ACTIVE_I_MSK 0xefffffff -+#define CMD52_ABORT_ACTIVE_SFT 28 -+#define CMD52_ABORT_ACTIVE_HI 28 -+#define CMD52_ABORT_ACTIVE_SZ 1 -+#define CMD52_RESET_ACTIVE_MSK 0x20000000 -+#define CMD52_RESET_ACTIVE_I_MSK 0xdfffffff -+#define CMD52_RESET_ACTIVE_SFT 29 -+#define CMD52_RESET_ACTIVE_HI 29 -+#define CMD52_RESET_ACTIVE_SZ 1 -+#define SDIO_PARTIAL_RESET_ACTIVE_MSK 0x40000000 -+#define SDIO_PARTIAL_RESET_ACTIVE_I_MSK 0xbfffffff -+#define SDIO_PARTIAL_RESET_ACTIVE_SFT 30 -+#define SDIO_PARTIAL_RESET_ACTIVE_HI 30 -+#define SDIO_PARTIAL_RESET_ACTIVE_SZ 1 -+#define SDIO_ALL_RESE_ACTIVE_MSK 0x80000000 -+#define SDIO_ALL_RESE_ACTIVE_I_MSK 0x7fffffff -+#define SDIO_ALL_RESE_ACTIVE_SFT 31 -+#define SDIO_ALL_RESE_ACTIVE_HI 31 -+#define SDIO_ALL_RESE_ACTIVE_SZ 1 -+#define RX_PACKET_LENGTH2_MSK 0x0000ffff -+#define RX_PACKET_LENGTH2_I_MSK 0xffff0000 -+#define RX_PACKET_LENGTH2_SFT 0 -+#define RX_PACKET_LENGTH2_HI 15 -+#define RX_PACKET_LENGTH2_SZ 16 -+#define RX_INT1_MSK 0x00010000 -+#define RX_INT1_I_MSK 0xfffeffff -+#define RX_INT1_SFT 16 -+#define RX_INT1_HI 16 -+#define RX_INT1_SZ 1 -+#define TX_DONE_MSK 0x00020000 -+#define TX_DONE_I_MSK 0xfffdffff -+#define TX_DONE_SFT 17 -+#define TX_DONE_HI 17 -+#define TX_DONE_SZ 1 -+#define HCI_TRX_FINISH_MSK 0x00040000 -+#define HCI_TRX_FINISH_I_MSK 0xfffbffff -+#define HCI_TRX_FINISH_SFT 18 -+#define HCI_TRX_FINISH_HI 18 -+#define HCI_TRX_FINISH_SZ 1 -+#define ALLOCATE_STATUS_MSK 0x00080000 -+#define ALLOCATE_STATUS_I_MSK 0xfff7ffff -+#define ALLOCATE_STATUS_SFT 19 -+#define ALLOCATE_STATUS_HI 19 -+#define ALLOCATE_STATUS_SZ 1 -+#define HCI_INPUT_FF_CNT_MSK 0x00f00000 -+#define HCI_INPUT_FF_CNT_I_MSK 0xff0fffff -+#define HCI_INPUT_FF_CNT_SFT 20 -+#define HCI_INPUT_FF_CNT_HI 23 -+#define HCI_INPUT_FF_CNT_SZ 4 -+#define HCI_OUTPUT_FF_CNT_MSK 0x1f000000 -+#define HCI_OUTPUT_FF_CNT_I_MSK 0xe0ffffff -+#define HCI_OUTPUT_FF_CNT_SFT 24 -+#define HCI_OUTPUT_FF_CNT_HI 28 -+#define HCI_OUTPUT_FF_CNT_SZ 5 -+#define AHB_HANG4_MSK 0x20000000 -+#define AHB_HANG4_I_MSK 0xdfffffff -+#define AHB_HANG4_SFT 29 -+#define AHB_HANG4_HI 29 -+#define AHB_HANG4_SZ 1 -+#define HCI_IN_QUE_EMPTY_MSK 0x40000000 -+#define HCI_IN_QUE_EMPTY_I_MSK 0xbfffffff -+#define HCI_IN_QUE_EMPTY_SFT 30 -+#define HCI_IN_QUE_EMPTY_HI 30 -+#define HCI_IN_QUE_EMPTY_SZ 1 -+#define SYSTEM_INT_MSK 0x80000000 -+#define SYSTEM_INT_I_MSK 0x7fffffff -+#define SYSTEM_INT_SFT 31 -+#define SYSTEM_INT_HI 31 -+#define SYSTEM_INT_SZ 1 -+#define CARD_RCA_REG_MSK 0x0000ffff -+#define CARD_RCA_REG_I_MSK 0xffff0000 -+#define CARD_RCA_REG_SFT 0 -+#define CARD_RCA_REG_HI 15 -+#define CARD_RCA_REG_SZ 16 -+#define SDIO_FIFO_WR_THLD_REG_MSK 0x000001ff -+#define SDIO_FIFO_WR_THLD_REG_I_MSK 0xfffffe00 -+#define SDIO_FIFO_WR_THLD_REG_SFT 0 -+#define SDIO_FIFO_WR_THLD_REG_HI 8 -+#define SDIO_FIFO_WR_THLD_REG_SZ 9 -+#define SDIO_FIFO_WR_LIMIT_REG_MSK 0x000001ff -+#define SDIO_FIFO_WR_LIMIT_REG_I_MSK 0xfffffe00 -+#define SDIO_FIFO_WR_LIMIT_REG_SFT 0 -+#define SDIO_FIFO_WR_LIMIT_REG_HI 8 -+#define SDIO_FIFO_WR_LIMIT_REG_SZ 9 -+#define SDIO_TX_DATA_BATCH_SIZE_REG_MSK 0x000001ff -+#define SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00 -+#define SDIO_TX_DATA_BATCH_SIZE_REG_SFT 0 -+#define SDIO_TX_DATA_BATCH_SIZE_REG_HI 8 -+#define SDIO_TX_DATA_BATCH_SIZE_REG_SZ 9 -+#define SDIO_THLD_FOR_CMD53RD_REG_MSK 0x000001ff -+#define SDIO_THLD_FOR_CMD53RD_REG_I_MSK 0xfffffe00 -+#define SDIO_THLD_FOR_CMD53RD_REG_SFT 0 -+#define SDIO_THLD_FOR_CMD53RD_REG_HI 8 -+#define SDIO_THLD_FOR_CMD53RD_REG_SZ 9 -+#define SDIO_RX_DATA_BATCH_SIZE_REG_MSK 0x000001ff -+#define SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00 -+#define SDIO_RX_DATA_BATCH_SIZE_REG_SFT 0 -+#define SDIO_RX_DATA_BATCH_SIZE_REG_HI 8 -+#define SDIO_RX_DATA_BATCH_SIZE_REG_SZ 9 -+#define START_BYTE_VALUE_MSK 0x000000ff -+#define START_BYTE_VALUE_I_MSK 0xffffff00 -+#define START_BYTE_VALUE_SFT 0 -+#define START_BYTE_VALUE_HI 7 -+#define START_BYTE_VALUE_SZ 8 -+#define END_BYTE_VALUE_MSK 0x0000ff00 -+#define END_BYTE_VALUE_I_MSK 0xffff00ff -+#define END_BYTE_VALUE_SFT 8 -+#define END_BYTE_VALUE_HI 15 -+#define END_BYTE_VALUE_SZ 8 -+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff -+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00 -+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0 -+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7 -+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8 -+#define SDIO_LAST_CMD_INDEX_REG_MSK 0x0000003f -+#define SDIO_LAST_CMD_INDEX_REG_I_MSK 0xffffffc0 -+#define SDIO_LAST_CMD_INDEX_REG_SFT 0 -+#define SDIO_LAST_CMD_INDEX_REG_HI 5 -+#define SDIO_LAST_CMD_INDEX_REG_SZ 6 -+#define SDIO_LAST_CMD_CRC_REG_MSK 0x00007f00 -+#define SDIO_LAST_CMD_CRC_REG_I_MSK 0xffff80ff -+#define SDIO_LAST_CMD_CRC_REG_SFT 8 -+#define SDIO_LAST_CMD_CRC_REG_HI 14 -+#define SDIO_LAST_CMD_CRC_REG_SZ 7 -+#define SDIO_LAST_CMD_ARG_REG_MSK 0xffffffff -+#define SDIO_LAST_CMD_ARG_REG_I_MSK 0x00000000 -+#define SDIO_LAST_CMD_ARG_REG_SFT 0 -+#define SDIO_LAST_CMD_ARG_REG_HI 31 -+#define SDIO_LAST_CMD_ARG_REG_SZ 32 -+#define SDIO_BUS_STATE_REG_MSK 0x0000001f -+#define SDIO_BUS_STATE_REG_I_MSK 0xffffffe0 -+#define SDIO_BUS_STATE_REG_SFT 0 -+#define SDIO_BUS_STATE_REG_HI 4 -+#define SDIO_BUS_STATE_REG_SZ 5 -+#define SDIO_BUSY_LONG_CNT_MSK 0xffff0000 -+#define SDIO_BUSY_LONG_CNT_I_MSK 0x0000ffff -+#define SDIO_BUSY_LONG_CNT_SFT 16 -+#define SDIO_BUSY_LONG_CNT_HI 31 -+#define SDIO_BUSY_LONG_CNT_SZ 16 -+#define SDIO_CARD_STATUS_REG_MSK 0xffffffff -+#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000 -+#define SDIO_CARD_STATUS_REG_SFT 0 -+#define SDIO_CARD_STATUS_REG_HI 31 -+#define SDIO_CARD_STATUS_REG_SZ 32 -+#define R5_RESPONSE_FLAG_MSK 0x000000ff -+#define R5_RESPONSE_FLAG_I_MSK 0xffffff00 -+#define R5_RESPONSE_FLAG_SFT 0 -+#define R5_RESPONSE_FLAG_HI 7 -+#define R5_RESPONSE_FLAG_SZ 8 -+#define RESP_OUT_EDGE_MSK 0x00000100 -+#define RESP_OUT_EDGE_I_MSK 0xfffffeff -+#define RESP_OUT_EDGE_SFT 8 -+#define RESP_OUT_EDGE_HI 8 -+#define RESP_OUT_EDGE_SZ 1 -+#define DAT_OUT_EDGE_MSK 0x00000200 -+#define DAT_OUT_EDGE_I_MSK 0xfffffdff -+#define DAT_OUT_EDGE_SFT 9 -+#define DAT_OUT_EDGE_HI 9 -+#define DAT_OUT_EDGE_SZ 1 -+#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000 -+#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff -+#define MCU_TO_SDIO_INFO_MASK_SFT 16 -+#define MCU_TO_SDIO_INFO_MASK_HI 16 -+#define MCU_TO_SDIO_INFO_MASK_SZ 1 -+#define INT_THROUGH_PIN_MSK 0x00020000 -+#define INT_THROUGH_PIN_I_MSK 0xfffdffff -+#define INT_THROUGH_PIN_SFT 17 -+#define INT_THROUGH_PIN_HI 17 -+#define INT_THROUGH_PIN_SZ 1 -+#define WRITE_DATA_MSK 0x000000ff -+#define WRITE_DATA_I_MSK 0xffffff00 -+#define WRITE_DATA_SFT 0 -+#define WRITE_DATA_HI 7 -+#define WRITE_DATA_SZ 8 -+#define WRITE_ADDRESS_MSK 0x0000ff00 -+#define WRITE_ADDRESS_I_MSK 0xffff00ff -+#define WRITE_ADDRESS_SFT 8 -+#define WRITE_ADDRESS_HI 15 -+#define WRITE_ADDRESS_SZ 8 -+#define READ_DATA_MSK 0x00ff0000 -+#define READ_DATA_I_MSK 0xff00ffff -+#define READ_DATA_SFT 16 -+#define READ_DATA_HI 23 -+#define READ_DATA_SZ 8 -+#define READ_ADDRESS_MSK 0xff000000 -+#define READ_ADDRESS_I_MSK 0x00ffffff -+#define READ_ADDRESS_SFT 24 -+#define READ_ADDRESS_HI 31 -+#define READ_ADDRESS_SZ 8 -+#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff -+#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000 -+#define FN1_DMA_START_ADDR_REG_SFT 0 -+#define FN1_DMA_START_ADDR_REG_HI 31 -+#define FN1_DMA_START_ADDR_REG_SZ 32 -+#define SDIO_TO_MCU_INFO_MSK 0x000000ff -+#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00 -+#define SDIO_TO_MCU_INFO_SFT 0 -+#define SDIO_TO_MCU_INFO_HI 7 -+#define SDIO_TO_MCU_INFO_SZ 8 -+#define SDIO_PARTIAL_RESET_MSK 0x00000100 -+#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff -+#define SDIO_PARTIAL_RESET_SFT 8 -+#define SDIO_PARTIAL_RESET_HI 8 -+#define SDIO_PARTIAL_RESET_SZ 1 -+#define SDIO_ALL_RESET_MSK 0x00000200 -+#define SDIO_ALL_RESET_I_MSK 0xfffffdff -+#define SDIO_ALL_RESET_SFT 9 -+#define SDIO_ALL_RESET_HI 9 -+#define SDIO_ALL_RESET_SZ 1 -+#define PERI_MAC_ALL_RESET_MSK 0x00000400 -+#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff -+#define PERI_MAC_ALL_RESET_SFT 10 -+#define PERI_MAC_ALL_RESET_HI 10 -+#define PERI_MAC_ALL_RESET_SZ 1 -+#define MAC_ALL_RESET_MSK 0x00000800 -+#define MAC_ALL_RESET_I_MSK 0xfffff7ff -+#define MAC_ALL_RESET_SFT 11 -+#define MAC_ALL_RESET_HI 11 -+#define MAC_ALL_RESET_SZ 1 -+#define AHB_BRIDGE_RESET_MSK 0x00001000 -+#define AHB_BRIDGE_RESET_I_MSK 0xffffefff -+#define AHB_BRIDGE_RESET_SFT 12 -+#define AHB_BRIDGE_RESET_HI 12 -+#define AHB_BRIDGE_RESET_SZ 1 -+#define IO_REG_PORT_REG_MSK 0x0001ffff -+#define IO_REG_PORT_REG_I_MSK 0xfffe0000 -+#define IO_REG_PORT_REG_SFT 0 -+#define IO_REG_PORT_REG_HI 16 -+#define IO_REG_PORT_REG_SZ 17 -+#define SDIO_FIFO_EMPTY_CNT_MSK 0x0000ffff -+#define SDIO_FIFO_EMPTY_CNT_I_MSK 0xffff0000 -+#define SDIO_FIFO_EMPTY_CNT_SFT 0 -+#define SDIO_FIFO_EMPTY_CNT_HI 15 -+#define SDIO_FIFO_EMPTY_CNT_SZ 16 -+#define SDIO_FIFO_FULL_CNT_MSK 0xffff0000 -+#define SDIO_FIFO_FULL_CNT_I_MSK 0x0000ffff -+#define SDIO_FIFO_FULL_CNT_SFT 16 -+#define SDIO_FIFO_FULL_CNT_HI 31 -+#define SDIO_FIFO_FULL_CNT_SZ 16 -+#define SDIO_CRC7_ERROR_CNT_MSK 0x0000ffff -+#define SDIO_CRC7_ERROR_CNT_I_MSK 0xffff0000 -+#define SDIO_CRC7_ERROR_CNT_SFT 0 -+#define SDIO_CRC7_ERROR_CNT_HI 15 -+#define SDIO_CRC7_ERROR_CNT_SZ 16 -+#define SDIO_CRC16_ERROR_CNT_MSK 0xffff0000 -+#define SDIO_CRC16_ERROR_CNT_I_MSK 0x0000ffff -+#define SDIO_CRC16_ERROR_CNT_SFT 16 -+#define SDIO_CRC16_ERROR_CNT_HI 31 -+#define SDIO_CRC16_ERROR_CNT_SZ 16 -+#define SDIO_RD_BLOCK_CNT_MSK 0x000001ff -+#define SDIO_RD_BLOCK_CNT_I_MSK 0xfffffe00 -+#define SDIO_RD_BLOCK_CNT_SFT 0 -+#define SDIO_RD_BLOCK_CNT_HI 8 -+#define SDIO_RD_BLOCK_CNT_SZ 9 -+#define SDIO_WR_BLOCK_CNT_MSK 0x01ff0000 -+#define SDIO_WR_BLOCK_CNT_I_MSK 0xfe00ffff -+#define SDIO_WR_BLOCK_CNT_SFT 16 -+#define SDIO_WR_BLOCK_CNT_HI 24 -+#define SDIO_WR_BLOCK_CNT_SZ 9 -+#define CMD52_RD_ABORT_CNT_MSK 0x000f0000 -+#define CMD52_RD_ABORT_CNT_I_MSK 0xfff0ffff -+#define CMD52_RD_ABORT_CNT_SFT 16 -+#define CMD52_RD_ABORT_CNT_HI 19 -+#define CMD52_RD_ABORT_CNT_SZ 4 -+#define CMD52_WR_ABORT_CNT_MSK 0x00f00000 -+#define CMD52_WR_ABORT_CNT_I_MSK 0xff0fffff -+#define CMD52_WR_ABORT_CNT_SFT 20 -+#define CMD52_WR_ABORT_CNT_HI 23 -+#define CMD52_WR_ABORT_CNT_SZ 4 -+#define SDIO_FIFO_WR_PTR_REG_MSK 0x000000ff -+#define SDIO_FIFO_WR_PTR_REG_I_MSK 0xffffff00 -+#define SDIO_FIFO_WR_PTR_REG_SFT 0 -+#define SDIO_FIFO_WR_PTR_REG_HI 7 -+#define SDIO_FIFO_WR_PTR_REG_SZ 8 -+#define SDIO_FIFO_RD_PTR_REG_MSK 0x0000ff00 -+#define SDIO_FIFO_RD_PTR_REG_I_MSK 0xffff00ff -+#define SDIO_FIFO_RD_PTR_REG_SFT 8 -+#define SDIO_FIFO_RD_PTR_REG_HI 15 -+#define SDIO_FIFO_RD_PTR_REG_SZ 8 -+#define SDIO_READ_DATA_CTRL_MSK 0x00010000 -+#define SDIO_READ_DATA_CTRL_I_MSK 0xfffeffff -+#define SDIO_READ_DATA_CTRL_SFT 16 -+#define SDIO_READ_DATA_CTRL_HI 16 -+#define SDIO_READ_DATA_CTRL_SZ 1 -+#define TX_SIZE_BEFORE_SHIFT_MSK 0x000000ff -+#define TX_SIZE_BEFORE_SHIFT_I_MSK 0xffffff00 -+#define TX_SIZE_BEFORE_SHIFT_SFT 0 -+#define TX_SIZE_BEFORE_SHIFT_HI 7 -+#define TX_SIZE_BEFORE_SHIFT_SZ 8 -+#define TX_SIZE_SHIFT_BITS_MSK 0x00000700 -+#define TX_SIZE_SHIFT_BITS_I_MSK 0xfffff8ff -+#define TX_SIZE_SHIFT_BITS_SFT 8 -+#define TX_SIZE_SHIFT_BITS_HI 10 -+#define TX_SIZE_SHIFT_BITS_SZ 3 -+#define SDIO_TX_ALLOC_STATE_MSK 0x00001000 -+#define SDIO_TX_ALLOC_STATE_I_MSK 0xffffefff -+#define SDIO_TX_ALLOC_STATE_SFT 12 -+#define SDIO_TX_ALLOC_STATE_HI 12 -+#define SDIO_TX_ALLOC_STATE_SZ 1 -+#define ALLOCATE_STATUS2_MSK 0x00010000 -+#define ALLOCATE_STATUS2_I_MSK 0xfffeffff -+#define ALLOCATE_STATUS2_SFT 16 -+#define ALLOCATE_STATUS2_HI 16 -+#define ALLOCATE_STATUS2_SZ 1 -+#define NO_ALLOCATE_SEND_ERROR_MSK 0x00020000 -+#define NO_ALLOCATE_SEND_ERROR_I_MSK 0xfffdffff -+#define NO_ALLOCATE_SEND_ERROR_SFT 17 -+#define NO_ALLOCATE_SEND_ERROR_HI 17 -+#define NO_ALLOCATE_SEND_ERROR_SZ 1 -+#define DOUBLE_ALLOCATE_ERROR_MSK 0x00040000 -+#define DOUBLE_ALLOCATE_ERROR_I_MSK 0xfffbffff -+#define DOUBLE_ALLOCATE_ERROR_SFT 18 -+#define DOUBLE_ALLOCATE_ERROR_HI 18 -+#define DOUBLE_ALLOCATE_ERROR_SZ 1 -+#define TX_DONE_STATUS_MSK 0x00080000 -+#define TX_DONE_STATUS_I_MSK 0xfff7ffff -+#define TX_DONE_STATUS_SFT 19 -+#define TX_DONE_STATUS_HI 19 -+#define TX_DONE_STATUS_SZ 1 -+#define AHB_HANG2_MSK 0x00100000 -+#define AHB_HANG2_I_MSK 0xffefffff -+#define AHB_HANG2_SFT 20 -+#define AHB_HANG2_HI 20 -+#define AHB_HANG2_SZ 1 -+#define HCI_TRX_FINISH2_MSK 0x00200000 -+#define HCI_TRX_FINISH2_I_MSK 0xffdfffff -+#define HCI_TRX_FINISH2_SFT 21 -+#define HCI_TRX_FINISH2_HI 21 -+#define HCI_TRX_FINISH2_SZ 1 -+#define INTR_RX_MSK 0x00400000 -+#define INTR_RX_I_MSK 0xffbfffff -+#define INTR_RX_SFT 22 -+#define INTR_RX_HI 22 -+#define INTR_RX_SZ 1 -+#define HCI_INPUT_QUEUE_FULL_MSK 0x00800000 -+#define HCI_INPUT_QUEUE_FULL_I_MSK 0xff7fffff -+#define HCI_INPUT_QUEUE_FULL_SFT 23 -+#define HCI_INPUT_QUEUE_FULL_HI 23 -+#define HCI_INPUT_QUEUE_FULL_SZ 1 -+#define ALLOCATESTATUS_MSK 0x00000001 -+#define ALLOCATESTATUS_I_MSK 0xfffffffe -+#define ALLOCATESTATUS_SFT 0 -+#define ALLOCATESTATUS_HI 0 -+#define ALLOCATESTATUS_SZ 1 -+#define HCI_TRX_FINISH3_MSK 0x00000002 -+#define HCI_TRX_FINISH3_I_MSK 0xfffffffd -+#define HCI_TRX_FINISH3_SFT 1 -+#define HCI_TRX_FINISH3_HI 1 -+#define HCI_TRX_FINISH3_SZ 1 -+#define HCI_IN_QUE_EMPTY2_MSK 0x00000004 -+#define HCI_IN_QUE_EMPTY2_I_MSK 0xfffffffb -+#define HCI_IN_QUE_EMPTY2_SFT 2 -+#define HCI_IN_QUE_EMPTY2_HI 2 -+#define HCI_IN_QUE_EMPTY2_SZ 1 -+#define MTX_MNG_UPTHOLD_INT_MSK 0x00000008 -+#define MTX_MNG_UPTHOLD_INT_I_MSK 0xfffffff7 -+#define MTX_MNG_UPTHOLD_INT_SFT 3 -+#define MTX_MNG_UPTHOLD_INT_HI 3 -+#define MTX_MNG_UPTHOLD_INT_SZ 1 -+#define EDCA0_UPTHOLD_INT_MSK 0x00000010 -+#define EDCA0_UPTHOLD_INT_I_MSK 0xffffffef -+#define EDCA0_UPTHOLD_INT_SFT 4 -+#define EDCA0_UPTHOLD_INT_HI 4 -+#define EDCA0_UPTHOLD_INT_SZ 1 -+#define EDCA1_UPTHOLD_INT_MSK 0x00000020 -+#define EDCA1_UPTHOLD_INT_I_MSK 0xffffffdf -+#define EDCA1_UPTHOLD_INT_SFT 5 -+#define EDCA1_UPTHOLD_INT_HI 5 -+#define EDCA1_UPTHOLD_INT_SZ 1 -+#define EDCA2_UPTHOLD_INT_MSK 0x00000040 -+#define EDCA2_UPTHOLD_INT_I_MSK 0xffffffbf -+#define EDCA2_UPTHOLD_INT_SFT 6 -+#define EDCA2_UPTHOLD_INT_HI 6 -+#define EDCA2_UPTHOLD_INT_SZ 1 -+#define EDCA3_UPTHOLD_INT_MSK 0x00000080 -+#define EDCA3_UPTHOLD_INT_I_MSK 0xffffff7f -+#define EDCA3_UPTHOLD_INT_SFT 7 -+#define EDCA3_UPTHOLD_INT_HI 7 -+#define EDCA3_UPTHOLD_INT_SZ 1 -+#define TX_PAGE_REMAIN2_MSK 0x0000ff00 -+#define TX_PAGE_REMAIN2_I_MSK 0xffff00ff -+#define TX_PAGE_REMAIN2_SFT 8 -+#define TX_PAGE_REMAIN2_HI 15 -+#define TX_PAGE_REMAIN2_SZ 8 -+#define TX_ID_REMAIN3_MSK 0x007f0000 -+#define TX_ID_REMAIN3_I_MSK 0xff80ffff -+#define TX_ID_REMAIN3_SFT 16 -+#define TX_ID_REMAIN3_HI 22 -+#define TX_ID_REMAIN3_SZ 7 -+#define HCI_OUTPUT_FF_CNT_0_MSK 0x00800000 -+#define HCI_OUTPUT_FF_CNT_0_I_MSK 0xff7fffff -+#define HCI_OUTPUT_FF_CNT_0_SFT 23 -+#define HCI_OUTPUT_FF_CNT_0_HI 23 -+#define HCI_OUTPUT_FF_CNT_0_SZ 1 -+#define HCI_OUTPUT_FF_CNT2_MSK 0x0f000000 -+#define HCI_OUTPUT_FF_CNT2_I_MSK 0xf0ffffff -+#define HCI_OUTPUT_FF_CNT2_SFT 24 -+#define HCI_OUTPUT_FF_CNT2_HI 27 -+#define HCI_OUTPUT_FF_CNT2_SZ 4 -+#define HCI_INPUT_FF_CNT2_MSK 0xf0000000 -+#define HCI_INPUT_FF_CNT2_I_MSK 0x0fffffff -+#define HCI_INPUT_FF_CNT2_SFT 28 -+#define HCI_INPUT_FF_CNT2_HI 31 -+#define HCI_INPUT_FF_CNT2_SZ 4 -+#define F1_BLOCK_SIZE_0_REG_MSK 0x00000fff -+#define F1_BLOCK_SIZE_0_REG_I_MSK 0xfffff000 -+#define F1_BLOCK_SIZE_0_REG_SFT 0 -+#define F1_BLOCK_SIZE_0_REG_HI 11 -+#define F1_BLOCK_SIZE_0_REG_SZ 12 -+#define START_BYTE_VALUE2_MSK 0x000000ff -+#define START_BYTE_VALUE2_I_MSK 0xffffff00 -+#define START_BYTE_VALUE2_SFT 0 -+#define START_BYTE_VALUE2_HI 7 -+#define START_BYTE_VALUE2_SZ 8 -+#define COMMAND_COUNTER_MSK 0x0000ff00 -+#define COMMAND_COUNTER_I_MSK 0xffff00ff -+#define COMMAND_COUNTER_SFT 8 -+#define COMMAND_COUNTER_HI 15 -+#define COMMAND_COUNTER_SZ 8 -+#define CMD_LOG_PART1_MSK 0xffff0000 -+#define CMD_LOG_PART1_I_MSK 0x0000ffff -+#define CMD_LOG_PART1_SFT 16 -+#define CMD_LOG_PART1_HI 31 -+#define CMD_LOG_PART1_SZ 16 -+#define CMD_LOG_PART2_MSK 0x00ffffff -+#define CMD_LOG_PART2_I_MSK 0xff000000 -+#define CMD_LOG_PART2_SFT 0 -+#define CMD_LOG_PART2_HI 23 -+#define CMD_LOG_PART2_SZ 24 -+#define END_BYTE_VALUE2_MSK 0xff000000 -+#define END_BYTE_VALUE2_I_MSK 0x00ffffff -+#define END_BYTE_VALUE2_SFT 24 -+#define END_BYTE_VALUE2_HI 31 -+#define END_BYTE_VALUE2_SZ 8 -+#define RX_PACKET_LENGTH3_MSK 0x0000ffff -+#define RX_PACKET_LENGTH3_I_MSK 0xffff0000 -+#define RX_PACKET_LENGTH3_SFT 0 -+#define RX_PACKET_LENGTH3_HI 15 -+#define RX_PACKET_LENGTH3_SZ 16 -+#define RX_INT3_MSK 0x00010000 -+#define RX_INT3_I_MSK 0xfffeffff -+#define RX_INT3_SFT 16 -+#define RX_INT3_HI 16 -+#define RX_INT3_SZ 1 -+#define TX_ID_REMAIN2_MSK 0x00fe0000 -+#define TX_ID_REMAIN2_I_MSK 0xff01ffff -+#define TX_ID_REMAIN2_SFT 17 -+#define TX_ID_REMAIN2_HI 23 -+#define TX_ID_REMAIN2_SZ 7 -+#define TX_PAGE_REMAIN3_MSK 0xff000000 -+#define TX_PAGE_REMAIN3_I_MSK 0x00ffffff -+#define TX_PAGE_REMAIN3_SFT 24 -+#define TX_PAGE_REMAIN3_HI 31 -+#define TX_PAGE_REMAIN3_SZ 8 -+#define CCCR_00H_REG_MSK 0x000000ff -+#define CCCR_00H_REG_I_MSK 0xffffff00 -+#define CCCR_00H_REG_SFT 0 -+#define CCCR_00H_REG_HI 7 -+#define CCCR_00H_REG_SZ 8 -+#define CCCR_02H_REG_MSK 0x00ff0000 -+#define CCCR_02H_REG_I_MSK 0xff00ffff -+#define CCCR_02H_REG_SFT 16 -+#define CCCR_02H_REG_HI 23 -+#define CCCR_02H_REG_SZ 8 -+#define CCCR_03H_REG_MSK 0xff000000 -+#define CCCR_03H_REG_I_MSK 0x00ffffff -+#define CCCR_03H_REG_SFT 24 -+#define CCCR_03H_REG_HI 31 -+#define CCCR_03H_REG_SZ 8 -+#define CCCR_04H_REG_MSK 0x000000ff -+#define CCCR_04H_REG_I_MSK 0xffffff00 -+#define CCCR_04H_REG_SFT 0 -+#define CCCR_04H_REG_HI 7 -+#define CCCR_04H_REG_SZ 8 -+#define CCCR_05H_REG_MSK 0x0000ff00 -+#define CCCR_05H_REG_I_MSK 0xffff00ff -+#define CCCR_05H_REG_SFT 8 -+#define CCCR_05H_REG_HI 15 -+#define CCCR_05H_REG_SZ 8 -+#define CCCR_06H_REG_MSK 0x000f0000 -+#define CCCR_06H_REG_I_MSK 0xfff0ffff -+#define CCCR_06H_REG_SFT 16 -+#define CCCR_06H_REG_HI 19 -+#define CCCR_06H_REG_SZ 4 -+#define CCCR_07H_REG_MSK 0xff000000 -+#define CCCR_07H_REG_I_MSK 0x00ffffff -+#define CCCR_07H_REG_SFT 24 -+#define CCCR_07H_REG_HI 31 -+#define CCCR_07H_REG_SZ 8 -+#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001 -+#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe -+#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0 -+#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0 -+#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1 -+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002 -+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd -+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1 -+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1 -+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1 -+#define SUPPORT_READ_WAIT_MSK 0x00000004 -+#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb -+#define SUPPORT_READ_WAIT_SFT 2 -+#define SUPPORT_READ_WAIT_HI 2 -+#define SUPPORT_READ_WAIT_SZ 1 -+#define SUPPORT_BUS_CONTROL_MSK 0x00000008 -+#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7 -+#define SUPPORT_BUS_CONTROL_SFT 3 -+#define SUPPORT_BUS_CONTROL_HI 3 -+#define SUPPORT_BUS_CONTROL_SZ 1 -+#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010 -+#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef -+#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4 -+#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4 -+#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1 -+#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020 -+#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf -+#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5 -+#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5 -+#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1 -+#define LOW_SPEED_CARD_MSK 0x00000040 -+#define LOW_SPEED_CARD_I_MSK 0xffffffbf -+#define LOW_SPEED_CARD_SFT 6 -+#define LOW_SPEED_CARD_HI 6 -+#define LOW_SPEED_CARD_SZ 1 -+#define LOW_SPEED_CARD_4BIT_MSK 0x00000080 -+#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f -+#define LOW_SPEED_CARD_4BIT_SFT 7 -+#define LOW_SPEED_CARD_4BIT_HI 7 -+#define LOW_SPEED_CARD_4BIT_SZ 1 -+#define COMMON_CIS_PONTER_MSK 0x01ffff00 -+#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff -+#define COMMON_CIS_PONTER_SFT 8 -+#define COMMON_CIS_PONTER_HI 24 -+#define COMMON_CIS_PONTER_SZ 17 -+#define SUPPORT_HIGH_SPEED_MSK 0x01000000 -+#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff -+#define SUPPORT_HIGH_SPEED_SFT 24 -+#define SUPPORT_HIGH_SPEED_HI 24 -+#define SUPPORT_HIGH_SPEED_SZ 1 -+#define BSS_MSK 0x0e000000 -+#define BSS_I_MSK 0xf1ffffff -+#define BSS_SFT 25 -+#define BSS_HI 27 -+#define BSS_SZ 3 -+#define FBR_100H_REG_MSK 0x0000000f -+#define FBR_100H_REG_I_MSK 0xfffffff0 -+#define FBR_100H_REG_SFT 0 -+#define FBR_100H_REG_HI 3 -+#define FBR_100H_REG_SZ 4 -+#define CSASUPPORT_MSK 0x00000040 -+#define CSASUPPORT_I_MSK 0xffffffbf -+#define CSASUPPORT_SFT 6 -+#define CSASUPPORT_HI 6 -+#define CSASUPPORT_SZ 1 -+#define ENABLECSA_MSK 0x00000080 -+#define ENABLECSA_I_MSK 0xffffff7f -+#define ENABLECSA_SFT 7 -+#define ENABLECSA_HI 7 -+#define ENABLECSA_SZ 1 -+#define FBR_101H_REG_MSK 0x0000ff00 -+#define FBR_101H_REG_I_MSK 0xffff00ff -+#define FBR_101H_REG_SFT 8 -+#define FBR_101H_REG_HI 15 -+#define FBR_101H_REG_SZ 8 -+#define FBR_109H_REG_MSK 0x01ffff00 -+#define FBR_109H_REG_I_MSK 0xfe0000ff -+#define FBR_109H_REG_SFT 8 -+#define FBR_109H_REG_HI 24 -+#define FBR_109H_REG_SZ 17 -+#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_31_0_SFT 0 -+#define F0_CIS_CONTENT_REG_31_0_HI 31 -+#define F0_CIS_CONTENT_REG_31_0_SZ 32 -+#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_63_32_SFT 0 -+#define F0_CIS_CONTENT_REG_63_32_HI 31 -+#define F0_CIS_CONTENT_REG_63_32_SZ 32 -+#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_95_64_SFT 0 -+#define F0_CIS_CONTENT_REG_95_64_HI 31 -+#define F0_CIS_CONTENT_REG_95_64_SZ 32 -+#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_127_96_SFT 0 -+#define F0_CIS_CONTENT_REG_127_96_HI 31 -+#define F0_CIS_CONTENT_REG_127_96_SZ 32 -+#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_159_128_SFT 0 -+#define F0_CIS_CONTENT_REG_159_128_HI 31 -+#define F0_CIS_CONTENT_REG_159_128_SZ 32 -+#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_191_160_SFT 0 -+#define F0_CIS_CONTENT_REG_191_160_HI 31 -+#define F0_CIS_CONTENT_REG_191_160_SZ 32 -+#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_223_192_SFT 0 -+#define F0_CIS_CONTENT_REG_223_192_HI 31 -+#define F0_CIS_CONTENT_REG_223_192_SZ 32 -+#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_255_224_SFT 0 -+#define F0_CIS_CONTENT_REG_255_224_HI 31 -+#define F0_CIS_CONTENT_REG_255_224_SZ 32 -+#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_287_256_SFT 0 -+#define F0_CIS_CONTENT_REG_287_256_HI 31 -+#define F0_CIS_CONTENT_REG_287_256_SZ 32 -+#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_319_288_SFT 0 -+#define F0_CIS_CONTENT_REG_319_288_HI 31 -+#define F0_CIS_CONTENT_REG_319_288_SZ 32 -+#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_351_320_SFT 0 -+#define F0_CIS_CONTENT_REG_351_320_HI 31 -+#define F0_CIS_CONTENT_REG_351_320_SZ 32 -+#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_383_352_SFT 0 -+#define F0_CIS_CONTENT_REG_383_352_HI 31 -+#define F0_CIS_CONTENT_REG_383_352_SZ 32 -+#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_415_384_SFT 0 -+#define F0_CIS_CONTENT_REG_415_384_HI 31 -+#define F0_CIS_CONTENT_REG_415_384_SZ 32 -+#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_447_416_SFT 0 -+#define F0_CIS_CONTENT_REG_447_416_HI 31 -+#define F0_CIS_CONTENT_REG_447_416_SZ 32 -+#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_479_448_SFT 0 -+#define F0_CIS_CONTENT_REG_479_448_HI 31 -+#define F0_CIS_CONTENT_REG_479_448_SZ 32 -+#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff -+#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000 -+#define F0_CIS_CONTENT_REG_511_480_SFT 0 -+#define F0_CIS_CONTENT_REG_511_480_HI 31 -+#define F0_CIS_CONTENT_REG_511_480_SZ 32 -+#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_31_0_SFT 0 -+#define F1_CIS_CONTENT_REG_31_0_HI 31 -+#define F1_CIS_CONTENT_REG_31_0_SZ 32 -+#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_63_32_SFT 0 -+#define F1_CIS_CONTENT_REG_63_32_HI 31 -+#define F1_CIS_CONTENT_REG_63_32_SZ 32 -+#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_95_64_SFT 0 -+#define F1_CIS_CONTENT_REG_95_64_HI 31 -+#define F1_CIS_CONTENT_REG_95_64_SZ 32 -+#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_127_96_SFT 0 -+#define F1_CIS_CONTENT_REG_127_96_HI 31 -+#define F1_CIS_CONTENT_REG_127_96_SZ 32 -+#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_159_128_SFT 0 -+#define F1_CIS_CONTENT_REG_159_128_HI 31 -+#define F1_CIS_CONTENT_REG_159_128_SZ 32 -+#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_191_160_SFT 0 -+#define F1_CIS_CONTENT_REG_191_160_HI 31 -+#define F1_CIS_CONTENT_REG_191_160_SZ 32 -+#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_223_192_SFT 0 -+#define F1_CIS_CONTENT_REG_223_192_HI 31 -+#define F1_CIS_CONTENT_REG_223_192_SZ 32 -+#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_255_224_SFT 0 -+#define F1_CIS_CONTENT_REG_255_224_HI 31 -+#define F1_CIS_CONTENT_REG_255_224_SZ 32 -+#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_287_256_SFT 0 -+#define F1_CIS_CONTENT_REG_287_256_HI 31 -+#define F1_CIS_CONTENT_REG_287_256_SZ 32 -+#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_319_288_SFT 0 -+#define F1_CIS_CONTENT_REG_319_288_HI 31 -+#define F1_CIS_CONTENT_REG_319_288_SZ 32 -+#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_351_320_SFT 0 -+#define F1_CIS_CONTENT_REG_351_320_HI 31 -+#define F1_CIS_CONTENT_REG_351_320_SZ 32 -+#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_383_352_SFT 0 -+#define F1_CIS_CONTENT_REG_383_352_HI 31 -+#define F1_CIS_CONTENT_REG_383_352_SZ 32 -+#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_415_384_SFT 0 -+#define F1_CIS_CONTENT_REG_415_384_HI 31 -+#define F1_CIS_CONTENT_REG_415_384_SZ 32 -+#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_447_416_SFT 0 -+#define F1_CIS_CONTENT_REG_447_416_HI 31 -+#define F1_CIS_CONTENT_REG_447_416_SZ 32 -+#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_479_448_SFT 0 -+#define F1_CIS_CONTENT_REG_479_448_HI 31 -+#define F1_CIS_CONTENT_REG_479_448_SZ 32 -+#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff -+#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000 -+#define F1_CIS_CONTENT_REG_511_480_SFT 0 -+#define F1_CIS_CONTENT_REG_511_480_HI 31 -+#define F1_CIS_CONTENT_REG_511_480_SZ 32 -+#define SPI_MODE_MSK 0xffffffff -+#define SPI_MODE_I_MSK 0x00000000 -+#define SPI_MODE_SFT 0 -+#define SPI_MODE_HI 31 -+#define SPI_MODE_SZ 32 -+#define RX_QUOTA_MSK 0x0000ffff -+#define RX_QUOTA_I_MSK 0xffff0000 -+#define RX_QUOTA_SFT 0 -+#define RX_QUOTA_HI 15 -+#define RX_QUOTA_SZ 16 -+#define CONDI_NUM_MSK 0x000000ff -+#define CONDI_NUM_I_MSK 0xffffff00 -+#define CONDI_NUM_SFT 0 -+#define CONDI_NUM_HI 7 -+#define CONDI_NUM_SZ 8 -+#define HOST_PATH_MSK 0x00000001 -+#define HOST_PATH_I_MSK 0xfffffffe -+#define HOST_PATH_SFT 0 -+#define HOST_PATH_HI 0 -+#define HOST_PATH_SZ 1 -+#define TX_SEG_MSK 0xffffffff -+#define TX_SEG_I_MSK 0x00000000 -+#define TX_SEG_SFT 0 -+#define TX_SEG_HI 31 -+#define TX_SEG_SZ 32 -+#define BRST_MODE_MSK 0x00000001 -+#define BRST_MODE_I_MSK 0xfffffffe -+#define BRST_MODE_SFT 0 -+#define BRST_MODE_HI 0 -+#define BRST_MODE_SZ 1 -+#define CLK_WIDTH_MSK 0x0000ffff -+#define CLK_WIDTH_I_MSK 0xffff0000 -+#define CLK_WIDTH_SFT 0 -+#define CLK_WIDTH_HI 15 -+#define CLK_WIDTH_SZ 16 -+#define CSN_INTER_MSK 0xffff0000 -+#define CSN_INTER_I_MSK 0x0000ffff -+#define CSN_INTER_SFT 16 -+#define CSN_INTER_HI 31 -+#define CSN_INTER_SZ 16 -+#define BACK_DLY_MSK 0x0000ffff -+#define BACK_DLY_I_MSK 0xffff0000 -+#define BACK_DLY_SFT 0 -+#define BACK_DLY_HI 15 -+#define BACK_DLY_SZ 16 -+#define FRONT_DLY_MSK 0xffff0000 -+#define FRONT_DLY_I_MSK 0x0000ffff -+#define FRONT_DLY_SFT 16 -+#define FRONT_DLY_HI 31 -+#define FRONT_DLY_SZ 16 -+#define RX_FIFO_FAIL_MSK 0x00000002 -+#define RX_FIFO_FAIL_I_MSK 0xfffffffd -+#define RX_FIFO_FAIL_SFT 1 -+#define RX_FIFO_FAIL_HI 1 -+#define RX_FIFO_FAIL_SZ 1 -+#define RX_HOST_FAIL_MSK 0x00000004 -+#define RX_HOST_FAIL_I_MSK 0xfffffffb -+#define RX_HOST_FAIL_SFT 2 -+#define RX_HOST_FAIL_HI 2 -+#define RX_HOST_FAIL_SZ 1 -+#define TX_FIFO_FAIL_MSK 0x00000008 -+#define TX_FIFO_FAIL_I_MSK 0xfffffff7 -+#define TX_FIFO_FAIL_SFT 3 -+#define TX_FIFO_FAIL_HI 3 -+#define TX_FIFO_FAIL_SZ 1 -+#define TX_HOST_FAIL_MSK 0x00000010 -+#define TX_HOST_FAIL_I_MSK 0xffffffef -+#define TX_HOST_FAIL_SFT 4 -+#define TX_HOST_FAIL_HI 4 -+#define TX_HOST_FAIL_SZ 1 -+#define SPI_DOUBLE_ALLOC_MSK 0x00000020 -+#define SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf -+#define SPI_DOUBLE_ALLOC_SFT 5 -+#define SPI_DOUBLE_ALLOC_HI 5 -+#define SPI_DOUBLE_ALLOC_SZ 1 -+#define SPI_TX_NO_ALLOC_MSK 0x00000040 -+#define SPI_TX_NO_ALLOC_I_MSK 0xffffffbf -+#define SPI_TX_NO_ALLOC_SFT 6 -+#define SPI_TX_NO_ALLOC_HI 6 -+#define SPI_TX_NO_ALLOC_SZ 1 -+#define RDATA_RDY_MSK 0x00000080 -+#define RDATA_RDY_I_MSK 0xffffff7f -+#define RDATA_RDY_SFT 7 -+#define RDATA_RDY_HI 7 -+#define RDATA_RDY_SZ 1 -+#define SPI_ALLOC_STATUS_MSK 0x00000100 -+#define SPI_ALLOC_STATUS_I_MSK 0xfffffeff -+#define SPI_ALLOC_STATUS_SFT 8 -+#define SPI_ALLOC_STATUS_HI 8 -+#define SPI_ALLOC_STATUS_SZ 1 -+#define SPI_DBG_WR_FIFO_FULL_MSK 0x00000200 -+#define SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff -+#define SPI_DBG_WR_FIFO_FULL_SFT 9 -+#define SPI_DBG_WR_FIFO_FULL_HI 9 -+#define SPI_DBG_WR_FIFO_FULL_SZ 1 -+#define RX_LEN_MSK 0xffff0000 -+#define RX_LEN_I_MSK 0x0000ffff -+#define RX_LEN_SFT 16 -+#define RX_LEN_HI 31 -+#define RX_LEN_SZ 16 -+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007 -+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8 -+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0 -+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2 -+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3 -+#define SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100 -+#define SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff -+#define SPI_HOST_TX_ALLOC_PKBUF_SFT 8 -+#define SPI_HOST_TX_ALLOC_PKBUF_HI 8 -+#define SPI_HOST_TX_ALLOC_PKBUF_SZ 1 -+#define SPI_TX_ALLOC_SIZE_MSK 0x000000ff -+#define SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00 -+#define SPI_TX_ALLOC_SIZE_SFT 0 -+#define SPI_TX_ALLOC_SIZE_HI 7 -+#define SPI_TX_ALLOC_SIZE_SZ 8 -+#define RD_DAT_CNT_MSK 0x0000ffff -+#define RD_DAT_CNT_I_MSK 0xffff0000 -+#define RD_DAT_CNT_SFT 0 -+#define RD_DAT_CNT_HI 15 -+#define RD_DAT_CNT_SZ 16 -+#define RD_STS_CNT_MSK 0xffff0000 -+#define RD_STS_CNT_I_MSK 0x0000ffff -+#define RD_STS_CNT_SFT 16 -+#define RD_STS_CNT_HI 31 -+#define RD_STS_CNT_SZ 16 -+#define JUDGE_CNT_MSK 0x0000ffff -+#define JUDGE_CNT_I_MSK 0xffff0000 -+#define JUDGE_CNT_SFT 0 -+#define JUDGE_CNT_HI 15 -+#define JUDGE_CNT_SZ 16 -+#define RD_STS_CNT_CLR_MSK 0x00010000 -+#define RD_STS_CNT_CLR_I_MSK 0xfffeffff -+#define RD_STS_CNT_CLR_SFT 16 -+#define RD_STS_CNT_CLR_HI 16 -+#define RD_STS_CNT_CLR_SZ 1 -+#define RD_DAT_CNT_CLR_MSK 0x00020000 -+#define RD_DAT_CNT_CLR_I_MSK 0xfffdffff -+#define RD_DAT_CNT_CLR_SFT 17 -+#define RD_DAT_CNT_CLR_HI 17 -+#define RD_DAT_CNT_CLR_SZ 1 -+#define JUDGE_CNT_CLR_MSK 0x00040000 -+#define JUDGE_CNT_CLR_I_MSK 0xfffbffff -+#define JUDGE_CNT_CLR_SFT 18 -+#define JUDGE_CNT_CLR_HI 18 -+#define JUDGE_CNT_CLR_SZ 1 -+#define TX_DONE_CNT_MSK 0x0000ffff -+#define TX_DONE_CNT_I_MSK 0xffff0000 -+#define TX_DONE_CNT_SFT 0 -+#define TX_DONE_CNT_HI 15 -+#define TX_DONE_CNT_SZ 16 -+#define TX_DISCARD_CNT_MSK 0xffff0000 -+#define TX_DISCARD_CNT_I_MSK 0x0000ffff -+#define TX_DISCARD_CNT_SFT 16 -+#define TX_DISCARD_CNT_HI 31 -+#define TX_DISCARD_CNT_SZ 16 -+#define TX_SET_CNT_MSK 0x0000ffff -+#define TX_SET_CNT_I_MSK 0xffff0000 -+#define TX_SET_CNT_SFT 0 -+#define TX_SET_CNT_HI 15 -+#define TX_SET_CNT_SZ 16 -+#define TX_DISCARD_CNT_CLR_MSK 0x00010000 -+#define TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff -+#define TX_DISCARD_CNT_CLR_SFT 16 -+#define TX_DISCARD_CNT_CLR_HI 16 -+#define TX_DISCARD_CNT_CLR_SZ 1 -+#define TX_DONE_CNT_CLR_MSK 0x00020000 -+#define TX_DONE_CNT_CLR_I_MSK 0xfffdffff -+#define TX_DONE_CNT_CLR_SFT 17 -+#define TX_DONE_CNT_CLR_HI 17 -+#define TX_DONE_CNT_CLR_SZ 1 -+#define TX_SET_CNT_CLR_MSK 0x00040000 -+#define TX_SET_CNT_CLR_I_MSK 0xfffbffff -+#define TX_SET_CNT_CLR_SFT 18 -+#define TX_SET_CNT_CLR_HI 18 -+#define TX_SET_CNT_CLR_SZ 1 -+#define DAT_MODE_OFF_MSK 0x00080000 -+#define DAT_MODE_OFF_I_MSK 0xfff7ffff -+#define DAT_MODE_OFF_SFT 19 -+#define DAT_MODE_OFF_HI 19 -+#define DAT_MODE_OFF_SZ 1 -+#define TX_FIFO_RESIDUE_MSK 0x00700000 -+#define TX_FIFO_RESIDUE_I_MSK 0xff8fffff -+#define TX_FIFO_RESIDUE_SFT 20 -+#define TX_FIFO_RESIDUE_HI 22 -+#define TX_FIFO_RESIDUE_SZ 3 -+#define RX_FIFO_RESIDUE_MSK 0x07000000 -+#define RX_FIFO_RESIDUE_I_MSK 0xf8ffffff -+#define RX_FIFO_RESIDUE_SFT 24 -+#define RX_FIFO_RESIDUE_HI 26 -+#define RX_FIFO_RESIDUE_SZ 3 -+#define RX_RDY_MSK 0x00000001 -+#define RX_RDY_I_MSK 0xfffffffe -+#define RX_RDY_SFT 0 -+#define RX_RDY_HI 0 -+#define RX_RDY_SZ 1 -+#define SDIO_SYS_INT_MSK 0x00000004 -+#define SDIO_SYS_INT_I_MSK 0xfffffffb -+#define SDIO_SYS_INT_SFT 2 -+#define SDIO_SYS_INT_HI 2 -+#define SDIO_SYS_INT_SZ 1 -+#define EDCA0_LOWTHOLD_INT_MSK 0x00000008 -+#define EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7 -+#define EDCA0_LOWTHOLD_INT_SFT 3 -+#define EDCA0_LOWTHOLD_INT_HI 3 -+#define EDCA0_LOWTHOLD_INT_SZ 1 -+#define EDCA1_LOWTHOLD_INT_MSK 0x00000010 -+#define EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef -+#define EDCA1_LOWTHOLD_INT_SFT 4 -+#define EDCA1_LOWTHOLD_INT_HI 4 -+#define EDCA1_LOWTHOLD_INT_SZ 1 -+#define EDCA2_LOWTHOLD_INT_MSK 0x00000020 -+#define EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf -+#define EDCA2_LOWTHOLD_INT_SFT 5 -+#define EDCA2_LOWTHOLD_INT_HI 5 -+#define EDCA2_LOWTHOLD_INT_SZ 1 -+#define EDCA3_LOWTHOLD_INT_MSK 0x00000040 -+#define EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf -+#define EDCA3_LOWTHOLD_INT_SFT 6 -+#define EDCA3_LOWTHOLD_INT_HI 6 -+#define EDCA3_LOWTHOLD_INT_SZ 1 -+#define TX_LIMIT_INT_IN_MSK 0x00000080 -+#define TX_LIMIT_INT_IN_I_MSK 0xffffff7f -+#define TX_LIMIT_INT_IN_SFT 7 -+#define TX_LIMIT_INT_IN_HI 7 -+#define TX_LIMIT_INT_IN_SZ 1 -+#define SPI_FN1_MSK 0x00007f00 -+#define SPI_FN1_I_MSK 0xffff80ff -+#define SPI_FN1_SFT 8 -+#define SPI_FN1_HI 14 -+#define SPI_FN1_SZ 7 -+#define SPI_CLK_EN_INT_MSK 0x00008000 -+#define SPI_CLK_EN_INT_I_MSK 0xffff7fff -+#define SPI_CLK_EN_INT_SFT 15 -+#define SPI_CLK_EN_INT_HI 15 -+#define SPI_CLK_EN_INT_SZ 1 -+#define SPI_HOST_MASK_MSK 0x00ff0000 -+#define SPI_HOST_MASK_I_MSK 0xff00ffff -+#define SPI_HOST_MASK_SFT 16 -+#define SPI_HOST_MASK_HI 23 -+#define SPI_HOST_MASK_SZ 8 -+#define I2CM_INT_WDONE_MSK 0x00000001 -+#define I2CM_INT_WDONE_I_MSK 0xfffffffe -+#define I2CM_INT_WDONE_SFT 0 -+#define I2CM_INT_WDONE_HI 0 -+#define I2CM_INT_WDONE_SZ 1 -+#define I2CM_INT_RDONE_MSK 0x00000002 -+#define I2CM_INT_RDONE_I_MSK 0xfffffffd -+#define I2CM_INT_RDONE_SFT 1 -+#define I2CM_INT_RDONE_HI 1 -+#define I2CM_INT_RDONE_SZ 1 -+#define I2CM_IDLE_MSK 0x00000004 -+#define I2CM_IDLE_I_MSK 0xfffffffb -+#define I2CM_IDLE_SFT 2 -+#define I2CM_IDLE_HI 2 -+#define I2CM_IDLE_SZ 1 -+#define I2CM_INT_MISMATCH_MSK 0x00000008 -+#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7 -+#define I2CM_INT_MISMATCH_SFT 3 -+#define I2CM_INT_MISMATCH_HI 3 -+#define I2CM_INT_MISMATCH_SZ 1 -+#define I2CM_PSCL_MSK 0x00003ff0 -+#define I2CM_PSCL_I_MSK 0xffffc00f -+#define I2CM_PSCL_SFT 4 -+#define I2CM_PSCL_HI 13 -+#define I2CM_PSCL_SZ 10 -+#define I2CM_MANUAL_MODE_MSK 0x00010000 -+#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff -+#define I2CM_MANUAL_MODE_SFT 16 -+#define I2CM_MANUAL_MODE_HI 16 -+#define I2CM_MANUAL_MODE_SZ 1 -+#define I2CM_INT_WDATA_NEED_MSK 0x00020000 -+#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff -+#define I2CM_INT_WDATA_NEED_SFT 17 -+#define I2CM_INT_WDATA_NEED_HI 17 -+#define I2CM_INT_WDATA_NEED_SZ 1 -+#define I2CM_INT_RDATA_NEED_MSK 0x00040000 -+#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff -+#define I2CM_INT_RDATA_NEED_SFT 18 -+#define I2CM_INT_RDATA_NEED_HI 18 -+#define I2CM_INT_RDATA_NEED_SZ 1 -+#define I2CM_DEV_A_MSK 0x000003ff -+#define I2CM_DEV_A_I_MSK 0xfffffc00 -+#define I2CM_DEV_A_SFT 0 -+#define I2CM_DEV_A_HI 9 -+#define I2CM_DEV_A_SZ 10 -+#define I2CM_DEV_A10B_MSK 0x00004000 -+#define I2CM_DEV_A10B_I_MSK 0xffffbfff -+#define I2CM_DEV_A10B_SFT 14 -+#define I2CM_DEV_A10B_HI 14 -+#define I2CM_DEV_A10B_SZ 1 -+#define I2CM_RX_MSK 0x00008000 -+#define I2CM_RX_I_MSK 0xffff7fff -+#define I2CM_RX_SFT 15 -+#define I2CM_RX_HI 15 -+#define I2CM_RX_SZ 1 -+#define I2CM_LEN_MSK 0x0000ffff -+#define I2CM_LEN_I_MSK 0xffff0000 -+#define I2CM_LEN_SFT 0 -+#define I2CM_LEN_HI 15 -+#define I2CM_LEN_SZ 16 -+#define I2CM_T_LEFT_MSK 0x00070000 -+#define I2CM_T_LEFT_I_MSK 0xfff8ffff -+#define I2CM_T_LEFT_SFT 16 -+#define I2CM_T_LEFT_HI 18 -+#define I2CM_T_LEFT_SZ 3 -+#define I2CM_R_GET_MSK 0x07000000 -+#define I2CM_R_GET_I_MSK 0xf8ffffff -+#define I2CM_R_GET_SFT 24 -+#define I2CM_R_GET_HI 26 -+#define I2CM_R_GET_SZ 3 -+#define I2CM_WDAT_MSK 0xffffffff -+#define I2CM_WDAT_I_MSK 0x00000000 -+#define I2CM_WDAT_SFT 0 -+#define I2CM_WDAT_HI 31 -+#define I2CM_WDAT_SZ 32 -+#define I2CM_RDAT_MSK 0xffffffff -+#define I2CM_RDAT_I_MSK 0x00000000 -+#define I2CM_RDAT_SFT 0 -+#define I2CM_RDAT_HI 31 -+#define I2CM_RDAT_SZ 32 -+#define I2CM_SR_LEN_MSK 0x0000ffff -+#define I2CM_SR_LEN_I_MSK 0xffff0000 -+#define I2CM_SR_LEN_SFT 0 -+#define I2CM_SR_LEN_HI 15 -+#define I2CM_SR_LEN_SZ 16 -+#define I2CM_SR_RX_MSK 0x00010000 -+#define I2CM_SR_RX_I_MSK 0xfffeffff -+#define I2CM_SR_RX_SFT 16 -+#define I2CM_SR_RX_HI 16 -+#define I2CM_SR_RX_SZ 1 -+#define I2CM_REPEAT_START_MSK 0x00020000 -+#define I2CM_REPEAT_START_I_MSK 0xfffdffff -+#define I2CM_REPEAT_START_SFT 17 -+#define I2CM_REPEAT_START_HI 17 -+#define I2CM_REPEAT_START_SZ 1 -+#define UART_DATA_MSK 0x000000ff -+#define UART_DATA_I_MSK 0xffffff00 -+#define UART_DATA_SFT 0 -+#define UART_DATA_HI 7 -+#define UART_DATA_SZ 8 -+#define DATA_RDY_IE_MSK 0x00000001 -+#define DATA_RDY_IE_I_MSK 0xfffffffe -+#define DATA_RDY_IE_SFT 0 -+#define DATA_RDY_IE_HI 0 -+#define DATA_RDY_IE_SZ 1 -+#define THR_EMPTY_IE_MSK 0x00000002 -+#define THR_EMPTY_IE_I_MSK 0xfffffffd -+#define THR_EMPTY_IE_SFT 1 -+#define THR_EMPTY_IE_HI 1 -+#define THR_EMPTY_IE_SZ 1 -+#define RX_LINESTS_IE_MSK 0x00000004 -+#define RX_LINESTS_IE_I_MSK 0xfffffffb -+#define RX_LINESTS_IE_SFT 2 -+#define RX_LINESTS_IE_HI 2 -+#define RX_LINESTS_IE_SZ 1 -+#define MDM_STS_IE_MSK 0x00000008 -+#define MDM_STS_IE_I_MSK 0xfffffff7 -+#define MDM_STS_IE_SFT 3 -+#define MDM_STS_IE_HI 3 -+#define MDM_STS_IE_SZ 1 -+#define DMA_RXEND_IE_MSK 0x00000040 -+#define DMA_RXEND_IE_I_MSK 0xffffffbf -+#define DMA_RXEND_IE_SFT 6 -+#define DMA_RXEND_IE_HI 6 -+#define DMA_RXEND_IE_SZ 1 -+#define DMA_TXEND_IE_MSK 0x00000080 -+#define DMA_TXEND_IE_I_MSK 0xffffff7f -+#define DMA_TXEND_IE_SFT 7 -+#define DMA_TXEND_IE_HI 7 -+#define DMA_TXEND_IE_SZ 1 -+#define FIFO_EN_MSK 0x00000001 -+#define FIFO_EN_I_MSK 0xfffffffe -+#define FIFO_EN_SFT 0 -+#define FIFO_EN_HI 0 -+#define FIFO_EN_SZ 1 -+#define RXFIFO_RST_MSK 0x00000002 -+#define RXFIFO_RST_I_MSK 0xfffffffd -+#define RXFIFO_RST_SFT 1 -+#define RXFIFO_RST_HI 1 -+#define RXFIFO_RST_SZ 1 -+#define TXFIFO_RST_MSK 0x00000004 -+#define TXFIFO_RST_I_MSK 0xfffffffb -+#define TXFIFO_RST_SFT 2 -+#define TXFIFO_RST_HI 2 -+#define TXFIFO_RST_SZ 1 -+#define DMA_MODE_MSK 0x00000008 -+#define DMA_MODE_I_MSK 0xfffffff7 -+#define DMA_MODE_SFT 3 -+#define DMA_MODE_HI 3 -+#define DMA_MODE_SZ 1 -+#define EN_AUTO_RTS_MSK 0x00000010 -+#define EN_AUTO_RTS_I_MSK 0xffffffef -+#define EN_AUTO_RTS_SFT 4 -+#define EN_AUTO_RTS_HI 4 -+#define EN_AUTO_RTS_SZ 1 -+#define EN_AUTO_CTS_MSK 0x00000020 -+#define EN_AUTO_CTS_I_MSK 0xffffffdf -+#define EN_AUTO_CTS_SFT 5 -+#define EN_AUTO_CTS_HI 5 -+#define EN_AUTO_CTS_SZ 1 -+#define RXFIFO_TRGLVL_MSK 0x000000c0 -+#define RXFIFO_TRGLVL_I_MSK 0xffffff3f -+#define RXFIFO_TRGLVL_SFT 6 -+#define RXFIFO_TRGLVL_HI 7 -+#define RXFIFO_TRGLVL_SZ 2 -+#define WORD_LEN_MSK 0x00000003 -+#define WORD_LEN_I_MSK 0xfffffffc -+#define WORD_LEN_SFT 0 -+#define WORD_LEN_HI 1 -+#define WORD_LEN_SZ 2 -+#define STOP_BIT_MSK 0x00000004 -+#define STOP_BIT_I_MSK 0xfffffffb -+#define STOP_BIT_SFT 2 -+#define STOP_BIT_HI 2 -+#define STOP_BIT_SZ 1 -+#define PARITY_EN_MSK 0x00000008 -+#define PARITY_EN_I_MSK 0xfffffff7 -+#define PARITY_EN_SFT 3 -+#define PARITY_EN_HI 3 -+#define PARITY_EN_SZ 1 -+#define EVEN_PARITY_MSK 0x00000010 -+#define EVEN_PARITY_I_MSK 0xffffffef -+#define EVEN_PARITY_SFT 4 -+#define EVEN_PARITY_HI 4 -+#define EVEN_PARITY_SZ 1 -+#define FORCE_PARITY_MSK 0x00000020 -+#define FORCE_PARITY_I_MSK 0xffffffdf -+#define FORCE_PARITY_SFT 5 -+#define FORCE_PARITY_HI 5 -+#define FORCE_PARITY_SZ 1 -+#define SET_BREAK_MSK 0x00000040 -+#define SET_BREAK_I_MSK 0xffffffbf -+#define SET_BREAK_SFT 6 -+#define SET_BREAK_HI 6 -+#define SET_BREAK_SZ 1 -+#define DLAB_MSK 0x00000080 -+#define DLAB_I_MSK 0xffffff7f -+#define DLAB_SFT 7 -+#define DLAB_HI 7 -+#define DLAB_SZ 1 -+#define DTR_MSK 0x00000001 -+#define DTR_I_MSK 0xfffffffe -+#define DTR_SFT 0 -+#define DTR_HI 0 -+#define DTR_SZ 1 -+#define RTS_MSK 0x00000002 -+#define RTS_I_MSK 0xfffffffd -+#define RTS_SFT 1 -+#define RTS_HI 1 -+#define RTS_SZ 1 -+#define OUT_1_MSK 0x00000004 -+#define OUT_1_I_MSK 0xfffffffb -+#define OUT_1_SFT 2 -+#define OUT_1_HI 2 -+#define OUT_1_SZ 1 -+#define OUT_2_MSK 0x00000008 -+#define OUT_2_I_MSK 0xfffffff7 -+#define OUT_2_SFT 3 -+#define OUT_2_HI 3 -+#define OUT_2_SZ 1 -+#define LOOP_BACK_MSK 0x00000010 -+#define LOOP_BACK_I_MSK 0xffffffef -+#define LOOP_BACK_SFT 4 -+#define LOOP_BACK_HI 4 -+#define LOOP_BACK_SZ 1 -+#define DATA_RDY_MSK 0x00000001 -+#define DATA_RDY_I_MSK 0xfffffffe -+#define DATA_RDY_SFT 0 -+#define DATA_RDY_HI 0 -+#define DATA_RDY_SZ 1 -+#define OVERRUN_ERR_MSK 0x00000002 -+#define OVERRUN_ERR_I_MSK 0xfffffffd -+#define OVERRUN_ERR_SFT 1 -+#define OVERRUN_ERR_HI 1 -+#define OVERRUN_ERR_SZ 1 -+#define PARITY_ERR_MSK 0x00000004 -+#define PARITY_ERR_I_MSK 0xfffffffb -+#define PARITY_ERR_SFT 2 -+#define PARITY_ERR_HI 2 -+#define PARITY_ERR_SZ 1 -+#define FRAMING_ERR_MSK 0x00000008 -+#define FRAMING_ERR_I_MSK 0xfffffff7 -+#define FRAMING_ERR_SFT 3 -+#define FRAMING_ERR_HI 3 -+#define FRAMING_ERR_SZ 1 -+#define BREAK_INT_MSK 0x00000010 -+#define BREAK_INT_I_MSK 0xffffffef -+#define BREAK_INT_SFT 4 -+#define BREAK_INT_HI 4 -+#define BREAK_INT_SZ 1 -+#define THR_EMPTY_MSK 0x00000020 -+#define THR_EMPTY_I_MSK 0xffffffdf -+#define THR_EMPTY_SFT 5 -+#define THR_EMPTY_HI 5 -+#define THR_EMPTY_SZ 1 -+#define TX_EMPTY_MSK 0x00000040 -+#define TX_EMPTY_I_MSK 0xffffffbf -+#define TX_EMPTY_SFT 6 -+#define TX_EMPTY_HI 6 -+#define TX_EMPTY_SZ 1 -+#define FIFODATA_ERR_MSK 0x00000080 -+#define FIFODATA_ERR_I_MSK 0xffffff7f -+#define FIFODATA_ERR_SFT 7 -+#define FIFODATA_ERR_HI 7 -+#define FIFODATA_ERR_SZ 1 -+#define DELTA_CTS_MSK 0x00000001 -+#define DELTA_CTS_I_MSK 0xfffffffe -+#define DELTA_CTS_SFT 0 -+#define DELTA_CTS_HI 0 -+#define DELTA_CTS_SZ 1 -+#define DELTA_DSR_MSK 0x00000002 -+#define DELTA_DSR_I_MSK 0xfffffffd -+#define DELTA_DSR_SFT 1 -+#define DELTA_DSR_HI 1 -+#define DELTA_DSR_SZ 1 -+#define TRAILEDGE_RI_MSK 0x00000004 -+#define TRAILEDGE_RI_I_MSK 0xfffffffb -+#define TRAILEDGE_RI_SFT 2 -+#define TRAILEDGE_RI_HI 2 -+#define TRAILEDGE_RI_SZ 1 -+#define DELTA_CD_MSK 0x00000008 -+#define DELTA_CD_I_MSK 0xfffffff7 -+#define DELTA_CD_SFT 3 -+#define DELTA_CD_HI 3 -+#define DELTA_CD_SZ 1 -+#define CTS_MSK 0x00000010 -+#define CTS_I_MSK 0xffffffef -+#define CTS_SFT 4 -+#define CTS_HI 4 -+#define CTS_SZ 1 -+#define DSR_MSK 0x00000020 -+#define DSR_I_MSK 0xffffffdf -+#define DSR_SFT 5 -+#define DSR_HI 5 -+#define DSR_SZ 1 -+#define RI_MSK 0x00000040 -+#define RI_I_MSK 0xffffffbf -+#define RI_SFT 6 -+#define RI_HI 6 -+#define RI_SZ 1 -+#define CD_MSK 0x00000080 -+#define CD_I_MSK 0xffffff7f -+#define CD_SFT 7 -+#define CD_HI 7 -+#define CD_SZ 1 -+#define BRDC_DIV_MSK 0x0000ffff -+#define BRDC_DIV_I_MSK 0xffff0000 -+#define BRDC_DIV_SFT 0 -+#define BRDC_DIV_HI 15 -+#define BRDC_DIV_SZ 16 -+#define RTHR_L_MSK 0x0000000f -+#define RTHR_L_I_MSK 0xfffffff0 -+#define RTHR_L_SFT 0 -+#define RTHR_L_HI 3 -+#define RTHR_L_SZ 4 -+#define RTHR_H_MSK 0x000000f0 -+#define RTHR_H_I_MSK 0xffffff0f -+#define RTHR_H_SFT 4 -+#define RTHR_H_HI 7 -+#define RTHR_H_SZ 4 -+#define INT_IDCODE_MSK 0x0000000f -+#define INT_IDCODE_I_MSK 0xfffffff0 -+#define INT_IDCODE_SFT 0 -+#define INT_IDCODE_HI 3 -+#define INT_IDCODE_SZ 4 -+#define FIFOS_ENABLED_MSK 0x000000c0 -+#define FIFOS_ENABLED_I_MSK 0xffffff3f -+#define FIFOS_ENABLED_SFT 6 -+#define FIFOS_ENABLED_HI 7 -+#define FIFOS_ENABLED_SZ 2 -+#define DAT_UART_DATA_MSK 0x000000ff -+#define DAT_UART_DATA_I_MSK 0xffffff00 -+#define DAT_UART_DATA_SFT 0 -+#define DAT_UART_DATA_HI 7 -+#define DAT_UART_DATA_SZ 8 -+#define DAT_DATA_RDY_IE_MSK 0x00000001 -+#define DAT_DATA_RDY_IE_I_MSK 0xfffffffe -+#define DAT_DATA_RDY_IE_SFT 0 -+#define DAT_DATA_RDY_IE_HI 0 -+#define DAT_DATA_RDY_IE_SZ 1 -+#define DAT_THR_EMPTY_IE_MSK 0x00000002 -+#define DAT_THR_EMPTY_IE_I_MSK 0xfffffffd -+#define DAT_THR_EMPTY_IE_SFT 1 -+#define DAT_THR_EMPTY_IE_HI 1 -+#define DAT_THR_EMPTY_IE_SZ 1 -+#define DAT_RX_LINESTS_IE_MSK 0x00000004 -+#define DAT_RX_LINESTS_IE_I_MSK 0xfffffffb -+#define DAT_RX_LINESTS_IE_SFT 2 -+#define DAT_RX_LINESTS_IE_HI 2 -+#define DAT_RX_LINESTS_IE_SZ 1 -+#define DAT_MDM_STS_IE_MSK 0x00000008 -+#define DAT_MDM_STS_IE_I_MSK 0xfffffff7 -+#define DAT_MDM_STS_IE_SFT 3 -+#define DAT_MDM_STS_IE_HI 3 -+#define DAT_MDM_STS_IE_SZ 1 -+#define DAT_DMA_RXEND_IE_MSK 0x00000040 -+#define DAT_DMA_RXEND_IE_I_MSK 0xffffffbf -+#define DAT_DMA_RXEND_IE_SFT 6 -+#define DAT_DMA_RXEND_IE_HI 6 -+#define DAT_DMA_RXEND_IE_SZ 1 -+#define DAT_DMA_TXEND_IE_MSK 0x00000080 -+#define DAT_DMA_TXEND_IE_I_MSK 0xffffff7f -+#define DAT_DMA_TXEND_IE_SFT 7 -+#define DAT_DMA_TXEND_IE_HI 7 -+#define DAT_DMA_TXEND_IE_SZ 1 -+#define DAT_FIFO_EN_MSK 0x00000001 -+#define DAT_FIFO_EN_I_MSK 0xfffffffe -+#define DAT_FIFO_EN_SFT 0 -+#define DAT_FIFO_EN_HI 0 -+#define DAT_FIFO_EN_SZ 1 -+#define DAT_RXFIFO_RST_MSK 0x00000002 -+#define DAT_RXFIFO_RST_I_MSK 0xfffffffd -+#define DAT_RXFIFO_RST_SFT 1 -+#define DAT_RXFIFO_RST_HI 1 -+#define DAT_RXFIFO_RST_SZ 1 -+#define DAT_TXFIFO_RST_MSK 0x00000004 -+#define DAT_TXFIFO_RST_I_MSK 0xfffffffb -+#define DAT_TXFIFO_RST_SFT 2 -+#define DAT_TXFIFO_RST_HI 2 -+#define DAT_TXFIFO_RST_SZ 1 -+#define DAT_DMA_MODE_MSK 0x00000008 -+#define DAT_DMA_MODE_I_MSK 0xfffffff7 -+#define DAT_DMA_MODE_SFT 3 -+#define DAT_DMA_MODE_HI 3 -+#define DAT_DMA_MODE_SZ 1 -+#define DAT_EN_AUTO_RTS_MSK 0x00000010 -+#define DAT_EN_AUTO_RTS_I_MSK 0xffffffef -+#define DAT_EN_AUTO_RTS_SFT 4 -+#define DAT_EN_AUTO_RTS_HI 4 -+#define DAT_EN_AUTO_RTS_SZ 1 -+#define DAT_EN_AUTO_CTS_MSK 0x00000020 -+#define DAT_EN_AUTO_CTS_I_MSK 0xffffffdf -+#define DAT_EN_AUTO_CTS_SFT 5 -+#define DAT_EN_AUTO_CTS_HI 5 -+#define DAT_EN_AUTO_CTS_SZ 1 -+#define DAT_RXFIFO_TRGLVL_MSK 0x000000c0 -+#define DAT_RXFIFO_TRGLVL_I_MSK 0xffffff3f -+#define DAT_RXFIFO_TRGLVL_SFT 6 -+#define DAT_RXFIFO_TRGLVL_HI 7 -+#define DAT_RXFIFO_TRGLVL_SZ 2 -+#define DAT_WORD_LEN_MSK 0x00000003 -+#define DAT_WORD_LEN_I_MSK 0xfffffffc -+#define DAT_WORD_LEN_SFT 0 -+#define DAT_WORD_LEN_HI 1 -+#define DAT_WORD_LEN_SZ 2 -+#define DAT_STOP_BIT_MSK 0x00000004 -+#define DAT_STOP_BIT_I_MSK 0xfffffffb -+#define DAT_STOP_BIT_SFT 2 -+#define DAT_STOP_BIT_HI 2 -+#define DAT_STOP_BIT_SZ 1 -+#define DAT_PARITY_EN_MSK 0x00000008 -+#define DAT_PARITY_EN_I_MSK 0xfffffff7 -+#define DAT_PARITY_EN_SFT 3 -+#define DAT_PARITY_EN_HI 3 -+#define DAT_PARITY_EN_SZ 1 -+#define DAT_EVEN_PARITY_MSK 0x00000010 -+#define DAT_EVEN_PARITY_I_MSK 0xffffffef -+#define DAT_EVEN_PARITY_SFT 4 -+#define DAT_EVEN_PARITY_HI 4 -+#define DAT_EVEN_PARITY_SZ 1 -+#define DAT_FORCE_PARITY_MSK 0x00000020 -+#define DAT_FORCE_PARITY_I_MSK 0xffffffdf -+#define DAT_FORCE_PARITY_SFT 5 -+#define DAT_FORCE_PARITY_HI 5 -+#define DAT_FORCE_PARITY_SZ 1 -+#define DAT_SET_BREAK_MSK 0x00000040 -+#define DAT_SET_BREAK_I_MSK 0xffffffbf -+#define DAT_SET_BREAK_SFT 6 -+#define DAT_SET_BREAK_HI 6 -+#define DAT_SET_BREAK_SZ 1 -+#define DAT_DLAB_MSK 0x00000080 -+#define DAT_DLAB_I_MSK 0xffffff7f -+#define DAT_DLAB_SFT 7 -+#define DAT_DLAB_HI 7 -+#define DAT_DLAB_SZ 1 -+#define DAT_DTR_MSK 0x00000001 -+#define DAT_DTR_I_MSK 0xfffffffe -+#define DAT_DTR_SFT 0 -+#define DAT_DTR_HI 0 -+#define DAT_DTR_SZ 1 -+#define DAT_RTS_MSK 0x00000002 -+#define DAT_RTS_I_MSK 0xfffffffd -+#define DAT_RTS_SFT 1 -+#define DAT_RTS_HI 1 -+#define DAT_RTS_SZ 1 -+#define DAT_OUT_1_MSK 0x00000004 -+#define DAT_OUT_1_I_MSK 0xfffffffb -+#define DAT_OUT_1_SFT 2 -+#define DAT_OUT_1_HI 2 -+#define DAT_OUT_1_SZ 1 -+#define DAT_OUT_2_MSK 0x00000008 -+#define DAT_OUT_2_I_MSK 0xfffffff7 -+#define DAT_OUT_2_SFT 3 -+#define DAT_OUT_2_HI 3 -+#define DAT_OUT_2_SZ 1 -+#define DAT_LOOP_BACK_MSK 0x00000010 -+#define DAT_LOOP_BACK_I_MSK 0xffffffef -+#define DAT_LOOP_BACK_SFT 4 -+#define DAT_LOOP_BACK_HI 4 -+#define DAT_LOOP_BACK_SZ 1 -+#define DAT_DATA_RDY_MSK 0x00000001 -+#define DAT_DATA_RDY_I_MSK 0xfffffffe -+#define DAT_DATA_RDY_SFT 0 -+#define DAT_DATA_RDY_HI 0 -+#define DAT_DATA_RDY_SZ 1 -+#define DAT_OVERRUN_ERR_MSK 0x00000002 -+#define DAT_OVERRUN_ERR_I_MSK 0xfffffffd -+#define DAT_OVERRUN_ERR_SFT 1 -+#define DAT_OVERRUN_ERR_HI 1 -+#define DAT_OVERRUN_ERR_SZ 1 -+#define DAT_PARITY_ERR_MSK 0x00000004 -+#define DAT_PARITY_ERR_I_MSK 0xfffffffb -+#define DAT_PARITY_ERR_SFT 2 -+#define DAT_PARITY_ERR_HI 2 -+#define DAT_PARITY_ERR_SZ 1 -+#define DAT_FRAMING_ERR_MSK 0x00000008 -+#define DAT_FRAMING_ERR_I_MSK 0xfffffff7 -+#define DAT_FRAMING_ERR_SFT 3 -+#define DAT_FRAMING_ERR_HI 3 -+#define DAT_FRAMING_ERR_SZ 1 -+#define DAT_BREAK_INT_MSK 0x00000010 -+#define DAT_BREAK_INT_I_MSK 0xffffffef -+#define DAT_BREAK_INT_SFT 4 -+#define DAT_BREAK_INT_HI 4 -+#define DAT_BREAK_INT_SZ 1 -+#define DAT_THR_EMPTY_MSK 0x00000020 -+#define DAT_THR_EMPTY_I_MSK 0xffffffdf -+#define DAT_THR_EMPTY_SFT 5 -+#define DAT_THR_EMPTY_HI 5 -+#define DAT_THR_EMPTY_SZ 1 -+#define DAT_TX_EMPTY_MSK 0x00000040 -+#define DAT_TX_EMPTY_I_MSK 0xffffffbf -+#define DAT_TX_EMPTY_SFT 6 -+#define DAT_TX_EMPTY_HI 6 -+#define DAT_TX_EMPTY_SZ 1 -+#define DAT_FIFODATA_ERR_MSK 0x00000080 -+#define DAT_FIFODATA_ERR_I_MSK 0xffffff7f -+#define DAT_FIFODATA_ERR_SFT 7 -+#define DAT_FIFODATA_ERR_HI 7 -+#define DAT_FIFODATA_ERR_SZ 1 -+#define DAT_DELTA_CTS_MSK 0x00000001 -+#define DAT_DELTA_CTS_I_MSK 0xfffffffe -+#define DAT_DELTA_CTS_SFT 0 -+#define DAT_DELTA_CTS_HI 0 -+#define DAT_DELTA_CTS_SZ 1 -+#define DAT_DELTA_DSR_MSK 0x00000002 -+#define DAT_DELTA_DSR_I_MSK 0xfffffffd -+#define DAT_DELTA_DSR_SFT 1 -+#define DAT_DELTA_DSR_HI 1 -+#define DAT_DELTA_DSR_SZ 1 -+#define DAT_TRAILEDGE_RI_MSK 0x00000004 -+#define DAT_TRAILEDGE_RI_I_MSK 0xfffffffb -+#define DAT_TRAILEDGE_RI_SFT 2 -+#define DAT_TRAILEDGE_RI_HI 2 -+#define DAT_TRAILEDGE_RI_SZ 1 -+#define DAT_DELTA_CD_MSK 0x00000008 -+#define DAT_DELTA_CD_I_MSK 0xfffffff7 -+#define DAT_DELTA_CD_SFT 3 -+#define DAT_DELTA_CD_HI 3 -+#define DAT_DELTA_CD_SZ 1 -+#define DAT_CTS_MSK 0x00000010 -+#define DAT_CTS_I_MSK 0xffffffef -+#define DAT_CTS_SFT 4 -+#define DAT_CTS_HI 4 -+#define DAT_CTS_SZ 1 -+#define DAT_DSR_MSK 0x00000020 -+#define DAT_DSR_I_MSK 0xffffffdf -+#define DAT_DSR_SFT 5 -+#define DAT_DSR_HI 5 -+#define DAT_DSR_SZ 1 -+#define DAT_RI_MSK 0x00000040 -+#define DAT_RI_I_MSK 0xffffffbf -+#define DAT_RI_SFT 6 -+#define DAT_RI_HI 6 -+#define DAT_RI_SZ 1 -+#define DAT_CD_MSK 0x00000080 -+#define DAT_CD_I_MSK 0xffffff7f -+#define DAT_CD_SFT 7 -+#define DAT_CD_HI 7 -+#define DAT_CD_SZ 1 -+#define DAT_BRDC_DIV_MSK 0x0000ffff -+#define DAT_BRDC_DIV_I_MSK 0xffff0000 -+#define DAT_BRDC_DIV_SFT 0 -+#define DAT_BRDC_DIV_HI 15 -+#define DAT_BRDC_DIV_SZ 16 -+#define DAT_RTHR_L_MSK 0x0000000f -+#define DAT_RTHR_L_I_MSK 0xfffffff0 -+#define DAT_RTHR_L_SFT 0 -+#define DAT_RTHR_L_HI 3 -+#define DAT_RTHR_L_SZ 4 -+#define DAT_RTHR_H_MSK 0x000000f0 -+#define DAT_RTHR_H_I_MSK 0xffffff0f -+#define DAT_RTHR_H_SFT 4 -+#define DAT_RTHR_H_HI 7 -+#define DAT_RTHR_H_SZ 4 -+#define DAT_INT_IDCODE_MSK 0x0000000f -+#define DAT_INT_IDCODE_I_MSK 0xfffffff0 -+#define DAT_INT_IDCODE_SFT 0 -+#define DAT_INT_IDCODE_HI 3 -+#define DAT_INT_IDCODE_SZ 4 -+#define DAT_FIFOS_ENABLED_MSK 0x000000c0 -+#define DAT_FIFOS_ENABLED_I_MSK 0xffffff3f -+#define DAT_FIFOS_ENABLED_SFT 6 -+#define DAT_FIFOS_ENABLED_HI 7 -+#define DAT_FIFOS_ENABLED_SZ 2 -+#define MASK_TOP_MSK 0xffffffff -+#define MASK_TOP_I_MSK 0x00000000 -+#define MASK_TOP_SFT 0 -+#define MASK_TOP_HI 31 -+#define MASK_TOP_SZ 32 -+#define INT_MODE_MSK 0xffffffff -+#define INT_MODE_I_MSK 0x00000000 -+#define INT_MODE_SFT 0 -+#define INT_MODE_HI 31 -+#define INT_MODE_SZ 32 -+#define IRQ_PHY_0_MSK 0x00000001 -+#define IRQ_PHY_0_I_MSK 0xfffffffe -+#define IRQ_PHY_0_SFT 0 -+#define IRQ_PHY_0_HI 0 -+#define IRQ_PHY_0_SZ 1 -+#define IRQ_PHY_1_MSK 0x00000002 -+#define IRQ_PHY_1_I_MSK 0xfffffffd -+#define IRQ_PHY_1_SFT 1 -+#define IRQ_PHY_1_HI 1 -+#define IRQ_PHY_1_SZ 1 -+#define IRQ_SDIO_MSK 0x00000004 -+#define IRQ_SDIO_I_MSK 0xfffffffb -+#define IRQ_SDIO_SFT 2 -+#define IRQ_SDIO_HI 2 -+#define IRQ_SDIO_SZ 1 -+#define IRQ_BEACON_DONE_MSK 0x00000008 -+#define IRQ_BEACON_DONE_I_MSK 0xfffffff7 -+#define IRQ_BEACON_DONE_SFT 3 -+#define IRQ_BEACON_DONE_HI 3 -+#define IRQ_BEACON_DONE_SZ 1 -+#define IRQ_BEACON_MSK 0x00000010 -+#define IRQ_BEACON_I_MSK 0xffffffef -+#define IRQ_BEACON_SFT 4 -+#define IRQ_BEACON_HI 4 -+#define IRQ_BEACON_SZ 1 -+#define IRQ_PRE_BEACON_MSK 0x00000020 -+#define IRQ_PRE_BEACON_I_MSK 0xffffffdf -+#define IRQ_PRE_BEACON_SFT 5 -+#define IRQ_PRE_BEACON_HI 5 -+#define IRQ_PRE_BEACON_SZ 1 -+#define IRQ_EDCA0_TX_DONE_MSK 0x00000040 -+#define IRQ_EDCA0_TX_DONE_I_MSK 0xffffffbf -+#define IRQ_EDCA0_TX_DONE_SFT 6 -+#define IRQ_EDCA0_TX_DONE_HI 6 -+#define IRQ_EDCA0_TX_DONE_SZ 1 -+#define IRQ_EDCA1_TX_DONE_MSK 0x00000080 -+#define IRQ_EDCA1_TX_DONE_I_MSK 0xffffff7f -+#define IRQ_EDCA1_TX_DONE_SFT 7 -+#define IRQ_EDCA1_TX_DONE_HI 7 -+#define IRQ_EDCA1_TX_DONE_SZ 1 -+#define IRQ_EDCA2_TX_DONE_MSK 0x00000100 -+#define IRQ_EDCA2_TX_DONE_I_MSK 0xfffffeff -+#define IRQ_EDCA2_TX_DONE_SFT 8 -+#define IRQ_EDCA2_TX_DONE_HI 8 -+#define IRQ_EDCA2_TX_DONE_SZ 1 -+#define IRQ_EDCA3_TX_DONE_MSK 0x00000200 -+#define IRQ_EDCA3_TX_DONE_I_MSK 0xfffffdff -+#define IRQ_EDCA3_TX_DONE_SFT 9 -+#define IRQ_EDCA3_TX_DONE_HI 9 -+#define IRQ_EDCA3_TX_DONE_SZ 1 -+#define IRQ_EDCA4_TX_DONE_MSK 0x00000400 -+#define IRQ_EDCA4_TX_DONE_I_MSK 0xfffffbff -+#define IRQ_EDCA4_TX_DONE_SFT 10 -+#define IRQ_EDCA4_TX_DONE_HI 10 -+#define IRQ_EDCA4_TX_DONE_SZ 1 -+#define IRQ_BEACON_DTIM_MSK 0x00001000 -+#define IRQ_BEACON_DTIM_I_MSK 0xffffefff -+#define IRQ_BEACON_DTIM_SFT 12 -+#define IRQ_BEACON_DTIM_HI 12 -+#define IRQ_BEACON_DTIM_SZ 1 -+#define IRQ_EDCA0_LOWTHOLD_INT_MSK 0x00002000 -+#define IRQ_EDCA0_LOWTHOLD_INT_I_MSK 0xffffdfff -+#define IRQ_EDCA0_LOWTHOLD_INT_SFT 13 -+#define IRQ_EDCA0_LOWTHOLD_INT_HI 13 -+#define IRQ_EDCA0_LOWTHOLD_INT_SZ 1 -+#define IRQ_EDCA1_LOWTHOLD_INT_MSK 0x00004000 -+#define IRQ_EDCA1_LOWTHOLD_INT_I_MSK 0xffffbfff -+#define IRQ_EDCA1_LOWTHOLD_INT_SFT 14 -+#define IRQ_EDCA1_LOWTHOLD_INT_HI 14 -+#define IRQ_EDCA1_LOWTHOLD_INT_SZ 1 -+#define IRQ_EDCA2_LOWTHOLD_INT_MSK 0x00008000 -+#define IRQ_EDCA2_LOWTHOLD_INT_I_MSK 0xffff7fff -+#define IRQ_EDCA2_LOWTHOLD_INT_SFT 15 -+#define IRQ_EDCA2_LOWTHOLD_INT_HI 15 -+#define IRQ_EDCA2_LOWTHOLD_INT_SZ 1 -+#define IRQ_EDCA3_LOWTHOLD_INT_MSK 0x00010000 -+#define IRQ_EDCA3_LOWTHOLD_INT_I_MSK 0xfffeffff -+#define IRQ_EDCA3_LOWTHOLD_INT_SFT 16 -+#define IRQ_EDCA3_LOWTHOLD_INT_HI 16 -+#define IRQ_EDCA3_LOWTHOLD_INT_SZ 1 -+#define IRQ_FENCE_HIT_INT_MSK 0x00020000 -+#define IRQ_FENCE_HIT_INT_I_MSK 0xfffdffff -+#define IRQ_FENCE_HIT_INT_SFT 17 -+#define IRQ_FENCE_HIT_INT_HI 17 -+#define IRQ_FENCE_HIT_INT_SZ 1 -+#define IRQ_ILL_ADDR_INT_MSK 0x00040000 -+#define IRQ_ILL_ADDR_INT_I_MSK 0xfffbffff -+#define IRQ_ILL_ADDR_INT_SFT 18 -+#define IRQ_ILL_ADDR_INT_HI 18 -+#define IRQ_ILL_ADDR_INT_SZ 1 -+#define IRQ_MBOX_MSK 0x00080000 -+#define IRQ_MBOX_I_MSK 0xfff7ffff -+#define IRQ_MBOX_SFT 19 -+#define IRQ_MBOX_HI 19 -+#define IRQ_MBOX_SZ 1 -+#define IRQ_US_TIMER0_MSK 0x00100000 -+#define IRQ_US_TIMER0_I_MSK 0xffefffff -+#define IRQ_US_TIMER0_SFT 20 -+#define IRQ_US_TIMER0_HI 20 -+#define IRQ_US_TIMER0_SZ 1 -+#define IRQ_US_TIMER1_MSK 0x00200000 -+#define IRQ_US_TIMER1_I_MSK 0xffdfffff -+#define IRQ_US_TIMER1_SFT 21 -+#define IRQ_US_TIMER1_HI 21 -+#define IRQ_US_TIMER1_SZ 1 -+#define IRQ_US_TIMER2_MSK 0x00400000 -+#define IRQ_US_TIMER2_I_MSK 0xffbfffff -+#define IRQ_US_TIMER2_SFT 22 -+#define IRQ_US_TIMER2_HI 22 -+#define IRQ_US_TIMER2_SZ 1 -+#define IRQ_US_TIMER3_MSK 0x00800000 -+#define IRQ_US_TIMER3_I_MSK 0xff7fffff -+#define IRQ_US_TIMER3_SFT 23 -+#define IRQ_US_TIMER3_HI 23 -+#define IRQ_US_TIMER3_SZ 1 -+#define IRQ_MS_TIMER0_MSK 0x01000000 -+#define IRQ_MS_TIMER0_I_MSK 0xfeffffff -+#define IRQ_MS_TIMER0_SFT 24 -+#define IRQ_MS_TIMER0_HI 24 -+#define IRQ_MS_TIMER0_SZ 1 -+#define IRQ_MS_TIMER1_MSK 0x02000000 -+#define IRQ_MS_TIMER1_I_MSK 0xfdffffff -+#define IRQ_MS_TIMER1_SFT 25 -+#define IRQ_MS_TIMER1_HI 25 -+#define IRQ_MS_TIMER1_SZ 1 -+#define IRQ_MS_TIMER2_MSK 0x04000000 -+#define IRQ_MS_TIMER2_I_MSK 0xfbffffff -+#define IRQ_MS_TIMER2_SFT 26 -+#define IRQ_MS_TIMER2_HI 26 -+#define IRQ_MS_TIMER2_SZ 1 -+#define IRQ_MS_TIMER3_MSK 0x08000000 -+#define IRQ_MS_TIMER3_I_MSK 0xf7ffffff -+#define IRQ_MS_TIMER3_SFT 27 -+#define IRQ_MS_TIMER3_HI 27 -+#define IRQ_MS_TIMER3_SZ 1 -+#define IRQ_TX_LIMIT_INT_MSK 0x10000000 -+#define IRQ_TX_LIMIT_INT_I_MSK 0xefffffff -+#define IRQ_TX_LIMIT_INT_SFT 28 -+#define IRQ_TX_LIMIT_INT_HI 28 -+#define IRQ_TX_LIMIT_INT_SZ 1 -+#define IRQ_DMA0_MSK 0x20000000 -+#define IRQ_DMA0_I_MSK 0xdfffffff -+#define IRQ_DMA0_SFT 29 -+#define IRQ_DMA0_HI 29 -+#define IRQ_DMA0_SZ 1 -+#define IRQ_CO_DMA_MSK 0x40000000 -+#define IRQ_CO_DMA_I_MSK 0xbfffffff -+#define IRQ_CO_DMA_SFT 30 -+#define IRQ_CO_DMA_HI 30 -+#define IRQ_CO_DMA_SZ 1 -+#define IRQ_PERI_GROUP_MSK 0x80000000 -+#define IRQ_PERI_GROUP_I_MSK 0x7fffffff -+#define IRQ_PERI_GROUP_SFT 31 -+#define IRQ_PERI_GROUP_HI 31 -+#define IRQ_PERI_GROUP_SZ 1 -+#define FIQ_STATUS_MSK 0xffffffff -+#define FIQ_STATUS_I_MSK 0x00000000 -+#define FIQ_STATUS_SFT 0 -+#define FIQ_STATUS_HI 31 -+#define FIQ_STATUS_SZ 32 -+#define IRQ_RAW_MSK 0xffffffff -+#define IRQ_RAW_I_MSK 0x00000000 -+#define IRQ_RAW_SFT 0 -+#define IRQ_RAW_HI 31 -+#define IRQ_RAW_SZ 32 -+#define FIQ_RAW_MSK 0xffffffff -+#define FIQ_RAW_I_MSK 0x00000000 -+#define FIQ_RAW_SFT 0 -+#define FIQ_RAW_HI 31 -+#define FIQ_RAW_SZ 32 -+#define INT_PERI_MASK_MSK 0xffffffff -+#define INT_PERI_MASK_I_MSK 0x00000000 -+#define INT_PERI_MASK_SFT 0 -+#define INT_PERI_MASK_HI 31 -+#define INT_PERI_MASK_SZ 32 -+#define PERI_RTC_MSK 0x00000001 -+#define PERI_RTC_I_MSK 0xfffffffe -+#define PERI_RTC_SFT 0 -+#define PERI_RTC_HI 0 -+#define PERI_RTC_SZ 1 -+#define IRQ_UART0_TX_MSK 0x00000002 -+#define IRQ_UART0_TX_I_MSK 0xfffffffd -+#define IRQ_UART0_TX_SFT 1 -+#define IRQ_UART0_TX_HI 1 -+#define IRQ_UART0_TX_SZ 1 -+#define IRQ_UART0_RX_MSK 0x00000004 -+#define IRQ_UART0_RX_I_MSK 0xfffffffb -+#define IRQ_UART0_RX_SFT 2 -+#define IRQ_UART0_RX_HI 2 -+#define IRQ_UART0_RX_SZ 1 -+#define PERI_GPI_2_MSK 0x00000008 -+#define PERI_GPI_2_I_MSK 0xfffffff7 -+#define PERI_GPI_2_SFT 3 -+#define PERI_GPI_2_HI 3 -+#define PERI_GPI_2_SZ 1 -+#define IRQ_SPI_IPC_MSK 0x00000010 -+#define IRQ_SPI_IPC_I_MSK 0xffffffef -+#define IRQ_SPI_IPC_SFT 4 -+#define IRQ_SPI_IPC_HI 4 -+#define IRQ_SPI_IPC_SZ 1 -+#define PERI_GPI_1_0_MSK 0x00000060 -+#define PERI_GPI_1_0_I_MSK 0xffffff9f -+#define PERI_GPI_1_0_SFT 5 -+#define PERI_GPI_1_0_HI 6 -+#define PERI_GPI_1_0_SZ 2 -+#define SCRT_INT_1_MSK 0x00000080 -+#define SCRT_INT_1_I_MSK 0xffffff7f -+#define SCRT_INT_1_SFT 7 -+#define SCRT_INT_1_HI 7 -+#define SCRT_INT_1_SZ 1 -+#define MMU_ALC_ERR_MSK 0x00000100 -+#define MMU_ALC_ERR_I_MSK 0xfffffeff -+#define MMU_ALC_ERR_SFT 8 -+#define MMU_ALC_ERR_HI 8 -+#define MMU_ALC_ERR_SZ 1 -+#define MMU_RLS_ERR_MSK 0x00000200 -+#define MMU_RLS_ERR_I_MSK 0xfffffdff -+#define MMU_RLS_ERR_SFT 9 -+#define MMU_RLS_ERR_HI 9 -+#define MMU_RLS_ERR_SZ 1 -+#define ID_MNG_INT_1_MSK 0x00000400 -+#define ID_MNG_INT_1_I_MSK 0xfffffbff -+#define ID_MNG_INT_1_SFT 10 -+#define ID_MNG_INT_1_HI 10 -+#define ID_MNG_INT_1_SZ 1 -+#define MBOX_INT_1_MSK 0x00000800 -+#define MBOX_INT_1_I_MSK 0xfffff7ff -+#define MBOX_INT_1_SFT 11 -+#define MBOX_INT_1_HI 11 -+#define MBOX_INT_1_SZ 1 -+#define MBOX_INT_2_MSK 0x00001000 -+#define MBOX_INT_2_I_MSK 0xffffefff -+#define MBOX_INT_2_SFT 12 -+#define MBOX_INT_2_HI 12 -+#define MBOX_INT_2_SZ 1 -+#define MBOX_INT_3_MSK 0x00002000 -+#define MBOX_INT_3_I_MSK 0xffffdfff -+#define MBOX_INT_3_SFT 13 -+#define MBOX_INT_3_HI 13 -+#define MBOX_INT_3_SZ 1 -+#define HCI_INT_1_MSK 0x00004000 -+#define HCI_INT_1_I_MSK 0xffffbfff -+#define HCI_INT_1_SFT 14 -+#define HCI_INT_1_HI 14 -+#define HCI_INT_1_SZ 1 -+#define UART_RX_TIMEOUT_MSK 0x00008000 -+#define UART_RX_TIMEOUT_I_MSK 0xffff7fff -+#define UART_RX_TIMEOUT_SFT 15 -+#define UART_RX_TIMEOUT_HI 15 -+#define UART_RX_TIMEOUT_SZ 1 -+#define UART_MULTI_IRQ_MSK 0x00010000 -+#define UART_MULTI_IRQ_I_MSK 0xfffeffff -+#define UART_MULTI_IRQ_SFT 16 -+#define UART_MULTI_IRQ_HI 16 -+#define UART_MULTI_IRQ_SZ 1 -+#define ID_MNG_INT_2_MSK 0x00020000 -+#define ID_MNG_INT_2_I_MSK 0xfffdffff -+#define ID_MNG_INT_2_SFT 17 -+#define ID_MNG_INT_2_HI 17 -+#define ID_MNG_INT_2_SZ 1 -+#define DMN_NOHIT_INT_MSK 0x00040000 -+#define DMN_NOHIT_INT_I_MSK 0xfffbffff -+#define DMN_NOHIT_INT_SFT 18 -+#define DMN_NOHIT_INT_HI 18 -+#define DMN_NOHIT_INT_SZ 1 -+#define ID_THOLD_RX_MSK 0x00080000 -+#define ID_THOLD_RX_I_MSK 0xfff7ffff -+#define ID_THOLD_RX_SFT 19 -+#define ID_THOLD_RX_HI 19 -+#define ID_THOLD_RX_SZ 1 -+#define ID_THOLD_TX_MSK 0x00100000 -+#define ID_THOLD_TX_I_MSK 0xffefffff -+#define ID_THOLD_TX_SFT 20 -+#define ID_THOLD_TX_HI 20 -+#define ID_THOLD_TX_SZ 1 -+#define ID_DOUBLE_RLS_MSK 0x00200000 -+#define ID_DOUBLE_RLS_I_MSK 0xffdfffff -+#define ID_DOUBLE_RLS_SFT 21 -+#define ID_DOUBLE_RLS_HI 21 -+#define ID_DOUBLE_RLS_SZ 1 -+#define RX_ID_LEN_THOLD_MSK 0x00400000 -+#define RX_ID_LEN_THOLD_I_MSK 0xffbfffff -+#define RX_ID_LEN_THOLD_SFT 22 -+#define RX_ID_LEN_THOLD_HI 22 -+#define RX_ID_LEN_THOLD_SZ 1 -+#define TX_ID_LEN_THOLD_MSK 0x00800000 -+#define TX_ID_LEN_THOLD_I_MSK 0xff7fffff -+#define TX_ID_LEN_THOLD_SFT 23 -+#define TX_ID_LEN_THOLD_HI 23 -+#define TX_ID_LEN_THOLD_SZ 1 -+#define ALL_ID_LEN_THOLD_MSK 0x01000000 -+#define ALL_ID_LEN_THOLD_I_MSK 0xfeffffff -+#define ALL_ID_LEN_THOLD_SFT 24 -+#define ALL_ID_LEN_THOLD_HI 24 -+#define ALL_ID_LEN_THOLD_SZ 1 -+#define DMN_MCU_INT_MSK 0x02000000 -+#define DMN_MCU_INT_I_MSK 0xfdffffff -+#define DMN_MCU_INT_SFT 25 -+#define DMN_MCU_INT_HI 25 -+#define DMN_MCU_INT_SZ 1 -+#define IRQ_DAT_UART_TX_MSK 0x04000000 -+#define IRQ_DAT_UART_TX_I_MSK 0xfbffffff -+#define IRQ_DAT_UART_TX_SFT 26 -+#define IRQ_DAT_UART_TX_HI 26 -+#define IRQ_DAT_UART_TX_SZ 1 -+#define IRQ_DAT_UART_RX_MSK 0x08000000 -+#define IRQ_DAT_UART_RX_I_MSK 0xf7ffffff -+#define IRQ_DAT_UART_RX_SFT 27 -+#define IRQ_DAT_UART_RX_HI 27 -+#define IRQ_DAT_UART_RX_SZ 1 -+#define DAT_UART_RX_TIMEOUT_MSK 0x10000000 -+#define DAT_UART_RX_TIMEOUT_I_MSK 0xefffffff -+#define DAT_UART_RX_TIMEOUT_SFT 28 -+#define DAT_UART_RX_TIMEOUT_HI 28 -+#define DAT_UART_RX_TIMEOUT_SZ 1 -+#define DAT_UART_MULTI_IRQ_MSK 0x20000000 -+#define DAT_UART_MULTI_IRQ_I_MSK 0xdfffffff -+#define DAT_UART_MULTI_IRQ_SFT 29 -+#define DAT_UART_MULTI_IRQ_HI 29 -+#define DAT_UART_MULTI_IRQ_SZ 1 -+#define ALR_ABT_NOCHG_INT_IRQ_MSK 0x40000000 -+#define ALR_ABT_NOCHG_INT_IRQ_I_MSK 0xbfffffff -+#define ALR_ABT_NOCHG_INT_IRQ_SFT 30 -+#define ALR_ABT_NOCHG_INT_IRQ_HI 30 -+#define ALR_ABT_NOCHG_INT_IRQ_SZ 1 -+#define TBLNEQ_MNGPKT_INT_IRQ_MSK 0x80000000 -+#define TBLNEQ_MNGPKT_INT_IRQ_I_MSK 0x7fffffff -+#define TBLNEQ_MNGPKT_INT_IRQ_SFT 31 -+#define TBLNEQ_MNGPKT_INT_IRQ_HI 31 -+#define TBLNEQ_MNGPKT_INT_IRQ_SZ 1 -+#define INTR_PERI_RAW_MSK 0xffffffff -+#define INTR_PERI_RAW_I_MSK 0x00000000 -+#define INTR_PERI_RAW_SFT 0 -+#define INTR_PERI_RAW_HI 31 -+#define INTR_PERI_RAW_SZ 32 -+#define INTR_GPI00_CFG_MSK 0x00000003 -+#define INTR_GPI00_CFG_I_MSK 0xfffffffc -+#define INTR_GPI00_CFG_SFT 0 -+#define INTR_GPI00_CFG_HI 1 -+#define INTR_GPI00_CFG_SZ 2 -+#define INTR_GPI01_CFG_MSK 0x0000000c -+#define INTR_GPI01_CFG_I_MSK 0xfffffff3 -+#define INTR_GPI01_CFG_SFT 2 -+#define INTR_GPI01_CFG_HI 3 -+#define INTR_GPI01_CFG_SZ 2 -+#define SYS_RST_INT_MSK 0x00000001 -+#define SYS_RST_INT_I_MSK 0xfffffffe -+#define SYS_RST_INT_SFT 0 -+#define SYS_RST_INT_HI 0 -+#define SYS_RST_INT_SZ 1 -+#define SPI_IPC_ADDR_MSK 0xffffffff -+#define SPI_IPC_ADDR_I_MSK 0x00000000 -+#define SPI_IPC_ADDR_SFT 0 -+#define SPI_IPC_ADDR_HI 31 -+#define SPI_IPC_ADDR_SZ 32 -+#define SD_MASK_TOP_MSK 0xffffffff -+#define SD_MASK_TOP_I_MSK 0x00000000 -+#define SD_MASK_TOP_SFT 0 -+#define SD_MASK_TOP_HI 31 -+#define SD_MASK_TOP_SZ 32 -+#define IRQ_PHY_0_SD_MSK 0x00000001 -+#define IRQ_PHY_0_SD_I_MSK 0xfffffffe -+#define IRQ_PHY_0_SD_SFT 0 -+#define IRQ_PHY_0_SD_HI 0 -+#define IRQ_PHY_0_SD_SZ 1 -+#define IRQ_PHY_1_SD_MSK 0x00000002 -+#define IRQ_PHY_1_SD_I_MSK 0xfffffffd -+#define IRQ_PHY_1_SD_SFT 1 -+#define IRQ_PHY_1_SD_HI 1 -+#define IRQ_PHY_1_SD_SZ 1 -+#define IRQ_SDIO_SD_MSK 0x00000004 -+#define IRQ_SDIO_SD_I_MSK 0xfffffffb -+#define IRQ_SDIO_SD_SFT 2 -+#define IRQ_SDIO_SD_HI 2 -+#define IRQ_SDIO_SD_SZ 1 -+#define IRQ_BEACON_DONE_SD_MSK 0x00000008 -+#define IRQ_BEACON_DONE_SD_I_MSK 0xfffffff7 -+#define IRQ_BEACON_DONE_SD_SFT 3 -+#define IRQ_BEACON_DONE_SD_HI 3 -+#define IRQ_BEACON_DONE_SD_SZ 1 -+#define IRQ_BEACON_SD_MSK 0x00000010 -+#define IRQ_BEACON_SD_I_MSK 0xffffffef -+#define IRQ_BEACON_SD_SFT 4 -+#define IRQ_BEACON_SD_HI 4 -+#define IRQ_BEACON_SD_SZ 1 -+#define IRQ_PRE_BEACON_SD_MSK 0x00000020 -+#define IRQ_PRE_BEACON_SD_I_MSK 0xffffffdf -+#define IRQ_PRE_BEACON_SD_SFT 5 -+#define IRQ_PRE_BEACON_SD_HI 5 -+#define IRQ_PRE_BEACON_SD_SZ 1 -+#define IRQ_EDCA0_TX_DONE_SD_MSK 0x00000040 -+#define IRQ_EDCA0_TX_DONE_SD_I_MSK 0xffffffbf -+#define IRQ_EDCA0_TX_DONE_SD_SFT 6 -+#define IRQ_EDCA0_TX_DONE_SD_HI 6 -+#define IRQ_EDCA0_TX_DONE_SD_SZ 1 -+#define IRQ_EDCA1_TX_DONE_SD_MSK 0x00000080 -+#define IRQ_EDCA1_TX_DONE_SD_I_MSK 0xffffff7f -+#define IRQ_EDCA1_TX_DONE_SD_SFT 7 -+#define IRQ_EDCA1_TX_DONE_SD_HI 7 -+#define IRQ_EDCA1_TX_DONE_SD_SZ 1 -+#define IRQ_EDCA2_TX_DONE_SD_MSK 0x00000100 -+#define IRQ_EDCA2_TX_DONE_SD_I_MSK 0xfffffeff -+#define IRQ_EDCA2_TX_DONE_SD_SFT 8 -+#define IRQ_EDCA2_TX_DONE_SD_HI 8 -+#define IRQ_EDCA2_TX_DONE_SD_SZ 1 -+#define IRQ_EDCA3_TX_DONE_SD_MSK 0x00000200 -+#define IRQ_EDCA3_TX_DONE_SD_I_MSK 0xfffffdff -+#define IRQ_EDCA3_TX_DONE_SD_SFT 9 -+#define IRQ_EDCA3_TX_DONE_SD_HI 9 -+#define IRQ_EDCA3_TX_DONE_SD_SZ 1 -+#define IRQ_EDCA4_TX_DONE_SD_MSK 0x00000400 -+#define IRQ_EDCA4_TX_DONE_SD_I_MSK 0xfffffbff -+#define IRQ_EDCA4_TX_DONE_SD_SFT 10 -+#define IRQ_EDCA4_TX_DONE_SD_HI 10 -+#define IRQ_EDCA4_TX_DONE_SD_SZ 1 -+#define IRQ_BEACON_DTIM_SD_MSK 0x00001000 -+#define IRQ_BEACON_DTIM_SD_I_MSK 0xffffefff -+#define IRQ_BEACON_DTIM_SD_SFT 12 -+#define IRQ_BEACON_DTIM_SD_HI 12 -+#define IRQ_BEACON_DTIM_SD_SZ 1 -+#define IRQ_EDCA0_LOWTHOLD_INT_SD_MSK 0x00002000 -+#define IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK 0xffffdfff -+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SFT 13 -+#define IRQ_EDCA0_LOWTHOLD_INT_SD_HI 13 -+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SZ 1 -+#define IRQ_EDCA1_LOWTHOLD_INT_SD_MSK 0x00004000 -+#define IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK 0xffffbfff -+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SFT 14 -+#define IRQ_EDCA1_LOWTHOLD_INT_SD_HI 14 -+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SZ 1 -+#define IRQ_EDCA2_LOWTHOLD_INT_SD_MSK 0x00008000 -+#define IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK 0xffff7fff -+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SFT 15 -+#define IRQ_EDCA2_LOWTHOLD_INT_SD_HI 15 -+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SZ 1 -+#define IRQ_EDCA3_LOWTHOLD_INT_SD_MSK 0x00010000 -+#define IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK 0xfffeffff -+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SFT 16 -+#define IRQ_EDCA3_LOWTHOLD_INT_SD_HI 16 -+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SZ 1 -+#define IRQ_FENCE_HIT_INT_SD_MSK 0x00020000 -+#define IRQ_FENCE_HIT_INT_SD_I_MSK 0xfffdffff -+#define IRQ_FENCE_HIT_INT_SD_SFT 17 -+#define IRQ_FENCE_HIT_INT_SD_HI 17 -+#define IRQ_FENCE_HIT_INT_SD_SZ 1 -+#define IRQ_ILL_ADDR_INT_SD_MSK 0x00040000 -+#define IRQ_ILL_ADDR_INT_SD_I_MSK 0xfffbffff -+#define IRQ_ILL_ADDR_INT_SD_SFT 18 -+#define IRQ_ILL_ADDR_INT_SD_HI 18 -+#define IRQ_ILL_ADDR_INT_SD_SZ 1 -+#define IRQ_MBOX_SD_MSK 0x00080000 -+#define IRQ_MBOX_SD_I_MSK 0xfff7ffff -+#define IRQ_MBOX_SD_SFT 19 -+#define IRQ_MBOX_SD_HI 19 -+#define IRQ_MBOX_SD_SZ 1 -+#define IRQ_US_TIMER0_SD_MSK 0x00100000 -+#define IRQ_US_TIMER0_SD_I_MSK 0xffefffff -+#define IRQ_US_TIMER0_SD_SFT 20 -+#define IRQ_US_TIMER0_SD_HI 20 -+#define IRQ_US_TIMER0_SD_SZ 1 -+#define IRQ_US_TIMER1_SD_MSK 0x00200000 -+#define IRQ_US_TIMER1_SD_I_MSK 0xffdfffff -+#define IRQ_US_TIMER1_SD_SFT 21 -+#define IRQ_US_TIMER1_SD_HI 21 -+#define IRQ_US_TIMER1_SD_SZ 1 -+#define IRQ_US_TIMER2_SD_MSK 0x00400000 -+#define IRQ_US_TIMER2_SD_I_MSK 0xffbfffff -+#define IRQ_US_TIMER2_SD_SFT 22 -+#define IRQ_US_TIMER2_SD_HI 22 -+#define IRQ_US_TIMER2_SD_SZ 1 -+#define IRQ_US_TIMER3_SD_MSK 0x00800000 -+#define IRQ_US_TIMER3_SD_I_MSK 0xff7fffff -+#define IRQ_US_TIMER3_SD_SFT 23 -+#define IRQ_US_TIMER3_SD_HI 23 -+#define IRQ_US_TIMER3_SD_SZ 1 -+#define IRQ_MS_TIMER0_SD_MSK 0x01000000 -+#define IRQ_MS_TIMER0_SD_I_MSK 0xfeffffff -+#define IRQ_MS_TIMER0_SD_SFT 24 -+#define IRQ_MS_TIMER0_SD_HI 24 -+#define IRQ_MS_TIMER0_SD_SZ 1 -+#define IRQ_MS_TIMER1_SD_MSK 0x02000000 -+#define IRQ_MS_TIMER1_SD_I_MSK 0xfdffffff -+#define IRQ_MS_TIMER1_SD_SFT 25 -+#define IRQ_MS_TIMER1_SD_HI 25 -+#define IRQ_MS_TIMER1_SD_SZ 1 -+#define IRQ_MS_TIMER2_SD_MSK 0x04000000 -+#define IRQ_MS_TIMER2_SD_I_MSK 0xfbffffff -+#define IRQ_MS_TIMER2_SD_SFT 26 -+#define IRQ_MS_TIMER2_SD_HI 26 -+#define IRQ_MS_TIMER2_SD_SZ 1 -+#define IRQ_MS_TIMER3_SD_MSK 0x08000000 -+#define IRQ_MS_TIMER3_SD_I_MSK 0xf7ffffff -+#define IRQ_MS_TIMER3_SD_SFT 27 -+#define IRQ_MS_TIMER3_SD_HI 27 -+#define IRQ_MS_TIMER3_SD_SZ 1 -+#define IRQ_TX_LIMIT_INT_SD_MSK 0x10000000 -+#define IRQ_TX_LIMIT_INT_SD_I_MSK 0xefffffff -+#define IRQ_TX_LIMIT_INT_SD_SFT 28 -+#define IRQ_TX_LIMIT_INT_SD_HI 28 -+#define IRQ_TX_LIMIT_INT_SD_SZ 1 -+#define IRQ_DMA0_SD_MSK 0x20000000 -+#define IRQ_DMA0_SD_I_MSK 0xdfffffff -+#define IRQ_DMA0_SD_SFT 29 -+#define IRQ_DMA0_SD_HI 29 -+#define IRQ_DMA0_SD_SZ 1 -+#define IRQ_CO_DMA_SD_MSK 0x40000000 -+#define IRQ_CO_DMA_SD_I_MSK 0xbfffffff -+#define IRQ_CO_DMA_SD_SFT 30 -+#define IRQ_CO_DMA_SD_HI 30 -+#define IRQ_CO_DMA_SD_SZ 1 -+#define IRQ_PERI_GROUP_SD_MSK 0x80000000 -+#define IRQ_PERI_GROUP_SD_I_MSK 0x7fffffff -+#define IRQ_PERI_GROUP_SD_SFT 31 -+#define IRQ_PERI_GROUP_SD_HI 31 -+#define IRQ_PERI_GROUP_SD_SZ 1 -+#define INT_PERI_MASK_SD_MSK 0xffffffff -+#define INT_PERI_MASK_SD_I_MSK 0x00000000 -+#define INT_PERI_MASK_SD_SFT 0 -+#define INT_PERI_MASK_SD_HI 31 -+#define INT_PERI_MASK_SD_SZ 32 -+#define PERI_RTC_SD_MSK 0x00000001 -+#define PERI_RTC_SD_I_MSK 0xfffffffe -+#define PERI_RTC_SD_SFT 0 -+#define PERI_RTC_SD_HI 0 -+#define PERI_RTC_SD_SZ 1 -+#define IRQ_UART0_TX_SD_MSK 0x00000002 -+#define IRQ_UART0_TX_SD_I_MSK 0xfffffffd -+#define IRQ_UART0_TX_SD_SFT 1 -+#define IRQ_UART0_TX_SD_HI 1 -+#define IRQ_UART0_TX_SD_SZ 1 -+#define IRQ_UART0_RX_SD_MSK 0x00000004 -+#define IRQ_UART0_RX_SD_I_MSK 0xfffffffb -+#define IRQ_UART0_RX_SD_SFT 2 -+#define IRQ_UART0_RX_SD_HI 2 -+#define IRQ_UART0_RX_SD_SZ 1 -+#define PERI_GPI_SD_2_MSK 0x00000008 -+#define PERI_GPI_SD_2_I_MSK 0xfffffff7 -+#define PERI_GPI_SD_2_SFT 3 -+#define PERI_GPI_SD_2_HI 3 -+#define PERI_GPI_SD_2_SZ 1 -+#define IRQ_SPI_IPC_SD_MSK 0x00000010 -+#define IRQ_SPI_IPC_SD_I_MSK 0xffffffef -+#define IRQ_SPI_IPC_SD_SFT 4 -+#define IRQ_SPI_IPC_SD_HI 4 -+#define IRQ_SPI_IPC_SD_SZ 1 -+#define PERI_GPI_SD_1_0_MSK 0x00000060 -+#define PERI_GPI_SD_1_0_I_MSK 0xffffff9f -+#define PERI_GPI_SD_1_0_SFT 5 -+#define PERI_GPI_SD_1_0_HI 6 -+#define PERI_GPI_SD_1_0_SZ 2 -+#define SCRT_INT_1_SD_MSK 0x00000080 -+#define SCRT_INT_1_SD_I_MSK 0xffffff7f -+#define SCRT_INT_1_SD_SFT 7 -+#define SCRT_INT_1_SD_HI 7 -+#define SCRT_INT_1_SD_SZ 1 -+#define MMU_ALC_ERR_SD_MSK 0x00000100 -+#define MMU_ALC_ERR_SD_I_MSK 0xfffffeff -+#define MMU_ALC_ERR_SD_SFT 8 -+#define MMU_ALC_ERR_SD_HI 8 -+#define MMU_ALC_ERR_SD_SZ 1 -+#define MMU_RLS_ERR_SD_MSK 0x00000200 -+#define MMU_RLS_ERR_SD_I_MSK 0xfffffdff -+#define MMU_RLS_ERR_SD_SFT 9 -+#define MMU_RLS_ERR_SD_HI 9 -+#define MMU_RLS_ERR_SD_SZ 1 -+#define ID_MNG_INT_1_SD_MSK 0x00000400 -+#define ID_MNG_INT_1_SD_I_MSK 0xfffffbff -+#define ID_MNG_INT_1_SD_SFT 10 -+#define ID_MNG_INT_1_SD_HI 10 -+#define ID_MNG_INT_1_SD_SZ 1 -+#define MBOX_INT_1_SD_MSK 0x00000800 -+#define MBOX_INT_1_SD_I_MSK 0xfffff7ff -+#define MBOX_INT_1_SD_SFT 11 -+#define MBOX_INT_1_SD_HI 11 -+#define MBOX_INT_1_SD_SZ 1 -+#define MBOX_INT_2_SD_MSK 0x00001000 -+#define MBOX_INT_2_SD_I_MSK 0xffffefff -+#define MBOX_INT_2_SD_SFT 12 -+#define MBOX_INT_2_SD_HI 12 -+#define MBOX_INT_2_SD_SZ 1 -+#define MBOX_INT_3_SD_MSK 0x00002000 -+#define MBOX_INT_3_SD_I_MSK 0xffffdfff -+#define MBOX_INT_3_SD_SFT 13 -+#define MBOX_INT_3_SD_HI 13 -+#define MBOX_INT_3_SD_SZ 1 -+#define HCI_INT_1_SD_MSK 0x00004000 -+#define HCI_INT_1_SD_I_MSK 0xffffbfff -+#define HCI_INT_1_SD_SFT 14 -+#define HCI_INT_1_SD_HI 14 -+#define HCI_INT_1_SD_SZ 1 -+#define UART_RX_TIMEOUT_SD_MSK 0x00008000 -+#define UART_RX_TIMEOUT_SD_I_MSK 0xffff7fff -+#define UART_RX_TIMEOUT_SD_SFT 15 -+#define UART_RX_TIMEOUT_SD_HI 15 -+#define UART_RX_TIMEOUT_SD_SZ 1 -+#define UART_MULTI_IRQ_SD_MSK 0x00010000 -+#define UART_MULTI_IRQ_SD_I_MSK 0xfffeffff -+#define UART_MULTI_IRQ_SD_SFT 16 -+#define UART_MULTI_IRQ_SD_HI 16 -+#define UART_MULTI_IRQ_SD_SZ 1 -+#define ID_MNG_INT_2_SD_MSK 0x00020000 -+#define ID_MNG_INT_2_SD_I_MSK 0xfffdffff -+#define ID_MNG_INT_2_SD_SFT 17 -+#define ID_MNG_INT_2_SD_HI 17 -+#define ID_MNG_INT_2_SD_SZ 1 -+#define DMN_NOHIT_INT_SD_MSK 0x00040000 -+#define DMN_NOHIT_INT_SD_I_MSK 0xfffbffff -+#define DMN_NOHIT_INT_SD_SFT 18 -+#define DMN_NOHIT_INT_SD_HI 18 -+#define DMN_NOHIT_INT_SD_SZ 1 -+#define ID_THOLD_RX_SD_MSK 0x00080000 -+#define ID_THOLD_RX_SD_I_MSK 0xfff7ffff -+#define ID_THOLD_RX_SD_SFT 19 -+#define ID_THOLD_RX_SD_HI 19 -+#define ID_THOLD_RX_SD_SZ 1 -+#define ID_THOLD_TX_SD_MSK 0x00100000 -+#define ID_THOLD_TX_SD_I_MSK 0xffefffff -+#define ID_THOLD_TX_SD_SFT 20 -+#define ID_THOLD_TX_SD_HI 20 -+#define ID_THOLD_TX_SD_SZ 1 -+#define ID_DOUBLE_RLS_SD_MSK 0x00200000 -+#define ID_DOUBLE_RLS_SD_I_MSK 0xffdfffff -+#define ID_DOUBLE_RLS_SD_SFT 21 -+#define ID_DOUBLE_RLS_SD_HI 21 -+#define ID_DOUBLE_RLS_SD_SZ 1 -+#define RX_ID_LEN_THOLD_SD_MSK 0x00400000 -+#define RX_ID_LEN_THOLD_SD_I_MSK 0xffbfffff -+#define RX_ID_LEN_THOLD_SD_SFT 22 -+#define RX_ID_LEN_THOLD_SD_HI 22 -+#define RX_ID_LEN_THOLD_SD_SZ 1 -+#define TX_ID_LEN_THOLD_SD_MSK 0x00800000 -+#define TX_ID_LEN_THOLD_SD_I_MSK 0xff7fffff -+#define TX_ID_LEN_THOLD_SD_SFT 23 -+#define TX_ID_LEN_THOLD_SD_HI 23 -+#define TX_ID_LEN_THOLD_SD_SZ 1 -+#define ALL_ID_LEN_THOLD_SD_MSK 0x01000000 -+#define ALL_ID_LEN_THOLD_SD_I_MSK 0xfeffffff -+#define ALL_ID_LEN_THOLD_SD_SFT 24 -+#define ALL_ID_LEN_THOLD_SD_HI 24 -+#define ALL_ID_LEN_THOLD_SD_SZ 1 -+#define DMN_MCU_INT_SD_MSK 0x02000000 -+#define DMN_MCU_INT_SD_I_MSK 0xfdffffff -+#define DMN_MCU_INT_SD_SFT 25 -+#define DMN_MCU_INT_SD_HI 25 -+#define DMN_MCU_INT_SD_SZ 1 -+#define IRQ_DAT_UART_TX_SD_MSK 0x04000000 -+#define IRQ_DAT_UART_TX_SD_I_MSK 0xfbffffff -+#define IRQ_DAT_UART_TX_SD_SFT 26 -+#define IRQ_DAT_UART_TX_SD_HI 26 -+#define IRQ_DAT_UART_TX_SD_SZ 1 -+#define IRQ_DAT_UART_RX_SD_MSK 0x08000000 -+#define IRQ_DAT_UART_RX_SD_I_MSK 0xf7ffffff -+#define IRQ_DAT_UART_RX_SD_SFT 27 -+#define IRQ_DAT_UART_RX_SD_HI 27 -+#define IRQ_DAT_UART_RX_SD_SZ 1 -+#define DAT_UART_RX_TIMEOUT_SD_MSK 0x10000000 -+#define DAT_UART_RX_TIMEOUT_SD_I_MSK 0xefffffff -+#define DAT_UART_RX_TIMEOUT_SD_SFT 28 -+#define DAT_UART_RX_TIMEOUT_SD_HI 28 -+#define DAT_UART_RX_TIMEOUT_SD_SZ 1 -+#define DAT_UART_MULTI_IRQ_SD_MSK 0x20000000 -+#define DAT_UART_MULTI_IRQ_SD_I_MSK 0xdfffffff -+#define DAT_UART_MULTI_IRQ_SD_SFT 29 -+#define DAT_UART_MULTI_IRQ_SD_HI 29 -+#define DAT_UART_MULTI_IRQ_SD_SZ 1 -+#define ALR_ABT_NOCHG_INT_IRQ_SD_MSK 0x40000000 -+#define ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK 0xbfffffff -+#define ALR_ABT_NOCHG_INT_IRQ_SD_SFT 30 -+#define ALR_ABT_NOCHG_INT_IRQ_SD_HI 30 -+#define ALR_ABT_NOCHG_INT_IRQ_SD_SZ 1 -+#define TBLNEQ_MNGPKT_INT_IRQ_SD_MSK 0x80000000 -+#define TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK 0x7fffffff -+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SFT 31 -+#define TBLNEQ_MNGPKT_INT_IRQ_SD_HI 31 -+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SZ 1 -+#define DBG_SPI_MODE_MSK 0xffffffff -+#define DBG_SPI_MODE_I_MSK 0x00000000 -+#define DBG_SPI_MODE_SFT 0 -+#define DBG_SPI_MODE_HI 31 -+#define DBG_SPI_MODE_SZ 32 -+#define DBG_RX_QUOTA_MSK 0x0000ffff -+#define DBG_RX_QUOTA_I_MSK 0xffff0000 -+#define DBG_RX_QUOTA_SFT 0 -+#define DBG_RX_QUOTA_HI 15 -+#define DBG_RX_QUOTA_SZ 16 -+#define DBG_CONDI_NUM_MSK 0x000000ff -+#define DBG_CONDI_NUM_I_MSK 0xffffff00 -+#define DBG_CONDI_NUM_SFT 0 -+#define DBG_CONDI_NUM_HI 7 -+#define DBG_CONDI_NUM_SZ 8 -+#define DBG_HOST_PATH_MSK 0x00000001 -+#define DBG_HOST_PATH_I_MSK 0xfffffffe -+#define DBG_HOST_PATH_SFT 0 -+#define DBG_HOST_PATH_HI 0 -+#define DBG_HOST_PATH_SZ 1 -+#define DBG_TX_SEG_MSK 0xffffffff -+#define DBG_TX_SEG_I_MSK 0x00000000 -+#define DBG_TX_SEG_SFT 0 -+#define DBG_TX_SEG_HI 31 -+#define DBG_TX_SEG_SZ 32 -+#define DBG_BRST_MODE_MSK 0x00000001 -+#define DBG_BRST_MODE_I_MSK 0xfffffffe -+#define DBG_BRST_MODE_SFT 0 -+#define DBG_BRST_MODE_HI 0 -+#define DBG_BRST_MODE_SZ 1 -+#define DBG_CLK_WIDTH_MSK 0x0000ffff -+#define DBG_CLK_WIDTH_I_MSK 0xffff0000 -+#define DBG_CLK_WIDTH_SFT 0 -+#define DBG_CLK_WIDTH_HI 15 -+#define DBG_CLK_WIDTH_SZ 16 -+#define DBG_CSN_INTER_MSK 0xffff0000 -+#define DBG_CSN_INTER_I_MSK 0x0000ffff -+#define DBG_CSN_INTER_SFT 16 -+#define DBG_CSN_INTER_HI 31 -+#define DBG_CSN_INTER_SZ 16 -+#define DBG_BACK_DLY_MSK 0x0000ffff -+#define DBG_BACK_DLY_I_MSK 0xffff0000 -+#define DBG_BACK_DLY_SFT 0 -+#define DBG_BACK_DLY_HI 15 -+#define DBG_BACK_DLY_SZ 16 -+#define DBG_FRONT_DLY_MSK 0xffff0000 -+#define DBG_FRONT_DLY_I_MSK 0x0000ffff -+#define DBG_FRONT_DLY_SFT 16 -+#define DBG_FRONT_DLY_HI 31 -+#define DBG_FRONT_DLY_SZ 16 -+#define DBG_RX_FIFO_FAIL_MSK 0x00000002 -+#define DBG_RX_FIFO_FAIL_I_MSK 0xfffffffd -+#define DBG_RX_FIFO_FAIL_SFT 1 -+#define DBG_RX_FIFO_FAIL_HI 1 -+#define DBG_RX_FIFO_FAIL_SZ 1 -+#define DBG_RX_HOST_FAIL_MSK 0x00000004 -+#define DBG_RX_HOST_FAIL_I_MSK 0xfffffffb -+#define DBG_RX_HOST_FAIL_SFT 2 -+#define DBG_RX_HOST_FAIL_HI 2 -+#define DBG_RX_HOST_FAIL_SZ 1 -+#define DBG_TX_FIFO_FAIL_MSK 0x00000008 -+#define DBG_TX_FIFO_FAIL_I_MSK 0xfffffff7 -+#define DBG_TX_FIFO_FAIL_SFT 3 -+#define DBG_TX_FIFO_FAIL_HI 3 -+#define DBG_TX_FIFO_FAIL_SZ 1 -+#define DBG_TX_HOST_FAIL_MSK 0x00000010 -+#define DBG_TX_HOST_FAIL_I_MSK 0xffffffef -+#define DBG_TX_HOST_FAIL_SFT 4 -+#define DBG_TX_HOST_FAIL_HI 4 -+#define DBG_TX_HOST_FAIL_SZ 1 -+#define DBG_SPI_DOUBLE_ALLOC_MSK 0x00000020 -+#define DBG_SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf -+#define DBG_SPI_DOUBLE_ALLOC_SFT 5 -+#define DBG_SPI_DOUBLE_ALLOC_HI 5 -+#define DBG_SPI_DOUBLE_ALLOC_SZ 1 -+#define DBG_SPI_TX_NO_ALLOC_MSK 0x00000040 -+#define DBG_SPI_TX_NO_ALLOC_I_MSK 0xffffffbf -+#define DBG_SPI_TX_NO_ALLOC_SFT 6 -+#define DBG_SPI_TX_NO_ALLOC_HI 6 -+#define DBG_SPI_TX_NO_ALLOC_SZ 1 -+#define DBG_RDATA_RDY_MSK 0x00000080 -+#define DBG_RDATA_RDY_I_MSK 0xffffff7f -+#define DBG_RDATA_RDY_SFT 7 -+#define DBG_RDATA_RDY_HI 7 -+#define DBG_RDATA_RDY_SZ 1 -+#define DBG_SPI_ALLOC_STATUS_MSK 0x00000100 -+#define DBG_SPI_ALLOC_STATUS_I_MSK 0xfffffeff -+#define DBG_SPI_ALLOC_STATUS_SFT 8 -+#define DBG_SPI_ALLOC_STATUS_HI 8 -+#define DBG_SPI_ALLOC_STATUS_SZ 1 -+#define DBG_SPI_DBG_WR_FIFO_FULL_MSK 0x00000200 -+#define DBG_SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff -+#define DBG_SPI_DBG_WR_FIFO_FULL_SFT 9 -+#define DBG_SPI_DBG_WR_FIFO_FULL_HI 9 -+#define DBG_SPI_DBG_WR_FIFO_FULL_SZ 1 -+#define DBG_RX_LEN_MSK 0xffff0000 -+#define DBG_RX_LEN_I_MSK 0x0000ffff -+#define DBG_RX_LEN_SFT 16 -+#define DBG_RX_LEN_HI 31 -+#define DBG_RX_LEN_SZ 16 -+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007 -+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8 -+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0 -+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2 -+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3 -+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100 -+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff -+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT 8 -+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_HI 8 -+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ 1 -+#define DBG_SPI_TX_ALLOC_SIZE_MSK 0x000000ff -+#define DBG_SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00 -+#define DBG_SPI_TX_ALLOC_SIZE_SFT 0 -+#define DBG_SPI_TX_ALLOC_SIZE_HI 7 -+#define DBG_SPI_TX_ALLOC_SIZE_SZ 8 -+#define DBG_RD_DAT_CNT_MSK 0x0000ffff -+#define DBG_RD_DAT_CNT_I_MSK 0xffff0000 -+#define DBG_RD_DAT_CNT_SFT 0 -+#define DBG_RD_DAT_CNT_HI 15 -+#define DBG_RD_DAT_CNT_SZ 16 -+#define DBG_RD_STS_CNT_MSK 0xffff0000 -+#define DBG_RD_STS_CNT_I_MSK 0x0000ffff -+#define DBG_RD_STS_CNT_SFT 16 -+#define DBG_RD_STS_CNT_HI 31 -+#define DBG_RD_STS_CNT_SZ 16 -+#define DBG_JUDGE_CNT_MSK 0x0000ffff -+#define DBG_JUDGE_CNT_I_MSK 0xffff0000 -+#define DBG_JUDGE_CNT_SFT 0 -+#define DBG_JUDGE_CNT_HI 15 -+#define DBG_JUDGE_CNT_SZ 16 -+#define DBG_RD_STS_CNT_CLR_MSK 0x00010000 -+#define DBG_RD_STS_CNT_CLR_I_MSK 0xfffeffff -+#define DBG_RD_STS_CNT_CLR_SFT 16 -+#define DBG_RD_STS_CNT_CLR_HI 16 -+#define DBG_RD_STS_CNT_CLR_SZ 1 -+#define DBG_RD_DAT_CNT_CLR_MSK 0x00020000 -+#define DBG_RD_DAT_CNT_CLR_I_MSK 0xfffdffff -+#define DBG_RD_DAT_CNT_CLR_SFT 17 -+#define DBG_RD_DAT_CNT_CLR_HI 17 -+#define DBG_RD_DAT_CNT_CLR_SZ 1 -+#define DBG_JUDGE_CNT_CLR_MSK 0x00040000 -+#define DBG_JUDGE_CNT_CLR_I_MSK 0xfffbffff -+#define DBG_JUDGE_CNT_CLR_SFT 18 -+#define DBG_JUDGE_CNT_CLR_HI 18 -+#define DBG_JUDGE_CNT_CLR_SZ 1 -+#define DBG_TX_DONE_CNT_MSK 0x0000ffff -+#define DBG_TX_DONE_CNT_I_MSK 0xffff0000 -+#define DBG_TX_DONE_CNT_SFT 0 -+#define DBG_TX_DONE_CNT_HI 15 -+#define DBG_TX_DONE_CNT_SZ 16 -+#define DBG_TX_DISCARD_CNT_MSK 0xffff0000 -+#define DBG_TX_DISCARD_CNT_I_MSK 0x0000ffff -+#define DBG_TX_DISCARD_CNT_SFT 16 -+#define DBG_TX_DISCARD_CNT_HI 31 -+#define DBG_TX_DISCARD_CNT_SZ 16 -+#define DBG_TX_SET_CNT_MSK 0x0000ffff -+#define DBG_TX_SET_CNT_I_MSK 0xffff0000 -+#define DBG_TX_SET_CNT_SFT 0 -+#define DBG_TX_SET_CNT_HI 15 -+#define DBG_TX_SET_CNT_SZ 16 -+#define DBG_TX_DISCARD_CNT_CLR_MSK 0x00010000 -+#define DBG_TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff -+#define DBG_TX_DISCARD_CNT_CLR_SFT 16 -+#define DBG_TX_DISCARD_CNT_CLR_HI 16 -+#define DBG_TX_DISCARD_CNT_CLR_SZ 1 -+#define DBG_TX_DONE_CNT_CLR_MSK 0x00020000 -+#define DBG_TX_DONE_CNT_CLR_I_MSK 0xfffdffff -+#define DBG_TX_DONE_CNT_CLR_SFT 17 -+#define DBG_TX_DONE_CNT_CLR_HI 17 -+#define DBG_TX_DONE_CNT_CLR_SZ 1 -+#define DBG_TX_SET_CNT_CLR_MSK 0x00040000 -+#define DBG_TX_SET_CNT_CLR_I_MSK 0xfffbffff -+#define DBG_TX_SET_CNT_CLR_SFT 18 -+#define DBG_TX_SET_CNT_CLR_HI 18 -+#define DBG_TX_SET_CNT_CLR_SZ 1 -+#define DBG_DAT_MODE_OFF_MSK 0x00080000 -+#define DBG_DAT_MODE_OFF_I_MSK 0xfff7ffff -+#define DBG_DAT_MODE_OFF_SFT 19 -+#define DBG_DAT_MODE_OFF_HI 19 -+#define DBG_DAT_MODE_OFF_SZ 1 -+#define DBG_TX_FIFO_RESIDUE_MSK 0x00700000 -+#define DBG_TX_FIFO_RESIDUE_I_MSK 0xff8fffff -+#define DBG_TX_FIFO_RESIDUE_SFT 20 -+#define DBG_TX_FIFO_RESIDUE_HI 22 -+#define DBG_TX_FIFO_RESIDUE_SZ 3 -+#define DBG_RX_FIFO_RESIDUE_MSK 0x07000000 -+#define DBG_RX_FIFO_RESIDUE_I_MSK 0xf8ffffff -+#define DBG_RX_FIFO_RESIDUE_SFT 24 -+#define DBG_RX_FIFO_RESIDUE_HI 26 -+#define DBG_RX_FIFO_RESIDUE_SZ 3 -+#define DBG_RX_RDY_MSK 0x00000001 -+#define DBG_RX_RDY_I_MSK 0xfffffffe -+#define DBG_RX_RDY_SFT 0 -+#define DBG_RX_RDY_HI 0 -+#define DBG_RX_RDY_SZ 1 -+#define DBG_SDIO_SYS_INT_MSK 0x00000004 -+#define DBG_SDIO_SYS_INT_I_MSK 0xfffffffb -+#define DBG_SDIO_SYS_INT_SFT 2 -+#define DBG_SDIO_SYS_INT_HI 2 -+#define DBG_SDIO_SYS_INT_SZ 1 -+#define DBG_EDCA0_LOWTHOLD_INT_MSK 0x00000008 -+#define DBG_EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7 -+#define DBG_EDCA0_LOWTHOLD_INT_SFT 3 -+#define DBG_EDCA0_LOWTHOLD_INT_HI 3 -+#define DBG_EDCA0_LOWTHOLD_INT_SZ 1 -+#define DBG_EDCA1_LOWTHOLD_INT_MSK 0x00000010 -+#define DBG_EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef -+#define DBG_EDCA1_LOWTHOLD_INT_SFT 4 -+#define DBG_EDCA1_LOWTHOLD_INT_HI 4 -+#define DBG_EDCA1_LOWTHOLD_INT_SZ 1 -+#define DBG_EDCA2_LOWTHOLD_INT_MSK 0x00000020 -+#define DBG_EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf -+#define DBG_EDCA2_LOWTHOLD_INT_SFT 5 -+#define DBG_EDCA2_LOWTHOLD_INT_HI 5 -+#define DBG_EDCA2_LOWTHOLD_INT_SZ 1 -+#define DBG_EDCA3_LOWTHOLD_INT_MSK 0x00000040 -+#define DBG_EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf -+#define DBG_EDCA3_LOWTHOLD_INT_SFT 6 -+#define DBG_EDCA3_LOWTHOLD_INT_HI 6 -+#define DBG_EDCA3_LOWTHOLD_INT_SZ 1 -+#define DBG_TX_LIMIT_INT_IN_MSK 0x00000080 -+#define DBG_TX_LIMIT_INT_IN_I_MSK 0xffffff7f -+#define DBG_TX_LIMIT_INT_IN_SFT 7 -+#define DBG_TX_LIMIT_INT_IN_HI 7 -+#define DBG_TX_LIMIT_INT_IN_SZ 1 -+#define DBG_SPI_FN1_MSK 0x00007f00 -+#define DBG_SPI_FN1_I_MSK 0xffff80ff -+#define DBG_SPI_FN1_SFT 8 -+#define DBG_SPI_FN1_HI 14 -+#define DBG_SPI_FN1_SZ 7 -+#define DBG_SPI_CLK_EN_INT_MSK 0x00008000 -+#define DBG_SPI_CLK_EN_INT_I_MSK 0xffff7fff -+#define DBG_SPI_CLK_EN_INT_SFT 15 -+#define DBG_SPI_CLK_EN_INT_HI 15 -+#define DBG_SPI_CLK_EN_INT_SZ 1 -+#define DBG_SPI_HOST_MASK_MSK 0x00ff0000 -+#define DBG_SPI_HOST_MASK_I_MSK 0xff00ffff -+#define DBG_SPI_HOST_MASK_SFT 16 -+#define DBG_SPI_HOST_MASK_HI 23 -+#define DBG_SPI_HOST_MASK_SZ 8 -+#define BOOT_ADDR_MSK 0x00ffffff -+#define BOOT_ADDR_I_MSK 0xff000000 -+#define BOOT_ADDR_SFT 0 -+#define BOOT_ADDR_HI 23 -+#define BOOT_ADDR_SZ 24 -+#define CHECK_SUM_FAIL_MSK 0x80000000 -+#define CHECK_SUM_FAIL_I_MSK 0x7fffffff -+#define CHECK_SUM_FAIL_SFT 31 -+#define CHECK_SUM_FAIL_HI 31 -+#define CHECK_SUM_FAIL_SZ 1 -+#define VERIFY_DATA_MSK 0xffffffff -+#define VERIFY_DATA_I_MSK 0x00000000 -+#define VERIFY_DATA_SFT 0 -+#define VERIFY_DATA_HI 31 -+#define VERIFY_DATA_SZ 32 -+#define FLASH_ADDR_MSK 0x00ffffff -+#define FLASH_ADDR_I_MSK 0xff000000 -+#define FLASH_ADDR_SFT 0 -+#define FLASH_ADDR_HI 23 -+#define FLASH_ADDR_SZ 24 -+#define FLASH_CMD_CLR_MSK 0x10000000 -+#define FLASH_CMD_CLR_I_MSK 0xefffffff -+#define FLASH_CMD_CLR_SFT 28 -+#define FLASH_CMD_CLR_HI 28 -+#define FLASH_CMD_CLR_SZ 1 -+#define FLASH_DMA_CLR_MSK 0x20000000 -+#define FLASH_DMA_CLR_I_MSK 0xdfffffff -+#define FLASH_DMA_CLR_SFT 29 -+#define FLASH_DMA_CLR_HI 29 -+#define FLASH_DMA_CLR_SZ 1 -+#define DMA_EN_MSK 0x40000000 -+#define DMA_EN_I_MSK 0xbfffffff -+#define DMA_EN_SFT 30 -+#define DMA_EN_HI 30 -+#define DMA_EN_SZ 1 -+#define DMA_BUSY_MSK 0x80000000 -+#define DMA_BUSY_I_MSK 0x7fffffff -+#define DMA_BUSY_SFT 31 -+#define DMA_BUSY_HI 31 -+#define DMA_BUSY_SZ 1 -+#define SRAM_ADDR_MSK 0xffffffff -+#define SRAM_ADDR_I_MSK 0x00000000 -+#define SRAM_ADDR_SFT 0 -+#define SRAM_ADDR_HI 31 -+#define SRAM_ADDR_SZ 32 -+#define FLASH_DMA_LEN_MSK 0xffffffff -+#define FLASH_DMA_LEN_I_MSK 0x00000000 -+#define FLASH_DMA_LEN_SFT 0 -+#define FLASH_DMA_LEN_HI 31 -+#define FLASH_DMA_LEN_SZ 32 -+#define FLASH_FRONT_DLY_MSK 0x0000ffff -+#define FLASH_FRONT_DLY_I_MSK 0xffff0000 -+#define FLASH_FRONT_DLY_SFT 0 -+#define FLASH_FRONT_DLY_HI 15 -+#define FLASH_FRONT_DLY_SZ 16 -+#define FLASH_BACK_DLY_MSK 0xffff0000 -+#define FLASH_BACK_DLY_I_MSK 0x0000ffff -+#define FLASH_BACK_DLY_SFT 16 -+#define FLASH_BACK_DLY_HI 31 -+#define FLASH_BACK_DLY_SZ 16 -+#define FLASH_CLK_WIDTH_MSK 0x0000ffff -+#define FLASH_CLK_WIDTH_I_MSK 0xffff0000 -+#define FLASH_CLK_WIDTH_SFT 0 -+#define FLASH_CLK_WIDTH_HI 15 -+#define FLASH_CLK_WIDTH_SZ 16 -+#define SPI_BUSY_MSK 0x00010000 -+#define SPI_BUSY_I_MSK 0xfffeffff -+#define SPI_BUSY_SFT 16 -+#define SPI_BUSY_HI 16 -+#define SPI_BUSY_SZ 1 -+#define FLS_REMAP_MSK 0x00020000 -+#define FLS_REMAP_I_MSK 0xfffdffff -+#define FLS_REMAP_SFT 17 -+#define FLS_REMAP_HI 17 -+#define FLS_REMAP_SZ 1 -+#define PBUS_SWP_MSK 0x00040000 -+#define PBUS_SWP_I_MSK 0xfffbffff -+#define PBUS_SWP_SFT 18 -+#define PBUS_SWP_HI 18 -+#define PBUS_SWP_SZ 1 -+#define BIT_MODE1_MSK 0x00080000 -+#define BIT_MODE1_I_MSK 0xfff7ffff -+#define BIT_MODE1_SFT 19 -+#define BIT_MODE1_HI 19 -+#define BIT_MODE1_SZ 1 -+#define BIT_MODE2_MSK 0x00100000 -+#define BIT_MODE2_I_MSK 0xffefffff -+#define BIT_MODE2_SFT 20 -+#define BIT_MODE2_HI 20 -+#define BIT_MODE2_SZ 1 -+#define BIT_MODE4_MSK 0x00200000 -+#define BIT_MODE4_I_MSK 0xffdfffff -+#define BIT_MODE4_SFT 21 -+#define BIT_MODE4_HI 21 -+#define BIT_MODE4_SZ 1 -+#define BOOT_CHECK_SUM_MSK 0xffffffff -+#define BOOT_CHECK_SUM_I_MSK 0x00000000 -+#define BOOT_CHECK_SUM_SFT 0 -+#define BOOT_CHECK_SUM_HI 31 -+#define BOOT_CHECK_SUM_SZ 32 -+#define CHECK_SUM_TAG_MSK 0xffffffff -+#define CHECK_SUM_TAG_I_MSK 0x00000000 -+#define CHECK_SUM_TAG_SFT 0 -+#define CHECK_SUM_TAG_HI 31 -+#define CHECK_SUM_TAG_SZ 32 -+#define CMD_LEN_MSK 0x0000ffff -+#define CMD_LEN_I_MSK 0xffff0000 -+#define CMD_LEN_SFT 0 -+#define CMD_LEN_HI 15 -+#define CMD_LEN_SZ 16 -+#define CMD_ADDR_MSK 0xffffffff -+#define CMD_ADDR_I_MSK 0x00000000 -+#define CMD_ADDR_SFT 0 -+#define CMD_ADDR_HI 31 -+#define CMD_ADDR_SZ 32 -+#define DMA_ADR_SRC_MSK 0xffffffff -+#define DMA_ADR_SRC_I_MSK 0x00000000 -+#define DMA_ADR_SRC_SFT 0 -+#define DMA_ADR_SRC_HI 31 -+#define DMA_ADR_SRC_SZ 32 -+#define DMA_ADR_DST_MSK 0xffffffff -+#define DMA_ADR_DST_I_MSK 0x00000000 -+#define DMA_ADR_DST_SFT 0 -+#define DMA_ADR_DST_HI 31 -+#define DMA_ADR_DST_SZ 32 -+#define DMA_SRC_SIZE_MSK 0x00000007 -+#define DMA_SRC_SIZE_I_MSK 0xfffffff8 -+#define DMA_SRC_SIZE_SFT 0 -+#define DMA_SRC_SIZE_HI 2 -+#define DMA_SRC_SIZE_SZ 3 -+#define DMA_SRC_INC_MSK 0x00000008 -+#define DMA_SRC_INC_I_MSK 0xfffffff7 -+#define DMA_SRC_INC_SFT 3 -+#define DMA_SRC_INC_HI 3 -+#define DMA_SRC_INC_SZ 1 -+#define DMA_DST_SIZE_MSK 0x00000070 -+#define DMA_DST_SIZE_I_MSK 0xffffff8f -+#define DMA_DST_SIZE_SFT 4 -+#define DMA_DST_SIZE_HI 6 -+#define DMA_DST_SIZE_SZ 3 -+#define DMA_DST_INC_MSK 0x00000080 -+#define DMA_DST_INC_I_MSK 0xffffff7f -+#define DMA_DST_INC_SFT 7 -+#define DMA_DST_INC_HI 7 -+#define DMA_DST_INC_SZ 1 -+#define DMA_FAST_FILL_MSK 0x00000100 -+#define DMA_FAST_FILL_I_MSK 0xfffffeff -+#define DMA_FAST_FILL_SFT 8 -+#define DMA_FAST_FILL_HI 8 -+#define DMA_FAST_FILL_SZ 1 -+#define DMA_SDIO_KICK_MSK 0x00001000 -+#define DMA_SDIO_KICK_I_MSK 0xffffefff -+#define DMA_SDIO_KICK_SFT 12 -+#define DMA_SDIO_KICK_HI 12 -+#define DMA_SDIO_KICK_SZ 1 -+#define DMA_BADR_EN_MSK 0x00002000 -+#define DMA_BADR_EN_I_MSK 0xffffdfff -+#define DMA_BADR_EN_SFT 13 -+#define DMA_BADR_EN_HI 13 -+#define DMA_BADR_EN_SZ 1 -+#define DMA_LEN_MSK 0xffff0000 -+#define DMA_LEN_I_MSK 0x0000ffff -+#define DMA_LEN_SFT 16 -+#define DMA_LEN_HI 31 -+#define DMA_LEN_SZ 16 -+#define DMA_INT_MASK_MSK 0x00000001 -+#define DMA_INT_MASK_I_MSK 0xfffffffe -+#define DMA_INT_MASK_SFT 0 -+#define DMA_INT_MASK_HI 0 -+#define DMA_INT_MASK_SZ 1 -+#define DMA_STS_MSK 0x00000100 -+#define DMA_STS_I_MSK 0xfffffeff -+#define DMA_STS_SFT 8 -+#define DMA_STS_HI 8 -+#define DMA_STS_SZ 1 -+#define DMA_FINISH_MSK 0x80000000 -+#define DMA_FINISH_I_MSK 0x7fffffff -+#define DMA_FINISH_SFT 31 -+#define DMA_FINISH_HI 31 -+#define DMA_FINISH_SZ 1 -+#define DMA_CONST_MSK 0xffffffff -+#define DMA_CONST_I_MSK 0x00000000 -+#define DMA_CONST_SFT 0 -+#define DMA_CONST_HI 31 -+#define DMA_CONST_SZ 32 -+#define SLEEP_WAKE_CNT_MSK 0x00ffffff -+#define SLEEP_WAKE_CNT_I_MSK 0xff000000 -+#define SLEEP_WAKE_CNT_SFT 0 -+#define SLEEP_WAKE_CNT_HI 23 -+#define SLEEP_WAKE_CNT_SZ 24 -+#define RG_DLDO_LEVEL_MSK 0x07000000 -+#define RG_DLDO_LEVEL_I_MSK 0xf8ffffff -+#define RG_DLDO_LEVEL_SFT 24 -+#define RG_DLDO_LEVEL_HI 26 -+#define RG_DLDO_LEVEL_SZ 3 -+#define RG_DLDO_BOOST_IQ_MSK 0x08000000 -+#define RG_DLDO_BOOST_IQ_I_MSK 0xf7ffffff -+#define RG_DLDO_BOOST_IQ_SFT 27 -+#define RG_DLDO_BOOST_IQ_HI 27 -+#define RG_DLDO_BOOST_IQ_SZ 1 -+#define RG_BUCK_LEVEL_MSK 0x70000000 -+#define RG_BUCK_LEVEL_I_MSK 0x8fffffff -+#define RG_BUCK_LEVEL_SFT 28 -+#define RG_BUCK_LEVEL_HI 30 -+#define RG_BUCK_LEVEL_SZ 3 -+#define RG_BUCK_VREF_SEL_MSK 0x80000000 -+#define RG_BUCK_VREF_SEL_I_MSK 0x7fffffff -+#define RG_BUCK_VREF_SEL_SFT 31 -+#define RG_BUCK_VREF_SEL_HI 31 -+#define RG_BUCK_VREF_SEL_SZ 1 -+#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x000003ff -+#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xfffffc00 -+#define RG_RTC_OSC_RES_SW_MANUAL_SFT 0 -+#define RG_RTC_OSC_RES_SW_MANUAL_HI 9 -+#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10 -+#define RG_RTC_OSC_RES_SW_MSK 0x03ff0000 -+#define RG_RTC_OSC_RES_SW_I_MSK 0xfc00ffff -+#define RG_RTC_OSC_RES_SW_SFT 16 -+#define RG_RTC_OSC_RES_SW_HI 25 -+#define RG_RTC_OSC_RES_SW_SZ 10 -+#define RTC_OSC_CAL_RES_RDY_MSK 0x80000000 -+#define RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff -+#define RTC_OSC_CAL_RES_RDY_SFT 31 -+#define RTC_OSC_CAL_RES_RDY_HI 31 -+#define RTC_OSC_CAL_RES_RDY_SZ 1 -+#define RG_DCDC_MODE_MSK 0x00000001 -+#define RG_DCDC_MODE_I_MSK 0xfffffffe -+#define RG_DCDC_MODE_SFT 0 -+#define RG_DCDC_MODE_HI 0 -+#define RG_DCDC_MODE_SZ 1 -+#define RG_BUCK_EN_PSM_MSK 0x00000010 -+#define RG_BUCK_EN_PSM_I_MSK 0xffffffef -+#define RG_BUCK_EN_PSM_SFT 4 -+#define RG_BUCK_EN_PSM_HI 4 -+#define RG_BUCK_EN_PSM_SZ 1 -+#define RG_BUCK_PSM_VTH_MSK 0x00000100 -+#define RG_BUCK_PSM_VTH_I_MSK 0xfffffeff -+#define RG_BUCK_PSM_VTH_SFT 8 -+#define RG_BUCK_PSM_VTH_HI 8 -+#define RG_BUCK_PSM_VTH_SZ 1 -+#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00001000 -+#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xffffefff -+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 12 -+#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 12 -+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1 -+#define RG_RTC_RDY_DEGLITCH_TIMER_MSK 0x00006000 -+#define RG_RTC_RDY_DEGLITCH_TIMER_I_MSK 0xffff9fff -+#define RG_RTC_RDY_DEGLITCH_TIMER_SFT 13 -+#define RG_RTC_RDY_DEGLITCH_TIMER_HI 14 -+#define RG_RTC_RDY_DEGLITCH_TIMER_SZ 2 -+#define RTC_CAL_ENA_MSK 0x00010000 -+#define RTC_CAL_ENA_I_MSK 0xfffeffff -+#define RTC_CAL_ENA_SFT 16 -+#define RTC_CAL_ENA_HI 16 -+#define RTC_CAL_ENA_SZ 1 -+#define PMU_WAKE_TRIG_EVENT_MSK 0x00000003 -+#define PMU_WAKE_TRIG_EVENT_I_MSK 0xfffffffc -+#define PMU_WAKE_TRIG_EVENT_SFT 0 -+#define PMU_WAKE_TRIG_EVENT_HI 1 -+#define PMU_WAKE_TRIG_EVENT_SZ 2 -+#define DIGI_TOP_POR_MASK_MSK 0x00000010 -+#define DIGI_TOP_POR_MASK_I_MSK 0xffffffef -+#define DIGI_TOP_POR_MASK_SFT 4 -+#define DIGI_TOP_POR_MASK_HI 4 -+#define DIGI_TOP_POR_MASK_SZ 1 -+#define PMU_ENTER_SLEEP_MODE_MSK 0x00000100 -+#define PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffeff -+#define PMU_ENTER_SLEEP_MODE_SFT 8 -+#define PMU_ENTER_SLEEP_MODE_HI 8 -+#define PMU_ENTER_SLEEP_MODE_SZ 1 -+#define RG_RTC_DUMMIES_MSK 0xffff0000 -+#define RG_RTC_DUMMIES_I_MSK 0x0000ffff -+#define RG_RTC_DUMMIES_SFT 16 -+#define RG_RTC_DUMMIES_HI 31 -+#define RG_RTC_DUMMIES_SZ 16 -+#define RTC_EN_MSK 0x00000001 -+#define RTC_EN_I_MSK 0xfffffffe -+#define RTC_EN_SFT 0 -+#define RTC_EN_HI 0 -+#define RTC_EN_SZ 1 -+#define RTC_SRC_MSK 0x00000002 -+#define RTC_SRC_I_MSK 0xfffffffd -+#define RTC_SRC_SFT 1 -+#define RTC_SRC_HI 1 -+#define RTC_SRC_SZ 1 -+#define RTC_TICK_CNT_MSK 0x7fff0000 -+#define RTC_TICK_CNT_I_MSK 0x8000ffff -+#define RTC_TICK_CNT_SFT 16 -+#define RTC_TICK_CNT_HI 30 -+#define RTC_TICK_CNT_SZ 15 -+#define RTC_INT_SEC_MASK_MSK 0x00000001 -+#define RTC_INT_SEC_MASK_I_MSK 0xfffffffe -+#define RTC_INT_SEC_MASK_SFT 0 -+#define RTC_INT_SEC_MASK_HI 0 -+#define RTC_INT_SEC_MASK_SZ 1 -+#define RTC_INT_ALARM_MASK_MSK 0x00000002 -+#define RTC_INT_ALARM_MASK_I_MSK 0xfffffffd -+#define RTC_INT_ALARM_MASK_SFT 1 -+#define RTC_INT_ALARM_MASK_HI 1 -+#define RTC_INT_ALARM_MASK_SZ 1 -+#define RTC_INT_SEC_MSK 0x00010000 -+#define RTC_INT_SEC_I_MSK 0xfffeffff -+#define RTC_INT_SEC_SFT 16 -+#define RTC_INT_SEC_HI 16 -+#define RTC_INT_SEC_SZ 1 -+#define RTC_INT_ALARM_MSK 0x00020000 -+#define RTC_INT_ALARM_I_MSK 0xfffdffff -+#define RTC_INT_ALARM_SFT 17 -+#define RTC_INT_ALARM_HI 17 -+#define RTC_INT_ALARM_SZ 1 -+#define RTC_SEC_START_CNT_MSK 0xffffffff -+#define RTC_SEC_START_CNT_I_MSK 0x00000000 -+#define RTC_SEC_START_CNT_SFT 0 -+#define RTC_SEC_START_CNT_HI 31 -+#define RTC_SEC_START_CNT_SZ 32 -+#define RTC_SEC_CNT_MSK 0xffffffff -+#define RTC_SEC_CNT_I_MSK 0x00000000 -+#define RTC_SEC_CNT_SFT 0 -+#define RTC_SEC_CNT_HI 31 -+#define RTC_SEC_CNT_SZ 32 -+#define RTC_SEC_ALARM_VALUE_MSK 0xffffffff -+#define RTC_SEC_ALARM_VALUE_I_MSK 0x00000000 -+#define RTC_SEC_ALARM_VALUE_SFT 0 -+#define RTC_SEC_ALARM_VALUE_HI 31 -+#define RTC_SEC_ALARM_VALUE_SZ 32 -+#define D2_DMA_ADR_SRC_MSK 0xffffffff -+#define D2_DMA_ADR_SRC_I_MSK 0x00000000 -+#define D2_DMA_ADR_SRC_SFT 0 -+#define D2_DMA_ADR_SRC_HI 31 -+#define D2_DMA_ADR_SRC_SZ 32 -+#define D2_DMA_ADR_DST_MSK 0xffffffff -+#define D2_DMA_ADR_DST_I_MSK 0x00000000 -+#define D2_DMA_ADR_DST_SFT 0 -+#define D2_DMA_ADR_DST_HI 31 -+#define D2_DMA_ADR_DST_SZ 32 -+#define D2_DMA_SRC_SIZE_MSK 0x00000007 -+#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8 -+#define D2_DMA_SRC_SIZE_SFT 0 -+#define D2_DMA_SRC_SIZE_HI 2 -+#define D2_DMA_SRC_SIZE_SZ 3 -+#define D2_DMA_SRC_INC_MSK 0x00000008 -+#define D2_DMA_SRC_INC_I_MSK 0xfffffff7 -+#define D2_DMA_SRC_INC_SFT 3 -+#define D2_DMA_SRC_INC_HI 3 -+#define D2_DMA_SRC_INC_SZ 1 -+#define D2_DMA_DST_SIZE_MSK 0x00000070 -+#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f -+#define D2_DMA_DST_SIZE_SFT 4 -+#define D2_DMA_DST_SIZE_HI 6 -+#define D2_DMA_DST_SIZE_SZ 3 -+#define D2_DMA_DST_INC_MSK 0x00000080 -+#define D2_DMA_DST_INC_I_MSK 0xffffff7f -+#define D2_DMA_DST_INC_SFT 7 -+#define D2_DMA_DST_INC_HI 7 -+#define D2_DMA_DST_INC_SZ 1 -+#define D2_DMA_FAST_FILL_MSK 0x00000100 -+#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff -+#define D2_DMA_FAST_FILL_SFT 8 -+#define D2_DMA_FAST_FILL_HI 8 -+#define D2_DMA_FAST_FILL_SZ 1 -+#define D2_DMA_SDIO_KICK_MSK 0x00001000 -+#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff -+#define D2_DMA_SDIO_KICK_SFT 12 -+#define D2_DMA_SDIO_KICK_HI 12 -+#define D2_DMA_SDIO_KICK_SZ 1 -+#define D2_DMA_BADR_EN_MSK 0x00002000 -+#define D2_DMA_BADR_EN_I_MSK 0xffffdfff -+#define D2_DMA_BADR_EN_SFT 13 -+#define D2_DMA_BADR_EN_HI 13 -+#define D2_DMA_BADR_EN_SZ 1 -+#define D2_DMA_LEN_MSK 0xffff0000 -+#define D2_DMA_LEN_I_MSK 0x0000ffff -+#define D2_DMA_LEN_SFT 16 -+#define D2_DMA_LEN_HI 31 -+#define D2_DMA_LEN_SZ 16 -+#define D2_DMA_INT_MASK_MSK 0x00000001 -+#define D2_DMA_INT_MASK_I_MSK 0xfffffffe -+#define D2_DMA_INT_MASK_SFT 0 -+#define D2_DMA_INT_MASK_HI 0 -+#define D2_DMA_INT_MASK_SZ 1 -+#define D2_DMA_STS_MSK 0x00000100 -+#define D2_DMA_STS_I_MSK 0xfffffeff -+#define D2_DMA_STS_SFT 8 -+#define D2_DMA_STS_HI 8 -+#define D2_DMA_STS_SZ 1 -+#define D2_DMA_FINISH_MSK 0x80000000 -+#define D2_DMA_FINISH_I_MSK 0x7fffffff -+#define D2_DMA_FINISH_SFT 31 -+#define D2_DMA_FINISH_HI 31 -+#define D2_DMA_FINISH_SZ 1 -+#define D2_DMA_CONST_MSK 0xffffffff -+#define D2_DMA_CONST_I_MSK 0x00000000 -+#define D2_DMA_CONST_SFT 0 -+#define D2_DMA_CONST_HI 31 -+#define D2_DMA_CONST_SZ 32 -+#define TRAP_UNKNOWN_TYPE_MSK 0x00000001 -+#define TRAP_UNKNOWN_TYPE_I_MSK 0xfffffffe -+#define TRAP_UNKNOWN_TYPE_SFT 0 -+#define TRAP_UNKNOWN_TYPE_HI 0 -+#define TRAP_UNKNOWN_TYPE_SZ 1 -+#define TX_ON_DEMAND_ENA_MSK 0x00000002 -+#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd -+#define TX_ON_DEMAND_ENA_SFT 1 -+#define TX_ON_DEMAND_ENA_HI 1 -+#define TX_ON_DEMAND_ENA_SZ 1 -+#define RX_2_HOST_MSK 0x00000004 -+#define RX_2_HOST_I_MSK 0xfffffffb -+#define RX_2_HOST_SFT 2 -+#define RX_2_HOST_HI 2 -+#define RX_2_HOST_SZ 1 -+#define AUTO_SEQNO_MSK 0x00000008 -+#define AUTO_SEQNO_I_MSK 0xfffffff7 -+#define AUTO_SEQNO_SFT 3 -+#define AUTO_SEQNO_HI 3 -+#define AUTO_SEQNO_SZ 1 -+#define BYPASSS_TX_PARSER_ENCAP_MSK 0x00000010 -+#define BYPASSS_TX_PARSER_ENCAP_I_MSK 0xffffffef -+#define BYPASSS_TX_PARSER_ENCAP_SFT 4 -+#define BYPASSS_TX_PARSER_ENCAP_HI 4 -+#define BYPASSS_TX_PARSER_ENCAP_SZ 1 -+#define HDR_STRIP_MSK 0x00000020 -+#define HDR_STRIP_I_MSK 0xffffffdf -+#define HDR_STRIP_SFT 5 -+#define HDR_STRIP_HI 5 -+#define HDR_STRIP_SZ 1 -+#define ERP_PROTECT_MSK 0x000000c0 -+#define ERP_PROTECT_I_MSK 0xffffff3f -+#define ERP_PROTECT_SFT 6 -+#define ERP_PROTECT_HI 7 -+#define ERP_PROTECT_SZ 2 -+#define PRO_VER_MSK 0x00000300 -+#define PRO_VER_I_MSK 0xfffffcff -+#define PRO_VER_SFT 8 -+#define PRO_VER_HI 9 -+#define PRO_VER_SZ 2 -+#define TXQ_ID0_MSK 0x00007000 -+#define TXQ_ID0_I_MSK 0xffff8fff -+#define TXQ_ID0_SFT 12 -+#define TXQ_ID0_HI 14 -+#define TXQ_ID0_SZ 3 -+#define TXQ_ID1_MSK 0x00070000 -+#define TXQ_ID1_I_MSK 0xfff8ffff -+#define TXQ_ID1_SFT 16 -+#define TXQ_ID1_HI 18 -+#define TXQ_ID1_SZ 3 -+#define TX_ETHER_TRAP_EN_MSK 0x00100000 -+#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff -+#define TX_ETHER_TRAP_EN_SFT 20 -+#define TX_ETHER_TRAP_EN_HI 20 -+#define TX_ETHER_TRAP_EN_SZ 1 -+#define RX_ETHER_TRAP_EN_MSK 0x00200000 -+#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff -+#define RX_ETHER_TRAP_EN_SFT 21 -+#define RX_ETHER_TRAP_EN_HI 21 -+#define RX_ETHER_TRAP_EN_SZ 1 -+#define RX_NULL_TRAP_EN_MSK 0x00400000 -+#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff -+#define RX_NULL_TRAP_EN_SFT 22 -+#define RX_NULL_TRAP_EN_HI 22 -+#define RX_NULL_TRAP_EN_SZ 1 -+#define RX_GET_TX_QUEUE_EN_MSK 0x02000000 -+#define RX_GET_TX_QUEUE_EN_I_MSK 0xfdffffff -+#define RX_GET_TX_QUEUE_EN_SFT 25 -+#define RX_GET_TX_QUEUE_EN_HI 25 -+#define RX_GET_TX_QUEUE_EN_SZ 1 -+#define HCI_INQ_SEL_MSK 0x04000000 -+#define HCI_INQ_SEL_I_MSK 0xfbffffff -+#define HCI_INQ_SEL_SFT 26 -+#define HCI_INQ_SEL_HI 26 -+#define HCI_INQ_SEL_SZ 1 -+#define TRX_DEBUG_CNT_ENA_MSK 0x10000000 -+#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff -+#define TRX_DEBUG_CNT_ENA_SFT 28 -+#define TRX_DEBUG_CNT_ENA_HI 28 -+#define TRX_DEBUG_CNT_ENA_SZ 1 -+#define WAKE_SOON_WITH_SCK_MSK 0x00000001 -+#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe -+#define WAKE_SOON_WITH_SCK_SFT 0 -+#define WAKE_SOON_WITH_SCK_HI 0 -+#define WAKE_SOON_WITH_SCK_SZ 1 -+#define TX_FLOW_CTRL_MSK 0x0000ffff -+#define TX_FLOW_CTRL_I_MSK 0xffff0000 -+#define TX_FLOW_CTRL_SFT 0 -+#define TX_FLOW_CTRL_HI 15 -+#define TX_FLOW_CTRL_SZ 16 -+#define TX_FLOW_MGMT_MSK 0xffff0000 -+#define TX_FLOW_MGMT_I_MSK 0x0000ffff -+#define TX_FLOW_MGMT_SFT 16 -+#define TX_FLOW_MGMT_HI 31 -+#define TX_FLOW_MGMT_SZ 16 -+#define TX_FLOW_DATA_MSK 0xffffffff -+#define TX_FLOW_DATA_I_MSK 0x00000000 -+#define TX_FLOW_DATA_SFT 0 -+#define TX_FLOW_DATA_HI 31 -+#define TX_FLOW_DATA_SZ 32 -+#define DOT11RTSTHRESHOLD_MSK 0xffff0000 -+#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff -+#define DOT11RTSTHRESHOLD_SFT 16 -+#define DOT11RTSTHRESHOLD_HI 31 -+#define DOT11RTSTHRESHOLD_SZ 16 -+#define TXF_ID_MSK 0x0000003f -+#define TXF_ID_I_MSK 0xffffffc0 -+#define TXF_ID_SFT 0 -+#define TXF_ID_HI 5 -+#define TXF_ID_SZ 6 -+#define SEQ_CTRL_MSK 0x0000ffff -+#define SEQ_CTRL_I_MSK 0xffff0000 -+#define SEQ_CTRL_SFT 0 -+#define SEQ_CTRL_HI 15 -+#define SEQ_CTRL_SZ 16 -+#define TX_PBOFFSET_MSK 0x000000ff -+#define TX_PBOFFSET_I_MSK 0xffffff00 -+#define TX_PBOFFSET_SFT 0 -+#define TX_PBOFFSET_HI 7 -+#define TX_PBOFFSET_SZ 8 -+#define TX_INFO_SIZE_MSK 0x0000ff00 -+#define TX_INFO_SIZE_I_MSK 0xffff00ff -+#define TX_INFO_SIZE_SFT 8 -+#define TX_INFO_SIZE_HI 15 -+#define TX_INFO_SIZE_SZ 8 -+#define RX_INFO_SIZE_MSK 0x00ff0000 -+#define RX_INFO_SIZE_I_MSK 0xff00ffff -+#define RX_INFO_SIZE_SFT 16 -+#define RX_INFO_SIZE_HI 23 -+#define RX_INFO_SIZE_SZ 8 -+#define RX_LAST_PHY_SIZE_MSK 0xff000000 -+#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff -+#define RX_LAST_PHY_SIZE_SFT 24 -+#define RX_LAST_PHY_SIZE_HI 31 -+#define RX_LAST_PHY_SIZE_SZ 8 -+#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f -+#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0 -+#define TX_INFO_CLEAR_SIZE_SFT 0 -+#define TX_INFO_CLEAR_SIZE_HI 5 -+#define TX_INFO_CLEAR_SIZE_SZ 6 -+#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100 -+#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff -+#define TX_INFO_CLEAR_ENABLE_SFT 8 -+#define TX_INFO_CLEAR_ENABLE_HI 8 -+#define TX_INFO_CLEAR_ENABLE_SZ 1 -+#define TXTRAP_ETHTYPE1_MSK 0x0000ffff -+#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000 -+#define TXTRAP_ETHTYPE1_SFT 0 -+#define TXTRAP_ETHTYPE1_HI 15 -+#define TXTRAP_ETHTYPE1_SZ 16 -+#define TXTRAP_ETHTYPE0_MSK 0xffff0000 -+#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff -+#define TXTRAP_ETHTYPE0_SFT 16 -+#define TXTRAP_ETHTYPE0_HI 31 -+#define TXTRAP_ETHTYPE0_SZ 16 -+#define RXTRAP_ETHTYPE1_MSK 0x0000ffff -+#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000 -+#define RXTRAP_ETHTYPE1_SFT 0 -+#define RXTRAP_ETHTYPE1_HI 15 -+#define RXTRAP_ETHTYPE1_SZ 16 -+#define RXTRAP_ETHTYPE0_MSK 0xffff0000 -+#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff -+#define RXTRAP_ETHTYPE0_SFT 16 -+#define RXTRAP_ETHTYPE0_HI 31 -+#define RXTRAP_ETHTYPE0_SZ 16 -+#define TX_PKT_COUNTER_MSK 0xffffffff -+#define TX_PKT_COUNTER_I_MSK 0x00000000 -+#define TX_PKT_COUNTER_SFT 0 -+#define TX_PKT_COUNTER_HI 31 -+#define TX_PKT_COUNTER_SZ 32 -+#define RX_PKT_COUNTER_MSK 0xffffffff -+#define RX_PKT_COUNTER_I_MSK 0x00000000 -+#define RX_PKT_COUNTER_SFT 0 -+#define RX_PKT_COUNTER_HI 31 -+#define RX_PKT_COUNTER_SZ 32 -+#define HOST_CMD_COUNTER_MSK 0x000000ff -+#define HOST_CMD_COUNTER_I_MSK 0xffffff00 -+#define HOST_CMD_COUNTER_SFT 0 -+#define HOST_CMD_COUNTER_HI 7 -+#define HOST_CMD_COUNTER_SZ 8 -+#define HOST_EVENT_COUNTER_MSK 0x000000ff -+#define HOST_EVENT_COUNTER_I_MSK 0xffffff00 -+#define HOST_EVENT_COUNTER_SFT 0 -+#define HOST_EVENT_COUNTER_HI 7 -+#define HOST_EVENT_COUNTER_SZ 8 -+#define TX_PKT_DROP_COUNTER_MSK 0x000000ff -+#define TX_PKT_DROP_COUNTER_I_MSK 0xffffff00 -+#define TX_PKT_DROP_COUNTER_SFT 0 -+#define TX_PKT_DROP_COUNTER_HI 7 -+#define TX_PKT_DROP_COUNTER_SZ 8 -+#define RX_PKT_DROP_COUNTER_MSK 0x000000ff -+#define RX_PKT_DROP_COUNTER_I_MSK 0xffffff00 -+#define RX_PKT_DROP_COUNTER_SFT 0 -+#define RX_PKT_DROP_COUNTER_HI 7 -+#define RX_PKT_DROP_COUNTER_SZ 8 -+#define TX_PKT_TRAP_COUNTER_MSK 0x000000ff -+#define TX_PKT_TRAP_COUNTER_I_MSK 0xffffff00 -+#define TX_PKT_TRAP_COUNTER_SFT 0 -+#define TX_PKT_TRAP_COUNTER_HI 7 -+#define TX_PKT_TRAP_COUNTER_SZ 8 -+#define RX_PKT_TRAP_COUNTER_MSK 0x000000ff -+#define RX_PKT_TRAP_COUNTER_I_MSK 0xffffff00 -+#define RX_PKT_TRAP_COUNTER_SFT 0 -+#define RX_PKT_TRAP_COUNTER_HI 7 -+#define RX_PKT_TRAP_COUNTER_SZ 8 -+#define HOST_TX_FAIL_COUNTER_MSK 0x000000ff -+#define HOST_TX_FAIL_COUNTER_I_MSK 0xffffff00 -+#define HOST_TX_FAIL_COUNTER_SFT 0 -+#define HOST_TX_FAIL_COUNTER_HI 7 -+#define HOST_TX_FAIL_COUNTER_SZ 8 -+#define HOST_RX_FAIL_COUNTER_MSK 0x000000ff -+#define HOST_RX_FAIL_COUNTER_I_MSK 0xffffff00 -+#define HOST_RX_FAIL_COUNTER_SFT 0 -+#define HOST_RX_FAIL_COUNTER_HI 7 -+#define HOST_RX_FAIL_COUNTER_SZ 8 -+#define HCI_STATE_MONITOR_MSK 0xffffffff -+#define HCI_STATE_MONITOR_I_MSK 0x00000000 -+#define HCI_STATE_MONITOR_SFT 0 -+#define HCI_STATE_MONITOR_HI 31 -+#define HCI_STATE_MONITOR_SZ 32 -+#define HCI_ST_TIMEOUT_MONITOR_MSK 0xffffffff -+#define HCI_ST_TIMEOUT_MONITOR_I_MSK 0x00000000 -+#define HCI_ST_TIMEOUT_MONITOR_SFT 0 -+#define HCI_ST_TIMEOUT_MONITOR_HI 31 -+#define HCI_ST_TIMEOUT_MONITOR_SZ 32 -+#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff -+#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000 -+#define TX_ON_DEMAND_LENGTH_SFT 0 -+#define TX_ON_DEMAND_LENGTH_HI 31 -+#define TX_ON_DEMAND_LENGTH_SZ 32 -+#define HCI_MONITOR_REG1_MSK 0xffffffff -+#define HCI_MONITOR_REG1_I_MSK 0x00000000 -+#define HCI_MONITOR_REG1_SFT 0 -+#define HCI_MONITOR_REG1_HI 31 -+#define HCI_MONITOR_REG1_SZ 32 -+#define HCI_MONITOR_REG2_MSK 0xffffffff -+#define HCI_MONITOR_REG2_I_MSK 0x00000000 -+#define HCI_MONITOR_REG2_SFT 0 -+#define HCI_MONITOR_REG2_HI 31 -+#define HCI_MONITOR_REG2_SZ 32 -+#define HCI_TX_ALLOC_TIME_31_0_MSK 0xffffffff -+#define HCI_TX_ALLOC_TIME_31_0_I_MSK 0x00000000 -+#define HCI_TX_ALLOC_TIME_31_0_SFT 0 -+#define HCI_TX_ALLOC_TIME_31_0_HI 31 -+#define HCI_TX_ALLOC_TIME_31_0_SZ 32 -+#define HCI_TX_ALLOC_TIME_47_32_MSK 0x0000ffff -+#define HCI_TX_ALLOC_TIME_47_32_I_MSK 0xffff0000 -+#define HCI_TX_ALLOC_TIME_47_32_SFT 0 -+#define HCI_TX_ALLOC_TIME_47_32_HI 15 -+#define HCI_TX_ALLOC_TIME_47_32_SZ 16 -+#define HCI_MB_MAX_CNT_MSK 0x00ff0000 -+#define HCI_MB_MAX_CNT_I_MSK 0xff00ffff -+#define HCI_MB_MAX_CNT_SFT 16 -+#define HCI_MB_MAX_CNT_HI 23 -+#define HCI_MB_MAX_CNT_SZ 8 -+#define HCI_TX_ALLOC_CNT_31_0_MSK 0xffffffff -+#define HCI_TX_ALLOC_CNT_31_0_I_MSK 0x00000000 -+#define HCI_TX_ALLOC_CNT_31_0_SFT 0 -+#define HCI_TX_ALLOC_CNT_31_0_HI 31 -+#define HCI_TX_ALLOC_CNT_31_0_SZ 32 -+#define HCI_TX_ALLOC_CNT_47_32_MSK 0x0000ffff -+#define HCI_TX_ALLOC_CNT_47_32_I_MSK 0xffff0000 -+#define HCI_TX_ALLOC_CNT_47_32_SFT 0 -+#define HCI_TX_ALLOC_CNT_47_32_HI 15 -+#define HCI_TX_ALLOC_CNT_47_32_SZ 16 -+#define HCI_PROC_CNT_MSK 0x00ff0000 -+#define HCI_PROC_CNT_I_MSK 0xff00ffff -+#define HCI_PROC_CNT_SFT 16 -+#define HCI_PROC_CNT_HI 23 -+#define HCI_PROC_CNT_SZ 8 -+#define SDIO_TRANS_CNT_MSK 0xff000000 -+#define SDIO_TRANS_CNT_I_MSK 0x00ffffff -+#define SDIO_TRANS_CNT_SFT 24 -+#define SDIO_TRANS_CNT_HI 31 -+#define SDIO_TRANS_CNT_SZ 8 -+#define SDIO_TX_INVALID_CNT_31_0_MSK 0xffffffff -+#define SDIO_TX_INVALID_CNT_31_0_I_MSK 0x00000000 -+#define SDIO_TX_INVALID_CNT_31_0_SFT 0 -+#define SDIO_TX_INVALID_CNT_31_0_HI 31 -+#define SDIO_TX_INVALID_CNT_31_0_SZ 32 -+#define SDIO_TX_INVALID_CNT_47_32_MSK 0x0000ffff -+#define SDIO_TX_INVALID_CNT_47_32_I_MSK 0xffff0000 -+#define SDIO_TX_INVALID_CNT_47_32_SFT 0 -+#define SDIO_TX_INVALID_CNT_47_32_HI 15 -+#define SDIO_TX_INVALID_CNT_47_32_SZ 16 -+#define CS_START_ADDR_MSK 0x0000ffff -+#define CS_START_ADDR_I_MSK 0xffff0000 -+#define CS_START_ADDR_SFT 0 -+#define CS_START_ADDR_HI 15 -+#define CS_START_ADDR_SZ 16 -+#define CS_PKT_ID_MSK 0x007f0000 -+#define CS_PKT_ID_I_MSK 0xff80ffff -+#define CS_PKT_ID_SFT 16 -+#define CS_PKT_ID_HI 22 -+#define CS_PKT_ID_SZ 7 -+#define ADD_LEN_MSK 0x0000ffff -+#define ADD_LEN_I_MSK 0xffff0000 -+#define ADD_LEN_SFT 0 -+#define ADD_LEN_HI 15 -+#define ADD_LEN_SZ 16 -+#define CS_ADDER_EN_MSK 0x00000001 -+#define CS_ADDER_EN_I_MSK 0xfffffffe -+#define CS_ADDER_EN_SFT 0 -+#define CS_ADDER_EN_HI 0 -+#define CS_ADDER_EN_SZ 1 -+#define PSEUDO_MSK 0x00000002 -+#define PSEUDO_I_MSK 0xfffffffd -+#define PSEUDO_SFT 1 -+#define PSEUDO_HI 1 -+#define PSEUDO_SZ 1 -+#define CALCULATE_MSK 0xffffffff -+#define CALCULATE_I_MSK 0x00000000 -+#define CALCULATE_SFT 0 -+#define CALCULATE_HI 31 -+#define CALCULATE_SZ 32 -+#define L4_LEN_MSK 0x0000ffff -+#define L4_LEN_I_MSK 0xffff0000 -+#define L4_LEN_SFT 0 -+#define L4_LEN_HI 15 -+#define L4_LEN_SZ 16 -+#define L4_PROTOL_MSK 0x00ff0000 -+#define L4_PROTOL_I_MSK 0xff00ffff -+#define L4_PROTOL_SFT 16 -+#define L4_PROTOL_HI 23 -+#define L4_PROTOL_SZ 8 -+#define CHECK_SUM_MSK 0x0000ffff -+#define CHECK_SUM_I_MSK 0xffff0000 -+#define CHECK_SUM_SFT 0 -+#define CHECK_SUM_HI 15 -+#define CHECK_SUM_SZ 16 -+#define RAND_EN_MSK 0x00000001 -+#define RAND_EN_I_MSK 0xfffffffe -+#define RAND_EN_SFT 0 -+#define RAND_EN_HI 0 -+#define RAND_EN_SZ 1 -+#define RAND_NUM_MSK 0xffffffff -+#define RAND_NUM_I_MSK 0x00000000 -+#define RAND_NUM_SFT 0 -+#define RAND_NUM_HI 31 -+#define RAND_NUM_SZ 32 -+#define MUL_OP1_MSK 0xffffffff -+#define MUL_OP1_I_MSK 0x00000000 -+#define MUL_OP1_SFT 0 -+#define MUL_OP1_HI 31 -+#define MUL_OP1_SZ 32 -+#define MUL_OP2_MSK 0xffffffff -+#define MUL_OP2_I_MSK 0x00000000 -+#define MUL_OP2_SFT 0 -+#define MUL_OP2_HI 31 -+#define MUL_OP2_SZ 32 -+#define MUL_ANS0_MSK 0xffffffff -+#define MUL_ANS0_I_MSK 0x00000000 -+#define MUL_ANS0_SFT 0 -+#define MUL_ANS0_HI 31 -+#define MUL_ANS0_SZ 32 -+#define MUL_ANS1_MSK 0xffffffff -+#define MUL_ANS1_I_MSK 0x00000000 -+#define MUL_ANS1_SFT 0 -+#define MUL_ANS1_HI 31 -+#define MUL_ANS1_SZ 32 -+#define RD_ADDR_MSK 0x0000ffff -+#define RD_ADDR_I_MSK 0xffff0000 -+#define RD_ADDR_SFT 0 -+#define RD_ADDR_HI 15 -+#define RD_ADDR_SZ 16 -+#define RD_ID_MSK 0x007f0000 -+#define RD_ID_I_MSK 0xff80ffff -+#define RD_ID_SFT 16 -+#define RD_ID_HI 22 -+#define RD_ID_SZ 7 -+#define WR_ADDR_MSK 0x0000ffff -+#define WR_ADDR_I_MSK 0xffff0000 -+#define WR_ADDR_SFT 0 -+#define WR_ADDR_HI 15 -+#define WR_ADDR_SZ 16 -+#define WR_ID_MSK 0x007f0000 -+#define WR_ID_I_MSK 0xff80ffff -+#define WR_ID_SFT 16 -+#define WR_ID_HI 22 -+#define WR_ID_SZ 7 -+#define LEN_MSK 0x0000ffff -+#define LEN_I_MSK 0xffff0000 -+#define LEN_SFT 0 -+#define LEN_HI 15 -+#define LEN_SZ 16 -+#define CLR_MSK 0x00000001 -+#define CLR_I_MSK 0xfffffffe -+#define CLR_SFT 0 -+#define CLR_HI 0 -+#define CLR_SZ 1 -+#define PHY_MODE_MSK 0x00000003 -+#define PHY_MODE_I_MSK 0xfffffffc -+#define PHY_MODE_SFT 0 -+#define PHY_MODE_HI 1 -+#define PHY_MODE_SZ 2 -+#define SHRT_PREAM_MSK 0x00000004 -+#define SHRT_PREAM_I_MSK 0xfffffffb -+#define SHRT_PREAM_SFT 2 -+#define SHRT_PREAM_HI 2 -+#define SHRT_PREAM_SZ 1 -+#define SHRT_GI_MSK 0x00000008 -+#define SHRT_GI_I_MSK 0xfffffff7 -+#define SHRT_GI_SFT 3 -+#define SHRT_GI_HI 3 -+#define SHRT_GI_SZ 1 -+#define DATA_RATE_MSK 0x000007f0 -+#define DATA_RATE_I_MSK 0xfffff80f -+#define DATA_RATE_SFT 4 -+#define DATA_RATE_HI 10 -+#define DATA_RATE_SZ 7 -+#define MCS_MSK 0x00007000 -+#define MCS_I_MSK 0xffff8fff -+#define MCS_SFT 12 -+#define MCS_HI 14 -+#define MCS_SZ 3 -+#define FRAME_LEN_MSK 0xffff0000 -+#define FRAME_LEN_I_MSK 0x0000ffff -+#define FRAME_LEN_SFT 16 -+#define FRAME_LEN_HI 31 -+#define FRAME_LEN_SZ 16 -+#define DURATION_MSK 0x0000ffff -+#define DURATION_I_MSK 0xffff0000 -+#define DURATION_SFT 0 -+#define DURATION_HI 15 -+#define DURATION_SZ 16 -+#define SHA_DST_ADDR_MSK 0xffffffff -+#define SHA_DST_ADDR_I_MSK 0x00000000 -+#define SHA_DST_ADDR_SFT 0 -+#define SHA_DST_ADDR_HI 31 -+#define SHA_DST_ADDR_SZ 32 -+#define SHA_SRC_ADDR_MSK 0xffffffff -+#define SHA_SRC_ADDR_I_MSK 0x00000000 -+#define SHA_SRC_ADDR_SFT 0 -+#define SHA_SRC_ADDR_HI 31 -+#define SHA_SRC_ADDR_SZ 32 -+#define SHA_BUSY_MSK 0x00000001 -+#define SHA_BUSY_I_MSK 0xfffffffe -+#define SHA_BUSY_SFT 0 -+#define SHA_BUSY_HI 0 -+#define SHA_BUSY_SZ 1 -+#define SHA_ENDIAN_MSK 0x00000002 -+#define SHA_ENDIAN_I_MSK 0xfffffffd -+#define SHA_ENDIAN_SFT 1 -+#define SHA_ENDIAN_HI 1 -+#define SHA_ENDIAN_SZ 1 -+#define EFS_CLKFREQ_MSK 0x00000fff -+#define EFS_CLKFREQ_I_MSK 0xfffff000 -+#define EFS_CLKFREQ_SFT 0 -+#define EFS_CLKFREQ_HI 11 -+#define EFS_CLKFREQ_SZ 12 -+#define LOW_ACTIVE_MSK 0x00010000 -+#define LOW_ACTIVE_I_MSK 0xfffeffff -+#define LOW_ACTIVE_SFT 16 -+#define LOW_ACTIVE_HI 16 -+#define LOW_ACTIVE_SZ 1 -+#define EFS_CLKFREQ_RD_MSK 0x0ff00000 -+#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff -+#define EFS_CLKFREQ_RD_SFT 20 -+#define EFS_CLKFREQ_RD_HI 27 -+#define EFS_CLKFREQ_RD_SZ 8 -+#define EFS_PRE_RD_MSK 0xf0000000 -+#define EFS_PRE_RD_I_MSK 0x0fffffff -+#define EFS_PRE_RD_SFT 28 -+#define EFS_PRE_RD_HI 31 -+#define EFS_PRE_RD_SZ 4 -+#define EFS_LDO_ON_MSK 0x0000ffff -+#define EFS_LDO_ON_I_MSK 0xffff0000 -+#define EFS_LDO_ON_SFT 0 -+#define EFS_LDO_ON_HI 15 -+#define EFS_LDO_ON_SZ 16 -+#define EFS_LDO_OFF_MSK 0xffff0000 -+#define EFS_LDO_OFF_I_MSK 0x0000ffff -+#define EFS_LDO_OFF_SFT 16 -+#define EFS_LDO_OFF_HI 31 -+#define EFS_LDO_OFF_SZ 16 -+#define EFS_RDATA_0_MSK 0xffffffff -+#define EFS_RDATA_0_I_MSK 0x00000000 -+#define EFS_RDATA_0_SFT 0 -+#define EFS_RDATA_0_HI 31 -+#define EFS_RDATA_0_SZ 32 -+#define EFS_WDATA_0_MSK 0xffffffff -+#define EFS_WDATA_0_I_MSK 0x00000000 -+#define EFS_WDATA_0_SFT 0 -+#define EFS_WDATA_0_HI 31 -+#define EFS_WDATA_0_SZ 32 -+#define EFS_RDATA_1_MSK 0xffffffff -+#define EFS_RDATA_1_I_MSK 0x00000000 -+#define EFS_RDATA_1_SFT 0 -+#define EFS_RDATA_1_HI 31 -+#define EFS_RDATA_1_SZ 32 -+#define EFS_WDATA_1_MSK 0xffffffff -+#define EFS_WDATA_1_I_MSK 0x00000000 -+#define EFS_WDATA_1_SFT 0 -+#define EFS_WDATA_1_HI 31 -+#define EFS_WDATA_1_SZ 32 -+#define EFS_RDATA_2_MSK 0xffffffff -+#define EFS_RDATA_2_I_MSK 0x00000000 -+#define EFS_RDATA_2_SFT 0 -+#define EFS_RDATA_2_HI 31 -+#define EFS_RDATA_2_SZ 32 -+#define EFS_WDATA_2_MSK 0xffffffff -+#define EFS_WDATA_2_I_MSK 0x00000000 -+#define EFS_WDATA_2_SFT 0 -+#define EFS_WDATA_2_HI 31 -+#define EFS_WDATA_2_SZ 32 -+#define EFS_RDATA_3_MSK 0xffffffff -+#define EFS_RDATA_3_I_MSK 0x00000000 -+#define EFS_RDATA_3_SFT 0 -+#define EFS_RDATA_3_HI 31 -+#define EFS_RDATA_3_SZ 32 -+#define EFS_WDATA_3_MSK 0xffffffff -+#define EFS_WDATA_3_I_MSK 0x00000000 -+#define EFS_WDATA_3_SFT 0 -+#define EFS_WDATA_3_HI 31 -+#define EFS_WDATA_3_SZ 32 -+#define EFS_RDATA_4_MSK 0xffffffff -+#define EFS_RDATA_4_I_MSK 0x00000000 -+#define EFS_RDATA_4_SFT 0 -+#define EFS_RDATA_4_HI 31 -+#define EFS_RDATA_4_SZ 32 -+#define EFS_WDATA_4_MSK 0xffffffff -+#define EFS_WDATA_4_I_MSK 0x00000000 -+#define EFS_WDATA_4_SFT 0 -+#define EFS_WDATA_4_HI 31 -+#define EFS_WDATA_4_SZ 32 -+#define EFS_RDATA_5_MSK 0xffffffff -+#define EFS_RDATA_5_I_MSK 0x00000000 -+#define EFS_RDATA_5_SFT 0 -+#define EFS_RDATA_5_HI 31 -+#define EFS_RDATA_5_SZ 32 -+#define EFS_WDATA_5_MSK 0xffffffff -+#define EFS_WDATA_5_I_MSK 0x00000000 -+#define EFS_WDATA_5_SFT 0 -+#define EFS_WDATA_5_HI 31 -+#define EFS_WDATA_5_SZ 32 -+#define EFS_RDATA_6_MSK 0xffffffff -+#define EFS_RDATA_6_I_MSK 0x00000000 -+#define EFS_RDATA_6_SFT 0 -+#define EFS_RDATA_6_HI 31 -+#define EFS_RDATA_6_SZ 32 -+#define EFS_WDATA_6_MSK 0xffffffff -+#define EFS_WDATA_6_I_MSK 0x00000000 -+#define EFS_WDATA_6_SFT 0 -+#define EFS_WDATA_6_HI 31 -+#define EFS_WDATA_6_SZ 32 -+#define EFS_RDATA_7_MSK 0xffffffff -+#define EFS_RDATA_7_I_MSK 0x00000000 -+#define EFS_RDATA_7_SFT 0 -+#define EFS_RDATA_7_HI 31 -+#define EFS_RDATA_7_SZ 32 -+#define EFS_WDATA_7_MSK 0xffffffff -+#define EFS_WDATA_7_I_MSK 0x00000000 -+#define EFS_WDATA_7_SFT 0 -+#define EFS_WDATA_7_HI 31 -+#define EFS_WDATA_7_SZ 32 -+#define EFS_SPI_RD0_EN_MSK 0x00000001 -+#define EFS_SPI_RD0_EN_I_MSK 0xfffffffe -+#define EFS_SPI_RD0_EN_SFT 0 -+#define EFS_SPI_RD0_EN_HI 0 -+#define EFS_SPI_RD0_EN_SZ 1 -+#define EFS_SPI_RD1_EN_MSK 0x00000001 -+#define EFS_SPI_RD1_EN_I_MSK 0xfffffffe -+#define EFS_SPI_RD1_EN_SFT 0 -+#define EFS_SPI_RD1_EN_HI 0 -+#define EFS_SPI_RD1_EN_SZ 1 -+#define EFS_SPI_RD2_EN_MSK 0x00000001 -+#define EFS_SPI_RD2_EN_I_MSK 0xfffffffe -+#define EFS_SPI_RD2_EN_SFT 0 -+#define EFS_SPI_RD2_EN_HI 0 -+#define EFS_SPI_RD2_EN_SZ 1 -+#define EFS_SPI_RD3_EN_MSK 0x00000001 -+#define EFS_SPI_RD3_EN_I_MSK 0xfffffffe -+#define EFS_SPI_RD3_EN_SFT 0 -+#define EFS_SPI_RD3_EN_HI 0 -+#define EFS_SPI_RD3_EN_SZ 1 -+#define EFS_SPI_RD4_EN_MSK 0x00000001 -+#define EFS_SPI_RD4_EN_I_MSK 0xfffffffe -+#define EFS_SPI_RD4_EN_SFT 0 -+#define EFS_SPI_RD4_EN_HI 0 -+#define EFS_SPI_RD4_EN_SZ 1 -+#define EFS_SPI_RD5_EN_MSK 0x00000001 -+#define EFS_SPI_RD5_EN_I_MSK 0xfffffffe -+#define EFS_SPI_RD5_EN_SFT 0 -+#define EFS_SPI_RD5_EN_HI 0 -+#define EFS_SPI_RD5_EN_SZ 1 -+#define EFS_SPI_RD6_EN_MSK 0x00000001 -+#define EFS_SPI_RD6_EN_I_MSK 0xfffffffe -+#define EFS_SPI_RD6_EN_SFT 0 -+#define EFS_SPI_RD6_EN_HI 0 -+#define EFS_SPI_RD6_EN_SZ 1 -+#define EFS_SPI_RD7_EN_MSK 0x00000001 -+#define EFS_SPI_RD7_EN_I_MSK 0xfffffffe -+#define EFS_SPI_RD7_EN_SFT 0 -+#define EFS_SPI_RD7_EN_HI 0 -+#define EFS_SPI_RD7_EN_SZ 1 -+#define EFS_SPI_RBUSY_MSK 0x00000001 -+#define EFS_SPI_RBUSY_I_MSK 0xfffffffe -+#define EFS_SPI_RBUSY_SFT 0 -+#define EFS_SPI_RBUSY_HI 0 -+#define EFS_SPI_RBUSY_SZ 1 -+#define EFS_SPI_RDATA_0_MSK 0xffffffff -+#define EFS_SPI_RDATA_0_I_MSK 0x00000000 -+#define EFS_SPI_RDATA_0_SFT 0 -+#define EFS_SPI_RDATA_0_HI 31 -+#define EFS_SPI_RDATA_0_SZ 32 -+#define EFS_SPI_RDATA_1_MSK 0xffffffff -+#define EFS_SPI_RDATA_1_I_MSK 0x00000000 -+#define EFS_SPI_RDATA_1_SFT 0 -+#define EFS_SPI_RDATA_1_HI 31 -+#define EFS_SPI_RDATA_1_SZ 32 -+#define EFS_SPI_RDATA_2_MSK 0xffffffff -+#define EFS_SPI_RDATA_2_I_MSK 0x00000000 -+#define EFS_SPI_RDATA_2_SFT 0 -+#define EFS_SPI_RDATA_2_HI 31 -+#define EFS_SPI_RDATA_2_SZ 32 -+#define EFS_SPI_RDATA_3_MSK 0xffffffff -+#define EFS_SPI_RDATA_3_I_MSK 0x00000000 -+#define EFS_SPI_RDATA_3_SFT 0 -+#define EFS_SPI_RDATA_3_HI 31 -+#define EFS_SPI_RDATA_3_SZ 32 -+#define EFS_SPI_RDATA_4_MSK 0xffffffff -+#define EFS_SPI_RDATA_4_I_MSK 0x00000000 -+#define EFS_SPI_RDATA_4_SFT 0 -+#define EFS_SPI_RDATA_4_HI 31 -+#define EFS_SPI_RDATA_4_SZ 32 -+#define EFS_SPI_RDATA_5_MSK 0xffffffff -+#define EFS_SPI_RDATA_5_I_MSK 0x00000000 -+#define EFS_SPI_RDATA_5_SFT 0 -+#define EFS_SPI_RDATA_5_HI 31 -+#define EFS_SPI_RDATA_5_SZ 32 -+#define EFS_SPI_RDATA_6_MSK 0xffffffff -+#define EFS_SPI_RDATA_6_I_MSK 0x00000000 -+#define EFS_SPI_RDATA_6_SFT 0 -+#define EFS_SPI_RDATA_6_HI 31 -+#define EFS_SPI_RDATA_6_SZ 32 -+#define EFS_SPI_RDATA_7_MSK 0xffffffff -+#define EFS_SPI_RDATA_7_I_MSK 0x00000000 -+#define EFS_SPI_RDATA_7_SFT 0 -+#define EFS_SPI_RDATA_7_HI 31 -+#define EFS_SPI_RDATA_7_SZ 32 -+#define GET_RK_MSK 0x00000001 -+#define GET_RK_I_MSK 0xfffffffe -+#define GET_RK_SFT 0 -+#define GET_RK_HI 0 -+#define GET_RK_SZ 1 -+#define FORCE_GET_RK_MSK 0x00000002 -+#define FORCE_GET_RK_I_MSK 0xfffffffd -+#define FORCE_GET_RK_SFT 1 -+#define FORCE_GET_RK_HI 1 -+#define FORCE_GET_RK_SZ 1 -+#define SMS4_DESCRY_EN_MSK 0x00000010 -+#define SMS4_DESCRY_EN_I_MSK 0xffffffef -+#define SMS4_DESCRY_EN_SFT 4 -+#define SMS4_DESCRY_EN_HI 4 -+#define SMS4_DESCRY_EN_SZ 1 -+#define DEC_DOUT_MSB_MSK 0x00000001 -+#define DEC_DOUT_MSB_I_MSK 0xfffffffe -+#define DEC_DOUT_MSB_SFT 0 -+#define DEC_DOUT_MSB_HI 0 -+#define DEC_DOUT_MSB_SZ 1 -+#define DEC_DIN_MSB_MSK 0x00000002 -+#define DEC_DIN_MSB_I_MSK 0xfffffffd -+#define DEC_DIN_MSB_SFT 1 -+#define DEC_DIN_MSB_HI 1 -+#define DEC_DIN_MSB_SZ 1 -+#define ENC_DOUT_MSB_MSK 0x00000004 -+#define ENC_DOUT_MSB_I_MSK 0xfffffffb -+#define ENC_DOUT_MSB_SFT 2 -+#define ENC_DOUT_MSB_HI 2 -+#define ENC_DOUT_MSB_SZ 1 -+#define ENC_DIN_MSB_MSK 0x00000008 -+#define ENC_DIN_MSB_I_MSK 0xfffffff7 -+#define ENC_DIN_MSB_SFT 3 -+#define ENC_DIN_MSB_HI 3 -+#define ENC_DIN_MSB_SZ 1 -+#define KEY_DIN_MSB_MSK 0x00000010 -+#define KEY_DIN_MSB_I_MSK 0xffffffef -+#define KEY_DIN_MSB_SFT 4 -+#define KEY_DIN_MSB_HI 4 -+#define KEY_DIN_MSB_SZ 1 -+#define SMS4_CBC_EN_MSK 0x00000001 -+#define SMS4_CBC_EN_I_MSK 0xfffffffe -+#define SMS4_CBC_EN_SFT 0 -+#define SMS4_CBC_EN_HI 0 -+#define SMS4_CBC_EN_SZ 1 -+#define SMS4_CFB_EN_MSK 0x00000002 -+#define SMS4_CFB_EN_I_MSK 0xfffffffd -+#define SMS4_CFB_EN_SFT 1 -+#define SMS4_CFB_EN_HI 1 -+#define SMS4_CFB_EN_SZ 1 -+#define SMS4_OFB_EN_MSK 0x00000004 -+#define SMS4_OFB_EN_I_MSK 0xfffffffb -+#define SMS4_OFB_EN_SFT 2 -+#define SMS4_OFB_EN_HI 2 -+#define SMS4_OFB_EN_SZ 1 -+#define SMS4_START_TRIG_MSK 0x00000001 -+#define SMS4_START_TRIG_I_MSK 0xfffffffe -+#define SMS4_START_TRIG_SFT 0 -+#define SMS4_START_TRIG_HI 0 -+#define SMS4_START_TRIG_SZ 1 -+#define SMS4_BUSY_MSK 0x00000001 -+#define SMS4_BUSY_I_MSK 0xfffffffe -+#define SMS4_BUSY_SFT 0 -+#define SMS4_BUSY_HI 0 -+#define SMS4_BUSY_SZ 1 -+#define SMS4_DONE_MSK 0x00000001 -+#define SMS4_DONE_I_MSK 0xfffffffe -+#define SMS4_DONE_SFT 0 -+#define SMS4_DONE_HI 0 -+#define SMS4_DONE_SZ 1 -+#define SMS4_DATAIN_0_MSK 0xffffffff -+#define SMS4_DATAIN_0_I_MSK 0x00000000 -+#define SMS4_DATAIN_0_SFT 0 -+#define SMS4_DATAIN_0_HI 31 -+#define SMS4_DATAIN_0_SZ 32 -+#define SMS4_DATAIN_1_MSK 0xffffffff -+#define SMS4_DATAIN_1_I_MSK 0x00000000 -+#define SMS4_DATAIN_1_SFT 0 -+#define SMS4_DATAIN_1_HI 31 -+#define SMS4_DATAIN_1_SZ 32 -+#define SMS4_DATAIN_2_MSK 0xffffffff -+#define SMS4_DATAIN_2_I_MSK 0x00000000 -+#define SMS4_DATAIN_2_SFT 0 -+#define SMS4_DATAIN_2_HI 31 -+#define SMS4_DATAIN_2_SZ 32 -+#define SMS4_DATAIN_3_MSK 0xffffffff -+#define SMS4_DATAIN_3_I_MSK 0x00000000 -+#define SMS4_DATAIN_3_SFT 0 -+#define SMS4_DATAIN_3_HI 31 -+#define SMS4_DATAIN_3_SZ 32 -+#define SMS4_DATAOUT_0_MSK 0xffffffff -+#define SMS4_DATAOUT_0_I_MSK 0x00000000 -+#define SMS4_DATAOUT_0_SFT 0 -+#define SMS4_DATAOUT_0_HI 31 -+#define SMS4_DATAOUT_0_SZ 32 -+#define SMS4_DATAOUT_1_MSK 0xffffffff -+#define SMS4_DATAOUT_1_I_MSK 0x00000000 -+#define SMS4_DATAOUT_1_SFT 0 -+#define SMS4_DATAOUT_1_HI 31 -+#define SMS4_DATAOUT_1_SZ 32 -+#define SMS4_DATAOUT_2_MSK 0xffffffff -+#define SMS4_DATAOUT_2_I_MSK 0x00000000 -+#define SMS4_DATAOUT_2_SFT 0 -+#define SMS4_DATAOUT_2_HI 31 -+#define SMS4_DATAOUT_2_SZ 32 -+#define SMS4_DATAOUT_3_MSK 0xffffffff -+#define SMS4_DATAOUT_3_I_MSK 0x00000000 -+#define SMS4_DATAOUT_3_SFT 0 -+#define SMS4_DATAOUT_3_HI 31 -+#define SMS4_DATAOUT_3_SZ 32 -+#define SMS4_KEY_0_MSK 0xffffffff -+#define SMS4_KEY_0_I_MSK 0x00000000 -+#define SMS4_KEY_0_SFT 0 -+#define SMS4_KEY_0_HI 31 -+#define SMS4_KEY_0_SZ 32 -+#define SMS4_KEY_1_MSK 0xffffffff -+#define SMS4_KEY_1_I_MSK 0x00000000 -+#define SMS4_KEY_1_SFT 0 -+#define SMS4_KEY_1_HI 31 -+#define SMS4_KEY_1_SZ 32 -+#define SMS4_KEY_2_MSK 0xffffffff -+#define SMS4_KEY_2_I_MSK 0x00000000 -+#define SMS4_KEY_2_SFT 0 -+#define SMS4_KEY_2_HI 31 -+#define SMS4_KEY_2_SZ 32 -+#define SMS4_KEY_3_MSK 0xffffffff -+#define SMS4_KEY_3_I_MSK 0x00000000 -+#define SMS4_KEY_3_SFT 0 -+#define SMS4_KEY_3_HI 31 -+#define SMS4_KEY_3_SZ 32 -+#define SMS4_MODE_IV0_MSK 0xffffffff -+#define SMS4_MODE_IV0_I_MSK 0x00000000 -+#define SMS4_MODE_IV0_SFT 0 -+#define SMS4_MODE_IV0_HI 31 -+#define SMS4_MODE_IV0_SZ 32 -+#define SMS4_MODE_IV1_MSK 0xffffffff -+#define SMS4_MODE_IV1_I_MSK 0x00000000 -+#define SMS4_MODE_IV1_SFT 0 -+#define SMS4_MODE_IV1_HI 31 -+#define SMS4_MODE_IV1_SZ 32 -+#define SMS4_MODE_IV2_MSK 0xffffffff -+#define SMS4_MODE_IV2_I_MSK 0x00000000 -+#define SMS4_MODE_IV2_SFT 0 -+#define SMS4_MODE_IV2_HI 31 -+#define SMS4_MODE_IV2_SZ 32 -+#define SMS4_MODE_IV3_MSK 0xffffffff -+#define SMS4_MODE_IV3_I_MSK 0x00000000 -+#define SMS4_MODE_IV3_SFT 0 -+#define SMS4_MODE_IV3_HI 31 -+#define SMS4_MODE_IV3_SZ 32 -+#define SMS4_OFB_ENC0_MSK 0xffffffff -+#define SMS4_OFB_ENC0_I_MSK 0x00000000 -+#define SMS4_OFB_ENC0_SFT 0 -+#define SMS4_OFB_ENC0_HI 31 -+#define SMS4_OFB_ENC0_SZ 32 -+#define SMS4_OFB_ENC1_MSK 0xffffffff -+#define SMS4_OFB_ENC1_I_MSK 0x00000000 -+#define SMS4_OFB_ENC1_SFT 0 -+#define SMS4_OFB_ENC1_HI 31 -+#define SMS4_OFB_ENC1_SZ 32 -+#define SMS4_OFB_ENC2_MSK 0xffffffff -+#define SMS4_OFB_ENC2_I_MSK 0x00000000 -+#define SMS4_OFB_ENC2_SFT 0 -+#define SMS4_OFB_ENC2_HI 31 -+#define SMS4_OFB_ENC2_SZ 32 -+#define SMS4_OFB_ENC3_MSK 0xffffffff -+#define SMS4_OFB_ENC3_I_MSK 0x00000000 -+#define SMS4_OFB_ENC3_SFT 0 -+#define SMS4_OFB_ENC3_HI 31 -+#define SMS4_OFB_ENC3_SZ 32 -+#define MRX_MCAST_TB0_31_0_MSK 0xffffffff -+#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000 -+#define MRX_MCAST_TB0_31_0_SFT 0 -+#define MRX_MCAST_TB0_31_0_HI 31 -+#define MRX_MCAST_TB0_31_0_SZ 32 -+#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff -+#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000 -+#define MRX_MCAST_TB0_47_32_SFT 0 -+#define MRX_MCAST_TB0_47_32_HI 15 -+#define MRX_MCAST_TB0_47_32_SZ 16 -+#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff -+#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000 -+#define MRX_MCAST_MASK0_31_0_SFT 0 -+#define MRX_MCAST_MASK0_31_0_HI 31 -+#define MRX_MCAST_MASK0_31_0_SZ 32 -+#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff -+#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000 -+#define MRX_MCAST_MASK0_47_32_SFT 0 -+#define MRX_MCAST_MASK0_47_32_HI 15 -+#define MRX_MCAST_MASK0_47_32_SZ 16 -+#define MRX_MCAST_CTRL_0_MSK 0x00000003 -+#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc -+#define MRX_MCAST_CTRL_0_SFT 0 -+#define MRX_MCAST_CTRL_0_HI 1 -+#define MRX_MCAST_CTRL_0_SZ 2 -+#define MRX_MCAST_TB1_31_0_MSK 0xffffffff -+#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000 -+#define MRX_MCAST_TB1_31_0_SFT 0 -+#define MRX_MCAST_TB1_31_0_HI 31 -+#define MRX_MCAST_TB1_31_0_SZ 32 -+#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff -+#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000 -+#define MRX_MCAST_TB1_47_32_SFT 0 -+#define MRX_MCAST_TB1_47_32_HI 15 -+#define MRX_MCAST_TB1_47_32_SZ 16 -+#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff -+#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000 -+#define MRX_MCAST_MASK1_31_0_SFT 0 -+#define MRX_MCAST_MASK1_31_0_HI 31 -+#define MRX_MCAST_MASK1_31_0_SZ 32 -+#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff -+#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000 -+#define MRX_MCAST_MASK1_47_32_SFT 0 -+#define MRX_MCAST_MASK1_47_32_HI 15 -+#define MRX_MCAST_MASK1_47_32_SZ 16 -+#define MRX_MCAST_CTRL_1_MSK 0x00000003 -+#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc -+#define MRX_MCAST_CTRL_1_SFT 0 -+#define MRX_MCAST_CTRL_1_HI 1 -+#define MRX_MCAST_CTRL_1_SZ 2 -+#define MRX_MCAST_TB2_31_0_MSK 0xffffffff -+#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000 -+#define MRX_MCAST_TB2_31_0_SFT 0 -+#define MRX_MCAST_TB2_31_0_HI 31 -+#define MRX_MCAST_TB2_31_0_SZ 32 -+#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff -+#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000 -+#define MRX_MCAST_TB2_47_32_SFT 0 -+#define MRX_MCAST_TB2_47_32_HI 15 -+#define MRX_MCAST_TB2_47_32_SZ 16 -+#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff -+#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000 -+#define MRX_MCAST_MASK2_31_0_SFT 0 -+#define MRX_MCAST_MASK2_31_0_HI 31 -+#define MRX_MCAST_MASK2_31_0_SZ 32 -+#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff -+#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000 -+#define MRX_MCAST_MASK2_47_32_SFT 0 -+#define MRX_MCAST_MASK2_47_32_HI 15 -+#define MRX_MCAST_MASK2_47_32_SZ 16 -+#define MRX_MCAST_CTRL_2_MSK 0x00000003 -+#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc -+#define MRX_MCAST_CTRL_2_SFT 0 -+#define MRX_MCAST_CTRL_2_HI 1 -+#define MRX_MCAST_CTRL_2_SZ 2 -+#define MRX_MCAST_TB3_31_0_MSK 0xffffffff -+#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000 -+#define MRX_MCAST_TB3_31_0_SFT 0 -+#define MRX_MCAST_TB3_31_0_HI 31 -+#define MRX_MCAST_TB3_31_0_SZ 32 -+#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff -+#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000 -+#define MRX_MCAST_TB3_47_32_SFT 0 -+#define MRX_MCAST_TB3_47_32_HI 15 -+#define MRX_MCAST_TB3_47_32_SZ 16 -+#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff -+#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000 -+#define MRX_MCAST_MASK3_31_0_SFT 0 -+#define MRX_MCAST_MASK3_31_0_HI 31 -+#define MRX_MCAST_MASK3_31_0_SZ 32 -+#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff -+#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000 -+#define MRX_MCAST_MASK3_47_32_SFT 0 -+#define MRX_MCAST_MASK3_47_32_HI 15 -+#define MRX_MCAST_MASK3_47_32_SZ 16 -+#define MRX_MCAST_CTRL_3_MSK 0x00000003 -+#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc -+#define MRX_MCAST_CTRL_3_SFT 0 -+#define MRX_MCAST_CTRL_3_HI 1 -+#define MRX_MCAST_CTRL_3_SZ 2 -+#define MRX_PHY_INFO_MSK 0xffffffff -+#define MRX_PHY_INFO_I_MSK 0x00000000 -+#define MRX_PHY_INFO_SFT 0 -+#define MRX_PHY_INFO_HI 31 -+#define MRX_PHY_INFO_SZ 32 -+#define DBG_BA_TYPE_MSK 0x0000003f -+#define DBG_BA_TYPE_I_MSK 0xffffffc0 -+#define DBG_BA_TYPE_SFT 0 -+#define DBG_BA_TYPE_HI 5 -+#define DBG_BA_TYPE_SZ 6 -+#define DBG_BA_SEQ_MSK 0x000fff00 -+#define DBG_BA_SEQ_I_MSK 0xfff000ff -+#define DBG_BA_SEQ_SFT 8 -+#define DBG_BA_SEQ_HI 19 -+#define DBG_BA_SEQ_SZ 12 -+#define MRX_FLT_TB0_MSK 0x00007fff -+#define MRX_FLT_TB0_I_MSK 0xffff8000 -+#define MRX_FLT_TB0_SFT 0 -+#define MRX_FLT_TB0_HI 14 -+#define MRX_FLT_TB0_SZ 15 -+#define MRX_FLT_TB1_MSK 0x00007fff -+#define MRX_FLT_TB1_I_MSK 0xffff8000 -+#define MRX_FLT_TB1_SFT 0 -+#define MRX_FLT_TB1_HI 14 -+#define MRX_FLT_TB1_SZ 15 -+#define MRX_FLT_TB2_MSK 0x00007fff -+#define MRX_FLT_TB2_I_MSK 0xffff8000 -+#define MRX_FLT_TB2_SFT 0 -+#define MRX_FLT_TB2_HI 14 -+#define MRX_FLT_TB2_SZ 15 -+#define MRX_FLT_TB3_MSK 0x00007fff -+#define MRX_FLT_TB3_I_MSK 0xffff8000 -+#define MRX_FLT_TB3_SFT 0 -+#define MRX_FLT_TB3_HI 14 -+#define MRX_FLT_TB3_SZ 15 -+#define MRX_FLT_TB4_MSK 0x00007fff -+#define MRX_FLT_TB4_I_MSK 0xffff8000 -+#define MRX_FLT_TB4_SFT 0 -+#define MRX_FLT_TB4_HI 14 -+#define MRX_FLT_TB4_SZ 15 -+#define MRX_FLT_TB5_MSK 0x00007fff -+#define MRX_FLT_TB5_I_MSK 0xffff8000 -+#define MRX_FLT_TB5_SFT 0 -+#define MRX_FLT_TB5_HI 14 -+#define MRX_FLT_TB5_SZ 15 -+#define MRX_FLT_TB6_MSK 0x00007fff -+#define MRX_FLT_TB6_I_MSK 0xffff8000 -+#define MRX_FLT_TB6_SFT 0 -+#define MRX_FLT_TB6_HI 14 -+#define MRX_FLT_TB6_SZ 15 -+#define MRX_FLT_TB7_MSK 0x00007fff -+#define MRX_FLT_TB7_I_MSK 0xffff8000 -+#define MRX_FLT_TB7_SFT 0 -+#define MRX_FLT_TB7_HI 14 -+#define MRX_FLT_TB7_SZ 15 -+#define MRX_FLT_TB8_MSK 0x00007fff -+#define MRX_FLT_TB8_I_MSK 0xffff8000 -+#define MRX_FLT_TB8_SFT 0 -+#define MRX_FLT_TB8_HI 14 -+#define MRX_FLT_TB8_SZ 15 -+#define MRX_FLT_TB9_MSK 0x00007fff -+#define MRX_FLT_TB9_I_MSK 0xffff8000 -+#define MRX_FLT_TB9_SFT 0 -+#define MRX_FLT_TB9_HI 14 -+#define MRX_FLT_TB9_SZ 15 -+#define MRX_FLT_TB10_MSK 0x00007fff -+#define MRX_FLT_TB10_I_MSK 0xffff8000 -+#define MRX_FLT_TB10_SFT 0 -+#define MRX_FLT_TB10_HI 14 -+#define MRX_FLT_TB10_SZ 15 -+#define MRX_FLT_TB11_MSK 0x00007fff -+#define MRX_FLT_TB11_I_MSK 0xffff8000 -+#define MRX_FLT_TB11_SFT 0 -+#define MRX_FLT_TB11_HI 14 -+#define MRX_FLT_TB11_SZ 15 -+#define MRX_FLT_TB12_MSK 0x00007fff -+#define MRX_FLT_TB12_I_MSK 0xffff8000 -+#define MRX_FLT_TB12_SFT 0 -+#define MRX_FLT_TB12_HI 14 -+#define MRX_FLT_TB12_SZ 15 -+#define MRX_FLT_TB13_MSK 0x00007fff -+#define MRX_FLT_TB13_I_MSK 0xffff8000 -+#define MRX_FLT_TB13_SFT 0 -+#define MRX_FLT_TB13_HI 14 -+#define MRX_FLT_TB13_SZ 15 -+#define MRX_FLT_TB14_MSK 0x00007fff -+#define MRX_FLT_TB14_I_MSK 0xffff8000 -+#define MRX_FLT_TB14_SFT 0 -+#define MRX_FLT_TB14_HI 14 -+#define MRX_FLT_TB14_SZ 15 -+#define MRX_FLT_TB15_MSK 0x00007fff -+#define MRX_FLT_TB15_I_MSK 0xffff8000 -+#define MRX_FLT_TB15_SFT 0 -+#define MRX_FLT_TB15_HI 14 -+#define MRX_FLT_TB15_SZ 15 -+#define MRX_FLT_EN0_MSK 0x0000ffff -+#define MRX_FLT_EN0_I_MSK 0xffff0000 -+#define MRX_FLT_EN0_SFT 0 -+#define MRX_FLT_EN0_HI 15 -+#define MRX_FLT_EN0_SZ 16 -+#define MRX_FLT_EN1_MSK 0x0000ffff -+#define MRX_FLT_EN1_I_MSK 0xffff0000 -+#define MRX_FLT_EN1_SFT 0 -+#define MRX_FLT_EN1_HI 15 -+#define MRX_FLT_EN1_SZ 16 -+#define MRX_FLT_EN2_MSK 0x0000ffff -+#define MRX_FLT_EN2_I_MSK 0xffff0000 -+#define MRX_FLT_EN2_SFT 0 -+#define MRX_FLT_EN2_HI 15 -+#define MRX_FLT_EN2_SZ 16 -+#define MRX_FLT_EN3_MSK 0x0000ffff -+#define MRX_FLT_EN3_I_MSK 0xffff0000 -+#define MRX_FLT_EN3_SFT 0 -+#define MRX_FLT_EN3_HI 15 -+#define MRX_FLT_EN3_SZ 16 -+#define MRX_FLT_EN4_MSK 0x0000ffff -+#define MRX_FLT_EN4_I_MSK 0xffff0000 -+#define MRX_FLT_EN4_SFT 0 -+#define MRX_FLT_EN4_HI 15 -+#define MRX_FLT_EN4_SZ 16 -+#define MRX_FLT_EN5_MSK 0x0000ffff -+#define MRX_FLT_EN5_I_MSK 0xffff0000 -+#define MRX_FLT_EN5_SFT 0 -+#define MRX_FLT_EN5_HI 15 -+#define MRX_FLT_EN5_SZ 16 -+#define MRX_FLT_EN6_MSK 0x0000ffff -+#define MRX_FLT_EN6_I_MSK 0xffff0000 -+#define MRX_FLT_EN6_SFT 0 -+#define MRX_FLT_EN6_HI 15 -+#define MRX_FLT_EN6_SZ 16 -+#define MRX_FLT_EN7_MSK 0x0000ffff -+#define MRX_FLT_EN7_I_MSK 0xffff0000 -+#define MRX_FLT_EN7_SFT 0 -+#define MRX_FLT_EN7_HI 15 -+#define MRX_FLT_EN7_SZ 16 -+#define MRX_FLT_EN8_MSK 0x0000ffff -+#define MRX_FLT_EN8_I_MSK 0xffff0000 -+#define MRX_FLT_EN8_SFT 0 -+#define MRX_FLT_EN8_HI 15 -+#define MRX_FLT_EN8_SZ 16 -+#define MRX_LEN_FLT_MSK 0x0000ffff -+#define MRX_LEN_FLT_I_MSK 0xffff0000 -+#define MRX_LEN_FLT_SFT 0 -+#define MRX_LEN_FLT_HI 15 -+#define MRX_LEN_FLT_SZ 16 -+#define RX_FLOW_DATA_MSK 0xffffffff -+#define RX_FLOW_DATA_I_MSK 0x00000000 -+#define RX_FLOW_DATA_SFT 0 -+#define RX_FLOW_DATA_HI 31 -+#define RX_FLOW_DATA_SZ 32 -+#define RX_FLOW_MNG_MSK 0x0000ffff -+#define RX_FLOW_MNG_I_MSK 0xffff0000 -+#define RX_FLOW_MNG_SFT 0 -+#define RX_FLOW_MNG_HI 15 -+#define RX_FLOW_MNG_SZ 16 -+#define RX_FLOW_CTRL_MSK 0x0000ffff -+#define RX_FLOW_CTRL_I_MSK 0xffff0000 -+#define RX_FLOW_CTRL_SFT 0 -+#define RX_FLOW_CTRL_HI 15 -+#define RX_FLOW_CTRL_SZ 16 -+#define MRX_STP_EN_MSK 0x00000001 -+#define MRX_STP_EN_I_MSK 0xfffffffe -+#define MRX_STP_EN_SFT 0 -+#define MRX_STP_EN_HI 0 -+#define MRX_STP_EN_SZ 1 -+#define MRX_STP_OFST_MSK 0x0000ff00 -+#define MRX_STP_OFST_I_MSK 0xffff00ff -+#define MRX_STP_OFST_SFT 8 -+#define MRX_STP_OFST_HI 15 -+#define MRX_STP_OFST_SZ 8 -+#define DBG_FF_FULL_MSK 0x0000ffff -+#define DBG_FF_FULL_I_MSK 0xffff0000 -+#define DBG_FF_FULL_SFT 0 -+#define DBG_FF_FULL_HI 15 -+#define DBG_FF_FULL_SZ 16 -+#define DBG_FF_FULL_CLR_MSK 0x80000000 -+#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff -+#define DBG_FF_FULL_CLR_SFT 31 -+#define DBG_FF_FULL_CLR_HI 31 -+#define DBG_FF_FULL_CLR_SZ 1 -+#define DBG_WFF_FULL_MSK 0x0000ffff -+#define DBG_WFF_FULL_I_MSK 0xffff0000 -+#define DBG_WFF_FULL_SFT 0 -+#define DBG_WFF_FULL_HI 15 -+#define DBG_WFF_FULL_SZ 16 -+#define DBG_WFF_FULL_CLR_MSK 0x80000000 -+#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff -+#define DBG_WFF_FULL_CLR_SFT 31 -+#define DBG_WFF_FULL_CLR_HI 31 -+#define DBG_WFF_FULL_CLR_SZ 1 -+#define DBG_MB_FULL_MSK 0x0000ffff -+#define DBG_MB_FULL_I_MSK 0xffff0000 -+#define DBG_MB_FULL_SFT 0 -+#define DBG_MB_FULL_HI 15 -+#define DBG_MB_FULL_SZ 16 -+#define DBG_MB_FULL_CLR_MSK 0x80000000 -+#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff -+#define DBG_MB_FULL_CLR_SFT 31 -+#define DBG_MB_FULL_CLR_HI 31 -+#define DBG_MB_FULL_CLR_SZ 1 -+#define BA_CTRL_MSK 0x00000003 -+#define BA_CTRL_I_MSK 0xfffffffc -+#define BA_CTRL_SFT 0 -+#define BA_CTRL_HI 1 -+#define BA_CTRL_SZ 2 -+#define BA_DBG_EN_MSK 0x00000004 -+#define BA_DBG_EN_I_MSK 0xfffffffb -+#define BA_DBG_EN_SFT 2 -+#define BA_DBG_EN_HI 2 -+#define BA_DBG_EN_SZ 1 -+#define BA_AGRE_EN_MSK 0x00000008 -+#define BA_AGRE_EN_I_MSK 0xfffffff7 -+#define BA_AGRE_EN_SFT 3 -+#define BA_AGRE_EN_HI 3 -+#define BA_AGRE_EN_SZ 1 -+#define BA_TA_31_0_MSK 0xffffffff -+#define BA_TA_31_0_I_MSK 0x00000000 -+#define BA_TA_31_0_SFT 0 -+#define BA_TA_31_0_HI 31 -+#define BA_TA_31_0_SZ 32 -+#define BA_TA_47_32_MSK 0x0000ffff -+#define BA_TA_47_32_I_MSK 0xffff0000 -+#define BA_TA_47_32_SFT 0 -+#define BA_TA_47_32_HI 15 -+#define BA_TA_47_32_SZ 16 -+#define BA_TID_MSK 0x0000000f -+#define BA_TID_I_MSK 0xfffffff0 -+#define BA_TID_SFT 0 -+#define BA_TID_HI 3 -+#define BA_TID_SZ 4 -+#define BA_ST_SEQ_MSK 0x00000fff -+#define BA_ST_SEQ_I_MSK 0xfffff000 -+#define BA_ST_SEQ_SFT 0 -+#define BA_ST_SEQ_HI 11 -+#define BA_ST_SEQ_SZ 12 -+#define BA_SB0_MSK 0xffffffff -+#define BA_SB0_I_MSK 0x00000000 -+#define BA_SB0_SFT 0 -+#define BA_SB0_HI 31 -+#define BA_SB0_SZ 32 -+#define BA_SB1_MSK 0xffffffff -+#define BA_SB1_I_MSK 0x00000000 -+#define BA_SB1_SFT 0 -+#define BA_SB1_HI 31 -+#define BA_SB1_SZ 32 -+#define MRX_WD_MSK 0x0001ffff -+#define MRX_WD_I_MSK 0xfffe0000 -+#define MRX_WD_SFT 0 -+#define MRX_WD_HI 16 -+#define MRX_WD_SZ 17 -+#define ACK_GEN_EN_MSK 0x00000001 -+#define ACK_GEN_EN_I_MSK 0xfffffffe -+#define ACK_GEN_EN_SFT 0 -+#define ACK_GEN_EN_HI 0 -+#define ACK_GEN_EN_SZ 1 -+#define BA_GEN_EN_MSK 0x00000002 -+#define BA_GEN_EN_I_MSK 0xfffffffd -+#define BA_GEN_EN_SFT 1 -+#define BA_GEN_EN_HI 1 -+#define BA_GEN_EN_SZ 1 -+#define ACK_GEN_DUR_MSK 0x0000ffff -+#define ACK_GEN_DUR_I_MSK 0xffff0000 -+#define ACK_GEN_DUR_SFT 0 -+#define ACK_GEN_DUR_HI 15 -+#define ACK_GEN_DUR_SZ 16 -+#define ACK_GEN_INFO_MSK 0x003f0000 -+#define ACK_GEN_INFO_I_MSK 0xffc0ffff -+#define ACK_GEN_INFO_SFT 16 -+#define ACK_GEN_INFO_HI 21 -+#define ACK_GEN_INFO_SZ 6 -+#define ACK_GEN_RA_31_0_MSK 0xffffffff -+#define ACK_GEN_RA_31_0_I_MSK 0x00000000 -+#define ACK_GEN_RA_31_0_SFT 0 -+#define ACK_GEN_RA_31_0_HI 31 -+#define ACK_GEN_RA_31_0_SZ 32 -+#define ACK_GEN_RA_47_32_MSK 0x0000ffff -+#define ACK_GEN_RA_47_32_I_MSK 0xffff0000 -+#define ACK_GEN_RA_47_32_SFT 0 -+#define ACK_GEN_RA_47_32_HI 15 -+#define ACK_GEN_RA_47_32_SZ 16 -+#define MIB_LEN_FAIL_MSK 0x0000ffff -+#define MIB_LEN_FAIL_I_MSK 0xffff0000 -+#define MIB_LEN_FAIL_SFT 0 -+#define MIB_LEN_FAIL_HI 15 -+#define MIB_LEN_FAIL_SZ 16 -+#define TRAP_HW_ID_MSK 0x0000000f -+#define TRAP_HW_ID_I_MSK 0xfffffff0 -+#define TRAP_HW_ID_SFT 0 -+#define TRAP_HW_ID_HI 3 -+#define TRAP_HW_ID_SZ 4 -+#define ID_IN_USE_MSK 0x000000ff -+#define ID_IN_USE_I_MSK 0xffffff00 -+#define ID_IN_USE_SFT 0 -+#define ID_IN_USE_HI 7 -+#define ID_IN_USE_SZ 8 -+#define MRX_ERR_MSK 0xffffffff -+#define MRX_ERR_I_MSK 0x00000000 -+#define MRX_ERR_SFT 0 -+#define MRX_ERR_HI 31 -+#define MRX_ERR_SZ 32 -+#define W0_T0_SEQ_MSK 0x0000ffff -+#define W0_T0_SEQ_I_MSK 0xffff0000 -+#define W0_T0_SEQ_SFT 0 -+#define W0_T0_SEQ_HI 15 -+#define W0_T0_SEQ_SZ 16 -+#define W0_T1_SEQ_MSK 0x0000ffff -+#define W0_T1_SEQ_I_MSK 0xffff0000 -+#define W0_T1_SEQ_SFT 0 -+#define W0_T1_SEQ_HI 15 -+#define W0_T1_SEQ_SZ 16 -+#define W0_T2_SEQ_MSK 0x0000ffff -+#define W0_T2_SEQ_I_MSK 0xffff0000 -+#define W0_T2_SEQ_SFT 0 -+#define W0_T2_SEQ_HI 15 -+#define W0_T2_SEQ_SZ 16 -+#define W0_T3_SEQ_MSK 0x0000ffff -+#define W0_T3_SEQ_I_MSK 0xffff0000 -+#define W0_T3_SEQ_SFT 0 -+#define W0_T3_SEQ_HI 15 -+#define W0_T3_SEQ_SZ 16 -+#define W0_T4_SEQ_MSK 0x0000ffff -+#define W0_T4_SEQ_I_MSK 0xffff0000 -+#define W0_T4_SEQ_SFT 0 -+#define W0_T4_SEQ_HI 15 -+#define W0_T4_SEQ_SZ 16 -+#define W0_T5_SEQ_MSK 0x0000ffff -+#define W0_T5_SEQ_I_MSK 0xffff0000 -+#define W0_T5_SEQ_SFT 0 -+#define W0_T5_SEQ_HI 15 -+#define W0_T5_SEQ_SZ 16 -+#define W0_T6_SEQ_MSK 0x0000ffff -+#define W0_T6_SEQ_I_MSK 0xffff0000 -+#define W0_T6_SEQ_SFT 0 -+#define W0_T6_SEQ_HI 15 -+#define W0_T6_SEQ_SZ 16 -+#define W0_T7_SEQ_MSK 0x0000ffff -+#define W0_T7_SEQ_I_MSK 0xffff0000 -+#define W0_T7_SEQ_SFT 0 -+#define W0_T7_SEQ_HI 15 -+#define W0_T7_SEQ_SZ 16 -+#define W1_T0_SEQ_MSK 0x0000ffff -+#define W1_T0_SEQ_I_MSK 0xffff0000 -+#define W1_T0_SEQ_SFT 0 -+#define W1_T0_SEQ_HI 15 -+#define W1_T0_SEQ_SZ 16 -+#define W1_T1_SEQ_MSK 0x0000ffff -+#define W1_T1_SEQ_I_MSK 0xffff0000 -+#define W1_T1_SEQ_SFT 0 -+#define W1_T1_SEQ_HI 15 -+#define W1_T1_SEQ_SZ 16 -+#define W1_T2_SEQ_MSK 0x0000ffff -+#define W1_T2_SEQ_I_MSK 0xffff0000 -+#define W1_T2_SEQ_SFT 0 -+#define W1_T2_SEQ_HI 15 -+#define W1_T2_SEQ_SZ 16 -+#define W1_T3_SEQ_MSK 0x0000ffff -+#define W1_T3_SEQ_I_MSK 0xffff0000 -+#define W1_T3_SEQ_SFT 0 -+#define W1_T3_SEQ_HI 15 -+#define W1_T3_SEQ_SZ 16 -+#define W1_T4_SEQ_MSK 0x0000ffff -+#define W1_T4_SEQ_I_MSK 0xffff0000 -+#define W1_T4_SEQ_SFT 0 -+#define W1_T4_SEQ_HI 15 -+#define W1_T4_SEQ_SZ 16 -+#define W1_T5_SEQ_MSK 0x0000ffff -+#define W1_T5_SEQ_I_MSK 0xffff0000 -+#define W1_T5_SEQ_SFT 0 -+#define W1_T5_SEQ_HI 15 -+#define W1_T5_SEQ_SZ 16 -+#define W1_T6_SEQ_MSK 0x0000ffff -+#define W1_T6_SEQ_I_MSK 0xffff0000 -+#define W1_T6_SEQ_SFT 0 -+#define W1_T6_SEQ_HI 15 -+#define W1_T6_SEQ_SZ 16 -+#define W1_T7_SEQ_MSK 0x0000ffff -+#define W1_T7_SEQ_I_MSK 0xffff0000 -+#define W1_T7_SEQ_SFT 0 -+#define W1_T7_SEQ_HI 15 -+#define W1_T7_SEQ_SZ 16 -+#define ADDR1A_SEL_MSK 0x00000003 -+#define ADDR1A_SEL_I_MSK 0xfffffffc -+#define ADDR1A_SEL_SFT 0 -+#define ADDR1A_SEL_HI 1 -+#define ADDR1A_SEL_SZ 2 -+#define ADDR2A_SEL_MSK 0x0000000c -+#define ADDR2A_SEL_I_MSK 0xfffffff3 -+#define ADDR2A_SEL_SFT 2 -+#define ADDR2A_SEL_HI 3 -+#define ADDR2A_SEL_SZ 2 -+#define ADDR3A_SEL_MSK 0x00000030 -+#define ADDR3A_SEL_I_MSK 0xffffffcf -+#define ADDR3A_SEL_SFT 4 -+#define ADDR3A_SEL_HI 5 -+#define ADDR3A_SEL_SZ 2 -+#define ADDR1B_SEL_MSK 0x000000c0 -+#define ADDR1B_SEL_I_MSK 0xffffff3f -+#define ADDR1B_SEL_SFT 6 -+#define ADDR1B_SEL_HI 7 -+#define ADDR1B_SEL_SZ 2 -+#define ADDR2B_SEL_MSK 0x00000300 -+#define ADDR2B_SEL_I_MSK 0xfffffcff -+#define ADDR2B_SEL_SFT 8 -+#define ADDR2B_SEL_HI 9 -+#define ADDR2B_SEL_SZ 2 -+#define ADDR3B_SEL_MSK 0x00000c00 -+#define ADDR3B_SEL_I_MSK 0xfffff3ff -+#define ADDR3B_SEL_SFT 10 -+#define ADDR3B_SEL_HI 11 -+#define ADDR3B_SEL_SZ 2 -+#define ADDR3C_SEL_MSK 0x00003000 -+#define ADDR3C_SEL_I_MSK 0xffffcfff -+#define ADDR3C_SEL_SFT 12 -+#define ADDR3C_SEL_HI 13 -+#define ADDR3C_SEL_SZ 2 -+#define FRM_CTRL_MSK 0x0000003f -+#define FRM_CTRL_I_MSK 0xffffffc0 -+#define FRM_CTRL_SFT 0 -+#define FRM_CTRL_HI 5 -+#define FRM_CTRL_SZ 6 -+#define CSR_PHY_INFO_MSK 0x00007fff -+#define CSR_PHY_INFO_I_MSK 0xffff8000 -+#define CSR_PHY_INFO_SFT 0 -+#define CSR_PHY_INFO_HI 14 -+#define CSR_PHY_INFO_SZ 15 -+#define AMPDU_SIG_MSK 0x000000ff -+#define AMPDU_SIG_I_MSK 0xffffff00 -+#define AMPDU_SIG_SFT 0 -+#define AMPDU_SIG_HI 7 -+#define AMPDU_SIG_SZ 8 -+#define MIB_AMPDU_MSK 0xffffffff -+#define MIB_AMPDU_I_MSK 0x00000000 -+#define MIB_AMPDU_SFT 0 -+#define MIB_AMPDU_HI 31 -+#define MIB_AMPDU_SZ 32 -+#define LEN_FLT_MSK 0x0000ffff -+#define LEN_FLT_I_MSK 0xffff0000 -+#define LEN_FLT_SFT 0 -+#define LEN_FLT_HI 15 -+#define LEN_FLT_SZ 16 -+#define MIB_DELIMITER_MSK 0x0000ffff -+#define MIB_DELIMITER_I_MSK 0xffff0000 -+#define MIB_DELIMITER_SFT 0 -+#define MIB_DELIMITER_HI 15 -+#define MIB_DELIMITER_SZ 16 -+#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000 -+#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff -+#define MTX_INT_Q0_Q_EMPTY_SFT 16 -+#define MTX_INT_Q0_Q_EMPTY_HI 16 -+#define MTX_INT_Q0_Q_EMPTY_SZ 1 -+#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000 -+#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff -+#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17 -+#define MTX_INT_Q0_TXOP_RUNOUT_HI 17 -+#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1 -+#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000 -+#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff -+#define MTX_INT_Q1_Q_EMPTY_SFT 18 -+#define MTX_INT_Q1_Q_EMPTY_HI 18 -+#define MTX_INT_Q1_Q_EMPTY_SZ 1 -+#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000 -+#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff -+#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19 -+#define MTX_INT_Q1_TXOP_RUNOUT_HI 19 -+#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1 -+#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000 -+#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff -+#define MTX_INT_Q2_Q_EMPTY_SFT 20 -+#define MTX_INT_Q2_Q_EMPTY_HI 20 -+#define MTX_INT_Q2_Q_EMPTY_SZ 1 -+#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000 -+#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff -+#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21 -+#define MTX_INT_Q2_TXOP_RUNOUT_HI 21 -+#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1 -+#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000 -+#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff -+#define MTX_INT_Q3_Q_EMPTY_SFT 22 -+#define MTX_INT_Q3_Q_EMPTY_HI 22 -+#define MTX_INT_Q3_Q_EMPTY_SZ 1 -+#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000 -+#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff -+#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23 -+#define MTX_INT_Q3_TXOP_RUNOUT_HI 23 -+#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1 -+#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000 -+#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff -+#define MTX_INT_Q4_Q_EMPTY_SFT 24 -+#define MTX_INT_Q4_Q_EMPTY_HI 24 -+#define MTX_INT_Q4_Q_EMPTY_SZ 1 -+#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000 -+#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff -+#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25 -+#define MTX_INT_Q4_TXOP_RUNOUT_HI 25 -+#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1 -+#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000 -+#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff -+#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16 -+#define MTX_EN_INT_Q0_Q_EMPTY_HI 16 -+#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1 -+#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000 -+#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff -+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17 -+#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17 -+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1 -+#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000 -+#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff -+#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18 -+#define MTX_EN_INT_Q1_Q_EMPTY_HI 18 -+#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1 -+#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000 -+#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff -+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19 -+#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19 -+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1 -+#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000 -+#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff -+#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20 -+#define MTX_EN_INT_Q2_Q_EMPTY_HI 20 -+#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1 -+#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000 -+#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff -+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21 -+#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21 -+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1 -+#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000 -+#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff -+#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22 -+#define MTX_EN_INT_Q3_Q_EMPTY_HI 22 -+#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1 -+#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000 -+#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff -+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23 -+#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23 -+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1 -+#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000 -+#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff -+#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24 -+#define MTX_EN_INT_Q4_Q_EMPTY_HI 24 -+#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1 -+#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000 -+#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff -+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25 -+#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25 -+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1 -+#define MTX_MTX2PHY_SLOW_MSK 0x00000001 -+#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe -+#define MTX_MTX2PHY_SLOW_SFT 0 -+#define MTX_MTX2PHY_SLOW_HI 0 -+#define MTX_MTX2PHY_SLOW_SZ 1 -+#define MTX_M2M_SLOW_PRD_MSK 0x0000000e -+#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1 -+#define MTX_M2M_SLOW_PRD_SFT 1 -+#define MTX_M2M_SLOW_PRD_HI 3 -+#define MTX_M2M_SLOW_PRD_SZ 3 -+#define MTX_AMPDU_CRC_AUTO_MSK 0x00000020 -+#define MTX_AMPDU_CRC_AUTO_I_MSK 0xffffffdf -+#define MTX_AMPDU_CRC_AUTO_SFT 5 -+#define MTX_AMPDU_CRC_AUTO_HI 5 -+#define MTX_AMPDU_CRC_AUTO_SZ 1 -+#define MTX_FAST_RSP_MODE_MSK 0x00000040 -+#define MTX_FAST_RSP_MODE_I_MSK 0xffffffbf -+#define MTX_FAST_RSP_MODE_SFT 6 -+#define MTX_FAST_RSP_MODE_HI 6 -+#define MTX_FAST_RSP_MODE_SZ 1 -+#define MTX_RAW_DATA_MODE_MSK 0x00000080 -+#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f -+#define MTX_RAW_DATA_MODE_SFT 7 -+#define MTX_RAW_DATA_MODE_HI 7 -+#define MTX_RAW_DATA_MODE_SZ 1 -+#define MTX_ACK_DUR0_MSK 0x00000100 -+#define MTX_ACK_DUR0_I_MSK 0xfffffeff -+#define MTX_ACK_DUR0_SFT 8 -+#define MTX_ACK_DUR0_HI 8 -+#define MTX_ACK_DUR0_SZ 1 -+#define MTX_TSF_AUTO_BCN_MSK 0x00000400 -+#define MTX_TSF_AUTO_BCN_I_MSK 0xfffffbff -+#define MTX_TSF_AUTO_BCN_SFT 10 -+#define MTX_TSF_AUTO_BCN_HI 10 -+#define MTX_TSF_AUTO_BCN_SZ 1 -+#define MTX_TSF_AUTO_MISC_MSK 0x00000800 -+#define MTX_TSF_AUTO_MISC_I_MSK 0xfffff7ff -+#define MTX_TSF_AUTO_MISC_SFT 11 -+#define MTX_TSF_AUTO_MISC_HI 11 -+#define MTX_TSF_AUTO_MISC_SZ 1 -+#define MTX_FORCE_CS_IDLE_MSK 0x00001000 -+#define MTX_FORCE_CS_IDLE_I_MSK 0xffffefff -+#define MTX_FORCE_CS_IDLE_SFT 12 -+#define MTX_FORCE_CS_IDLE_HI 12 -+#define MTX_FORCE_CS_IDLE_SZ 1 -+#define MTX_FORCE_BKF_RXEN0_MSK 0x00002000 -+#define MTX_FORCE_BKF_RXEN0_I_MSK 0xffffdfff -+#define MTX_FORCE_BKF_RXEN0_SFT 13 -+#define MTX_FORCE_BKF_RXEN0_HI 13 -+#define MTX_FORCE_BKF_RXEN0_SZ 1 -+#define MTX_FORCE_DMA_RXEN0_MSK 0x00004000 -+#define MTX_FORCE_DMA_RXEN0_I_MSK 0xffffbfff -+#define MTX_FORCE_DMA_RXEN0_SFT 14 -+#define MTX_FORCE_DMA_RXEN0_HI 14 -+#define MTX_FORCE_DMA_RXEN0_SZ 1 -+#define MTX_FORCE_RXEN0_MSK 0x00008000 -+#define MTX_FORCE_RXEN0_I_MSK 0xffff7fff -+#define MTX_FORCE_RXEN0_SFT 15 -+#define MTX_FORCE_RXEN0_HI 15 -+#define MTX_FORCE_RXEN0_SZ 1 -+#define MTX_HALT_Q_MB_MSK 0x003f0000 -+#define MTX_HALT_Q_MB_I_MSK 0xffc0ffff -+#define MTX_HALT_Q_MB_SFT 16 -+#define MTX_HALT_Q_MB_HI 21 -+#define MTX_HALT_Q_MB_SZ 6 -+#define MTX_CTS_SET_DIF_MSK 0x00400000 -+#define MTX_CTS_SET_DIF_I_MSK 0xffbfffff -+#define MTX_CTS_SET_DIF_SFT 22 -+#define MTX_CTS_SET_DIF_HI 22 -+#define MTX_CTS_SET_DIF_SZ 1 -+#define MTX_AMPDU_SET_DIF_MSK 0x00800000 -+#define MTX_AMPDU_SET_DIF_I_MSK 0xff7fffff -+#define MTX_AMPDU_SET_DIF_SFT 23 -+#define MTX_AMPDU_SET_DIF_HI 23 -+#define MTX_AMPDU_SET_DIF_SZ 1 -+#define MTX_EDCCA_TOUT_MSK 0x000003ff -+#define MTX_EDCCA_TOUT_I_MSK 0xfffffc00 -+#define MTX_EDCCA_TOUT_SFT 0 -+#define MTX_EDCCA_TOUT_HI 9 -+#define MTX_EDCCA_TOUT_SZ 10 -+#define MTX_INT_BCN_MSK 0x00000002 -+#define MTX_INT_BCN_I_MSK 0xfffffffd -+#define MTX_INT_BCN_SFT 1 -+#define MTX_INT_BCN_HI 1 -+#define MTX_INT_BCN_SZ 1 -+#define MTX_INT_DTIM_MSK 0x00000008 -+#define MTX_INT_DTIM_I_MSK 0xfffffff7 -+#define MTX_INT_DTIM_SFT 3 -+#define MTX_INT_DTIM_HI 3 -+#define MTX_INT_DTIM_SZ 1 -+#define MTX_EN_INT_BCN_MSK 0x00000002 -+#define MTX_EN_INT_BCN_I_MSK 0xfffffffd -+#define MTX_EN_INT_BCN_SFT 1 -+#define MTX_EN_INT_BCN_HI 1 -+#define MTX_EN_INT_BCN_SZ 1 -+#define MTX_EN_INT_DTIM_MSK 0x00000008 -+#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7 -+#define MTX_EN_INT_DTIM_SFT 3 -+#define MTX_EN_INT_DTIM_HI 3 -+#define MTX_EN_INT_DTIM_SZ 1 -+#define MTX_BCN_TIMER_EN_MSK 0x00000001 -+#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe -+#define MTX_BCN_TIMER_EN_SFT 0 -+#define MTX_BCN_TIMER_EN_HI 0 -+#define MTX_BCN_TIMER_EN_SZ 1 -+#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002 -+#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd -+#define MTX_TIME_STAMP_AUTO_FILL_SFT 1 -+#define MTX_TIME_STAMP_AUTO_FILL_HI 1 -+#define MTX_TIME_STAMP_AUTO_FILL_SZ 1 -+#define MTX_TSF_TIMER_EN_MSK 0x00000020 -+#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf -+#define MTX_TSF_TIMER_EN_SFT 5 -+#define MTX_TSF_TIMER_EN_HI 5 -+#define MTX_TSF_TIMER_EN_SZ 1 -+#define MTX_HALT_MNG_UNTIL_DTIM_MSK 0x00000040 -+#define MTX_HALT_MNG_UNTIL_DTIM_I_MSK 0xffffffbf -+#define MTX_HALT_MNG_UNTIL_DTIM_SFT 6 -+#define MTX_HALT_MNG_UNTIL_DTIM_HI 6 -+#define MTX_HALT_MNG_UNTIL_DTIM_SZ 1 -+#define MTX_INT_DTIM_NUM_MSK 0x0000ff00 -+#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff -+#define MTX_INT_DTIM_NUM_SFT 8 -+#define MTX_INT_DTIM_NUM_HI 15 -+#define MTX_INT_DTIM_NUM_SZ 8 -+#define MTX_AUTO_FLUSH_Q4_MSK 0x00010000 -+#define MTX_AUTO_FLUSH_Q4_I_MSK 0xfffeffff -+#define MTX_AUTO_FLUSH_Q4_SFT 16 -+#define MTX_AUTO_FLUSH_Q4_HI 16 -+#define MTX_AUTO_FLUSH_Q4_SZ 1 -+#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001 -+#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe -+#define MTX_BCN_PKTID_CH_LOCK_SFT 0 -+#define MTX_BCN_PKTID_CH_LOCK_HI 0 -+#define MTX_BCN_PKTID_CH_LOCK_SZ 1 -+#define MTX_BCN_CFG_VLD_MSK 0x00000006 -+#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9 -+#define MTX_BCN_CFG_VLD_SFT 1 -+#define MTX_BCN_CFG_VLD_HI 2 -+#define MTX_BCN_CFG_VLD_SZ 2 -+#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008 -+#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7 -+#define MTX_AUTO_BCN_ONGOING_SFT 3 -+#define MTX_AUTO_BCN_ONGOING_HI 3 -+#define MTX_AUTO_BCN_ONGOING_SZ 1 -+#define MTX_BCN_TIMER_MSK 0xffff0000 -+#define MTX_BCN_TIMER_I_MSK 0x0000ffff -+#define MTX_BCN_TIMER_SFT 16 -+#define MTX_BCN_TIMER_HI 31 -+#define MTX_BCN_TIMER_SZ 16 -+#define MTX_BCN_PERIOD_MSK 0x0000ffff -+#define MTX_BCN_PERIOD_I_MSK 0xffff0000 -+#define MTX_BCN_PERIOD_SFT 0 -+#define MTX_BCN_PERIOD_HI 15 -+#define MTX_BCN_PERIOD_SZ 16 -+#define MTX_DTIM_NUM_MSK 0xff000000 -+#define MTX_DTIM_NUM_I_MSK 0x00ffffff -+#define MTX_DTIM_NUM_SFT 24 -+#define MTX_DTIM_NUM_HI 31 -+#define MTX_DTIM_NUM_SZ 8 -+#define MTX_BCN_TSF_L_MSK 0xffffffff -+#define MTX_BCN_TSF_L_I_MSK 0x00000000 -+#define MTX_BCN_TSF_L_SFT 0 -+#define MTX_BCN_TSF_L_HI 31 -+#define MTX_BCN_TSF_L_SZ 32 -+#define MTX_BCN_TSF_U_MSK 0xffffffff -+#define MTX_BCN_TSF_U_I_MSK 0x00000000 -+#define MTX_BCN_TSF_U_SFT 0 -+#define MTX_BCN_TSF_U_HI 31 -+#define MTX_BCN_TSF_U_SZ 32 -+#define MTX_BCN_PKT_ID0_MSK 0x0000007f -+#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80 -+#define MTX_BCN_PKT_ID0_SFT 0 -+#define MTX_BCN_PKT_ID0_HI 6 -+#define MTX_BCN_PKT_ID0_SZ 7 -+#define MTX_DTIM_OFST0_MSK 0x03ff0000 -+#define MTX_DTIM_OFST0_I_MSK 0xfc00ffff -+#define MTX_DTIM_OFST0_SFT 16 -+#define MTX_DTIM_OFST0_HI 25 -+#define MTX_DTIM_OFST0_SZ 10 -+#define MTX_BCN_PKT_ID1_MSK 0x0000007f -+#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80 -+#define MTX_BCN_PKT_ID1_SFT 0 -+#define MTX_BCN_PKT_ID1_HI 6 -+#define MTX_BCN_PKT_ID1_SZ 7 -+#define MTX_DTIM_OFST1_MSK 0x03ff0000 -+#define MTX_DTIM_OFST1_I_MSK 0xfc00ffff -+#define MTX_DTIM_OFST1_SFT 16 -+#define MTX_DTIM_OFST1_HI 25 -+#define MTX_DTIM_OFST1_SZ 10 -+#define MTX_CCA_MSK 0x00000001 -+#define MTX_CCA_I_MSK 0xfffffffe -+#define MTX_CCA_SFT 0 -+#define MTX_CCA_HI 0 -+#define MTX_CCA_SZ 1 -+#define MRX_CCA_MSK 0x00000002 -+#define MRX_CCA_I_MSK 0xfffffffd -+#define MRX_CCA_SFT 1 -+#define MRX_CCA_HI 1 -+#define MRX_CCA_SZ 1 -+#define MTX_DMA_FSM_MSK 0x0000001c -+#define MTX_DMA_FSM_I_MSK 0xffffffe3 -+#define MTX_DMA_FSM_SFT 2 -+#define MTX_DMA_FSM_HI 4 -+#define MTX_DMA_FSM_SZ 3 -+#define CH_ST_FSM_MSK 0x000000e0 -+#define CH_ST_FSM_I_MSK 0xffffff1f -+#define CH_ST_FSM_SFT 5 -+#define CH_ST_FSM_HI 7 -+#define CH_ST_FSM_SZ 3 -+#define MTX_GNT_LOCK_MSK 0x00000100 -+#define MTX_GNT_LOCK_I_MSK 0xfffffeff -+#define MTX_GNT_LOCK_SFT 8 -+#define MTX_GNT_LOCK_HI 8 -+#define MTX_GNT_LOCK_SZ 1 -+#define MTX_DMA_REQ_MSK 0x00000200 -+#define MTX_DMA_REQ_I_MSK 0xfffffdff -+#define MTX_DMA_REQ_SFT 9 -+#define MTX_DMA_REQ_HI 9 -+#define MTX_DMA_REQ_SZ 1 -+#define MTX_Q_REQ_MSK 0x00000400 -+#define MTX_Q_REQ_I_MSK 0xfffffbff -+#define MTX_Q_REQ_SFT 10 -+#define MTX_Q_REQ_HI 10 -+#define MTX_Q_REQ_SZ 1 -+#define MTX_TX_EN_MSK 0x00000800 -+#define MTX_TX_EN_I_MSK 0xfffff7ff -+#define MTX_TX_EN_SFT 11 -+#define MTX_TX_EN_HI 11 -+#define MTX_TX_EN_SZ 1 -+#define MRX_RX_EN_MSK 0x00001000 -+#define MRX_RX_EN_I_MSK 0xffffefff -+#define MRX_RX_EN_SFT 12 -+#define MRX_RX_EN_HI 12 -+#define MRX_RX_EN_SZ 1 -+#define DBG_PRTC_PRD_MSK 0x00002000 -+#define DBG_PRTC_PRD_I_MSK 0xffffdfff -+#define DBG_PRTC_PRD_SFT 13 -+#define DBG_PRTC_PRD_HI 13 -+#define DBG_PRTC_PRD_SZ 1 -+#define DBG_DMA_RDY_MSK 0x00004000 -+#define DBG_DMA_RDY_I_MSK 0xffffbfff -+#define DBG_DMA_RDY_SFT 14 -+#define DBG_DMA_RDY_HI 14 -+#define DBG_DMA_RDY_SZ 1 -+#define DBG_WAIT_RSP_MSK 0x00008000 -+#define DBG_WAIT_RSP_I_MSK 0xffff7fff -+#define DBG_WAIT_RSP_SFT 15 -+#define DBG_WAIT_RSP_HI 15 -+#define DBG_WAIT_RSP_SZ 1 -+#define DBG_CFRM_BUSY_MSK 0x00010000 -+#define DBG_CFRM_BUSY_I_MSK 0xfffeffff -+#define DBG_CFRM_BUSY_SFT 16 -+#define DBG_CFRM_BUSY_HI 16 -+#define DBG_CFRM_BUSY_SZ 1 -+#define DBG_RST_MSK 0x00000001 -+#define DBG_RST_I_MSK 0xfffffffe -+#define DBG_RST_SFT 0 -+#define DBG_RST_HI 0 -+#define DBG_RST_SZ 1 -+#define DBG_MODE_MSK 0x00000002 -+#define DBG_MODE_I_MSK 0xfffffffd -+#define DBG_MODE_SFT 1 -+#define DBG_MODE_HI 1 -+#define DBG_MODE_SZ 1 -+#define MB_REQ_DUR_MSK 0x0000ffff -+#define MB_REQ_DUR_I_MSK 0xffff0000 -+#define MB_REQ_DUR_SFT 0 -+#define MB_REQ_DUR_HI 15 -+#define MB_REQ_DUR_SZ 16 -+#define RX_EN_DUR_MSK 0xffff0000 -+#define RX_EN_DUR_I_MSK 0x0000ffff -+#define RX_EN_DUR_SFT 16 -+#define RX_EN_DUR_HI 31 -+#define RX_EN_DUR_SZ 16 -+#define RX_CS_DUR_MSK 0x0000ffff -+#define RX_CS_DUR_I_MSK 0xffff0000 -+#define RX_CS_DUR_SFT 0 -+#define RX_CS_DUR_HI 15 -+#define RX_CS_DUR_SZ 16 -+#define TX_CCA_DUR_MSK 0xffff0000 -+#define TX_CCA_DUR_I_MSK 0x0000ffff -+#define TX_CCA_DUR_SFT 16 -+#define TX_CCA_DUR_HI 31 -+#define TX_CCA_DUR_SZ 16 -+#define Q_REQ_DUR_MSK 0x0000ffff -+#define Q_REQ_DUR_I_MSK 0xffff0000 -+#define Q_REQ_DUR_SFT 0 -+#define Q_REQ_DUR_HI 15 -+#define Q_REQ_DUR_SZ 16 -+#define CH_STA0_DUR_MSK 0xffff0000 -+#define CH_STA0_DUR_I_MSK 0x0000ffff -+#define CH_STA0_DUR_SFT 16 -+#define CH_STA0_DUR_HI 31 -+#define CH_STA0_DUR_SZ 16 -+#define MTX_DUR_RSP_TOUT_B_MSK 0x000000ff -+#define MTX_DUR_RSP_TOUT_B_I_MSK 0xffffff00 -+#define MTX_DUR_RSP_TOUT_B_SFT 0 -+#define MTX_DUR_RSP_TOUT_B_HI 7 -+#define MTX_DUR_RSP_TOUT_B_SZ 8 -+#define MTX_DUR_RSP_TOUT_G_MSK 0x0000ff00 -+#define MTX_DUR_RSP_TOUT_G_I_MSK 0xffff00ff -+#define MTX_DUR_RSP_TOUT_G_SFT 8 -+#define MTX_DUR_RSP_TOUT_G_HI 15 -+#define MTX_DUR_RSP_TOUT_G_SZ 8 -+#define MTX_DUR_RSP_SIFS_MSK 0x000000ff -+#define MTX_DUR_RSP_SIFS_I_MSK 0xffffff00 -+#define MTX_DUR_RSP_SIFS_SFT 0 -+#define MTX_DUR_RSP_SIFS_HI 7 -+#define MTX_DUR_RSP_SIFS_SZ 8 -+#define MTX_DUR_BURST_SIFS_MSK 0x0000ff00 -+#define MTX_DUR_BURST_SIFS_I_MSK 0xffff00ff -+#define MTX_DUR_BURST_SIFS_SFT 8 -+#define MTX_DUR_BURST_SIFS_HI 15 -+#define MTX_DUR_BURST_SIFS_SZ 8 -+#define MTX_DUR_SLOT_MSK 0x003f0000 -+#define MTX_DUR_SLOT_I_MSK 0xffc0ffff -+#define MTX_DUR_SLOT_SFT 16 -+#define MTX_DUR_SLOT_HI 21 -+#define MTX_DUR_SLOT_SZ 6 -+#define MTX_DUR_RSP_EIFS_MSK 0xffc00000 -+#define MTX_DUR_RSP_EIFS_I_MSK 0x003fffff -+#define MTX_DUR_RSP_EIFS_SFT 22 -+#define MTX_DUR_RSP_EIFS_HI 31 -+#define MTX_DUR_RSP_EIFS_SZ 10 -+#define MTX_DUR_RSP_SIFS_G_MSK 0x000000ff -+#define MTX_DUR_RSP_SIFS_G_I_MSK 0xffffff00 -+#define MTX_DUR_RSP_SIFS_G_SFT 0 -+#define MTX_DUR_RSP_SIFS_G_HI 7 -+#define MTX_DUR_RSP_SIFS_G_SZ 8 -+#define MTX_DUR_BURST_SIFS_G_MSK 0x0000ff00 -+#define MTX_DUR_BURST_SIFS_G_I_MSK 0xffff00ff -+#define MTX_DUR_BURST_SIFS_G_SFT 8 -+#define MTX_DUR_BURST_SIFS_G_HI 15 -+#define MTX_DUR_BURST_SIFS_G_SZ 8 -+#define MTX_DUR_SLOT_G_MSK 0x003f0000 -+#define MTX_DUR_SLOT_G_I_MSK 0xffc0ffff -+#define MTX_DUR_SLOT_G_SFT 16 -+#define MTX_DUR_SLOT_G_HI 21 -+#define MTX_DUR_SLOT_G_SZ 6 -+#define MTX_DUR_RSP_EIFS_G_MSK 0xffc00000 -+#define MTX_DUR_RSP_EIFS_G_I_MSK 0x003fffff -+#define MTX_DUR_RSP_EIFS_G_SFT 22 -+#define MTX_DUR_RSP_EIFS_G_HI 31 -+#define MTX_DUR_RSP_EIFS_G_SZ 10 -+#define CH_STA1_DUR_MSK 0x0000ffff -+#define CH_STA1_DUR_I_MSK 0xffff0000 -+#define CH_STA1_DUR_SFT 0 -+#define CH_STA1_DUR_HI 15 -+#define CH_STA1_DUR_SZ 16 -+#define CH_STA2_DUR_MSK 0xffff0000 -+#define CH_STA2_DUR_I_MSK 0x0000ffff -+#define CH_STA2_DUR_SFT 16 -+#define CH_STA2_DUR_HI 31 -+#define CH_STA2_DUR_SZ 16 -+#define MTX_NAV_MSK 0x0000ffff -+#define MTX_NAV_I_MSK 0xffff0000 -+#define MTX_NAV_SFT 0 -+#define MTX_NAV_HI 15 -+#define MTX_NAV_SZ 16 -+#define MTX_MIB_CNT0_MSK 0x3fffffff -+#define MTX_MIB_CNT0_I_MSK 0xc0000000 -+#define MTX_MIB_CNT0_SFT 0 -+#define MTX_MIB_CNT0_HI 29 -+#define MTX_MIB_CNT0_SZ 30 -+#define MTX_MIB_EN0_MSK 0x40000000 -+#define MTX_MIB_EN0_I_MSK 0xbfffffff -+#define MTX_MIB_EN0_SFT 30 -+#define MTX_MIB_EN0_HI 30 -+#define MTX_MIB_EN0_SZ 1 -+#define MTX_MIB_CNT1_MSK 0x3fffffff -+#define MTX_MIB_CNT1_I_MSK 0xc0000000 -+#define MTX_MIB_CNT1_SFT 0 -+#define MTX_MIB_CNT1_HI 29 -+#define MTX_MIB_CNT1_SZ 30 -+#define MTX_MIB_EN1_MSK 0x40000000 -+#define MTX_MIB_EN1_I_MSK 0xbfffffff -+#define MTX_MIB_EN1_SFT 30 -+#define MTX_MIB_EN1_HI 30 -+#define MTX_MIB_EN1_SZ 1 -+#define CH_STA3_DUR_MSK 0x0000ffff -+#define CH_STA3_DUR_I_MSK 0xffff0000 -+#define CH_STA3_DUR_SFT 0 -+#define CH_STA3_DUR_HI 15 -+#define CH_STA3_DUR_SZ 16 -+#define CH_STA4_DUR_MSK 0xffff0000 -+#define CH_STA4_DUR_I_MSK 0x0000ffff -+#define CH_STA4_DUR_SFT 16 -+#define CH_STA4_DUR_HI 31 -+#define CH_STA4_DUR_SZ 16 -+#define TXQ0_MTX_Q_PRE_LD_MSK 0x00000002 -+#define TXQ0_MTX_Q_PRE_LD_I_MSK 0xfffffffd -+#define TXQ0_MTX_Q_PRE_LD_SFT 1 -+#define TXQ0_MTX_Q_PRE_LD_HI 1 -+#define TXQ0_MTX_Q_PRE_LD_SZ 1 -+#define TXQ0_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004 -+#define TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb -+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SFT 2 -+#define TXQ0_MTX_Q_BKF_CNT_FIXED_HI 2 -+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SZ 1 -+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008 -+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7 -+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3 -+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI 3 -+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1 -+#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010 -+#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef -+#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4 -+#define TXQ0_MTX_Q_MB_NO_RLS_HI 4 -+#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1 -+#define TXQ0_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020 -+#define TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf -+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SFT 5 -+#define TXQ0_MTX_Q_TXOP_FRC_BUR_HI 5 -+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SZ 1 -+#define TXQ0_MTX_Q_RND_MODE_MSK 0x000000c0 -+#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xffffff3f -+#define TXQ0_MTX_Q_RND_MODE_SFT 6 -+#define TXQ0_MTX_Q_RND_MODE_HI 7 -+#define TXQ0_MTX_Q_RND_MODE_SZ 2 -+#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f -+#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0 -+#define TXQ0_MTX_Q_AIFSN_SFT 0 -+#define TXQ0_MTX_Q_AIFSN_HI 3 -+#define TXQ0_MTX_Q_AIFSN_SZ 4 -+#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00 -+#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff -+#define TXQ0_MTX_Q_ECWMIN_SFT 8 -+#define TXQ0_MTX_Q_ECWMIN_HI 11 -+#define TXQ0_MTX_Q_ECWMIN_SZ 4 -+#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000 -+#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff -+#define TXQ0_MTX_Q_ECWMAX_SFT 12 -+#define TXQ0_MTX_Q_ECWMAX_HI 15 -+#define TXQ0_MTX_Q_ECWMAX_SZ 4 -+#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000 -+#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff -+#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16 -+#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31 -+#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16 -+#define TXQ0_MTX_Q_BKF_CNT_MSK 0x0000ffff -+#define TXQ0_MTX_Q_BKF_CNT_I_MSK 0xffff0000 -+#define TXQ0_MTX_Q_BKF_CNT_SFT 0 -+#define TXQ0_MTX_Q_BKF_CNT_HI 15 -+#define TXQ0_MTX_Q_BKF_CNT_SZ 16 -+#define TXQ0_MTX_Q_SRC_LIMIT_MSK 0x000000ff -+#define TXQ0_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00 -+#define TXQ0_MTX_Q_SRC_LIMIT_SFT 0 -+#define TXQ0_MTX_Q_SRC_LIMIT_HI 7 -+#define TXQ0_MTX_Q_SRC_LIMIT_SZ 8 -+#define TXQ0_MTX_Q_LRC_LIMIT_MSK 0x0000ff00 -+#define TXQ0_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff -+#define TXQ0_MTX_Q_LRC_LIMIT_SFT 8 -+#define TXQ0_MTX_Q_LRC_LIMIT_HI 15 -+#define TXQ0_MTX_Q_LRC_LIMIT_SZ 8 -+#define TXQ0_MTX_Q_ID_MAP_L_MSK 0xffffffff -+#define TXQ0_MTX_Q_ID_MAP_L_I_MSK 0x00000000 -+#define TXQ0_MTX_Q_ID_MAP_L_SFT 0 -+#define TXQ0_MTX_Q_ID_MAP_L_HI 31 -+#define TXQ0_MTX_Q_ID_MAP_L_SZ 32 -+#define TXQ0_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff -+#define TXQ0_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000 -+#define TXQ0_MTX_Q_TXOP_CH_THD_SFT 0 -+#define TXQ0_MTX_Q_TXOP_CH_THD_HI 15 -+#define TXQ0_MTX_Q_TXOP_CH_THD_SZ 16 -+#define TXQ0_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff -+#define TXQ0_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000 -+#define TXQ0_MTX_Q_TXOP_OV_THD_SFT 0 -+#define TXQ0_MTX_Q_TXOP_OV_THD_HI 15 -+#define TXQ0_MTX_Q_TXOP_OV_THD_SZ 16 -+#define TXQ1_MTX_Q_PRE_LD_MSK 0x00000002 -+#define TXQ1_MTX_Q_PRE_LD_I_MSK 0xfffffffd -+#define TXQ1_MTX_Q_PRE_LD_SFT 1 -+#define TXQ1_MTX_Q_PRE_LD_HI 1 -+#define TXQ1_MTX_Q_PRE_LD_SZ 1 -+#define TXQ1_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004 -+#define TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb -+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SFT 2 -+#define TXQ1_MTX_Q_BKF_CNT_FIXED_HI 2 -+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SZ 1 -+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008 -+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7 -+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3 -+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI 3 -+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1 -+#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010 -+#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef -+#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4 -+#define TXQ1_MTX_Q_MB_NO_RLS_HI 4 -+#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1 -+#define TXQ1_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020 -+#define TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf -+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SFT 5 -+#define TXQ1_MTX_Q_TXOP_FRC_BUR_HI 5 -+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SZ 1 -+#define TXQ1_MTX_Q_RND_MODE_MSK 0x000000c0 -+#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xffffff3f -+#define TXQ1_MTX_Q_RND_MODE_SFT 6 -+#define TXQ1_MTX_Q_RND_MODE_HI 7 -+#define TXQ1_MTX_Q_RND_MODE_SZ 2 -+#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f -+#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0 -+#define TXQ1_MTX_Q_AIFSN_SFT 0 -+#define TXQ1_MTX_Q_AIFSN_HI 3 -+#define TXQ1_MTX_Q_AIFSN_SZ 4 -+#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00 -+#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff -+#define TXQ1_MTX_Q_ECWMIN_SFT 8 -+#define TXQ1_MTX_Q_ECWMIN_HI 11 -+#define TXQ1_MTX_Q_ECWMIN_SZ 4 -+#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000 -+#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff -+#define TXQ1_MTX_Q_ECWMAX_SFT 12 -+#define TXQ1_MTX_Q_ECWMAX_HI 15 -+#define TXQ1_MTX_Q_ECWMAX_SZ 4 -+#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000 -+#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff -+#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16 -+#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31 -+#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16 -+#define TXQ1_MTX_Q_BKF_CNT_MSK 0x0000ffff -+#define TXQ1_MTX_Q_BKF_CNT_I_MSK 0xffff0000 -+#define TXQ1_MTX_Q_BKF_CNT_SFT 0 -+#define TXQ1_MTX_Q_BKF_CNT_HI 15 -+#define TXQ1_MTX_Q_BKF_CNT_SZ 16 -+#define TXQ1_MTX_Q_SRC_LIMIT_MSK 0x000000ff -+#define TXQ1_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00 -+#define TXQ1_MTX_Q_SRC_LIMIT_SFT 0 -+#define TXQ1_MTX_Q_SRC_LIMIT_HI 7 -+#define TXQ1_MTX_Q_SRC_LIMIT_SZ 8 -+#define TXQ1_MTX_Q_LRC_LIMIT_MSK 0x0000ff00 -+#define TXQ1_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff -+#define TXQ1_MTX_Q_LRC_LIMIT_SFT 8 -+#define TXQ1_MTX_Q_LRC_LIMIT_HI 15 -+#define TXQ1_MTX_Q_LRC_LIMIT_SZ 8 -+#define TXQ1_MTX_Q_ID_MAP_L_MSK 0xffffffff -+#define TXQ1_MTX_Q_ID_MAP_L_I_MSK 0x00000000 -+#define TXQ1_MTX_Q_ID_MAP_L_SFT 0 -+#define TXQ1_MTX_Q_ID_MAP_L_HI 31 -+#define TXQ1_MTX_Q_ID_MAP_L_SZ 32 -+#define TXQ1_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff -+#define TXQ1_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000 -+#define TXQ1_MTX_Q_TXOP_CH_THD_SFT 0 -+#define TXQ1_MTX_Q_TXOP_CH_THD_HI 15 -+#define TXQ1_MTX_Q_TXOP_CH_THD_SZ 16 -+#define TXQ1_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff -+#define TXQ1_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000 -+#define TXQ1_MTX_Q_TXOP_OV_THD_SFT 0 -+#define TXQ1_MTX_Q_TXOP_OV_THD_HI 15 -+#define TXQ1_MTX_Q_TXOP_OV_THD_SZ 16 -+#define TXQ2_MTX_Q_PRE_LD_MSK 0x00000002 -+#define TXQ2_MTX_Q_PRE_LD_I_MSK 0xfffffffd -+#define TXQ2_MTX_Q_PRE_LD_SFT 1 -+#define TXQ2_MTX_Q_PRE_LD_HI 1 -+#define TXQ2_MTX_Q_PRE_LD_SZ 1 -+#define TXQ2_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004 -+#define TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb -+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SFT 2 -+#define TXQ2_MTX_Q_BKF_CNT_FIXED_HI 2 -+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SZ 1 -+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008 -+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7 -+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3 -+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI 3 -+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1 -+#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010 -+#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef -+#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4 -+#define TXQ2_MTX_Q_MB_NO_RLS_HI 4 -+#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1 -+#define TXQ2_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020 -+#define TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf -+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SFT 5 -+#define TXQ2_MTX_Q_TXOP_FRC_BUR_HI 5 -+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SZ 1 -+#define TXQ2_MTX_Q_RND_MODE_MSK 0x000000c0 -+#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xffffff3f -+#define TXQ2_MTX_Q_RND_MODE_SFT 6 -+#define TXQ2_MTX_Q_RND_MODE_HI 7 -+#define TXQ2_MTX_Q_RND_MODE_SZ 2 -+#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f -+#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0 -+#define TXQ2_MTX_Q_AIFSN_SFT 0 -+#define TXQ2_MTX_Q_AIFSN_HI 3 -+#define TXQ2_MTX_Q_AIFSN_SZ 4 -+#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00 -+#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff -+#define TXQ2_MTX_Q_ECWMIN_SFT 8 -+#define TXQ2_MTX_Q_ECWMIN_HI 11 -+#define TXQ2_MTX_Q_ECWMIN_SZ 4 -+#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000 -+#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff -+#define TXQ2_MTX_Q_ECWMAX_SFT 12 -+#define TXQ2_MTX_Q_ECWMAX_HI 15 -+#define TXQ2_MTX_Q_ECWMAX_SZ 4 -+#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000 -+#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff -+#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16 -+#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31 -+#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16 -+#define TXQ2_MTX_Q_BKF_CNT_MSK 0x0000ffff -+#define TXQ2_MTX_Q_BKF_CNT_I_MSK 0xffff0000 -+#define TXQ2_MTX_Q_BKF_CNT_SFT 0 -+#define TXQ2_MTX_Q_BKF_CNT_HI 15 -+#define TXQ2_MTX_Q_BKF_CNT_SZ 16 -+#define TXQ2_MTX_Q_SRC_LIMIT_MSK 0x000000ff -+#define TXQ2_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00 -+#define TXQ2_MTX_Q_SRC_LIMIT_SFT 0 -+#define TXQ2_MTX_Q_SRC_LIMIT_HI 7 -+#define TXQ2_MTX_Q_SRC_LIMIT_SZ 8 -+#define TXQ2_MTX_Q_LRC_LIMIT_MSK 0x0000ff00 -+#define TXQ2_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff -+#define TXQ2_MTX_Q_LRC_LIMIT_SFT 8 -+#define TXQ2_MTX_Q_LRC_LIMIT_HI 15 -+#define TXQ2_MTX_Q_LRC_LIMIT_SZ 8 -+#define TXQ2_MTX_Q_ID_MAP_L_MSK 0xffffffff -+#define TXQ2_MTX_Q_ID_MAP_L_I_MSK 0x00000000 -+#define TXQ2_MTX_Q_ID_MAP_L_SFT 0 -+#define TXQ2_MTX_Q_ID_MAP_L_HI 31 -+#define TXQ2_MTX_Q_ID_MAP_L_SZ 32 -+#define TXQ2_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff -+#define TXQ2_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000 -+#define TXQ2_MTX_Q_TXOP_CH_THD_SFT 0 -+#define TXQ2_MTX_Q_TXOP_CH_THD_HI 15 -+#define TXQ2_MTX_Q_TXOP_CH_THD_SZ 16 -+#define TXQ2_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff -+#define TXQ2_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000 -+#define TXQ2_MTX_Q_TXOP_OV_THD_SFT 0 -+#define TXQ2_MTX_Q_TXOP_OV_THD_HI 15 -+#define TXQ2_MTX_Q_TXOP_OV_THD_SZ 16 -+#define TXQ3_MTX_Q_PRE_LD_MSK 0x00000002 -+#define TXQ3_MTX_Q_PRE_LD_I_MSK 0xfffffffd -+#define TXQ3_MTX_Q_PRE_LD_SFT 1 -+#define TXQ3_MTX_Q_PRE_LD_HI 1 -+#define TXQ3_MTX_Q_PRE_LD_SZ 1 -+#define TXQ3_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004 -+#define TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb -+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SFT 2 -+#define TXQ3_MTX_Q_BKF_CNT_FIXED_HI 2 -+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SZ 1 -+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008 -+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7 -+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3 -+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI 3 -+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1 -+#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010 -+#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef -+#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4 -+#define TXQ3_MTX_Q_MB_NO_RLS_HI 4 -+#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1 -+#define TXQ3_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020 -+#define TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf -+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SFT 5 -+#define TXQ3_MTX_Q_TXOP_FRC_BUR_HI 5 -+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SZ 1 -+#define TXQ3_MTX_Q_RND_MODE_MSK 0x000000c0 -+#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xffffff3f -+#define TXQ3_MTX_Q_RND_MODE_SFT 6 -+#define TXQ3_MTX_Q_RND_MODE_HI 7 -+#define TXQ3_MTX_Q_RND_MODE_SZ 2 -+#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f -+#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0 -+#define TXQ3_MTX_Q_AIFSN_SFT 0 -+#define TXQ3_MTX_Q_AIFSN_HI 3 -+#define TXQ3_MTX_Q_AIFSN_SZ 4 -+#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00 -+#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff -+#define TXQ3_MTX_Q_ECWMIN_SFT 8 -+#define TXQ3_MTX_Q_ECWMIN_HI 11 -+#define TXQ3_MTX_Q_ECWMIN_SZ 4 -+#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000 -+#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff -+#define TXQ3_MTX_Q_ECWMAX_SFT 12 -+#define TXQ3_MTX_Q_ECWMAX_HI 15 -+#define TXQ3_MTX_Q_ECWMAX_SZ 4 -+#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000 -+#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff -+#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16 -+#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31 -+#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16 -+#define TXQ3_MTX_Q_BKF_CNT_MSK 0x0000ffff -+#define TXQ3_MTX_Q_BKF_CNT_I_MSK 0xffff0000 -+#define TXQ3_MTX_Q_BKF_CNT_SFT 0 -+#define TXQ3_MTX_Q_BKF_CNT_HI 15 -+#define TXQ3_MTX_Q_BKF_CNT_SZ 16 -+#define TXQ3_MTX_Q_SRC_LIMIT_MSK 0x000000ff -+#define TXQ3_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00 -+#define TXQ3_MTX_Q_SRC_LIMIT_SFT 0 -+#define TXQ3_MTX_Q_SRC_LIMIT_HI 7 -+#define TXQ3_MTX_Q_SRC_LIMIT_SZ 8 -+#define TXQ3_MTX_Q_LRC_LIMIT_MSK 0x0000ff00 -+#define TXQ3_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff -+#define TXQ3_MTX_Q_LRC_LIMIT_SFT 8 -+#define TXQ3_MTX_Q_LRC_LIMIT_HI 15 -+#define TXQ3_MTX_Q_LRC_LIMIT_SZ 8 -+#define TXQ3_MTX_Q_ID_MAP_L_MSK 0xffffffff -+#define TXQ3_MTX_Q_ID_MAP_L_I_MSK 0x00000000 -+#define TXQ3_MTX_Q_ID_MAP_L_SFT 0 -+#define TXQ3_MTX_Q_ID_MAP_L_HI 31 -+#define TXQ3_MTX_Q_ID_MAP_L_SZ 32 -+#define TXQ3_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff -+#define TXQ3_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000 -+#define TXQ3_MTX_Q_TXOP_CH_THD_SFT 0 -+#define TXQ3_MTX_Q_TXOP_CH_THD_HI 15 -+#define TXQ3_MTX_Q_TXOP_CH_THD_SZ 16 -+#define TXQ3_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff -+#define TXQ3_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000 -+#define TXQ3_MTX_Q_TXOP_OV_THD_SFT 0 -+#define TXQ3_MTX_Q_TXOP_OV_THD_HI 15 -+#define TXQ3_MTX_Q_TXOP_OV_THD_SZ 16 -+#define TXQ4_MTX_Q_PRE_LD_MSK 0x00000002 -+#define TXQ4_MTX_Q_PRE_LD_I_MSK 0xfffffffd -+#define TXQ4_MTX_Q_PRE_LD_SFT 1 -+#define TXQ4_MTX_Q_PRE_LD_HI 1 -+#define TXQ4_MTX_Q_PRE_LD_SZ 1 -+#define TXQ4_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004 -+#define TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb -+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SFT 2 -+#define TXQ4_MTX_Q_BKF_CNT_FIXED_HI 2 -+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SZ 1 -+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008 -+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7 -+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3 -+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI 3 -+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1 -+#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010 -+#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef -+#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4 -+#define TXQ4_MTX_Q_MB_NO_RLS_HI 4 -+#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1 -+#define TXQ4_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020 -+#define TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf -+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SFT 5 -+#define TXQ4_MTX_Q_TXOP_FRC_BUR_HI 5 -+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SZ 1 -+#define TXQ4_MTX_Q_RND_MODE_MSK 0x000000c0 -+#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xffffff3f -+#define TXQ4_MTX_Q_RND_MODE_SFT 6 -+#define TXQ4_MTX_Q_RND_MODE_HI 7 -+#define TXQ4_MTX_Q_RND_MODE_SZ 2 -+#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f -+#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0 -+#define TXQ4_MTX_Q_AIFSN_SFT 0 -+#define TXQ4_MTX_Q_AIFSN_HI 3 -+#define TXQ4_MTX_Q_AIFSN_SZ 4 -+#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00 -+#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff -+#define TXQ4_MTX_Q_ECWMIN_SFT 8 -+#define TXQ4_MTX_Q_ECWMIN_HI 11 -+#define TXQ4_MTX_Q_ECWMIN_SZ 4 -+#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000 -+#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff -+#define TXQ4_MTX_Q_ECWMAX_SFT 12 -+#define TXQ4_MTX_Q_ECWMAX_HI 15 -+#define TXQ4_MTX_Q_ECWMAX_SZ 4 -+#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000 -+#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff -+#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16 -+#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31 -+#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16 -+#define TXQ4_MTX_Q_BKF_CNT_MSK 0x0000ffff -+#define TXQ4_MTX_Q_BKF_CNT_I_MSK 0xffff0000 -+#define TXQ4_MTX_Q_BKF_CNT_SFT 0 -+#define TXQ4_MTX_Q_BKF_CNT_HI 15 -+#define TXQ4_MTX_Q_BKF_CNT_SZ 16 -+#define TXQ4_MTX_Q_SRC_LIMIT_MSK 0x000000ff -+#define TXQ4_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00 -+#define TXQ4_MTX_Q_SRC_LIMIT_SFT 0 -+#define TXQ4_MTX_Q_SRC_LIMIT_HI 7 -+#define TXQ4_MTX_Q_SRC_LIMIT_SZ 8 -+#define TXQ4_MTX_Q_LRC_LIMIT_MSK 0x0000ff00 -+#define TXQ4_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff -+#define TXQ4_MTX_Q_LRC_LIMIT_SFT 8 -+#define TXQ4_MTX_Q_LRC_LIMIT_HI 15 -+#define TXQ4_MTX_Q_LRC_LIMIT_SZ 8 -+#define TXQ4_MTX_Q_ID_MAP_L_MSK 0xffffffff -+#define TXQ4_MTX_Q_ID_MAP_L_I_MSK 0x00000000 -+#define TXQ4_MTX_Q_ID_MAP_L_SFT 0 -+#define TXQ4_MTX_Q_ID_MAP_L_HI 31 -+#define TXQ4_MTX_Q_ID_MAP_L_SZ 32 -+#define TXQ4_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff -+#define TXQ4_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000 -+#define TXQ4_MTX_Q_TXOP_CH_THD_SFT 0 -+#define TXQ4_MTX_Q_TXOP_CH_THD_HI 15 -+#define TXQ4_MTX_Q_TXOP_CH_THD_SZ 16 -+#define TXQ4_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff -+#define TXQ4_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000 -+#define TXQ4_MTX_Q_TXOP_OV_THD_SFT 0 -+#define TXQ4_MTX_Q_TXOP_OV_THD_HI 15 -+#define TXQ4_MTX_Q_TXOP_OV_THD_SZ 16 -+#define VALID0_MSK 0x00000001 -+#define VALID0_I_MSK 0xfffffffe -+#define VALID0_SFT 0 -+#define VALID0_HI 0 -+#define VALID0_SZ 1 -+#define PEER_QOS_EN0_MSK 0x00000002 -+#define PEER_QOS_EN0_I_MSK 0xfffffffd -+#define PEER_QOS_EN0_SFT 1 -+#define PEER_QOS_EN0_HI 1 -+#define PEER_QOS_EN0_SZ 1 -+#define PEER_OP_MODE0_MSK 0x0000000c -+#define PEER_OP_MODE0_I_MSK 0xfffffff3 -+#define PEER_OP_MODE0_SFT 2 -+#define PEER_OP_MODE0_HI 3 -+#define PEER_OP_MODE0_SZ 2 -+#define PEER_HT_MODE0_MSK 0x00000030 -+#define PEER_HT_MODE0_I_MSK 0xffffffcf -+#define PEER_HT_MODE0_SFT 4 -+#define PEER_HT_MODE0_HI 5 -+#define PEER_HT_MODE0_SZ 2 -+#define PEER_MAC0_31_0_MSK 0xffffffff -+#define PEER_MAC0_31_0_I_MSK 0x00000000 -+#define PEER_MAC0_31_0_SFT 0 -+#define PEER_MAC0_31_0_HI 31 -+#define PEER_MAC0_31_0_SZ 32 -+#define PEER_MAC0_47_32_MSK 0x0000ffff -+#define PEER_MAC0_47_32_I_MSK 0xffff0000 -+#define PEER_MAC0_47_32_SFT 0 -+#define PEER_MAC0_47_32_HI 15 -+#define PEER_MAC0_47_32_SZ 16 -+#define TX_ACK_POLICY_0_0_MSK 0x00000003 -+#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_0_0_SFT 0 -+#define TX_ACK_POLICY_0_0_HI 1 -+#define TX_ACK_POLICY_0_0_SZ 2 -+#define TX_SEQ_CTRL_0_0_MSK 0x00000fff -+#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_0_0_SFT 0 -+#define TX_SEQ_CTRL_0_0_HI 11 -+#define TX_SEQ_CTRL_0_0_SZ 12 -+#define TX_ACK_POLICY_0_1_MSK 0x00000003 -+#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_0_1_SFT 0 -+#define TX_ACK_POLICY_0_1_HI 1 -+#define TX_ACK_POLICY_0_1_SZ 2 -+#define TX_SEQ_CTRL_0_1_MSK 0x00000fff -+#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_0_1_SFT 0 -+#define TX_SEQ_CTRL_0_1_HI 11 -+#define TX_SEQ_CTRL_0_1_SZ 12 -+#define TX_ACK_POLICY_0_2_MSK 0x00000003 -+#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_0_2_SFT 0 -+#define TX_ACK_POLICY_0_2_HI 1 -+#define TX_ACK_POLICY_0_2_SZ 2 -+#define TX_SEQ_CTRL_0_2_MSK 0x00000fff -+#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_0_2_SFT 0 -+#define TX_SEQ_CTRL_0_2_HI 11 -+#define TX_SEQ_CTRL_0_2_SZ 12 -+#define TX_ACK_POLICY_0_3_MSK 0x00000003 -+#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_0_3_SFT 0 -+#define TX_ACK_POLICY_0_3_HI 1 -+#define TX_ACK_POLICY_0_3_SZ 2 -+#define TX_SEQ_CTRL_0_3_MSK 0x00000fff -+#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_0_3_SFT 0 -+#define TX_SEQ_CTRL_0_3_HI 11 -+#define TX_SEQ_CTRL_0_3_SZ 12 -+#define TX_ACK_POLICY_0_4_MSK 0x00000003 -+#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_0_4_SFT 0 -+#define TX_ACK_POLICY_0_4_HI 1 -+#define TX_ACK_POLICY_0_4_SZ 2 -+#define TX_SEQ_CTRL_0_4_MSK 0x00000fff -+#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_0_4_SFT 0 -+#define TX_SEQ_CTRL_0_4_HI 11 -+#define TX_SEQ_CTRL_0_4_SZ 12 -+#define TX_ACK_POLICY_0_5_MSK 0x00000003 -+#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_0_5_SFT 0 -+#define TX_ACK_POLICY_0_5_HI 1 -+#define TX_ACK_POLICY_0_5_SZ 2 -+#define TX_SEQ_CTRL_0_5_MSK 0x00000fff -+#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_0_5_SFT 0 -+#define TX_SEQ_CTRL_0_5_HI 11 -+#define TX_SEQ_CTRL_0_5_SZ 12 -+#define TX_ACK_POLICY_0_6_MSK 0x00000003 -+#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_0_6_SFT 0 -+#define TX_ACK_POLICY_0_6_HI 1 -+#define TX_ACK_POLICY_0_6_SZ 2 -+#define TX_SEQ_CTRL_0_6_MSK 0x00000fff -+#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_0_6_SFT 0 -+#define TX_SEQ_CTRL_0_6_HI 11 -+#define TX_SEQ_CTRL_0_6_SZ 12 -+#define TX_ACK_POLICY_0_7_MSK 0x00000003 -+#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_0_7_SFT 0 -+#define TX_ACK_POLICY_0_7_HI 1 -+#define TX_ACK_POLICY_0_7_SZ 2 -+#define TX_SEQ_CTRL_0_7_MSK 0x00000fff -+#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_0_7_SFT 0 -+#define TX_SEQ_CTRL_0_7_HI 11 -+#define TX_SEQ_CTRL_0_7_SZ 12 -+#define VALID1_MSK 0x00000001 -+#define VALID1_I_MSK 0xfffffffe -+#define VALID1_SFT 0 -+#define VALID1_HI 0 -+#define VALID1_SZ 1 -+#define PEER_QOS_EN1_MSK 0x00000002 -+#define PEER_QOS_EN1_I_MSK 0xfffffffd -+#define PEER_QOS_EN1_SFT 1 -+#define PEER_QOS_EN1_HI 1 -+#define PEER_QOS_EN1_SZ 1 -+#define PEER_OP_MODE1_MSK 0x0000000c -+#define PEER_OP_MODE1_I_MSK 0xfffffff3 -+#define PEER_OP_MODE1_SFT 2 -+#define PEER_OP_MODE1_HI 3 -+#define PEER_OP_MODE1_SZ 2 -+#define PEER_HT_MODE1_MSK 0x00000030 -+#define PEER_HT_MODE1_I_MSK 0xffffffcf -+#define PEER_HT_MODE1_SFT 4 -+#define PEER_HT_MODE1_HI 5 -+#define PEER_HT_MODE1_SZ 2 -+#define PEER_MAC1_31_0_MSK 0xffffffff -+#define PEER_MAC1_31_0_I_MSK 0x00000000 -+#define PEER_MAC1_31_0_SFT 0 -+#define PEER_MAC1_31_0_HI 31 -+#define PEER_MAC1_31_0_SZ 32 -+#define PEER_MAC1_47_32_MSK 0x0000ffff -+#define PEER_MAC1_47_32_I_MSK 0xffff0000 -+#define PEER_MAC1_47_32_SFT 0 -+#define PEER_MAC1_47_32_HI 15 -+#define PEER_MAC1_47_32_SZ 16 -+#define TX_ACK_POLICY_1_0_MSK 0x00000003 -+#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_1_0_SFT 0 -+#define TX_ACK_POLICY_1_0_HI 1 -+#define TX_ACK_POLICY_1_0_SZ 2 -+#define TX_SEQ_CTRL_1_0_MSK 0x00000fff -+#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_1_0_SFT 0 -+#define TX_SEQ_CTRL_1_0_HI 11 -+#define TX_SEQ_CTRL_1_0_SZ 12 -+#define TX_ACK_POLICY_1_1_MSK 0x00000003 -+#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_1_1_SFT 0 -+#define TX_ACK_POLICY_1_1_HI 1 -+#define TX_ACK_POLICY_1_1_SZ 2 -+#define TX_SEQ_CTRL_1_1_MSK 0x00000fff -+#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_1_1_SFT 0 -+#define TX_SEQ_CTRL_1_1_HI 11 -+#define TX_SEQ_CTRL_1_1_SZ 12 -+#define TX_ACK_POLICY_1_2_MSK 0x00000003 -+#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_1_2_SFT 0 -+#define TX_ACK_POLICY_1_2_HI 1 -+#define TX_ACK_POLICY_1_2_SZ 2 -+#define TX_SEQ_CTRL_1_2_MSK 0x00000fff -+#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_1_2_SFT 0 -+#define TX_SEQ_CTRL_1_2_HI 11 -+#define TX_SEQ_CTRL_1_2_SZ 12 -+#define TX_ACK_POLICY_1_3_MSK 0x00000003 -+#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_1_3_SFT 0 -+#define TX_ACK_POLICY_1_3_HI 1 -+#define TX_ACK_POLICY_1_3_SZ 2 -+#define TX_SEQ_CTRL_1_3_MSK 0x00000fff -+#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_1_3_SFT 0 -+#define TX_SEQ_CTRL_1_3_HI 11 -+#define TX_SEQ_CTRL_1_3_SZ 12 -+#define TX_ACK_POLICY_1_4_MSK 0x00000003 -+#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_1_4_SFT 0 -+#define TX_ACK_POLICY_1_4_HI 1 -+#define TX_ACK_POLICY_1_4_SZ 2 -+#define TX_SEQ_CTRL_1_4_MSK 0x00000fff -+#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_1_4_SFT 0 -+#define TX_SEQ_CTRL_1_4_HI 11 -+#define TX_SEQ_CTRL_1_4_SZ 12 -+#define TX_ACK_POLICY_1_5_MSK 0x00000003 -+#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_1_5_SFT 0 -+#define TX_ACK_POLICY_1_5_HI 1 -+#define TX_ACK_POLICY_1_5_SZ 2 -+#define TX_SEQ_CTRL_1_5_MSK 0x00000fff -+#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_1_5_SFT 0 -+#define TX_SEQ_CTRL_1_5_HI 11 -+#define TX_SEQ_CTRL_1_5_SZ 12 -+#define TX_ACK_POLICY_1_6_MSK 0x00000003 -+#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_1_6_SFT 0 -+#define TX_ACK_POLICY_1_6_HI 1 -+#define TX_ACK_POLICY_1_6_SZ 2 -+#define TX_SEQ_CTRL_1_6_MSK 0x00000fff -+#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_1_6_SFT 0 -+#define TX_SEQ_CTRL_1_6_HI 11 -+#define TX_SEQ_CTRL_1_6_SZ 12 -+#define TX_ACK_POLICY_1_7_MSK 0x00000003 -+#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc -+#define TX_ACK_POLICY_1_7_SFT 0 -+#define TX_ACK_POLICY_1_7_HI 1 -+#define TX_ACK_POLICY_1_7_SZ 2 -+#define TX_SEQ_CTRL_1_7_MSK 0x00000fff -+#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000 -+#define TX_SEQ_CTRL_1_7_SFT 0 -+#define TX_SEQ_CTRL_1_7_HI 11 -+#define TX_SEQ_CTRL_1_7_SZ 12 -+#define INFO0_MSK 0xffffffff -+#define INFO0_I_MSK 0x00000000 -+#define INFO0_SFT 0 -+#define INFO0_HI 31 -+#define INFO0_SZ 32 -+#define INFO1_MSK 0xffffffff -+#define INFO1_I_MSK 0x00000000 -+#define INFO1_SFT 0 -+#define INFO1_HI 31 -+#define INFO1_SZ 32 -+#define INFO2_MSK 0xffffffff -+#define INFO2_I_MSK 0x00000000 -+#define INFO2_SFT 0 -+#define INFO2_HI 31 -+#define INFO2_SZ 32 -+#define INFO3_MSK 0xffffffff -+#define INFO3_I_MSK 0x00000000 -+#define INFO3_SFT 0 -+#define INFO3_HI 31 -+#define INFO3_SZ 32 -+#define INFO4_MSK 0xffffffff -+#define INFO4_I_MSK 0x00000000 -+#define INFO4_SFT 0 -+#define INFO4_HI 31 -+#define INFO4_SZ 32 -+#define INFO5_MSK 0xffffffff -+#define INFO5_I_MSK 0x00000000 -+#define INFO5_SFT 0 -+#define INFO5_HI 31 -+#define INFO5_SZ 32 -+#define INFO6_MSK 0xffffffff -+#define INFO6_I_MSK 0x00000000 -+#define INFO6_SFT 0 -+#define INFO6_HI 31 -+#define INFO6_SZ 32 -+#define INFO7_MSK 0xffffffff -+#define INFO7_I_MSK 0x00000000 -+#define INFO7_SFT 0 -+#define INFO7_HI 31 -+#define INFO7_SZ 32 -+#define INFO8_MSK 0xffffffff -+#define INFO8_I_MSK 0x00000000 -+#define INFO8_SFT 0 -+#define INFO8_HI 31 -+#define INFO8_SZ 32 -+#define INFO9_MSK 0xffffffff -+#define INFO9_I_MSK 0x00000000 -+#define INFO9_SFT 0 -+#define INFO9_HI 31 -+#define INFO9_SZ 32 -+#define INFO10_MSK 0xffffffff -+#define INFO10_I_MSK 0x00000000 -+#define INFO10_SFT 0 -+#define INFO10_HI 31 -+#define INFO10_SZ 32 -+#define INFO11_MSK 0xffffffff -+#define INFO11_I_MSK 0x00000000 -+#define INFO11_SFT 0 -+#define INFO11_HI 31 -+#define INFO11_SZ 32 -+#define INFO12_MSK 0xffffffff -+#define INFO12_I_MSK 0x00000000 -+#define INFO12_SFT 0 -+#define INFO12_HI 31 -+#define INFO12_SZ 32 -+#define INFO13_MSK 0xffffffff -+#define INFO13_I_MSK 0x00000000 -+#define INFO13_SFT 0 -+#define INFO13_HI 31 -+#define INFO13_SZ 32 -+#define INFO14_MSK 0xffffffff -+#define INFO14_I_MSK 0x00000000 -+#define INFO14_SFT 0 -+#define INFO14_HI 31 -+#define INFO14_SZ 32 -+#define INFO15_MSK 0xffffffff -+#define INFO15_I_MSK 0x00000000 -+#define INFO15_SFT 0 -+#define INFO15_HI 31 -+#define INFO15_SZ 32 -+#define INFO16_MSK 0xffffffff -+#define INFO16_I_MSK 0x00000000 -+#define INFO16_SFT 0 -+#define INFO16_HI 31 -+#define INFO16_SZ 32 -+#define INFO17_MSK 0xffffffff -+#define INFO17_I_MSK 0x00000000 -+#define INFO17_SFT 0 -+#define INFO17_HI 31 -+#define INFO17_SZ 32 -+#define INFO18_MSK 0xffffffff -+#define INFO18_I_MSK 0x00000000 -+#define INFO18_SFT 0 -+#define INFO18_HI 31 -+#define INFO18_SZ 32 -+#define INFO19_MSK 0xffffffff -+#define INFO19_I_MSK 0x00000000 -+#define INFO19_SFT 0 -+#define INFO19_HI 31 -+#define INFO19_SZ 32 -+#define INFO20_MSK 0xffffffff -+#define INFO20_I_MSK 0x00000000 -+#define INFO20_SFT 0 -+#define INFO20_HI 31 -+#define INFO20_SZ 32 -+#define INFO21_MSK 0xffffffff -+#define INFO21_I_MSK 0x00000000 -+#define INFO21_SFT 0 -+#define INFO21_HI 31 -+#define INFO21_SZ 32 -+#define INFO22_MSK 0xffffffff -+#define INFO22_I_MSK 0x00000000 -+#define INFO22_SFT 0 -+#define INFO22_HI 31 -+#define INFO22_SZ 32 -+#define INFO23_MSK 0xffffffff -+#define INFO23_I_MSK 0x00000000 -+#define INFO23_SFT 0 -+#define INFO23_HI 31 -+#define INFO23_SZ 32 -+#define INFO24_MSK 0xffffffff -+#define INFO24_I_MSK 0x00000000 -+#define INFO24_SFT 0 -+#define INFO24_HI 31 -+#define INFO24_SZ 32 -+#define INFO25_MSK 0xffffffff -+#define INFO25_I_MSK 0x00000000 -+#define INFO25_SFT 0 -+#define INFO25_HI 31 -+#define INFO25_SZ 32 -+#define INFO26_MSK 0xffffffff -+#define INFO26_I_MSK 0x00000000 -+#define INFO26_SFT 0 -+#define INFO26_HI 31 -+#define INFO26_SZ 32 -+#define INFO27_MSK 0xffffffff -+#define INFO27_I_MSK 0x00000000 -+#define INFO27_SFT 0 -+#define INFO27_HI 31 -+#define INFO27_SZ 32 -+#define INFO28_MSK 0xffffffff -+#define INFO28_I_MSK 0x00000000 -+#define INFO28_SFT 0 -+#define INFO28_HI 31 -+#define INFO28_SZ 32 -+#define INFO29_MSK 0xffffffff -+#define INFO29_I_MSK 0x00000000 -+#define INFO29_SFT 0 -+#define INFO29_HI 31 -+#define INFO29_SZ 32 -+#define INFO30_MSK 0xffffffff -+#define INFO30_I_MSK 0x00000000 -+#define INFO30_SFT 0 -+#define INFO30_HI 31 -+#define INFO30_SZ 32 -+#define INFO31_MSK 0xffffffff -+#define INFO31_I_MSK 0x00000000 -+#define INFO31_SFT 0 -+#define INFO31_HI 31 -+#define INFO31_SZ 32 -+#define INFO32_MSK 0xffffffff -+#define INFO32_I_MSK 0x00000000 -+#define INFO32_SFT 0 -+#define INFO32_HI 31 -+#define INFO32_SZ 32 -+#define INFO33_MSK 0xffffffff -+#define INFO33_I_MSK 0x00000000 -+#define INFO33_SFT 0 -+#define INFO33_HI 31 -+#define INFO33_SZ 32 -+#define INFO34_MSK 0xffffffff -+#define INFO34_I_MSK 0x00000000 -+#define INFO34_SFT 0 -+#define INFO34_HI 31 -+#define INFO34_SZ 32 -+#define INFO35_MSK 0xffffffff -+#define INFO35_I_MSK 0x00000000 -+#define INFO35_SFT 0 -+#define INFO35_HI 31 -+#define INFO35_SZ 32 -+#define INFO36_MSK 0xffffffff -+#define INFO36_I_MSK 0x00000000 -+#define INFO36_SFT 0 -+#define INFO36_HI 31 -+#define INFO36_SZ 32 -+#define INFO37_MSK 0xffffffff -+#define INFO37_I_MSK 0x00000000 -+#define INFO37_SFT 0 -+#define INFO37_HI 31 -+#define INFO37_SZ 32 -+#define INFO38_MSK 0xffffffff -+#define INFO38_I_MSK 0x00000000 -+#define INFO38_SFT 0 -+#define INFO38_HI 31 -+#define INFO38_SZ 32 -+#define INFO_MASK_MSK 0xffffffff -+#define INFO_MASK_I_MSK 0x00000000 -+#define INFO_MASK_SFT 0 -+#define INFO_MASK_HI 31 -+#define INFO_MASK_SZ 32 -+#define INFO_DEF_RATE_MSK 0x0000003f -+#define INFO_DEF_RATE_I_MSK 0xffffffc0 -+#define INFO_DEF_RATE_SFT 0 -+#define INFO_DEF_RATE_HI 5 -+#define INFO_DEF_RATE_SZ 6 -+#define INFO_MRX_OFFSET_MSK 0x000f0000 -+#define INFO_MRX_OFFSET_I_MSK 0xfff0ffff -+#define INFO_MRX_OFFSET_SFT 16 -+#define INFO_MRX_OFFSET_HI 19 -+#define INFO_MRX_OFFSET_SZ 4 -+#define BCAST_RATEUNKNOW_MSK 0x3f000000 -+#define BCAST_RATEUNKNOW_I_MSK 0xc0ffffff -+#define BCAST_RATEUNKNOW_SFT 24 -+#define BCAST_RATEUNKNOW_HI 29 -+#define BCAST_RATEUNKNOW_SZ 6 -+#define INFO_IDX_TBL_ADDR_MSK 0xffffffff -+#define INFO_IDX_TBL_ADDR_I_MSK 0x00000000 -+#define INFO_IDX_TBL_ADDR_SFT 0 -+#define INFO_IDX_TBL_ADDR_HI 31 -+#define INFO_IDX_TBL_ADDR_SZ 32 -+#define INFO_LEN_TBL_ADDR_MSK 0xffffffff -+#define INFO_LEN_TBL_ADDR_I_MSK 0x00000000 -+#define INFO_LEN_TBL_ADDR_SFT 0 -+#define INFO_LEN_TBL_ADDR_HI 31 -+#define INFO_LEN_TBL_ADDR_SZ 32 -+#define IC_TAG_31_0_MSK 0xffffffff -+#define IC_TAG_31_0_I_MSK 0x00000000 -+#define IC_TAG_31_0_SFT 0 -+#define IC_TAG_31_0_HI 31 -+#define IC_TAG_31_0_SZ 32 -+#define IC_TAG_63_32_MSK 0xffffffff -+#define IC_TAG_63_32_I_MSK 0x00000000 -+#define IC_TAG_63_32_SFT 0 -+#define IC_TAG_63_32_HI 31 -+#define IC_TAG_63_32_SZ 32 -+#define CH1_PRI_MSK 0x00000003 -+#define CH1_PRI_I_MSK 0xfffffffc -+#define CH1_PRI_SFT 0 -+#define CH1_PRI_HI 1 -+#define CH1_PRI_SZ 2 -+#define CH2_PRI_MSK 0x00000300 -+#define CH2_PRI_I_MSK 0xfffffcff -+#define CH2_PRI_SFT 8 -+#define CH2_PRI_HI 9 -+#define CH2_PRI_SZ 2 -+#define CH3_PRI_MSK 0x00030000 -+#define CH3_PRI_I_MSK 0xfffcffff -+#define CH3_PRI_SFT 16 -+#define CH3_PRI_HI 17 -+#define CH3_PRI_SZ 2 -+#define RG_MAC_LPBK_MSK 0x00000001 -+#define RG_MAC_LPBK_I_MSK 0xfffffffe -+#define RG_MAC_LPBK_SFT 0 -+#define RG_MAC_LPBK_HI 0 -+#define RG_MAC_LPBK_SZ 1 -+#define RG_MAC_M2M_MSK 0x00000002 -+#define RG_MAC_M2M_I_MSK 0xfffffffd -+#define RG_MAC_M2M_SFT 1 -+#define RG_MAC_M2M_HI 1 -+#define RG_MAC_M2M_SZ 1 -+#define RG_PHY_LPBK_MSK 0x00000004 -+#define RG_PHY_LPBK_I_MSK 0xfffffffb -+#define RG_PHY_LPBK_SFT 2 -+#define RG_PHY_LPBK_HI 2 -+#define RG_PHY_LPBK_SZ 1 -+#define RG_LPBK_RX_EN_MSK 0x00000008 -+#define RG_LPBK_RX_EN_I_MSK 0xfffffff7 -+#define RG_LPBK_RX_EN_SFT 3 -+#define RG_LPBK_RX_EN_HI 3 -+#define RG_LPBK_RX_EN_SZ 1 -+#define EXT_MAC_MODE_MSK 0x00000010 -+#define EXT_MAC_MODE_I_MSK 0xffffffef -+#define EXT_MAC_MODE_SFT 4 -+#define EXT_MAC_MODE_HI 4 -+#define EXT_MAC_MODE_SZ 1 -+#define EXT_PHY_MODE_MSK 0x00000020 -+#define EXT_PHY_MODE_I_MSK 0xffffffdf -+#define EXT_PHY_MODE_SFT 5 -+#define EXT_PHY_MODE_HI 5 -+#define EXT_PHY_MODE_SZ 1 -+#define ASIC_TAG_MSK 0xff000000 -+#define ASIC_TAG_I_MSK 0x00ffffff -+#define ASIC_TAG_SFT 24 -+#define ASIC_TAG_HI 31 -+#define ASIC_TAG_SZ 8 -+#define HCI_SW_RST_MSK 0x00000001 -+#define HCI_SW_RST_I_MSK 0xfffffffe -+#define HCI_SW_RST_SFT 0 -+#define HCI_SW_RST_HI 0 -+#define HCI_SW_RST_SZ 1 -+#define CO_PROC_SW_RST_MSK 0x00000002 -+#define CO_PROC_SW_RST_I_MSK 0xfffffffd -+#define CO_PROC_SW_RST_SFT 1 -+#define CO_PROC_SW_RST_HI 1 -+#define CO_PROC_SW_RST_SZ 1 -+#define MTX_MISC_SW_RST_MSK 0x00000008 -+#define MTX_MISC_SW_RST_I_MSK 0xfffffff7 -+#define MTX_MISC_SW_RST_SFT 3 -+#define MTX_MISC_SW_RST_HI 3 -+#define MTX_MISC_SW_RST_SZ 1 -+#define MTX_QUE_SW_RST_MSK 0x00000010 -+#define MTX_QUE_SW_RST_I_MSK 0xffffffef -+#define MTX_QUE_SW_RST_SFT 4 -+#define MTX_QUE_SW_RST_HI 4 -+#define MTX_QUE_SW_RST_SZ 1 -+#define MTX_CHST_SW_RST_MSK 0x00000020 -+#define MTX_CHST_SW_RST_I_MSK 0xffffffdf -+#define MTX_CHST_SW_RST_SFT 5 -+#define MTX_CHST_SW_RST_HI 5 -+#define MTX_CHST_SW_RST_SZ 1 -+#define MTX_BCN_SW_RST_MSK 0x00000040 -+#define MTX_BCN_SW_RST_I_MSK 0xffffffbf -+#define MTX_BCN_SW_RST_SFT 6 -+#define MTX_BCN_SW_RST_HI 6 -+#define MTX_BCN_SW_RST_SZ 1 -+#define MRX_SW_RST_MSK 0x00000080 -+#define MRX_SW_RST_I_MSK 0xffffff7f -+#define MRX_SW_RST_SFT 7 -+#define MRX_SW_RST_HI 7 -+#define MRX_SW_RST_SZ 1 -+#define AMPDU_SW_RST_MSK 0x00000100 -+#define AMPDU_SW_RST_I_MSK 0xfffffeff -+#define AMPDU_SW_RST_SFT 8 -+#define AMPDU_SW_RST_HI 8 -+#define AMPDU_SW_RST_SZ 1 -+#define MMU_SW_RST_MSK 0x00000200 -+#define MMU_SW_RST_I_MSK 0xfffffdff -+#define MMU_SW_RST_SFT 9 -+#define MMU_SW_RST_HI 9 -+#define MMU_SW_RST_SZ 1 -+#define ID_MNG_SW_RST_MSK 0x00000800 -+#define ID_MNG_SW_RST_I_MSK 0xfffff7ff -+#define ID_MNG_SW_RST_SFT 11 -+#define ID_MNG_SW_RST_HI 11 -+#define ID_MNG_SW_RST_SZ 1 -+#define MBOX_SW_RST_MSK 0x00001000 -+#define MBOX_SW_RST_I_MSK 0xffffefff -+#define MBOX_SW_RST_SFT 12 -+#define MBOX_SW_RST_HI 12 -+#define MBOX_SW_RST_SZ 1 -+#define SCRT_SW_RST_MSK 0x00002000 -+#define SCRT_SW_RST_I_MSK 0xffffdfff -+#define SCRT_SW_RST_SFT 13 -+#define SCRT_SW_RST_HI 13 -+#define SCRT_SW_RST_SZ 1 -+#define MIC_SW_RST_MSK 0x00004000 -+#define MIC_SW_RST_I_MSK 0xffffbfff -+#define MIC_SW_RST_SFT 14 -+#define MIC_SW_RST_HI 14 -+#define MIC_SW_RST_SZ 1 -+#define CO_PROC_ENG_RST_MSK 0x00000002 -+#define CO_PROC_ENG_RST_I_MSK 0xfffffffd -+#define CO_PROC_ENG_RST_SFT 1 -+#define CO_PROC_ENG_RST_HI 1 -+#define CO_PROC_ENG_RST_SZ 1 -+#define MTX_MISC_ENG_RST_MSK 0x00000008 -+#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7 -+#define MTX_MISC_ENG_RST_SFT 3 -+#define MTX_MISC_ENG_RST_HI 3 -+#define MTX_MISC_ENG_RST_SZ 1 -+#define MTX_QUE_ENG_RST_MSK 0x00000010 -+#define MTX_QUE_ENG_RST_I_MSK 0xffffffef -+#define MTX_QUE_ENG_RST_SFT 4 -+#define MTX_QUE_ENG_RST_HI 4 -+#define MTX_QUE_ENG_RST_SZ 1 -+#define MTX_CHST_ENG_RST_MSK 0x00000020 -+#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf -+#define MTX_CHST_ENG_RST_SFT 5 -+#define MTX_CHST_ENG_RST_HI 5 -+#define MTX_CHST_ENG_RST_SZ 1 -+#define MTX_BCN_ENG_RST_MSK 0x00000040 -+#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf -+#define MTX_BCN_ENG_RST_SFT 6 -+#define MTX_BCN_ENG_RST_HI 6 -+#define MTX_BCN_ENG_RST_SZ 1 -+#define MRX_ENG_RST_MSK 0x00000080 -+#define MRX_ENG_RST_I_MSK 0xffffff7f -+#define MRX_ENG_RST_SFT 7 -+#define MRX_ENG_RST_HI 7 -+#define MRX_ENG_RST_SZ 1 -+#define AMPDU_ENG_RST_MSK 0x00000100 -+#define AMPDU_ENG_RST_I_MSK 0xfffffeff -+#define AMPDU_ENG_RST_SFT 8 -+#define AMPDU_ENG_RST_HI 8 -+#define AMPDU_ENG_RST_SZ 1 -+#define ID_MNG_ENG_RST_MSK 0x00004000 -+#define ID_MNG_ENG_RST_I_MSK 0xffffbfff -+#define ID_MNG_ENG_RST_SFT 14 -+#define ID_MNG_ENG_RST_HI 14 -+#define ID_MNG_ENG_RST_SZ 1 -+#define MBOX_ENG_RST_MSK 0x00008000 -+#define MBOX_ENG_RST_I_MSK 0xffff7fff -+#define MBOX_ENG_RST_SFT 15 -+#define MBOX_ENG_RST_HI 15 -+#define MBOX_ENG_RST_SZ 1 -+#define SCRT_ENG_RST_MSK 0x00010000 -+#define SCRT_ENG_RST_I_MSK 0xfffeffff -+#define SCRT_ENG_RST_SFT 16 -+#define SCRT_ENG_RST_HI 16 -+#define SCRT_ENG_RST_SZ 1 -+#define MIC_ENG_RST_MSK 0x00020000 -+#define MIC_ENG_RST_I_MSK 0xfffdffff -+#define MIC_ENG_RST_SFT 17 -+#define MIC_ENG_RST_HI 17 -+#define MIC_ENG_RST_SZ 1 -+#define CO_PROC_CSR_RST_MSK 0x00000002 -+#define CO_PROC_CSR_RST_I_MSK 0xfffffffd -+#define CO_PROC_CSR_RST_SFT 1 -+#define CO_PROC_CSR_RST_HI 1 -+#define CO_PROC_CSR_RST_SZ 1 -+#define MTX_MISC_CSR_RST_MSK 0x00000008 -+#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7 -+#define MTX_MISC_CSR_RST_SFT 3 -+#define MTX_MISC_CSR_RST_HI 3 -+#define MTX_MISC_CSR_RST_SZ 1 -+#define MTX_QUE0_CSR_RST_MSK 0x00000010 -+#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef -+#define MTX_QUE0_CSR_RST_SFT 4 -+#define MTX_QUE0_CSR_RST_HI 4 -+#define MTX_QUE0_CSR_RST_SZ 1 -+#define MTX_QUE1_CSR_RST_MSK 0x00000020 -+#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf -+#define MTX_QUE1_CSR_RST_SFT 5 -+#define MTX_QUE1_CSR_RST_HI 5 -+#define MTX_QUE1_CSR_RST_SZ 1 -+#define MTX_QUE2_CSR_RST_MSK 0x00000040 -+#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf -+#define MTX_QUE2_CSR_RST_SFT 6 -+#define MTX_QUE2_CSR_RST_HI 6 -+#define MTX_QUE2_CSR_RST_SZ 1 -+#define MTX_QUE3_CSR_RST_MSK 0x00000080 -+#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f -+#define MTX_QUE3_CSR_RST_SFT 7 -+#define MTX_QUE3_CSR_RST_HI 7 -+#define MTX_QUE3_CSR_RST_SZ 1 -+#define MTX_QUE4_CSR_RST_MSK 0x00000100 -+#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff -+#define MTX_QUE4_CSR_RST_SFT 8 -+#define MTX_QUE4_CSR_RST_HI 8 -+#define MTX_QUE4_CSR_RST_SZ 1 -+#define MTX_QUE5_CSR_RST_MSK 0x00000200 -+#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff -+#define MTX_QUE5_CSR_RST_SFT 9 -+#define MTX_QUE5_CSR_RST_HI 9 -+#define MTX_QUE5_CSR_RST_SZ 1 -+#define MRX_CSR_RST_MSK 0x00000400 -+#define MRX_CSR_RST_I_MSK 0xfffffbff -+#define MRX_CSR_RST_SFT 10 -+#define MRX_CSR_RST_HI 10 -+#define MRX_CSR_RST_SZ 1 -+#define AMPDU_CSR_RST_MSK 0x00000800 -+#define AMPDU_CSR_RST_I_MSK 0xfffff7ff -+#define AMPDU_CSR_RST_SFT 11 -+#define AMPDU_CSR_RST_HI 11 -+#define AMPDU_CSR_RST_SZ 1 -+#define SCRT_CSR_RST_MSK 0x00002000 -+#define SCRT_CSR_RST_I_MSK 0xffffdfff -+#define SCRT_CSR_RST_SFT 13 -+#define SCRT_CSR_RST_HI 13 -+#define SCRT_CSR_RST_SZ 1 -+#define ID_MNG_CSR_RST_MSK 0x00004000 -+#define ID_MNG_CSR_RST_I_MSK 0xffffbfff -+#define ID_MNG_CSR_RST_SFT 14 -+#define ID_MNG_CSR_RST_HI 14 -+#define ID_MNG_CSR_RST_SZ 1 -+#define MBOX_CSR_RST_MSK 0x00008000 -+#define MBOX_CSR_RST_I_MSK 0xffff7fff -+#define MBOX_CSR_RST_SFT 15 -+#define MBOX_CSR_RST_HI 15 -+#define MBOX_CSR_RST_SZ 1 -+#define HCI_CLK_EN_MSK 0x00000001 -+#define HCI_CLK_EN_I_MSK 0xfffffffe -+#define HCI_CLK_EN_SFT 0 -+#define HCI_CLK_EN_HI 0 -+#define HCI_CLK_EN_SZ 1 -+#define CO_PROC_CLK_EN_MSK 0x00000002 -+#define CO_PROC_CLK_EN_I_MSK 0xfffffffd -+#define CO_PROC_CLK_EN_SFT 1 -+#define CO_PROC_CLK_EN_HI 1 -+#define CO_PROC_CLK_EN_SZ 1 -+#define MTX_MISC_CLK_EN_MSK 0x00000008 -+#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7 -+#define MTX_MISC_CLK_EN_SFT 3 -+#define MTX_MISC_CLK_EN_HI 3 -+#define MTX_MISC_CLK_EN_SZ 1 -+#define MTX_QUE_CLK_EN_MSK 0x00000010 -+#define MTX_QUE_CLK_EN_I_MSK 0xffffffef -+#define MTX_QUE_CLK_EN_SFT 4 -+#define MTX_QUE_CLK_EN_HI 4 -+#define MTX_QUE_CLK_EN_SZ 1 -+#define MRX_CLK_EN_MSK 0x00000020 -+#define MRX_CLK_EN_I_MSK 0xffffffdf -+#define MRX_CLK_EN_SFT 5 -+#define MRX_CLK_EN_HI 5 -+#define MRX_CLK_EN_SZ 1 -+#define AMPDU_CLK_EN_MSK 0x00000040 -+#define AMPDU_CLK_EN_I_MSK 0xffffffbf -+#define AMPDU_CLK_EN_SFT 6 -+#define AMPDU_CLK_EN_HI 6 -+#define AMPDU_CLK_EN_SZ 1 -+#define MMU_CLK_EN_MSK 0x00000080 -+#define MMU_CLK_EN_I_MSK 0xffffff7f -+#define MMU_CLK_EN_SFT 7 -+#define MMU_CLK_EN_HI 7 -+#define MMU_CLK_EN_SZ 1 -+#define ID_MNG_CLK_EN_MSK 0x00000200 -+#define ID_MNG_CLK_EN_I_MSK 0xfffffdff -+#define ID_MNG_CLK_EN_SFT 9 -+#define ID_MNG_CLK_EN_HI 9 -+#define ID_MNG_CLK_EN_SZ 1 -+#define MBOX_CLK_EN_MSK 0x00000400 -+#define MBOX_CLK_EN_I_MSK 0xfffffbff -+#define MBOX_CLK_EN_SFT 10 -+#define MBOX_CLK_EN_HI 10 -+#define MBOX_CLK_EN_SZ 1 -+#define SCRT_CLK_EN_MSK 0x00000800 -+#define SCRT_CLK_EN_I_MSK 0xfffff7ff -+#define SCRT_CLK_EN_SFT 11 -+#define SCRT_CLK_EN_HI 11 -+#define SCRT_CLK_EN_SZ 1 -+#define MIC_CLK_EN_MSK 0x00001000 -+#define MIC_CLK_EN_I_MSK 0xffffefff -+#define MIC_CLK_EN_SFT 12 -+#define MIC_CLK_EN_HI 12 -+#define MIC_CLK_EN_SZ 1 -+#define MIB_CLK_EN_MSK 0x00002000 -+#define MIB_CLK_EN_I_MSK 0xffffdfff -+#define MIB_CLK_EN_SFT 13 -+#define MIB_CLK_EN_HI 13 -+#define MIB_CLK_EN_SZ 1 -+#define HCI_ENG_CLK_EN_MSK 0x00000001 -+#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe -+#define HCI_ENG_CLK_EN_SFT 0 -+#define HCI_ENG_CLK_EN_HI 0 -+#define HCI_ENG_CLK_EN_SZ 1 -+#define CO_PROC_ENG_CLK_EN_MSK 0x00000002 -+#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd -+#define CO_PROC_ENG_CLK_EN_SFT 1 -+#define CO_PROC_ENG_CLK_EN_HI 1 -+#define CO_PROC_ENG_CLK_EN_SZ 1 -+#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008 -+#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7 -+#define MTX_MISC_ENG_CLK_EN_SFT 3 -+#define MTX_MISC_ENG_CLK_EN_HI 3 -+#define MTX_MISC_ENG_CLK_EN_SZ 1 -+#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010 -+#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef -+#define MTX_QUE_ENG_CLK_EN_SFT 4 -+#define MTX_QUE_ENG_CLK_EN_HI 4 -+#define MTX_QUE_ENG_CLK_EN_SZ 1 -+#define MRX_ENG_CLK_EN_MSK 0x00000020 -+#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf -+#define MRX_ENG_CLK_EN_SFT 5 -+#define MRX_ENG_CLK_EN_HI 5 -+#define MRX_ENG_CLK_EN_SZ 1 -+#define AMPDU_ENG_CLK_EN_MSK 0x00000040 -+#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf -+#define AMPDU_ENG_CLK_EN_SFT 6 -+#define AMPDU_ENG_CLK_EN_HI 6 -+#define AMPDU_ENG_CLK_EN_SZ 1 -+#define ID_MNG_ENG_CLK_EN_MSK 0x00001000 -+#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff -+#define ID_MNG_ENG_CLK_EN_SFT 12 -+#define ID_MNG_ENG_CLK_EN_HI 12 -+#define ID_MNG_ENG_CLK_EN_SZ 1 -+#define MBOX_ENG_CLK_EN_MSK 0x00002000 -+#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff -+#define MBOX_ENG_CLK_EN_SFT 13 -+#define MBOX_ENG_CLK_EN_HI 13 -+#define MBOX_ENG_CLK_EN_SZ 1 -+#define SCRT_ENG_CLK_EN_MSK 0x00004000 -+#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff -+#define SCRT_ENG_CLK_EN_SFT 14 -+#define SCRT_ENG_CLK_EN_HI 14 -+#define SCRT_ENG_CLK_EN_SZ 1 -+#define MIC_ENG_CLK_EN_MSK 0x00008000 -+#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff -+#define MIC_ENG_CLK_EN_SFT 15 -+#define MIC_ENG_CLK_EN_HI 15 -+#define MIC_ENG_CLK_EN_SZ 1 -+#define CO_PROC_CSR_CLK_EN_MSK 0x00000002 -+#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd -+#define CO_PROC_CSR_CLK_EN_SFT 1 -+#define CO_PROC_CSR_CLK_EN_HI 1 -+#define CO_PROC_CSR_CLK_EN_SZ 1 -+#define MRX_CSR_CLK_EN_MSK 0x00000400 -+#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff -+#define MRX_CSR_CLK_EN_SFT 10 -+#define MRX_CSR_CLK_EN_HI 10 -+#define MRX_CSR_CLK_EN_SZ 1 -+#define AMPDU_CSR_CLK_EN_MSK 0x00000800 -+#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff -+#define AMPDU_CSR_CLK_EN_SFT 11 -+#define AMPDU_CSR_CLK_EN_HI 11 -+#define AMPDU_CSR_CLK_EN_SZ 1 -+#define SCRT_CSR_CLK_EN_MSK 0x00002000 -+#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff -+#define SCRT_CSR_CLK_EN_SFT 13 -+#define SCRT_CSR_CLK_EN_HI 13 -+#define SCRT_CSR_CLK_EN_SZ 1 -+#define ID_MNG_CSR_CLK_EN_MSK 0x00004000 -+#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff -+#define ID_MNG_CSR_CLK_EN_SFT 14 -+#define ID_MNG_CSR_CLK_EN_HI 14 -+#define ID_MNG_CSR_CLK_EN_SZ 1 -+#define MBOX_CSR_CLK_EN_MSK 0x00008000 -+#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff -+#define MBOX_CSR_CLK_EN_SFT 15 -+#define MBOX_CSR_CLK_EN_HI 15 -+#define MBOX_CSR_CLK_EN_SZ 1 -+#define OP_MODE_MSK 0x00000003 -+#define OP_MODE_I_MSK 0xfffffffc -+#define OP_MODE_SFT 0 -+#define OP_MODE_HI 1 -+#define OP_MODE_SZ 2 -+#define HT_MODE_MSK 0x0000000c -+#define HT_MODE_I_MSK 0xfffffff3 -+#define HT_MODE_SFT 2 -+#define HT_MODE_HI 3 -+#define HT_MODE_SZ 2 -+#define QOS_EN_MSK 0x00000010 -+#define QOS_EN_I_MSK 0xffffffef -+#define QOS_EN_SFT 4 -+#define QOS_EN_HI 4 -+#define QOS_EN_SZ 1 -+#define PB_OFFSET_MSK 0x0000ff00 -+#define PB_OFFSET_I_MSK 0xffff00ff -+#define PB_OFFSET_SFT 8 -+#define PB_OFFSET_HI 15 -+#define PB_OFFSET_SZ 8 -+#define SNIFFER_MODE_MSK 0x00010000 -+#define SNIFFER_MODE_I_MSK 0xfffeffff -+#define SNIFFER_MODE_SFT 16 -+#define SNIFFER_MODE_HI 16 -+#define SNIFFER_MODE_SZ 1 -+#define DUP_FLT_MSK 0x00020000 -+#define DUP_FLT_I_MSK 0xfffdffff -+#define DUP_FLT_SFT 17 -+#define DUP_FLT_HI 17 -+#define DUP_FLT_SZ 1 -+#define TX_PKT_RSVD_MSK 0x001c0000 -+#define TX_PKT_RSVD_I_MSK 0xffe3ffff -+#define TX_PKT_RSVD_SFT 18 -+#define TX_PKT_RSVD_HI 20 -+#define TX_PKT_RSVD_SZ 3 -+#define AMPDU_SNIFFER_MSK 0x00200000 -+#define AMPDU_SNIFFER_I_MSK 0xffdfffff -+#define AMPDU_SNIFFER_SFT 21 -+#define AMPDU_SNIFFER_HI 21 -+#define AMPDU_SNIFFER_SZ 1 -+#define REASON_TRAP0_MSK 0xffffffff -+#define REASON_TRAP0_I_MSK 0x00000000 -+#define REASON_TRAP0_SFT 0 -+#define REASON_TRAP0_HI 31 -+#define REASON_TRAP0_SZ 32 -+#define REASON_TRAP1_MSK 0xffffffff -+#define REASON_TRAP1_I_MSK 0x00000000 -+#define REASON_TRAP1_SFT 0 -+#define REASON_TRAP1_HI 31 -+#define REASON_TRAP1_SZ 32 -+#define BSSID_31_0_MSK 0xffffffff -+#define BSSID_31_0_I_MSK 0x00000000 -+#define BSSID_31_0_SFT 0 -+#define BSSID_31_0_HI 31 -+#define BSSID_31_0_SZ 32 -+#define BSSID_47_32_MSK 0x0000ffff -+#define BSSID_47_32_I_MSK 0xffff0000 -+#define BSSID_47_32_SFT 0 -+#define BSSID_47_32_HI 15 -+#define BSSID_47_32_SZ 16 -+#define SCRT_STATE_MSK 0x0000000f -+#define SCRT_STATE_I_MSK 0xfffffff0 -+#define SCRT_STATE_SFT 0 -+#define SCRT_STATE_HI 3 -+#define SCRT_STATE_SZ 4 -+#define STA_MAC_31_0_MSK 0xffffffff -+#define STA_MAC_31_0_I_MSK 0x00000000 -+#define STA_MAC_31_0_SFT 0 -+#define STA_MAC_31_0_HI 31 -+#define STA_MAC_31_0_SZ 32 -+#define STA_MAC_47_32_MSK 0x0000ffff -+#define STA_MAC_47_32_I_MSK 0xffff0000 -+#define STA_MAC_47_32_SFT 0 -+#define STA_MAC_47_32_HI 15 -+#define STA_MAC_47_32_SZ 16 -+#define PAIR_SCRT_MSK 0x00000007 -+#define PAIR_SCRT_I_MSK 0xfffffff8 -+#define PAIR_SCRT_SFT 0 -+#define PAIR_SCRT_HI 2 -+#define PAIR_SCRT_SZ 3 -+#define GRP_SCRT_MSK 0x00000038 -+#define GRP_SCRT_I_MSK 0xffffffc7 -+#define GRP_SCRT_SFT 3 -+#define GRP_SCRT_HI 5 -+#define GRP_SCRT_SZ 3 -+#define SCRT_PKT_ID_MSK 0x00001fc0 -+#define SCRT_PKT_ID_I_MSK 0xffffe03f -+#define SCRT_PKT_ID_SFT 6 -+#define SCRT_PKT_ID_HI 12 -+#define SCRT_PKT_ID_SZ 7 -+#define SCRT_RPLY_IGNORE_MSK 0x00010000 -+#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff -+#define SCRT_RPLY_IGNORE_SFT 16 -+#define SCRT_RPLY_IGNORE_HI 16 -+#define SCRT_RPLY_IGNORE_SZ 1 -+#define COEXIST_EN_MSK 0x00000001 -+#define COEXIST_EN_I_MSK 0xfffffffe -+#define COEXIST_EN_SFT 0 -+#define COEXIST_EN_HI 0 -+#define COEXIST_EN_SZ 1 -+#define WIRE_MODE_MSK 0x0000000e -+#define WIRE_MODE_I_MSK 0xfffffff1 -+#define WIRE_MODE_SFT 1 -+#define WIRE_MODE_HI 3 -+#define WIRE_MODE_SZ 3 -+#define WL_RX_PRI_MSK 0x00000010 -+#define WL_RX_PRI_I_MSK 0xffffffef -+#define WL_RX_PRI_SFT 4 -+#define WL_RX_PRI_HI 4 -+#define WL_RX_PRI_SZ 1 -+#define WL_TX_PRI_MSK 0x00000020 -+#define WL_TX_PRI_I_MSK 0xffffffdf -+#define WL_TX_PRI_SFT 5 -+#define WL_TX_PRI_HI 5 -+#define WL_TX_PRI_SZ 1 -+#define GURAN_USE_EN_MSK 0x00000100 -+#define GURAN_USE_EN_I_MSK 0xfffffeff -+#define GURAN_USE_EN_SFT 8 -+#define GURAN_USE_EN_HI 8 -+#define GURAN_USE_EN_SZ 1 -+#define GURAN_USE_CTRL_MSK 0x00000200 -+#define GURAN_USE_CTRL_I_MSK 0xfffffdff -+#define GURAN_USE_CTRL_SFT 9 -+#define GURAN_USE_CTRL_HI 9 -+#define GURAN_USE_CTRL_SZ 1 -+#define BEACON_TIMEOUT_EN_MSK 0x00000400 -+#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff -+#define BEACON_TIMEOUT_EN_SFT 10 -+#define BEACON_TIMEOUT_EN_HI 10 -+#define BEACON_TIMEOUT_EN_SZ 1 -+#define WLAN_ACT_POL_MSK 0x00000800 -+#define WLAN_ACT_POL_I_MSK 0xfffff7ff -+#define WLAN_ACT_POL_SFT 11 -+#define WLAN_ACT_POL_HI 11 -+#define WLAN_ACT_POL_SZ 1 -+#define DUAL_ANT_EN_MSK 0x00001000 -+#define DUAL_ANT_EN_I_MSK 0xffffefff -+#define DUAL_ANT_EN_SFT 12 -+#define DUAL_ANT_EN_HI 12 -+#define DUAL_ANT_EN_SZ 1 -+#define TRSW_PHY_POL_MSK 0x00010000 -+#define TRSW_PHY_POL_I_MSK 0xfffeffff -+#define TRSW_PHY_POL_SFT 16 -+#define TRSW_PHY_POL_HI 16 -+#define TRSW_PHY_POL_SZ 1 -+#define WIFI_TX_SW_POL_MSK 0x00020000 -+#define WIFI_TX_SW_POL_I_MSK 0xfffdffff -+#define WIFI_TX_SW_POL_SFT 17 -+#define WIFI_TX_SW_POL_HI 17 -+#define WIFI_TX_SW_POL_SZ 1 -+#define WIFI_RX_SW_POL_MSK 0x00040000 -+#define WIFI_RX_SW_POL_I_MSK 0xfffbffff -+#define WIFI_RX_SW_POL_SFT 18 -+#define WIFI_RX_SW_POL_HI 18 -+#define WIFI_RX_SW_POL_SZ 1 -+#define BT_SW_POL_MSK 0x00080000 -+#define BT_SW_POL_I_MSK 0xfff7ffff -+#define BT_SW_POL_SFT 19 -+#define BT_SW_POL_HI 19 -+#define BT_SW_POL_SZ 1 -+#define BT_PRI_SMP_TIME_MSK 0x000000ff -+#define BT_PRI_SMP_TIME_I_MSK 0xffffff00 -+#define BT_PRI_SMP_TIME_SFT 0 -+#define BT_PRI_SMP_TIME_HI 7 -+#define BT_PRI_SMP_TIME_SZ 8 -+#define BT_STA_SMP_TIME_MSK 0x0000ff00 -+#define BT_STA_SMP_TIME_I_MSK 0xffff00ff -+#define BT_STA_SMP_TIME_SFT 8 -+#define BT_STA_SMP_TIME_HI 15 -+#define BT_STA_SMP_TIME_SZ 8 -+#define BEACON_TIMEOUT_MSK 0x00ff0000 -+#define BEACON_TIMEOUT_I_MSK 0xff00ffff -+#define BEACON_TIMEOUT_SFT 16 -+#define BEACON_TIMEOUT_HI 23 -+#define BEACON_TIMEOUT_SZ 8 -+#define WLAN_REMAIN_TIME_MSK 0xff000000 -+#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff -+#define WLAN_REMAIN_TIME_SFT 24 -+#define WLAN_REMAIN_TIME_HI 31 -+#define WLAN_REMAIN_TIME_SZ 8 -+#define SW_MANUAL_EN_MSK 0x00000001 -+#define SW_MANUAL_EN_I_MSK 0xfffffffe -+#define SW_MANUAL_EN_SFT 0 -+#define SW_MANUAL_EN_HI 0 -+#define SW_MANUAL_EN_SZ 1 -+#define SW_WL_TX_MSK 0x00000002 -+#define SW_WL_TX_I_MSK 0xfffffffd -+#define SW_WL_TX_SFT 1 -+#define SW_WL_TX_HI 1 -+#define SW_WL_TX_SZ 1 -+#define SW_WL_RX_MSK 0x00000004 -+#define SW_WL_RX_I_MSK 0xfffffffb -+#define SW_WL_RX_SFT 2 -+#define SW_WL_RX_HI 2 -+#define SW_WL_RX_SZ 1 -+#define SW_BT_TRX_MSK 0x00000008 -+#define SW_BT_TRX_I_MSK 0xfffffff7 -+#define SW_BT_TRX_SFT 3 -+#define SW_BT_TRX_HI 3 -+#define SW_BT_TRX_SZ 1 -+#define BT_TXBAR_MANUAL_EN_MSK 0x00000010 -+#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef -+#define BT_TXBAR_MANUAL_EN_SFT 4 -+#define BT_TXBAR_MANUAL_EN_HI 4 -+#define BT_TXBAR_MANUAL_EN_SZ 1 -+#define BT_TXBAR_SET_MSK 0x00000020 -+#define BT_TXBAR_SET_I_MSK 0xffffffdf -+#define BT_TXBAR_SET_SFT 5 -+#define BT_TXBAR_SET_HI 5 -+#define BT_TXBAR_SET_SZ 1 -+#define BT_BUSY_MANUAL_EN_MSK 0x00000100 -+#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff -+#define BT_BUSY_MANUAL_EN_SFT 8 -+#define BT_BUSY_MANUAL_EN_HI 8 -+#define BT_BUSY_MANUAL_EN_SZ 1 -+#define BT_BUSY_SET_MSK 0x00000200 -+#define BT_BUSY_SET_I_MSK 0xfffffdff -+#define BT_BUSY_SET_SFT 9 -+#define BT_BUSY_SET_HI 9 -+#define BT_BUSY_SET_SZ 1 -+#define G0_PKT_CLS_MIB_EN_MSK 0x00000004 -+#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb -+#define G0_PKT_CLS_MIB_EN_SFT 2 -+#define G0_PKT_CLS_MIB_EN_HI 2 -+#define G0_PKT_CLS_MIB_EN_SZ 1 -+#define G0_PKT_CLS_ONGOING_MSK 0x00000008 -+#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7 -+#define G0_PKT_CLS_ONGOING_SFT 3 -+#define G0_PKT_CLS_ONGOING_HI 3 -+#define G0_PKT_CLS_ONGOING_SZ 1 -+#define G1_PKT_CLS_MIB_EN_MSK 0x00000010 -+#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef -+#define G1_PKT_CLS_MIB_EN_SFT 4 -+#define G1_PKT_CLS_MIB_EN_HI 4 -+#define G1_PKT_CLS_MIB_EN_SZ 1 -+#define G1_PKT_CLS_ONGOING_MSK 0x00000020 -+#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf -+#define G1_PKT_CLS_ONGOING_SFT 5 -+#define G1_PKT_CLS_ONGOING_HI 5 -+#define G1_PKT_CLS_ONGOING_SZ 1 -+#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040 -+#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf -+#define Q0_PKT_CLS_MIB_EN_SFT 6 -+#define Q0_PKT_CLS_MIB_EN_HI 6 -+#define Q0_PKT_CLS_MIB_EN_SZ 1 -+#define Q0_PKT_CLS_ONGOING_MSK 0x00000080 -+#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f -+#define Q0_PKT_CLS_ONGOING_SFT 7 -+#define Q0_PKT_CLS_ONGOING_HI 7 -+#define Q0_PKT_CLS_ONGOING_SZ 1 -+#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100 -+#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff -+#define Q1_PKT_CLS_MIB_EN_SFT 8 -+#define Q1_PKT_CLS_MIB_EN_HI 8 -+#define Q1_PKT_CLS_MIB_EN_SZ 1 -+#define Q1_PKT_CLS_ONGOING_MSK 0x00000200 -+#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff -+#define Q1_PKT_CLS_ONGOING_SFT 9 -+#define Q1_PKT_CLS_ONGOING_HI 9 -+#define Q1_PKT_CLS_ONGOING_SZ 1 -+#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400 -+#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff -+#define Q2_PKT_CLS_MIB_EN_SFT 10 -+#define Q2_PKT_CLS_MIB_EN_HI 10 -+#define Q2_PKT_CLS_MIB_EN_SZ 1 -+#define Q2_PKT_CLS_ONGOING_MSK 0x00000800 -+#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff -+#define Q2_PKT_CLS_ONGOING_SFT 11 -+#define Q2_PKT_CLS_ONGOING_HI 11 -+#define Q2_PKT_CLS_ONGOING_SZ 1 -+#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000 -+#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff -+#define Q3_PKT_CLS_MIB_EN_SFT 12 -+#define Q3_PKT_CLS_MIB_EN_HI 12 -+#define Q3_PKT_CLS_MIB_EN_SZ 1 -+#define Q3_PKT_CLS_ONGOING_MSK 0x00002000 -+#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff -+#define Q3_PKT_CLS_ONGOING_SFT 13 -+#define Q3_PKT_CLS_ONGOING_HI 13 -+#define Q3_PKT_CLS_ONGOING_SZ 1 -+#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000 -+#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff -+#define SCRT_PKT_CLS_MIB_EN_SFT 14 -+#define SCRT_PKT_CLS_MIB_EN_HI 14 -+#define SCRT_PKT_CLS_MIB_EN_SZ 1 -+#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000 -+#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff -+#define SCRT_PKT_CLS_ONGOING_SFT 15 -+#define SCRT_PKT_CLS_ONGOING_HI 15 -+#define SCRT_PKT_CLS_ONGOING_SZ 1 -+#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000 -+#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff -+#define MISC_PKT_CLS_MIB_EN_SFT 16 -+#define MISC_PKT_CLS_MIB_EN_HI 16 -+#define MISC_PKT_CLS_MIB_EN_SZ 1 -+#define MISC_PKT_CLS_ONGOING_MSK 0x00020000 -+#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff -+#define MISC_PKT_CLS_ONGOING_SFT 17 -+#define MISC_PKT_CLS_ONGOING_HI 17 -+#define MISC_PKT_CLS_ONGOING_SZ 1 -+#define MTX_WSID0_SUCC_MSK 0x0000ffff -+#define MTX_WSID0_SUCC_I_MSK 0xffff0000 -+#define MTX_WSID0_SUCC_SFT 0 -+#define MTX_WSID0_SUCC_HI 15 -+#define MTX_WSID0_SUCC_SZ 16 -+#define MTX_WSID0_FRM_MSK 0x0000ffff -+#define MTX_WSID0_FRM_I_MSK 0xffff0000 -+#define MTX_WSID0_FRM_SFT 0 -+#define MTX_WSID0_FRM_HI 15 -+#define MTX_WSID0_FRM_SZ 16 -+#define MTX_WSID0_RETRY_MSK 0x0000ffff -+#define MTX_WSID0_RETRY_I_MSK 0xffff0000 -+#define MTX_WSID0_RETRY_SFT 0 -+#define MTX_WSID0_RETRY_HI 15 -+#define MTX_WSID0_RETRY_SZ 16 -+#define MTX_WSID0_TOTAL_MSK 0x0000ffff -+#define MTX_WSID0_TOTAL_I_MSK 0xffff0000 -+#define MTX_WSID0_TOTAL_SFT 0 -+#define MTX_WSID0_TOTAL_HI 15 -+#define MTX_WSID0_TOTAL_SZ 16 -+#define MTX_GRP_MSK 0x000fffff -+#define MTX_GRP_I_MSK 0xfff00000 -+#define MTX_GRP_SFT 0 -+#define MTX_GRP_HI 19 -+#define MTX_GRP_SZ 20 -+#define MTX_FAIL_MSK 0x0000ffff -+#define MTX_FAIL_I_MSK 0xffff0000 -+#define MTX_FAIL_SFT 0 -+#define MTX_FAIL_HI 15 -+#define MTX_FAIL_SZ 16 -+#define MTX_RETRY_MSK 0x000fffff -+#define MTX_RETRY_I_MSK 0xfff00000 -+#define MTX_RETRY_SFT 0 -+#define MTX_RETRY_HI 19 -+#define MTX_RETRY_SZ 20 -+#define MTX_MULTI_RETRY_MSK 0x000fffff -+#define MTX_MULTI_RETRY_I_MSK 0xfff00000 -+#define MTX_MULTI_RETRY_SFT 0 -+#define MTX_MULTI_RETRY_HI 19 -+#define MTX_MULTI_RETRY_SZ 20 -+#define MTX_RTS_SUCC_MSK 0x0000ffff -+#define MTX_RTS_SUCC_I_MSK 0xffff0000 -+#define MTX_RTS_SUCC_SFT 0 -+#define MTX_RTS_SUCC_HI 15 -+#define MTX_RTS_SUCC_SZ 16 -+#define MTX_RTS_FAIL_MSK 0x0000ffff -+#define MTX_RTS_FAIL_I_MSK 0xffff0000 -+#define MTX_RTS_FAIL_SFT 0 -+#define MTX_RTS_FAIL_HI 15 -+#define MTX_RTS_FAIL_SZ 16 -+#define MTX_ACK_FAIL_MSK 0x0000ffff -+#define MTX_ACK_FAIL_I_MSK 0xffff0000 -+#define MTX_ACK_FAIL_SFT 0 -+#define MTX_ACK_FAIL_HI 15 -+#define MTX_ACK_FAIL_SZ 16 -+#define MTX_FRM_MSK 0x000fffff -+#define MTX_FRM_I_MSK 0xfff00000 -+#define MTX_FRM_SFT 0 -+#define MTX_FRM_HI 19 -+#define MTX_FRM_SZ 20 -+#define MTX_ACK_TX_MSK 0x0000ffff -+#define MTX_ACK_TX_I_MSK 0xffff0000 -+#define MTX_ACK_TX_SFT 0 -+#define MTX_ACK_TX_HI 15 -+#define MTX_ACK_TX_SZ 16 -+#define MTX_CTS_TX_MSK 0x0000ffff -+#define MTX_CTS_TX_I_MSK 0xffff0000 -+#define MTX_CTS_TX_SFT 0 -+#define MTX_CTS_TX_HI 15 -+#define MTX_CTS_TX_SZ 16 -+#define MRX_DUP_MSK 0x0000ffff -+#define MRX_DUP_I_MSK 0xffff0000 -+#define MRX_DUP_SFT 0 -+#define MRX_DUP_HI 15 -+#define MRX_DUP_SZ 16 -+#define MRX_FRG_MSK 0x000fffff -+#define MRX_FRG_I_MSK 0xfff00000 -+#define MRX_FRG_SFT 0 -+#define MRX_FRG_HI 19 -+#define MRX_FRG_SZ 20 -+#define MRX_GRP_MSK 0x000fffff -+#define MRX_GRP_I_MSK 0xfff00000 -+#define MRX_GRP_SFT 0 -+#define MRX_GRP_HI 19 -+#define MRX_GRP_SZ 20 -+#define MRX_FCS_ERR_MSK 0x0000ffff -+#define MRX_FCS_ERR_I_MSK 0xffff0000 -+#define MRX_FCS_ERR_SFT 0 -+#define MRX_FCS_ERR_HI 15 -+#define MRX_FCS_ERR_SZ 16 -+#define MRX_FCS_SUC_MSK 0x0000ffff -+#define MRX_FCS_SUC_I_MSK 0xffff0000 -+#define MRX_FCS_SUC_SFT 0 -+#define MRX_FCS_SUC_HI 15 -+#define MRX_FCS_SUC_SZ 16 -+#define MRX_MISS_MSK 0x0000ffff -+#define MRX_MISS_I_MSK 0xffff0000 -+#define MRX_MISS_SFT 0 -+#define MRX_MISS_HI 15 -+#define MRX_MISS_SZ 16 -+#define MRX_ALC_FAIL_MSK 0x0000ffff -+#define MRX_ALC_FAIL_I_MSK 0xffff0000 -+#define MRX_ALC_FAIL_SFT 0 -+#define MRX_ALC_FAIL_HI 15 -+#define MRX_ALC_FAIL_SZ 16 -+#define MRX_DAT_NTF_MSK 0x0000ffff -+#define MRX_DAT_NTF_I_MSK 0xffff0000 -+#define MRX_DAT_NTF_SFT 0 -+#define MRX_DAT_NTF_HI 15 -+#define MRX_DAT_NTF_SZ 16 -+#define MRX_RTS_NTF_MSK 0x0000ffff -+#define MRX_RTS_NTF_I_MSK 0xffff0000 -+#define MRX_RTS_NTF_SFT 0 -+#define MRX_RTS_NTF_HI 15 -+#define MRX_RTS_NTF_SZ 16 -+#define MRX_CTS_NTF_MSK 0x0000ffff -+#define MRX_CTS_NTF_I_MSK 0xffff0000 -+#define MRX_CTS_NTF_SFT 0 -+#define MRX_CTS_NTF_HI 15 -+#define MRX_CTS_NTF_SZ 16 -+#define MRX_ACK_NTF_MSK 0x0000ffff -+#define MRX_ACK_NTF_I_MSK 0xffff0000 -+#define MRX_ACK_NTF_SFT 0 -+#define MRX_ACK_NTF_HI 15 -+#define MRX_ACK_NTF_SZ 16 -+#define MRX_BA_NTF_MSK 0x0000ffff -+#define MRX_BA_NTF_I_MSK 0xffff0000 -+#define MRX_BA_NTF_SFT 0 -+#define MRX_BA_NTF_HI 15 -+#define MRX_BA_NTF_SZ 16 -+#define MRX_DATA_NTF_MSK 0x0000ffff -+#define MRX_DATA_NTF_I_MSK 0xffff0000 -+#define MRX_DATA_NTF_SFT 0 -+#define MRX_DATA_NTF_HI 15 -+#define MRX_DATA_NTF_SZ 16 -+#define MRX_MNG_NTF_MSK 0x0000ffff -+#define MRX_MNG_NTF_I_MSK 0xffff0000 -+#define MRX_MNG_NTF_SFT 0 -+#define MRX_MNG_NTF_HI 15 -+#define MRX_MNG_NTF_SZ 16 -+#define MRX_DAT_CRC_NTF_MSK 0x0000ffff -+#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000 -+#define MRX_DAT_CRC_NTF_SFT 0 -+#define MRX_DAT_CRC_NTF_HI 15 -+#define MRX_DAT_CRC_NTF_SZ 16 -+#define MRX_BAR_NTF_MSK 0x0000ffff -+#define MRX_BAR_NTF_I_MSK 0xffff0000 -+#define MRX_BAR_NTF_SFT 0 -+#define MRX_BAR_NTF_HI 15 -+#define MRX_BAR_NTF_SZ 16 -+#define MRX_MB_MISS_MSK 0x0000ffff -+#define MRX_MB_MISS_I_MSK 0xffff0000 -+#define MRX_MB_MISS_SFT 0 -+#define MRX_MB_MISS_HI 15 -+#define MRX_MB_MISS_SZ 16 -+#define MRX_NIDLE_MISS_MSK 0x0000ffff -+#define MRX_NIDLE_MISS_I_MSK 0xffff0000 -+#define MRX_NIDLE_MISS_SFT 0 -+#define MRX_NIDLE_MISS_HI 15 -+#define MRX_NIDLE_MISS_SZ 16 -+#define MRX_CSR_NTF_MSK 0x0000ffff -+#define MRX_CSR_NTF_I_MSK 0xffff0000 -+#define MRX_CSR_NTF_SFT 0 -+#define MRX_CSR_NTF_HI 15 -+#define MRX_CSR_NTF_SZ 16 -+#define DBG_Q0_SUCC_MSK 0x0000ffff -+#define DBG_Q0_SUCC_I_MSK 0xffff0000 -+#define DBG_Q0_SUCC_SFT 0 -+#define DBG_Q0_SUCC_HI 15 -+#define DBG_Q0_SUCC_SZ 16 -+#define DBG_Q0_FAIL_MSK 0x0000ffff -+#define DBG_Q0_FAIL_I_MSK 0xffff0000 -+#define DBG_Q0_FAIL_SFT 0 -+#define DBG_Q0_FAIL_HI 15 -+#define DBG_Q0_FAIL_SZ 16 -+#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff -+#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000 -+#define DBG_Q0_ACK_SUCC_SFT 0 -+#define DBG_Q0_ACK_SUCC_HI 15 -+#define DBG_Q0_ACK_SUCC_SZ 16 -+#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff -+#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000 -+#define DBG_Q0_ACK_FAIL_SFT 0 -+#define DBG_Q0_ACK_FAIL_HI 15 -+#define DBG_Q0_ACK_FAIL_SZ 16 -+#define DBG_Q1_SUCC_MSK 0x0000ffff -+#define DBG_Q1_SUCC_I_MSK 0xffff0000 -+#define DBG_Q1_SUCC_SFT 0 -+#define DBG_Q1_SUCC_HI 15 -+#define DBG_Q1_SUCC_SZ 16 -+#define DBG_Q1_FAIL_MSK 0x0000ffff -+#define DBG_Q1_FAIL_I_MSK 0xffff0000 -+#define DBG_Q1_FAIL_SFT 0 -+#define DBG_Q1_FAIL_HI 15 -+#define DBG_Q1_FAIL_SZ 16 -+#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff -+#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000 -+#define DBG_Q1_ACK_SUCC_SFT 0 -+#define DBG_Q1_ACK_SUCC_HI 15 -+#define DBG_Q1_ACK_SUCC_SZ 16 -+#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff -+#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000 -+#define DBG_Q1_ACK_FAIL_SFT 0 -+#define DBG_Q1_ACK_FAIL_HI 15 -+#define DBG_Q1_ACK_FAIL_SZ 16 -+#define DBG_Q2_SUCC_MSK 0x0000ffff -+#define DBG_Q2_SUCC_I_MSK 0xffff0000 -+#define DBG_Q2_SUCC_SFT 0 -+#define DBG_Q2_SUCC_HI 15 -+#define DBG_Q2_SUCC_SZ 16 -+#define DBG_Q2_FAIL_MSK 0x0000ffff -+#define DBG_Q2_FAIL_I_MSK 0xffff0000 -+#define DBG_Q2_FAIL_SFT 0 -+#define DBG_Q2_FAIL_HI 15 -+#define DBG_Q2_FAIL_SZ 16 -+#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff -+#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000 -+#define DBG_Q2_ACK_SUCC_SFT 0 -+#define DBG_Q2_ACK_SUCC_HI 15 -+#define DBG_Q2_ACK_SUCC_SZ 16 -+#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff -+#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000 -+#define DBG_Q2_ACK_FAIL_SFT 0 -+#define DBG_Q2_ACK_FAIL_HI 15 -+#define DBG_Q2_ACK_FAIL_SZ 16 -+#define DBG_Q3_SUCC_MSK 0x0000ffff -+#define DBG_Q3_SUCC_I_MSK 0xffff0000 -+#define DBG_Q3_SUCC_SFT 0 -+#define DBG_Q3_SUCC_HI 15 -+#define DBG_Q3_SUCC_SZ 16 -+#define DBG_Q3_FAIL_MSK 0x0000ffff -+#define DBG_Q3_FAIL_I_MSK 0xffff0000 -+#define DBG_Q3_FAIL_SFT 0 -+#define DBG_Q3_FAIL_HI 15 -+#define DBG_Q3_FAIL_SZ 16 -+#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff -+#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000 -+#define DBG_Q3_ACK_SUCC_SFT 0 -+#define DBG_Q3_ACK_SUCC_HI 15 -+#define DBG_Q3_ACK_SUCC_SZ 16 -+#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff -+#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000 -+#define DBG_Q3_ACK_FAIL_SFT 0 -+#define DBG_Q3_ACK_FAIL_HI 15 -+#define DBG_Q3_ACK_FAIL_SZ 16 -+#define SCRT_TKIP_CERR_MSK 0x000fffff -+#define SCRT_TKIP_CERR_I_MSK 0xfff00000 -+#define SCRT_TKIP_CERR_SFT 0 -+#define SCRT_TKIP_CERR_HI 19 -+#define SCRT_TKIP_CERR_SZ 20 -+#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff -+#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000 -+#define SCRT_TKIP_MIC_ERR_SFT 0 -+#define SCRT_TKIP_MIC_ERR_HI 19 -+#define SCRT_TKIP_MIC_ERR_SZ 20 -+#define SCRT_TKIP_RPLY_MSK 0x000fffff -+#define SCRT_TKIP_RPLY_I_MSK 0xfff00000 -+#define SCRT_TKIP_RPLY_SFT 0 -+#define SCRT_TKIP_RPLY_HI 19 -+#define SCRT_TKIP_RPLY_SZ 20 -+#define SCRT_CCMP_RPLY_MSK 0x000fffff -+#define SCRT_CCMP_RPLY_I_MSK 0xfff00000 -+#define SCRT_CCMP_RPLY_SFT 0 -+#define SCRT_CCMP_RPLY_HI 19 -+#define SCRT_CCMP_RPLY_SZ 20 -+#define SCRT_CCMP_CERR_MSK 0x000fffff -+#define SCRT_CCMP_CERR_I_MSK 0xfff00000 -+#define SCRT_CCMP_CERR_SFT 0 -+#define SCRT_CCMP_CERR_HI 19 -+#define SCRT_CCMP_CERR_SZ 20 -+#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff -+#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000 -+#define DBG_LEN_CRC_FAIL_SFT 0 -+#define DBG_LEN_CRC_FAIL_HI 15 -+#define DBG_LEN_CRC_FAIL_SZ 16 -+#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff -+#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000 -+#define DBG_LEN_ALC_FAIL_SFT 0 -+#define DBG_LEN_ALC_FAIL_HI 15 -+#define DBG_LEN_ALC_FAIL_SZ 16 -+#define DBG_AMPDU_PASS_MSK 0x0000ffff -+#define DBG_AMPDU_PASS_I_MSK 0xffff0000 -+#define DBG_AMPDU_PASS_SFT 0 -+#define DBG_AMPDU_PASS_HI 15 -+#define DBG_AMPDU_PASS_SZ 16 -+#define DBG_AMPDU_FAIL_MSK 0x0000ffff -+#define DBG_AMPDU_FAIL_I_MSK 0xffff0000 -+#define DBG_AMPDU_FAIL_SFT 0 -+#define DBG_AMPDU_FAIL_HI 15 -+#define DBG_AMPDU_FAIL_SZ 16 -+#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff -+#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000 -+#define RXID_ALC_CNT_FAIL_SFT 0 -+#define RXID_ALC_CNT_FAIL_HI 15 -+#define RXID_ALC_CNT_FAIL_SZ 16 -+#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff -+#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000 -+#define RXID_ALC_LEN_FAIL_SFT 0 -+#define RXID_ALC_LEN_FAIL_HI 15 -+#define RXID_ALC_LEN_FAIL_SZ 16 -+#define CBR_RG_EN_MANUAL_MSK 0x00000001 -+#define CBR_RG_EN_MANUAL_I_MSK 0xfffffffe -+#define CBR_RG_EN_MANUAL_SFT 0 -+#define CBR_RG_EN_MANUAL_HI 0 -+#define CBR_RG_EN_MANUAL_SZ 1 -+#define CBR_RG_TX_EN_MSK 0x00000002 -+#define CBR_RG_TX_EN_I_MSK 0xfffffffd -+#define CBR_RG_TX_EN_SFT 1 -+#define CBR_RG_TX_EN_HI 1 -+#define CBR_RG_TX_EN_SZ 1 -+#define CBR_RG_TX_PA_EN_MSK 0x00000004 -+#define CBR_RG_TX_PA_EN_I_MSK 0xfffffffb -+#define CBR_RG_TX_PA_EN_SFT 2 -+#define CBR_RG_TX_PA_EN_HI 2 -+#define CBR_RG_TX_PA_EN_SZ 1 -+#define CBR_RG_TX_DAC_EN_MSK 0x00000008 -+#define CBR_RG_TX_DAC_EN_I_MSK 0xfffffff7 -+#define CBR_RG_TX_DAC_EN_SFT 3 -+#define CBR_RG_TX_DAC_EN_HI 3 -+#define CBR_RG_TX_DAC_EN_SZ 1 -+#define CBR_RG_RX_AGC_MSK 0x00000010 -+#define CBR_RG_RX_AGC_I_MSK 0xffffffef -+#define CBR_RG_RX_AGC_SFT 4 -+#define CBR_RG_RX_AGC_HI 4 -+#define CBR_RG_RX_AGC_SZ 1 -+#define CBR_RG_RX_GAIN_MANUAL_MSK 0x00000020 -+#define CBR_RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf -+#define CBR_RG_RX_GAIN_MANUAL_SFT 5 -+#define CBR_RG_RX_GAIN_MANUAL_HI 5 -+#define CBR_RG_RX_GAIN_MANUAL_SZ 1 -+#define CBR_RG_RFG_MSK 0x000000c0 -+#define CBR_RG_RFG_I_MSK 0xffffff3f -+#define CBR_RG_RFG_SFT 6 -+#define CBR_RG_RFG_HI 7 -+#define CBR_RG_RFG_SZ 2 -+#define CBR_RG_PGAG_MSK 0x00000f00 -+#define CBR_RG_PGAG_I_MSK 0xfffff0ff -+#define CBR_RG_PGAG_SFT 8 -+#define CBR_RG_PGAG_HI 11 -+#define CBR_RG_PGAG_SZ 4 -+#define CBR_RG_MODE_MSK 0x00003000 -+#define CBR_RG_MODE_I_MSK 0xffffcfff -+#define CBR_RG_MODE_SFT 12 -+#define CBR_RG_MODE_HI 13 -+#define CBR_RG_MODE_SZ 2 -+#define CBR_RG_EN_TX_TRSW_MSK 0x00004000 -+#define CBR_RG_EN_TX_TRSW_I_MSK 0xffffbfff -+#define CBR_RG_EN_TX_TRSW_SFT 14 -+#define CBR_RG_EN_TX_TRSW_HI 14 -+#define CBR_RG_EN_TX_TRSW_SZ 1 -+#define CBR_RG_EN_SX_MSK 0x00008000 -+#define CBR_RG_EN_SX_I_MSK 0xffff7fff -+#define CBR_RG_EN_SX_SFT 15 -+#define CBR_RG_EN_SX_HI 15 -+#define CBR_RG_EN_SX_SZ 1 -+#define CBR_RG_EN_RX_LNA_MSK 0x00010000 -+#define CBR_RG_EN_RX_LNA_I_MSK 0xfffeffff -+#define CBR_RG_EN_RX_LNA_SFT 16 -+#define CBR_RG_EN_RX_LNA_HI 16 -+#define CBR_RG_EN_RX_LNA_SZ 1 -+#define CBR_RG_EN_RX_MIXER_MSK 0x00020000 -+#define CBR_RG_EN_RX_MIXER_I_MSK 0xfffdffff -+#define CBR_RG_EN_RX_MIXER_SFT 17 -+#define CBR_RG_EN_RX_MIXER_HI 17 -+#define CBR_RG_EN_RX_MIXER_SZ 1 -+#define CBR_RG_EN_RX_DIV2_MSK 0x00040000 -+#define CBR_RG_EN_RX_DIV2_I_MSK 0xfffbffff -+#define CBR_RG_EN_RX_DIV2_SFT 18 -+#define CBR_RG_EN_RX_DIV2_HI 18 -+#define CBR_RG_EN_RX_DIV2_SZ 1 -+#define CBR_RG_EN_RX_LOBUF_MSK 0x00080000 -+#define CBR_RG_EN_RX_LOBUF_I_MSK 0xfff7ffff -+#define CBR_RG_EN_RX_LOBUF_SFT 19 -+#define CBR_RG_EN_RX_LOBUF_HI 19 -+#define CBR_RG_EN_RX_LOBUF_SZ 1 -+#define CBR_RG_EN_RX_TZ_MSK 0x00100000 -+#define CBR_RG_EN_RX_TZ_I_MSK 0xffefffff -+#define CBR_RG_EN_RX_TZ_SFT 20 -+#define CBR_RG_EN_RX_TZ_HI 20 -+#define CBR_RG_EN_RX_TZ_SZ 1 -+#define CBR_RG_EN_RX_FILTER_MSK 0x00200000 -+#define CBR_RG_EN_RX_FILTER_I_MSK 0xffdfffff -+#define CBR_RG_EN_RX_FILTER_SFT 21 -+#define CBR_RG_EN_RX_FILTER_HI 21 -+#define CBR_RG_EN_RX_FILTER_SZ 1 -+#define CBR_RG_EN_RX_HPF_MSK 0x00400000 -+#define CBR_RG_EN_RX_HPF_I_MSK 0xffbfffff -+#define CBR_RG_EN_RX_HPF_SFT 22 -+#define CBR_RG_EN_RX_HPF_HI 22 -+#define CBR_RG_EN_RX_HPF_SZ 1 -+#define CBR_RG_EN_RX_RSSI_MSK 0x00800000 -+#define CBR_RG_EN_RX_RSSI_I_MSK 0xff7fffff -+#define CBR_RG_EN_RX_RSSI_SFT 23 -+#define CBR_RG_EN_RX_RSSI_HI 23 -+#define CBR_RG_EN_RX_RSSI_SZ 1 -+#define CBR_RG_EN_ADC_MSK 0x01000000 -+#define CBR_RG_EN_ADC_I_MSK 0xfeffffff -+#define CBR_RG_EN_ADC_SFT 24 -+#define CBR_RG_EN_ADC_HI 24 -+#define CBR_RG_EN_ADC_SZ 1 -+#define CBR_RG_EN_TX_MOD_MSK 0x02000000 -+#define CBR_RG_EN_TX_MOD_I_MSK 0xfdffffff -+#define CBR_RG_EN_TX_MOD_SFT 25 -+#define CBR_RG_EN_TX_MOD_HI 25 -+#define CBR_RG_EN_TX_MOD_SZ 1 -+#define CBR_RG_EN_TX_DIV2_MSK 0x04000000 -+#define CBR_RG_EN_TX_DIV2_I_MSK 0xfbffffff -+#define CBR_RG_EN_TX_DIV2_SFT 26 -+#define CBR_RG_EN_TX_DIV2_HI 26 -+#define CBR_RG_EN_TX_DIV2_SZ 1 -+#define CBR_RG_EN_TX_DIV2_BUF_MSK 0x08000000 -+#define CBR_RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff -+#define CBR_RG_EN_TX_DIV2_BUF_SFT 27 -+#define CBR_RG_EN_TX_DIV2_BUF_HI 27 -+#define CBR_RG_EN_TX_DIV2_BUF_SZ 1 -+#define CBR_RG_EN_TX_LOBF_MSK 0x10000000 -+#define CBR_RG_EN_TX_LOBF_I_MSK 0xefffffff -+#define CBR_RG_EN_TX_LOBF_SFT 28 -+#define CBR_RG_EN_TX_LOBF_HI 28 -+#define CBR_RG_EN_TX_LOBF_SZ 1 -+#define CBR_RG_EN_RX_LOBF_MSK 0x20000000 -+#define CBR_RG_EN_RX_LOBF_I_MSK 0xdfffffff -+#define CBR_RG_EN_RX_LOBF_SFT 29 -+#define CBR_RG_EN_RX_LOBF_HI 29 -+#define CBR_RG_EN_RX_LOBF_SZ 1 -+#define CBR_RG_SEL_DPLL_CLK_MSK 0x40000000 -+#define CBR_RG_SEL_DPLL_CLK_I_MSK 0xbfffffff -+#define CBR_RG_SEL_DPLL_CLK_SFT 30 -+#define CBR_RG_SEL_DPLL_CLK_HI 30 -+#define CBR_RG_SEL_DPLL_CLK_SZ 1 -+#define CBR_RG_EN_TX_DPD_MSK 0x00000001 -+#define CBR_RG_EN_TX_DPD_I_MSK 0xfffffffe -+#define CBR_RG_EN_TX_DPD_SFT 0 -+#define CBR_RG_EN_TX_DPD_HI 0 -+#define CBR_RG_EN_TX_DPD_SZ 1 -+#define CBR_RG_EN_TX_TSSI_MSK 0x00000002 -+#define CBR_RG_EN_TX_TSSI_I_MSK 0xfffffffd -+#define CBR_RG_EN_TX_TSSI_SFT 1 -+#define CBR_RG_EN_TX_TSSI_HI 1 -+#define CBR_RG_EN_TX_TSSI_SZ 1 -+#define CBR_RG_EN_RX_IQCAL_MSK 0x00000004 -+#define CBR_RG_EN_RX_IQCAL_I_MSK 0xfffffffb -+#define CBR_RG_EN_RX_IQCAL_SFT 2 -+#define CBR_RG_EN_RX_IQCAL_HI 2 -+#define CBR_RG_EN_RX_IQCAL_SZ 1 -+#define CBR_RG_EN_TX_DAC_CAL_MSK 0x00000008 -+#define CBR_RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7 -+#define CBR_RG_EN_TX_DAC_CAL_SFT 3 -+#define CBR_RG_EN_TX_DAC_CAL_HI 3 -+#define CBR_RG_EN_TX_DAC_CAL_SZ 1 -+#define CBR_RG_EN_TX_SELF_MIXER_MSK 0x00000010 -+#define CBR_RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef -+#define CBR_RG_EN_TX_SELF_MIXER_SFT 4 -+#define CBR_RG_EN_TX_SELF_MIXER_HI 4 -+#define CBR_RG_EN_TX_SELF_MIXER_SZ 1 -+#define CBR_RG_EN_TX_DAC_OUT_MSK 0x00000020 -+#define CBR_RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf -+#define CBR_RG_EN_TX_DAC_OUT_SFT 5 -+#define CBR_RG_EN_TX_DAC_OUT_HI 5 -+#define CBR_RG_EN_TX_DAC_OUT_SZ 1 -+#define CBR_RG_EN_LDO_RX_FE_MSK 0x00000040 -+#define CBR_RG_EN_LDO_RX_FE_I_MSK 0xffffffbf -+#define CBR_RG_EN_LDO_RX_FE_SFT 6 -+#define CBR_RG_EN_LDO_RX_FE_HI 6 -+#define CBR_RG_EN_LDO_RX_FE_SZ 1 -+#define CBR_RG_EN_LDO_ABB_MSK 0x00000080 -+#define CBR_RG_EN_LDO_ABB_I_MSK 0xffffff7f -+#define CBR_RG_EN_LDO_ABB_SFT 7 -+#define CBR_RG_EN_LDO_ABB_HI 7 -+#define CBR_RG_EN_LDO_ABB_SZ 1 -+#define CBR_RG_EN_LDO_AFE_MSK 0x00000100 -+#define CBR_RG_EN_LDO_AFE_I_MSK 0xfffffeff -+#define CBR_RG_EN_LDO_AFE_SFT 8 -+#define CBR_RG_EN_LDO_AFE_HI 8 -+#define CBR_RG_EN_LDO_AFE_SZ 1 -+#define CBR_RG_EN_SX_CHPLDO_MSK 0x00000200 -+#define CBR_RG_EN_SX_CHPLDO_I_MSK 0xfffffdff -+#define CBR_RG_EN_SX_CHPLDO_SFT 9 -+#define CBR_RG_EN_SX_CHPLDO_HI 9 -+#define CBR_RG_EN_SX_CHPLDO_SZ 1 -+#define CBR_RG_EN_SX_LOBFLDO_MSK 0x00000400 -+#define CBR_RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff -+#define CBR_RG_EN_SX_LOBFLDO_SFT 10 -+#define CBR_RG_EN_SX_LOBFLDO_HI 10 -+#define CBR_RG_EN_SX_LOBFLDO_SZ 1 -+#define CBR_RG_EN_IREF_RX_MSK 0x00000800 -+#define CBR_RG_EN_IREF_RX_I_MSK 0xfffff7ff -+#define CBR_RG_EN_IREF_RX_SFT 11 -+#define CBR_RG_EN_IREF_RX_HI 11 -+#define CBR_RG_EN_IREF_RX_SZ 1 -+#define CBR_RG_DCDC_MODE_MSK 0x00001000 -+#define CBR_RG_DCDC_MODE_I_MSK 0xffffefff -+#define CBR_RG_DCDC_MODE_SFT 12 -+#define CBR_RG_DCDC_MODE_HI 12 -+#define CBR_RG_DCDC_MODE_SZ 1 -+#define CBR_RG_LDO_LEVEL_RX_FE_MSK 0x00000007 -+#define CBR_RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8 -+#define CBR_RG_LDO_LEVEL_RX_FE_SFT 0 -+#define CBR_RG_LDO_LEVEL_RX_FE_HI 2 -+#define CBR_RG_LDO_LEVEL_RX_FE_SZ 3 -+#define CBR_RG_LDO_LEVEL_ABB_MSK 0x00000038 -+#define CBR_RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7 -+#define CBR_RG_LDO_LEVEL_ABB_SFT 3 -+#define CBR_RG_LDO_LEVEL_ABB_HI 5 -+#define CBR_RG_LDO_LEVEL_ABB_SZ 3 -+#define CBR_RG_LDO_LEVEL_AFE_MSK 0x000001c0 -+#define CBR_RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f -+#define CBR_RG_LDO_LEVEL_AFE_SFT 6 -+#define CBR_RG_LDO_LEVEL_AFE_HI 8 -+#define CBR_RG_LDO_LEVEL_AFE_SZ 3 -+#define CBR_RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00 -+#define CBR_RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff -+#define CBR_RG_SX_LDO_CHP_LEVEL_SFT 9 -+#define CBR_RG_SX_LDO_CHP_LEVEL_HI 11 -+#define CBR_RG_SX_LDO_CHP_LEVEL_SZ 3 -+#define CBR_RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000 -+#define CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff -+#define CBR_RG_SX_LDO_LOBF_LEVEL_SFT 12 -+#define CBR_RG_SX_LDO_LOBF_LEVEL_HI 14 -+#define CBR_RG_SX_LDO_LOBF_LEVEL_SZ 3 -+#define CBR_RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000 -+#define CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff -+#define CBR_RG_SX_LDO_XOSC_LEVEL_SFT 15 -+#define CBR_RG_SX_LDO_XOSC_LEVEL_HI 17 -+#define CBR_RG_SX_LDO_XOSC_LEVEL_SZ 3 -+#define CBR_RG_DP_LDO_LEVEL_MSK 0x001c0000 -+#define CBR_RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff -+#define CBR_RG_DP_LDO_LEVEL_SFT 18 -+#define CBR_RG_DP_LDO_LEVEL_HI 20 -+#define CBR_RG_DP_LDO_LEVEL_SZ 3 -+#define CBR_RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000 -+#define CBR_RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff -+#define CBR_RG_SX_LDO_VCO_LEVEL_SFT 21 -+#define CBR_RG_SX_LDO_VCO_LEVEL_HI 23 -+#define CBR_RG_SX_LDO_VCO_LEVEL_SZ 3 -+#define CBR_RG_TX_LDO_TX_LEVEL_MSK 0x07000000 -+#define CBR_RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff -+#define CBR_RG_TX_LDO_TX_LEVEL_SFT 24 -+#define CBR_RG_TX_LDO_TX_LEVEL_HI 26 -+#define CBR_RG_TX_LDO_TX_LEVEL_SZ 3 -+#define CBR_RG_BUCK_LEVEL_MSK 0x38000000 -+#define CBR_RG_BUCK_LEVEL_I_MSK 0xc7ffffff -+#define CBR_RG_BUCK_LEVEL_SFT 27 -+#define CBR_RG_BUCK_LEVEL_HI 29 -+#define CBR_RG_BUCK_LEVEL_SZ 3 -+#define CBR_RG_EN_RX_PADSW_MSK 0x00000001 -+#define CBR_RG_EN_RX_PADSW_I_MSK 0xfffffffe -+#define CBR_RG_EN_RX_PADSW_SFT 0 -+#define CBR_RG_EN_RX_PADSW_HI 0 -+#define CBR_RG_EN_RX_PADSW_SZ 1 -+#define CBR_RG_EN_RX_TESTNODE_MSK 0x00000002 -+#define CBR_RG_EN_RX_TESTNODE_I_MSK 0xfffffffd -+#define CBR_RG_EN_RX_TESTNODE_SFT 1 -+#define CBR_RG_EN_RX_TESTNODE_HI 1 -+#define CBR_RG_EN_RX_TESTNODE_SZ 1 -+#define CBR_RG_RX_ABBCFIX_MSK 0x00000004 -+#define CBR_RG_RX_ABBCFIX_I_MSK 0xfffffffb -+#define CBR_RG_RX_ABBCFIX_SFT 2 -+#define CBR_RG_RX_ABBCFIX_HI 2 -+#define CBR_RG_RX_ABBCFIX_SZ 1 -+#define CBR_RG_RX_ABBCTUNE_MSK 0x000001f8 -+#define CBR_RG_RX_ABBCTUNE_I_MSK 0xfffffe07 -+#define CBR_RG_RX_ABBCTUNE_SFT 3 -+#define CBR_RG_RX_ABBCTUNE_HI 8 -+#define CBR_RG_RX_ABBCTUNE_SZ 6 -+#define CBR_RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200 -+#define CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff -+#define CBR_RG_RX_ABBOUT_TRI_STATE_SFT 9 -+#define CBR_RG_RX_ABBOUT_TRI_STATE_HI 9 -+#define CBR_RG_RX_ABBOUT_TRI_STATE_SZ 1 -+#define CBR_RG_RX_ABB_N_MODE_MSK 0x00000400 -+#define CBR_RG_RX_ABB_N_MODE_I_MSK 0xfffffbff -+#define CBR_RG_RX_ABB_N_MODE_SFT 10 -+#define CBR_RG_RX_ABB_N_MODE_HI 10 -+#define CBR_RG_RX_ABB_N_MODE_SZ 1 -+#define CBR_RG_RX_EN_LOOPA_MSK 0x00000800 -+#define CBR_RG_RX_EN_LOOPA_I_MSK 0xfffff7ff -+#define CBR_RG_RX_EN_LOOPA_SFT 11 -+#define CBR_RG_RX_EN_LOOPA_HI 11 -+#define CBR_RG_RX_EN_LOOPA_SZ 1 -+#define CBR_RG_RX_FILTERI1ST_MSK 0x00003000 -+#define CBR_RG_RX_FILTERI1ST_I_MSK 0xffffcfff -+#define CBR_RG_RX_FILTERI1ST_SFT 12 -+#define CBR_RG_RX_FILTERI1ST_HI 13 -+#define CBR_RG_RX_FILTERI1ST_SZ 2 -+#define CBR_RG_RX_FILTERI2ND_MSK 0x0000c000 -+#define CBR_RG_RX_FILTERI2ND_I_MSK 0xffff3fff -+#define CBR_RG_RX_FILTERI2ND_SFT 14 -+#define CBR_RG_RX_FILTERI2ND_HI 15 -+#define CBR_RG_RX_FILTERI2ND_SZ 2 -+#define CBR_RG_RX_FILTERI3RD_MSK 0x00030000 -+#define CBR_RG_RX_FILTERI3RD_I_MSK 0xfffcffff -+#define CBR_RG_RX_FILTERI3RD_SFT 16 -+#define CBR_RG_RX_FILTERI3RD_HI 17 -+#define CBR_RG_RX_FILTERI3RD_SZ 2 -+#define CBR_RG_RX_FILTERI_COURSE_MSK 0x000c0000 -+#define CBR_RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff -+#define CBR_RG_RX_FILTERI_COURSE_SFT 18 -+#define CBR_RG_RX_FILTERI_COURSE_HI 19 -+#define CBR_RG_RX_FILTERI_COURSE_SZ 2 -+#define CBR_RG_RX_FILTERVCM_MSK 0x00300000 -+#define CBR_RG_RX_FILTERVCM_I_MSK 0xffcfffff -+#define CBR_RG_RX_FILTERVCM_SFT 20 -+#define CBR_RG_RX_FILTERVCM_HI 21 -+#define CBR_RG_RX_FILTERVCM_SZ 2 -+#define CBR_RG_RX_HPF3M_MSK 0x00400000 -+#define CBR_RG_RX_HPF3M_I_MSK 0xffbfffff -+#define CBR_RG_RX_HPF3M_SFT 22 -+#define CBR_RG_RX_HPF3M_HI 22 -+#define CBR_RG_RX_HPF3M_SZ 1 -+#define CBR_RG_RX_HPF300K_MSK 0x00800000 -+#define CBR_RG_RX_HPF300K_I_MSK 0xff7fffff -+#define CBR_RG_RX_HPF300K_SFT 23 -+#define CBR_RG_RX_HPF300K_HI 23 -+#define CBR_RG_RX_HPF300K_SZ 1 -+#define CBR_RG_RX_HPFI_MSK 0x03000000 -+#define CBR_RG_RX_HPFI_I_MSK 0xfcffffff -+#define CBR_RG_RX_HPFI_SFT 24 -+#define CBR_RG_RX_HPFI_HI 25 -+#define CBR_RG_RX_HPFI_SZ 2 -+#define CBR_RG_RX_HPF_FINALCORNER_MSK 0x0c000000 -+#define CBR_RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff -+#define CBR_RG_RX_HPF_FINALCORNER_SFT 26 -+#define CBR_RG_RX_HPF_FINALCORNER_HI 27 -+#define CBR_RG_RX_HPF_FINALCORNER_SZ 2 -+#define CBR_RG_RX_HPF_SETTLE1_C_MSK 0x30000000 -+#define CBR_RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff -+#define CBR_RG_RX_HPF_SETTLE1_C_SFT 28 -+#define CBR_RG_RX_HPF_SETTLE1_C_HI 29 -+#define CBR_RG_RX_HPF_SETTLE1_C_SZ 2 -+#define CBR_RG_RX_HPF_SETTLE1_R_MSK 0x00000003 -+#define CBR_RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc -+#define CBR_RG_RX_HPF_SETTLE1_R_SFT 0 -+#define CBR_RG_RX_HPF_SETTLE1_R_HI 1 -+#define CBR_RG_RX_HPF_SETTLE1_R_SZ 2 -+#define CBR_RG_RX_HPF_SETTLE2_C_MSK 0x0000000c -+#define CBR_RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3 -+#define CBR_RG_RX_HPF_SETTLE2_C_SFT 2 -+#define CBR_RG_RX_HPF_SETTLE2_C_HI 3 -+#define CBR_RG_RX_HPF_SETTLE2_C_SZ 2 -+#define CBR_RG_RX_HPF_SETTLE2_R_MSK 0x00000030 -+#define CBR_RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf -+#define CBR_RG_RX_HPF_SETTLE2_R_SFT 4 -+#define CBR_RG_RX_HPF_SETTLE2_R_HI 5 -+#define CBR_RG_RX_HPF_SETTLE2_R_SZ 2 -+#define CBR_RG_RX_HPF_VCMCON2_MSK 0x000000c0 -+#define CBR_RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f -+#define CBR_RG_RX_HPF_VCMCON2_SFT 6 -+#define CBR_RG_RX_HPF_VCMCON2_HI 7 -+#define CBR_RG_RX_HPF_VCMCON2_SZ 2 -+#define CBR_RG_RX_HPF_VCMCON_MSK 0x00000300 -+#define CBR_RG_RX_HPF_VCMCON_I_MSK 0xfffffcff -+#define CBR_RG_RX_HPF_VCMCON_SFT 8 -+#define CBR_RG_RX_HPF_VCMCON_HI 9 -+#define CBR_RG_RX_HPF_VCMCON_SZ 2 -+#define CBR_RG_RX_OUTVCM_MSK 0x00000c00 -+#define CBR_RG_RX_OUTVCM_I_MSK 0xfffff3ff -+#define CBR_RG_RX_OUTVCM_SFT 10 -+#define CBR_RG_RX_OUTVCM_HI 11 -+#define CBR_RG_RX_OUTVCM_SZ 2 -+#define CBR_RG_RX_TZI_MSK 0x00003000 -+#define CBR_RG_RX_TZI_I_MSK 0xffffcfff -+#define CBR_RG_RX_TZI_SFT 12 -+#define CBR_RG_RX_TZI_HI 13 -+#define CBR_RG_RX_TZI_SZ 2 -+#define CBR_RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000 -+#define CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff -+#define CBR_RG_RX_TZ_OUT_TRISTATE_SFT 14 -+#define CBR_RG_RX_TZ_OUT_TRISTATE_HI 14 -+#define CBR_RG_RX_TZ_OUT_TRISTATE_SZ 1 -+#define CBR_RG_RX_TZ_VCM_MSK 0x00018000 -+#define CBR_RG_RX_TZ_VCM_I_MSK 0xfffe7fff -+#define CBR_RG_RX_TZ_VCM_SFT 15 -+#define CBR_RG_RX_TZ_VCM_HI 16 -+#define CBR_RG_RX_TZ_VCM_SZ 2 -+#define CBR_RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000 -+#define CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff -+#define CBR_RG_EN_RX_RSSI_TESTNODE_SFT 17 -+#define CBR_RG_EN_RX_RSSI_TESTNODE_HI 19 -+#define CBR_RG_EN_RX_RSSI_TESTNODE_SZ 3 -+#define CBR_RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000 -+#define CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff -+#define CBR_RG_RX_ADCRSSI_CLKSEL_SFT 20 -+#define CBR_RG_RX_ADCRSSI_CLKSEL_HI 20 -+#define CBR_RG_RX_ADCRSSI_CLKSEL_SZ 1 -+#define CBR_RG_RX_ADCRSSI_VCM_MSK 0x00600000 -+#define CBR_RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff -+#define CBR_RG_RX_ADCRSSI_VCM_SFT 21 -+#define CBR_RG_RX_ADCRSSI_VCM_HI 22 -+#define CBR_RG_RX_ADCRSSI_VCM_SZ 2 -+#define CBR_RG_RX_REC_LPFCORNER_MSK 0x01800000 -+#define CBR_RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff -+#define CBR_RG_RX_REC_LPFCORNER_SFT 23 -+#define CBR_RG_RX_REC_LPFCORNER_HI 24 -+#define CBR_RG_RX_REC_LPFCORNER_SZ 2 -+#define CBR_RG_RSSI_CLOCK_GATING_MSK 0x02000000 -+#define CBR_RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff -+#define CBR_RG_RSSI_CLOCK_GATING_SFT 25 -+#define CBR_RG_RSSI_CLOCK_GATING_HI 25 -+#define CBR_RG_RSSI_CLOCK_GATING_SZ 1 -+#define CBR_RG_TXPGA_CAPSW_MSK 0x00000003 -+#define CBR_RG_TXPGA_CAPSW_I_MSK 0xfffffffc -+#define CBR_RG_TXPGA_CAPSW_SFT 0 -+#define CBR_RG_TXPGA_CAPSW_HI 1 -+#define CBR_RG_TXPGA_CAPSW_SZ 2 -+#define CBR_RG_TXPGA_MAIN_MSK 0x000000fc -+#define CBR_RG_TXPGA_MAIN_I_MSK 0xffffff03 -+#define CBR_RG_TXPGA_MAIN_SFT 2 -+#define CBR_RG_TXPGA_MAIN_HI 7 -+#define CBR_RG_TXPGA_MAIN_SZ 6 -+#define CBR_RG_TXPGA_STEER_MSK 0x00003f00 -+#define CBR_RG_TXPGA_STEER_I_MSK 0xffffc0ff -+#define CBR_RG_TXPGA_STEER_SFT 8 -+#define CBR_RG_TXPGA_STEER_HI 13 -+#define CBR_RG_TXPGA_STEER_SZ 6 -+#define CBR_RG_TXMOD_GMCELL_MSK 0x0000c000 -+#define CBR_RG_TXMOD_GMCELL_I_MSK 0xffff3fff -+#define CBR_RG_TXMOD_GMCELL_SFT 14 -+#define CBR_RG_TXMOD_GMCELL_HI 15 -+#define CBR_RG_TXMOD_GMCELL_SZ 2 -+#define CBR_RG_TXLPF_GMCELL_MSK 0x00030000 -+#define CBR_RG_TXLPF_GMCELL_I_MSK 0xfffcffff -+#define CBR_RG_TXLPF_GMCELL_SFT 16 -+#define CBR_RG_TXLPF_GMCELL_HI 17 -+#define CBR_RG_TXLPF_GMCELL_SZ 2 -+#define CBR_RG_PACELL_EN_MSK 0x001c0000 -+#define CBR_RG_PACELL_EN_I_MSK 0xffe3ffff -+#define CBR_RG_PACELL_EN_SFT 18 -+#define CBR_RG_PACELL_EN_HI 20 -+#define CBR_RG_PACELL_EN_SZ 3 -+#define CBR_RG_PABIAS_CTRL_MSK 0x01e00000 -+#define CBR_RG_PABIAS_CTRL_I_MSK 0xfe1fffff -+#define CBR_RG_PABIAS_CTRL_SFT 21 -+#define CBR_RG_PABIAS_CTRL_HI 24 -+#define CBR_RG_PABIAS_CTRL_SZ 4 -+#define CBR_RG_PABIAS_AB_MSK 0x02000000 -+#define CBR_RG_PABIAS_AB_I_MSK 0xfdffffff -+#define CBR_RG_PABIAS_AB_SFT 25 -+#define CBR_RG_PABIAS_AB_HI 25 -+#define CBR_RG_PABIAS_AB_SZ 1 -+#define CBR_RG_TX_DIV_VSET_MSK 0x0c000000 -+#define CBR_RG_TX_DIV_VSET_I_MSK 0xf3ffffff -+#define CBR_RG_TX_DIV_VSET_SFT 26 -+#define CBR_RG_TX_DIV_VSET_HI 27 -+#define CBR_RG_TX_DIV_VSET_SZ 2 -+#define CBR_RG_TX_LOBUF_VSET_MSK 0x30000000 -+#define CBR_RG_TX_LOBUF_VSET_I_MSK 0xcfffffff -+#define CBR_RG_TX_LOBUF_VSET_SFT 28 -+#define CBR_RG_TX_LOBUF_VSET_HI 29 -+#define CBR_RG_TX_LOBUF_VSET_SZ 2 -+#define CBR_RG_RX_SQDC_MSK 0x00000007 -+#define CBR_RG_RX_SQDC_I_MSK 0xfffffff8 -+#define CBR_RG_RX_SQDC_SFT 0 -+#define CBR_RG_RX_SQDC_HI 2 -+#define CBR_RG_RX_SQDC_SZ 3 -+#define CBR_RG_RX_DIV2_CORE_MSK 0x00000018 -+#define CBR_RG_RX_DIV2_CORE_I_MSK 0xffffffe7 -+#define CBR_RG_RX_DIV2_CORE_SFT 3 -+#define CBR_RG_RX_DIV2_CORE_HI 4 -+#define CBR_RG_RX_DIV2_CORE_SZ 2 -+#define CBR_RG_RX_LOBUF_MSK 0x00000060 -+#define CBR_RG_RX_LOBUF_I_MSK 0xffffff9f -+#define CBR_RG_RX_LOBUF_SFT 5 -+#define CBR_RG_RX_LOBUF_HI 6 -+#define CBR_RG_RX_LOBUF_SZ 2 -+#define CBR_RG_TX_DPDGM_BIAS_MSK 0x00000780 -+#define CBR_RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f -+#define CBR_RG_TX_DPDGM_BIAS_SFT 7 -+#define CBR_RG_TX_DPDGM_BIAS_HI 10 -+#define CBR_RG_TX_DPDGM_BIAS_SZ 4 -+#define CBR_RG_TX_DPD_DIV_MSK 0x00007800 -+#define CBR_RG_TX_DPD_DIV_I_MSK 0xffff87ff -+#define CBR_RG_TX_DPD_DIV_SFT 11 -+#define CBR_RG_TX_DPD_DIV_HI 14 -+#define CBR_RG_TX_DPD_DIV_SZ 4 -+#define CBR_RG_TX_TSSI_BIAS_MSK 0x00038000 -+#define CBR_RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff -+#define CBR_RG_TX_TSSI_BIAS_SFT 15 -+#define CBR_RG_TX_TSSI_BIAS_HI 17 -+#define CBR_RG_TX_TSSI_BIAS_SZ 3 -+#define CBR_RG_TX_TSSI_DIV_MSK 0x001c0000 -+#define CBR_RG_TX_TSSI_DIV_I_MSK 0xffe3ffff -+#define CBR_RG_TX_TSSI_DIV_SFT 18 -+#define CBR_RG_TX_TSSI_DIV_HI 20 -+#define CBR_RG_TX_TSSI_DIV_SZ 3 -+#define CBR_RG_TX_TSSI_TESTMODE_MSK 0x00200000 -+#define CBR_RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff -+#define CBR_RG_TX_TSSI_TESTMODE_SFT 21 -+#define CBR_RG_TX_TSSI_TESTMODE_HI 21 -+#define CBR_RG_TX_TSSI_TESTMODE_SZ 1 -+#define CBR_RG_TX_TSSI_TEST_MSK 0x00c00000 -+#define CBR_RG_TX_TSSI_TEST_I_MSK 0xff3fffff -+#define CBR_RG_TX_TSSI_TEST_SFT 22 -+#define CBR_RG_TX_TSSI_TEST_HI 23 -+#define CBR_RG_TX_TSSI_TEST_SZ 2 -+#define CBR_RG_RX_HG_LNA_GC_MSK 0x00000003 -+#define CBR_RG_RX_HG_LNA_GC_I_MSK 0xfffffffc -+#define CBR_RG_RX_HG_LNA_GC_SFT 0 -+#define CBR_RG_RX_HG_LNA_GC_HI 1 -+#define CBR_RG_RX_HG_LNA_GC_SZ 2 -+#define CBR_RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c -+#define CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3 -+#define CBR_RG_RX_HG_LNAHGN_BIAS_SFT 2 -+#define CBR_RG_RX_HG_LNAHGN_BIAS_HI 5 -+#define CBR_RG_RX_HG_LNAHGN_BIAS_SZ 4 -+#define CBR_RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0 -+#define CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f -+#define CBR_RG_RX_HG_LNAHGP_BIAS_SFT 6 -+#define CBR_RG_RX_HG_LNAHGP_BIAS_HI 9 -+#define CBR_RG_RX_HG_LNAHGP_BIAS_SZ 4 -+#define CBR_RG_RX_HG_LNALG_BIAS_MSK 0x00003c00 -+#define CBR_RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff -+#define CBR_RG_RX_HG_LNALG_BIAS_SFT 10 -+#define CBR_RG_RX_HG_LNALG_BIAS_HI 13 -+#define CBR_RG_RX_HG_LNALG_BIAS_SZ 4 -+#define CBR_RG_RX_HG_TZ_GC_MSK 0x0000c000 -+#define CBR_RG_RX_HG_TZ_GC_I_MSK 0xffff3fff -+#define CBR_RG_RX_HG_TZ_GC_SFT 14 -+#define CBR_RG_RX_HG_TZ_GC_HI 15 -+#define CBR_RG_RX_HG_TZ_GC_SZ 2 -+#define CBR_RG_RX_HG_TZ_CAP_MSK 0x00070000 -+#define CBR_RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff -+#define CBR_RG_RX_HG_TZ_CAP_SFT 16 -+#define CBR_RG_RX_HG_TZ_CAP_HI 18 -+#define CBR_RG_RX_HG_TZ_CAP_SZ 3 -+#define CBR_RG_RX_MG_LNA_GC_MSK 0x00000003 -+#define CBR_RG_RX_MG_LNA_GC_I_MSK 0xfffffffc -+#define CBR_RG_RX_MG_LNA_GC_SFT 0 -+#define CBR_RG_RX_MG_LNA_GC_HI 1 -+#define CBR_RG_RX_MG_LNA_GC_SZ 2 -+#define CBR_RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c -+#define CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3 -+#define CBR_RG_RX_MG_LNAHGN_BIAS_SFT 2 -+#define CBR_RG_RX_MG_LNAHGN_BIAS_HI 5 -+#define CBR_RG_RX_MG_LNAHGN_BIAS_SZ 4 -+#define CBR_RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0 -+#define CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f -+#define CBR_RG_RX_MG_LNAHGP_BIAS_SFT 6 -+#define CBR_RG_RX_MG_LNAHGP_BIAS_HI 9 -+#define CBR_RG_RX_MG_LNAHGP_BIAS_SZ 4 -+#define CBR_RG_RX_MG_LNALG_BIAS_MSK 0x00003c00 -+#define CBR_RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff -+#define CBR_RG_RX_MG_LNALG_BIAS_SFT 10 -+#define CBR_RG_RX_MG_LNALG_BIAS_HI 13 -+#define CBR_RG_RX_MG_LNALG_BIAS_SZ 4 -+#define CBR_RG_RX_MG_TZ_GC_MSK 0x0000c000 -+#define CBR_RG_RX_MG_TZ_GC_I_MSK 0xffff3fff -+#define CBR_RG_RX_MG_TZ_GC_SFT 14 -+#define CBR_RG_RX_MG_TZ_GC_HI 15 -+#define CBR_RG_RX_MG_TZ_GC_SZ 2 -+#define CBR_RG_RX_MG_TZ_CAP_MSK 0x00070000 -+#define CBR_RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff -+#define CBR_RG_RX_MG_TZ_CAP_SFT 16 -+#define CBR_RG_RX_MG_TZ_CAP_HI 18 -+#define CBR_RG_RX_MG_TZ_CAP_SZ 3 -+#define CBR_RG_RX_LG_LNA_GC_MSK 0x00000003 -+#define CBR_RG_RX_LG_LNA_GC_I_MSK 0xfffffffc -+#define CBR_RG_RX_LG_LNA_GC_SFT 0 -+#define CBR_RG_RX_LG_LNA_GC_HI 1 -+#define CBR_RG_RX_LG_LNA_GC_SZ 2 -+#define CBR_RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c -+#define CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3 -+#define CBR_RG_RX_LG_LNAHGN_BIAS_SFT 2 -+#define CBR_RG_RX_LG_LNAHGN_BIAS_HI 5 -+#define CBR_RG_RX_LG_LNAHGN_BIAS_SZ 4 -+#define CBR_RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0 -+#define CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f -+#define CBR_RG_RX_LG_LNAHGP_BIAS_SFT 6 -+#define CBR_RG_RX_LG_LNAHGP_BIAS_HI 9 -+#define CBR_RG_RX_LG_LNAHGP_BIAS_SZ 4 -+#define CBR_RG_RX_LG_LNALG_BIAS_MSK 0x00003c00 -+#define CBR_RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff -+#define CBR_RG_RX_LG_LNALG_BIAS_SFT 10 -+#define CBR_RG_RX_LG_LNALG_BIAS_HI 13 -+#define CBR_RG_RX_LG_LNALG_BIAS_SZ 4 -+#define CBR_RG_RX_LG_TZ_GC_MSK 0x0000c000 -+#define CBR_RG_RX_LG_TZ_GC_I_MSK 0xffff3fff -+#define CBR_RG_RX_LG_TZ_GC_SFT 14 -+#define CBR_RG_RX_LG_TZ_GC_HI 15 -+#define CBR_RG_RX_LG_TZ_GC_SZ 2 -+#define CBR_RG_RX_LG_TZ_CAP_MSK 0x00070000 -+#define CBR_RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff -+#define CBR_RG_RX_LG_TZ_CAP_SFT 16 -+#define CBR_RG_RX_LG_TZ_CAP_HI 18 -+#define CBR_RG_RX_LG_TZ_CAP_SZ 3 -+#define CBR_RG_RX_ULG_LNA_GC_MSK 0x00000003 -+#define CBR_RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc -+#define CBR_RG_RX_ULG_LNA_GC_SFT 0 -+#define CBR_RG_RX_ULG_LNA_GC_HI 1 -+#define CBR_RG_RX_ULG_LNA_GC_SZ 2 -+#define CBR_RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c -+#define CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3 -+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SFT 2 -+#define CBR_RG_RX_ULG_LNAHGN_BIAS_HI 5 -+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SZ 4 -+#define CBR_RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0 -+#define CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f -+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SFT 6 -+#define CBR_RG_RX_ULG_LNAHGP_BIAS_HI 9 -+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SZ 4 -+#define CBR_RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00 -+#define CBR_RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff -+#define CBR_RG_RX_ULG_LNALG_BIAS_SFT 10 -+#define CBR_RG_RX_ULG_LNALG_BIAS_HI 13 -+#define CBR_RG_RX_ULG_LNALG_BIAS_SZ 4 -+#define CBR_RG_RX_ULG_TZ_GC_MSK 0x0000c000 -+#define CBR_RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff -+#define CBR_RG_RX_ULG_TZ_GC_SFT 14 -+#define CBR_RG_RX_ULG_TZ_GC_HI 15 -+#define CBR_RG_RX_ULG_TZ_GC_SZ 2 -+#define CBR_RG_RX_ULG_TZ_CAP_MSK 0x00070000 -+#define CBR_RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff -+#define CBR_RG_RX_ULG_TZ_CAP_SFT 16 -+#define CBR_RG_RX_ULG_TZ_CAP_HI 18 -+#define CBR_RG_RX_ULG_TZ_CAP_SZ 3 -+#define CBR_RG_HPF1_FAST_SET_X_MSK 0x00000001 -+#define CBR_RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe -+#define CBR_RG_HPF1_FAST_SET_X_SFT 0 -+#define CBR_RG_HPF1_FAST_SET_X_HI 0 -+#define CBR_RG_HPF1_FAST_SET_X_SZ 1 -+#define CBR_RG_HPF1_FAST_SET_Y_MSK 0x00000002 -+#define CBR_RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd -+#define CBR_RG_HPF1_FAST_SET_Y_SFT 1 -+#define CBR_RG_HPF1_FAST_SET_Y_HI 1 -+#define CBR_RG_HPF1_FAST_SET_Y_SZ 1 -+#define CBR_RG_HPF1_FAST_SET_Z_MSK 0x00000004 -+#define CBR_RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb -+#define CBR_RG_HPF1_FAST_SET_Z_SFT 2 -+#define CBR_RG_HPF1_FAST_SET_Z_HI 2 -+#define CBR_RG_HPF1_FAST_SET_Z_SZ 1 -+#define CBR_RG_HPF_T1A_MSK 0x00000018 -+#define CBR_RG_HPF_T1A_I_MSK 0xffffffe7 -+#define CBR_RG_HPF_T1A_SFT 3 -+#define CBR_RG_HPF_T1A_HI 4 -+#define CBR_RG_HPF_T1A_SZ 2 -+#define CBR_RG_HPF_T1B_MSK 0x00000060 -+#define CBR_RG_HPF_T1B_I_MSK 0xffffff9f -+#define CBR_RG_HPF_T1B_SFT 5 -+#define CBR_RG_HPF_T1B_HI 6 -+#define CBR_RG_HPF_T1B_SZ 2 -+#define CBR_RG_HPF_T1C_MSK 0x00000180 -+#define CBR_RG_HPF_T1C_I_MSK 0xfffffe7f -+#define CBR_RG_HPF_T1C_SFT 7 -+#define CBR_RG_HPF_T1C_HI 8 -+#define CBR_RG_HPF_T1C_SZ 2 -+#define CBR_RG_RX_LNA_TRI_SEL_MSK 0x00000600 -+#define CBR_RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff -+#define CBR_RG_RX_LNA_TRI_SEL_SFT 9 -+#define CBR_RG_RX_LNA_TRI_SEL_HI 10 -+#define CBR_RG_RX_LNA_TRI_SEL_SZ 2 -+#define CBR_RG_RX_LNA_SETTLE_MSK 0x00001800 -+#define CBR_RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff -+#define CBR_RG_RX_LNA_SETTLE_SFT 11 -+#define CBR_RG_RX_LNA_SETTLE_HI 12 -+#define CBR_RG_RX_LNA_SETTLE_SZ 2 -+#define CBR_RG_ADC_CLKSEL_MSK 0x00000001 -+#define CBR_RG_ADC_CLKSEL_I_MSK 0xfffffffe -+#define CBR_RG_ADC_CLKSEL_SFT 0 -+#define CBR_RG_ADC_CLKSEL_HI 0 -+#define CBR_RG_ADC_CLKSEL_SZ 1 -+#define CBR_RG_ADC_DIBIAS_MSK 0x00000006 -+#define CBR_RG_ADC_DIBIAS_I_MSK 0xfffffff9 -+#define CBR_RG_ADC_DIBIAS_SFT 1 -+#define CBR_RG_ADC_DIBIAS_HI 2 -+#define CBR_RG_ADC_DIBIAS_SZ 2 -+#define CBR_RG_ADC_DIVR_MSK 0x00000008 -+#define CBR_RG_ADC_DIVR_I_MSK 0xfffffff7 -+#define CBR_RG_ADC_DIVR_SFT 3 -+#define CBR_RG_ADC_DIVR_HI 3 -+#define CBR_RG_ADC_DIVR_SZ 1 -+#define CBR_RG_ADC_DVCMI_MSK 0x00000030 -+#define CBR_RG_ADC_DVCMI_I_MSK 0xffffffcf -+#define CBR_RG_ADC_DVCMI_SFT 4 -+#define CBR_RG_ADC_DVCMI_HI 5 -+#define CBR_RG_ADC_DVCMI_SZ 2 -+#define CBR_RG_ADC_SAMSEL_MSK 0x000003c0 -+#define CBR_RG_ADC_SAMSEL_I_MSK 0xfffffc3f -+#define CBR_RG_ADC_SAMSEL_SFT 6 -+#define CBR_RG_ADC_SAMSEL_HI 9 -+#define CBR_RG_ADC_SAMSEL_SZ 4 -+#define CBR_RG_ADC_STNBY_MSK 0x00000400 -+#define CBR_RG_ADC_STNBY_I_MSK 0xfffffbff -+#define CBR_RG_ADC_STNBY_SFT 10 -+#define CBR_RG_ADC_STNBY_HI 10 -+#define CBR_RG_ADC_STNBY_SZ 1 -+#define CBR_RG_ADC_TESTMODE_MSK 0x00000800 -+#define CBR_RG_ADC_TESTMODE_I_MSK 0xfffff7ff -+#define CBR_RG_ADC_TESTMODE_SFT 11 -+#define CBR_RG_ADC_TESTMODE_HI 11 -+#define CBR_RG_ADC_TESTMODE_SZ 1 -+#define CBR_RG_ADC_TSEL_MSK 0x0000f000 -+#define CBR_RG_ADC_TSEL_I_MSK 0xffff0fff -+#define CBR_RG_ADC_TSEL_SFT 12 -+#define CBR_RG_ADC_TSEL_HI 15 -+#define CBR_RG_ADC_TSEL_SZ 4 -+#define CBR_RG_ADC_VRSEL_MSK 0x00030000 -+#define CBR_RG_ADC_VRSEL_I_MSK 0xfffcffff -+#define CBR_RG_ADC_VRSEL_SFT 16 -+#define CBR_RG_ADC_VRSEL_HI 17 -+#define CBR_RG_ADC_VRSEL_SZ 2 -+#define CBR_RG_DICMP_MSK 0x000c0000 -+#define CBR_RG_DICMP_I_MSK 0xfff3ffff -+#define CBR_RG_DICMP_SFT 18 -+#define CBR_RG_DICMP_HI 19 -+#define CBR_RG_DICMP_SZ 2 -+#define CBR_RG_DIOP_MSK 0x00300000 -+#define CBR_RG_DIOP_I_MSK 0xffcfffff -+#define CBR_RG_DIOP_SFT 20 -+#define CBR_RG_DIOP_HI 21 -+#define CBR_RG_DIOP_SZ 2 -+#define CBR_RG_DACI1ST_MSK 0x00000003 -+#define CBR_RG_DACI1ST_I_MSK 0xfffffffc -+#define CBR_RG_DACI1ST_SFT 0 -+#define CBR_RG_DACI1ST_HI 1 -+#define CBR_RG_DACI1ST_SZ 2 -+#define CBR_RG_TX_DACLPF_ICOURSE_MSK 0x0000000c -+#define CBR_RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3 -+#define CBR_RG_TX_DACLPF_ICOURSE_SFT 2 -+#define CBR_RG_TX_DACLPF_ICOURSE_HI 3 -+#define CBR_RG_TX_DACLPF_ICOURSE_SZ 2 -+#define CBR_RG_TX_DACLPF_IFINE_MSK 0x00000030 -+#define CBR_RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf -+#define CBR_RG_TX_DACLPF_IFINE_SFT 4 -+#define CBR_RG_TX_DACLPF_IFINE_HI 5 -+#define CBR_RG_TX_DACLPF_IFINE_SZ 2 -+#define CBR_RG_TX_DACLPF_VCM_MSK 0x000000c0 -+#define CBR_RG_TX_DACLPF_VCM_I_MSK 0xffffff3f -+#define CBR_RG_TX_DACLPF_VCM_SFT 6 -+#define CBR_RG_TX_DACLPF_VCM_HI 7 -+#define CBR_RG_TX_DACLPF_VCM_SZ 2 -+#define CBR_RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100 -+#define CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff -+#define CBR_RG_TX_DAC_CKEDGE_SEL_SFT 8 -+#define CBR_RG_TX_DAC_CKEDGE_SEL_HI 8 -+#define CBR_RG_TX_DAC_CKEDGE_SEL_SZ 1 -+#define CBR_RG_TX_DAC_IBIAS_MSK 0x00000600 -+#define CBR_RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff -+#define CBR_RG_TX_DAC_IBIAS_SFT 9 -+#define CBR_RG_TX_DAC_IBIAS_HI 10 -+#define CBR_RG_TX_DAC_IBIAS_SZ 2 -+#define CBR_RG_TX_DAC_OS_MSK 0x00003800 -+#define CBR_RG_TX_DAC_OS_I_MSK 0xffffc7ff -+#define CBR_RG_TX_DAC_OS_SFT 11 -+#define CBR_RG_TX_DAC_OS_HI 13 -+#define CBR_RG_TX_DAC_OS_SZ 3 -+#define CBR_RG_TX_DAC_RCAL_MSK 0x0000c000 -+#define CBR_RG_TX_DAC_RCAL_I_MSK 0xffff3fff -+#define CBR_RG_TX_DAC_RCAL_SFT 14 -+#define CBR_RG_TX_DAC_RCAL_HI 15 -+#define CBR_RG_TX_DAC_RCAL_SZ 2 -+#define CBR_RG_TX_DAC_TSEL_MSK 0x000f0000 -+#define CBR_RG_TX_DAC_TSEL_I_MSK 0xfff0ffff -+#define CBR_RG_TX_DAC_TSEL_SFT 16 -+#define CBR_RG_TX_DAC_TSEL_HI 19 -+#define CBR_RG_TX_DAC_TSEL_SZ 4 -+#define CBR_RG_TX_EN_VOLTAGE_IN_MSK 0x00100000 -+#define CBR_RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff -+#define CBR_RG_TX_EN_VOLTAGE_IN_SFT 20 -+#define CBR_RG_TX_EN_VOLTAGE_IN_HI 20 -+#define CBR_RG_TX_EN_VOLTAGE_IN_SZ 1 -+#define CBR_RG_TXLPF_BYPASS_MSK 0x00200000 -+#define CBR_RG_TXLPF_BYPASS_I_MSK 0xffdfffff -+#define CBR_RG_TXLPF_BYPASS_SFT 21 -+#define CBR_RG_TXLPF_BYPASS_HI 21 -+#define CBR_RG_TXLPF_BYPASS_SZ 1 -+#define CBR_RG_TXLPF_BOOSTI_MSK 0x00400000 -+#define CBR_RG_TXLPF_BOOSTI_I_MSK 0xffbfffff -+#define CBR_RG_TXLPF_BOOSTI_SFT 22 -+#define CBR_RG_TXLPF_BOOSTI_HI 22 -+#define CBR_RG_TXLPF_BOOSTI_SZ 1 -+#define CBR_RG_EN_SX_R3_MSK 0x00000001 -+#define CBR_RG_EN_SX_R3_I_MSK 0xfffffffe -+#define CBR_RG_EN_SX_R3_SFT 0 -+#define CBR_RG_EN_SX_R3_HI 0 -+#define CBR_RG_EN_SX_R3_SZ 1 -+#define CBR_RG_EN_SX_CH_MSK 0x00000002 -+#define CBR_RG_EN_SX_CH_I_MSK 0xfffffffd -+#define CBR_RG_EN_SX_CH_SFT 1 -+#define CBR_RG_EN_SX_CH_HI 1 -+#define CBR_RG_EN_SX_CH_SZ 1 -+#define CBR_RG_EN_SX_CHP_MSK 0x00000004 -+#define CBR_RG_EN_SX_CHP_I_MSK 0xfffffffb -+#define CBR_RG_EN_SX_CHP_SFT 2 -+#define CBR_RG_EN_SX_CHP_HI 2 -+#define CBR_RG_EN_SX_CHP_SZ 1 -+#define CBR_RG_EN_SX_DIVCK_MSK 0x00000008 -+#define CBR_RG_EN_SX_DIVCK_I_MSK 0xfffffff7 -+#define CBR_RG_EN_SX_DIVCK_SFT 3 -+#define CBR_RG_EN_SX_DIVCK_HI 3 -+#define CBR_RG_EN_SX_DIVCK_SZ 1 -+#define CBR_RG_EN_SX_VCOBF_MSK 0x00000010 -+#define CBR_RG_EN_SX_VCOBF_I_MSK 0xffffffef -+#define CBR_RG_EN_SX_VCOBF_SFT 4 -+#define CBR_RG_EN_SX_VCOBF_HI 4 -+#define CBR_RG_EN_SX_VCOBF_SZ 1 -+#define CBR_RG_EN_SX_VCO_MSK 0x00000020 -+#define CBR_RG_EN_SX_VCO_I_MSK 0xffffffdf -+#define CBR_RG_EN_SX_VCO_SFT 5 -+#define CBR_RG_EN_SX_VCO_HI 5 -+#define CBR_RG_EN_SX_VCO_SZ 1 -+#define CBR_RG_EN_SX_MOD_MSK 0x00000040 -+#define CBR_RG_EN_SX_MOD_I_MSK 0xffffffbf -+#define CBR_RG_EN_SX_MOD_SFT 6 -+#define CBR_RG_EN_SX_MOD_HI 6 -+#define CBR_RG_EN_SX_MOD_SZ 1 -+#define CBR_RG_EN_SX_LCK_MSK 0x00000080 -+#define CBR_RG_EN_SX_LCK_I_MSK 0xffffff7f -+#define CBR_RG_EN_SX_LCK_SFT 7 -+#define CBR_RG_EN_SX_LCK_HI 7 -+#define CBR_RG_EN_SX_LCK_SZ 1 -+#define CBR_RG_EN_SX_DITHER_MSK 0x00000100 -+#define CBR_RG_EN_SX_DITHER_I_MSK 0xfffffeff -+#define CBR_RG_EN_SX_DITHER_SFT 8 -+#define CBR_RG_EN_SX_DITHER_HI 8 -+#define CBR_RG_EN_SX_DITHER_SZ 1 -+#define CBR_RG_EN_SX_DELCAL_MSK 0x00000200 -+#define CBR_RG_EN_SX_DELCAL_I_MSK 0xfffffdff -+#define CBR_RG_EN_SX_DELCAL_SFT 9 -+#define CBR_RG_EN_SX_DELCAL_HI 9 -+#define CBR_RG_EN_SX_DELCAL_SZ 1 -+#define CBR_RG_EN_SX_PC_BYPASS_MSK 0x00000400 -+#define CBR_RG_EN_SX_PC_BYPASS_I_MSK 0xfffffbff -+#define CBR_RG_EN_SX_PC_BYPASS_SFT 10 -+#define CBR_RG_EN_SX_PC_BYPASS_HI 10 -+#define CBR_RG_EN_SX_PC_BYPASS_SZ 1 -+#define CBR_RG_EN_SX_VT_MON_MSK 0x00000800 -+#define CBR_RG_EN_SX_VT_MON_I_MSK 0xfffff7ff -+#define CBR_RG_EN_SX_VT_MON_SFT 11 -+#define CBR_RG_EN_SX_VT_MON_HI 11 -+#define CBR_RG_EN_SX_VT_MON_SZ 1 -+#define CBR_RG_EN_SX_VT_MON_DG_MSK 0x00001000 -+#define CBR_RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff -+#define CBR_RG_EN_SX_VT_MON_DG_SFT 12 -+#define CBR_RG_EN_SX_VT_MON_DG_HI 12 -+#define CBR_RG_EN_SX_VT_MON_DG_SZ 1 -+#define CBR_RG_EN_SX_DIV_MSK 0x00002000 -+#define CBR_RG_EN_SX_DIV_I_MSK 0xffffdfff -+#define CBR_RG_EN_SX_DIV_SFT 13 -+#define CBR_RG_EN_SX_DIV_HI 13 -+#define CBR_RG_EN_SX_DIV_SZ 1 -+#define CBR_RG_EN_SX_LPF_MSK 0x00004000 -+#define CBR_RG_EN_SX_LPF_I_MSK 0xffffbfff -+#define CBR_RG_EN_SX_LPF_SFT 14 -+#define CBR_RG_EN_SX_LPF_HI 14 -+#define CBR_RG_EN_SX_LPF_SZ 1 -+#define CBR_RG_SX_RFCTRL_F_MSK 0x00ffffff -+#define CBR_RG_SX_RFCTRL_F_I_MSK 0xff000000 -+#define CBR_RG_SX_RFCTRL_F_SFT 0 -+#define CBR_RG_SX_RFCTRL_F_HI 23 -+#define CBR_RG_SX_RFCTRL_F_SZ 24 -+#define CBR_RG_SX_SEL_CP_MSK 0x0f000000 -+#define CBR_RG_SX_SEL_CP_I_MSK 0xf0ffffff -+#define CBR_RG_SX_SEL_CP_SFT 24 -+#define CBR_RG_SX_SEL_CP_HI 27 -+#define CBR_RG_SX_SEL_CP_SZ 4 -+#define CBR_RG_SX_SEL_CS_MSK 0xf0000000 -+#define CBR_RG_SX_SEL_CS_I_MSK 0x0fffffff -+#define CBR_RG_SX_SEL_CS_SFT 28 -+#define CBR_RG_SX_SEL_CS_HI 31 -+#define CBR_RG_SX_SEL_CS_SZ 4 -+#define CBR_RG_SX_RFCTRL_CH_MSK 0x000007ff -+#define CBR_RG_SX_RFCTRL_CH_I_MSK 0xfffff800 -+#define CBR_RG_SX_RFCTRL_CH_SFT 0 -+#define CBR_RG_SX_RFCTRL_CH_HI 10 -+#define CBR_RG_SX_RFCTRL_CH_SZ 11 -+#define CBR_RG_SX_SEL_C3_MSK 0x00007800 -+#define CBR_RG_SX_SEL_C3_I_MSK 0xffff87ff -+#define CBR_RG_SX_SEL_C3_SFT 11 -+#define CBR_RG_SX_SEL_C3_HI 14 -+#define CBR_RG_SX_SEL_C3_SZ 4 -+#define CBR_RG_SX_SEL_RS_MSK 0x000f8000 -+#define CBR_RG_SX_SEL_RS_I_MSK 0xfff07fff -+#define CBR_RG_SX_SEL_RS_SFT 15 -+#define CBR_RG_SX_SEL_RS_HI 19 -+#define CBR_RG_SX_SEL_RS_SZ 5 -+#define CBR_RG_SX_SEL_R3_MSK 0x01f00000 -+#define CBR_RG_SX_SEL_R3_I_MSK 0xfe0fffff -+#define CBR_RG_SX_SEL_R3_SFT 20 -+#define CBR_RG_SX_SEL_R3_HI 24 -+#define CBR_RG_SX_SEL_R3_SZ 5 -+#define CBR_RG_SX_SEL_ICHP_MSK 0x0000001f -+#define CBR_RG_SX_SEL_ICHP_I_MSK 0xffffffe0 -+#define CBR_RG_SX_SEL_ICHP_SFT 0 -+#define CBR_RG_SX_SEL_ICHP_HI 4 -+#define CBR_RG_SX_SEL_ICHP_SZ 5 -+#define CBR_RG_SX_SEL_PCHP_MSK 0x000003e0 -+#define CBR_RG_SX_SEL_PCHP_I_MSK 0xfffffc1f -+#define CBR_RG_SX_SEL_PCHP_SFT 5 -+#define CBR_RG_SX_SEL_PCHP_HI 9 -+#define CBR_RG_SX_SEL_PCHP_SZ 5 -+#define CBR_RG_SX_SEL_CHP_REGOP_MSK 0x00003c00 -+#define CBR_RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff -+#define CBR_RG_SX_SEL_CHP_REGOP_SFT 10 -+#define CBR_RG_SX_SEL_CHP_REGOP_HI 13 -+#define CBR_RG_SX_SEL_CHP_REGOP_SZ 4 -+#define CBR_RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000 -+#define CBR_RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff -+#define CBR_RG_SX_SEL_CHP_UNIOP_SFT 14 -+#define CBR_RG_SX_SEL_CHP_UNIOP_HI 17 -+#define CBR_RG_SX_SEL_CHP_UNIOP_SZ 4 -+#define CBR_RG_SX_CHP_IOST_POL_MSK 0x00040000 -+#define CBR_RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff -+#define CBR_RG_SX_CHP_IOST_POL_SFT 18 -+#define CBR_RG_SX_CHP_IOST_POL_HI 18 -+#define CBR_RG_SX_CHP_IOST_POL_SZ 1 -+#define CBR_RG_SX_CHP_IOST_MSK 0x00380000 -+#define CBR_RG_SX_CHP_IOST_I_MSK 0xffc7ffff -+#define CBR_RG_SX_CHP_IOST_SFT 19 -+#define CBR_RG_SX_CHP_IOST_HI 21 -+#define CBR_RG_SX_CHP_IOST_SZ 3 -+#define CBR_RG_SX_PFDSEL_MSK 0x00400000 -+#define CBR_RG_SX_PFDSEL_I_MSK 0xffbfffff -+#define CBR_RG_SX_PFDSEL_SFT 22 -+#define CBR_RG_SX_PFDSEL_HI 22 -+#define CBR_RG_SX_PFDSEL_SZ 1 -+#define CBR_RG_SX_PFD_SET_MSK 0x00800000 -+#define CBR_RG_SX_PFD_SET_I_MSK 0xff7fffff -+#define CBR_RG_SX_PFD_SET_SFT 23 -+#define CBR_RG_SX_PFD_SET_HI 23 -+#define CBR_RG_SX_PFD_SET_SZ 1 -+#define CBR_RG_SX_PFD_SET1_MSK 0x01000000 -+#define CBR_RG_SX_PFD_SET1_I_MSK 0xfeffffff -+#define CBR_RG_SX_PFD_SET1_SFT 24 -+#define CBR_RG_SX_PFD_SET1_HI 24 -+#define CBR_RG_SX_PFD_SET1_SZ 1 -+#define CBR_RG_SX_PFD_SET2_MSK 0x02000000 -+#define CBR_RG_SX_PFD_SET2_I_MSK 0xfdffffff -+#define CBR_RG_SX_PFD_SET2_SFT 25 -+#define CBR_RG_SX_PFD_SET2_HI 25 -+#define CBR_RG_SX_PFD_SET2_SZ 1 -+#define CBR_RG_SX_VBNCAS_SEL_MSK 0x04000000 -+#define CBR_RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff -+#define CBR_RG_SX_VBNCAS_SEL_SFT 26 -+#define CBR_RG_SX_VBNCAS_SEL_HI 26 -+#define CBR_RG_SX_VBNCAS_SEL_SZ 1 -+#define CBR_RG_SX_PFD_RST_H_MSK 0x08000000 -+#define CBR_RG_SX_PFD_RST_H_I_MSK 0xf7ffffff -+#define CBR_RG_SX_PFD_RST_H_SFT 27 -+#define CBR_RG_SX_PFD_RST_H_HI 27 -+#define CBR_RG_SX_PFD_RST_H_SZ 1 -+#define CBR_RG_SX_PFD_TRUP_MSK 0x10000000 -+#define CBR_RG_SX_PFD_TRUP_I_MSK 0xefffffff -+#define CBR_RG_SX_PFD_TRUP_SFT 28 -+#define CBR_RG_SX_PFD_TRUP_HI 28 -+#define CBR_RG_SX_PFD_TRUP_SZ 1 -+#define CBR_RG_SX_PFD_TRDN_MSK 0x20000000 -+#define CBR_RG_SX_PFD_TRDN_I_MSK 0xdfffffff -+#define CBR_RG_SX_PFD_TRDN_SFT 29 -+#define CBR_RG_SX_PFD_TRDN_HI 29 -+#define CBR_RG_SX_PFD_TRDN_SZ 1 -+#define CBR_RG_SX_PFD_TRSEL_MSK 0x40000000 -+#define CBR_RG_SX_PFD_TRSEL_I_MSK 0xbfffffff -+#define CBR_RG_SX_PFD_TRSEL_SFT 30 -+#define CBR_RG_SX_PFD_TRSEL_HI 30 -+#define CBR_RG_SX_PFD_TRSEL_SZ 1 -+#define CBR_RG_SX_VCOBA_R_MSK 0x00000007 -+#define CBR_RG_SX_VCOBA_R_I_MSK 0xfffffff8 -+#define CBR_RG_SX_VCOBA_R_SFT 0 -+#define CBR_RG_SX_VCOBA_R_HI 2 -+#define CBR_RG_SX_VCOBA_R_SZ 3 -+#define CBR_RG_SX_VCORSEL_MSK 0x000000f8 -+#define CBR_RG_SX_VCORSEL_I_MSK 0xffffff07 -+#define CBR_RG_SX_VCORSEL_SFT 3 -+#define CBR_RG_SX_VCORSEL_HI 7 -+#define CBR_RG_SX_VCORSEL_SZ 5 -+#define CBR_RG_SX_VCOCUSEL_MSK 0x00000f00 -+#define CBR_RG_SX_VCOCUSEL_I_MSK 0xfffff0ff -+#define CBR_RG_SX_VCOCUSEL_SFT 8 -+#define CBR_RG_SX_VCOCUSEL_HI 11 -+#define CBR_RG_SX_VCOCUSEL_SZ 4 -+#define CBR_RG_SX_RXBFSEL_MSK 0x0000f000 -+#define CBR_RG_SX_RXBFSEL_I_MSK 0xffff0fff -+#define CBR_RG_SX_RXBFSEL_SFT 12 -+#define CBR_RG_SX_RXBFSEL_HI 15 -+#define CBR_RG_SX_RXBFSEL_SZ 4 -+#define CBR_RG_SX_TXBFSEL_MSK 0x000f0000 -+#define CBR_RG_SX_TXBFSEL_I_MSK 0xfff0ffff -+#define CBR_RG_SX_TXBFSEL_SFT 16 -+#define CBR_RG_SX_TXBFSEL_HI 19 -+#define CBR_RG_SX_TXBFSEL_SZ 4 -+#define CBR_RG_SX_VCOBFSEL_MSK 0x00f00000 -+#define CBR_RG_SX_VCOBFSEL_I_MSK 0xff0fffff -+#define CBR_RG_SX_VCOBFSEL_SFT 20 -+#define CBR_RG_SX_VCOBFSEL_HI 23 -+#define CBR_RG_SX_VCOBFSEL_SZ 4 -+#define CBR_RG_SX_DIVBFSEL_MSK 0x0f000000 -+#define CBR_RG_SX_DIVBFSEL_I_MSK 0xf0ffffff -+#define CBR_RG_SX_DIVBFSEL_SFT 24 -+#define CBR_RG_SX_DIVBFSEL_HI 27 -+#define CBR_RG_SX_DIVBFSEL_SZ 4 -+#define CBR_RG_SX_GNDR_SEL_MSK 0xf0000000 -+#define CBR_RG_SX_GNDR_SEL_I_MSK 0x0fffffff -+#define CBR_RG_SX_GNDR_SEL_SFT 28 -+#define CBR_RG_SX_GNDR_SEL_HI 31 -+#define CBR_RG_SX_GNDR_SEL_SZ 4 -+#define CBR_RG_SX_DITHER_WEIGHT_MSK 0x00000003 -+#define CBR_RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc -+#define CBR_RG_SX_DITHER_WEIGHT_SFT 0 -+#define CBR_RG_SX_DITHER_WEIGHT_HI 1 -+#define CBR_RG_SX_DITHER_WEIGHT_SZ 2 -+#define CBR_RG_SX_MOD_ERRCMP_MSK 0x0000000c -+#define CBR_RG_SX_MOD_ERRCMP_I_MSK 0xfffffff3 -+#define CBR_RG_SX_MOD_ERRCMP_SFT 2 -+#define CBR_RG_SX_MOD_ERRCMP_HI 3 -+#define CBR_RG_SX_MOD_ERRCMP_SZ 2 -+#define CBR_RG_SX_MOD_ORDER_MSK 0x00000030 -+#define CBR_RG_SX_MOD_ORDER_I_MSK 0xffffffcf -+#define CBR_RG_SX_MOD_ORDER_SFT 4 -+#define CBR_RG_SX_MOD_ORDER_HI 5 -+#define CBR_RG_SX_MOD_ORDER_SZ 2 -+#define CBR_RG_SX_SDM_D1_MSK 0x00000040 -+#define CBR_RG_SX_SDM_D1_I_MSK 0xffffffbf -+#define CBR_RG_SX_SDM_D1_SFT 6 -+#define CBR_RG_SX_SDM_D1_HI 6 -+#define CBR_RG_SX_SDM_D1_SZ 1 -+#define CBR_RG_SX_SDM_D2_MSK 0x00000080 -+#define CBR_RG_SX_SDM_D2_I_MSK 0xffffff7f -+#define CBR_RG_SX_SDM_D2_SFT 7 -+#define CBR_RG_SX_SDM_D2_HI 7 -+#define CBR_RG_SX_SDM_D2_SZ 1 -+#define CBR_RG_SDM_PASS_MSK 0x00000100 -+#define CBR_RG_SDM_PASS_I_MSK 0xfffffeff -+#define CBR_RG_SDM_PASS_SFT 8 -+#define CBR_RG_SDM_PASS_HI 8 -+#define CBR_RG_SDM_PASS_SZ 1 -+#define CBR_RG_SX_RST_H_DIV_MSK 0x00000200 -+#define CBR_RG_SX_RST_H_DIV_I_MSK 0xfffffdff -+#define CBR_RG_SX_RST_H_DIV_SFT 9 -+#define CBR_RG_SX_RST_H_DIV_HI 9 -+#define CBR_RG_SX_RST_H_DIV_SZ 1 -+#define CBR_RG_SX_SDM_EDGE_MSK 0x00000400 -+#define CBR_RG_SX_SDM_EDGE_I_MSK 0xfffffbff -+#define CBR_RG_SX_SDM_EDGE_SFT 10 -+#define CBR_RG_SX_SDM_EDGE_HI 10 -+#define CBR_RG_SX_SDM_EDGE_SZ 1 -+#define CBR_RG_SX_XO_GM_MSK 0x00001800 -+#define CBR_RG_SX_XO_GM_I_MSK 0xffffe7ff -+#define CBR_RG_SX_XO_GM_SFT 11 -+#define CBR_RG_SX_XO_GM_HI 12 -+#define CBR_RG_SX_XO_GM_SZ 2 -+#define CBR_RG_SX_REFBYTWO_MSK 0x00002000 -+#define CBR_RG_SX_REFBYTWO_I_MSK 0xffffdfff -+#define CBR_RG_SX_REFBYTWO_SFT 13 -+#define CBR_RG_SX_REFBYTWO_HI 13 -+#define CBR_RG_SX_REFBYTWO_SZ 1 -+#define CBR_RG_SX_XO_SWCAP_MSK 0x0003c000 -+#define CBR_RG_SX_XO_SWCAP_I_MSK 0xfffc3fff -+#define CBR_RG_SX_XO_SWCAP_SFT 14 -+#define CBR_RG_SX_XO_SWCAP_HI 17 -+#define CBR_RG_SX_XO_SWCAP_SZ 4 -+#define CBR_RG_SX_SDMLUT_INV_MSK 0x00040000 -+#define CBR_RG_SX_SDMLUT_INV_I_MSK 0xfffbffff -+#define CBR_RG_SX_SDMLUT_INV_SFT 18 -+#define CBR_RG_SX_SDMLUT_INV_HI 18 -+#define CBR_RG_SX_SDMLUT_INV_SZ 1 -+#define CBR_RG_SX_LCKEN_MSK 0x00080000 -+#define CBR_RG_SX_LCKEN_I_MSK 0xfff7ffff -+#define CBR_RG_SX_LCKEN_SFT 19 -+#define CBR_RG_SX_LCKEN_HI 19 -+#define CBR_RG_SX_LCKEN_SZ 1 -+#define CBR_RG_SX_PREVDD_MSK 0x00f00000 -+#define CBR_RG_SX_PREVDD_I_MSK 0xff0fffff -+#define CBR_RG_SX_PREVDD_SFT 20 -+#define CBR_RG_SX_PREVDD_HI 23 -+#define CBR_RG_SX_PREVDD_SZ 4 -+#define CBR_RG_SX_PSCONTERVDD_MSK 0x0f000000 -+#define CBR_RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff -+#define CBR_RG_SX_PSCONTERVDD_SFT 24 -+#define CBR_RG_SX_PSCONTERVDD_HI 27 -+#define CBR_RG_SX_PSCONTERVDD_SZ 4 -+#define CBR_RG_SX_MOD_ERR_DELAY_MSK 0x30000000 -+#define CBR_RG_SX_MOD_ERR_DELAY_I_MSK 0xcfffffff -+#define CBR_RG_SX_MOD_ERR_DELAY_SFT 28 -+#define CBR_RG_SX_MOD_ERR_DELAY_HI 29 -+#define CBR_RG_SX_MOD_ERR_DELAY_SZ 2 -+#define CBR_RG_SX_MODDB_MSK 0x40000000 -+#define CBR_RG_SX_MODDB_I_MSK 0xbfffffff -+#define CBR_RG_SX_MODDB_SFT 30 -+#define CBR_RG_SX_MODDB_HI 30 -+#define CBR_RG_SX_MODDB_SZ 1 -+#define CBR_RG_SX_CV_CURVE_SEL_MSK 0x00000003 -+#define CBR_RG_SX_CV_CURVE_SEL_I_MSK 0xfffffffc -+#define CBR_RG_SX_CV_CURVE_SEL_SFT 0 -+#define CBR_RG_SX_CV_CURVE_SEL_HI 1 -+#define CBR_RG_SX_CV_CURVE_SEL_SZ 2 -+#define CBR_RG_SX_SEL_DELAY_MSK 0x0000007c -+#define CBR_RG_SX_SEL_DELAY_I_MSK 0xffffff83 -+#define CBR_RG_SX_SEL_DELAY_SFT 2 -+#define CBR_RG_SX_SEL_DELAY_HI 6 -+#define CBR_RG_SX_SEL_DELAY_SZ 5 -+#define CBR_RG_SX_REF_CYCLE_MSK 0x00000780 -+#define CBR_RG_SX_REF_CYCLE_I_MSK 0xfffff87f -+#define CBR_RG_SX_REF_CYCLE_SFT 7 -+#define CBR_RG_SX_REF_CYCLE_HI 10 -+#define CBR_RG_SX_REF_CYCLE_SZ 4 -+#define CBR_RG_SX_VCOBY16_MSK 0x00000800 -+#define CBR_RG_SX_VCOBY16_I_MSK 0xfffff7ff -+#define CBR_RG_SX_VCOBY16_SFT 11 -+#define CBR_RG_SX_VCOBY16_HI 11 -+#define CBR_RG_SX_VCOBY16_SZ 1 -+#define CBR_RG_SX_VCOBY32_MSK 0x00001000 -+#define CBR_RG_SX_VCOBY32_I_MSK 0xffffefff -+#define CBR_RG_SX_VCOBY32_SFT 12 -+#define CBR_RG_SX_VCOBY32_HI 12 -+#define CBR_RG_SX_VCOBY32_SZ 1 -+#define CBR_RG_SX_PH_MSK 0x00002000 -+#define CBR_RG_SX_PH_I_MSK 0xffffdfff -+#define CBR_RG_SX_PH_SFT 13 -+#define CBR_RG_SX_PH_HI 13 -+#define CBR_RG_SX_PH_SZ 1 -+#define CBR_RG_SX_PL_MSK 0x00004000 -+#define CBR_RG_SX_PL_I_MSK 0xffffbfff -+#define CBR_RG_SX_PL_SFT 14 -+#define CBR_RG_SX_PL_HI 14 -+#define CBR_RG_SX_PL_SZ 1 -+#define CBR_RG_SX_VT_MON_MODE_MSK 0x00000001 -+#define CBR_RG_SX_VT_MON_MODE_I_MSK 0xfffffffe -+#define CBR_RG_SX_VT_MON_MODE_SFT 0 -+#define CBR_RG_SX_VT_MON_MODE_HI 0 -+#define CBR_RG_SX_VT_MON_MODE_SZ 1 -+#define CBR_RG_SX_VT_TH_HI_MSK 0x00000006 -+#define CBR_RG_SX_VT_TH_HI_I_MSK 0xfffffff9 -+#define CBR_RG_SX_VT_TH_HI_SFT 1 -+#define CBR_RG_SX_VT_TH_HI_HI 2 -+#define CBR_RG_SX_VT_TH_HI_SZ 2 -+#define CBR_RG_SX_VT_TH_LO_MSK 0x00000018 -+#define CBR_RG_SX_VT_TH_LO_I_MSK 0xffffffe7 -+#define CBR_RG_SX_VT_TH_LO_SFT 3 -+#define CBR_RG_SX_VT_TH_LO_HI 4 -+#define CBR_RG_SX_VT_TH_LO_SZ 2 -+#define CBR_RG_SX_VT_SET_MSK 0x00000020 -+#define CBR_RG_SX_VT_SET_I_MSK 0xffffffdf -+#define CBR_RG_SX_VT_SET_SFT 5 -+#define CBR_RG_SX_VT_SET_HI 5 -+#define CBR_RG_SX_VT_SET_SZ 1 -+#define CBR_RG_SX_VT_MON_TMR_MSK 0x00007fc0 -+#define CBR_RG_SX_VT_MON_TMR_I_MSK 0xffff803f -+#define CBR_RG_SX_VT_MON_TMR_SFT 6 -+#define CBR_RG_SX_VT_MON_TMR_HI 14 -+#define CBR_RG_SX_VT_MON_TMR_SZ 9 -+#define CBR_RG_IDEAL_CYCLE_MSK 0x0fff8000 -+#define CBR_RG_IDEAL_CYCLE_I_MSK 0xf0007fff -+#define CBR_RG_IDEAL_CYCLE_SFT 15 -+#define CBR_RG_IDEAL_CYCLE_HI 27 -+#define CBR_RG_IDEAL_CYCLE_SZ 13 -+#define CBR_RG_EN_DP_VT_MON_MSK 0x00000001 -+#define CBR_RG_EN_DP_VT_MON_I_MSK 0xfffffffe -+#define CBR_RG_EN_DP_VT_MON_SFT 0 -+#define CBR_RG_EN_DP_VT_MON_HI 0 -+#define CBR_RG_EN_DP_VT_MON_SZ 1 -+#define CBR_RG_DP_VT_TH_HI_MSK 0x00000006 -+#define CBR_RG_DP_VT_TH_HI_I_MSK 0xfffffff9 -+#define CBR_RG_DP_VT_TH_HI_SFT 1 -+#define CBR_RG_DP_VT_TH_HI_HI 2 -+#define CBR_RG_DP_VT_TH_HI_SZ 2 -+#define CBR_RG_DP_VT_TH_LO_MSK 0x00000018 -+#define CBR_RG_DP_VT_TH_LO_I_MSK 0xffffffe7 -+#define CBR_RG_DP_VT_TH_LO_SFT 3 -+#define CBR_RG_DP_VT_TH_LO_HI 4 -+#define CBR_RG_DP_VT_TH_LO_SZ 2 -+#define CBR_RG_DP_VT_MON_TMR_MSK 0x00003fe0 -+#define CBR_RG_DP_VT_MON_TMR_I_MSK 0xffffc01f -+#define CBR_RG_DP_VT_MON_TMR_SFT 5 -+#define CBR_RG_DP_VT_MON_TMR_HI 13 -+#define CBR_RG_DP_VT_MON_TMR_SZ 9 -+#define CBR_RG_DP_CK320BY2_MSK 0x00004000 -+#define CBR_RG_DP_CK320BY2_I_MSK 0xffffbfff -+#define CBR_RG_DP_CK320BY2_SFT 14 -+#define CBR_RG_DP_CK320BY2_HI 14 -+#define CBR_RG_DP_CK320BY2_SZ 1 -+#define CBR_RG_SX_DELCTRL_MSK 0x001f8000 -+#define CBR_RG_SX_DELCTRL_I_MSK 0xffe07fff -+#define CBR_RG_SX_DELCTRL_SFT 15 -+#define CBR_RG_SX_DELCTRL_HI 20 -+#define CBR_RG_SX_DELCTRL_SZ 6 -+#define CBR_RG_DP_OD_TEST_MSK 0x00200000 -+#define CBR_RG_DP_OD_TEST_I_MSK 0xffdfffff -+#define CBR_RG_DP_OD_TEST_SFT 21 -+#define CBR_RG_DP_OD_TEST_HI 21 -+#define CBR_RG_DP_OD_TEST_SZ 1 -+#define CBR_RG_DP_BBPLL_BP_MSK 0x00000001 -+#define CBR_RG_DP_BBPLL_BP_I_MSK 0xfffffffe -+#define CBR_RG_DP_BBPLL_BP_SFT 0 -+#define CBR_RG_DP_BBPLL_BP_HI 0 -+#define CBR_RG_DP_BBPLL_BP_SZ 1 -+#define CBR_RG_DP_BBPLL_ICP_MSK 0x00000006 -+#define CBR_RG_DP_BBPLL_ICP_I_MSK 0xfffffff9 -+#define CBR_RG_DP_BBPLL_ICP_SFT 1 -+#define CBR_RG_DP_BBPLL_ICP_HI 2 -+#define CBR_RG_DP_BBPLL_ICP_SZ 2 -+#define CBR_RG_DP_BBPLL_IDUAL_MSK 0x00000018 -+#define CBR_RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7 -+#define CBR_RG_DP_BBPLL_IDUAL_SFT 3 -+#define CBR_RG_DP_BBPLL_IDUAL_HI 4 -+#define CBR_RG_DP_BBPLL_IDUAL_SZ 2 -+#define CBR_RG_DP_BBPLL_OD_TEST_MSK 0x000001e0 -+#define CBR_RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f -+#define CBR_RG_DP_BBPLL_OD_TEST_SFT 5 -+#define CBR_RG_DP_BBPLL_OD_TEST_HI 8 -+#define CBR_RG_DP_BBPLL_OD_TEST_SZ 4 -+#define CBR_RG_DP_BBPLL_PD_MSK 0x00000200 -+#define CBR_RG_DP_BBPLL_PD_I_MSK 0xfffffdff -+#define CBR_RG_DP_BBPLL_PD_SFT 9 -+#define CBR_RG_DP_BBPLL_PD_HI 9 -+#define CBR_RG_DP_BBPLL_PD_SZ 1 -+#define CBR_RG_DP_BBPLL_TESTSEL_MSK 0x00001c00 -+#define CBR_RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff -+#define CBR_RG_DP_BBPLL_TESTSEL_SFT 10 -+#define CBR_RG_DP_BBPLL_TESTSEL_HI 12 -+#define CBR_RG_DP_BBPLL_TESTSEL_SZ 3 -+#define CBR_RG_DP_BBPLL_PFD_DLY_MSK 0x00006000 -+#define CBR_RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff -+#define CBR_RG_DP_BBPLL_PFD_DLY_SFT 13 -+#define CBR_RG_DP_BBPLL_PFD_DLY_HI 14 -+#define CBR_RG_DP_BBPLL_PFD_DLY_SZ 2 -+#define CBR_RG_DP_RP_MSK 0x00038000 -+#define CBR_RG_DP_RP_I_MSK 0xfffc7fff -+#define CBR_RG_DP_RP_SFT 15 -+#define CBR_RG_DP_RP_HI 17 -+#define CBR_RG_DP_RP_SZ 3 -+#define CBR_RG_DP_RHP_MSK 0x000c0000 -+#define CBR_RG_DP_RHP_I_MSK 0xfff3ffff -+#define CBR_RG_DP_RHP_SFT 18 -+#define CBR_RG_DP_RHP_HI 19 -+#define CBR_RG_DP_RHP_SZ 2 -+#define CBR_RG_DP_DR3_MSK 0x00700000 -+#define CBR_RG_DP_DR3_I_MSK 0xff8fffff -+#define CBR_RG_DP_DR3_SFT 20 -+#define CBR_RG_DP_DR3_HI 22 -+#define CBR_RG_DP_DR3_SZ 3 -+#define CBR_RG_DP_DCP_MSK 0x07800000 -+#define CBR_RG_DP_DCP_I_MSK 0xf87fffff -+#define CBR_RG_DP_DCP_SFT 23 -+#define CBR_RG_DP_DCP_HI 26 -+#define CBR_RG_DP_DCP_SZ 4 -+#define CBR_RG_DP_DCS_MSK 0x78000000 -+#define CBR_RG_DP_DCS_I_MSK 0x87ffffff -+#define CBR_RG_DP_DCS_SFT 27 -+#define CBR_RG_DP_DCS_HI 30 -+#define CBR_RG_DP_DCS_SZ 4 -+#define CBR_RG_DP_FBDIV_MSK 0x00000fff -+#define CBR_RG_DP_FBDIV_I_MSK 0xfffff000 -+#define CBR_RG_DP_FBDIV_SFT 0 -+#define CBR_RG_DP_FBDIV_HI 11 -+#define CBR_RG_DP_FBDIV_SZ 12 -+#define CBR_RG_DP_FODIV_MSK 0x003ff000 -+#define CBR_RG_DP_FODIV_I_MSK 0xffc00fff -+#define CBR_RG_DP_FODIV_SFT 12 -+#define CBR_RG_DP_FODIV_HI 21 -+#define CBR_RG_DP_FODIV_SZ 10 -+#define CBR_RG_DP_REFDIV_MSK 0xffc00000 -+#define CBR_RG_DP_REFDIV_I_MSK 0x003fffff -+#define CBR_RG_DP_REFDIV_SFT 22 -+#define CBR_RG_DP_REFDIV_HI 31 -+#define CBR_RG_DP_REFDIV_SZ 10 -+#define CBR_RG_IDACAI_PGAG15_MSK 0x0000003f -+#define CBR_RG_IDACAI_PGAG15_I_MSK 0xffffffc0 -+#define CBR_RG_IDACAI_PGAG15_SFT 0 -+#define CBR_RG_IDACAI_PGAG15_HI 5 -+#define CBR_RG_IDACAI_PGAG15_SZ 6 -+#define CBR_RG_IDACAQ_PGAG15_MSK 0x00000fc0 -+#define CBR_RG_IDACAQ_PGAG15_I_MSK 0xfffff03f -+#define CBR_RG_IDACAQ_PGAG15_SFT 6 -+#define CBR_RG_IDACAQ_PGAG15_HI 11 -+#define CBR_RG_IDACAQ_PGAG15_SZ 6 -+#define CBR_RG_IDACAI_PGAG14_MSK 0x0003f000 -+#define CBR_RG_IDACAI_PGAG14_I_MSK 0xfffc0fff -+#define CBR_RG_IDACAI_PGAG14_SFT 12 -+#define CBR_RG_IDACAI_PGAG14_HI 17 -+#define CBR_RG_IDACAI_PGAG14_SZ 6 -+#define CBR_RG_IDACAQ_PGAG14_MSK 0x00fc0000 -+#define CBR_RG_IDACAQ_PGAG14_I_MSK 0xff03ffff -+#define CBR_RG_IDACAQ_PGAG14_SFT 18 -+#define CBR_RG_IDACAQ_PGAG14_HI 23 -+#define CBR_RG_IDACAQ_PGAG14_SZ 6 -+#define CBR_RG_IDACAI_PGAG13_MSK 0x0000003f -+#define CBR_RG_IDACAI_PGAG13_I_MSK 0xffffffc0 -+#define CBR_RG_IDACAI_PGAG13_SFT 0 -+#define CBR_RG_IDACAI_PGAG13_HI 5 -+#define CBR_RG_IDACAI_PGAG13_SZ 6 -+#define CBR_RG_IDACAQ_PGAG13_MSK 0x00000fc0 -+#define CBR_RG_IDACAQ_PGAG13_I_MSK 0xfffff03f -+#define CBR_RG_IDACAQ_PGAG13_SFT 6 -+#define CBR_RG_IDACAQ_PGAG13_HI 11 -+#define CBR_RG_IDACAQ_PGAG13_SZ 6 -+#define CBR_RG_IDACAI_PGAG12_MSK 0x0003f000 -+#define CBR_RG_IDACAI_PGAG12_I_MSK 0xfffc0fff -+#define CBR_RG_IDACAI_PGAG12_SFT 12 -+#define CBR_RG_IDACAI_PGAG12_HI 17 -+#define CBR_RG_IDACAI_PGAG12_SZ 6 -+#define CBR_RG_IDACAQ_PGAG12_MSK 0x00fc0000 -+#define CBR_RG_IDACAQ_PGAG12_I_MSK 0xff03ffff -+#define CBR_RG_IDACAQ_PGAG12_SFT 18 -+#define CBR_RG_IDACAQ_PGAG12_HI 23 -+#define CBR_RG_IDACAQ_PGAG12_SZ 6 -+#define CBR_RG_IDACAI_PGAG11_MSK 0x0000003f -+#define CBR_RG_IDACAI_PGAG11_I_MSK 0xffffffc0 -+#define CBR_RG_IDACAI_PGAG11_SFT 0 -+#define CBR_RG_IDACAI_PGAG11_HI 5 -+#define CBR_RG_IDACAI_PGAG11_SZ 6 -+#define CBR_RG_IDACAQ_PGAG11_MSK 0x00000fc0 -+#define CBR_RG_IDACAQ_PGAG11_I_MSK 0xfffff03f -+#define CBR_RG_IDACAQ_PGAG11_SFT 6 -+#define CBR_RG_IDACAQ_PGAG11_HI 11 -+#define CBR_RG_IDACAQ_PGAG11_SZ 6 -+#define CBR_RG_IDACAI_PGAG10_MSK 0x0003f000 -+#define CBR_RG_IDACAI_PGAG10_I_MSK 0xfffc0fff -+#define CBR_RG_IDACAI_PGAG10_SFT 12 -+#define CBR_RG_IDACAI_PGAG10_HI 17 -+#define CBR_RG_IDACAI_PGAG10_SZ 6 -+#define CBR_RG_IDACAQ_PGAG10_MSK 0x00fc0000 -+#define CBR_RG_IDACAQ_PGAG10_I_MSK 0xff03ffff -+#define CBR_RG_IDACAQ_PGAG10_SFT 18 -+#define CBR_RG_IDACAQ_PGAG10_HI 23 -+#define CBR_RG_IDACAQ_PGAG10_SZ 6 -+#define CBR_RG_IDACAI_PGAG9_MSK 0x0000003f -+#define CBR_RG_IDACAI_PGAG9_I_MSK 0xffffffc0 -+#define CBR_RG_IDACAI_PGAG9_SFT 0 -+#define CBR_RG_IDACAI_PGAG9_HI 5 -+#define CBR_RG_IDACAI_PGAG9_SZ 6 -+#define CBR_RG_IDACAQ_PGAG9_MSK 0x00000fc0 -+#define CBR_RG_IDACAQ_PGAG9_I_MSK 0xfffff03f -+#define CBR_RG_IDACAQ_PGAG9_SFT 6 -+#define CBR_RG_IDACAQ_PGAG9_HI 11 -+#define CBR_RG_IDACAQ_PGAG9_SZ 6 -+#define CBR_RG_IDACAI_PGAG8_MSK 0x0003f000 -+#define CBR_RG_IDACAI_PGAG8_I_MSK 0xfffc0fff -+#define CBR_RG_IDACAI_PGAG8_SFT 12 -+#define CBR_RG_IDACAI_PGAG8_HI 17 -+#define CBR_RG_IDACAI_PGAG8_SZ 6 -+#define CBR_RG_IDACAQ_PGAG8_MSK 0x00fc0000 -+#define CBR_RG_IDACAQ_PGAG8_I_MSK 0xff03ffff -+#define CBR_RG_IDACAQ_PGAG8_SFT 18 -+#define CBR_RG_IDACAQ_PGAG8_HI 23 -+#define CBR_RG_IDACAQ_PGAG8_SZ 6 -+#define CBR_RG_IDACAI_PGAG7_MSK 0x0000003f -+#define CBR_RG_IDACAI_PGAG7_I_MSK 0xffffffc0 -+#define CBR_RG_IDACAI_PGAG7_SFT 0 -+#define CBR_RG_IDACAI_PGAG7_HI 5 -+#define CBR_RG_IDACAI_PGAG7_SZ 6 -+#define CBR_RG_IDACAQ_PGAG7_MSK 0x00000fc0 -+#define CBR_RG_IDACAQ_PGAG7_I_MSK 0xfffff03f -+#define CBR_RG_IDACAQ_PGAG7_SFT 6 -+#define CBR_RG_IDACAQ_PGAG7_HI 11 -+#define CBR_RG_IDACAQ_PGAG7_SZ 6 -+#define CBR_RG_IDACAI_PGAG6_MSK 0x0003f000 -+#define CBR_RG_IDACAI_PGAG6_I_MSK 0xfffc0fff -+#define CBR_RG_IDACAI_PGAG6_SFT 12 -+#define CBR_RG_IDACAI_PGAG6_HI 17 -+#define CBR_RG_IDACAI_PGAG6_SZ 6 -+#define CBR_RG_IDACAQ_PGAG6_MSK 0x00fc0000 -+#define CBR_RG_IDACAQ_PGAG6_I_MSK 0xff03ffff -+#define CBR_RG_IDACAQ_PGAG6_SFT 18 -+#define CBR_RG_IDACAQ_PGAG6_HI 23 -+#define CBR_RG_IDACAQ_PGAG6_SZ 6 -+#define CBR_RG_IDACAI_PGAG5_MSK 0x0000003f -+#define CBR_RG_IDACAI_PGAG5_I_MSK 0xffffffc0 -+#define CBR_RG_IDACAI_PGAG5_SFT 0 -+#define CBR_RG_IDACAI_PGAG5_HI 5 -+#define CBR_RG_IDACAI_PGAG5_SZ 6 -+#define CBR_RG_IDACAQ_PGAG5_MSK 0x00000fc0 -+#define CBR_RG_IDACAQ_PGAG5_I_MSK 0xfffff03f -+#define CBR_RG_IDACAQ_PGAG5_SFT 6 -+#define CBR_RG_IDACAQ_PGAG5_HI 11 -+#define CBR_RG_IDACAQ_PGAG5_SZ 6 -+#define CBR_RG_IDACAI_PGAG4_MSK 0x0003f000 -+#define CBR_RG_IDACAI_PGAG4_I_MSK 0xfffc0fff -+#define CBR_RG_IDACAI_PGAG4_SFT 12 -+#define CBR_RG_IDACAI_PGAG4_HI 17 -+#define CBR_RG_IDACAI_PGAG4_SZ 6 -+#define CBR_RG_IDACAQ_PGAG4_MSK 0x00fc0000 -+#define CBR_RG_IDACAQ_PGAG4_I_MSK 0xff03ffff -+#define CBR_RG_IDACAQ_PGAG4_SFT 18 -+#define CBR_RG_IDACAQ_PGAG4_HI 23 -+#define CBR_RG_IDACAQ_PGAG4_SZ 6 -+#define CBR_RG_IDACAI_PGAG3_MSK 0x0000003f -+#define CBR_RG_IDACAI_PGAG3_I_MSK 0xffffffc0 -+#define CBR_RG_IDACAI_PGAG3_SFT 0 -+#define CBR_RG_IDACAI_PGAG3_HI 5 -+#define CBR_RG_IDACAI_PGAG3_SZ 6 -+#define CBR_RG_IDACAQ_PGAG3_MSK 0x00000fc0 -+#define CBR_RG_IDACAQ_PGAG3_I_MSK 0xfffff03f -+#define CBR_RG_IDACAQ_PGAG3_SFT 6 -+#define CBR_RG_IDACAQ_PGAG3_HI 11 -+#define CBR_RG_IDACAQ_PGAG3_SZ 6 -+#define CBR_RG_IDACAI_PGAG2_MSK 0x0003f000 -+#define CBR_RG_IDACAI_PGAG2_I_MSK 0xfffc0fff -+#define CBR_RG_IDACAI_PGAG2_SFT 12 -+#define CBR_RG_IDACAI_PGAG2_HI 17 -+#define CBR_RG_IDACAI_PGAG2_SZ 6 -+#define CBR_RG_IDACAQ_PGAG2_MSK 0x00fc0000 -+#define CBR_RG_IDACAQ_PGAG2_I_MSK 0xff03ffff -+#define CBR_RG_IDACAQ_PGAG2_SFT 18 -+#define CBR_RG_IDACAQ_PGAG2_HI 23 -+#define CBR_RG_IDACAQ_PGAG2_SZ 6 -+#define CBR_RG_IDACAI_PGAG1_MSK 0x0000003f -+#define CBR_RG_IDACAI_PGAG1_I_MSK 0xffffffc0 -+#define CBR_RG_IDACAI_PGAG1_SFT 0 -+#define CBR_RG_IDACAI_PGAG1_HI 5 -+#define CBR_RG_IDACAI_PGAG1_SZ 6 -+#define CBR_RG_IDACAQ_PGAG1_MSK 0x00000fc0 -+#define CBR_RG_IDACAQ_PGAG1_I_MSK 0xfffff03f -+#define CBR_RG_IDACAQ_PGAG1_SFT 6 -+#define CBR_RG_IDACAQ_PGAG1_HI 11 -+#define CBR_RG_IDACAQ_PGAG1_SZ 6 -+#define CBR_RG_IDACAI_PGAG0_MSK 0x0003f000 -+#define CBR_RG_IDACAI_PGAG0_I_MSK 0xfffc0fff -+#define CBR_RG_IDACAI_PGAG0_SFT 12 -+#define CBR_RG_IDACAI_PGAG0_HI 17 -+#define CBR_RG_IDACAI_PGAG0_SZ 6 -+#define CBR_RG_IDACAQ_PGAG0_MSK 0x00fc0000 -+#define CBR_RG_IDACAQ_PGAG0_I_MSK 0xff03ffff -+#define CBR_RG_IDACAQ_PGAG0_SFT 18 -+#define CBR_RG_IDACAQ_PGAG0_HI 23 -+#define CBR_RG_IDACAQ_PGAG0_SZ 6 -+#define CBR_RG_EN_RCAL_MSK 0x00000001 -+#define CBR_RG_EN_RCAL_I_MSK 0xfffffffe -+#define CBR_RG_EN_RCAL_SFT 0 -+#define CBR_RG_EN_RCAL_HI 0 -+#define CBR_RG_EN_RCAL_SZ 1 -+#define CBR_RG_RCAL_SPD_MSK 0x00000002 -+#define CBR_RG_RCAL_SPD_I_MSK 0xfffffffd -+#define CBR_RG_RCAL_SPD_SFT 1 -+#define CBR_RG_RCAL_SPD_HI 1 -+#define CBR_RG_RCAL_SPD_SZ 1 -+#define CBR_RG_RCAL_TMR_MSK 0x000001fc -+#define CBR_RG_RCAL_TMR_I_MSK 0xfffffe03 -+#define CBR_RG_RCAL_TMR_SFT 2 -+#define CBR_RG_RCAL_TMR_HI 8 -+#define CBR_RG_RCAL_TMR_SZ 7 -+#define CBR_RG_RCAL_CODE_CWR_MSK 0x00000200 -+#define CBR_RG_RCAL_CODE_CWR_I_MSK 0xfffffdff -+#define CBR_RG_RCAL_CODE_CWR_SFT 9 -+#define CBR_RG_RCAL_CODE_CWR_HI 9 -+#define CBR_RG_RCAL_CODE_CWR_SZ 1 -+#define CBR_RG_RCAL_CODE_CWD_MSK 0x00007c00 -+#define CBR_RG_RCAL_CODE_CWD_I_MSK 0xffff83ff -+#define CBR_RG_RCAL_CODE_CWD_SFT 10 -+#define CBR_RG_RCAL_CODE_CWD_HI 14 -+#define CBR_RG_RCAL_CODE_CWD_SZ 5 -+#define CBR_RG_SX_SUB_SEL_CWR_MSK 0x00000001 -+#define CBR_RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe -+#define CBR_RG_SX_SUB_SEL_CWR_SFT 0 -+#define CBR_RG_SX_SUB_SEL_CWR_HI 0 -+#define CBR_RG_SX_SUB_SEL_CWR_SZ 1 -+#define CBR_RG_SX_SUB_SEL_CWD_MSK 0x000000fe -+#define CBR_RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01 -+#define CBR_RG_SX_SUB_SEL_CWD_SFT 1 -+#define CBR_RG_SX_SUB_SEL_CWD_HI 7 -+#define CBR_RG_SX_SUB_SEL_CWD_SZ 7 -+#define CBR_RG_DP_BBPLL_BS_CWR_MSK 0x00000100 -+#define CBR_RG_DP_BBPLL_BS_CWR_I_MSK 0xfffffeff -+#define CBR_RG_DP_BBPLL_BS_CWR_SFT 8 -+#define CBR_RG_DP_BBPLL_BS_CWR_HI 8 -+#define CBR_RG_DP_BBPLL_BS_CWR_SZ 1 -+#define CBR_RG_DP_BBPLL_BS_CWD_MSK 0x00007e00 -+#define CBR_RG_DP_BBPLL_BS_CWD_I_MSK 0xffff81ff -+#define CBR_RG_DP_BBPLL_BS_CWD_SFT 9 -+#define CBR_RG_DP_BBPLL_BS_CWD_HI 14 -+#define CBR_RG_DP_BBPLL_BS_CWD_SZ 6 -+#define CBR_RCAL_RDY_MSK 0x00000001 -+#define CBR_RCAL_RDY_I_MSK 0xfffffffe -+#define CBR_RCAL_RDY_SFT 0 -+#define CBR_RCAL_RDY_HI 0 -+#define CBR_RCAL_RDY_SZ 1 -+#define CBR_DA_LCK_RDY_MSK 0x00000002 -+#define CBR_DA_LCK_RDY_I_MSK 0xfffffffd -+#define CBR_DA_LCK_RDY_SFT 1 -+#define CBR_DA_LCK_RDY_HI 1 -+#define CBR_DA_LCK_RDY_SZ 1 -+#define CBR_VT_MON_RDY_MSK 0x00000004 -+#define CBR_VT_MON_RDY_I_MSK 0xfffffffb -+#define CBR_VT_MON_RDY_SFT 2 -+#define CBR_VT_MON_RDY_HI 2 -+#define CBR_VT_MON_RDY_SZ 1 -+#define CBR_DP_VT_MON_RDY_MSK 0x00000008 -+#define CBR_DP_VT_MON_RDY_I_MSK 0xfffffff7 -+#define CBR_DP_VT_MON_RDY_SFT 3 -+#define CBR_DP_VT_MON_RDY_HI 3 -+#define CBR_DP_VT_MON_RDY_SZ 1 -+#define CBR_CH_RDY_MSK 0x00000010 -+#define CBR_CH_RDY_I_MSK 0xffffffef -+#define CBR_CH_RDY_SFT 4 -+#define CBR_CH_RDY_HI 4 -+#define CBR_CH_RDY_SZ 1 -+#define CBR_DA_R_CODE_LUT_MSK 0x000007c0 -+#define CBR_DA_R_CODE_LUT_I_MSK 0xfffff83f -+#define CBR_DA_R_CODE_LUT_SFT 6 -+#define CBR_DA_R_CODE_LUT_HI 10 -+#define CBR_DA_R_CODE_LUT_SZ 5 -+#define CBR_AD_SX_VT_MON_Q_MSK 0x00001800 -+#define CBR_AD_SX_VT_MON_Q_I_MSK 0xffffe7ff -+#define CBR_AD_SX_VT_MON_Q_SFT 11 -+#define CBR_AD_SX_VT_MON_Q_HI 12 -+#define CBR_AD_SX_VT_MON_Q_SZ 2 -+#define CBR_AD_DP_VT_MON_Q_MSK 0x00006000 -+#define CBR_AD_DP_VT_MON_Q_I_MSK 0xffff9fff -+#define CBR_AD_DP_VT_MON_Q_SFT 13 -+#define CBR_AD_DP_VT_MON_Q_HI 14 -+#define CBR_AD_DP_VT_MON_Q_SZ 2 -+#define CBR_DA_R_CAL_CODE_MSK 0x0000001f -+#define CBR_DA_R_CAL_CODE_I_MSK 0xffffffe0 -+#define CBR_DA_R_CAL_CODE_SFT 0 -+#define CBR_DA_R_CAL_CODE_HI 4 -+#define CBR_DA_R_CAL_CODE_SZ 5 -+#define CBR_DA_SX_SUB_SEL_MSK 0x00000fe0 -+#define CBR_DA_SX_SUB_SEL_I_MSK 0xfffff01f -+#define CBR_DA_SX_SUB_SEL_SFT 5 -+#define CBR_DA_SX_SUB_SEL_HI 11 -+#define CBR_DA_SX_SUB_SEL_SZ 7 -+#define CBR_DA_DP_BBPLL_BS_MSK 0x0003f000 -+#define CBR_DA_DP_BBPLL_BS_I_MSK 0xfffc0fff -+#define CBR_DA_DP_BBPLL_BS_SFT 12 -+#define CBR_DA_DP_BBPLL_BS_HI 17 -+#define CBR_DA_DP_BBPLL_BS_SZ 6 -+#define CBR_TX_EN_MSK 0x00000001 -+#define CBR_TX_EN_I_MSK 0xfffffffe -+#define CBR_TX_EN_SFT 0 -+#define CBR_TX_EN_HI 0 -+#define CBR_TX_EN_SZ 1 -+#define CBR_TX_CNT_RST_MSK 0x00000002 -+#define CBR_TX_CNT_RST_I_MSK 0xfffffffd -+#define CBR_TX_CNT_RST_SFT 1 -+#define CBR_TX_CNT_RST_HI 1 -+#define CBR_TX_CNT_RST_SZ 1 -+#define CBR_IFS_TIME_MSK 0x000000fc -+#define CBR_IFS_TIME_I_MSK 0xffffff03 -+#define CBR_IFS_TIME_SFT 2 -+#define CBR_IFS_TIME_HI 7 -+#define CBR_IFS_TIME_SZ 6 -+#define CBR_LENGTH_TARGET_MSK 0x000fff00 -+#define CBR_LENGTH_TARGET_I_MSK 0xfff000ff -+#define CBR_LENGTH_TARGET_SFT 8 -+#define CBR_LENGTH_TARGET_HI 19 -+#define CBR_LENGTH_TARGET_SZ 12 -+#define CBR_TX_CNT_TARGET_MSK 0xff000000 -+#define CBR_TX_CNT_TARGET_I_MSK 0x00ffffff -+#define CBR_TX_CNT_TARGET_SFT 24 -+#define CBR_TX_CNT_TARGET_HI 31 -+#define CBR_TX_CNT_TARGET_SZ 8 -+#define CBR_TC_CNT_TARGET_MSK 0x00ffffff -+#define CBR_TC_CNT_TARGET_I_MSK 0xff000000 -+#define CBR_TC_CNT_TARGET_SFT 0 -+#define CBR_TC_CNT_TARGET_HI 23 -+#define CBR_TC_CNT_TARGET_SZ 24 -+#define CBR_PLCP_PSDU_DATA_MEM_MSK 0x000000ff -+#define CBR_PLCP_PSDU_DATA_MEM_I_MSK 0xffffff00 -+#define CBR_PLCP_PSDU_DATA_MEM_SFT 0 -+#define CBR_PLCP_PSDU_DATA_MEM_HI 7 -+#define CBR_PLCP_PSDU_DATA_MEM_SZ 8 -+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK 0x00000100 -+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK 0xfffffeff -+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT 8 -+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_HI 8 -+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ 1 -+#define CBR_PLCP_BYTE_LENGTH_MSK 0x001ffe00 -+#define CBR_PLCP_BYTE_LENGTH_I_MSK 0xffe001ff -+#define CBR_PLCP_BYTE_LENGTH_SFT 9 -+#define CBR_PLCP_BYTE_LENGTH_HI 20 -+#define CBR_PLCP_BYTE_LENGTH_SZ 12 -+#define CBR_PLCP_PSDU_RATE_MSK 0x00600000 -+#define CBR_PLCP_PSDU_RATE_I_MSK 0xff9fffff -+#define CBR_PLCP_PSDU_RATE_SFT 21 -+#define CBR_PLCP_PSDU_RATE_HI 22 -+#define CBR_PLCP_PSDU_RATE_SZ 2 -+#define CBR_TAIL_TIME_MSK 0x1f800000 -+#define CBR_TAIL_TIME_I_MSK 0xe07fffff -+#define CBR_TAIL_TIME_SFT 23 -+#define CBR_TAIL_TIME_HI 28 -+#define CBR_TAIL_TIME_SZ 6 -+#define CBR_RG_O_PAD_PD_MSK 0x00000001 -+#define CBR_RG_O_PAD_PD_I_MSK 0xfffffffe -+#define CBR_RG_O_PAD_PD_SFT 0 -+#define CBR_RG_O_PAD_PD_HI 0 -+#define CBR_RG_O_PAD_PD_SZ 1 -+#define CBR_RG_I_PAD_PD_MSK 0x00000002 -+#define CBR_RG_I_PAD_PD_I_MSK 0xfffffffd -+#define CBR_RG_I_PAD_PD_SFT 1 -+#define CBR_RG_I_PAD_PD_HI 1 -+#define CBR_RG_I_PAD_PD_SZ 1 -+#define CBR_SEL_ADCKP_INV_MSK 0x00000004 -+#define CBR_SEL_ADCKP_INV_I_MSK 0xfffffffb -+#define CBR_SEL_ADCKP_INV_SFT 2 -+#define CBR_SEL_ADCKP_INV_HI 2 -+#define CBR_SEL_ADCKP_INV_SZ 1 -+#define CBR_RG_PAD_DS_MSK 0x00000008 -+#define CBR_RG_PAD_DS_I_MSK 0xfffffff7 -+#define CBR_RG_PAD_DS_SFT 3 -+#define CBR_RG_PAD_DS_HI 3 -+#define CBR_RG_PAD_DS_SZ 1 -+#define CBR_SEL_ADCKP_MUX_MSK 0x00000010 -+#define CBR_SEL_ADCKP_MUX_I_MSK 0xffffffef -+#define CBR_SEL_ADCKP_MUX_SFT 4 -+#define CBR_SEL_ADCKP_MUX_HI 4 -+#define CBR_SEL_ADCKP_MUX_SZ 1 -+#define CBR_RG_PAD_DS_CLK_MSK 0x00000020 -+#define CBR_RG_PAD_DS_CLK_I_MSK 0xffffffdf -+#define CBR_RG_PAD_DS_CLK_SFT 5 -+#define CBR_RG_PAD_DS_CLK_HI 5 -+#define CBR_RG_PAD_DS_CLK_SZ 1 -+#define CBR_INTP_SEL_MSK 0x00000200 -+#define CBR_INTP_SEL_I_MSK 0xfffffdff -+#define CBR_INTP_SEL_SFT 9 -+#define CBR_INTP_SEL_HI 9 -+#define CBR_INTP_SEL_SZ 1 -+#define CBR_IQ_SWP_MSK 0x00000400 -+#define CBR_IQ_SWP_I_MSK 0xfffffbff -+#define CBR_IQ_SWP_SFT 10 -+#define CBR_IQ_SWP_HI 10 -+#define CBR_IQ_SWP_SZ 1 -+#define CBR_RG_EN_EXT_DA_MSK 0x00000800 -+#define CBR_RG_EN_EXT_DA_I_MSK 0xfffff7ff -+#define CBR_RG_EN_EXT_DA_SFT 11 -+#define CBR_RG_EN_EXT_DA_HI 11 -+#define CBR_RG_EN_EXT_DA_SZ 1 -+#define CBR_RG_DIS_DA_OFFSET_MSK 0x00001000 -+#define CBR_RG_DIS_DA_OFFSET_I_MSK 0xffffefff -+#define CBR_RG_DIS_DA_OFFSET_SFT 12 -+#define CBR_RG_DIS_DA_OFFSET_HI 12 -+#define CBR_RG_DIS_DA_OFFSET_SZ 1 -+#define CBR_DBG_SEL_MSK 0x000f0000 -+#define CBR_DBG_SEL_I_MSK 0xfff0ffff -+#define CBR_DBG_SEL_SFT 16 -+#define CBR_DBG_SEL_HI 19 -+#define CBR_DBG_SEL_SZ 4 -+#define CBR_DBG_EN_MSK 0x00100000 -+#define CBR_DBG_EN_I_MSK 0xffefffff -+#define CBR_DBG_EN_SFT 20 -+#define CBR_DBG_EN_HI 20 -+#define CBR_DBG_EN_SZ 1 -+#define CBR_RG_PKT_GEN_TX_CNT_MSK 0xffffffff -+#define CBR_RG_PKT_GEN_TX_CNT_I_MSK 0x00000000 -+#define CBR_RG_PKT_GEN_TX_CNT_SFT 0 -+#define CBR_RG_PKT_GEN_TX_CNT_HI 31 -+#define CBR_RG_PKT_GEN_TX_CNT_SZ 32 -+#define CBR_TP_SEL_MSK 0x0000001f -+#define CBR_TP_SEL_I_MSK 0xffffffe0 -+#define CBR_TP_SEL_SFT 0 -+#define CBR_TP_SEL_HI 4 -+#define CBR_TP_SEL_SZ 5 -+#define CBR_IDEAL_IQ_EN_MSK 0x00000020 -+#define CBR_IDEAL_IQ_EN_I_MSK 0xffffffdf -+#define CBR_IDEAL_IQ_EN_SFT 5 -+#define CBR_IDEAL_IQ_EN_HI 5 -+#define CBR_IDEAL_IQ_EN_SZ 1 -+#define CBR_DATA_OUT_SEL_MSK 0x000001c0 -+#define CBR_DATA_OUT_SEL_I_MSK 0xfffffe3f -+#define CBR_DATA_OUT_SEL_SFT 6 -+#define CBR_DATA_OUT_SEL_HI 8 -+#define CBR_DATA_OUT_SEL_SZ 3 -+#define CBR_TWO_TONE_EN_MSK 0x00000200 -+#define CBR_TWO_TONE_EN_I_MSK 0xfffffdff -+#define CBR_TWO_TONE_EN_SFT 9 -+#define CBR_TWO_TONE_EN_HI 9 -+#define CBR_TWO_TONE_EN_SZ 1 -+#define CBR_FREQ_SEL_MSK 0x00ff0000 -+#define CBR_FREQ_SEL_I_MSK 0xff00ffff -+#define CBR_FREQ_SEL_SFT 16 -+#define CBR_FREQ_SEL_HI 23 -+#define CBR_FREQ_SEL_SZ 8 -+#define CBR_IQ_SCALE_MSK 0xff000000 -+#define CBR_IQ_SCALE_I_MSK 0x00ffffff -+#define CBR_IQ_SCALE_SFT 24 -+#define CBR_IQ_SCALE_HI 31 -+#define CBR_IQ_SCALE_SZ 8 -+#define CPU_QUE_POP_MSK 0x00000001 -+#define CPU_QUE_POP_I_MSK 0xfffffffe -+#define CPU_QUE_POP_SFT 0 -+#define CPU_QUE_POP_HI 0 -+#define CPU_QUE_POP_SZ 1 -+#define CPU_INT_MSK 0x00000004 -+#define CPU_INT_I_MSK 0xfffffffb -+#define CPU_INT_SFT 2 -+#define CPU_INT_HI 2 -+#define CPU_INT_SZ 1 -+#define CPU_ID_TB0_MSK 0xffffffff -+#define CPU_ID_TB0_I_MSK 0x00000000 -+#define CPU_ID_TB0_SFT 0 -+#define CPU_ID_TB0_HI 31 -+#define CPU_ID_TB0_SZ 32 -+#define CPU_ID_TB1_MSK 0xffffffff -+#define CPU_ID_TB1_I_MSK 0x00000000 -+#define CPU_ID_TB1_SFT 0 -+#define CPU_ID_TB1_HI 31 -+#define CPU_ID_TB1_SZ 32 -+#define HW_PKTID_MSK 0x000007ff -+#define HW_PKTID_I_MSK 0xfffff800 -+#define HW_PKTID_SFT 0 -+#define HW_PKTID_HI 10 -+#define HW_PKTID_SZ 11 -+#define CH0_INT_ADDR_MSK 0xffffffff -+#define CH0_INT_ADDR_I_MSK 0x00000000 -+#define CH0_INT_ADDR_SFT 0 -+#define CH0_INT_ADDR_HI 31 -+#define CH0_INT_ADDR_SZ 32 -+#define PRI_HW_PKTID_MSK 0x000007ff -+#define PRI_HW_PKTID_I_MSK 0xfffff800 -+#define PRI_HW_PKTID_SFT 0 -+#define PRI_HW_PKTID_HI 10 -+#define PRI_HW_PKTID_SZ 11 -+#define CH0_FULL_MSK 0x00000001 -+#define CH0_FULL_I_MSK 0xfffffffe -+#define CH0_FULL_SFT 0 -+#define CH0_FULL_HI 0 -+#define CH0_FULL_SZ 1 -+#define FF0_EMPTY_MSK 0x00000002 -+#define FF0_EMPTY_I_MSK 0xfffffffd -+#define FF0_EMPTY_SFT 1 -+#define FF0_EMPTY_HI 1 -+#define FF0_EMPTY_SZ 1 -+#define RLS_BUSY_MSK 0x00000200 -+#define RLS_BUSY_I_MSK 0xfffffdff -+#define RLS_BUSY_SFT 9 -+#define RLS_BUSY_HI 9 -+#define RLS_BUSY_SZ 1 -+#define RLS_COUNT_CLR_MSK 0x00000400 -+#define RLS_COUNT_CLR_I_MSK 0xfffffbff -+#define RLS_COUNT_CLR_SFT 10 -+#define RLS_COUNT_CLR_HI 10 -+#define RLS_COUNT_CLR_SZ 1 -+#define RTN_COUNT_CLR_MSK 0x00000800 -+#define RTN_COUNT_CLR_I_MSK 0xfffff7ff -+#define RTN_COUNT_CLR_SFT 11 -+#define RTN_COUNT_CLR_HI 11 -+#define RTN_COUNT_CLR_SZ 1 -+#define RLS_COUNT_MSK 0x00ff0000 -+#define RLS_COUNT_I_MSK 0xff00ffff -+#define RLS_COUNT_SFT 16 -+#define RLS_COUNT_HI 23 -+#define RLS_COUNT_SZ 8 -+#define RTN_COUNT_MSK 0xff000000 -+#define RTN_COUNT_I_MSK 0x00ffffff -+#define RTN_COUNT_SFT 24 -+#define RTN_COUNT_HI 31 -+#define RTN_COUNT_SZ 8 -+#define FF0_CNT_MSK 0x0000001f -+#define FF0_CNT_I_MSK 0xffffffe0 -+#define FF0_CNT_SFT 0 -+#define FF0_CNT_HI 4 -+#define FF0_CNT_SZ 5 -+#define FF1_CNT_MSK 0x000001e0 -+#define FF1_CNT_I_MSK 0xfffffe1f -+#define FF1_CNT_SFT 5 -+#define FF1_CNT_HI 8 -+#define FF1_CNT_SZ 4 -+#define FF3_CNT_MSK 0x00003800 -+#define FF3_CNT_I_MSK 0xffffc7ff -+#define FF3_CNT_SFT 11 -+#define FF3_CNT_HI 13 -+#define FF3_CNT_SZ 3 -+#define FF5_CNT_MSK 0x000e0000 -+#define FF5_CNT_I_MSK 0xfff1ffff -+#define FF5_CNT_SFT 17 -+#define FF5_CNT_HI 19 -+#define FF5_CNT_SZ 3 -+#define FF6_CNT_MSK 0x00700000 -+#define FF6_CNT_I_MSK 0xff8fffff -+#define FF6_CNT_SFT 20 -+#define FF6_CNT_HI 22 -+#define FF6_CNT_SZ 3 -+#define FF7_CNT_MSK 0x03800000 -+#define FF7_CNT_I_MSK 0xfc7fffff -+#define FF7_CNT_SFT 23 -+#define FF7_CNT_HI 25 -+#define FF7_CNT_SZ 3 -+#define FF8_CNT_MSK 0x1c000000 -+#define FF8_CNT_I_MSK 0xe3ffffff -+#define FF8_CNT_SFT 26 -+#define FF8_CNT_HI 28 -+#define FF8_CNT_SZ 3 -+#define FF9_CNT_MSK 0xe0000000 -+#define FF9_CNT_I_MSK 0x1fffffff -+#define FF9_CNT_SFT 29 -+#define FF9_CNT_HI 31 -+#define FF9_CNT_SZ 3 -+#define FF10_CNT_MSK 0x00000007 -+#define FF10_CNT_I_MSK 0xfffffff8 -+#define FF10_CNT_SFT 0 -+#define FF10_CNT_HI 2 -+#define FF10_CNT_SZ 3 -+#define FF11_CNT_MSK 0x00000038 -+#define FF11_CNT_I_MSK 0xffffffc7 -+#define FF11_CNT_SFT 3 -+#define FF11_CNT_HI 5 -+#define FF11_CNT_SZ 3 -+#define FF12_CNT_MSK 0x000001c0 -+#define FF12_CNT_I_MSK 0xfffffe3f -+#define FF12_CNT_SFT 6 -+#define FF12_CNT_HI 8 -+#define FF12_CNT_SZ 3 -+#define FF13_CNT_MSK 0x00000600 -+#define FF13_CNT_I_MSK 0xfffff9ff -+#define FF13_CNT_SFT 9 -+#define FF13_CNT_HI 10 -+#define FF13_CNT_SZ 2 -+#define FF14_CNT_MSK 0x00001800 -+#define FF14_CNT_I_MSK 0xffffe7ff -+#define FF14_CNT_SFT 11 -+#define FF14_CNT_HI 12 -+#define FF14_CNT_SZ 2 -+#define FF15_CNT_MSK 0x00006000 -+#define FF15_CNT_I_MSK 0xffff9fff -+#define FF15_CNT_SFT 13 -+#define FF15_CNT_HI 14 -+#define FF15_CNT_SZ 2 -+#define FF4_CNT_MSK 0x000f8000 -+#define FF4_CNT_I_MSK 0xfff07fff -+#define FF4_CNT_SFT 15 -+#define FF4_CNT_HI 19 -+#define FF4_CNT_SZ 5 -+#define FF2_CNT_MSK 0x00700000 -+#define FF2_CNT_I_MSK 0xff8fffff -+#define FF2_CNT_SFT 20 -+#define FF2_CNT_HI 22 -+#define FF2_CNT_SZ 3 -+#define CH1_FULL_MSK 0x00000002 -+#define CH1_FULL_I_MSK 0xfffffffd -+#define CH1_FULL_SFT 1 -+#define CH1_FULL_HI 1 -+#define CH1_FULL_SZ 1 -+#define CH2_FULL_MSK 0x00000004 -+#define CH2_FULL_I_MSK 0xfffffffb -+#define CH2_FULL_SFT 2 -+#define CH2_FULL_HI 2 -+#define CH2_FULL_SZ 1 -+#define CH3_FULL_MSK 0x00000008 -+#define CH3_FULL_I_MSK 0xfffffff7 -+#define CH3_FULL_SFT 3 -+#define CH3_FULL_HI 3 -+#define CH3_FULL_SZ 1 -+#define CH4_FULL_MSK 0x00000010 -+#define CH4_FULL_I_MSK 0xffffffef -+#define CH4_FULL_SFT 4 -+#define CH4_FULL_HI 4 -+#define CH4_FULL_SZ 1 -+#define CH5_FULL_MSK 0x00000020 -+#define CH5_FULL_I_MSK 0xffffffdf -+#define CH5_FULL_SFT 5 -+#define CH5_FULL_HI 5 -+#define CH5_FULL_SZ 1 -+#define CH6_FULL_MSK 0x00000040 -+#define CH6_FULL_I_MSK 0xffffffbf -+#define CH6_FULL_SFT 6 -+#define CH6_FULL_HI 6 -+#define CH6_FULL_SZ 1 -+#define CH7_FULL_MSK 0x00000080 -+#define CH7_FULL_I_MSK 0xffffff7f -+#define CH7_FULL_SFT 7 -+#define CH7_FULL_HI 7 -+#define CH7_FULL_SZ 1 -+#define CH8_FULL_MSK 0x00000100 -+#define CH8_FULL_I_MSK 0xfffffeff -+#define CH8_FULL_SFT 8 -+#define CH8_FULL_HI 8 -+#define CH8_FULL_SZ 1 -+#define CH9_FULL_MSK 0x00000200 -+#define CH9_FULL_I_MSK 0xfffffdff -+#define CH9_FULL_SFT 9 -+#define CH9_FULL_HI 9 -+#define CH9_FULL_SZ 1 -+#define CH10_FULL_MSK 0x00000400 -+#define CH10_FULL_I_MSK 0xfffffbff -+#define CH10_FULL_SFT 10 -+#define CH10_FULL_HI 10 -+#define CH10_FULL_SZ 1 -+#define CH11_FULL_MSK 0x00000800 -+#define CH11_FULL_I_MSK 0xfffff7ff -+#define CH11_FULL_SFT 11 -+#define CH11_FULL_HI 11 -+#define CH11_FULL_SZ 1 -+#define CH12_FULL_MSK 0x00001000 -+#define CH12_FULL_I_MSK 0xffffefff -+#define CH12_FULL_SFT 12 -+#define CH12_FULL_HI 12 -+#define CH12_FULL_SZ 1 -+#define CH13_FULL_MSK 0x00002000 -+#define CH13_FULL_I_MSK 0xffffdfff -+#define CH13_FULL_SFT 13 -+#define CH13_FULL_HI 13 -+#define CH13_FULL_SZ 1 -+#define CH14_FULL_MSK 0x00004000 -+#define CH14_FULL_I_MSK 0xffffbfff -+#define CH14_FULL_SFT 14 -+#define CH14_FULL_HI 14 -+#define CH14_FULL_SZ 1 -+#define CH15_FULL_MSK 0x00008000 -+#define CH15_FULL_I_MSK 0xffff7fff -+#define CH15_FULL_SFT 15 -+#define CH15_FULL_HI 15 -+#define CH15_FULL_SZ 1 -+#define HALT_CH0_MSK 0x00000001 -+#define HALT_CH0_I_MSK 0xfffffffe -+#define HALT_CH0_SFT 0 -+#define HALT_CH0_HI 0 -+#define HALT_CH0_SZ 1 -+#define HALT_CH1_MSK 0x00000002 -+#define HALT_CH1_I_MSK 0xfffffffd -+#define HALT_CH1_SFT 1 -+#define HALT_CH1_HI 1 -+#define HALT_CH1_SZ 1 -+#define HALT_CH2_MSK 0x00000004 -+#define HALT_CH2_I_MSK 0xfffffffb -+#define HALT_CH2_SFT 2 -+#define HALT_CH2_HI 2 -+#define HALT_CH2_SZ 1 -+#define HALT_CH3_MSK 0x00000008 -+#define HALT_CH3_I_MSK 0xfffffff7 -+#define HALT_CH3_SFT 3 -+#define HALT_CH3_HI 3 -+#define HALT_CH3_SZ 1 -+#define HALT_CH4_MSK 0x00000010 -+#define HALT_CH4_I_MSK 0xffffffef -+#define HALT_CH4_SFT 4 -+#define HALT_CH4_HI 4 -+#define HALT_CH4_SZ 1 -+#define HALT_CH5_MSK 0x00000020 -+#define HALT_CH5_I_MSK 0xffffffdf -+#define HALT_CH5_SFT 5 -+#define HALT_CH5_HI 5 -+#define HALT_CH5_SZ 1 -+#define HALT_CH6_MSK 0x00000040 -+#define HALT_CH6_I_MSK 0xffffffbf -+#define HALT_CH6_SFT 6 -+#define HALT_CH6_HI 6 -+#define HALT_CH6_SZ 1 -+#define HALT_CH7_MSK 0x00000080 -+#define HALT_CH7_I_MSK 0xffffff7f -+#define HALT_CH7_SFT 7 -+#define HALT_CH7_HI 7 -+#define HALT_CH7_SZ 1 -+#define HALT_CH8_MSK 0x00000100 -+#define HALT_CH8_I_MSK 0xfffffeff -+#define HALT_CH8_SFT 8 -+#define HALT_CH8_HI 8 -+#define HALT_CH8_SZ 1 -+#define HALT_CH9_MSK 0x00000200 -+#define HALT_CH9_I_MSK 0xfffffdff -+#define HALT_CH9_SFT 9 -+#define HALT_CH9_HI 9 -+#define HALT_CH9_SZ 1 -+#define HALT_CH10_MSK 0x00000400 -+#define HALT_CH10_I_MSK 0xfffffbff -+#define HALT_CH10_SFT 10 -+#define HALT_CH10_HI 10 -+#define HALT_CH10_SZ 1 -+#define HALT_CH11_MSK 0x00000800 -+#define HALT_CH11_I_MSK 0xfffff7ff -+#define HALT_CH11_SFT 11 -+#define HALT_CH11_HI 11 -+#define HALT_CH11_SZ 1 -+#define HALT_CH12_MSK 0x00001000 -+#define HALT_CH12_I_MSK 0xffffefff -+#define HALT_CH12_SFT 12 -+#define HALT_CH12_HI 12 -+#define HALT_CH12_SZ 1 -+#define HALT_CH13_MSK 0x00002000 -+#define HALT_CH13_I_MSK 0xffffdfff -+#define HALT_CH13_SFT 13 -+#define HALT_CH13_HI 13 -+#define HALT_CH13_SZ 1 -+#define HALT_CH14_MSK 0x00004000 -+#define HALT_CH14_I_MSK 0xffffbfff -+#define HALT_CH14_SFT 14 -+#define HALT_CH14_HI 14 -+#define HALT_CH14_SZ 1 -+#define HALT_CH15_MSK 0x00008000 -+#define HALT_CH15_I_MSK 0xffff7fff -+#define HALT_CH15_SFT 15 -+#define HALT_CH15_HI 15 -+#define HALT_CH15_SZ 1 -+#define STOP_MBOX_MSK 0x00010000 -+#define STOP_MBOX_I_MSK 0xfffeffff -+#define STOP_MBOX_SFT 16 -+#define STOP_MBOX_HI 16 -+#define STOP_MBOX_SZ 1 -+#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000 -+#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff -+#define MB_ERR_AUTO_HALT_EN_SFT 20 -+#define MB_ERR_AUTO_HALT_EN_HI 20 -+#define MB_ERR_AUTO_HALT_EN_SZ 1 -+#define MB_EXCEPT_CLR_MSK 0x00200000 -+#define MB_EXCEPT_CLR_I_MSK 0xffdfffff -+#define MB_EXCEPT_CLR_SFT 21 -+#define MB_EXCEPT_CLR_HI 21 -+#define MB_EXCEPT_CLR_SZ 1 -+#define MB_EXCEPT_CASE_MSK 0xff000000 -+#define MB_EXCEPT_CASE_I_MSK 0x00ffffff -+#define MB_EXCEPT_CASE_SFT 24 -+#define MB_EXCEPT_CASE_HI 31 -+#define MB_EXCEPT_CASE_SZ 8 -+#define MB_DBG_TIME_STEP_MSK 0x0000ffff -+#define MB_DBG_TIME_STEP_I_MSK 0xffff0000 -+#define MB_DBG_TIME_STEP_SFT 0 -+#define MB_DBG_TIME_STEP_HI 15 -+#define MB_DBG_TIME_STEP_SZ 16 -+#define DBG_TYPE_MSK 0x00030000 -+#define DBG_TYPE_I_MSK 0xfffcffff -+#define DBG_TYPE_SFT 16 -+#define DBG_TYPE_HI 17 -+#define DBG_TYPE_SZ 2 -+#define MB_DBG_CLR_MSK 0x00040000 -+#define MB_DBG_CLR_I_MSK 0xfffbffff -+#define MB_DBG_CLR_SFT 18 -+#define MB_DBG_CLR_HI 18 -+#define MB_DBG_CLR_SZ 1 -+#define DBG_ALC_LOG_EN_MSK 0x00080000 -+#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff -+#define DBG_ALC_LOG_EN_SFT 19 -+#define DBG_ALC_LOG_EN_HI 19 -+#define DBG_ALC_LOG_EN_SZ 1 -+#define MB_DBG_COUNTER_EN_MSK 0x01000000 -+#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff -+#define MB_DBG_COUNTER_EN_SFT 24 -+#define MB_DBG_COUNTER_EN_HI 24 -+#define MB_DBG_COUNTER_EN_SZ 1 -+#define MB_DBG_EN_MSK 0x80000000 -+#define MB_DBG_EN_I_MSK 0x7fffffff -+#define MB_DBG_EN_SFT 31 -+#define MB_DBG_EN_HI 31 -+#define MB_DBG_EN_SZ 1 -+#define MB_DBG_RECORD_CNT_MSK 0x0000ffff -+#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000 -+#define MB_DBG_RECORD_CNT_SFT 0 -+#define MB_DBG_RECORD_CNT_HI 15 -+#define MB_DBG_RECORD_CNT_SZ 16 -+#define MB_DBG_LENGTH_MSK 0xffff0000 -+#define MB_DBG_LENGTH_I_MSK 0x0000ffff -+#define MB_DBG_LENGTH_SFT 16 -+#define MB_DBG_LENGTH_HI 31 -+#define MB_DBG_LENGTH_SZ 16 -+#define MB_DBG_CFG_ADDR_MSK 0xffffffff -+#define MB_DBG_CFG_ADDR_I_MSK 0x00000000 -+#define MB_DBG_CFG_ADDR_SFT 0 -+#define MB_DBG_CFG_ADDR_HI 31 -+#define MB_DBG_CFG_ADDR_SZ 32 -+#define DBG_HWID0_WR_EN_MSK 0x00000001 -+#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe -+#define DBG_HWID0_WR_EN_SFT 0 -+#define DBG_HWID0_WR_EN_HI 0 -+#define DBG_HWID0_WR_EN_SZ 1 -+#define DBG_HWID1_WR_EN_MSK 0x00000002 -+#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd -+#define DBG_HWID1_WR_EN_SFT 1 -+#define DBG_HWID1_WR_EN_HI 1 -+#define DBG_HWID1_WR_EN_SZ 1 -+#define DBG_HWID2_WR_EN_MSK 0x00000004 -+#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb -+#define DBG_HWID2_WR_EN_SFT 2 -+#define DBG_HWID2_WR_EN_HI 2 -+#define DBG_HWID2_WR_EN_SZ 1 -+#define DBG_HWID3_WR_EN_MSK 0x00000008 -+#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7 -+#define DBG_HWID3_WR_EN_SFT 3 -+#define DBG_HWID3_WR_EN_HI 3 -+#define DBG_HWID3_WR_EN_SZ 1 -+#define DBG_HWID4_WR_EN_MSK 0x00000010 -+#define DBG_HWID4_WR_EN_I_MSK 0xffffffef -+#define DBG_HWID4_WR_EN_SFT 4 -+#define DBG_HWID4_WR_EN_HI 4 -+#define DBG_HWID4_WR_EN_SZ 1 -+#define DBG_HWID5_WR_EN_MSK 0x00000020 -+#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf -+#define DBG_HWID5_WR_EN_SFT 5 -+#define DBG_HWID5_WR_EN_HI 5 -+#define DBG_HWID5_WR_EN_SZ 1 -+#define DBG_HWID6_WR_EN_MSK 0x00000040 -+#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf -+#define DBG_HWID6_WR_EN_SFT 6 -+#define DBG_HWID6_WR_EN_HI 6 -+#define DBG_HWID6_WR_EN_SZ 1 -+#define DBG_HWID7_WR_EN_MSK 0x00000080 -+#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f -+#define DBG_HWID7_WR_EN_SFT 7 -+#define DBG_HWID7_WR_EN_HI 7 -+#define DBG_HWID7_WR_EN_SZ 1 -+#define DBG_HWID8_WR_EN_MSK 0x00000100 -+#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff -+#define DBG_HWID8_WR_EN_SFT 8 -+#define DBG_HWID8_WR_EN_HI 8 -+#define DBG_HWID8_WR_EN_SZ 1 -+#define DBG_HWID9_WR_EN_MSK 0x00000200 -+#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff -+#define DBG_HWID9_WR_EN_SFT 9 -+#define DBG_HWID9_WR_EN_HI 9 -+#define DBG_HWID9_WR_EN_SZ 1 -+#define DBG_HWID10_WR_EN_MSK 0x00000400 -+#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff -+#define DBG_HWID10_WR_EN_SFT 10 -+#define DBG_HWID10_WR_EN_HI 10 -+#define DBG_HWID10_WR_EN_SZ 1 -+#define DBG_HWID11_WR_EN_MSK 0x00000800 -+#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff -+#define DBG_HWID11_WR_EN_SFT 11 -+#define DBG_HWID11_WR_EN_HI 11 -+#define DBG_HWID11_WR_EN_SZ 1 -+#define DBG_HWID12_WR_EN_MSK 0x00001000 -+#define DBG_HWID12_WR_EN_I_MSK 0xffffefff -+#define DBG_HWID12_WR_EN_SFT 12 -+#define DBG_HWID12_WR_EN_HI 12 -+#define DBG_HWID12_WR_EN_SZ 1 -+#define DBG_HWID13_WR_EN_MSK 0x00002000 -+#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff -+#define DBG_HWID13_WR_EN_SFT 13 -+#define DBG_HWID13_WR_EN_HI 13 -+#define DBG_HWID13_WR_EN_SZ 1 -+#define DBG_HWID14_WR_EN_MSK 0x00004000 -+#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff -+#define DBG_HWID14_WR_EN_SFT 14 -+#define DBG_HWID14_WR_EN_HI 14 -+#define DBG_HWID14_WR_EN_SZ 1 -+#define DBG_HWID15_WR_EN_MSK 0x00008000 -+#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff -+#define DBG_HWID15_WR_EN_SFT 15 -+#define DBG_HWID15_WR_EN_HI 15 -+#define DBG_HWID15_WR_EN_SZ 1 -+#define DBG_HWID0_RD_EN_MSK 0x00010000 -+#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff -+#define DBG_HWID0_RD_EN_SFT 16 -+#define DBG_HWID0_RD_EN_HI 16 -+#define DBG_HWID0_RD_EN_SZ 1 -+#define DBG_HWID1_RD_EN_MSK 0x00020000 -+#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff -+#define DBG_HWID1_RD_EN_SFT 17 -+#define DBG_HWID1_RD_EN_HI 17 -+#define DBG_HWID1_RD_EN_SZ 1 -+#define DBG_HWID2_RD_EN_MSK 0x00040000 -+#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff -+#define DBG_HWID2_RD_EN_SFT 18 -+#define DBG_HWID2_RD_EN_HI 18 -+#define DBG_HWID2_RD_EN_SZ 1 -+#define DBG_HWID3_RD_EN_MSK 0x00080000 -+#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff -+#define DBG_HWID3_RD_EN_SFT 19 -+#define DBG_HWID3_RD_EN_HI 19 -+#define DBG_HWID3_RD_EN_SZ 1 -+#define DBG_HWID4_RD_EN_MSK 0x00100000 -+#define DBG_HWID4_RD_EN_I_MSK 0xffefffff -+#define DBG_HWID4_RD_EN_SFT 20 -+#define DBG_HWID4_RD_EN_HI 20 -+#define DBG_HWID4_RD_EN_SZ 1 -+#define DBG_HWID5_RD_EN_MSK 0x00200000 -+#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff -+#define DBG_HWID5_RD_EN_SFT 21 -+#define DBG_HWID5_RD_EN_HI 21 -+#define DBG_HWID5_RD_EN_SZ 1 -+#define DBG_HWID6_RD_EN_MSK 0x00400000 -+#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff -+#define DBG_HWID6_RD_EN_SFT 22 -+#define DBG_HWID6_RD_EN_HI 22 -+#define DBG_HWID6_RD_EN_SZ 1 -+#define DBG_HWID7_RD_EN_MSK 0x00800000 -+#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff -+#define DBG_HWID7_RD_EN_SFT 23 -+#define DBG_HWID7_RD_EN_HI 23 -+#define DBG_HWID7_RD_EN_SZ 1 -+#define DBG_HWID8_RD_EN_MSK 0x01000000 -+#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff -+#define DBG_HWID8_RD_EN_SFT 24 -+#define DBG_HWID8_RD_EN_HI 24 -+#define DBG_HWID8_RD_EN_SZ 1 -+#define DBG_HWID9_RD_EN_MSK 0x02000000 -+#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff -+#define DBG_HWID9_RD_EN_SFT 25 -+#define DBG_HWID9_RD_EN_HI 25 -+#define DBG_HWID9_RD_EN_SZ 1 -+#define DBG_HWID10_RD_EN_MSK 0x04000000 -+#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff -+#define DBG_HWID10_RD_EN_SFT 26 -+#define DBG_HWID10_RD_EN_HI 26 -+#define DBG_HWID10_RD_EN_SZ 1 -+#define DBG_HWID11_RD_EN_MSK 0x08000000 -+#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff -+#define DBG_HWID11_RD_EN_SFT 27 -+#define DBG_HWID11_RD_EN_HI 27 -+#define DBG_HWID11_RD_EN_SZ 1 -+#define DBG_HWID12_RD_EN_MSK 0x10000000 -+#define DBG_HWID12_RD_EN_I_MSK 0xefffffff -+#define DBG_HWID12_RD_EN_SFT 28 -+#define DBG_HWID12_RD_EN_HI 28 -+#define DBG_HWID12_RD_EN_SZ 1 -+#define DBG_HWID13_RD_EN_MSK 0x20000000 -+#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff -+#define DBG_HWID13_RD_EN_SFT 29 -+#define DBG_HWID13_RD_EN_HI 29 -+#define DBG_HWID13_RD_EN_SZ 1 -+#define DBG_HWID14_RD_EN_MSK 0x40000000 -+#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff -+#define DBG_HWID14_RD_EN_SFT 30 -+#define DBG_HWID14_RD_EN_HI 30 -+#define DBG_HWID14_RD_EN_SZ 1 -+#define DBG_HWID15_RD_EN_MSK 0x80000000 -+#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff -+#define DBG_HWID15_RD_EN_SFT 31 -+#define DBG_HWID15_RD_EN_HI 31 -+#define DBG_HWID15_RD_EN_SZ 1 -+#define MB_OUT_QUEUE_EN_MSK 0x00000002 -+#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd -+#define MB_OUT_QUEUE_EN_SFT 1 -+#define MB_OUT_QUEUE_EN_HI 1 -+#define MB_OUT_QUEUE_EN_SZ 1 -+#define CH0_QUEUE_FLUSH_MSK 0x00000001 -+#define CH0_QUEUE_FLUSH_I_MSK 0xfffffffe -+#define CH0_QUEUE_FLUSH_SFT 0 -+#define CH0_QUEUE_FLUSH_HI 0 -+#define CH0_QUEUE_FLUSH_SZ 1 -+#define CH1_QUEUE_FLUSH_MSK 0x00000002 -+#define CH1_QUEUE_FLUSH_I_MSK 0xfffffffd -+#define CH1_QUEUE_FLUSH_SFT 1 -+#define CH1_QUEUE_FLUSH_HI 1 -+#define CH1_QUEUE_FLUSH_SZ 1 -+#define CH2_QUEUE_FLUSH_MSK 0x00000004 -+#define CH2_QUEUE_FLUSH_I_MSK 0xfffffffb -+#define CH2_QUEUE_FLUSH_SFT 2 -+#define CH2_QUEUE_FLUSH_HI 2 -+#define CH2_QUEUE_FLUSH_SZ 1 -+#define CH3_QUEUE_FLUSH_MSK 0x00000008 -+#define CH3_QUEUE_FLUSH_I_MSK 0xfffffff7 -+#define CH3_QUEUE_FLUSH_SFT 3 -+#define CH3_QUEUE_FLUSH_HI 3 -+#define CH3_QUEUE_FLUSH_SZ 1 -+#define CH4_QUEUE_FLUSH_MSK 0x00000010 -+#define CH4_QUEUE_FLUSH_I_MSK 0xffffffef -+#define CH4_QUEUE_FLUSH_SFT 4 -+#define CH4_QUEUE_FLUSH_HI 4 -+#define CH4_QUEUE_FLUSH_SZ 1 -+#define CH5_QUEUE_FLUSH_MSK 0x00000020 -+#define CH5_QUEUE_FLUSH_I_MSK 0xffffffdf -+#define CH5_QUEUE_FLUSH_SFT 5 -+#define CH5_QUEUE_FLUSH_HI 5 -+#define CH5_QUEUE_FLUSH_SZ 1 -+#define CH6_QUEUE_FLUSH_MSK 0x00000040 -+#define CH6_QUEUE_FLUSH_I_MSK 0xffffffbf -+#define CH6_QUEUE_FLUSH_SFT 6 -+#define CH6_QUEUE_FLUSH_HI 6 -+#define CH6_QUEUE_FLUSH_SZ 1 -+#define CH7_QUEUE_FLUSH_MSK 0x00000080 -+#define CH7_QUEUE_FLUSH_I_MSK 0xffffff7f -+#define CH7_QUEUE_FLUSH_SFT 7 -+#define CH7_QUEUE_FLUSH_HI 7 -+#define CH7_QUEUE_FLUSH_SZ 1 -+#define CH8_QUEUE_FLUSH_MSK 0x00000100 -+#define CH8_QUEUE_FLUSH_I_MSK 0xfffffeff -+#define CH8_QUEUE_FLUSH_SFT 8 -+#define CH8_QUEUE_FLUSH_HI 8 -+#define CH8_QUEUE_FLUSH_SZ 1 -+#define CH9_QUEUE_FLUSH_MSK 0x00000200 -+#define CH9_QUEUE_FLUSH_I_MSK 0xfffffdff -+#define CH9_QUEUE_FLUSH_SFT 9 -+#define CH9_QUEUE_FLUSH_HI 9 -+#define CH9_QUEUE_FLUSH_SZ 1 -+#define CH10_QUEUE_FLUSH_MSK 0x00000400 -+#define CH10_QUEUE_FLUSH_I_MSK 0xfffffbff -+#define CH10_QUEUE_FLUSH_SFT 10 -+#define CH10_QUEUE_FLUSH_HI 10 -+#define CH10_QUEUE_FLUSH_SZ 1 -+#define CH11_QUEUE_FLUSH_MSK 0x00000800 -+#define CH11_QUEUE_FLUSH_I_MSK 0xfffff7ff -+#define CH11_QUEUE_FLUSH_SFT 11 -+#define CH11_QUEUE_FLUSH_HI 11 -+#define CH11_QUEUE_FLUSH_SZ 1 -+#define CH12_QUEUE_FLUSH_MSK 0x00001000 -+#define CH12_QUEUE_FLUSH_I_MSK 0xffffefff -+#define CH12_QUEUE_FLUSH_SFT 12 -+#define CH12_QUEUE_FLUSH_HI 12 -+#define CH12_QUEUE_FLUSH_SZ 1 -+#define CH13_QUEUE_FLUSH_MSK 0x00002000 -+#define CH13_QUEUE_FLUSH_I_MSK 0xffffdfff -+#define CH13_QUEUE_FLUSH_SFT 13 -+#define CH13_QUEUE_FLUSH_HI 13 -+#define CH13_QUEUE_FLUSH_SZ 1 -+#define CH14_QUEUE_FLUSH_MSK 0x00004000 -+#define CH14_QUEUE_FLUSH_I_MSK 0xffffbfff -+#define CH14_QUEUE_FLUSH_SFT 14 -+#define CH14_QUEUE_FLUSH_HI 14 -+#define CH14_QUEUE_FLUSH_SZ 1 -+#define CH15_QUEUE_FLUSH_MSK 0x00008000 -+#define CH15_QUEUE_FLUSH_I_MSK 0xffff7fff -+#define CH15_QUEUE_FLUSH_SFT 15 -+#define CH15_QUEUE_FLUSH_HI 15 -+#define CH15_QUEUE_FLUSH_SZ 1 -+#define FFO0_CNT_MSK 0x0000001f -+#define FFO0_CNT_I_MSK 0xffffffe0 -+#define FFO0_CNT_SFT 0 -+#define FFO0_CNT_HI 4 -+#define FFO0_CNT_SZ 5 -+#define FFO1_CNT_MSK 0x000003e0 -+#define FFO1_CNT_I_MSK 0xfffffc1f -+#define FFO1_CNT_SFT 5 -+#define FFO1_CNT_HI 9 -+#define FFO1_CNT_SZ 5 -+#define FFO2_CNT_MSK 0x00000c00 -+#define FFO2_CNT_I_MSK 0xfffff3ff -+#define FFO2_CNT_SFT 10 -+#define FFO2_CNT_HI 11 -+#define FFO2_CNT_SZ 2 -+#define FFO3_CNT_MSK 0x000f8000 -+#define FFO3_CNT_I_MSK 0xfff07fff -+#define FFO3_CNT_SFT 15 -+#define FFO3_CNT_HI 19 -+#define FFO3_CNT_SZ 5 -+#define FFO4_CNT_MSK 0x00300000 -+#define FFO4_CNT_I_MSK 0xffcfffff -+#define FFO4_CNT_SFT 20 -+#define FFO4_CNT_HI 21 -+#define FFO4_CNT_SZ 2 -+#define FFO5_CNT_MSK 0x0e000000 -+#define FFO5_CNT_I_MSK 0xf1ffffff -+#define FFO5_CNT_SFT 25 -+#define FFO5_CNT_HI 27 -+#define FFO5_CNT_SZ 3 -+#define FFO6_CNT_MSK 0x0000000f -+#define FFO6_CNT_I_MSK 0xfffffff0 -+#define FFO6_CNT_SFT 0 -+#define FFO6_CNT_HI 3 -+#define FFO6_CNT_SZ 4 -+#define FFO7_CNT_MSK 0x000003e0 -+#define FFO7_CNT_I_MSK 0xfffffc1f -+#define FFO7_CNT_SFT 5 -+#define FFO7_CNT_HI 9 -+#define FFO7_CNT_SZ 5 -+#define FFO8_CNT_MSK 0x00007c00 -+#define FFO8_CNT_I_MSK 0xffff83ff -+#define FFO8_CNT_SFT 10 -+#define FFO8_CNT_HI 14 -+#define FFO8_CNT_SZ 5 -+#define FFO9_CNT_MSK 0x000f8000 -+#define FFO9_CNT_I_MSK 0xfff07fff -+#define FFO9_CNT_SFT 15 -+#define FFO9_CNT_HI 19 -+#define FFO9_CNT_SZ 5 -+#define FFO10_CNT_MSK 0x00f00000 -+#define FFO10_CNT_I_MSK 0xff0fffff -+#define FFO10_CNT_SFT 20 -+#define FFO10_CNT_HI 23 -+#define FFO10_CNT_SZ 4 -+#define FFO11_CNT_MSK 0x3e000000 -+#define FFO11_CNT_I_MSK 0xc1ffffff -+#define FFO11_CNT_SFT 25 -+#define FFO11_CNT_HI 29 -+#define FFO11_CNT_SZ 5 -+#define FFO12_CNT_MSK 0x00000007 -+#define FFO12_CNT_I_MSK 0xfffffff8 -+#define FFO12_CNT_SFT 0 -+#define FFO12_CNT_HI 2 -+#define FFO12_CNT_SZ 3 -+#define FFO13_CNT_MSK 0x00000060 -+#define FFO13_CNT_I_MSK 0xffffff9f -+#define FFO13_CNT_SFT 5 -+#define FFO13_CNT_HI 6 -+#define FFO13_CNT_SZ 2 -+#define FFO14_CNT_MSK 0x00000c00 -+#define FFO14_CNT_I_MSK 0xfffff3ff -+#define FFO14_CNT_SFT 10 -+#define FFO14_CNT_HI 11 -+#define FFO14_CNT_SZ 2 -+#define FFO15_CNT_MSK 0x001f8000 -+#define FFO15_CNT_I_MSK 0xffe07fff -+#define FFO15_CNT_SFT 15 -+#define FFO15_CNT_HI 20 -+#define FFO15_CNT_SZ 6 -+#define CH0_FFO_FULL_MSK 0x00000001 -+#define CH0_FFO_FULL_I_MSK 0xfffffffe -+#define CH0_FFO_FULL_SFT 0 -+#define CH0_FFO_FULL_HI 0 -+#define CH0_FFO_FULL_SZ 1 -+#define CH1_FFO_FULL_MSK 0x00000002 -+#define CH1_FFO_FULL_I_MSK 0xfffffffd -+#define CH1_FFO_FULL_SFT 1 -+#define CH1_FFO_FULL_HI 1 -+#define CH1_FFO_FULL_SZ 1 -+#define CH2_FFO_FULL_MSK 0x00000004 -+#define CH2_FFO_FULL_I_MSK 0xfffffffb -+#define CH2_FFO_FULL_SFT 2 -+#define CH2_FFO_FULL_HI 2 -+#define CH2_FFO_FULL_SZ 1 -+#define CH3_FFO_FULL_MSK 0x00000008 -+#define CH3_FFO_FULL_I_MSK 0xfffffff7 -+#define CH3_FFO_FULL_SFT 3 -+#define CH3_FFO_FULL_HI 3 -+#define CH3_FFO_FULL_SZ 1 -+#define CH4_FFO_FULL_MSK 0x00000010 -+#define CH4_FFO_FULL_I_MSK 0xffffffef -+#define CH4_FFO_FULL_SFT 4 -+#define CH4_FFO_FULL_HI 4 -+#define CH4_FFO_FULL_SZ 1 -+#define CH5_FFO_FULL_MSK 0x00000020 -+#define CH5_FFO_FULL_I_MSK 0xffffffdf -+#define CH5_FFO_FULL_SFT 5 -+#define CH5_FFO_FULL_HI 5 -+#define CH5_FFO_FULL_SZ 1 -+#define CH6_FFO_FULL_MSK 0x00000040 -+#define CH6_FFO_FULL_I_MSK 0xffffffbf -+#define CH6_FFO_FULL_SFT 6 -+#define CH6_FFO_FULL_HI 6 -+#define CH6_FFO_FULL_SZ 1 -+#define CH7_FFO_FULL_MSK 0x00000080 -+#define CH7_FFO_FULL_I_MSK 0xffffff7f -+#define CH7_FFO_FULL_SFT 7 -+#define CH7_FFO_FULL_HI 7 -+#define CH7_FFO_FULL_SZ 1 -+#define CH8_FFO_FULL_MSK 0x00000100 -+#define CH8_FFO_FULL_I_MSK 0xfffffeff -+#define CH8_FFO_FULL_SFT 8 -+#define CH8_FFO_FULL_HI 8 -+#define CH8_FFO_FULL_SZ 1 -+#define CH9_FFO_FULL_MSK 0x00000200 -+#define CH9_FFO_FULL_I_MSK 0xfffffdff -+#define CH9_FFO_FULL_SFT 9 -+#define CH9_FFO_FULL_HI 9 -+#define CH9_FFO_FULL_SZ 1 -+#define CH10_FFO_FULL_MSK 0x00000400 -+#define CH10_FFO_FULL_I_MSK 0xfffffbff -+#define CH10_FFO_FULL_SFT 10 -+#define CH10_FFO_FULL_HI 10 -+#define CH10_FFO_FULL_SZ 1 -+#define CH11_FFO_FULL_MSK 0x00000800 -+#define CH11_FFO_FULL_I_MSK 0xfffff7ff -+#define CH11_FFO_FULL_SFT 11 -+#define CH11_FFO_FULL_HI 11 -+#define CH11_FFO_FULL_SZ 1 -+#define CH12_FFO_FULL_MSK 0x00001000 -+#define CH12_FFO_FULL_I_MSK 0xffffefff -+#define CH12_FFO_FULL_SFT 12 -+#define CH12_FFO_FULL_HI 12 -+#define CH12_FFO_FULL_SZ 1 -+#define CH13_FFO_FULL_MSK 0x00002000 -+#define CH13_FFO_FULL_I_MSK 0xffffdfff -+#define CH13_FFO_FULL_SFT 13 -+#define CH13_FFO_FULL_HI 13 -+#define CH13_FFO_FULL_SZ 1 -+#define CH14_FFO_FULL_MSK 0x00004000 -+#define CH14_FFO_FULL_I_MSK 0xffffbfff -+#define CH14_FFO_FULL_SFT 14 -+#define CH14_FFO_FULL_HI 14 -+#define CH14_FFO_FULL_SZ 1 -+#define CH15_FFO_FULL_MSK 0x00008000 -+#define CH15_FFO_FULL_I_MSK 0xffff7fff -+#define CH15_FFO_FULL_SFT 15 -+#define CH15_FFO_FULL_HI 15 -+#define CH15_FFO_FULL_SZ 1 -+#define CH0_LOWTHOLD_INT_MSK 0x00000001 -+#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe -+#define CH0_LOWTHOLD_INT_SFT 0 -+#define CH0_LOWTHOLD_INT_HI 0 -+#define CH0_LOWTHOLD_INT_SZ 1 -+#define CH1_LOWTHOLD_INT_MSK 0x00000002 -+#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd -+#define CH1_LOWTHOLD_INT_SFT 1 -+#define CH1_LOWTHOLD_INT_HI 1 -+#define CH1_LOWTHOLD_INT_SZ 1 -+#define CH2_LOWTHOLD_INT_MSK 0x00000004 -+#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb -+#define CH2_LOWTHOLD_INT_SFT 2 -+#define CH2_LOWTHOLD_INT_HI 2 -+#define CH2_LOWTHOLD_INT_SZ 1 -+#define CH3_LOWTHOLD_INT_MSK 0x00000008 -+#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7 -+#define CH3_LOWTHOLD_INT_SFT 3 -+#define CH3_LOWTHOLD_INT_HI 3 -+#define CH3_LOWTHOLD_INT_SZ 1 -+#define CH4_LOWTHOLD_INT_MSK 0x00000010 -+#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef -+#define CH4_LOWTHOLD_INT_SFT 4 -+#define CH4_LOWTHOLD_INT_HI 4 -+#define CH4_LOWTHOLD_INT_SZ 1 -+#define CH5_LOWTHOLD_INT_MSK 0x00000020 -+#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf -+#define CH5_LOWTHOLD_INT_SFT 5 -+#define CH5_LOWTHOLD_INT_HI 5 -+#define CH5_LOWTHOLD_INT_SZ 1 -+#define CH6_LOWTHOLD_INT_MSK 0x00000040 -+#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf -+#define CH6_LOWTHOLD_INT_SFT 6 -+#define CH6_LOWTHOLD_INT_HI 6 -+#define CH6_LOWTHOLD_INT_SZ 1 -+#define CH7_LOWTHOLD_INT_MSK 0x00000080 -+#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f -+#define CH7_LOWTHOLD_INT_SFT 7 -+#define CH7_LOWTHOLD_INT_HI 7 -+#define CH7_LOWTHOLD_INT_SZ 1 -+#define CH8_LOWTHOLD_INT_MSK 0x00000100 -+#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff -+#define CH8_LOWTHOLD_INT_SFT 8 -+#define CH8_LOWTHOLD_INT_HI 8 -+#define CH8_LOWTHOLD_INT_SZ 1 -+#define CH9_LOWTHOLD_INT_MSK 0x00000200 -+#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff -+#define CH9_LOWTHOLD_INT_SFT 9 -+#define CH9_LOWTHOLD_INT_HI 9 -+#define CH9_LOWTHOLD_INT_SZ 1 -+#define CH10_LOWTHOLD_INT_MSK 0x00000400 -+#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff -+#define CH10_LOWTHOLD_INT_SFT 10 -+#define CH10_LOWTHOLD_INT_HI 10 -+#define CH10_LOWTHOLD_INT_SZ 1 -+#define CH11_LOWTHOLD_INT_MSK 0x00000800 -+#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff -+#define CH11_LOWTHOLD_INT_SFT 11 -+#define CH11_LOWTHOLD_INT_HI 11 -+#define CH11_LOWTHOLD_INT_SZ 1 -+#define CH12_LOWTHOLD_INT_MSK 0x00001000 -+#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff -+#define CH12_LOWTHOLD_INT_SFT 12 -+#define CH12_LOWTHOLD_INT_HI 12 -+#define CH12_LOWTHOLD_INT_SZ 1 -+#define CH13_LOWTHOLD_INT_MSK 0x00002000 -+#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff -+#define CH13_LOWTHOLD_INT_SFT 13 -+#define CH13_LOWTHOLD_INT_HI 13 -+#define CH13_LOWTHOLD_INT_SZ 1 -+#define CH14_LOWTHOLD_INT_MSK 0x00004000 -+#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff -+#define CH14_LOWTHOLD_INT_SFT 14 -+#define CH14_LOWTHOLD_INT_HI 14 -+#define CH14_LOWTHOLD_INT_SZ 1 -+#define CH15_LOWTHOLD_INT_MSK 0x00008000 -+#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff -+#define CH15_LOWTHOLD_INT_SFT 15 -+#define CH15_LOWTHOLD_INT_HI 15 -+#define CH15_LOWTHOLD_INT_SZ 1 -+#define MB_LOW_THOLD_EN_MSK 0x80000000 -+#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff -+#define MB_LOW_THOLD_EN_SFT 31 -+#define MB_LOW_THOLD_EN_HI 31 -+#define MB_LOW_THOLD_EN_SZ 1 -+#define CH0_LOWTHOLD_MSK 0x0000001f -+#define CH0_LOWTHOLD_I_MSK 0xffffffe0 -+#define CH0_LOWTHOLD_SFT 0 -+#define CH0_LOWTHOLD_HI 4 -+#define CH0_LOWTHOLD_SZ 5 -+#define CH1_LOWTHOLD_MSK 0x00001f00 -+#define CH1_LOWTHOLD_I_MSK 0xffffe0ff -+#define CH1_LOWTHOLD_SFT 8 -+#define CH1_LOWTHOLD_HI 12 -+#define CH1_LOWTHOLD_SZ 5 -+#define CH2_LOWTHOLD_MSK 0x001f0000 -+#define CH2_LOWTHOLD_I_MSK 0xffe0ffff -+#define CH2_LOWTHOLD_SFT 16 -+#define CH2_LOWTHOLD_HI 20 -+#define CH2_LOWTHOLD_SZ 5 -+#define CH3_LOWTHOLD_MSK 0x1f000000 -+#define CH3_LOWTHOLD_I_MSK 0xe0ffffff -+#define CH3_LOWTHOLD_SFT 24 -+#define CH3_LOWTHOLD_HI 28 -+#define CH3_LOWTHOLD_SZ 5 -+#define CH4_LOWTHOLD_MSK 0x0000001f -+#define CH4_LOWTHOLD_I_MSK 0xffffffe0 -+#define CH4_LOWTHOLD_SFT 0 -+#define CH4_LOWTHOLD_HI 4 -+#define CH4_LOWTHOLD_SZ 5 -+#define CH5_LOWTHOLD_MSK 0x00001f00 -+#define CH5_LOWTHOLD_I_MSK 0xffffe0ff -+#define CH5_LOWTHOLD_SFT 8 -+#define CH5_LOWTHOLD_HI 12 -+#define CH5_LOWTHOLD_SZ 5 -+#define CH6_LOWTHOLD_MSK 0x001f0000 -+#define CH6_LOWTHOLD_I_MSK 0xffe0ffff -+#define CH6_LOWTHOLD_SFT 16 -+#define CH6_LOWTHOLD_HI 20 -+#define CH6_LOWTHOLD_SZ 5 -+#define CH7_LOWTHOLD_MSK 0x1f000000 -+#define CH7_LOWTHOLD_I_MSK 0xe0ffffff -+#define CH7_LOWTHOLD_SFT 24 -+#define CH7_LOWTHOLD_HI 28 -+#define CH7_LOWTHOLD_SZ 5 -+#define CH8_LOWTHOLD_MSK 0x0000001f -+#define CH8_LOWTHOLD_I_MSK 0xffffffe0 -+#define CH8_LOWTHOLD_SFT 0 -+#define CH8_LOWTHOLD_HI 4 -+#define CH8_LOWTHOLD_SZ 5 -+#define CH9_LOWTHOLD_MSK 0x00001f00 -+#define CH9_LOWTHOLD_I_MSK 0xffffe0ff -+#define CH9_LOWTHOLD_SFT 8 -+#define CH9_LOWTHOLD_HI 12 -+#define CH9_LOWTHOLD_SZ 5 -+#define CH10_LOWTHOLD_MSK 0x001f0000 -+#define CH10_LOWTHOLD_I_MSK 0xffe0ffff -+#define CH10_LOWTHOLD_SFT 16 -+#define CH10_LOWTHOLD_HI 20 -+#define CH10_LOWTHOLD_SZ 5 -+#define CH11_LOWTHOLD_MSK 0x1f000000 -+#define CH11_LOWTHOLD_I_MSK 0xe0ffffff -+#define CH11_LOWTHOLD_SFT 24 -+#define CH11_LOWTHOLD_HI 28 -+#define CH11_LOWTHOLD_SZ 5 -+#define CH12_LOWTHOLD_MSK 0x0000001f -+#define CH12_LOWTHOLD_I_MSK 0xffffffe0 -+#define CH12_LOWTHOLD_SFT 0 -+#define CH12_LOWTHOLD_HI 4 -+#define CH12_LOWTHOLD_SZ 5 -+#define CH13_LOWTHOLD_MSK 0x00001f00 -+#define CH13_LOWTHOLD_I_MSK 0xffffe0ff -+#define CH13_LOWTHOLD_SFT 8 -+#define CH13_LOWTHOLD_HI 12 -+#define CH13_LOWTHOLD_SZ 5 -+#define CH14_LOWTHOLD_MSK 0x001f0000 -+#define CH14_LOWTHOLD_I_MSK 0xffe0ffff -+#define CH14_LOWTHOLD_SFT 16 -+#define CH14_LOWTHOLD_HI 20 -+#define CH14_LOWTHOLD_SZ 5 -+#define CH15_LOWTHOLD_MSK 0x1f000000 -+#define CH15_LOWTHOLD_I_MSK 0xe0ffffff -+#define CH15_LOWTHOLD_SFT 24 -+#define CH15_LOWTHOLD_HI 28 -+#define CH15_LOWTHOLD_SZ 5 -+#define TRASH_TIMEOUT_EN_MSK 0x00000001 -+#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe -+#define TRASH_TIMEOUT_EN_SFT 0 -+#define TRASH_TIMEOUT_EN_HI 0 -+#define TRASH_TIMEOUT_EN_SZ 1 -+#define TRASH_CAN_INT_MSK 0x00000002 -+#define TRASH_CAN_INT_I_MSK 0xfffffffd -+#define TRASH_CAN_INT_SFT 1 -+#define TRASH_CAN_INT_HI 1 -+#define TRASH_CAN_INT_SZ 1 -+#define TRASH_INT_ID_MSK 0x000007f0 -+#define TRASH_INT_ID_I_MSK 0xfffff80f -+#define TRASH_INT_ID_SFT 4 -+#define TRASH_INT_ID_HI 10 -+#define TRASH_INT_ID_SZ 7 -+#define TRASH_TIMEOUT_MSK 0x03ff0000 -+#define TRASH_TIMEOUT_I_MSK 0xfc00ffff -+#define TRASH_TIMEOUT_SFT 16 -+#define TRASH_TIMEOUT_HI 25 -+#define TRASH_TIMEOUT_SZ 10 -+#define CH0_WRFF_FLUSH_MSK 0x00000001 -+#define CH0_WRFF_FLUSH_I_MSK 0xfffffffe -+#define CH0_WRFF_FLUSH_SFT 0 -+#define CH0_WRFF_FLUSH_HI 0 -+#define CH0_WRFF_FLUSH_SZ 1 -+#define CH1_WRFF_FLUSH_MSK 0x00000002 -+#define CH1_WRFF_FLUSH_I_MSK 0xfffffffd -+#define CH1_WRFF_FLUSH_SFT 1 -+#define CH1_WRFF_FLUSH_HI 1 -+#define CH1_WRFF_FLUSH_SZ 1 -+#define CH2_WRFF_FLUSH_MSK 0x00000004 -+#define CH2_WRFF_FLUSH_I_MSK 0xfffffffb -+#define CH2_WRFF_FLUSH_SFT 2 -+#define CH2_WRFF_FLUSH_HI 2 -+#define CH2_WRFF_FLUSH_SZ 1 -+#define CH3_WRFF_FLUSH_MSK 0x00000008 -+#define CH3_WRFF_FLUSH_I_MSK 0xfffffff7 -+#define CH3_WRFF_FLUSH_SFT 3 -+#define CH3_WRFF_FLUSH_HI 3 -+#define CH3_WRFF_FLUSH_SZ 1 -+#define CH4_WRFF_FLUSH_MSK 0x00000010 -+#define CH4_WRFF_FLUSH_I_MSK 0xffffffef -+#define CH4_WRFF_FLUSH_SFT 4 -+#define CH4_WRFF_FLUSH_HI 4 -+#define CH4_WRFF_FLUSH_SZ 1 -+#define CH5_WRFF_FLUSH_MSK 0x00000020 -+#define CH5_WRFF_FLUSH_I_MSK 0xffffffdf -+#define CH5_WRFF_FLUSH_SFT 5 -+#define CH5_WRFF_FLUSH_HI 5 -+#define CH5_WRFF_FLUSH_SZ 1 -+#define CH6_WRFF_FLUSH_MSK 0x00000040 -+#define CH6_WRFF_FLUSH_I_MSK 0xffffffbf -+#define CH6_WRFF_FLUSH_SFT 6 -+#define CH6_WRFF_FLUSH_HI 6 -+#define CH6_WRFF_FLUSH_SZ 1 -+#define CH7_WRFF_FLUSH_MSK 0x00000080 -+#define CH7_WRFF_FLUSH_I_MSK 0xffffff7f -+#define CH7_WRFF_FLUSH_SFT 7 -+#define CH7_WRFF_FLUSH_HI 7 -+#define CH7_WRFF_FLUSH_SZ 1 -+#define CH8_WRFF_FLUSH_MSK 0x00000100 -+#define CH8_WRFF_FLUSH_I_MSK 0xfffffeff -+#define CH8_WRFF_FLUSH_SFT 8 -+#define CH8_WRFF_FLUSH_HI 8 -+#define CH8_WRFF_FLUSH_SZ 1 -+#define CH9_WRFF_FLUSH_MSK 0x00000200 -+#define CH9_WRFF_FLUSH_I_MSK 0xfffffdff -+#define CH9_WRFF_FLUSH_SFT 9 -+#define CH9_WRFF_FLUSH_HI 9 -+#define CH9_WRFF_FLUSH_SZ 1 -+#define CH10_WRFF_FLUSH_MSK 0x00000400 -+#define CH10_WRFF_FLUSH_I_MSK 0xfffffbff -+#define CH10_WRFF_FLUSH_SFT 10 -+#define CH10_WRFF_FLUSH_HI 10 -+#define CH10_WRFF_FLUSH_SZ 1 -+#define CH11_WRFF_FLUSH_MSK 0x00000800 -+#define CH11_WRFF_FLUSH_I_MSK 0xfffff7ff -+#define CH11_WRFF_FLUSH_SFT 11 -+#define CH11_WRFF_FLUSH_HI 11 -+#define CH11_WRFF_FLUSH_SZ 1 -+#define CH12_WRFF_FLUSH_MSK 0x00001000 -+#define CH12_WRFF_FLUSH_I_MSK 0xffffefff -+#define CH12_WRFF_FLUSH_SFT 12 -+#define CH12_WRFF_FLUSH_HI 12 -+#define CH12_WRFF_FLUSH_SZ 1 -+#define CH13_WRFF_FLUSH_MSK 0x00002000 -+#define CH13_WRFF_FLUSH_I_MSK 0xffffdfff -+#define CH13_WRFF_FLUSH_SFT 13 -+#define CH13_WRFF_FLUSH_HI 13 -+#define CH13_WRFF_FLUSH_SZ 1 -+#define CH14_WRFF_FLUSH_MSK 0x00004000 -+#define CH14_WRFF_FLUSH_I_MSK 0xffffbfff -+#define CH14_WRFF_FLUSH_SFT 14 -+#define CH14_WRFF_FLUSH_HI 14 -+#define CH14_WRFF_FLUSH_SZ 1 -+#define CPU_ID_TB2_MSK 0xffffffff -+#define CPU_ID_TB2_I_MSK 0x00000000 -+#define CPU_ID_TB2_SFT 0 -+#define CPU_ID_TB2_HI 31 -+#define CPU_ID_TB2_SZ 32 -+#define CPU_ID_TB3_MSK 0xffffffff -+#define CPU_ID_TB3_I_MSK 0x00000000 -+#define CPU_ID_TB3_SFT 0 -+#define CPU_ID_TB3_HI 31 -+#define CPU_ID_TB3_SZ 32 -+#define IQ_LOG_EN_MSK 0x00000001 -+#define IQ_LOG_EN_I_MSK 0xfffffffe -+#define IQ_LOG_EN_SFT 0 -+#define IQ_LOG_EN_HI 0 -+#define IQ_LOG_EN_SZ 1 -+#define IQ_LOG_STOP_MODE_MSK 0x00000001 -+#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe -+#define IQ_LOG_STOP_MODE_SFT 0 -+#define IQ_LOG_STOP_MODE_HI 0 -+#define IQ_LOG_STOP_MODE_SZ 1 -+#define GPIO_STOP_EN_MSK 0x00000010 -+#define GPIO_STOP_EN_I_MSK 0xffffffef -+#define GPIO_STOP_EN_SFT 4 -+#define GPIO_STOP_EN_HI 4 -+#define GPIO_STOP_EN_SZ 1 -+#define GPIO_STOP_POL_MSK 0x00000020 -+#define GPIO_STOP_POL_I_MSK 0xffffffdf -+#define GPIO_STOP_POL_SFT 5 -+#define GPIO_STOP_POL_HI 5 -+#define GPIO_STOP_POL_SZ 1 -+#define IQ_LOG_TIMER_MSK 0xffff0000 -+#define IQ_LOG_TIMER_I_MSK 0x0000ffff -+#define IQ_LOG_TIMER_SFT 16 -+#define IQ_LOG_TIMER_HI 31 -+#define IQ_LOG_TIMER_SZ 16 -+#define IQ_LOG_LEN_MSK 0x0000ffff -+#define IQ_LOG_LEN_I_MSK 0xffff0000 -+#define IQ_LOG_LEN_SFT 0 -+#define IQ_LOG_LEN_HI 15 -+#define IQ_LOG_LEN_SZ 16 -+#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff -+#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000 -+#define IQ_LOG_TAIL_ADR_SFT 0 -+#define IQ_LOG_TAIL_ADR_HI 15 -+#define IQ_LOG_TAIL_ADR_SZ 16 -+#define ALC_LENG_MSK 0x0003ffff -+#define ALC_LENG_I_MSK 0xfffc0000 -+#define ALC_LENG_SFT 0 -+#define ALC_LENG_HI 17 -+#define ALC_LENG_SZ 18 -+#define CH0_DYN_PRI_MSK 0x00300000 -+#define CH0_DYN_PRI_I_MSK 0xffcfffff -+#define CH0_DYN_PRI_SFT 20 -+#define CH0_DYN_PRI_HI 21 -+#define CH0_DYN_PRI_SZ 2 -+#define MCU_PKTID_MSK 0xffffffff -+#define MCU_PKTID_I_MSK 0x00000000 -+#define MCU_PKTID_SFT 0 -+#define MCU_PKTID_HI 31 -+#define MCU_PKTID_SZ 32 -+#define CH0_STA_PRI_MSK 0x00000003 -+#define CH0_STA_PRI_I_MSK 0xfffffffc -+#define CH0_STA_PRI_SFT 0 -+#define CH0_STA_PRI_HI 1 -+#define CH0_STA_PRI_SZ 2 -+#define CH1_STA_PRI_MSK 0x00000030 -+#define CH1_STA_PRI_I_MSK 0xffffffcf -+#define CH1_STA_PRI_SFT 4 -+#define CH1_STA_PRI_HI 5 -+#define CH1_STA_PRI_SZ 2 -+#define CH2_STA_PRI_MSK 0x00000300 -+#define CH2_STA_PRI_I_MSK 0xfffffcff -+#define CH2_STA_PRI_SFT 8 -+#define CH2_STA_PRI_HI 9 -+#define CH2_STA_PRI_SZ 2 -+#define CH3_STA_PRI_MSK 0x00003000 -+#define CH3_STA_PRI_I_MSK 0xffffcfff -+#define CH3_STA_PRI_SFT 12 -+#define CH3_STA_PRI_HI 13 -+#define CH3_STA_PRI_SZ 2 -+#define ID_TB0_MSK 0xffffffff -+#define ID_TB0_I_MSK 0x00000000 -+#define ID_TB0_SFT 0 -+#define ID_TB0_HI 31 -+#define ID_TB0_SZ 32 -+#define ID_TB1_MSK 0xffffffff -+#define ID_TB1_I_MSK 0x00000000 -+#define ID_TB1_SFT 0 -+#define ID_TB1_HI 31 -+#define ID_TB1_SZ 32 -+#define ID_MNG_HALT_MSK 0x00000010 -+#define ID_MNG_HALT_I_MSK 0xffffffef -+#define ID_MNG_HALT_SFT 4 -+#define ID_MNG_HALT_HI 4 -+#define ID_MNG_HALT_SZ 1 -+#define ID_MNG_ERR_HALT_EN_MSK 0x00000020 -+#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf -+#define ID_MNG_ERR_HALT_EN_SFT 5 -+#define ID_MNG_ERR_HALT_EN_HI 5 -+#define ID_MNG_ERR_HALT_EN_SZ 1 -+#define ID_EXCEPT_FLG_CLR_MSK 0x00000040 -+#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf -+#define ID_EXCEPT_FLG_CLR_SFT 6 -+#define ID_EXCEPT_FLG_CLR_HI 6 -+#define ID_EXCEPT_FLG_CLR_SZ 1 -+#define ID_EXCEPT_FLG_MSK 0x00000080 -+#define ID_EXCEPT_FLG_I_MSK 0xffffff7f -+#define ID_EXCEPT_FLG_SFT 7 -+#define ID_EXCEPT_FLG_HI 7 -+#define ID_EXCEPT_FLG_SZ 1 -+#define ID_FULL_MSK 0x00000001 -+#define ID_FULL_I_MSK 0xfffffffe -+#define ID_FULL_SFT 0 -+#define ID_FULL_HI 0 -+#define ID_FULL_SZ 1 -+#define ID_MNG_BUSY_MSK 0x00000002 -+#define ID_MNG_BUSY_I_MSK 0xfffffffd -+#define ID_MNG_BUSY_SFT 1 -+#define ID_MNG_BUSY_HI 1 -+#define ID_MNG_BUSY_SZ 1 -+#define REQ_LOCK_MSK 0x00000004 -+#define REQ_LOCK_I_MSK 0xfffffffb -+#define REQ_LOCK_SFT 2 -+#define REQ_LOCK_HI 2 -+#define REQ_LOCK_SZ 1 -+#define CH0_REQ_LOCK_MSK 0x00000010 -+#define CH0_REQ_LOCK_I_MSK 0xffffffef -+#define CH0_REQ_LOCK_SFT 4 -+#define CH0_REQ_LOCK_HI 4 -+#define CH0_REQ_LOCK_SZ 1 -+#define CH1_REQ_LOCK_MSK 0x00000020 -+#define CH1_REQ_LOCK_I_MSK 0xffffffdf -+#define CH1_REQ_LOCK_SFT 5 -+#define CH1_REQ_LOCK_HI 5 -+#define CH1_REQ_LOCK_SZ 1 -+#define CH2_REQ_LOCK_MSK 0x00000040 -+#define CH2_REQ_LOCK_I_MSK 0xffffffbf -+#define CH2_REQ_LOCK_SFT 6 -+#define CH2_REQ_LOCK_HI 6 -+#define CH2_REQ_LOCK_SZ 1 -+#define CH3_REQ_LOCK_MSK 0x00000080 -+#define CH3_REQ_LOCK_I_MSK 0xffffff7f -+#define CH3_REQ_LOCK_SFT 7 -+#define CH3_REQ_LOCK_HI 7 -+#define CH3_REQ_LOCK_SZ 1 -+#define REQ_LOCK_INT_EN_MSK 0x00000100 -+#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff -+#define REQ_LOCK_INT_EN_SFT 8 -+#define REQ_LOCK_INT_EN_HI 8 -+#define REQ_LOCK_INT_EN_SZ 1 -+#define REQ_LOCK_INT_MSK 0x00000200 -+#define REQ_LOCK_INT_I_MSK 0xfffffdff -+#define REQ_LOCK_INT_SFT 9 -+#define REQ_LOCK_INT_HI 9 -+#define REQ_LOCK_INT_SZ 1 -+#define MCU_ALC_READY_MSK 0x00000001 -+#define MCU_ALC_READY_I_MSK 0xfffffffe -+#define MCU_ALC_READY_SFT 0 -+#define MCU_ALC_READY_HI 0 -+#define MCU_ALC_READY_SZ 1 -+#define ALC_FAIL_MSK 0x00000002 -+#define ALC_FAIL_I_MSK 0xfffffffd -+#define ALC_FAIL_SFT 1 -+#define ALC_FAIL_HI 1 -+#define ALC_FAIL_SZ 1 -+#define ALC_BUSY_MSK 0x00000004 -+#define ALC_BUSY_I_MSK 0xfffffffb -+#define ALC_BUSY_SFT 2 -+#define ALC_BUSY_HI 2 -+#define ALC_BUSY_SZ 1 -+#define CH0_NVLD_MSK 0x00000010 -+#define CH0_NVLD_I_MSK 0xffffffef -+#define CH0_NVLD_SFT 4 -+#define CH0_NVLD_HI 4 -+#define CH0_NVLD_SZ 1 -+#define CH1_NVLD_MSK 0x00000020 -+#define CH1_NVLD_I_MSK 0xffffffdf -+#define CH1_NVLD_SFT 5 -+#define CH1_NVLD_HI 5 -+#define CH1_NVLD_SZ 1 -+#define CH2_NVLD_MSK 0x00000040 -+#define CH2_NVLD_I_MSK 0xffffffbf -+#define CH2_NVLD_SFT 6 -+#define CH2_NVLD_HI 6 -+#define CH2_NVLD_SZ 1 -+#define CH3_NVLD_MSK 0x00000080 -+#define CH3_NVLD_I_MSK 0xffffff7f -+#define CH3_NVLD_SFT 7 -+#define CH3_NVLD_HI 7 -+#define CH3_NVLD_SZ 1 -+#define ALC_INT_ID_MSK 0x00007f00 -+#define ALC_INT_ID_I_MSK 0xffff80ff -+#define ALC_INT_ID_SFT 8 -+#define ALC_INT_ID_HI 14 -+#define ALC_INT_ID_SZ 7 -+#define ALC_TIMEOUT_MSK 0x03ff0000 -+#define ALC_TIMEOUT_I_MSK 0xfc00ffff -+#define ALC_TIMEOUT_SFT 16 -+#define ALC_TIMEOUT_HI 25 -+#define ALC_TIMEOUT_SZ 10 -+#define ALC_TIMEOUT_INT_EN_MSK 0x40000000 -+#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff -+#define ALC_TIMEOUT_INT_EN_SFT 30 -+#define ALC_TIMEOUT_INT_EN_HI 30 -+#define ALC_TIMEOUT_INT_EN_SZ 1 -+#define ALC_TIMEOUT_INT_MSK 0x80000000 -+#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff -+#define ALC_TIMEOUT_INT_SFT 31 -+#define ALC_TIMEOUT_INT_HI 31 -+#define ALC_TIMEOUT_INT_SZ 1 -+#define TX_ID_COUNT_MSK 0x000000ff -+#define TX_ID_COUNT_I_MSK 0xffffff00 -+#define TX_ID_COUNT_SFT 0 -+#define TX_ID_COUNT_HI 7 -+#define TX_ID_COUNT_SZ 8 -+#define RX_ID_COUNT_MSK 0x0000ff00 -+#define RX_ID_COUNT_I_MSK 0xffff00ff -+#define RX_ID_COUNT_SFT 8 -+#define RX_ID_COUNT_HI 15 -+#define RX_ID_COUNT_SZ 8 -+#define TX_ID_THOLD_MSK 0x000000ff -+#define TX_ID_THOLD_I_MSK 0xffffff00 -+#define TX_ID_THOLD_SFT 0 -+#define TX_ID_THOLD_HI 7 -+#define TX_ID_THOLD_SZ 8 -+#define RX_ID_THOLD_MSK 0x0000ff00 -+#define RX_ID_THOLD_I_MSK 0xffff00ff -+#define RX_ID_THOLD_SFT 8 -+#define RX_ID_THOLD_HI 15 -+#define RX_ID_THOLD_SZ 8 -+#define ID_THOLD_RX_INT_MSK 0x00010000 -+#define ID_THOLD_RX_INT_I_MSK 0xfffeffff -+#define ID_THOLD_RX_INT_SFT 16 -+#define ID_THOLD_RX_INT_HI 16 -+#define ID_THOLD_RX_INT_SZ 1 -+#define RX_INT_CH_MSK 0x000e0000 -+#define RX_INT_CH_I_MSK 0xfff1ffff -+#define RX_INT_CH_SFT 17 -+#define RX_INT_CH_HI 19 -+#define RX_INT_CH_SZ 3 -+#define ID_THOLD_TX_INT_MSK 0x00100000 -+#define ID_THOLD_TX_INT_I_MSK 0xffefffff -+#define ID_THOLD_TX_INT_SFT 20 -+#define ID_THOLD_TX_INT_HI 20 -+#define ID_THOLD_TX_INT_SZ 1 -+#define TX_INT_CH_MSK 0x00e00000 -+#define TX_INT_CH_I_MSK 0xff1fffff -+#define TX_INT_CH_SFT 21 -+#define TX_INT_CH_HI 23 -+#define TX_INT_CH_SZ 3 -+#define ID_THOLD_INT_EN_MSK 0x01000000 -+#define ID_THOLD_INT_EN_I_MSK 0xfeffffff -+#define ID_THOLD_INT_EN_SFT 24 -+#define ID_THOLD_INT_EN_HI 24 -+#define ID_THOLD_INT_EN_SZ 1 -+#define TX_ID_TB0_MSK 0xffffffff -+#define TX_ID_TB0_I_MSK 0x00000000 -+#define TX_ID_TB0_SFT 0 -+#define TX_ID_TB0_HI 31 -+#define TX_ID_TB0_SZ 32 -+#define TX_ID_TB1_MSK 0xffffffff -+#define TX_ID_TB1_I_MSK 0x00000000 -+#define TX_ID_TB1_SFT 0 -+#define TX_ID_TB1_HI 31 -+#define TX_ID_TB1_SZ 32 -+#define RX_ID_TB0_MSK 0xffffffff -+#define RX_ID_TB0_I_MSK 0x00000000 -+#define RX_ID_TB0_SFT 0 -+#define RX_ID_TB0_HI 31 -+#define RX_ID_TB0_SZ 32 -+#define RX_ID_TB1_MSK 0xffffffff -+#define RX_ID_TB1_I_MSK 0x00000000 -+#define RX_ID_TB1_SFT 0 -+#define RX_ID_TB1_HI 31 -+#define RX_ID_TB1_SZ 32 -+#define DOUBLE_RLS_INT_EN_MSK 0x00000001 -+#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe -+#define DOUBLE_RLS_INT_EN_SFT 0 -+#define DOUBLE_RLS_INT_EN_HI 0 -+#define DOUBLE_RLS_INT_EN_SZ 1 -+#define ID_DOUBLE_RLS_INT_MSK 0x00000002 -+#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd -+#define ID_DOUBLE_RLS_INT_SFT 1 -+#define ID_DOUBLE_RLS_INT_HI 1 -+#define ID_DOUBLE_RLS_INT_SZ 1 -+#define DOUBLE_RLS_ID_MSK 0x00007f00 -+#define DOUBLE_RLS_ID_I_MSK 0xffff80ff -+#define DOUBLE_RLS_ID_SFT 8 -+#define DOUBLE_RLS_ID_HI 14 -+#define DOUBLE_RLS_ID_SZ 7 -+#define ID_LEN_THOLD_INT_EN_MSK 0x00000001 -+#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe -+#define ID_LEN_THOLD_INT_EN_SFT 0 -+#define ID_LEN_THOLD_INT_EN_HI 0 -+#define ID_LEN_THOLD_INT_EN_SZ 1 -+#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002 -+#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd -+#define ALL_ID_LEN_THOLD_INT_SFT 1 -+#define ALL_ID_LEN_THOLD_INT_HI 1 -+#define ALL_ID_LEN_THOLD_INT_SZ 1 -+#define TX_ID_LEN_THOLD_INT_MSK 0x00000004 -+#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb -+#define TX_ID_LEN_THOLD_INT_SFT 2 -+#define TX_ID_LEN_THOLD_INT_HI 2 -+#define TX_ID_LEN_THOLD_INT_SZ 1 -+#define RX_ID_LEN_THOLD_INT_MSK 0x00000008 -+#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7 -+#define RX_ID_LEN_THOLD_INT_SFT 3 -+#define RX_ID_LEN_THOLD_INT_HI 3 -+#define RX_ID_LEN_THOLD_INT_SZ 1 -+#define ID_TX_LEN_THOLD_MSK 0x00001ff0 -+#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f -+#define ID_TX_LEN_THOLD_SFT 4 -+#define ID_TX_LEN_THOLD_HI 12 -+#define ID_TX_LEN_THOLD_SZ 9 -+#define ID_RX_LEN_THOLD_MSK 0x003fe000 -+#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff -+#define ID_RX_LEN_THOLD_SFT 13 -+#define ID_RX_LEN_THOLD_HI 21 -+#define ID_RX_LEN_THOLD_SZ 9 -+#define ID_LEN_THOLD_MSK 0x7fc00000 -+#define ID_LEN_THOLD_I_MSK 0x803fffff -+#define ID_LEN_THOLD_SFT 22 -+#define ID_LEN_THOLD_HI 30 -+#define ID_LEN_THOLD_SZ 9 -+#define ALL_ID_ALC_LEN_MSK 0x000001ff -+#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00 -+#define ALL_ID_ALC_LEN_SFT 0 -+#define ALL_ID_ALC_LEN_HI 8 -+#define ALL_ID_ALC_LEN_SZ 9 -+#define TX_ID_ALC_LEN_MSK 0x0003fe00 -+#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff -+#define TX_ID_ALC_LEN_SFT 9 -+#define TX_ID_ALC_LEN_HI 17 -+#define TX_ID_ALC_LEN_SZ 9 -+#define RX_ID_ALC_LEN_MSK 0x07fc0000 -+#define RX_ID_ALC_LEN_I_MSK 0xf803ffff -+#define RX_ID_ALC_LEN_SFT 18 -+#define RX_ID_ALC_LEN_HI 26 -+#define RX_ID_ALC_LEN_SZ 9 -+#define CH_ARB_EN_MSK 0x00000001 -+#define CH_ARB_EN_I_MSK 0xfffffffe -+#define CH_ARB_EN_SFT 0 -+#define CH_ARB_EN_HI 0 -+#define CH_ARB_EN_SZ 1 -+#define CH_PRI1_MSK 0x00000030 -+#define CH_PRI1_I_MSK 0xffffffcf -+#define CH_PRI1_SFT 4 -+#define CH_PRI1_HI 5 -+#define CH_PRI1_SZ 2 -+#define CH_PRI2_MSK 0x00000300 -+#define CH_PRI2_I_MSK 0xfffffcff -+#define CH_PRI2_SFT 8 -+#define CH_PRI2_HI 9 -+#define CH_PRI2_SZ 2 -+#define CH_PRI3_MSK 0x00003000 -+#define CH_PRI3_I_MSK 0xffffcfff -+#define CH_PRI3_SFT 12 -+#define CH_PRI3_HI 13 -+#define CH_PRI3_SZ 2 -+#define CH_PRI4_MSK 0x00030000 -+#define CH_PRI4_I_MSK 0xfffcffff -+#define CH_PRI4_SFT 16 -+#define CH_PRI4_HI 17 -+#define CH_PRI4_SZ 2 -+#define TX_ID_REMAIN_MSK 0x0000007f -+#define TX_ID_REMAIN_I_MSK 0xffffff80 -+#define TX_ID_REMAIN_SFT 0 -+#define TX_ID_REMAIN_HI 6 -+#define TX_ID_REMAIN_SZ 7 -+#define TX_PAGE_REMAIN_MSK 0x0001ff00 -+#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff -+#define TX_PAGE_REMAIN_SFT 8 -+#define TX_PAGE_REMAIN_HI 16 -+#define TX_PAGE_REMAIN_SZ 9 -+#define ID_PAGE_MAX_SIZE_MSK 0x000001ff -+#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00 -+#define ID_PAGE_MAX_SIZE_SFT 0 -+#define ID_PAGE_MAX_SIZE_HI 8 -+#define ID_PAGE_MAX_SIZE_SZ 9 -+#define TX_PAGE_LIMIT_MSK 0x000001ff -+#define TX_PAGE_LIMIT_I_MSK 0xfffffe00 -+#define TX_PAGE_LIMIT_SFT 0 -+#define TX_PAGE_LIMIT_HI 8 -+#define TX_PAGE_LIMIT_SZ 9 -+#define TX_COUNT_LIMIT_MSK 0x00ff0000 -+#define TX_COUNT_LIMIT_I_MSK 0xff00ffff -+#define TX_COUNT_LIMIT_SFT 16 -+#define TX_COUNT_LIMIT_HI 23 -+#define TX_COUNT_LIMIT_SZ 8 -+#define TX_LIMIT_INT_MSK 0x40000000 -+#define TX_LIMIT_INT_I_MSK 0xbfffffff -+#define TX_LIMIT_INT_SFT 30 -+#define TX_LIMIT_INT_HI 30 -+#define TX_LIMIT_INT_SZ 1 -+#define TX_LIMIT_INT_EN_MSK 0x80000000 -+#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff -+#define TX_LIMIT_INT_EN_SFT 31 -+#define TX_LIMIT_INT_EN_HI 31 -+#define TX_LIMIT_INT_EN_SZ 1 -+#define TX_PAGE_USE_7_0_MSK 0x000000ff -+#define TX_PAGE_USE_7_0_I_MSK 0xffffff00 -+#define TX_PAGE_USE_7_0_SFT 0 -+#define TX_PAGE_USE_7_0_HI 7 -+#define TX_PAGE_USE_7_0_SZ 8 -+#define TX_ID_USE_5_0_MSK 0x00003f00 -+#define TX_ID_USE_5_0_I_MSK 0xffffc0ff -+#define TX_ID_USE_5_0_SFT 8 -+#define TX_ID_USE_5_0_HI 13 -+#define TX_ID_USE_5_0_SZ 6 -+#define EDCA0_FFO_CNT_MSK 0x0003c000 -+#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff -+#define EDCA0_FFO_CNT_SFT 14 -+#define EDCA0_FFO_CNT_HI 17 -+#define EDCA0_FFO_CNT_SZ 4 -+#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000 -+#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff -+#define EDCA1_FFO_CNT_3_0_SFT 18 -+#define EDCA1_FFO_CNT_3_0_HI 21 -+#define EDCA1_FFO_CNT_3_0_SZ 4 -+#define EDCA2_FFO_CNT_MSK 0x07c00000 -+#define EDCA2_FFO_CNT_I_MSK 0xf83fffff -+#define EDCA2_FFO_CNT_SFT 22 -+#define EDCA2_FFO_CNT_HI 26 -+#define EDCA2_FFO_CNT_SZ 5 -+#define EDCA3_FFO_CNT_MSK 0xf8000000 -+#define EDCA3_FFO_CNT_I_MSK 0x07ffffff -+#define EDCA3_FFO_CNT_SFT 27 -+#define EDCA3_FFO_CNT_HI 31 -+#define EDCA3_FFO_CNT_SZ 5 -+#define ID_TB2_MSK 0xffffffff -+#define ID_TB2_I_MSK 0x00000000 -+#define ID_TB2_SFT 0 -+#define ID_TB2_HI 31 -+#define ID_TB2_SZ 32 -+#define ID_TB3_MSK 0xffffffff -+#define ID_TB3_I_MSK 0x00000000 -+#define ID_TB3_SFT 0 -+#define ID_TB3_HI 31 -+#define ID_TB3_SZ 32 -+#define TX_ID_TB2_MSK 0xffffffff -+#define TX_ID_TB2_I_MSK 0x00000000 -+#define TX_ID_TB2_SFT 0 -+#define TX_ID_TB2_HI 31 -+#define TX_ID_TB2_SZ 32 -+#define TX_ID_TB3_MSK 0xffffffff -+#define TX_ID_TB3_I_MSK 0x00000000 -+#define TX_ID_TB3_SFT 0 -+#define TX_ID_TB3_HI 31 -+#define TX_ID_TB3_SZ 32 -+#define RX_ID_TB2_MSK 0xffffffff -+#define RX_ID_TB2_I_MSK 0x00000000 -+#define RX_ID_TB2_SFT 0 -+#define RX_ID_TB2_HI 31 -+#define RX_ID_TB2_SZ 32 -+#define RX_ID_TB3_MSK 0xffffffff -+#define RX_ID_TB3_I_MSK 0x00000000 -+#define RX_ID_TB3_SFT 0 -+#define RX_ID_TB3_HI 31 -+#define RX_ID_TB3_SZ 32 -+#define TX_PAGE_USE2_MSK 0x000001ff -+#define TX_PAGE_USE2_I_MSK 0xfffffe00 -+#define TX_PAGE_USE2_SFT 0 -+#define TX_PAGE_USE2_HI 8 -+#define TX_PAGE_USE2_SZ 9 -+#define TX_ID_USE2_MSK 0x0001fe00 -+#define TX_ID_USE2_I_MSK 0xfffe01ff -+#define TX_ID_USE2_SFT 9 -+#define TX_ID_USE2_HI 16 -+#define TX_ID_USE2_SZ 8 -+#define EDCA4_FFO_CNT_MSK 0x001e0000 -+#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff -+#define EDCA4_FFO_CNT_SFT 17 -+#define EDCA4_FFO_CNT_HI 20 -+#define EDCA4_FFO_CNT_SZ 4 -+#define TX_PAGE_USE3_MSK 0x000001ff -+#define TX_PAGE_USE3_I_MSK 0xfffffe00 -+#define TX_PAGE_USE3_SFT 0 -+#define TX_PAGE_USE3_HI 8 -+#define TX_PAGE_USE3_SZ 9 -+#define TX_ID_USE3_MSK 0x0001fe00 -+#define TX_ID_USE3_I_MSK 0xfffe01ff -+#define TX_ID_USE3_SFT 9 -+#define TX_ID_USE3_HI 16 -+#define TX_ID_USE3_SZ 8 -+#define EDCA1_FFO_CNT2_MSK 0x03e00000 -+#define EDCA1_FFO_CNT2_I_MSK 0xfc1fffff -+#define EDCA1_FFO_CNT2_SFT 21 -+#define EDCA1_FFO_CNT2_HI 25 -+#define EDCA1_FFO_CNT2_SZ 5 -+#define EDCA4_FFO_CNT2_MSK 0x3c000000 -+#define EDCA4_FFO_CNT2_I_MSK 0xc3ffffff -+#define EDCA4_FFO_CNT2_SFT 26 -+#define EDCA4_FFO_CNT2_HI 29 -+#define EDCA4_FFO_CNT2_SZ 4 -+#define TX_PAGE_USE4_MSK 0x000001ff -+#define TX_PAGE_USE4_I_MSK 0xfffffe00 -+#define TX_PAGE_USE4_SFT 0 -+#define TX_PAGE_USE4_HI 8 -+#define TX_PAGE_USE4_SZ 9 -+#define TX_ID_USE4_MSK 0x0001fe00 -+#define TX_ID_USE4_I_MSK 0xfffe01ff -+#define TX_ID_USE4_SFT 9 -+#define TX_ID_USE4_HI 16 -+#define TX_ID_USE4_SZ 8 -+#define EDCA2_FFO_CNT2_MSK 0x003e0000 -+#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff -+#define EDCA2_FFO_CNT2_SFT 17 -+#define EDCA2_FFO_CNT2_HI 21 -+#define EDCA2_FFO_CNT2_SZ 5 -+#define EDCA3_FFO_CNT2_MSK 0x07c00000 -+#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff -+#define EDCA3_FFO_CNT2_SFT 22 -+#define EDCA3_FFO_CNT2_HI 26 -+#define EDCA3_FFO_CNT2_SZ 5 -+#define TX_ID_IFO_LEN_MSK 0x000001ff -+#define TX_ID_IFO_LEN_I_MSK 0xfffffe00 -+#define TX_ID_IFO_LEN_SFT 0 -+#define TX_ID_IFO_LEN_HI 8 -+#define TX_ID_IFO_LEN_SZ 9 -+#define RX_ID_IFO_LEN_MSK 0x01ff0000 -+#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff -+#define RX_ID_IFO_LEN_SFT 16 -+#define RX_ID_IFO_LEN_HI 24 -+#define RX_ID_IFO_LEN_SZ 9 -+#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff -+#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00 -+#define MAX_ALL_ALC_ID_CNT_SFT 0 -+#define MAX_ALL_ALC_ID_CNT_HI 7 -+#define MAX_ALL_ALC_ID_CNT_SZ 8 -+#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00 -+#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff -+#define MAX_TX_ALC_ID_CNT_SFT 8 -+#define MAX_TX_ALC_ID_CNT_HI 15 -+#define MAX_TX_ALC_ID_CNT_SZ 8 -+#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000 -+#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff -+#define MAX_RX_ALC_ID_CNT_SFT 16 -+#define MAX_RX_ALC_ID_CNT_HI 23 -+#define MAX_RX_ALC_ID_CNT_SZ 8 -+#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff -+#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00 -+#define MAX_ALL_ID_ALC_LEN_SFT 0 -+#define MAX_ALL_ID_ALC_LEN_HI 8 -+#define MAX_ALL_ID_ALC_LEN_SZ 9 -+#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00 -+#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff -+#define MAX_TX_ID_ALC_LEN_SFT 9 -+#define MAX_TX_ID_ALC_LEN_HI 17 -+#define MAX_TX_ID_ALC_LEN_SZ 9 -+#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000 -+#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff -+#define MAX_RX_ID_ALC_LEN_SFT 18 -+#define MAX_RX_ID_ALC_LEN_HI 26 -+#define MAX_RX_ID_ALC_LEN_SZ 9 -+#define RG_PMDLBK_MSK 0x00000001 -+#define RG_PMDLBK_I_MSK 0xfffffffe -+#define RG_PMDLBK_SFT 0 -+#define RG_PMDLBK_HI 0 -+#define RG_PMDLBK_SZ 1 -+#define RG_RDYACK_SEL_MSK 0x00000006 -+#define RG_RDYACK_SEL_I_MSK 0xfffffff9 -+#define RG_RDYACK_SEL_SFT 1 -+#define RG_RDYACK_SEL_HI 2 -+#define RG_RDYACK_SEL_SZ 2 -+#define RG_ADEDGE_SEL_MSK 0x00000008 -+#define RG_ADEDGE_SEL_I_MSK 0xfffffff7 -+#define RG_ADEDGE_SEL_SFT 3 -+#define RG_ADEDGE_SEL_HI 3 -+#define RG_ADEDGE_SEL_SZ 1 -+#define RG_SIGN_SWAP_MSK 0x00000010 -+#define RG_SIGN_SWAP_I_MSK 0xffffffef -+#define RG_SIGN_SWAP_SFT 4 -+#define RG_SIGN_SWAP_HI 4 -+#define RG_SIGN_SWAP_SZ 1 -+#define RG_IQ_SWAP_MSK 0x00000020 -+#define RG_IQ_SWAP_I_MSK 0xffffffdf -+#define RG_IQ_SWAP_SFT 5 -+#define RG_IQ_SWAP_HI 5 -+#define RG_IQ_SWAP_SZ 1 -+#define RG_Q_INV_MSK 0x00000040 -+#define RG_Q_INV_I_MSK 0xffffffbf -+#define RG_Q_INV_SFT 6 -+#define RG_Q_INV_HI 6 -+#define RG_Q_INV_SZ 1 -+#define RG_I_INV_MSK 0x00000080 -+#define RG_I_INV_I_MSK 0xffffff7f -+#define RG_I_INV_SFT 7 -+#define RG_I_INV_HI 7 -+#define RG_I_INV_SZ 1 -+#define RG_BYPASS_ACI_MSK 0x00000100 -+#define RG_BYPASS_ACI_I_MSK 0xfffffeff -+#define RG_BYPASS_ACI_SFT 8 -+#define RG_BYPASS_ACI_HI 8 -+#define RG_BYPASS_ACI_SZ 1 -+#define RG_LBK_ANA_PATH_MSK 0x00000200 -+#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff -+#define RG_LBK_ANA_PATH_SFT 9 -+#define RG_LBK_ANA_PATH_HI 9 -+#define RG_LBK_ANA_PATH_SZ 1 -+#define RG_SPECTRUM_LEAKY_FACTOR_MSK 0x00000c00 -+#define RG_SPECTRUM_LEAKY_FACTOR_I_MSK 0xfffff3ff -+#define RG_SPECTRUM_LEAKY_FACTOR_SFT 10 -+#define RG_SPECTRUM_LEAKY_FACTOR_HI 11 -+#define RG_SPECTRUM_LEAKY_FACTOR_SZ 2 -+#define RG_SPECTRUM_BW_MSK 0x00003000 -+#define RG_SPECTRUM_BW_I_MSK 0xffffcfff -+#define RG_SPECTRUM_BW_SFT 12 -+#define RG_SPECTRUM_BW_HI 13 -+#define RG_SPECTRUM_BW_SZ 2 -+#define RG_SPECTRUM_FREQ_MANUAL_MSK 0x00004000 -+#define RG_SPECTRUM_FREQ_MANUAL_I_MSK 0xffffbfff -+#define RG_SPECTRUM_FREQ_MANUAL_SFT 14 -+#define RG_SPECTRUM_FREQ_MANUAL_HI 14 -+#define RG_SPECTRUM_FREQ_MANUAL_SZ 1 -+#define RG_SPECTRUM_EN_MSK 0x00008000 -+#define RG_SPECTRUM_EN_I_MSK 0xffff7fff -+#define RG_SPECTRUM_EN_SFT 15 -+#define RG_SPECTRUM_EN_HI 15 -+#define RG_SPECTRUM_EN_SZ 1 -+#define RG_TXPWRLVL_SET_MSK 0x00ff0000 -+#define RG_TXPWRLVL_SET_I_MSK 0xff00ffff -+#define RG_TXPWRLVL_SET_SFT 16 -+#define RG_TXPWRLVL_SET_HI 23 -+#define RG_TXPWRLVL_SET_SZ 8 -+#define RG_TXPWRLVL_SEL_MSK 0x01000000 -+#define RG_TXPWRLVL_SEL_I_MSK 0xfeffffff -+#define RG_TXPWRLVL_SEL_SFT 24 -+#define RG_TXPWRLVL_SEL_HI 24 -+#define RG_TXPWRLVL_SEL_SZ 1 -+#define RG_RF_BB_CLK_SEL_MSK 0x80000000 -+#define RG_RF_BB_CLK_SEL_I_MSK 0x7fffffff -+#define RG_RF_BB_CLK_SEL_SFT 31 -+#define RG_RF_BB_CLK_SEL_HI 31 -+#define RG_RF_BB_CLK_SEL_SZ 1 -+#define RG_PHY_MD_EN_MSK 0x00000001 -+#define RG_PHY_MD_EN_I_MSK 0xfffffffe -+#define RG_PHY_MD_EN_SFT 0 -+#define RG_PHY_MD_EN_HI 0 -+#define RG_PHY_MD_EN_SZ 1 -+#define RG_PHYRX_MD_EN_MSK 0x00000002 -+#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd -+#define RG_PHYRX_MD_EN_SFT 1 -+#define RG_PHYRX_MD_EN_HI 1 -+#define RG_PHYRX_MD_EN_SZ 1 -+#define RG_PHYTX_MD_EN_MSK 0x00000004 -+#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb -+#define RG_PHYTX_MD_EN_SFT 2 -+#define RG_PHYTX_MD_EN_HI 2 -+#define RG_PHYTX_MD_EN_SZ 1 -+#define RG_PHY11GN_MD_EN_MSK 0x00000008 -+#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7 -+#define RG_PHY11GN_MD_EN_SFT 3 -+#define RG_PHY11GN_MD_EN_HI 3 -+#define RG_PHY11GN_MD_EN_SZ 1 -+#define RG_PHY11B_MD_EN_MSK 0x00000010 -+#define RG_PHY11B_MD_EN_I_MSK 0xffffffef -+#define RG_PHY11B_MD_EN_SFT 4 -+#define RG_PHY11B_MD_EN_HI 4 -+#define RG_PHY11B_MD_EN_SZ 1 -+#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020 -+#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf -+#define RG_PHYRXFIFO_MD_EN_SFT 5 -+#define RG_PHYRXFIFO_MD_EN_HI 5 -+#define RG_PHYRXFIFO_MD_EN_SZ 1 -+#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040 -+#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf -+#define RG_PHYTXFIFO_MD_EN_SFT 6 -+#define RG_PHYTXFIFO_MD_EN_HI 6 -+#define RG_PHYTXFIFO_MD_EN_SZ 1 -+#define RG_PHY11BGN_MD_EN_MSK 0x00000100 -+#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff -+#define RG_PHY11BGN_MD_EN_SFT 8 -+#define RG_PHY11BGN_MD_EN_HI 8 -+#define RG_PHY11BGN_MD_EN_SZ 1 -+#define RG_FORCE_11GN_EN_MSK 0x00001000 -+#define RG_FORCE_11GN_EN_I_MSK 0xffffefff -+#define RG_FORCE_11GN_EN_SFT 12 -+#define RG_FORCE_11GN_EN_HI 12 -+#define RG_FORCE_11GN_EN_SZ 1 -+#define RG_FORCE_11B_EN_MSK 0x00002000 -+#define RG_FORCE_11B_EN_I_MSK 0xffffdfff -+#define RG_FORCE_11B_EN_SFT 13 -+#define RG_FORCE_11B_EN_HI 13 -+#define RG_FORCE_11B_EN_SZ 1 -+#define RG_FFT_MEM_CLK_EN_RX_MSK 0x00004000 -+#define RG_FFT_MEM_CLK_EN_RX_I_MSK 0xffffbfff -+#define RG_FFT_MEM_CLK_EN_RX_SFT 14 -+#define RG_FFT_MEM_CLK_EN_RX_HI 14 -+#define RG_FFT_MEM_CLK_EN_RX_SZ 1 -+#define RG_FFT_MEM_CLK_EN_TX_MSK 0x00008000 -+#define RG_FFT_MEM_CLK_EN_TX_I_MSK 0xffff7fff -+#define RG_FFT_MEM_CLK_EN_TX_SFT 15 -+#define RG_FFT_MEM_CLK_EN_TX_HI 15 -+#define RG_FFT_MEM_CLK_EN_TX_SZ 1 -+#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000 -+#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff -+#define RG_PHY_IQ_TRIG_SEL_SFT 16 -+#define RG_PHY_IQ_TRIG_SEL_HI 19 -+#define RG_PHY_IQ_TRIG_SEL_SZ 4 -+#define RG_SPECTRUM_FREQ_MSK 0x3ff00000 -+#define RG_SPECTRUM_FREQ_I_MSK 0xc00fffff -+#define RG_SPECTRUM_FREQ_SFT 20 -+#define RG_SPECTRUM_FREQ_HI 29 -+#define RG_SPECTRUM_FREQ_SZ 10 -+#define SVN_VERSION_MSK 0xffffffff -+#define SVN_VERSION_I_MSK 0x00000000 -+#define SVN_VERSION_SFT 0 -+#define SVN_VERSION_HI 31 -+#define SVN_VERSION_SZ 32 -+#define RG_LENGTH_MSK 0x0000ffff -+#define RG_LENGTH_I_MSK 0xffff0000 -+#define RG_LENGTH_SFT 0 -+#define RG_LENGTH_HI 15 -+#define RG_LENGTH_SZ 16 -+#define RG_PKT_MODE_MSK 0x00070000 -+#define RG_PKT_MODE_I_MSK 0xfff8ffff -+#define RG_PKT_MODE_SFT 16 -+#define RG_PKT_MODE_HI 18 -+#define RG_PKT_MODE_SZ 3 -+#define RG_CH_BW_MSK 0x00380000 -+#define RG_CH_BW_I_MSK 0xffc7ffff -+#define RG_CH_BW_SFT 19 -+#define RG_CH_BW_HI 21 -+#define RG_CH_BW_SZ 3 -+#define RG_PRM_MSK 0x00400000 -+#define RG_PRM_I_MSK 0xffbfffff -+#define RG_PRM_SFT 22 -+#define RG_PRM_HI 22 -+#define RG_PRM_SZ 1 -+#define RG_SHORTGI_MSK 0x00800000 -+#define RG_SHORTGI_I_MSK 0xff7fffff -+#define RG_SHORTGI_SFT 23 -+#define RG_SHORTGI_HI 23 -+#define RG_SHORTGI_SZ 1 -+#define RG_RATE_MSK 0x7f000000 -+#define RG_RATE_I_MSK 0x80ffffff -+#define RG_RATE_SFT 24 -+#define RG_RATE_HI 30 -+#define RG_RATE_SZ 7 -+#define RG_L_LENGTH_MSK 0x00000fff -+#define RG_L_LENGTH_I_MSK 0xfffff000 -+#define RG_L_LENGTH_SFT 0 -+#define RG_L_LENGTH_HI 11 -+#define RG_L_LENGTH_SZ 12 -+#define RG_L_RATE_MSK 0x00007000 -+#define RG_L_RATE_I_MSK 0xffff8fff -+#define RG_L_RATE_SFT 12 -+#define RG_L_RATE_HI 14 -+#define RG_L_RATE_SZ 3 -+#define RG_SERVICE_MSK 0xffff0000 -+#define RG_SERVICE_I_MSK 0x0000ffff -+#define RG_SERVICE_SFT 16 -+#define RG_SERVICE_HI 31 -+#define RG_SERVICE_SZ 16 -+#define RG_SMOOTHING_MSK 0x00000001 -+#define RG_SMOOTHING_I_MSK 0xfffffffe -+#define RG_SMOOTHING_SFT 0 -+#define RG_SMOOTHING_HI 0 -+#define RG_SMOOTHING_SZ 1 -+#define RG_NO_SOUND_MSK 0x00000002 -+#define RG_NO_SOUND_I_MSK 0xfffffffd -+#define RG_NO_SOUND_SFT 1 -+#define RG_NO_SOUND_HI 1 -+#define RG_NO_SOUND_SZ 1 -+#define RG_AGGREGATE_MSK 0x00000004 -+#define RG_AGGREGATE_I_MSK 0xfffffffb -+#define RG_AGGREGATE_SFT 2 -+#define RG_AGGREGATE_HI 2 -+#define RG_AGGREGATE_SZ 1 -+#define RG_STBC_MSK 0x00000018 -+#define RG_STBC_I_MSK 0xffffffe7 -+#define RG_STBC_SFT 3 -+#define RG_STBC_HI 4 -+#define RG_STBC_SZ 2 -+#define RG_FEC_MSK 0x00000020 -+#define RG_FEC_I_MSK 0xffffffdf -+#define RG_FEC_SFT 5 -+#define RG_FEC_HI 5 -+#define RG_FEC_SZ 1 -+#define RG_N_ESS_MSK 0x000000c0 -+#define RG_N_ESS_I_MSK 0xffffff3f -+#define RG_N_ESS_SFT 6 -+#define RG_N_ESS_HI 7 -+#define RG_N_ESS_SZ 2 -+#define RG_TXPWRLVL_MSK 0x0000ff00 -+#define RG_TXPWRLVL_I_MSK 0xffff00ff -+#define RG_TXPWRLVL_SFT 8 -+#define RG_TXPWRLVL_HI 15 -+#define RG_TXPWRLVL_SZ 8 -+#define RG_TX_START_MSK 0x00000001 -+#define RG_TX_START_I_MSK 0xfffffffe -+#define RG_TX_START_SFT 0 -+#define RG_TX_START_HI 0 -+#define RG_TX_START_SZ 1 -+#define RG_IFS_TIME_MSK 0x000000fc -+#define RG_IFS_TIME_I_MSK 0xffffff03 -+#define RG_IFS_TIME_SFT 2 -+#define RG_IFS_TIME_HI 7 -+#define RG_IFS_TIME_SZ 6 -+#define RG_CONTINUOUS_DATA_MSK 0x00000100 -+#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff -+#define RG_CONTINUOUS_DATA_SFT 8 -+#define RG_CONTINUOUS_DATA_HI 8 -+#define RG_CONTINUOUS_DATA_SZ 1 -+#define RG_DATA_SEL_MSK 0x00000600 -+#define RG_DATA_SEL_I_MSK 0xfffff9ff -+#define RG_DATA_SEL_SFT 9 -+#define RG_DATA_SEL_HI 10 -+#define RG_DATA_SEL_SZ 2 -+#define RG_TX_D_MSK 0x00ff0000 -+#define RG_TX_D_I_MSK 0xff00ffff -+#define RG_TX_D_SFT 16 -+#define RG_TX_D_HI 23 -+#define RG_TX_D_SZ 8 -+#define RG_TX_CNT_TARGET_MSK 0xffffffff -+#define RG_TX_CNT_TARGET_I_MSK 0x00000000 -+#define RG_TX_CNT_TARGET_SFT 0 -+#define RG_TX_CNT_TARGET_HI 31 -+#define RG_TX_CNT_TARGET_SZ 32 -+#define RG_FFT_IFFT_MODE_MSK 0x000000c0 -+#define RG_FFT_IFFT_MODE_I_MSK 0xffffff3f -+#define RG_FFT_IFFT_MODE_SFT 6 -+#define RG_FFT_IFFT_MODE_HI 7 -+#define RG_FFT_IFFT_MODE_SZ 2 -+#define RG_DAC_DBG_MODE_MSK 0x00000100 -+#define RG_DAC_DBG_MODE_I_MSK 0xfffffeff -+#define RG_DAC_DBG_MODE_SFT 8 -+#define RG_DAC_DBG_MODE_HI 8 -+#define RG_DAC_DBG_MODE_SZ 1 -+#define RG_DAC_SGN_SWAP_MSK 0x00000200 -+#define RG_DAC_SGN_SWAP_I_MSK 0xfffffdff -+#define RG_DAC_SGN_SWAP_SFT 9 -+#define RG_DAC_SGN_SWAP_HI 9 -+#define RG_DAC_SGN_SWAP_SZ 1 -+#define RG_TXD_SEL_MSK 0x00000c00 -+#define RG_TXD_SEL_I_MSK 0xfffff3ff -+#define RG_TXD_SEL_SFT 10 -+#define RG_TXD_SEL_HI 11 -+#define RG_TXD_SEL_SZ 2 -+#define RG_UP8X_MSK 0x00ff0000 -+#define RG_UP8X_I_MSK 0xff00ffff -+#define RG_UP8X_SFT 16 -+#define RG_UP8X_HI 23 -+#define RG_UP8X_SZ 8 -+#define RG_IQ_DC_BYP_MSK 0x01000000 -+#define RG_IQ_DC_BYP_I_MSK 0xfeffffff -+#define RG_IQ_DC_BYP_SFT 24 -+#define RG_IQ_DC_BYP_HI 24 -+#define RG_IQ_DC_BYP_SZ 1 -+#define RG_IQ_DC_LEAKY_FACTOR_MSK 0x30000000 -+#define RG_IQ_DC_LEAKY_FACTOR_I_MSK 0xcfffffff -+#define RG_IQ_DC_LEAKY_FACTOR_SFT 28 -+#define RG_IQ_DC_LEAKY_FACTOR_HI 29 -+#define RG_IQ_DC_LEAKY_FACTOR_SZ 2 -+#define RG_DAC_DCEN_MSK 0x00000001 -+#define RG_DAC_DCEN_I_MSK 0xfffffffe -+#define RG_DAC_DCEN_SFT 0 -+#define RG_DAC_DCEN_HI 0 -+#define RG_DAC_DCEN_SZ 1 -+#define RG_DAC_DCQ_MSK 0x00003ff0 -+#define RG_DAC_DCQ_I_MSK 0xffffc00f -+#define RG_DAC_DCQ_SFT 4 -+#define RG_DAC_DCQ_HI 13 -+#define RG_DAC_DCQ_SZ 10 -+#define RG_DAC_DCI_MSK 0x03ff0000 -+#define RG_DAC_DCI_I_MSK 0xfc00ffff -+#define RG_DAC_DCI_SFT 16 -+#define RG_DAC_DCI_HI 25 -+#define RG_DAC_DCI_SZ 10 -+#define RG_PGA_REFDB_SAT_MSK 0x0000007f -+#define RG_PGA_REFDB_SAT_I_MSK 0xffffff80 -+#define RG_PGA_REFDB_SAT_SFT 0 -+#define RG_PGA_REFDB_SAT_HI 6 -+#define RG_PGA_REFDB_SAT_SZ 7 -+#define RG_PGA_REFDB_TOP_MSK 0x00007f00 -+#define RG_PGA_REFDB_TOP_I_MSK 0xffff80ff -+#define RG_PGA_REFDB_TOP_SFT 8 -+#define RG_PGA_REFDB_TOP_HI 14 -+#define RG_PGA_REFDB_TOP_SZ 7 -+#define RG_PGA_REF_UND_MSK 0x03ff0000 -+#define RG_PGA_REF_UND_I_MSK 0xfc00ffff -+#define RG_PGA_REF_UND_SFT 16 -+#define RG_PGA_REF_UND_HI 25 -+#define RG_PGA_REF_UND_SZ 10 -+#define RG_RF_REF_SAT_MSK 0xf0000000 -+#define RG_RF_REF_SAT_I_MSK 0x0fffffff -+#define RG_RF_REF_SAT_SFT 28 -+#define RG_RF_REF_SAT_HI 31 -+#define RG_RF_REF_SAT_SZ 4 -+#define RG_PGAGC_SET_MSK 0x0000000f -+#define RG_PGAGC_SET_I_MSK 0xfffffff0 -+#define RG_PGAGC_SET_SFT 0 -+#define RG_PGAGC_SET_HI 3 -+#define RG_PGAGC_SET_SZ 4 -+#define RG_PGAGC_OW_MSK 0x00000010 -+#define RG_PGAGC_OW_I_MSK 0xffffffef -+#define RG_PGAGC_OW_SFT 4 -+#define RG_PGAGC_OW_HI 4 -+#define RG_PGAGC_OW_SZ 1 -+#define RG_RFGC_SET_MSK 0x00000060 -+#define RG_RFGC_SET_I_MSK 0xffffff9f -+#define RG_RFGC_SET_SFT 5 -+#define RG_RFGC_SET_HI 6 -+#define RG_RFGC_SET_SZ 2 -+#define RG_RFGC_OW_MSK 0x00000080 -+#define RG_RFGC_OW_I_MSK 0xffffff7f -+#define RG_RFGC_OW_SFT 7 -+#define RG_RFGC_OW_HI 7 -+#define RG_RFGC_OW_SZ 1 -+#define RG_WAIT_T_RXAGC_MSK 0x00003f00 -+#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff -+#define RG_WAIT_T_RXAGC_SFT 8 -+#define RG_WAIT_T_RXAGC_HI 13 -+#define RG_WAIT_T_RXAGC_SZ 6 -+#define RG_RXAGC_SET_MSK 0x00004000 -+#define RG_RXAGC_SET_I_MSK 0xffffbfff -+#define RG_RXAGC_SET_SFT 14 -+#define RG_RXAGC_SET_HI 14 -+#define RG_RXAGC_SET_SZ 1 -+#define RG_RXAGC_OW_MSK 0x00008000 -+#define RG_RXAGC_OW_I_MSK 0xffff7fff -+#define RG_RXAGC_OW_SFT 15 -+#define RG_RXAGC_OW_HI 15 -+#define RG_RXAGC_OW_SZ 1 -+#define RG_WAIT_T_FINAL_MSK 0x003f0000 -+#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff -+#define RG_WAIT_T_FINAL_SFT 16 -+#define RG_WAIT_T_FINAL_HI 21 -+#define RG_WAIT_T_FINAL_SZ 6 -+#define RG_WAIT_T_MSK 0x3f000000 -+#define RG_WAIT_T_I_MSK 0xc0ffffff -+#define RG_WAIT_T_SFT 24 -+#define RG_WAIT_T_HI 29 -+#define RG_WAIT_T_SZ 6 -+#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f -+#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0 -+#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0 -+#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3 -+#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4 -+#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0 -+#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f -+#define RG_LG_PGA_UND_PGA_GAIN_SFT 4 -+#define RG_LG_PGA_UND_PGA_GAIN_HI 7 -+#define RG_LG_PGA_UND_PGA_GAIN_SZ 4 -+#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00 -+#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff -+#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8 -+#define RG_LG_PGA_SAT_PGA_GAIN_HI 11 -+#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4 -+#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000 -+#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff -+#define RG_LG_RF_SAT_PGA_GAIN_SFT 12 -+#define RG_LG_RF_SAT_PGA_GAIN_HI 15 -+#define RG_LG_RF_SAT_PGA_GAIN_SZ 4 -+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000 -+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff -+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16 -+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19 -+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4 -+#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000 -+#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff -+#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20 -+#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23 -+#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4 -+#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000 -+#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff -+#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24 -+#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27 -+#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4 -+#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000 -+#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff -+#define RG_HG_RF_SAT_PGA_GAIN_SFT 28 -+#define RG_HG_RF_SAT_PGA_GAIN_HI 31 -+#define RG_HG_RF_SAT_PGA_GAIN_SZ 4 -+#define RG_MG_PGA_JB_TH_MSK 0x0000000f -+#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0 -+#define RG_MG_PGA_JB_TH_SFT 0 -+#define RG_MG_PGA_JB_TH_HI 3 -+#define RG_MG_PGA_JB_TH_SZ 4 -+#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000 -+#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff -+#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16 -+#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20 -+#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5 -+#define RG_WR_RFGC_INIT_SET_MSK 0x00600000 -+#define RG_WR_RFGC_INIT_SET_I_MSK 0xff9fffff -+#define RG_WR_RFGC_INIT_SET_SFT 21 -+#define RG_WR_RFGC_INIT_SET_HI 22 -+#define RG_WR_RFGC_INIT_SET_SZ 2 -+#define RG_WR_RFGC_INIT_EN_MSK 0x00800000 -+#define RG_WR_RFGC_INIT_EN_I_MSK 0xff7fffff -+#define RG_WR_RFGC_INIT_EN_SFT 23 -+#define RG_WR_RFGC_INIT_EN_HI 23 -+#define RG_WR_RFGC_INIT_EN_SZ 1 -+#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000 -+#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff -+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24 -+#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28 -+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5 -+#define RG_AGC_THRESHOLD_MSK 0x00003fff -+#define RG_AGC_THRESHOLD_I_MSK 0xffffc000 -+#define RG_AGC_THRESHOLD_SFT 0 -+#define RG_AGC_THRESHOLD_HI 13 -+#define RG_AGC_THRESHOLD_SZ 14 -+#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000 -+#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff -+#define RG_ACI_POINT_CNT_LMT_11B_SFT 16 -+#define RG_ACI_POINT_CNT_LMT_11B_HI 22 -+#define RG_ACI_POINT_CNT_LMT_11B_SZ 7 -+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000 -+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff -+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24 -+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25 -+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2 -+#define RG_WR_ACI_GAIN_INI_SEL_11B_MSK 0x000000ff -+#define RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK 0xffffff00 -+#define RG_WR_ACI_GAIN_INI_SEL_11B_SFT 0 -+#define RG_WR_ACI_GAIN_INI_SEL_11B_HI 7 -+#define RG_WR_ACI_GAIN_INI_SEL_11B_SZ 8 -+#define RG_WR_ACI_GAIN_SEL_11B_MSK 0x0000ff00 -+#define RG_WR_ACI_GAIN_SEL_11B_I_MSK 0xffff00ff -+#define RG_WR_ACI_GAIN_SEL_11B_SFT 8 -+#define RG_WR_ACI_GAIN_SEL_11B_HI 15 -+#define RG_WR_ACI_GAIN_SEL_11B_SZ 8 -+#define RG_ACI_DAGC_SET_VALUE_11B_MSK 0x007f0000 -+#define RG_ACI_DAGC_SET_VALUE_11B_I_MSK 0xff80ffff -+#define RG_ACI_DAGC_SET_VALUE_11B_SFT 16 -+#define RG_ACI_DAGC_SET_VALUE_11B_HI 22 -+#define RG_ACI_DAGC_SET_VALUE_11B_SZ 7 -+#define RG_WR_ACI_GAIN_OW_11B_MSK 0x80000000 -+#define RG_WR_ACI_GAIN_OW_11B_I_MSK 0x7fffffff -+#define RG_WR_ACI_GAIN_OW_11B_SFT 31 -+#define RG_WR_ACI_GAIN_OW_11B_HI 31 -+#define RG_WR_ACI_GAIN_OW_11B_SZ 1 -+#define RG_ACI_POINT_CNT_LMT_11GN_MSK 0x000000ff -+#define RG_ACI_POINT_CNT_LMT_11GN_I_MSK 0xffffff00 -+#define RG_ACI_POINT_CNT_LMT_11GN_SFT 0 -+#define RG_ACI_POINT_CNT_LMT_11GN_HI 7 -+#define RG_ACI_POINT_CNT_LMT_11GN_SZ 8 -+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK 0x00000300 -+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK 0xfffffcff -+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT 8 -+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI 9 -+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ 2 -+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000 -+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff -+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24 -+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31 -+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8 -+#define RG_ACI_DAGC_SET_VALUE_11GN_MSK 0x0000007f -+#define RG_ACI_DAGC_SET_VALUE_11GN_I_MSK 0xffffff80 -+#define RG_ACI_DAGC_SET_VALUE_11GN_SFT 0 -+#define RG_ACI_DAGC_SET_VALUE_11GN_HI 6 -+#define RG_ACI_DAGC_SET_VALUE_11GN_SZ 7 -+#define RG_ACI_GAIN_INI_VAL_11GN_MSK 0x0000ff00 -+#define RG_ACI_GAIN_INI_VAL_11GN_I_MSK 0xffff00ff -+#define RG_ACI_GAIN_INI_VAL_11GN_SFT 8 -+#define RG_ACI_GAIN_INI_VAL_11GN_HI 15 -+#define RG_ACI_GAIN_INI_VAL_11GN_SZ 8 -+#define RG_ACI_GAIN_OW_VAL_11GN_MSK 0x00ff0000 -+#define RG_ACI_GAIN_OW_VAL_11GN_I_MSK 0xff00ffff -+#define RG_ACI_GAIN_OW_VAL_11GN_SFT 16 -+#define RG_ACI_GAIN_OW_VAL_11GN_HI 23 -+#define RG_ACI_GAIN_OW_VAL_11GN_SZ 8 -+#define RG_ACI_GAIN_OW_11GN_MSK 0x80000000 -+#define RG_ACI_GAIN_OW_11GN_I_MSK 0x7fffffff -+#define RG_ACI_GAIN_OW_11GN_SFT 31 -+#define RG_ACI_GAIN_OW_11GN_HI 31 -+#define RG_ACI_GAIN_OW_11GN_SZ 1 -+#define RO_CCA_PWR_MA_11GN_MSK 0x0000007f -+#define RO_CCA_PWR_MA_11GN_I_MSK 0xffffff80 -+#define RO_CCA_PWR_MA_11GN_SFT 0 -+#define RO_CCA_PWR_MA_11GN_HI 6 -+#define RO_CCA_PWR_MA_11GN_SZ 7 -+#define RO_ED_STATE_MSK 0x00008000 -+#define RO_ED_STATE_I_MSK 0xffff7fff -+#define RO_ED_STATE_SFT 15 -+#define RO_ED_STATE_HI 15 -+#define RO_ED_STATE_SZ 1 -+#define RO_CCA_PWR_MA_11B_MSK 0x007f0000 -+#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff -+#define RO_CCA_PWR_MA_11B_SFT 16 -+#define RO_CCA_PWR_MA_11B_HI 22 -+#define RO_CCA_PWR_MA_11B_SZ 7 -+#define RO_PGA_PWR_FF1_MSK 0x00003fff -+#define RO_PGA_PWR_FF1_I_MSK 0xffffc000 -+#define RO_PGA_PWR_FF1_SFT 0 -+#define RO_PGA_PWR_FF1_HI 13 -+#define RO_PGA_PWR_FF1_SZ 14 -+#define RO_RF_PWR_FF1_MSK 0x000f0000 -+#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff -+#define RO_RF_PWR_FF1_SFT 16 -+#define RO_RF_PWR_FF1_HI 19 -+#define RO_RF_PWR_FF1_SZ 4 -+#define RO_PGAGC_FF1_MSK 0x0f000000 -+#define RO_PGAGC_FF1_I_MSK 0xf0ffffff -+#define RO_PGAGC_FF1_SFT 24 -+#define RO_PGAGC_FF1_HI 27 -+#define RO_PGAGC_FF1_SZ 4 -+#define RO_RFGC_FF1_MSK 0x30000000 -+#define RO_RFGC_FF1_I_MSK 0xcfffffff -+#define RO_RFGC_FF1_SFT 28 -+#define RO_RFGC_FF1_HI 29 -+#define RO_RFGC_FF1_SZ 2 -+#define RO_PGA_PWR_FF2_MSK 0x00003fff -+#define RO_PGA_PWR_FF2_I_MSK 0xffffc000 -+#define RO_PGA_PWR_FF2_SFT 0 -+#define RO_PGA_PWR_FF2_HI 13 -+#define RO_PGA_PWR_FF2_SZ 14 -+#define RO_RF_PWR_FF2_MSK 0x000f0000 -+#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff -+#define RO_RF_PWR_FF2_SFT 16 -+#define RO_RF_PWR_FF2_HI 19 -+#define RO_RF_PWR_FF2_SZ 4 -+#define RO_PGAGC_FF2_MSK 0x0f000000 -+#define RO_PGAGC_FF2_I_MSK 0xf0ffffff -+#define RO_PGAGC_FF2_SFT 24 -+#define RO_PGAGC_FF2_HI 27 -+#define RO_PGAGC_FF2_SZ 4 -+#define RO_RFGC_FF2_MSK 0x30000000 -+#define RO_RFGC_FF2_I_MSK 0xcfffffff -+#define RO_RFGC_FF2_SFT 28 -+#define RO_RFGC_FF2_HI 29 -+#define RO_RFGC_FF2_SZ 2 -+#define RO_PGA_PWR_FF3_MSK 0x00003fff -+#define RO_PGA_PWR_FF3_I_MSK 0xffffc000 -+#define RO_PGA_PWR_FF3_SFT 0 -+#define RO_PGA_PWR_FF3_HI 13 -+#define RO_PGA_PWR_FF3_SZ 14 -+#define RO_RF_PWR_FF3_MSK 0x000f0000 -+#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff -+#define RO_RF_PWR_FF3_SFT 16 -+#define RO_RF_PWR_FF3_HI 19 -+#define RO_RF_PWR_FF3_SZ 4 -+#define RO_PGAGC_FF3_MSK 0x0f000000 -+#define RO_PGAGC_FF3_I_MSK 0xf0ffffff -+#define RO_PGAGC_FF3_SFT 24 -+#define RO_PGAGC_FF3_HI 27 -+#define RO_PGAGC_FF3_SZ 4 -+#define RO_RFGC_FF3_MSK 0x30000000 -+#define RO_RFGC_FF3_I_MSK 0xcfffffff -+#define RO_RFGC_FF3_SFT 28 -+#define RO_RFGC_FF3_HI 29 -+#define RO_RFGC_FF3_SZ 2 -+#define RG_TX_DES_RATE_MSK 0x0000001f -+#define RG_TX_DES_RATE_I_MSK 0xffffffe0 -+#define RG_TX_DES_RATE_SFT 0 -+#define RG_TX_DES_RATE_HI 4 -+#define RG_TX_DES_RATE_SZ 5 -+#define RG_TX_DES_MODE_MSK 0x00001f00 -+#define RG_TX_DES_MODE_I_MSK 0xffffe0ff -+#define RG_TX_DES_MODE_SFT 8 -+#define RG_TX_DES_MODE_HI 12 -+#define RG_TX_DES_MODE_SZ 5 -+#define RG_TX_DES_LEN_LO_MSK 0x001f0000 -+#define RG_TX_DES_LEN_LO_I_MSK 0xffe0ffff -+#define RG_TX_DES_LEN_LO_SFT 16 -+#define RG_TX_DES_LEN_LO_HI 20 -+#define RG_TX_DES_LEN_LO_SZ 5 -+#define RG_TX_DES_LEN_UP_MSK 0x1f000000 -+#define RG_TX_DES_LEN_UP_I_MSK 0xe0ffffff -+#define RG_TX_DES_LEN_UP_SFT 24 -+#define RG_TX_DES_LEN_UP_HI 28 -+#define RG_TX_DES_LEN_UP_SZ 5 -+#define RG_TX_DES_SRVC_UP_MSK 0x0000001f -+#define RG_TX_DES_SRVC_UP_I_MSK 0xffffffe0 -+#define RG_TX_DES_SRVC_UP_SFT 0 -+#define RG_TX_DES_SRVC_UP_HI 4 -+#define RG_TX_DES_SRVC_UP_SZ 5 -+#define RG_TX_DES_L_LEN_LO_MSK 0x00001f00 -+#define RG_TX_DES_L_LEN_LO_I_MSK 0xffffe0ff -+#define RG_TX_DES_L_LEN_LO_SFT 8 -+#define RG_TX_DES_L_LEN_LO_HI 12 -+#define RG_TX_DES_L_LEN_LO_SZ 5 -+#define RG_TX_DES_L_LEN_UP_MSK 0x001f0000 -+#define RG_TX_DES_L_LEN_UP_I_MSK 0xffe0ffff -+#define RG_TX_DES_L_LEN_UP_SFT 16 -+#define RG_TX_DES_L_LEN_UP_HI 20 -+#define RG_TX_DES_L_LEN_UP_SZ 5 -+#define RG_TX_DES_TYPE_MSK 0x1f000000 -+#define RG_TX_DES_TYPE_I_MSK 0xe0ffffff -+#define RG_TX_DES_TYPE_SFT 24 -+#define RG_TX_DES_TYPE_HI 28 -+#define RG_TX_DES_TYPE_SZ 5 -+#define RG_TX_DES_L_LEN_UP_COMB_MSK 0x00000001 -+#define RG_TX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe -+#define RG_TX_DES_L_LEN_UP_COMB_SFT 0 -+#define RG_TX_DES_L_LEN_UP_COMB_HI 0 -+#define RG_TX_DES_L_LEN_UP_COMB_SZ 1 -+#define RG_TX_DES_TYPE_COMB_MSK 0x00000010 -+#define RG_TX_DES_TYPE_COMB_I_MSK 0xffffffef -+#define RG_TX_DES_TYPE_COMB_SFT 4 -+#define RG_TX_DES_TYPE_COMB_HI 4 -+#define RG_TX_DES_TYPE_COMB_SZ 1 -+#define RG_TX_DES_RATE_COMB_MSK 0x00000100 -+#define RG_TX_DES_RATE_COMB_I_MSK 0xfffffeff -+#define RG_TX_DES_RATE_COMB_SFT 8 -+#define RG_TX_DES_RATE_COMB_HI 8 -+#define RG_TX_DES_RATE_COMB_SZ 1 -+#define RG_TX_DES_MODE_COMB_MSK 0x00001000 -+#define RG_TX_DES_MODE_COMB_I_MSK 0xffffefff -+#define RG_TX_DES_MODE_COMB_SFT 12 -+#define RG_TX_DES_MODE_COMB_HI 12 -+#define RG_TX_DES_MODE_COMB_SZ 1 -+#define RG_TX_DES_PWRLVL_MSK 0x001f0000 -+#define RG_TX_DES_PWRLVL_I_MSK 0xffe0ffff -+#define RG_TX_DES_PWRLVL_SFT 16 -+#define RG_TX_DES_PWRLVL_HI 20 -+#define RG_TX_DES_PWRLVL_SZ 5 -+#define RG_TX_DES_SRVC_LO_MSK 0x1f000000 -+#define RG_TX_DES_SRVC_LO_I_MSK 0xe0ffffff -+#define RG_TX_DES_SRVC_LO_SFT 24 -+#define RG_TX_DES_SRVC_LO_HI 28 -+#define RG_TX_DES_SRVC_LO_SZ 5 -+#define RG_RX_DES_RATE_MSK 0x0000003f -+#define RG_RX_DES_RATE_I_MSK 0xffffffc0 -+#define RG_RX_DES_RATE_SFT 0 -+#define RG_RX_DES_RATE_HI 5 -+#define RG_RX_DES_RATE_SZ 6 -+#define RG_RX_DES_MODE_MSK 0x00003f00 -+#define RG_RX_DES_MODE_I_MSK 0xffffc0ff -+#define RG_RX_DES_MODE_SFT 8 -+#define RG_RX_DES_MODE_HI 13 -+#define RG_RX_DES_MODE_SZ 6 -+#define RG_RX_DES_LEN_LO_MSK 0x003f0000 -+#define RG_RX_DES_LEN_LO_I_MSK 0xffc0ffff -+#define RG_RX_DES_LEN_LO_SFT 16 -+#define RG_RX_DES_LEN_LO_HI 21 -+#define RG_RX_DES_LEN_LO_SZ 6 -+#define RG_RX_DES_LEN_UP_MSK 0x3f000000 -+#define RG_RX_DES_LEN_UP_I_MSK 0xc0ffffff -+#define RG_RX_DES_LEN_UP_SFT 24 -+#define RG_RX_DES_LEN_UP_HI 29 -+#define RG_RX_DES_LEN_UP_SZ 6 -+#define RG_RX_DES_SRVC_UP_MSK 0x0000003f -+#define RG_RX_DES_SRVC_UP_I_MSK 0xffffffc0 -+#define RG_RX_DES_SRVC_UP_SFT 0 -+#define RG_RX_DES_SRVC_UP_HI 5 -+#define RG_RX_DES_SRVC_UP_SZ 6 -+#define RG_RX_DES_L_LEN_LO_MSK 0x00003f00 -+#define RG_RX_DES_L_LEN_LO_I_MSK 0xffffc0ff -+#define RG_RX_DES_L_LEN_LO_SFT 8 -+#define RG_RX_DES_L_LEN_LO_HI 13 -+#define RG_RX_DES_L_LEN_LO_SZ 6 -+#define RG_RX_DES_L_LEN_UP_MSK 0x003f0000 -+#define RG_RX_DES_L_LEN_UP_I_MSK 0xffc0ffff -+#define RG_RX_DES_L_LEN_UP_SFT 16 -+#define RG_RX_DES_L_LEN_UP_HI 21 -+#define RG_RX_DES_L_LEN_UP_SZ 6 -+#define RG_RX_DES_TYPE_MSK 0x3f000000 -+#define RG_RX_DES_TYPE_I_MSK 0xc0ffffff -+#define RG_RX_DES_TYPE_SFT 24 -+#define RG_RX_DES_TYPE_HI 29 -+#define RG_RX_DES_TYPE_SZ 6 -+#define RG_RX_DES_L_LEN_UP_COMB_MSK 0x00000001 -+#define RG_RX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe -+#define RG_RX_DES_L_LEN_UP_COMB_SFT 0 -+#define RG_RX_DES_L_LEN_UP_COMB_HI 0 -+#define RG_RX_DES_L_LEN_UP_COMB_SZ 1 -+#define RG_RX_DES_TYPE_COMB_MSK 0x00000010 -+#define RG_RX_DES_TYPE_COMB_I_MSK 0xffffffef -+#define RG_RX_DES_TYPE_COMB_SFT 4 -+#define RG_RX_DES_TYPE_COMB_HI 4 -+#define RG_RX_DES_TYPE_COMB_SZ 1 -+#define RG_RX_DES_RATE_COMB_MSK 0x00000100 -+#define RG_RX_DES_RATE_COMB_I_MSK 0xfffffeff -+#define RG_RX_DES_RATE_COMB_SFT 8 -+#define RG_RX_DES_RATE_COMB_HI 8 -+#define RG_RX_DES_RATE_COMB_SZ 1 -+#define RG_RX_DES_MODE_COMB_MSK 0x00001000 -+#define RG_RX_DES_MODE_COMB_I_MSK 0xffffefff -+#define RG_RX_DES_MODE_COMB_SFT 12 -+#define RG_RX_DES_MODE_COMB_HI 12 -+#define RG_RX_DES_MODE_COMB_SZ 1 -+#define RG_RX_DES_SNR_MSK 0x000f0000 -+#define RG_RX_DES_SNR_I_MSK 0xfff0ffff -+#define RG_RX_DES_SNR_SFT 16 -+#define RG_RX_DES_SNR_HI 19 -+#define RG_RX_DES_SNR_SZ 4 -+#define RG_RX_DES_RCPI_MSK 0x00f00000 -+#define RG_RX_DES_RCPI_I_MSK 0xff0fffff -+#define RG_RX_DES_RCPI_SFT 20 -+#define RG_RX_DES_RCPI_HI 23 -+#define RG_RX_DES_RCPI_SZ 4 -+#define RG_RX_DES_SRVC_LO_MSK 0x3f000000 -+#define RG_RX_DES_SRVC_LO_I_MSK 0xc0ffffff -+#define RG_RX_DES_SRVC_LO_SFT 24 -+#define RG_RX_DES_SRVC_LO_HI 29 -+#define RG_RX_DES_SRVC_LO_SZ 6 -+#define RO_TX_DES_EXCP_RATE_CNT_MSK 0x000000ff -+#define RO_TX_DES_EXCP_RATE_CNT_I_MSK 0xffffff00 -+#define RO_TX_DES_EXCP_RATE_CNT_SFT 0 -+#define RO_TX_DES_EXCP_RATE_CNT_HI 7 -+#define RO_TX_DES_EXCP_RATE_CNT_SZ 8 -+#define RO_TX_DES_EXCP_CH_BW_CNT_MSK 0x0000ff00 -+#define RO_TX_DES_EXCP_CH_BW_CNT_I_MSK 0xffff00ff -+#define RO_TX_DES_EXCP_CH_BW_CNT_SFT 8 -+#define RO_TX_DES_EXCP_CH_BW_CNT_HI 15 -+#define RO_TX_DES_EXCP_CH_BW_CNT_SZ 8 -+#define RO_TX_DES_EXCP_MODE_CNT_MSK 0x00ff0000 -+#define RO_TX_DES_EXCP_MODE_CNT_I_MSK 0xff00ffff -+#define RO_TX_DES_EXCP_MODE_CNT_SFT 16 -+#define RO_TX_DES_EXCP_MODE_CNT_HI 23 -+#define RO_TX_DES_EXCP_MODE_CNT_SZ 8 -+#define RG_TX_DES_EXCP_RATE_DEFAULT_MSK 0x07000000 -+#define RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK 0xf8ffffff -+#define RG_TX_DES_EXCP_RATE_DEFAULT_SFT 24 -+#define RG_TX_DES_EXCP_RATE_DEFAULT_HI 26 -+#define RG_TX_DES_EXCP_RATE_DEFAULT_SZ 3 -+#define RG_TX_DES_EXCP_MODE_DEFAULT_MSK 0x70000000 -+#define RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK 0x8fffffff -+#define RG_TX_DES_EXCP_MODE_DEFAULT_SFT 28 -+#define RG_TX_DES_EXCP_MODE_DEFAULT_HI 30 -+#define RG_TX_DES_EXCP_MODE_DEFAULT_SZ 3 -+#define RG_TX_DES_EXCP_CLR_MSK 0x80000000 -+#define RG_TX_DES_EXCP_CLR_I_MSK 0x7fffffff -+#define RG_TX_DES_EXCP_CLR_SFT 31 -+#define RG_TX_DES_EXCP_CLR_HI 31 -+#define RG_TX_DES_EXCP_CLR_SZ 1 -+#define RG_TX_DES_ACK_WIDTH_MSK 0x00000001 -+#define RG_TX_DES_ACK_WIDTH_I_MSK 0xfffffffe -+#define RG_TX_DES_ACK_WIDTH_SFT 0 -+#define RG_TX_DES_ACK_WIDTH_HI 0 -+#define RG_TX_DES_ACK_WIDTH_SZ 1 -+#define RG_TX_DES_ACK_PRD_MSK 0x0000000e -+#define RG_TX_DES_ACK_PRD_I_MSK 0xfffffff1 -+#define RG_TX_DES_ACK_PRD_SFT 1 -+#define RG_TX_DES_ACK_PRD_HI 3 -+#define RG_TX_DES_ACK_PRD_SZ 3 -+#define RG_RX_DES_SNR_GN_MSK 0x003f0000 -+#define RG_RX_DES_SNR_GN_I_MSK 0xffc0ffff -+#define RG_RX_DES_SNR_GN_SFT 16 -+#define RG_RX_DES_SNR_GN_HI 21 -+#define RG_RX_DES_SNR_GN_SZ 6 -+#define RG_RX_DES_RCPI_GN_MSK 0x3f000000 -+#define RG_RX_DES_RCPI_GN_I_MSK 0xc0ffffff -+#define RG_RX_DES_RCPI_GN_SFT 24 -+#define RG_RX_DES_RCPI_GN_HI 29 -+#define RG_RX_DES_RCPI_GN_SZ 6 -+#define RG_TST_TBUS_SEL_MSK 0x0000000f -+#define RG_TST_TBUS_SEL_I_MSK 0xfffffff0 -+#define RG_TST_TBUS_SEL_SFT 0 -+#define RG_TST_TBUS_SEL_HI 3 -+#define RG_TST_TBUS_SEL_SZ 4 -+#define RG_RSSI_OFFSET_MSK 0x00ff0000 -+#define RG_RSSI_OFFSET_I_MSK 0xff00ffff -+#define RG_RSSI_OFFSET_SFT 16 -+#define RG_RSSI_OFFSET_HI 23 -+#define RG_RSSI_OFFSET_SZ 8 -+#define RG_RSSI_INV_MSK 0x01000000 -+#define RG_RSSI_INV_I_MSK 0xfeffffff -+#define RG_RSSI_INV_SFT 24 -+#define RG_RSSI_INV_HI 24 -+#define RG_RSSI_INV_SZ 1 -+#define RG_TST_ADC_ON_MSK 0x40000000 -+#define RG_TST_ADC_ON_I_MSK 0xbfffffff -+#define RG_TST_ADC_ON_SFT 30 -+#define RG_TST_ADC_ON_HI 30 -+#define RG_TST_ADC_ON_SZ 1 -+#define RG_TST_EXT_GAIN_MSK 0x80000000 -+#define RG_TST_EXT_GAIN_I_MSK 0x7fffffff -+#define RG_TST_EXT_GAIN_SFT 31 -+#define RG_TST_EXT_GAIN_HI 31 -+#define RG_TST_EXT_GAIN_SZ 1 -+#define RG_DAC_Q_SET_MSK 0x000003ff -+#define RG_DAC_Q_SET_I_MSK 0xfffffc00 -+#define RG_DAC_Q_SET_SFT 0 -+#define RG_DAC_Q_SET_HI 9 -+#define RG_DAC_Q_SET_SZ 10 -+#define RG_DAC_I_SET_MSK 0x003ff000 -+#define RG_DAC_I_SET_I_MSK 0xffc00fff -+#define RG_DAC_I_SET_SFT 12 -+#define RG_DAC_I_SET_HI 21 -+#define RG_DAC_I_SET_SZ 10 -+#define RG_DAC_EN_MAN_MSK 0x10000000 -+#define RG_DAC_EN_MAN_I_MSK 0xefffffff -+#define RG_DAC_EN_MAN_SFT 28 -+#define RG_DAC_EN_MAN_HI 28 -+#define RG_DAC_EN_MAN_SZ 1 -+#define RG_IQC_FFT_EN_MSK 0x20000000 -+#define RG_IQC_FFT_EN_I_MSK 0xdfffffff -+#define RG_IQC_FFT_EN_SFT 29 -+#define RG_IQC_FFT_EN_HI 29 -+#define RG_IQC_FFT_EN_SZ 1 -+#define RG_DAC_MAN_Q_EN_MSK 0x40000000 -+#define RG_DAC_MAN_Q_EN_I_MSK 0xbfffffff -+#define RG_DAC_MAN_Q_EN_SFT 30 -+#define RG_DAC_MAN_Q_EN_HI 30 -+#define RG_DAC_MAN_Q_EN_SZ 1 -+#define RG_DAC_MAN_I_EN_MSK 0x80000000 -+#define RG_DAC_MAN_I_EN_I_MSK 0x7fffffff -+#define RG_DAC_MAN_I_EN_SFT 31 -+#define RG_DAC_MAN_I_EN_HI 31 -+#define RG_DAC_MAN_I_EN_SZ 1 -+#define RO_MRX_EN_CNT_MSK 0x0000ffff -+#define RO_MRX_EN_CNT_I_MSK 0xffff0000 -+#define RO_MRX_EN_CNT_SFT 0 -+#define RO_MRX_EN_CNT_HI 15 -+#define RO_MRX_EN_CNT_SZ 16 -+#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000 -+#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff -+#define RG_MRX_EN_CNT_RST_N_SFT 31 -+#define RG_MRX_EN_CNT_RST_N_HI 31 -+#define RG_MRX_EN_CNT_RST_N_SZ 1 -+#define RG_PA_RISE_TIME_MSK 0x000000ff -+#define RG_PA_RISE_TIME_I_MSK 0xffffff00 -+#define RG_PA_RISE_TIME_SFT 0 -+#define RG_PA_RISE_TIME_HI 7 -+#define RG_PA_RISE_TIME_SZ 8 -+#define RG_RFTX_RISE_TIME_MSK 0x0000ff00 -+#define RG_RFTX_RISE_TIME_I_MSK 0xffff00ff -+#define RG_RFTX_RISE_TIME_SFT 8 -+#define RG_RFTX_RISE_TIME_HI 15 -+#define RG_RFTX_RISE_TIME_SZ 8 -+#define RG_DAC_RISE_TIME_MSK 0x00ff0000 -+#define RG_DAC_RISE_TIME_I_MSK 0xff00ffff -+#define RG_DAC_RISE_TIME_SFT 16 -+#define RG_DAC_RISE_TIME_HI 23 -+#define RG_DAC_RISE_TIME_SZ 8 -+#define RG_SW_RISE_TIME_MSK 0xff000000 -+#define RG_SW_RISE_TIME_I_MSK 0x00ffffff -+#define RG_SW_RISE_TIME_SFT 24 -+#define RG_SW_RISE_TIME_HI 31 -+#define RG_SW_RISE_TIME_SZ 8 -+#define RG_PA_FALL_TIME_MSK 0x000000ff -+#define RG_PA_FALL_TIME_I_MSK 0xffffff00 -+#define RG_PA_FALL_TIME_SFT 0 -+#define RG_PA_FALL_TIME_HI 7 -+#define RG_PA_FALL_TIME_SZ 8 -+#define RG_RFTX_FALL_TIME_MSK 0x0000ff00 -+#define RG_RFTX_FALL_TIME_I_MSK 0xffff00ff -+#define RG_RFTX_FALL_TIME_SFT 8 -+#define RG_RFTX_FALL_TIME_HI 15 -+#define RG_RFTX_FALL_TIME_SZ 8 -+#define RG_DAC_FALL_TIME_MSK 0x00ff0000 -+#define RG_DAC_FALL_TIME_I_MSK 0xff00ffff -+#define RG_DAC_FALL_TIME_SFT 16 -+#define RG_DAC_FALL_TIME_HI 23 -+#define RG_DAC_FALL_TIME_SZ 8 -+#define RG_SW_FALL_TIME_MSK 0xff000000 -+#define RG_SW_FALL_TIME_I_MSK 0x00ffffff -+#define RG_SW_FALL_TIME_SFT 24 -+#define RG_SW_FALL_TIME_HI 31 -+#define RG_SW_FALL_TIME_SZ 8 -+#define RG_ANT_SW_0_MSK 0x00000007 -+#define RG_ANT_SW_0_I_MSK 0xfffffff8 -+#define RG_ANT_SW_0_SFT 0 -+#define RG_ANT_SW_0_HI 2 -+#define RG_ANT_SW_0_SZ 3 -+#define RG_ANT_SW_1_MSK 0x00000038 -+#define RG_ANT_SW_1_I_MSK 0xffffffc7 -+#define RG_ANT_SW_1_SFT 3 -+#define RG_ANT_SW_1_HI 5 -+#define RG_ANT_SW_1_SZ 3 -+#define RG_MTX_LEN_LOWER_TH_0_MSK 0x00001fff -+#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffffe000 -+#define RG_MTX_LEN_LOWER_TH_0_SFT 0 -+#define RG_MTX_LEN_LOWER_TH_0_HI 12 -+#define RG_MTX_LEN_LOWER_TH_0_SZ 13 -+#define RG_MTX_LEN_UPPER_TH_0_MSK 0x1fff0000 -+#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0xe000ffff -+#define RG_MTX_LEN_UPPER_TH_0_SFT 16 -+#define RG_MTX_LEN_UPPER_TH_0_HI 28 -+#define RG_MTX_LEN_UPPER_TH_0_SZ 13 -+#define RG_MTX_LEN_CNT_EN_0_MSK 0x80000000 -+#define RG_MTX_LEN_CNT_EN_0_I_MSK 0x7fffffff -+#define RG_MTX_LEN_CNT_EN_0_SFT 31 -+#define RG_MTX_LEN_CNT_EN_0_HI 31 -+#define RG_MTX_LEN_CNT_EN_0_SZ 1 -+#define RG_MTX_LEN_LOWER_TH_1_MSK 0x00001fff -+#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffffe000 -+#define RG_MTX_LEN_LOWER_TH_1_SFT 0 -+#define RG_MTX_LEN_LOWER_TH_1_HI 12 -+#define RG_MTX_LEN_LOWER_TH_1_SZ 13 -+#define RG_MTX_LEN_UPPER_TH_1_MSK 0x1fff0000 -+#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0xe000ffff -+#define RG_MTX_LEN_UPPER_TH_1_SFT 16 -+#define RG_MTX_LEN_UPPER_TH_1_HI 28 -+#define RG_MTX_LEN_UPPER_TH_1_SZ 13 -+#define RG_MTX_LEN_CNT_EN_1_MSK 0x80000000 -+#define RG_MTX_LEN_CNT_EN_1_I_MSK 0x7fffffff -+#define RG_MTX_LEN_CNT_EN_1_SFT 31 -+#define RG_MTX_LEN_CNT_EN_1_HI 31 -+#define RG_MTX_LEN_CNT_EN_1_SZ 1 -+#define RG_MRX_LEN_LOWER_TH_0_MSK 0x00001fff -+#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffffe000 -+#define RG_MRX_LEN_LOWER_TH_0_SFT 0 -+#define RG_MRX_LEN_LOWER_TH_0_HI 12 -+#define RG_MRX_LEN_LOWER_TH_0_SZ 13 -+#define RG_MRX_LEN_UPPER_TH_0_MSK 0x1fff0000 -+#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0xe000ffff -+#define RG_MRX_LEN_UPPER_TH_0_SFT 16 -+#define RG_MRX_LEN_UPPER_TH_0_HI 28 -+#define RG_MRX_LEN_UPPER_TH_0_SZ 13 -+#define RG_MRX_LEN_CNT_EN_0_MSK 0x80000000 -+#define RG_MRX_LEN_CNT_EN_0_I_MSK 0x7fffffff -+#define RG_MRX_LEN_CNT_EN_0_SFT 31 -+#define RG_MRX_LEN_CNT_EN_0_HI 31 -+#define RG_MRX_LEN_CNT_EN_0_SZ 1 -+#define RG_MRX_LEN_LOWER_TH_1_MSK 0x00001fff -+#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffffe000 -+#define RG_MRX_LEN_LOWER_TH_1_SFT 0 -+#define RG_MRX_LEN_LOWER_TH_1_HI 12 -+#define RG_MRX_LEN_LOWER_TH_1_SZ 13 -+#define RG_MRX_LEN_UPPER_TH_1_MSK 0x1fff0000 -+#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0xe000ffff -+#define RG_MRX_LEN_UPPER_TH_1_SFT 16 -+#define RG_MRX_LEN_UPPER_TH_1_HI 28 -+#define RG_MRX_LEN_UPPER_TH_1_SZ 13 -+#define RG_MRX_LEN_CNT_EN_1_MSK 0x80000000 -+#define RG_MRX_LEN_CNT_EN_1_I_MSK 0x7fffffff -+#define RG_MRX_LEN_CNT_EN_1_SFT 31 -+#define RG_MRX_LEN_CNT_EN_1_HI 31 -+#define RG_MRX_LEN_CNT_EN_1_SZ 1 -+#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff -+#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000 -+#define RO_MTX_LEN_CNT_1_SFT 0 -+#define RO_MTX_LEN_CNT_1_HI 15 -+#define RO_MTX_LEN_CNT_1_SZ 16 -+#define RO_MTX_LEN_CNT_0_MSK 0xffff0000 -+#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff -+#define RO_MTX_LEN_CNT_0_SFT 16 -+#define RO_MTX_LEN_CNT_0_HI 31 -+#define RO_MTX_LEN_CNT_0_SZ 16 -+#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff -+#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000 -+#define RO_MRX_LEN_CNT_1_SFT 0 -+#define RO_MRX_LEN_CNT_1_HI 15 -+#define RO_MRX_LEN_CNT_1_SZ 16 -+#define RO_MRX_LEN_CNT_0_MSK 0xffff0000 -+#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff -+#define RO_MRX_LEN_CNT_0_SFT 16 -+#define RO_MRX_LEN_CNT_0_HI 31 -+#define RO_MRX_LEN_CNT_0_SZ 16 -+#define RG_MODE_REG_IN_16_MSK 0x0000ffff -+#define RG_MODE_REG_IN_16_I_MSK 0xffff0000 -+#define RG_MODE_REG_IN_16_SFT 0 -+#define RG_MODE_REG_IN_16_HI 15 -+#define RG_MODE_REG_IN_16_SZ 16 -+#define RG_PARALLEL_DR_16_MSK 0x00100000 -+#define RG_PARALLEL_DR_16_I_MSK 0xffefffff -+#define RG_PARALLEL_DR_16_SFT 20 -+#define RG_PARALLEL_DR_16_HI 20 -+#define RG_PARALLEL_DR_16_SZ 1 -+#define RG_MBRUN_16_MSK 0x01000000 -+#define RG_MBRUN_16_I_MSK 0xfeffffff -+#define RG_MBRUN_16_SFT 24 -+#define RG_MBRUN_16_HI 24 -+#define RG_MBRUN_16_SZ 1 -+#define RG_SHIFT_DR_16_MSK 0x10000000 -+#define RG_SHIFT_DR_16_I_MSK 0xefffffff -+#define RG_SHIFT_DR_16_SFT 28 -+#define RG_SHIFT_DR_16_HI 28 -+#define RG_SHIFT_DR_16_SZ 1 -+#define RG_MODE_REG_SI_16_MSK 0x20000000 -+#define RG_MODE_REG_SI_16_I_MSK 0xdfffffff -+#define RG_MODE_REG_SI_16_SFT 29 -+#define RG_MODE_REG_SI_16_HI 29 -+#define RG_MODE_REG_SI_16_SZ 1 -+#define RG_SIMULATION_MODE_16_MSK 0x40000000 -+#define RG_SIMULATION_MODE_16_I_MSK 0xbfffffff -+#define RG_SIMULATION_MODE_16_SFT 30 -+#define RG_SIMULATION_MODE_16_HI 30 -+#define RG_SIMULATION_MODE_16_SZ 1 -+#define RG_DBIST_MODE_16_MSK 0x80000000 -+#define RG_DBIST_MODE_16_I_MSK 0x7fffffff -+#define RG_DBIST_MODE_16_SFT 31 -+#define RG_DBIST_MODE_16_HI 31 -+#define RG_DBIST_MODE_16_SZ 1 -+#define RO_MODE_REG_OUT_16_MSK 0x0000ffff -+#define RO_MODE_REG_OUT_16_I_MSK 0xffff0000 -+#define RO_MODE_REG_OUT_16_SFT 0 -+#define RO_MODE_REG_OUT_16_HI 15 -+#define RO_MODE_REG_OUT_16_SZ 16 -+#define RO_MODE_REG_SO_16_MSK 0x01000000 -+#define RO_MODE_REG_SO_16_I_MSK 0xfeffffff -+#define RO_MODE_REG_SO_16_SFT 24 -+#define RO_MODE_REG_SO_16_HI 24 -+#define RO_MODE_REG_SO_16_SZ 1 -+#define RO_MONITOR_BUS_16_MSK 0x0007ffff -+#define RO_MONITOR_BUS_16_I_MSK 0xfff80000 -+#define RO_MONITOR_BUS_16_SFT 0 -+#define RO_MONITOR_BUS_16_HI 18 -+#define RO_MONITOR_BUS_16_SZ 19 -+#define RG_MRX_TYPE_1_MSK 0x000000ff -+#define RG_MRX_TYPE_1_I_MSK 0xffffff00 -+#define RG_MRX_TYPE_1_SFT 0 -+#define RG_MRX_TYPE_1_HI 7 -+#define RG_MRX_TYPE_1_SZ 8 -+#define RG_MRX_TYPE_0_MSK 0x0000ff00 -+#define RG_MRX_TYPE_0_I_MSK 0xffff00ff -+#define RG_MRX_TYPE_0_SFT 8 -+#define RG_MRX_TYPE_0_HI 15 -+#define RG_MRX_TYPE_0_SZ 8 -+#define RG_MTX_TYPE_1_MSK 0x00ff0000 -+#define RG_MTX_TYPE_1_I_MSK 0xff00ffff -+#define RG_MTX_TYPE_1_SFT 16 -+#define RG_MTX_TYPE_1_HI 23 -+#define RG_MTX_TYPE_1_SZ 8 -+#define RG_MTX_TYPE_0_MSK 0xff000000 -+#define RG_MTX_TYPE_0_I_MSK 0x00ffffff -+#define RG_MTX_TYPE_0_SFT 24 -+#define RG_MTX_TYPE_0_HI 31 -+#define RG_MTX_TYPE_0_SZ 8 -+#define RO_MTX_TYPE_CNT_1_MSK 0x0000ffff -+#define RO_MTX_TYPE_CNT_1_I_MSK 0xffff0000 -+#define RO_MTX_TYPE_CNT_1_SFT 0 -+#define RO_MTX_TYPE_CNT_1_HI 15 -+#define RO_MTX_TYPE_CNT_1_SZ 16 -+#define RO_MTX_TYPE_CNT_0_MSK 0xffff0000 -+#define RO_MTX_TYPE_CNT_0_I_MSK 0x0000ffff -+#define RO_MTX_TYPE_CNT_0_SFT 16 -+#define RO_MTX_TYPE_CNT_0_HI 31 -+#define RO_MTX_TYPE_CNT_0_SZ 16 -+#define RO_MRX_TYPE_CNT_1_MSK 0x0000ffff -+#define RO_MRX_TYPE_CNT_1_I_MSK 0xffff0000 -+#define RO_MRX_TYPE_CNT_1_SFT 0 -+#define RO_MRX_TYPE_CNT_1_HI 15 -+#define RO_MRX_TYPE_CNT_1_SZ 16 -+#define RO_MRX_TYPE_CNT_0_MSK 0xffff0000 -+#define RO_MRX_TYPE_CNT_0_I_MSK 0x0000ffff -+#define RO_MRX_TYPE_CNT_0_SFT 16 -+#define RO_MRX_TYPE_CNT_0_HI 31 -+#define RO_MRX_TYPE_CNT_0_SZ 16 -+#define RG_HB_COEF0_MSK 0x00000fff -+#define RG_HB_COEF0_I_MSK 0xfffff000 -+#define RG_HB_COEF0_SFT 0 -+#define RG_HB_COEF0_HI 11 -+#define RG_HB_COEF0_SZ 12 -+#define RG_HB_COEF1_MSK 0x0fff0000 -+#define RG_HB_COEF1_I_MSK 0xf000ffff -+#define RG_HB_COEF1_SFT 16 -+#define RG_HB_COEF1_HI 27 -+#define RG_HB_COEF1_SZ 12 -+#define RG_HB_COEF2_MSK 0x00000fff -+#define RG_HB_COEF2_I_MSK 0xfffff000 -+#define RG_HB_COEF2_SFT 0 -+#define RG_HB_COEF2_HI 11 -+#define RG_HB_COEF2_SZ 12 -+#define RG_HB_COEF3_MSK 0x0fff0000 -+#define RG_HB_COEF3_I_MSK 0xf000ffff -+#define RG_HB_COEF3_SFT 16 -+#define RG_HB_COEF3_HI 27 -+#define RG_HB_COEF3_SZ 12 -+#define RG_HB_COEF4_MSK 0x00000fff -+#define RG_HB_COEF4_I_MSK 0xfffff000 -+#define RG_HB_COEF4_SFT 0 -+#define RG_HB_COEF4_HI 11 -+#define RG_HB_COEF4_SZ 12 -+#define RO_TBUS_O_MSK 0x000fffff -+#define RO_TBUS_O_I_MSK 0xfff00000 -+#define RO_TBUS_O_SFT 0 -+#define RO_TBUS_O_HI 19 -+#define RO_TBUS_O_SZ 20 -+#define RG_LPF4_00_MSK 0x00001fff -+#define RG_LPF4_00_I_MSK 0xffffe000 -+#define RG_LPF4_00_SFT 0 -+#define RG_LPF4_00_HI 12 -+#define RG_LPF4_00_SZ 13 -+#define RG_LPF4_01_MSK 0x00001fff -+#define RG_LPF4_01_I_MSK 0xffffe000 -+#define RG_LPF4_01_SFT 0 -+#define RG_LPF4_01_HI 12 -+#define RG_LPF4_01_SZ 13 -+#define RG_LPF4_02_MSK 0x00001fff -+#define RG_LPF4_02_I_MSK 0xffffe000 -+#define RG_LPF4_02_SFT 0 -+#define RG_LPF4_02_HI 12 -+#define RG_LPF4_02_SZ 13 -+#define RG_LPF4_03_MSK 0x00001fff -+#define RG_LPF4_03_I_MSK 0xffffe000 -+#define RG_LPF4_03_SFT 0 -+#define RG_LPF4_03_HI 12 -+#define RG_LPF4_03_SZ 13 -+#define RG_LPF4_04_MSK 0x00001fff -+#define RG_LPF4_04_I_MSK 0xffffe000 -+#define RG_LPF4_04_SFT 0 -+#define RG_LPF4_04_HI 12 -+#define RG_LPF4_04_SZ 13 -+#define RG_LPF4_05_MSK 0x00001fff -+#define RG_LPF4_05_I_MSK 0xffffe000 -+#define RG_LPF4_05_SFT 0 -+#define RG_LPF4_05_HI 12 -+#define RG_LPF4_05_SZ 13 -+#define RG_LPF4_06_MSK 0x00001fff -+#define RG_LPF4_06_I_MSK 0xffffe000 -+#define RG_LPF4_06_SFT 0 -+#define RG_LPF4_06_HI 12 -+#define RG_LPF4_06_SZ 13 -+#define RG_LPF4_07_MSK 0x00001fff -+#define RG_LPF4_07_I_MSK 0xffffe000 -+#define RG_LPF4_07_SFT 0 -+#define RG_LPF4_07_HI 12 -+#define RG_LPF4_07_SZ 13 -+#define RG_LPF4_08_MSK 0x00001fff -+#define RG_LPF4_08_I_MSK 0xffffe000 -+#define RG_LPF4_08_SFT 0 -+#define RG_LPF4_08_HI 12 -+#define RG_LPF4_08_SZ 13 -+#define RG_LPF4_09_MSK 0x00001fff -+#define RG_LPF4_09_I_MSK 0xffffe000 -+#define RG_LPF4_09_SFT 0 -+#define RG_LPF4_09_HI 12 -+#define RG_LPF4_09_SZ 13 -+#define RG_LPF4_10_MSK 0x00001fff -+#define RG_LPF4_10_I_MSK 0xffffe000 -+#define RG_LPF4_10_SFT 0 -+#define RG_LPF4_10_HI 12 -+#define RG_LPF4_10_SZ 13 -+#define RG_LPF4_11_MSK 0x00001fff -+#define RG_LPF4_11_I_MSK 0xffffe000 -+#define RG_LPF4_11_SFT 0 -+#define RG_LPF4_11_HI 12 -+#define RG_LPF4_11_SZ 13 -+#define RG_LPF4_12_MSK 0x00001fff -+#define RG_LPF4_12_I_MSK 0xffffe000 -+#define RG_LPF4_12_SFT 0 -+#define RG_LPF4_12_HI 12 -+#define RG_LPF4_12_SZ 13 -+#define RG_LPF4_13_MSK 0x00001fff -+#define RG_LPF4_13_I_MSK 0xffffe000 -+#define RG_LPF4_13_SFT 0 -+#define RG_LPF4_13_HI 12 -+#define RG_LPF4_13_SZ 13 -+#define RG_LPF4_14_MSK 0x00001fff -+#define RG_LPF4_14_I_MSK 0xffffe000 -+#define RG_LPF4_14_SFT 0 -+#define RG_LPF4_14_HI 12 -+#define RG_LPF4_14_SZ 13 -+#define RG_LPF4_15_MSK 0x00001fff -+#define RG_LPF4_15_I_MSK 0xffffe000 -+#define RG_LPF4_15_SFT 0 -+#define RG_LPF4_15_HI 12 -+#define RG_LPF4_15_SZ 13 -+#define RG_LPF4_16_MSK 0x00001fff -+#define RG_LPF4_16_I_MSK 0xffffe000 -+#define RG_LPF4_16_SFT 0 -+#define RG_LPF4_16_HI 12 -+#define RG_LPF4_16_SZ 13 -+#define RG_LPF4_17_MSK 0x00001fff -+#define RG_LPF4_17_I_MSK 0xffffe000 -+#define RG_LPF4_17_SFT 0 -+#define RG_LPF4_17_HI 12 -+#define RG_LPF4_17_SZ 13 -+#define RG_LPF4_18_MSK 0x00001fff -+#define RG_LPF4_18_I_MSK 0xffffe000 -+#define RG_LPF4_18_SFT 0 -+#define RG_LPF4_18_HI 12 -+#define RG_LPF4_18_SZ 13 -+#define RG_LPF4_19_MSK 0x00001fff -+#define RG_LPF4_19_I_MSK 0xffffe000 -+#define RG_LPF4_19_SFT 0 -+#define RG_LPF4_19_HI 12 -+#define RG_LPF4_19_SZ 13 -+#define RG_LPF4_20_MSK 0x00001fff -+#define RG_LPF4_20_I_MSK 0xffffe000 -+#define RG_LPF4_20_SFT 0 -+#define RG_LPF4_20_HI 12 -+#define RG_LPF4_20_SZ 13 -+#define RG_LPF4_21_MSK 0x00001fff -+#define RG_LPF4_21_I_MSK 0xffffe000 -+#define RG_LPF4_21_SFT 0 -+#define RG_LPF4_21_HI 12 -+#define RG_LPF4_21_SZ 13 -+#define RG_LPF4_22_MSK 0x00001fff -+#define RG_LPF4_22_I_MSK 0xffffe000 -+#define RG_LPF4_22_SFT 0 -+#define RG_LPF4_22_HI 12 -+#define RG_LPF4_22_SZ 13 -+#define RG_LPF4_23_MSK 0x00001fff -+#define RG_LPF4_23_I_MSK 0xffffe000 -+#define RG_LPF4_23_SFT 0 -+#define RG_LPF4_23_HI 12 -+#define RG_LPF4_23_SZ 13 -+#define RG_LPF4_24_MSK 0x00001fff -+#define RG_LPF4_24_I_MSK 0xffffe000 -+#define RG_LPF4_24_SFT 0 -+#define RG_LPF4_24_HI 12 -+#define RG_LPF4_24_SZ 13 -+#define RG_LPF4_25_MSK 0x00001fff -+#define RG_LPF4_25_I_MSK 0xffffe000 -+#define RG_LPF4_25_SFT 0 -+#define RG_LPF4_25_HI 12 -+#define RG_LPF4_25_SZ 13 -+#define RG_LPF4_26_MSK 0x00001fff -+#define RG_LPF4_26_I_MSK 0xffffe000 -+#define RG_LPF4_26_SFT 0 -+#define RG_LPF4_26_HI 12 -+#define RG_LPF4_26_SZ 13 -+#define RG_LPF4_27_MSK 0x00001fff -+#define RG_LPF4_27_I_MSK 0xffffe000 -+#define RG_LPF4_27_SFT 0 -+#define RG_LPF4_27_HI 12 -+#define RG_LPF4_27_SZ 13 -+#define RG_LPF4_28_MSK 0x00001fff -+#define RG_LPF4_28_I_MSK 0xffffe000 -+#define RG_LPF4_28_SFT 0 -+#define RG_LPF4_28_HI 12 -+#define RG_LPF4_28_SZ 13 -+#define RG_LPF4_29_MSK 0x00001fff -+#define RG_LPF4_29_I_MSK 0xffffe000 -+#define RG_LPF4_29_SFT 0 -+#define RG_LPF4_29_HI 12 -+#define RG_LPF4_29_SZ 13 -+#define RG_LPF4_30_MSK 0x00001fff -+#define RG_LPF4_30_I_MSK 0xffffe000 -+#define RG_LPF4_30_SFT 0 -+#define RG_LPF4_30_HI 12 -+#define RG_LPF4_30_SZ 13 -+#define RG_LPF4_31_MSK 0x00001fff -+#define RG_LPF4_31_I_MSK 0xffffe000 -+#define RG_LPF4_31_SFT 0 -+#define RG_LPF4_31_HI 12 -+#define RG_LPF4_31_SZ 13 -+#define RG_LPF4_32_MSK 0x00001fff -+#define RG_LPF4_32_I_MSK 0xffffe000 -+#define RG_LPF4_32_SFT 0 -+#define RG_LPF4_32_HI 12 -+#define RG_LPF4_32_SZ 13 -+#define RG_LPF4_33_MSK 0x00001fff -+#define RG_LPF4_33_I_MSK 0xffffe000 -+#define RG_LPF4_33_SFT 0 -+#define RG_LPF4_33_HI 12 -+#define RG_LPF4_33_SZ 13 -+#define RG_LPF4_34_MSK 0x00001fff -+#define RG_LPF4_34_I_MSK 0xffffe000 -+#define RG_LPF4_34_SFT 0 -+#define RG_LPF4_34_HI 12 -+#define RG_LPF4_34_SZ 13 -+#define RG_LPF4_35_MSK 0x00001fff -+#define RG_LPF4_35_I_MSK 0xffffe000 -+#define RG_LPF4_35_SFT 0 -+#define RG_LPF4_35_HI 12 -+#define RG_LPF4_35_SZ 13 -+#define RG_LPF4_36_MSK 0x00001fff -+#define RG_LPF4_36_I_MSK 0xffffe000 -+#define RG_LPF4_36_SFT 0 -+#define RG_LPF4_36_HI 12 -+#define RG_LPF4_36_SZ 13 -+#define RG_LPF4_37_MSK 0x00001fff -+#define RG_LPF4_37_I_MSK 0xffffe000 -+#define RG_LPF4_37_SFT 0 -+#define RG_LPF4_37_HI 12 -+#define RG_LPF4_37_SZ 13 -+#define RG_LPF4_38_MSK 0x00001fff -+#define RG_LPF4_38_I_MSK 0xffffe000 -+#define RG_LPF4_38_SFT 0 -+#define RG_LPF4_38_HI 12 -+#define RG_LPF4_38_SZ 13 -+#define RG_LPF4_39_MSK 0x00001fff -+#define RG_LPF4_39_I_MSK 0xffffe000 -+#define RG_LPF4_39_SFT 0 -+#define RG_LPF4_39_HI 12 -+#define RG_LPF4_39_SZ 13 -+#define RG_LPF4_40_MSK 0x00001fff -+#define RG_LPF4_40_I_MSK 0xffffe000 -+#define RG_LPF4_40_SFT 0 -+#define RG_LPF4_40_HI 12 -+#define RG_LPF4_40_SZ 13 -+#define RG_BP_SMB_MSK 0x00002000 -+#define RG_BP_SMB_I_MSK 0xffffdfff -+#define RG_BP_SMB_SFT 13 -+#define RG_BP_SMB_HI 13 -+#define RG_BP_SMB_SZ 1 -+#define RG_EN_SRVC_MSK 0x00004000 -+#define RG_EN_SRVC_I_MSK 0xffffbfff -+#define RG_EN_SRVC_SFT 14 -+#define RG_EN_SRVC_HI 14 -+#define RG_EN_SRVC_SZ 1 -+#define RG_DES_SPD_MSK 0x00030000 -+#define RG_DES_SPD_I_MSK 0xfffcffff -+#define RG_DES_SPD_SFT 16 -+#define RG_DES_SPD_HI 17 -+#define RG_DES_SPD_SZ 2 -+#define RG_BB_11B_RISE_TIME_MSK 0x000000ff -+#define RG_BB_11B_RISE_TIME_I_MSK 0xffffff00 -+#define RG_BB_11B_RISE_TIME_SFT 0 -+#define RG_BB_11B_RISE_TIME_HI 7 -+#define RG_BB_11B_RISE_TIME_SZ 8 -+#define RG_BB_11B_FALL_TIME_MSK 0x0000ff00 -+#define RG_BB_11B_FALL_TIME_I_MSK 0xffff00ff -+#define RG_BB_11B_FALL_TIME_SFT 8 -+#define RG_BB_11B_FALL_TIME_HI 15 -+#define RG_BB_11B_FALL_TIME_SZ 8 -+#define RG_WR_TX_EN_CNT_RST_N_MSK 0x00000001 -+#define RG_WR_TX_EN_CNT_RST_N_I_MSK 0xfffffffe -+#define RG_WR_TX_EN_CNT_RST_N_SFT 0 -+#define RG_WR_TX_EN_CNT_RST_N_HI 0 -+#define RG_WR_TX_EN_CNT_RST_N_SZ 1 -+#define RO_TX_EN_CNT_MSK 0x0000ffff -+#define RO_TX_EN_CNT_I_MSK 0xffff0000 -+#define RO_TX_EN_CNT_SFT 0 -+#define RO_TX_EN_CNT_HI 15 -+#define RO_TX_EN_CNT_SZ 16 -+#define RO_TX_CNT_MSK 0xffffffff -+#define RO_TX_CNT_I_MSK 0x00000000 -+#define RO_TX_CNT_SFT 0 -+#define RO_TX_CNT_HI 31 -+#define RO_TX_CNT_SZ 32 -+#define RG_POS_DES_11B_L_EXT_MSK 0x0000000f -+#define RG_POS_DES_11B_L_EXT_I_MSK 0xfffffff0 -+#define RG_POS_DES_11B_L_EXT_SFT 0 -+#define RG_POS_DES_11B_L_EXT_HI 3 -+#define RG_POS_DES_11B_L_EXT_SZ 4 -+#define RG_PRE_DES_11B_DLY_MSK 0x000000f0 -+#define RG_PRE_DES_11B_DLY_I_MSK 0xffffff0f -+#define RG_PRE_DES_11B_DLY_SFT 4 -+#define RG_PRE_DES_11B_DLY_HI 7 -+#define RG_PRE_DES_11B_DLY_SZ 4 -+#define RG_CNT_CCA_LMT_MSK 0x000f0000 -+#define RG_CNT_CCA_LMT_I_MSK 0xfff0ffff -+#define RG_CNT_CCA_LMT_SFT 16 -+#define RG_CNT_CCA_LMT_HI 19 -+#define RG_CNT_CCA_LMT_SZ 4 -+#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000 -+#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff -+#define RG_BYPASS_DESCRAMBLER_SFT 29 -+#define RG_BYPASS_DESCRAMBLER_HI 29 -+#define RG_BYPASS_DESCRAMBLER_SZ 1 -+#define RG_BYPASS_AGC_MSK 0x80000000 -+#define RG_BYPASS_AGC_I_MSK 0x7fffffff -+#define RG_BYPASS_AGC_SFT 31 -+#define RG_BYPASS_AGC_HI 31 -+#define RG_BYPASS_AGC_SZ 1 -+#define RG_CCA_BIT_CNT_LMT_RX_MSK 0x000000f0 -+#define RG_CCA_BIT_CNT_LMT_RX_I_MSK 0xffffff0f -+#define RG_CCA_BIT_CNT_LMT_RX_SFT 4 -+#define RG_CCA_BIT_CNT_LMT_RX_HI 7 -+#define RG_CCA_BIT_CNT_LMT_RX_SZ 4 -+#define RG_CCA_SCALE_BF_MSK 0x007f0000 -+#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff -+#define RG_CCA_SCALE_BF_SFT 16 -+#define RG_CCA_SCALE_BF_HI 22 -+#define RG_CCA_SCALE_BF_SZ 7 -+#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000 -+#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff -+#define RG_PEAK_IDX_CNT_SEL_SFT 28 -+#define RG_PEAK_IDX_CNT_SEL_HI 29 -+#define RG_PEAK_IDX_CNT_SEL_SZ 2 -+#define RG_TR_KI_T2_MSK 0x00000007 -+#define RG_TR_KI_T2_I_MSK 0xfffffff8 -+#define RG_TR_KI_T2_SFT 0 -+#define RG_TR_KI_T2_HI 2 -+#define RG_TR_KI_T2_SZ 3 -+#define RG_TR_KP_T2_MSK 0x00000070 -+#define RG_TR_KP_T2_I_MSK 0xffffff8f -+#define RG_TR_KP_T2_SFT 4 -+#define RG_TR_KP_T2_HI 6 -+#define RG_TR_KP_T2_SZ 3 -+#define RG_TR_KI_T1_MSK 0x00000700 -+#define RG_TR_KI_T1_I_MSK 0xfffff8ff -+#define RG_TR_KI_T1_SFT 8 -+#define RG_TR_KI_T1_HI 10 -+#define RG_TR_KI_T1_SZ 3 -+#define RG_TR_KP_T1_MSK 0x00007000 -+#define RG_TR_KP_T1_I_MSK 0xffff8fff -+#define RG_TR_KP_T1_SFT 12 -+#define RG_TR_KP_T1_HI 14 -+#define RG_TR_KP_T1_SZ 3 -+#define RG_CR_KI_T1_MSK 0x00070000 -+#define RG_CR_KI_T1_I_MSK 0xfff8ffff -+#define RG_CR_KI_T1_SFT 16 -+#define RG_CR_KI_T1_HI 18 -+#define RG_CR_KI_T1_SZ 3 -+#define RG_CR_KP_T1_MSK 0x00700000 -+#define RG_CR_KP_T1_I_MSK 0xff8fffff -+#define RG_CR_KP_T1_SFT 20 -+#define RG_CR_KP_T1_HI 22 -+#define RG_CR_KP_T1_SZ 3 -+#define RG_CHIP_CNT_SLICER_MSK 0x0000001f -+#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0 -+#define RG_CHIP_CNT_SLICER_SFT 0 -+#define RG_CHIP_CNT_SLICER_HI 4 -+#define RG_CHIP_CNT_SLICER_SZ 5 -+#define RG_CE_T4_CNT_LMT_MSK 0x0000ff00 -+#define RG_CE_T4_CNT_LMT_I_MSK 0xffff00ff -+#define RG_CE_T4_CNT_LMT_SFT 8 -+#define RG_CE_T4_CNT_LMT_HI 15 -+#define RG_CE_T4_CNT_LMT_SZ 8 -+#define RG_CE_T3_CNT_LMT_MSK 0x00ff0000 -+#define RG_CE_T3_CNT_LMT_I_MSK 0xff00ffff -+#define RG_CE_T3_CNT_LMT_SFT 16 -+#define RG_CE_T3_CNT_LMT_HI 23 -+#define RG_CE_T3_CNT_LMT_SZ 8 -+#define RG_CE_T2_CNT_LMT_MSK 0xff000000 -+#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff -+#define RG_CE_T2_CNT_LMT_SFT 24 -+#define RG_CE_T2_CNT_LMT_HI 31 -+#define RG_CE_T2_CNT_LMT_SZ 8 -+#define RG_CE_MU_T1_MSK 0x00000007 -+#define RG_CE_MU_T1_I_MSK 0xfffffff8 -+#define RG_CE_MU_T1_SFT 0 -+#define RG_CE_MU_T1_HI 2 -+#define RG_CE_MU_T1_SZ 3 -+#define RG_CE_DLY_SEL_MSK 0x003f0000 -+#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff -+#define RG_CE_DLY_SEL_SFT 16 -+#define RG_CE_DLY_SEL_HI 21 -+#define RG_CE_DLY_SEL_SZ 6 -+#define RG_CE_MU_T8_MSK 0x00000007 -+#define RG_CE_MU_T8_I_MSK 0xfffffff8 -+#define RG_CE_MU_T8_SFT 0 -+#define RG_CE_MU_T8_HI 2 -+#define RG_CE_MU_T8_SZ 3 -+#define RG_CE_MU_T7_MSK 0x00000070 -+#define RG_CE_MU_T7_I_MSK 0xffffff8f -+#define RG_CE_MU_T7_SFT 4 -+#define RG_CE_MU_T7_HI 6 -+#define RG_CE_MU_T7_SZ 3 -+#define RG_CE_MU_T6_MSK 0x00000700 -+#define RG_CE_MU_T6_I_MSK 0xfffff8ff -+#define RG_CE_MU_T6_SFT 8 -+#define RG_CE_MU_T6_HI 10 -+#define RG_CE_MU_T6_SZ 3 -+#define RG_CE_MU_T5_MSK 0x00007000 -+#define RG_CE_MU_T5_I_MSK 0xffff8fff -+#define RG_CE_MU_T5_SFT 12 -+#define RG_CE_MU_T5_HI 14 -+#define RG_CE_MU_T5_SZ 3 -+#define RG_CE_MU_T4_MSK 0x00070000 -+#define RG_CE_MU_T4_I_MSK 0xfff8ffff -+#define RG_CE_MU_T4_SFT 16 -+#define RG_CE_MU_T4_HI 18 -+#define RG_CE_MU_T4_SZ 3 -+#define RG_CE_MU_T3_MSK 0x00700000 -+#define RG_CE_MU_T3_I_MSK 0xff8fffff -+#define RG_CE_MU_T3_SFT 20 -+#define RG_CE_MU_T3_HI 22 -+#define RG_CE_MU_T3_SZ 3 -+#define RG_CE_MU_T2_MSK 0x07000000 -+#define RG_CE_MU_T2_I_MSK 0xf8ffffff -+#define RG_CE_MU_T2_SFT 24 -+#define RG_CE_MU_T2_HI 26 -+#define RG_CE_MU_T2_SZ 3 -+#define RG_EQ_MU_FB_T2_MSK 0x0000000f -+#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0 -+#define RG_EQ_MU_FB_T2_SFT 0 -+#define RG_EQ_MU_FB_T2_HI 3 -+#define RG_EQ_MU_FB_T2_SZ 4 -+#define RG_EQ_MU_FF_T2_MSK 0x000000f0 -+#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f -+#define RG_EQ_MU_FF_T2_SFT 4 -+#define RG_EQ_MU_FF_T2_HI 7 -+#define RG_EQ_MU_FF_T2_SZ 4 -+#define RG_EQ_MU_FB_T1_MSK 0x000f0000 -+#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff -+#define RG_EQ_MU_FB_T1_SFT 16 -+#define RG_EQ_MU_FB_T1_HI 19 -+#define RG_EQ_MU_FB_T1_SZ 4 -+#define RG_EQ_MU_FF_T1_MSK 0x00f00000 -+#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff -+#define RG_EQ_MU_FF_T1_SFT 20 -+#define RG_EQ_MU_FF_T1_HI 23 -+#define RG_EQ_MU_FF_T1_SZ 4 -+#define RG_EQ_MU_FB_T4_MSK 0x0000000f -+#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0 -+#define RG_EQ_MU_FB_T4_SFT 0 -+#define RG_EQ_MU_FB_T4_HI 3 -+#define RG_EQ_MU_FB_T4_SZ 4 -+#define RG_EQ_MU_FF_T4_MSK 0x000000f0 -+#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f -+#define RG_EQ_MU_FF_T4_SFT 4 -+#define RG_EQ_MU_FF_T4_HI 7 -+#define RG_EQ_MU_FF_T4_SZ 4 -+#define RG_EQ_MU_FB_T3_MSK 0x000f0000 -+#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff -+#define RG_EQ_MU_FB_T3_SFT 16 -+#define RG_EQ_MU_FB_T3_HI 19 -+#define RG_EQ_MU_FB_T3_SZ 4 -+#define RG_EQ_MU_FF_T3_MSK 0x00f00000 -+#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff -+#define RG_EQ_MU_FF_T3_SFT 20 -+#define RG_EQ_MU_FF_T3_HI 23 -+#define RG_EQ_MU_FF_T3_SZ 4 -+#define RG_EQ_KI_T2_MSK 0x00000700 -+#define RG_EQ_KI_T2_I_MSK 0xfffff8ff -+#define RG_EQ_KI_T2_SFT 8 -+#define RG_EQ_KI_T2_HI 10 -+#define RG_EQ_KI_T2_SZ 3 -+#define RG_EQ_KP_T2_MSK 0x00007000 -+#define RG_EQ_KP_T2_I_MSK 0xffff8fff -+#define RG_EQ_KP_T2_SFT 12 -+#define RG_EQ_KP_T2_HI 14 -+#define RG_EQ_KP_T2_SZ 3 -+#define RG_EQ_KI_T1_MSK 0x00070000 -+#define RG_EQ_KI_T1_I_MSK 0xfff8ffff -+#define RG_EQ_KI_T1_SFT 16 -+#define RG_EQ_KI_T1_HI 18 -+#define RG_EQ_KI_T1_SZ 3 -+#define RG_EQ_KP_T1_MSK 0x00700000 -+#define RG_EQ_KP_T1_I_MSK 0xff8fffff -+#define RG_EQ_KP_T1_SFT 20 -+#define RG_EQ_KP_T1_HI 22 -+#define RG_EQ_KP_T1_SZ 3 -+#define RG_TR_LPF_RATE_MSK 0x003fffff -+#define RG_TR_LPF_RATE_I_MSK 0xffc00000 -+#define RG_TR_LPF_RATE_SFT 0 -+#define RG_TR_LPF_RATE_HI 21 -+#define RG_TR_LPF_RATE_SZ 22 -+#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f -+#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80 -+#define RG_CE_BIT_CNT_LMT_SFT 0 -+#define RG_CE_BIT_CNT_LMT_HI 6 -+#define RG_CE_BIT_CNT_LMT_SZ 7 -+#define RG_CE_CH_MAIN_SET_MSK 0x00000080 -+#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f -+#define RG_CE_CH_MAIN_SET_SFT 7 -+#define RG_CE_CH_MAIN_SET_HI 7 -+#define RG_CE_CH_MAIN_SET_SZ 1 -+#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00 -+#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff -+#define RG_TC_BIT_CNT_LMT_SFT 8 -+#define RG_TC_BIT_CNT_LMT_HI 14 -+#define RG_TC_BIT_CNT_LMT_SZ 7 -+#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000 -+#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff -+#define RG_CR_BIT_CNT_LMT_SFT 16 -+#define RG_CR_BIT_CNT_LMT_HI 22 -+#define RG_CR_BIT_CNT_LMT_SZ 7 -+#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000 -+#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff -+#define RG_TR_BIT_CNT_LMT_SFT 24 -+#define RG_TR_BIT_CNT_LMT_HI 30 -+#define RG_TR_BIT_CNT_LMT_SZ 7 -+#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001 -+#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe -+#define RG_EQ_MAIN_TAP_MAN_SFT 0 -+#define RG_EQ_MAIN_TAP_MAN_HI 0 -+#define RG_EQ_MAIN_TAP_MAN_SZ 1 -+#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000 -+#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff -+#define RG_EQ_MAIN_TAP_COEF_SFT 16 -+#define RG_EQ_MAIN_TAP_COEF_HI 26 -+#define RG_EQ_MAIN_TAP_COEF_SZ 11 -+#define RG_PWRON_DLY_TH_11B_MSK 0x000000ff -+#define RG_PWRON_DLY_TH_11B_I_MSK 0xffffff00 -+#define RG_PWRON_DLY_TH_11B_SFT 0 -+#define RG_PWRON_DLY_TH_11B_HI 7 -+#define RG_PWRON_DLY_TH_11B_SZ 8 -+#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000 -+#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff -+#define RG_SFD_BIT_CNT_LMT_SFT 16 -+#define RG_SFD_BIT_CNT_LMT_HI 23 -+#define RG_SFD_BIT_CNT_LMT_SZ 8 -+#define RG_CCA_PWR_TH_RX_MSK 0x00007fff -+#define RG_CCA_PWR_TH_RX_I_MSK 0xffff8000 -+#define RG_CCA_PWR_TH_RX_SFT 0 -+#define RG_CCA_PWR_TH_RX_HI 14 -+#define RG_CCA_PWR_TH_RX_SZ 15 -+#define RG_CCA_PWR_CNT_TH_MSK 0x001f0000 -+#define RG_CCA_PWR_CNT_TH_I_MSK 0xffe0ffff -+#define RG_CCA_PWR_CNT_TH_SFT 16 -+#define RG_CCA_PWR_CNT_TH_HI 20 -+#define RG_CCA_PWR_CNT_TH_SZ 5 -+#define B_FREQ_OS_MSK 0x000007ff -+#define B_FREQ_OS_I_MSK 0xfffff800 -+#define B_FREQ_OS_SFT 0 -+#define B_FREQ_OS_HI 10 -+#define B_FREQ_OS_SZ 11 -+#define B_SNR_MSK 0x0000007f -+#define B_SNR_I_MSK 0xffffff80 -+#define B_SNR_SFT 0 -+#define B_SNR_HI 6 -+#define B_SNR_SZ 7 -+#define B_RCPI_MSK 0x007f0000 -+#define B_RCPI_I_MSK 0xff80ffff -+#define B_RCPI_SFT 16 -+#define B_RCPI_HI 22 -+#define B_RCPI_SZ 7 -+#define CRC_CNT_MSK 0x0000ffff -+#define CRC_CNT_I_MSK 0xffff0000 -+#define CRC_CNT_SFT 0 -+#define CRC_CNT_HI 15 -+#define CRC_CNT_SZ 16 -+#define SFD_CNT_MSK 0xffff0000 -+#define SFD_CNT_I_MSK 0x0000ffff -+#define SFD_CNT_SFT 16 -+#define SFD_CNT_HI 31 -+#define SFD_CNT_SZ 16 -+#define B_PACKET_ERR_CNT_MSK 0x0000ffff -+#define B_PACKET_ERR_CNT_I_MSK 0xffff0000 -+#define B_PACKET_ERR_CNT_SFT 0 -+#define B_PACKET_ERR_CNT_HI 15 -+#define B_PACKET_ERR_CNT_SZ 16 -+#define PACKET_ERR_MSK 0x00010000 -+#define PACKET_ERR_I_MSK 0xfffeffff -+#define PACKET_ERR_SFT 16 -+#define PACKET_ERR_HI 16 -+#define PACKET_ERR_SZ 1 -+#define B_PACKET_CNT_MSK 0x0000ffff -+#define B_PACKET_CNT_I_MSK 0xffff0000 -+#define B_PACKET_CNT_SFT 0 -+#define B_PACKET_CNT_HI 15 -+#define B_PACKET_CNT_SZ 16 -+#define B_CCA_CNT_MSK 0xffff0000 -+#define B_CCA_CNT_I_MSK 0x0000ffff -+#define B_CCA_CNT_SFT 16 -+#define B_CCA_CNT_HI 31 -+#define B_CCA_CNT_SZ 16 -+#define B_LENGTH_FIELD_MSK 0x0000ffff -+#define B_LENGTH_FIELD_I_MSK 0xffff0000 -+#define B_LENGTH_FIELD_SFT 0 -+#define B_LENGTH_FIELD_HI 15 -+#define B_LENGTH_FIELD_SZ 16 -+#define SFD_FIELD_MSK 0xffff0000 -+#define SFD_FIELD_I_MSK 0x0000ffff -+#define SFD_FIELD_SFT 16 -+#define SFD_FIELD_HI 31 -+#define SFD_FIELD_SZ 16 -+#define SIGNAL_FIELD_MSK 0x000000ff -+#define SIGNAL_FIELD_I_MSK 0xffffff00 -+#define SIGNAL_FIELD_SFT 0 -+#define SIGNAL_FIELD_HI 7 -+#define SIGNAL_FIELD_SZ 8 -+#define B_SERVICE_FIELD_MSK 0x0000ff00 -+#define B_SERVICE_FIELD_I_MSK 0xffff00ff -+#define B_SERVICE_FIELD_SFT 8 -+#define B_SERVICE_FIELD_HI 15 -+#define B_SERVICE_FIELD_SZ 8 -+#define CRC_CORRECT_MSK 0x00010000 -+#define CRC_CORRECT_I_MSK 0xfffeffff -+#define CRC_CORRECT_SFT 16 -+#define CRC_CORRECT_HI 16 -+#define CRC_CORRECT_SZ 1 -+#define DEBUG_SEL_MSK 0x0000000f -+#define DEBUG_SEL_I_MSK 0xfffffff0 -+#define DEBUG_SEL_SFT 0 -+#define DEBUG_SEL_HI 3 -+#define DEBUG_SEL_SZ 4 -+#define RG_PACKET_STAT_EN_11B_MSK 0x00100000 -+#define RG_PACKET_STAT_EN_11B_I_MSK 0xffefffff -+#define RG_PACKET_STAT_EN_11B_SFT 20 -+#define RG_PACKET_STAT_EN_11B_HI 20 -+#define RG_PACKET_STAT_EN_11B_SZ 1 -+#define RG_BIT_REVERSE_MSK 0x00200000 -+#define RG_BIT_REVERSE_I_MSK 0xffdfffff -+#define RG_BIT_REVERSE_SFT 21 -+#define RG_BIT_REVERSE_HI 21 -+#define RG_BIT_REVERSE_SZ 1 -+#define RX_PHY_11B_SOFT_RST_N_MSK 0x00000001 -+#define RX_PHY_11B_SOFT_RST_N_I_MSK 0xfffffffe -+#define RX_PHY_11B_SOFT_RST_N_SFT 0 -+#define RX_PHY_11B_SOFT_RST_N_HI 0 -+#define RX_PHY_11B_SOFT_RST_N_SZ 1 -+#define RG_CE_BYPASS_TAP_MSK 0x000000f0 -+#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f -+#define RG_CE_BYPASS_TAP_SFT 4 -+#define RG_CE_BYPASS_TAP_HI 7 -+#define RG_CE_BYPASS_TAP_SZ 4 -+#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00 -+#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff -+#define RG_EQ_BYPASS_FBW_TAP_SFT 8 -+#define RG_EQ_BYPASS_FBW_TAP_HI 11 -+#define RG_EQ_BYPASS_FBW_TAP_SZ 4 -+#define RG_BB_11GN_RISE_TIME_MSK 0x000000ff -+#define RG_BB_11GN_RISE_TIME_I_MSK 0xffffff00 -+#define RG_BB_11GN_RISE_TIME_SFT 0 -+#define RG_BB_11GN_RISE_TIME_HI 7 -+#define RG_BB_11GN_RISE_TIME_SZ 8 -+#define RG_BB_11GN_FALL_TIME_MSK 0x0000ff00 -+#define RG_BB_11GN_FALL_TIME_I_MSK 0xffff00ff -+#define RG_BB_11GN_FALL_TIME_SFT 8 -+#define RG_BB_11GN_FALL_TIME_HI 15 -+#define RG_BB_11GN_FALL_TIME_SZ 8 -+#define RG_HTCARR52_FFT_SCALE_MSK 0x000003ff -+#define RG_HTCARR52_FFT_SCALE_I_MSK 0xfffffc00 -+#define RG_HTCARR52_FFT_SCALE_SFT 0 -+#define RG_HTCARR52_FFT_SCALE_HI 9 -+#define RG_HTCARR52_FFT_SCALE_SZ 10 -+#define RG_HTCARR56_FFT_SCALE_MSK 0x003ff000 -+#define RG_HTCARR56_FFT_SCALE_I_MSK 0xffc00fff -+#define RG_HTCARR56_FFT_SCALE_SFT 12 -+#define RG_HTCARR56_FFT_SCALE_HI 21 -+#define RG_HTCARR56_FFT_SCALE_SZ 10 -+#define RG_PACKET_STAT_EN_MSK 0x00800000 -+#define RG_PACKET_STAT_EN_I_MSK 0xff7fffff -+#define RG_PACKET_STAT_EN_SFT 23 -+#define RG_PACKET_STAT_EN_HI 23 -+#define RG_PACKET_STAT_EN_SZ 1 -+#define RG_SMB_DEF_MSK 0x7f000000 -+#define RG_SMB_DEF_I_MSK 0x80ffffff -+#define RG_SMB_DEF_SFT 24 -+#define RG_SMB_DEF_HI 30 -+#define RG_SMB_DEF_SZ 7 -+#define RG_CONTINUOUS_DATA_11GN_MSK 0x80000000 -+#define RG_CONTINUOUS_DATA_11GN_I_MSK 0x7fffffff -+#define RG_CONTINUOUS_DATA_11GN_SFT 31 -+#define RG_CONTINUOUS_DATA_11GN_HI 31 -+#define RG_CONTINUOUS_DATA_11GN_SZ 1 -+#define RO_TX_CNT_R_MSK 0xffffffff -+#define RO_TX_CNT_R_I_MSK 0x00000000 -+#define RO_TX_CNT_R_SFT 0 -+#define RO_TX_CNT_R_HI 31 -+#define RO_TX_CNT_R_SZ 32 -+#define RO_PACKET_ERR_CNT_MSK 0x0000ffff -+#define RO_PACKET_ERR_CNT_I_MSK 0xffff0000 -+#define RO_PACKET_ERR_CNT_SFT 0 -+#define RO_PACKET_ERR_CNT_HI 15 -+#define RO_PACKET_ERR_CNT_SZ 16 -+#define RG_POS_DES_11GN_L_EXT_MSK 0x0000000f -+#define RG_POS_DES_11GN_L_EXT_I_MSK 0xfffffff0 -+#define RG_POS_DES_11GN_L_EXT_SFT 0 -+#define RG_POS_DES_11GN_L_EXT_HI 3 -+#define RG_POS_DES_11GN_L_EXT_SZ 4 -+#define RG_PRE_DES_11GN_DLY_MSK 0x000000f0 -+#define RG_PRE_DES_11GN_DLY_I_MSK 0xffffff0f -+#define RG_PRE_DES_11GN_DLY_SFT 4 -+#define RG_PRE_DES_11GN_DLY_HI 7 -+#define RG_PRE_DES_11GN_DLY_SZ 4 -+#define RG_TR_LPF_KI_G_T1_MSK 0x0000000f -+#define RG_TR_LPF_KI_G_T1_I_MSK 0xfffffff0 -+#define RG_TR_LPF_KI_G_T1_SFT 0 -+#define RG_TR_LPF_KI_G_T1_HI 3 -+#define RG_TR_LPF_KI_G_T1_SZ 4 -+#define RG_TR_LPF_KP_G_T1_MSK 0x000000f0 -+#define RG_TR_LPF_KP_G_T1_I_MSK 0xffffff0f -+#define RG_TR_LPF_KP_G_T1_SFT 4 -+#define RG_TR_LPF_KP_G_T1_HI 7 -+#define RG_TR_LPF_KP_G_T1_SZ 4 -+#define RG_TR_CNT_T1_MSK 0x0000ff00 -+#define RG_TR_CNT_T1_I_MSK 0xffff00ff -+#define RG_TR_CNT_T1_SFT 8 -+#define RG_TR_CNT_T1_HI 15 -+#define RG_TR_CNT_T1_SZ 8 -+#define RG_TR_LPF_KI_G_T0_MSK 0x000f0000 -+#define RG_TR_LPF_KI_G_T0_I_MSK 0xfff0ffff -+#define RG_TR_LPF_KI_G_T0_SFT 16 -+#define RG_TR_LPF_KI_G_T0_HI 19 -+#define RG_TR_LPF_KI_G_T0_SZ 4 -+#define RG_TR_LPF_KP_G_T0_MSK 0x00f00000 -+#define RG_TR_LPF_KP_G_T0_I_MSK 0xff0fffff -+#define RG_TR_LPF_KP_G_T0_SFT 20 -+#define RG_TR_LPF_KP_G_T0_HI 23 -+#define RG_TR_LPF_KP_G_T0_SZ 4 -+#define RG_TR_CNT_T0_MSK 0xff000000 -+#define RG_TR_CNT_T0_I_MSK 0x00ffffff -+#define RG_TR_CNT_T0_SFT 24 -+#define RG_TR_CNT_T0_HI 31 -+#define RG_TR_CNT_T0_SZ 8 -+#define RG_TR_LPF_KI_G_T2_MSK 0x0000000f -+#define RG_TR_LPF_KI_G_T2_I_MSK 0xfffffff0 -+#define RG_TR_LPF_KI_G_T2_SFT 0 -+#define RG_TR_LPF_KI_G_T2_HI 3 -+#define RG_TR_LPF_KI_G_T2_SZ 4 -+#define RG_TR_LPF_KP_G_T2_MSK 0x000000f0 -+#define RG_TR_LPF_KP_G_T2_I_MSK 0xffffff0f -+#define RG_TR_LPF_KP_G_T2_SFT 4 -+#define RG_TR_LPF_KP_G_T2_HI 7 -+#define RG_TR_LPF_KP_G_T2_SZ 4 -+#define RG_TR_CNT_T2_MSK 0x0000ff00 -+#define RG_TR_CNT_T2_I_MSK 0xffff00ff -+#define RG_TR_CNT_T2_SFT 8 -+#define RG_TR_CNT_T2_HI 15 -+#define RG_TR_CNT_T2_SZ 8 -+#define RG_TR_LPF_KI_G_MSK 0x0000000f -+#define RG_TR_LPF_KI_G_I_MSK 0xfffffff0 -+#define RG_TR_LPF_KI_G_SFT 0 -+#define RG_TR_LPF_KI_G_HI 3 -+#define RG_TR_LPF_KI_G_SZ 4 -+#define RG_TR_LPF_KP_G_MSK 0x000000f0 -+#define RG_TR_LPF_KP_G_I_MSK 0xffffff0f -+#define RG_TR_LPF_KP_G_SFT 4 -+#define RG_TR_LPF_KP_G_HI 7 -+#define RG_TR_LPF_KP_G_SZ 4 -+#define RG_TR_LPF_RATE_G_MSK 0x3fffff00 -+#define RG_TR_LPF_RATE_G_I_MSK 0xc00000ff -+#define RG_TR_LPF_RATE_G_SFT 8 -+#define RG_TR_LPF_RATE_G_HI 29 -+#define RG_TR_LPF_RATE_G_SZ 22 -+#define RG_CR_LPF_KI_G_MSK 0x00000007 -+#define RG_CR_LPF_KI_G_I_MSK 0xfffffff8 -+#define RG_CR_LPF_KI_G_SFT 0 -+#define RG_CR_LPF_KI_G_HI 2 -+#define RG_CR_LPF_KI_G_SZ 3 -+#define RG_SYM_BOUND_CNT_MSK 0x00007f00 -+#define RG_SYM_BOUND_CNT_I_MSK 0xffff80ff -+#define RG_SYM_BOUND_CNT_SFT 8 -+#define RG_SYM_BOUND_CNT_HI 14 -+#define RG_SYM_BOUND_CNT_SZ 7 -+#define RG_XSCOR32_RATIO_MSK 0x007f0000 -+#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff -+#define RG_XSCOR32_RATIO_SFT 16 -+#define RG_XSCOR32_RATIO_HI 22 -+#define RG_XSCOR32_RATIO_SZ 7 -+#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000 -+#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff -+#define RG_ATCOR64_CNT_LMT_SFT 24 -+#define RG_ATCOR64_CNT_LMT_HI 30 -+#define RG_ATCOR64_CNT_LMT_SZ 7 -+#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00 -+#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff -+#define RG_ATCOR16_CNT_LMT2_SFT 8 -+#define RG_ATCOR16_CNT_LMT2_HI 14 -+#define RG_ATCOR16_CNT_LMT2_SZ 7 -+#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000 -+#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff -+#define RG_ATCOR16_CNT_LMT1_SFT 16 -+#define RG_ATCOR16_CNT_LMT1_HI 22 -+#define RG_ATCOR16_CNT_LMT1_SZ 7 -+#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000 -+#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff -+#define RG_ATCOR16_RATIO_SB_SFT 24 -+#define RG_ATCOR16_RATIO_SB_HI 30 -+#define RG_ATCOR16_RATIO_SB_SZ 7 -+#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000 -+#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff -+#define RG_XSCOR64_CNT_LMT2_SFT 16 -+#define RG_XSCOR64_CNT_LMT2_HI 22 -+#define RG_XSCOR64_CNT_LMT2_SZ 7 -+#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000 -+#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff -+#define RG_XSCOR64_CNT_LMT1_SFT 24 -+#define RG_XSCOR64_CNT_LMT1_HI 30 -+#define RG_XSCOR64_CNT_LMT1_SZ 7 -+#define RG_RX_FFT_SCALE_MSK 0x000003ff -+#define RG_RX_FFT_SCALE_I_MSK 0xfffffc00 -+#define RG_RX_FFT_SCALE_SFT 0 -+#define RG_RX_FFT_SCALE_HI 9 -+#define RG_RX_FFT_SCALE_SZ 10 -+#define RG_VITERBI_AB_SWAP_MSK 0x00010000 -+#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff -+#define RG_VITERBI_AB_SWAP_SFT 16 -+#define RG_VITERBI_AB_SWAP_HI 16 -+#define RG_VITERBI_AB_SWAP_SZ 1 -+#define RG_ATCOR16_CNT_TH_MSK 0x0f000000 -+#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff -+#define RG_ATCOR16_CNT_TH_SFT 24 -+#define RG_ATCOR16_CNT_TH_HI 27 -+#define RG_ATCOR16_CNT_TH_SZ 4 -+#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff -+#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00 -+#define RG_NORMSQUARE_LOW_SNR_7_SFT 0 -+#define RG_NORMSQUARE_LOW_SNR_7_HI 7 -+#define RG_NORMSQUARE_LOW_SNR_7_SZ 8 -+#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00 -+#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff -+#define RG_NORMSQUARE_LOW_SNR_6_SFT 8 -+#define RG_NORMSQUARE_LOW_SNR_6_HI 15 -+#define RG_NORMSQUARE_LOW_SNR_6_SZ 8 -+#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000 -+#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff -+#define RG_NORMSQUARE_LOW_SNR_5_SFT 16 -+#define RG_NORMSQUARE_LOW_SNR_5_HI 23 -+#define RG_NORMSQUARE_LOW_SNR_5_SZ 8 -+#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000 -+#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff -+#define RG_NORMSQUARE_LOW_SNR_4_SFT 24 -+#define RG_NORMSQUARE_LOW_SNR_4_HI 31 -+#define RG_NORMSQUARE_LOW_SNR_4_SZ 8 -+#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000 -+#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff -+#define RG_NORMSQUARE_LOW_SNR_8_SFT 24 -+#define RG_NORMSQUARE_LOW_SNR_8_HI 31 -+#define RG_NORMSQUARE_LOW_SNR_8_SZ 8 -+#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff -+#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00 -+#define RG_NORMSQUARE_SNR_3_SFT 0 -+#define RG_NORMSQUARE_SNR_3_HI 7 -+#define RG_NORMSQUARE_SNR_3_SZ 8 -+#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00 -+#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff -+#define RG_NORMSQUARE_SNR_2_SFT 8 -+#define RG_NORMSQUARE_SNR_2_HI 15 -+#define RG_NORMSQUARE_SNR_2_SZ 8 -+#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000 -+#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff -+#define RG_NORMSQUARE_SNR_1_SFT 16 -+#define RG_NORMSQUARE_SNR_1_HI 23 -+#define RG_NORMSQUARE_SNR_1_SZ 8 -+#define RG_NORMSQUARE_SNR_0_MSK 0xff000000 -+#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff -+#define RG_NORMSQUARE_SNR_0_SFT 24 -+#define RG_NORMSQUARE_SNR_0_HI 31 -+#define RG_NORMSQUARE_SNR_0_SZ 8 -+#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff -+#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00 -+#define RG_NORMSQUARE_SNR_7_SFT 0 -+#define RG_NORMSQUARE_SNR_7_HI 7 -+#define RG_NORMSQUARE_SNR_7_SZ 8 -+#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00 -+#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff -+#define RG_NORMSQUARE_SNR_6_SFT 8 -+#define RG_NORMSQUARE_SNR_6_HI 15 -+#define RG_NORMSQUARE_SNR_6_SZ 8 -+#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000 -+#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff -+#define RG_NORMSQUARE_SNR_5_SFT 16 -+#define RG_NORMSQUARE_SNR_5_HI 23 -+#define RG_NORMSQUARE_SNR_5_SZ 8 -+#define RG_NORMSQUARE_SNR_4_MSK 0xff000000 -+#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff -+#define RG_NORMSQUARE_SNR_4_SFT 24 -+#define RG_NORMSQUARE_SNR_4_HI 31 -+#define RG_NORMSQUARE_SNR_4_SZ 8 -+#define RG_NORMSQUARE_SNR_8_MSK 0xff000000 -+#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff -+#define RG_NORMSQUARE_SNR_8_SFT 24 -+#define RG_NORMSQUARE_SNR_8_HI 31 -+#define RG_NORMSQUARE_SNR_8_SZ 8 -+#define RG_SNR_TH_64QAM_MSK 0x0000007f -+#define RG_SNR_TH_64QAM_I_MSK 0xffffff80 -+#define RG_SNR_TH_64QAM_SFT 0 -+#define RG_SNR_TH_64QAM_HI 6 -+#define RG_SNR_TH_64QAM_SZ 7 -+#define RG_SNR_TH_16QAM_MSK 0x00007f00 -+#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff -+#define RG_SNR_TH_16QAM_SFT 8 -+#define RG_SNR_TH_16QAM_HI 14 -+#define RG_SNR_TH_16QAM_SZ 7 -+#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f -+#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80 -+#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0 -+#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6 -+#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7 -+#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00 -+#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff -+#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8 -+#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14 -+#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7 -+#define RG_SYM_BOUND_METHOD_MSK 0x00030000 -+#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff -+#define RG_SYM_BOUND_METHOD_SFT 16 -+#define RG_SYM_BOUND_METHOD_HI 17 -+#define RG_SYM_BOUND_METHOD_SZ 2 -+#define RG_PWRON_DLY_TH_11GN_MSK 0x000000ff -+#define RG_PWRON_DLY_TH_11GN_I_MSK 0xffffff00 -+#define RG_PWRON_DLY_TH_11GN_SFT 0 -+#define RG_PWRON_DLY_TH_11GN_HI 7 -+#define RG_PWRON_DLY_TH_11GN_SZ 8 -+#define RG_SB_START_CNT_MSK 0x00007f00 -+#define RG_SB_START_CNT_I_MSK 0xffff80ff -+#define RG_SB_START_CNT_SFT 8 -+#define RG_SB_START_CNT_HI 14 -+#define RG_SB_START_CNT_SZ 7 -+#define RG_POW16_CNT_TH_MSK 0x000000f0 -+#define RG_POW16_CNT_TH_I_MSK 0xffffff0f -+#define RG_POW16_CNT_TH_SFT 4 -+#define RG_POW16_CNT_TH_HI 7 -+#define RG_POW16_CNT_TH_SZ 4 -+#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700 -+#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff -+#define RG_POW16_SHORT_CNT_LMT_SFT 8 -+#define RG_POW16_SHORT_CNT_LMT_HI 10 -+#define RG_POW16_SHORT_CNT_LMT_SZ 3 -+#define RG_POW16_TH_L_MSK 0x7f000000 -+#define RG_POW16_TH_L_I_MSK 0x80ffffff -+#define RG_POW16_TH_L_SFT 24 -+#define RG_POW16_TH_L_HI 30 -+#define RG_POW16_TH_L_SZ 7 -+#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007 -+#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8 -+#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0 -+#define RG_XSCOR16_SHORT_CNT_LMT_HI 2 -+#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3 -+#define RG_XSCOR16_RATIO_MSK 0x00007f00 -+#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff -+#define RG_XSCOR16_RATIO_SFT 8 -+#define RG_XSCOR16_RATIO_HI 14 -+#define RG_XSCOR16_RATIO_SZ 7 -+#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000 -+#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff -+#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16 -+#define RG_ATCOR16_SHORT_CNT_LMT_HI 18 -+#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3 -+#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000 -+#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff -+#define RG_ATCOR16_RATIO_CCD_SFT 24 -+#define RG_ATCOR16_RATIO_CCD_HI 30 -+#define RG_ATCOR16_RATIO_CCD_SZ 7 -+#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f -+#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80 -+#define RG_ATCOR64_ACC_LMT_SFT 0 -+#define RG_ATCOR64_ACC_LMT_HI 6 -+#define RG_ATCOR64_ACC_LMT_SZ 7 -+#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000 -+#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff -+#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16 -+#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18 -+#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3 -+#define RG_VITERBI_TB_BITS_MSK 0xff000000 -+#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff -+#define RG_VITERBI_TB_BITS_SFT 24 -+#define RG_VITERBI_TB_BITS_HI 31 -+#define RG_VITERBI_TB_BITS_SZ 8 -+#define RG_CR_CNT_UPDATE_MSK 0x000000ff -+#define RG_CR_CNT_UPDATE_I_MSK 0xffffff00 -+#define RG_CR_CNT_UPDATE_SFT 0 -+#define RG_CR_CNT_UPDATE_HI 7 -+#define RG_CR_CNT_UPDATE_SZ 8 -+#define RG_TR_CNT_UPDATE_MSK 0x00ff0000 -+#define RG_TR_CNT_UPDATE_I_MSK 0xff00ffff -+#define RG_TR_CNT_UPDATE_SFT 16 -+#define RG_TR_CNT_UPDATE_HI 23 -+#define RG_TR_CNT_UPDATE_SZ 8 -+#define RG_BYPASS_CPE_MA_MSK 0x00000010 -+#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef -+#define RG_BYPASS_CPE_MA_SFT 4 -+#define RG_BYPASS_CPE_MA_HI 4 -+#define RG_BYPASS_CPE_MA_SZ 1 -+#define RG_PILOT_BNDRY_SHIFT_MSK 0x00000700 -+#define RG_PILOT_BNDRY_SHIFT_I_MSK 0xfffff8ff -+#define RG_PILOT_BNDRY_SHIFT_SFT 8 -+#define RG_PILOT_BNDRY_SHIFT_HI 10 -+#define RG_PILOT_BNDRY_SHIFT_SZ 3 -+#define RG_EQ_SHORT_GI_SHIFT_MSK 0x00007000 -+#define RG_EQ_SHORT_GI_SHIFT_I_MSK 0xffff8fff -+#define RG_EQ_SHORT_GI_SHIFT_SFT 12 -+#define RG_EQ_SHORT_GI_SHIFT_HI 14 -+#define RG_EQ_SHORT_GI_SHIFT_SZ 3 -+#define RG_FFT_WDW_SHORT_SHIFT_MSK 0x00070000 -+#define RG_FFT_WDW_SHORT_SHIFT_I_MSK 0xfff8ffff -+#define RG_FFT_WDW_SHORT_SHIFT_SFT 16 -+#define RG_FFT_WDW_SHORT_SHIFT_HI 18 -+#define RG_FFT_WDW_SHORT_SHIFT_SZ 3 -+#define RG_CHSMTH_COEF_MSK 0x00030000 -+#define RG_CHSMTH_COEF_I_MSK 0xfffcffff -+#define RG_CHSMTH_COEF_SFT 16 -+#define RG_CHSMTH_COEF_HI 17 -+#define RG_CHSMTH_COEF_SZ 2 -+#define RG_CHSMTH_EN_MSK 0x00040000 -+#define RG_CHSMTH_EN_I_MSK 0xfffbffff -+#define RG_CHSMTH_EN_SFT 18 -+#define RG_CHSMTH_EN_HI 18 -+#define RG_CHSMTH_EN_SZ 1 -+#define RG_CHEST_DD_FACTOR_MSK 0x07000000 -+#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff -+#define RG_CHEST_DD_FACTOR_SFT 24 -+#define RG_CHEST_DD_FACTOR_HI 26 -+#define RG_CHEST_DD_FACTOR_SZ 3 -+#define RG_CH_UPDATE_MSK 0x80000000 -+#define RG_CH_UPDATE_I_MSK 0x7fffffff -+#define RG_CH_UPDATE_SFT 31 -+#define RG_CH_UPDATE_HI 31 -+#define RG_CH_UPDATE_SZ 1 -+#define RG_FMT_DET_MM_TH_MSK 0x000000ff -+#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00 -+#define RG_FMT_DET_MM_TH_SFT 0 -+#define RG_FMT_DET_MM_TH_HI 7 -+#define RG_FMT_DET_MM_TH_SZ 8 -+#define RG_FMT_DET_GF_TH_MSK 0x0000ff00 -+#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff -+#define RG_FMT_DET_GF_TH_SFT 8 -+#define RG_FMT_DET_GF_TH_HI 15 -+#define RG_FMT_DET_GF_TH_SZ 8 -+#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000 -+#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff -+#define RG_DO_NOT_CHECK_L_RATE_SFT 25 -+#define RG_DO_NOT_CHECK_L_RATE_HI 25 -+#define RG_DO_NOT_CHECK_L_RATE_SZ 1 -+#define RG_FMT_DET_LENGTH_TH_MSK 0x0000ffff -+#define RG_FMT_DET_LENGTH_TH_I_MSK 0xffff0000 -+#define RG_FMT_DET_LENGTH_TH_SFT 0 -+#define RG_FMT_DET_LENGTH_TH_HI 15 -+#define RG_FMT_DET_LENGTH_TH_SZ 16 -+#define RG_L_LENGTH_MAX_MSK 0xffff0000 -+#define RG_L_LENGTH_MAX_I_MSK 0x0000ffff -+#define RG_L_LENGTH_MAX_SFT 16 -+#define RG_L_LENGTH_MAX_HI 31 -+#define RG_L_LENGTH_MAX_SZ 16 -+#define RG_TX_TIME_EXT_MSK 0x000000ff -+#define RG_TX_TIME_EXT_I_MSK 0xffffff00 -+#define RG_TX_TIME_EXT_SFT 0 -+#define RG_TX_TIME_EXT_HI 7 -+#define RG_TX_TIME_EXT_SZ 8 -+#define RG_MAC_DES_SPACE_MSK 0x00f00000 -+#define RG_MAC_DES_SPACE_I_MSK 0xff0fffff -+#define RG_MAC_DES_SPACE_SFT 20 -+#define RG_MAC_DES_SPACE_HI 23 -+#define RG_MAC_DES_SPACE_SZ 4 -+#define RG_TR_LPF_STBC_GF_KI_G_MSK 0x0000000f -+#define RG_TR_LPF_STBC_GF_KI_G_I_MSK 0xfffffff0 -+#define RG_TR_LPF_STBC_GF_KI_G_SFT 0 -+#define RG_TR_LPF_STBC_GF_KI_G_HI 3 -+#define RG_TR_LPF_STBC_GF_KI_G_SZ 4 -+#define RG_TR_LPF_STBC_GF_KP_G_MSK 0x000000f0 -+#define RG_TR_LPF_STBC_GF_KP_G_I_MSK 0xffffff0f -+#define RG_TR_LPF_STBC_GF_KP_G_SFT 4 -+#define RG_TR_LPF_STBC_GF_KP_G_HI 7 -+#define RG_TR_LPF_STBC_GF_KP_G_SZ 4 -+#define RG_TR_LPF_STBC_MF_KI_G_MSK 0x00000f00 -+#define RG_TR_LPF_STBC_MF_KI_G_I_MSK 0xfffff0ff -+#define RG_TR_LPF_STBC_MF_KI_G_SFT 8 -+#define RG_TR_LPF_STBC_MF_KI_G_HI 11 -+#define RG_TR_LPF_STBC_MF_KI_G_SZ 4 -+#define RG_TR_LPF_STBC_MF_KP_G_MSK 0x0000f000 -+#define RG_TR_LPF_STBC_MF_KP_G_I_MSK 0xffff0fff -+#define RG_TR_LPF_STBC_MF_KP_G_SFT 12 -+#define RG_TR_LPF_STBC_MF_KP_G_HI 15 -+#define RG_TR_LPF_STBC_MF_KP_G_SZ 4 -+#define RG_MODE_REG_IN_80_MSK 0x0001ffff -+#define RG_MODE_REG_IN_80_I_MSK 0xfffe0000 -+#define RG_MODE_REG_IN_80_SFT 0 -+#define RG_MODE_REG_IN_80_HI 16 -+#define RG_MODE_REG_IN_80_SZ 17 -+#define RG_PARALLEL_DR_80_MSK 0x00100000 -+#define RG_PARALLEL_DR_80_I_MSK 0xffefffff -+#define RG_PARALLEL_DR_80_SFT 20 -+#define RG_PARALLEL_DR_80_HI 20 -+#define RG_PARALLEL_DR_80_SZ 1 -+#define RG_MBRUN_80_MSK 0x01000000 -+#define RG_MBRUN_80_I_MSK 0xfeffffff -+#define RG_MBRUN_80_SFT 24 -+#define RG_MBRUN_80_HI 24 -+#define RG_MBRUN_80_SZ 1 -+#define RG_SHIFT_DR_80_MSK 0x10000000 -+#define RG_SHIFT_DR_80_I_MSK 0xefffffff -+#define RG_SHIFT_DR_80_SFT 28 -+#define RG_SHIFT_DR_80_HI 28 -+#define RG_SHIFT_DR_80_SZ 1 -+#define RG_MODE_REG_SI_80_MSK 0x20000000 -+#define RG_MODE_REG_SI_80_I_MSK 0xdfffffff -+#define RG_MODE_REG_SI_80_SFT 29 -+#define RG_MODE_REG_SI_80_HI 29 -+#define RG_MODE_REG_SI_80_SZ 1 -+#define RG_SIMULATION_MODE_80_MSK 0x40000000 -+#define RG_SIMULATION_MODE_80_I_MSK 0xbfffffff -+#define RG_SIMULATION_MODE_80_SFT 30 -+#define RG_SIMULATION_MODE_80_HI 30 -+#define RG_SIMULATION_MODE_80_SZ 1 -+#define RG_DBIST_MODE_80_MSK 0x80000000 -+#define RG_DBIST_MODE_80_I_MSK 0x7fffffff -+#define RG_DBIST_MODE_80_SFT 31 -+#define RG_DBIST_MODE_80_HI 31 -+#define RG_DBIST_MODE_80_SZ 1 -+#define RG_MODE_REG_IN_64_MSK 0x0000ffff -+#define RG_MODE_REG_IN_64_I_MSK 0xffff0000 -+#define RG_MODE_REG_IN_64_SFT 0 -+#define RG_MODE_REG_IN_64_HI 15 -+#define RG_MODE_REG_IN_64_SZ 16 -+#define RG_PARALLEL_DR_64_MSK 0x00100000 -+#define RG_PARALLEL_DR_64_I_MSK 0xffefffff -+#define RG_PARALLEL_DR_64_SFT 20 -+#define RG_PARALLEL_DR_64_HI 20 -+#define RG_PARALLEL_DR_64_SZ 1 -+#define RG_MBRUN_64_MSK 0x01000000 -+#define RG_MBRUN_64_I_MSK 0xfeffffff -+#define RG_MBRUN_64_SFT 24 -+#define RG_MBRUN_64_HI 24 -+#define RG_MBRUN_64_SZ 1 -+#define RG_SHIFT_DR_64_MSK 0x10000000 -+#define RG_SHIFT_DR_64_I_MSK 0xefffffff -+#define RG_SHIFT_DR_64_SFT 28 -+#define RG_SHIFT_DR_64_HI 28 -+#define RG_SHIFT_DR_64_SZ 1 -+#define RG_MODE_REG_SI_64_MSK 0x20000000 -+#define RG_MODE_REG_SI_64_I_MSK 0xdfffffff -+#define RG_MODE_REG_SI_64_SFT 29 -+#define RG_MODE_REG_SI_64_HI 29 -+#define RG_MODE_REG_SI_64_SZ 1 -+#define RG_SIMULATION_MODE_64_MSK 0x40000000 -+#define RG_SIMULATION_MODE_64_I_MSK 0xbfffffff -+#define RG_SIMULATION_MODE_64_SFT 30 -+#define RG_SIMULATION_MODE_64_HI 30 -+#define RG_SIMULATION_MODE_64_SZ 1 -+#define RG_DBIST_MODE_64_MSK 0x80000000 -+#define RG_DBIST_MODE_64_I_MSK 0x7fffffff -+#define RG_DBIST_MODE_64_SFT 31 -+#define RG_DBIST_MODE_64_HI 31 -+#define RG_DBIST_MODE_64_SZ 1 -+#define RO_MODE_REG_OUT_80_MSK 0x0001ffff -+#define RO_MODE_REG_OUT_80_I_MSK 0xfffe0000 -+#define RO_MODE_REG_OUT_80_SFT 0 -+#define RO_MODE_REG_OUT_80_HI 16 -+#define RO_MODE_REG_OUT_80_SZ 17 -+#define RO_MODE_REG_SO_80_MSK 0x01000000 -+#define RO_MODE_REG_SO_80_I_MSK 0xfeffffff -+#define RO_MODE_REG_SO_80_SFT 24 -+#define RO_MODE_REG_SO_80_HI 24 -+#define RO_MODE_REG_SO_80_SZ 1 -+#define RO_MONITOR_BUS_80_MSK 0x003fffff -+#define RO_MONITOR_BUS_80_I_MSK 0xffc00000 -+#define RO_MONITOR_BUS_80_SFT 0 -+#define RO_MONITOR_BUS_80_HI 21 -+#define RO_MONITOR_BUS_80_SZ 22 -+#define RO_MODE_REG_OUT_64_MSK 0x0000ffff -+#define RO_MODE_REG_OUT_64_I_MSK 0xffff0000 -+#define RO_MODE_REG_OUT_64_SFT 0 -+#define RO_MODE_REG_OUT_64_HI 15 -+#define RO_MODE_REG_OUT_64_SZ 16 -+#define RO_MODE_REG_SO_64_MSK 0x01000000 -+#define RO_MODE_REG_SO_64_I_MSK 0xfeffffff -+#define RO_MODE_REG_SO_64_SFT 24 -+#define RO_MODE_REG_SO_64_HI 24 -+#define RO_MODE_REG_SO_64_SZ 1 -+#define RO_MONITOR_BUS_64_MSK 0x0007ffff -+#define RO_MONITOR_BUS_64_I_MSK 0xfff80000 -+#define RO_MONITOR_BUS_64_SFT 0 -+#define RO_MONITOR_BUS_64_HI 18 -+#define RO_MONITOR_BUS_64_SZ 19 -+#define RO_SPECTRUM_DATA_MSK 0xffffffff -+#define RO_SPECTRUM_DATA_I_MSK 0x00000000 -+#define RO_SPECTRUM_DATA_SFT 0 -+#define RO_SPECTRUM_DATA_HI 31 -+#define RO_SPECTRUM_DATA_SZ 32 -+#define GN_SNR_MSK 0x0000007f -+#define GN_SNR_I_MSK 0xffffff80 -+#define GN_SNR_SFT 0 -+#define GN_SNR_HI 6 -+#define GN_SNR_SZ 7 -+#define GN_NOISE_PWR_MSK 0x00007f00 -+#define GN_NOISE_PWR_I_MSK 0xffff80ff -+#define GN_NOISE_PWR_SFT 8 -+#define GN_NOISE_PWR_HI 14 -+#define GN_NOISE_PWR_SZ 7 -+#define GN_RCPI_MSK 0x007f0000 -+#define GN_RCPI_I_MSK 0xff80ffff -+#define GN_RCPI_SFT 16 -+#define GN_RCPI_HI 22 -+#define GN_RCPI_SZ 7 -+#define GN_SIGNAL_PWR_MSK 0x7f000000 -+#define GN_SIGNAL_PWR_I_MSK 0x80ffffff -+#define GN_SIGNAL_PWR_SFT 24 -+#define GN_SIGNAL_PWR_HI 30 -+#define GN_SIGNAL_PWR_SZ 7 -+#define RO_FREQ_OS_LTS_MSK 0x00007fff -+#define RO_FREQ_OS_LTS_I_MSK 0xffff8000 -+#define RO_FREQ_OS_LTS_SFT 0 -+#define RO_FREQ_OS_LTS_HI 14 -+#define RO_FREQ_OS_LTS_SZ 15 -+#define CSTATE_MSK 0x000f0000 -+#define CSTATE_I_MSK 0xfff0ffff -+#define CSTATE_SFT 16 -+#define CSTATE_HI 19 -+#define CSTATE_SZ 4 -+#define SIGNAL_FIELD0_MSK 0x00ffffff -+#define SIGNAL_FIELD0_I_MSK 0xff000000 -+#define SIGNAL_FIELD0_SFT 0 -+#define SIGNAL_FIELD0_HI 23 -+#define SIGNAL_FIELD0_SZ 24 -+#define SIGNAL_FIELD1_MSK 0x00ffffff -+#define SIGNAL_FIELD1_I_MSK 0xff000000 -+#define SIGNAL_FIELD1_SFT 0 -+#define SIGNAL_FIELD1_HI 23 -+#define SIGNAL_FIELD1_SZ 24 -+#define GN_PACKET_ERR_CNT_MSK 0x0000ffff -+#define GN_PACKET_ERR_CNT_I_MSK 0xffff0000 -+#define GN_PACKET_ERR_CNT_SFT 0 -+#define GN_PACKET_ERR_CNT_HI 15 -+#define GN_PACKET_ERR_CNT_SZ 16 -+#define GN_PACKET_CNT_MSK 0x0000ffff -+#define GN_PACKET_CNT_I_MSK 0xffff0000 -+#define GN_PACKET_CNT_SFT 0 -+#define GN_PACKET_CNT_HI 15 -+#define GN_PACKET_CNT_SZ 16 -+#define GN_CCA_CNT_MSK 0xffff0000 -+#define GN_CCA_CNT_I_MSK 0x0000ffff -+#define GN_CCA_CNT_SFT 16 -+#define GN_CCA_CNT_HI 31 -+#define GN_CCA_CNT_SZ 16 -+#define GN_LENGTH_FIELD_MSK 0x0000ffff -+#define GN_LENGTH_FIELD_I_MSK 0xffff0000 -+#define GN_LENGTH_FIELD_SFT 0 -+#define GN_LENGTH_FIELD_HI 15 -+#define GN_LENGTH_FIELD_SZ 16 -+#define GN_SERVICE_FIELD_MSK 0xffff0000 -+#define GN_SERVICE_FIELD_I_MSK 0x0000ffff -+#define GN_SERVICE_FIELD_SFT 16 -+#define GN_SERVICE_FIELD_HI 31 -+#define GN_SERVICE_FIELD_SZ 16 -+#define RO_HT_MCS_40M_MSK 0x0000007f -+#define RO_HT_MCS_40M_I_MSK 0xffffff80 -+#define RO_HT_MCS_40M_SFT 0 -+#define RO_HT_MCS_40M_HI 6 -+#define RO_HT_MCS_40M_SZ 7 -+#define RO_L_RATE_40M_MSK 0x00003f00 -+#define RO_L_RATE_40M_I_MSK 0xffffc0ff -+#define RO_L_RATE_40M_SFT 8 -+#define RO_L_RATE_40M_HI 13 -+#define RO_L_RATE_40M_SZ 6 -+#define RG_DAGC_CNT_TH_MSK 0x00000003 -+#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc -+#define RG_DAGC_CNT_TH_SFT 0 -+#define RG_DAGC_CNT_TH_HI 1 -+#define RG_DAGC_CNT_TH_SZ 2 -+#define RG_PACKET_STAT_EN_11GN_MSK 0x00100000 -+#define RG_PACKET_STAT_EN_11GN_I_MSK 0xffefffff -+#define RG_PACKET_STAT_EN_11GN_SFT 20 -+#define RG_PACKET_STAT_EN_11GN_HI 20 -+#define RG_PACKET_STAT_EN_11GN_SZ 1 -+#define RX_PHY_11GN_SOFT_RST_N_MSK 0x00000001 -+#define RX_PHY_11GN_SOFT_RST_N_I_MSK 0xfffffffe -+#define RX_PHY_11GN_SOFT_RST_N_SFT 0 -+#define RX_PHY_11GN_SOFT_RST_N_HI 0 -+#define RX_PHY_11GN_SOFT_RST_N_SZ 1 -+#define RG_RIFS_EN_MSK 0x00000002 -+#define RG_RIFS_EN_I_MSK 0xfffffffd -+#define RG_RIFS_EN_SFT 1 -+#define RG_RIFS_EN_HI 1 -+#define RG_RIFS_EN_SZ 1 -+#define RG_STBC_EN_MSK 0x00000004 -+#define RG_STBC_EN_I_MSK 0xfffffffb -+#define RG_STBC_EN_SFT 2 -+#define RG_STBC_EN_HI 2 -+#define RG_STBC_EN_SZ 1 -+#define RG_COR_SEL_MSK 0x00000008 -+#define RG_COR_SEL_I_MSK 0xfffffff7 -+#define RG_COR_SEL_SFT 3 -+#define RG_COR_SEL_HI 3 -+#define RG_COR_SEL_SZ 1 -+#define RG_INI_PHASE_MSK 0x00000030 -+#define RG_INI_PHASE_I_MSK 0xffffffcf -+#define RG_INI_PHASE_SFT 4 -+#define RG_INI_PHASE_HI 5 -+#define RG_INI_PHASE_SZ 2 -+#define RG_HT_LTF_SEL_EQ_MSK 0x00000040 -+#define RG_HT_LTF_SEL_EQ_I_MSK 0xffffffbf -+#define RG_HT_LTF_SEL_EQ_SFT 6 -+#define RG_HT_LTF_SEL_EQ_HI 6 -+#define RG_HT_LTF_SEL_EQ_SZ 1 -+#define RG_HT_LTF_SEL_PILOT_MSK 0x00000080 -+#define RG_HT_LTF_SEL_PILOT_I_MSK 0xffffff7f -+#define RG_HT_LTF_SEL_PILOT_SFT 7 -+#define RG_HT_LTF_SEL_PILOT_HI 7 -+#define RG_HT_LTF_SEL_PILOT_SZ 1 -+#define RG_CCA_PWR_SEL_MSK 0x00000200 -+#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff -+#define RG_CCA_PWR_SEL_SFT 9 -+#define RG_CCA_PWR_SEL_HI 9 -+#define RG_CCA_PWR_SEL_SZ 1 -+#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400 -+#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff -+#define RG_CCA_XSCOR_PWR_SEL_SFT 10 -+#define RG_CCA_XSCOR_PWR_SEL_HI 10 -+#define RG_CCA_XSCOR_PWR_SEL_SZ 1 -+#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800 -+#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff -+#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11 -+#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11 -+#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1 -+#define RG_DEBUG_SEL_MSK 0x0000f000 -+#define RG_DEBUG_SEL_I_MSK 0xffff0fff -+#define RG_DEBUG_SEL_SFT 12 -+#define RG_DEBUG_SEL_HI 15 -+#define RG_DEBUG_SEL_SZ 4 -+#define RG_POST_CLK_EN_MSK 0x00010000 -+#define RG_POST_CLK_EN_I_MSK 0xfffeffff -+#define RG_POST_CLK_EN_SFT 16 -+#define RG_POST_CLK_EN_HI 16 -+#define RG_POST_CLK_EN_SZ 1 -+#define IQCAL_RF_TX_EN_MSK 0x00000001 -+#define IQCAL_RF_TX_EN_I_MSK 0xfffffffe -+#define IQCAL_RF_TX_EN_SFT 0 -+#define IQCAL_RF_TX_EN_HI 0 -+#define IQCAL_RF_TX_EN_SZ 1 -+#define IQCAL_RF_TX_PA_EN_MSK 0x00000002 -+#define IQCAL_RF_TX_PA_EN_I_MSK 0xfffffffd -+#define IQCAL_RF_TX_PA_EN_SFT 1 -+#define IQCAL_RF_TX_PA_EN_HI 1 -+#define IQCAL_RF_TX_PA_EN_SZ 1 -+#define IQCAL_RF_TX_DAC_EN_MSK 0x00000004 -+#define IQCAL_RF_TX_DAC_EN_I_MSK 0xfffffffb -+#define IQCAL_RF_TX_DAC_EN_SFT 2 -+#define IQCAL_RF_TX_DAC_EN_HI 2 -+#define IQCAL_RF_TX_DAC_EN_SZ 1 -+#define IQCAL_RF_RX_AGC_MSK 0x00000008 -+#define IQCAL_RF_RX_AGC_I_MSK 0xfffffff7 -+#define IQCAL_RF_RX_AGC_SFT 3 -+#define IQCAL_RF_RX_AGC_HI 3 -+#define IQCAL_RF_RX_AGC_SZ 1 -+#define IQCAL_RF_PGAG_MSK 0x00000f00 -+#define IQCAL_RF_PGAG_I_MSK 0xfffff0ff -+#define IQCAL_RF_PGAG_SFT 8 -+#define IQCAL_RF_PGAG_HI 11 -+#define IQCAL_RF_PGAG_SZ 4 -+#define IQCAL_RF_RFG_MSK 0x00003000 -+#define IQCAL_RF_RFG_I_MSK 0xffffcfff -+#define IQCAL_RF_RFG_SFT 12 -+#define IQCAL_RF_RFG_HI 13 -+#define IQCAL_RF_RFG_SZ 2 -+#define RG_TONEGEN_FREQ_MSK 0x007f0000 -+#define RG_TONEGEN_FREQ_I_MSK 0xff80ffff -+#define RG_TONEGEN_FREQ_SFT 16 -+#define RG_TONEGEN_FREQ_HI 22 -+#define RG_TONEGEN_FREQ_SZ 7 -+#define RG_TONEGEN_EN_MSK 0x00800000 -+#define RG_TONEGEN_EN_I_MSK 0xff7fffff -+#define RG_TONEGEN_EN_SFT 23 -+#define RG_TONEGEN_EN_HI 23 -+#define RG_TONEGEN_EN_SZ 1 -+#define RG_TONEGEN_INIT_PH_MSK 0x7f000000 -+#define RG_TONEGEN_INIT_PH_I_MSK 0x80ffffff -+#define RG_TONEGEN_INIT_PH_SFT 24 -+#define RG_TONEGEN_INIT_PH_HI 30 -+#define RG_TONEGEN_INIT_PH_SZ 7 -+#define RG_TONEGEN2_FREQ_MSK 0x0000007f -+#define RG_TONEGEN2_FREQ_I_MSK 0xffffff80 -+#define RG_TONEGEN2_FREQ_SFT 0 -+#define RG_TONEGEN2_FREQ_HI 6 -+#define RG_TONEGEN2_FREQ_SZ 7 -+#define RG_TONEGEN2_EN_MSK 0x00000080 -+#define RG_TONEGEN2_EN_I_MSK 0xffffff7f -+#define RG_TONEGEN2_EN_SFT 7 -+#define RG_TONEGEN2_EN_HI 7 -+#define RG_TONEGEN2_EN_SZ 1 -+#define RG_TONEGEN2_SCALE_MSK 0x0000ff00 -+#define RG_TONEGEN2_SCALE_I_MSK 0xffff00ff -+#define RG_TONEGEN2_SCALE_SFT 8 -+#define RG_TONEGEN2_SCALE_HI 15 -+#define RG_TONEGEN2_SCALE_SZ 8 -+#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff -+#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00 -+#define RG_TXIQ_CLP_THD_I_SFT 0 -+#define RG_TXIQ_CLP_THD_I_HI 9 -+#define RG_TXIQ_CLP_THD_I_SZ 10 -+#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000 -+#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff -+#define RG_TXIQ_CLP_THD_Q_SFT 16 -+#define RG_TXIQ_CLP_THD_Q_HI 25 -+#define RG_TXIQ_CLP_THD_Q_SZ 10 -+#define RG_TX_I_SCALE_MSK 0x000000ff -+#define RG_TX_I_SCALE_I_MSK 0xffffff00 -+#define RG_TX_I_SCALE_SFT 0 -+#define RG_TX_I_SCALE_HI 7 -+#define RG_TX_I_SCALE_SZ 8 -+#define RG_TX_Q_SCALE_MSK 0x0000ff00 -+#define RG_TX_Q_SCALE_I_MSK 0xffff00ff -+#define RG_TX_Q_SCALE_SFT 8 -+#define RG_TX_Q_SCALE_HI 15 -+#define RG_TX_Q_SCALE_SZ 8 -+#define RG_TX_IQ_SWP_MSK 0x00010000 -+#define RG_TX_IQ_SWP_I_MSK 0xfffeffff -+#define RG_TX_IQ_SWP_SFT 16 -+#define RG_TX_IQ_SWP_HI 16 -+#define RG_TX_IQ_SWP_SZ 1 -+#define RG_TX_SGN_OUT_MSK 0x00020000 -+#define RG_TX_SGN_OUT_I_MSK 0xfffdffff -+#define RG_TX_SGN_OUT_SFT 17 -+#define RG_TX_SGN_OUT_HI 17 -+#define RG_TX_SGN_OUT_SZ 1 -+#define RG_TXIQ_EMU_IDX_MSK 0x003c0000 -+#define RG_TXIQ_EMU_IDX_I_MSK 0xffc3ffff -+#define RG_TXIQ_EMU_IDX_SFT 18 -+#define RG_TXIQ_EMU_IDX_HI 21 -+#define RG_TXIQ_EMU_IDX_SZ 4 -+#define RG_TX_IQ_SRC_MSK 0x03000000 -+#define RG_TX_IQ_SRC_I_MSK 0xfcffffff -+#define RG_TX_IQ_SRC_SFT 24 -+#define RG_TX_IQ_SRC_HI 25 -+#define RG_TX_IQ_SRC_SZ 2 -+#define RG_TX_I_DC_MSK 0x000003ff -+#define RG_TX_I_DC_I_MSK 0xfffffc00 -+#define RG_TX_I_DC_SFT 0 -+#define RG_TX_I_DC_HI 9 -+#define RG_TX_I_DC_SZ 10 -+#define RG_TX_Q_DC_MSK 0x03ff0000 -+#define RG_TX_Q_DC_I_MSK 0xfc00ffff -+#define RG_TX_Q_DC_SFT 16 -+#define RG_TX_Q_DC_HI 25 -+#define RG_TX_Q_DC_SZ 10 -+#define RG_TX_IQ_THETA_MSK 0x0000001f -+#define RG_TX_IQ_THETA_I_MSK 0xffffffe0 -+#define RG_TX_IQ_THETA_SFT 0 -+#define RG_TX_IQ_THETA_HI 4 -+#define RG_TX_IQ_THETA_SZ 5 -+#define RG_TX_IQ_ALPHA_MSK 0x00001f00 -+#define RG_TX_IQ_ALPHA_I_MSK 0xffffe0ff -+#define RG_TX_IQ_ALPHA_SFT 8 -+#define RG_TX_IQ_ALPHA_HI 12 -+#define RG_TX_IQ_ALPHA_SZ 5 -+#define RG_TXIQ_NOSHRINK_MSK 0x00002000 -+#define RG_TXIQ_NOSHRINK_I_MSK 0xffffdfff -+#define RG_TXIQ_NOSHRINK_SFT 13 -+#define RG_TXIQ_NOSHRINK_HI 13 -+#define RG_TXIQ_NOSHRINK_SZ 1 -+#define RG_TX_I_OFFSET_MSK 0x00ff0000 -+#define RG_TX_I_OFFSET_I_MSK 0xff00ffff -+#define RG_TX_I_OFFSET_SFT 16 -+#define RG_TX_I_OFFSET_HI 23 -+#define RG_TX_I_OFFSET_SZ 8 -+#define RG_TX_Q_OFFSET_MSK 0xff000000 -+#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff -+#define RG_TX_Q_OFFSET_SFT 24 -+#define RG_TX_Q_OFFSET_HI 31 -+#define RG_TX_Q_OFFSET_SZ 8 -+#define RG_RX_IQ_THETA_MSK 0x0000001f -+#define RG_RX_IQ_THETA_I_MSK 0xffffffe0 -+#define RG_RX_IQ_THETA_SFT 0 -+#define RG_RX_IQ_THETA_HI 4 -+#define RG_RX_IQ_THETA_SZ 5 -+#define RG_RX_IQ_ALPHA_MSK 0x00001f00 -+#define RG_RX_IQ_ALPHA_I_MSK 0xffffe0ff -+#define RG_RX_IQ_ALPHA_SFT 8 -+#define RG_RX_IQ_ALPHA_HI 12 -+#define RG_RX_IQ_ALPHA_SZ 5 -+#define RG_RXIQ_NOSHRINK_MSK 0x00002000 -+#define RG_RXIQ_NOSHRINK_I_MSK 0xffffdfff -+#define RG_RXIQ_NOSHRINK_SFT 13 -+#define RG_RXIQ_NOSHRINK_HI 13 -+#define RG_RXIQ_NOSHRINK_SZ 1 -+#define RG_MA_DPTH_MSK 0x0000000f -+#define RG_MA_DPTH_I_MSK 0xfffffff0 -+#define RG_MA_DPTH_SFT 0 -+#define RG_MA_DPTH_HI 3 -+#define RG_MA_DPTH_SZ 4 -+#define RG_INTG_PH_MSK 0x000003f0 -+#define RG_INTG_PH_I_MSK 0xfffffc0f -+#define RG_INTG_PH_SFT 4 -+#define RG_INTG_PH_HI 9 -+#define RG_INTG_PH_SZ 6 -+#define RG_INTG_PRD_MSK 0x00001c00 -+#define RG_INTG_PRD_I_MSK 0xffffe3ff -+#define RG_INTG_PRD_SFT 10 -+#define RG_INTG_PRD_HI 12 -+#define RG_INTG_PRD_SZ 3 -+#define RG_INTG_MU_MSK 0x00006000 -+#define RG_INTG_MU_I_MSK 0xffff9fff -+#define RG_INTG_MU_SFT 13 -+#define RG_INTG_MU_HI 14 -+#define RG_INTG_MU_SZ 2 -+#define RG_IQCAL_SPRM_SELQ_MSK 0x00010000 -+#define RG_IQCAL_SPRM_SELQ_I_MSK 0xfffeffff -+#define RG_IQCAL_SPRM_SELQ_SFT 16 -+#define RG_IQCAL_SPRM_SELQ_HI 16 -+#define RG_IQCAL_SPRM_SELQ_SZ 1 -+#define RG_IQCAL_SPRM_EN_MSK 0x00020000 -+#define RG_IQCAL_SPRM_EN_I_MSK 0xfffdffff -+#define RG_IQCAL_SPRM_EN_SFT 17 -+#define RG_IQCAL_SPRM_EN_HI 17 -+#define RG_IQCAL_SPRM_EN_SZ 1 -+#define RG_IQCAL_SPRM_FREQ_MSK 0x00fc0000 -+#define RG_IQCAL_SPRM_FREQ_I_MSK 0xff03ffff -+#define RG_IQCAL_SPRM_FREQ_SFT 18 -+#define RG_IQCAL_SPRM_FREQ_HI 23 -+#define RG_IQCAL_SPRM_FREQ_SZ 6 -+#define RG_IQCAL_IQCOL_EN_MSK 0x01000000 -+#define RG_IQCAL_IQCOL_EN_I_MSK 0xfeffffff -+#define RG_IQCAL_IQCOL_EN_SFT 24 -+#define RG_IQCAL_IQCOL_EN_HI 24 -+#define RG_IQCAL_IQCOL_EN_SZ 1 -+#define RG_IQCAL_ALPHA_ESTM_EN_MSK 0x02000000 -+#define RG_IQCAL_ALPHA_ESTM_EN_I_MSK 0xfdffffff -+#define RG_IQCAL_ALPHA_ESTM_EN_SFT 25 -+#define RG_IQCAL_ALPHA_ESTM_EN_HI 25 -+#define RG_IQCAL_ALPHA_ESTM_EN_SZ 1 -+#define RG_IQCAL_DC_EN_MSK 0x04000000 -+#define RG_IQCAL_DC_EN_I_MSK 0xfbffffff -+#define RG_IQCAL_DC_EN_SFT 26 -+#define RG_IQCAL_DC_EN_HI 26 -+#define RG_IQCAL_DC_EN_SZ 1 -+#define RG_PHEST_STBY_MSK 0x08000000 -+#define RG_PHEST_STBY_I_MSK 0xf7ffffff -+#define RG_PHEST_STBY_SFT 27 -+#define RG_PHEST_STBY_HI 27 -+#define RG_PHEST_STBY_SZ 1 -+#define RG_PHEST_EN_MSK 0x10000000 -+#define RG_PHEST_EN_I_MSK 0xefffffff -+#define RG_PHEST_EN_SFT 28 -+#define RG_PHEST_EN_HI 28 -+#define RG_PHEST_EN_SZ 1 -+#define RG_GP_DIV_EN_MSK 0x20000000 -+#define RG_GP_DIV_EN_I_MSK 0xdfffffff -+#define RG_GP_DIV_EN_SFT 29 -+#define RG_GP_DIV_EN_HI 29 -+#define RG_GP_DIV_EN_SZ 1 -+#define RG_DPD_GAIN_EST_EN_MSK 0x40000000 -+#define RG_DPD_GAIN_EST_EN_I_MSK 0xbfffffff -+#define RG_DPD_GAIN_EST_EN_SFT 30 -+#define RG_DPD_GAIN_EST_EN_HI 30 -+#define RG_DPD_GAIN_EST_EN_SZ 1 -+#define RG_IQCAL_MULT_OP0_MSK 0x000003ff -+#define RG_IQCAL_MULT_OP0_I_MSK 0xfffffc00 -+#define RG_IQCAL_MULT_OP0_SFT 0 -+#define RG_IQCAL_MULT_OP0_HI 9 -+#define RG_IQCAL_MULT_OP0_SZ 10 -+#define RG_IQCAL_MULT_OP1_MSK 0x03ff0000 -+#define RG_IQCAL_MULT_OP1_I_MSK 0xfc00ffff -+#define RG_IQCAL_MULT_OP1_SFT 16 -+#define RG_IQCAL_MULT_OP1_HI 25 -+#define RG_IQCAL_MULT_OP1_SZ 10 -+#define RO_IQCAL_O_MSK 0x000fffff -+#define RO_IQCAL_O_I_MSK 0xfff00000 -+#define RO_IQCAL_O_SFT 0 -+#define RO_IQCAL_O_HI 19 -+#define RO_IQCAL_O_SZ 20 -+#define RO_IQCAL_SPRM_RDY_MSK 0x00100000 -+#define RO_IQCAL_SPRM_RDY_I_MSK 0xffefffff -+#define RO_IQCAL_SPRM_RDY_SFT 20 -+#define RO_IQCAL_SPRM_RDY_HI 20 -+#define RO_IQCAL_SPRM_RDY_SZ 1 -+#define RO_IQCAL_IQCOL_RDY_MSK 0x00200000 -+#define RO_IQCAL_IQCOL_RDY_I_MSK 0xffdfffff -+#define RO_IQCAL_IQCOL_RDY_SFT 21 -+#define RO_IQCAL_IQCOL_RDY_HI 21 -+#define RO_IQCAL_IQCOL_RDY_SZ 1 -+#define RO_IQCAL_ALPHA_ESTM_RDY_MSK 0x00400000 -+#define RO_IQCAL_ALPHA_ESTM_RDY_I_MSK 0xffbfffff -+#define RO_IQCAL_ALPHA_ESTM_RDY_SFT 22 -+#define RO_IQCAL_ALPHA_ESTM_RDY_HI 22 -+#define RO_IQCAL_ALPHA_ESTM_RDY_SZ 1 -+#define RO_IQCAL_DC_RDY_MSK 0x00800000 -+#define RO_IQCAL_DC_RDY_I_MSK 0xff7fffff -+#define RO_IQCAL_DC_RDY_SFT 23 -+#define RO_IQCAL_DC_RDY_HI 23 -+#define RO_IQCAL_DC_RDY_SZ 1 -+#define RO_IQCAL_MULT_RDY_MSK 0x01000000 -+#define RO_IQCAL_MULT_RDY_I_MSK 0xfeffffff -+#define RO_IQCAL_MULT_RDY_SFT 24 -+#define RO_IQCAL_MULT_RDY_HI 24 -+#define RO_IQCAL_MULT_RDY_SZ 1 -+#define RO_FFT_ENRG_RDY_MSK 0x02000000 -+#define RO_FFT_ENRG_RDY_I_MSK 0xfdffffff -+#define RO_FFT_ENRG_RDY_SFT 25 -+#define RO_FFT_ENRG_RDY_HI 25 -+#define RO_FFT_ENRG_RDY_SZ 1 -+#define RO_PHEST_RDY_MSK 0x04000000 -+#define RO_PHEST_RDY_I_MSK 0xfbffffff -+#define RO_PHEST_RDY_SFT 26 -+#define RO_PHEST_RDY_HI 26 -+#define RO_PHEST_RDY_SZ 1 -+#define RO_GP_DIV_RDY_MSK 0x08000000 -+#define RO_GP_DIV_RDY_I_MSK 0xf7ffffff -+#define RO_GP_DIV_RDY_SFT 27 -+#define RO_GP_DIV_RDY_HI 27 -+#define RO_GP_DIV_RDY_SZ 1 -+#define RO_GAIN_EST_RDY_MSK 0x10000000 -+#define RO_GAIN_EST_RDY_I_MSK 0xefffffff -+#define RO_GAIN_EST_RDY_SFT 28 -+#define RO_GAIN_EST_RDY_HI 28 -+#define RO_GAIN_EST_RDY_SZ 1 -+#define RO_AMP_O_MSK 0x000001ff -+#define RO_AMP_O_I_MSK 0xfffffe00 -+#define RO_AMP_O_SFT 0 -+#define RO_AMP_O_HI 8 -+#define RO_AMP_O_SZ 9 -+#define RG_RX_I_SCALE_MSK 0x000000ff -+#define RG_RX_I_SCALE_I_MSK 0xffffff00 -+#define RG_RX_I_SCALE_SFT 0 -+#define RG_RX_I_SCALE_HI 7 -+#define RG_RX_I_SCALE_SZ 8 -+#define RG_RX_Q_SCALE_MSK 0x0000ff00 -+#define RG_RX_Q_SCALE_I_MSK 0xffff00ff -+#define RG_RX_Q_SCALE_SFT 8 -+#define RG_RX_Q_SCALE_HI 15 -+#define RG_RX_Q_SCALE_SZ 8 -+#define RG_RX_I_OFFSET_MSK 0x00ff0000 -+#define RG_RX_I_OFFSET_I_MSK 0xff00ffff -+#define RG_RX_I_OFFSET_SFT 16 -+#define RG_RX_I_OFFSET_HI 23 -+#define RG_RX_I_OFFSET_SZ 8 -+#define RG_RX_Q_OFFSET_MSK 0xff000000 -+#define RG_RX_Q_OFFSET_I_MSK 0x00ffffff -+#define RG_RX_Q_OFFSET_SFT 24 -+#define RG_RX_Q_OFFSET_HI 31 -+#define RG_RX_Q_OFFSET_SZ 8 -+#define RG_RX_IQ_SWP_MSK 0x00000001 -+#define RG_RX_IQ_SWP_I_MSK 0xfffffffe -+#define RG_RX_IQ_SWP_SFT 0 -+#define RG_RX_IQ_SWP_HI 0 -+#define RG_RX_IQ_SWP_SZ 1 -+#define RG_RX_SGN_IN_MSK 0x00000002 -+#define RG_RX_SGN_IN_I_MSK 0xfffffffd -+#define RG_RX_SGN_IN_SFT 1 -+#define RG_RX_SGN_IN_HI 1 -+#define RG_RX_SGN_IN_SZ 1 -+#define RG_RX_IQ_SRC_MSK 0x0000000c -+#define RG_RX_IQ_SRC_I_MSK 0xfffffff3 -+#define RG_RX_IQ_SRC_SFT 2 -+#define RG_RX_IQ_SRC_HI 3 -+#define RG_RX_IQ_SRC_SZ 2 -+#define RG_ACI_GAIN_MSK 0x00000ff0 -+#define RG_ACI_GAIN_I_MSK 0xfffff00f -+#define RG_ACI_GAIN_SFT 4 -+#define RG_ACI_GAIN_HI 11 -+#define RG_ACI_GAIN_SZ 8 -+#define RG_FFT_EN_MSK 0x00001000 -+#define RG_FFT_EN_I_MSK 0xffffefff -+#define RG_FFT_EN_SFT 12 -+#define RG_FFT_EN_HI 12 -+#define RG_FFT_EN_SZ 1 -+#define RG_FFT_MOD_MSK 0x00002000 -+#define RG_FFT_MOD_I_MSK 0xffffdfff -+#define RG_FFT_MOD_SFT 13 -+#define RG_FFT_MOD_HI 13 -+#define RG_FFT_MOD_SZ 1 -+#define RG_FFT_SCALE_MSK 0x00ffc000 -+#define RG_FFT_SCALE_I_MSK 0xff003fff -+#define RG_FFT_SCALE_SFT 14 -+#define RG_FFT_SCALE_HI 23 -+#define RG_FFT_SCALE_SZ 10 -+#define RG_FFT_ENRG_FREQ_MSK 0x3f000000 -+#define RG_FFT_ENRG_FREQ_I_MSK 0xc0ffffff -+#define RG_FFT_ENRG_FREQ_SFT 24 -+#define RG_FFT_ENRG_FREQ_HI 29 -+#define RG_FFT_ENRG_FREQ_SZ 6 -+#define RG_FPGA_80M_PH_UP_MSK 0x40000000 -+#define RG_FPGA_80M_PH_UP_I_MSK 0xbfffffff -+#define RG_FPGA_80M_PH_UP_SFT 30 -+#define RG_FPGA_80M_PH_UP_HI 30 -+#define RG_FPGA_80M_PH_UP_SZ 1 -+#define RG_FPGA_80M_PH_STP_MSK 0x80000000 -+#define RG_FPGA_80M_PH_STP_I_MSK 0x7fffffff -+#define RG_FPGA_80M_PH_STP_SFT 31 -+#define RG_FPGA_80M_PH_STP_HI 31 -+#define RG_FPGA_80M_PH_STP_SZ 1 -+#define RG_ADC2LA_SEL_MSK 0x00000001 -+#define RG_ADC2LA_SEL_I_MSK 0xfffffffe -+#define RG_ADC2LA_SEL_SFT 0 -+#define RG_ADC2LA_SEL_HI 0 -+#define RG_ADC2LA_SEL_SZ 1 -+#define RG_ADC2LA_CLKPH_MSK 0x00000002 -+#define RG_ADC2LA_CLKPH_I_MSK 0xfffffffd -+#define RG_ADC2LA_CLKPH_SFT 1 -+#define RG_ADC2LA_CLKPH_HI 1 -+#define RG_ADC2LA_CLKPH_SZ 1 -+#define RG_RXIQ_EMU_IDX_MSK 0x0000000f -+#define RG_RXIQ_EMU_IDX_I_MSK 0xfffffff0 -+#define RG_RXIQ_EMU_IDX_SFT 0 -+#define RG_RXIQ_EMU_IDX_HI 3 -+#define RG_RXIQ_EMU_IDX_SZ 4 -+#define RG_IQCAL_BP_ACI_MSK 0x00000010 -+#define RG_IQCAL_BP_ACI_I_MSK 0xffffffef -+#define RG_IQCAL_BP_ACI_SFT 4 -+#define RG_IQCAL_BP_ACI_HI 4 -+#define RG_IQCAL_BP_ACI_SZ 1 -+#define RG_DPD_AM_EN_MSK 0x00000001 -+#define RG_DPD_AM_EN_I_MSK 0xfffffffe -+#define RG_DPD_AM_EN_SFT 0 -+#define RG_DPD_AM_EN_HI 0 -+#define RG_DPD_AM_EN_SZ 1 -+#define RG_DPD_PM_EN_MSK 0x00000002 -+#define RG_DPD_PM_EN_I_MSK 0xfffffffd -+#define RG_DPD_PM_EN_SFT 1 -+#define RG_DPD_PM_EN_HI 1 -+#define RG_DPD_PM_EN_SZ 1 -+#define RG_DPD_PM_AMSEL_MSK 0x00000004 -+#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb -+#define RG_DPD_PM_AMSEL_SFT 2 -+#define RG_DPD_PM_AMSEL_HI 2 -+#define RG_DPD_PM_AMSEL_SZ 1 -+#define RG_DPD_020_GAIN_MSK 0x000003ff -+#define RG_DPD_020_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_020_GAIN_SFT 0 -+#define RG_DPD_020_GAIN_HI 9 -+#define RG_DPD_020_GAIN_SZ 10 -+#define RG_DPD_040_GAIN_MSK 0x03ff0000 -+#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_040_GAIN_SFT 16 -+#define RG_DPD_040_GAIN_HI 25 -+#define RG_DPD_040_GAIN_SZ 10 -+#define RG_DPD_060_GAIN_MSK 0x000003ff -+#define RG_DPD_060_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_060_GAIN_SFT 0 -+#define RG_DPD_060_GAIN_HI 9 -+#define RG_DPD_060_GAIN_SZ 10 -+#define RG_DPD_080_GAIN_MSK 0x03ff0000 -+#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_080_GAIN_SFT 16 -+#define RG_DPD_080_GAIN_HI 25 -+#define RG_DPD_080_GAIN_SZ 10 -+#define RG_DPD_0A0_GAIN_MSK 0x000003ff -+#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_0A0_GAIN_SFT 0 -+#define RG_DPD_0A0_GAIN_HI 9 -+#define RG_DPD_0A0_GAIN_SZ 10 -+#define RG_DPD_0C0_GAIN_MSK 0x03ff0000 -+#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_0C0_GAIN_SFT 16 -+#define RG_DPD_0C0_GAIN_HI 25 -+#define RG_DPD_0C0_GAIN_SZ 10 -+#define RG_DPD_0D0_GAIN_MSK 0x000003ff -+#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_0D0_GAIN_SFT 0 -+#define RG_DPD_0D0_GAIN_HI 9 -+#define RG_DPD_0D0_GAIN_SZ 10 -+#define RG_DPD_0E0_GAIN_MSK 0x03ff0000 -+#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_0E0_GAIN_SFT 16 -+#define RG_DPD_0E0_GAIN_HI 25 -+#define RG_DPD_0E0_GAIN_SZ 10 -+#define RG_DPD_0F0_GAIN_MSK 0x000003ff -+#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_0F0_GAIN_SFT 0 -+#define RG_DPD_0F0_GAIN_HI 9 -+#define RG_DPD_0F0_GAIN_SZ 10 -+#define RG_DPD_100_GAIN_MSK 0x03ff0000 -+#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_100_GAIN_SFT 16 -+#define RG_DPD_100_GAIN_HI 25 -+#define RG_DPD_100_GAIN_SZ 10 -+#define RG_DPD_110_GAIN_MSK 0x000003ff -+#define RG_DPD_110_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_110_GAIN_SFT 0 -+#define RG_DPD_110_GAIN_HI 9 -+#define RG_DPD_110_GAIN_SZ 10 -+#define RG_DPD_120_GAIN_MSK 0x03ff0000 -+#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_120_GAIN_SFT 16 -+#define RG_DPD_120_GAIN_HI 25 -+#define RG_DPD_120_GAIN_SZ 10 -+#define RG_DPD_130_GAIN_MSK 0x000003ff -+#define RG_DPD_130_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_130_GAIN_SFT 0 -+#define RG_DPD_130_GAIN_HI 9 -+#define RG_DPD_130_GAIN_SZ 10 -+#define RG_DPD_140_GAIN_MSK 0x03ff0000 -+#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_140_GAIN_SFT 16 -+#define RG_DPD_140_GAIN_HI 25 -+#define RG_DPD_140_GAIN_SZ 10 -+#define RG_DPD_150_GAIN_MSK 0x000003ff -+#define RG_DPD_150_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_150_GAIN_SFT 0 -+#define RG_DPD_150_GAIN_HI 9 -+#define RG_DPD_150_GAIN_SZ 10 -+#define RG_DPD_160_GAIN_MSK 0x03ff0000 -+#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_160_GAIN_SFT 16 -+#define RG_DPD_160_GAIN_HI 25 -+#define RG_DPD_160_GAIN_SZ 10 -+#define RG_DPD_170_GAIN_MSK 0x000003ff -+#define RG_DPD_170_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_170_GAIN_SFT 0 -+#define RG_DPD_170_GAIN_HI 9 -+#define RG_DPD_170_GAIN_SZ 10 -+#define RG_DPD_180_GAIN_MSK 0x03ff0000 -+#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_180_GAIN_SFT 16 -+#define RG_DPD_180_GAIN_HI 25 -+#define RG_DPD_180_GAIN_SZ 10 -+#define RG_DPD_190_GAIN_MSK 0x000003ff -+#define RG_DPD_190_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_190_GAIN_SFT 0 -+#define RG_DPD_190_GAIN_HI 9 -+#define RG_DPD_190_GAIN_SZ 10 -+#define RG_DPD_1A0_GAIN_MSK 0x03ff0000 -+#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_1A0_GAIN_SFT 16 -+#define RG_DPD_1A0_GAIN_HI 25 -+#define RG_DPD_1A0_GAIN_SZ 10 -+#define RG_DPD_1B0_GAIN_MSK 0x000003ff -+#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_1B0_GAIN_SFT 0 -+#define RG_DPD_1B0_GAIN_HI 9 -+#define RG_DPD_1B0_GAIN_SZ 10 -+#define RG_DPD_1C0_GAIN_MSK 0x03ff0000 -+#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_1C0_GAIN_SFT 16 -+#define RG_DPD_1C0_GAIN_HI 25 -+#define RG_DPD_1C0_GAIN_SZ 10 -+#define RG_DPD_1D0_GAIN_MSK 0x000003ff -+#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_1D0_GAIN_SFT 0 -+#define RG_DPD_1D0_GAIN_HI 9 -+#define RG_DPD_1D0_GAIN_SZ 10 -+#define RG_DPD_1E0_GAIN_MSK 0x03ff0000 -+#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_1E0_GAIN_SFT 16 -+#define RG_DPD_1E0_GAIN_HI 25 -+#define RG_DPD_1E0_GAIN_SZ 10 -+#define RG_DPD_1F0_GAIN_MSK 0x000003ff -+#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_1F0_GAIN_SFT 0 -+#define RG_DPD_1F0_GAIN_HI 9 -+#define RG_DPD_1F0_GAIN_SZ 10 -+#define RG_DPD_200_GAIN_MSK 0x03ff0000 -+#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff -+#define RG_DPD_200_GAIN_SFT 16 -+#define RG_DPD_200_GAIN_HI 25 -+#define RG_DPD_200_GAIN_SZ 10 -+#define RG_DPD_020_PH_MSK 0x00001fff -+#define RG_DPD_020_PH_I_MSK 0xffffe000 -+#define RG_DPD_020_PH_SFT 0 -+#define RG_DPD_020_PH_HI 12 -+#define RG_DPD_020_PH_SZ 13 -+#define RG_DPD_040_PH_MSK 0x1fff0000 -+#define RG_DPD_040_PH_I_MSK 0xe000ffff -+#define RG_DPD_040_PH_SFT 16 -+#define RG_DPD_040_PH_HI 28 -+#define RG_DPD_040_PH_SZ 13 -+#define RG_DPD_060_PH_MSK 0x00001fff -+#define RG_DPD_060_PH_I_MSK 0xffffe000 -+#define RG_DPD_060_PH_SFT 0 -+#define RG_DPD_060_PH_HI 12 -+#define RG_DPD_060_PH_SZ 13 -+#define RG_DPD_080_PH_MSK 0x1fff0000 -+#define RG_DPD_080_PH_I_MSK 0xe000ffff -+#define RG_DPD_080_PH_SFT 16 -+#define RG_DPD_080_PH_HI 28 -+#define RG_DPD_080_PH_SZ 13 -+#define RG_DPD_0A0_PH_MSK 0x00001fff -+#define RG_DPD_0A0_PH_I_MSK 0xffffe000 -+#define RG_DPD_0A0_PH_SFT 0 -+#define RG_DPD_0A0_PH_HI 12 -+#define RG_DPD_0A0_PH_SZ 13 -+#define RG_DPD_0C0_PH_MSK 0x1fff0000 -+#define RG_DPD_0C0_PH_I_MSK 0xe000ffff -+#define RG_DPD_0C0_PH_SFT 16 -+#define RG_DPD_0C0_PH_HI 28 -+#define RG_DPD_0C0_PH_SZ 13 -+#define RG_DPD_0D0_PH_MSK 0x00001fff -+#define RG_DPD_0D0_PH_I_MSK 0xffffe000 -+#define RG_DPD_0D0_PH_SFT 0 -+#define RG_DPD_0D0_PH_HI 12 -+#define RG_DPD_0D0_PH_SZ 13 -+#define RG_DPD_0E0_PH_MSK 0x1fff0000 -+#define RG_DPD_0E0_PH_I_MSK 0xe000ffff -+#define RG_DPD_0E0_PH_SFT 16 -+#define RG_DPD_0E0_PH_HI 28 -+#define RG_DPD_0E0_PH_SZ 13 -+#define RG_DPD_0F0_PH_MSK 0x00001fff -+#define RG_DPD_0F0_PH_I_MSK 0xffffe000 -+#define RG_DPD_0F0_PH_SFT 0 -+#define RG_DPD_0F0_PH_HI 12 -+#define RG_DPD_0F0_PH_SZ 13 -+#define RG_DPD_100_PH_MSK 0x1fff0000 -+#define RG_DPD_100_PH_I_MSK 0xe000ffff -+#define RG_DPD_100_PH_SFT 16 -+#define RG_DPD_100_PH_HI 28 -+#define RG_DPD_100_PH_SZ 13 -+#define RG_DPD_110_PH_MSK 0x00001fff -+#define RG_DPD_110_PH_I_MSK 0xffffe000 -+#define RG_DPD_110_PH_SFT 0 -+#define RG_DPD_110_PH_HI 12 -+#define RG_DPD_110_PH_SZ 13 -+#define RG_DPD_120_PH_MSK 0x1fff0000 -+#define RG_DPD_120_PH_I_MSK 0xe000ffff -+#define RG_DPD_120_PH_SFT 16 -+#define RG_DPD_120_PH_HI 28 -+#define RG_DPD_120_PH_SZ 13 -+#define RG_DPD_130_PH_MSK 0x00001fff -+#define RG_DPD_130_PH_I_MSK 0xffffe000 -+#define RG_DPD_130_PH_SFT 0 -+#define RG_DPD_130_PH_HI 12 -+#define RG_DPD_130_PH_SZ 13 -+#define RG_DPD_140_PH_MSK 0x1fff0000 -+#define RG_DPD_140_PH_I_MSK 0xe000ffff -+#define RG_DPD_140_PH_SFT 16 -+#define RG_DPD_140_PH_HI 28 -+#define RG_DPD_140_PH_SZ 13 -+#define RG_DPD_150_PH_MSK 0x00001fff -+#define RG_DPD_150_PH_I_MSK 0xffffe000 -+#define RG_DPD_150_PH_SFT 0 -+#define RG_DPD_150_PH_HI 12 -+#define RG_DPD_150_PH_SZ 13 -+#define RG_DPD_160_PH_MSK 0x1fff0000 -+#define RG_DPD_160_PH_I_MSK 0xe000ffff -+#define RG_DPD_160_PH_SFT 16 -+#define RG_DPD_160_PH_HI 28 -+#define RG_DPD_160_PH_SZ 13 -+#define RG_DPD_170_PH_MSK 0x00001fff -+#define RG_DPD_170_PH_I_MSK 0xffffe000 -+#define RG_DPD_170_PH_SFT 0 -+#define RG_DPD_170_PH_HI 12 -+#define RG_DPD_170_PH_SZ 13 -+#define RG_DPD_180_PH_MSK 0x1fff0000 -+#define RG_DPD_180_PH_I_MSK 0xe000ffff -+#define RG_DPD_180_PH_SFT 16 -+#define RG_DPD_180_PH_HI 28 -+#define RG_DPD_180_PH_SZ 13 -+#define RG_DPD_190_PH_MSK 0x00001fff -+#define RG_DPD_190_PH_I_MSK 0xffffe000 -+#define RG_DPD_190_PH_SFT 0 -+#define RG_DPD_190_PH_HI 12 -+#define RG_DPD_190_PH_SZ 13 -+#define RG_DPD_1A0_PH_MSK 0x1fff0000 -+#define RG_DPD_1A0_PH_I_MSK 0xe000ffff -+#define RG_DPD_1A0_PH_SFT 16 -+#define RG_DPD_1A0_PH_HI 28 -+#define RG_DPD_1A0_PH_SZ 13 -+#define RG_DPD_1B0_PH_MSK 0x00001fff -+#define RG_DPD_1B0_PH_I_MSK 0xffffe000 -+#define RG_DPD_1B0_PH_SFT 0 -+#define RG_DPD_1B0_PH_HI 12 -+#define RG_DPD_1B0_PH_SZ 13 -+#define RG_DPD_1C0_PH_MSK 0x1fff0000 -+#define RG_DPD_1C0_PH_I_MSK 0xe000ffff -+#define RG_DPD_1C0_PH_SFT 16 -+#define RG_DPD_1C0_PH_HI 28 -+#define RG_DPD_1C0_PH_SZ 13 -+#define RG_DPD_1D0_PH_MSK 0x00001fff -+#define RG_DPD_1D0_PH_I_MSK 0xffffe000 -+#define RG_DPD_1D0_PH_SFT 0 -+#define RG_DPD_1D0_PH_HI 12 -+#define RG_DPD_1D0_PH_SZ 13 -+#define RG_DPD_1E0_PH_MSK 0x1fff0000 -+#define RG_DPD_1E0_PH_I_MSK 0xe000ffff -+#define RG_DPD_1E0_PH_SFT 16 -+#define RG_DPD_1E0_PH_HI 28 -+#define RG_DPD_1E0_PH_SZ 13 -+#define RG_DPD_1F0_PH_MSK 0x00001fff -+#define RG_DPD_1F0_PH_I_MSK 0xffffe000 -+#define RG_DPD_1F0_PH_SFT 0 -+#define RG_DPD_1F0_PH_HI 12 -+#define RG_DPD_1F0_PH_SZ 13 -+#define RG_DPD_200_PH_MSK 0x1fff0000 -+#define RG_DPD_200_PH_I_MSK 0xe000ffff -+#define RG_DPD_200_PH_SFT 16 -+#define RG_DPD_200_PH_HI 28 -+#define RG_DPD_200_PH_SZ 13 -+#define RG_DPD_GAIN_EST_Y0_MSK 0x000001ff -+#define RG_DPD_GAIN_EST_Y0_I_MSK 0xfffffe00 -+#define RG_DPD_GAIN_EST_Y0_SFT 0 -+#define RG_DPD_GAIN_EST_Y0_HI 8 -+#define RG_DPD_GAIN_EST_Y0_SZ 9 -+#define RG_DPD_GAIN_EST_Y1_MSK 0x01ff0000 -+#define RG_DPD_GAIN_EST_Y1_I_MSK 0xfe00ffff -+#define RG_DPD_GAIN_EST_Y1_SFT 16 -+#define RG_DPD_GAIN_EST_Y1_HI 24 -+#define RG_DPD_GAIN_EST_Y1_SZ 9 -+#define RG_DPD_LOOP_GAIN_MSK 0x000003ff -+#define RG_DPD_LOOP_GAIN_I_MSK 0xfffffc00 -+#define RG_DPD_LOOP_GAIN_SFT 0 -+#define RG_DPD_LOOP_GAIN_HI 9 -+#define RG_DPD_LOOP_GAIN_SZ 10 -+#define RG_DPD_GAIN_EST_X0_MSK 0x000001ff -+#define RG_DPD_GAIN_EST_X0_I_MSK 0xfffffe00 -+#define RG_DPD_GAIN_EST_X0_SFT 0 -+#define RG_DPD_GAIN_EST_X0_HI 8 -+#define RG_DPD_GAIN_EST_X0_SZ 9 -+#define RO_DPD_GAIN_MSK 0x03ff0000 -+#define RO_DPD_GAIN_I_MSK 0xfc00ffff -+#define RO_DPD_GAIN_SFT 16 -+#define RO_DPD_GAIN_HI 25 -+#define RO_DPD_GAIN_SZ 10 -+#define TX_SCALE_11B_MSK 0x000000ff -+#define TX_SCALE_11B_I_MSK 0xffffff00 -+#define TX_SCALE_11B_SFT 0 -+#define TX_SCALE_11B_HI 7 -+#define TX_SCALE_11B_SZ 8 -+#define TX_SCALE_11B_P0D5_MSK 0x0000ff00 -+#define TX_SCALE_11B_P0D5_I_MSK 0xffff00ff -+#define TX_SCALE_11B_P0D5_SFT 8 -+#define TX_SCALE_11B_P0D5_HI 15 -+#define TX_SCALE_11B_P0D5_SZ 8 -+#define TX_SCALE_11G_MSK 0x00ff0000 -+#define TX_SCALE_11G_I_MSK 0xff00ffff -+#define TX_SCALE_11G_SFT 16 -+#define TX_SCALE_11G_HI 23 -+#define TX_SCALE_11G_SZ 8 -+#define TX_SCALE_11G_P0D5_MSK 0xff000000 -+#define TX_SCALE_11G_P0D5_I_MSK 0x00ffffff -+#define TX_SCALE_11G_P0D5_SFT 24 -+#define TX_SCALE_11G_P0D5_HI 31 -+#define TX_SCALE_11G_P0D5_SZ 8 -+#define RG_EN_MANUAL_MSK 0x00000001 -+#define RG_EN_MANUAL_I_MSK 0xfffffffe -+#define RG_EN_MANUAL_SFT 0 -+#define RG_EN_MANUAL_HI 0 -+#define RG_EN_MANUAL_SZ 1 -+#define RG_TX_EN_MSK 0x00000002 -+#define RG_TX_EN_I_MSK 0xfffffffd -+#define RG_TX_EN_SFT 1 -+#define RG_TX_EN_HI 1 -+#define RG_TX_EN_SZ 1 -+#define RG_TX_PA_EN_MSK 0x00000004 -+#define RG_TX_PA_EN_I_MSK 0xfffffffb -+#define RG_TX_PA_EN_SFT 2 -+#define RG_TX_PA_EN_HI 2 -+#define RG_TX_PA_EN_SZ 1 -+#define RG_TX_DAC_EN_MSK 0x00000008 -+#define RG_TX_DAC_EN_I_MSK 0xfffffff7 -+#define RG_TX_DAC_EN_SFT 3 -+#define RG_TX_DAC_EN_HI 3 -+#define RG_TX_DAC_EN_SZ 1 -+#define RG_RX_AGC_MSK 0x00000010 -+#define RG_RX_AGC_I_MSK 0xffffffef -+#define RG_RX_AGC_SFT 4 -+#define RG_RX_AGC_HI 4 -+#define RG_RX_AGC_SZ 1 -+#define RG_RX_GAIN_MANUAL_MSK 0x00000020 -+#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf -+#define RG_RX_GAIN_MANUAL_SFT 5 -+#define RG_RX_GAIN_MANUAL_HI 5 -+#define RG_RX_GAIN_MANUAL_SZ 1 -+#define RG_RFG_MSK 0x000000c0 -+#define RG_RFG_I_MSK 0xffffff3f -+#define RG_RFG_SFT 6 -+#define RG_RFG_HI 7 -+#define RG_RFG_SZ 2 -+#define RG_PGAG_MSK 0x00000f00 -+#define RG_PGAG_I_MSK 0xfffff0ff -+#define RG_PGAG_SFT 8 -+#define RG_PGAG_HI 11 -+#define RG_PGAG_SZ 4 -+#define RG_MODE_MSK 0x00003000 -+#define RG_MODE_I_MSK 0xffffcfff -+#define RG_MODE_SFT 12 -+#define RG_MODE_HI 13 -+#define RG_MODE_SZ 2 -+#define RG_EN_TX_TRSW_MSK 0x00004000 -+#define RG_EN_TX_TRSW_I_MSK 0xffffbfff -+#define RG_EN_TX_TRSW_SFT 14 -+#define RG_EN_TX_TRSW_HI 14 -+#define RG_EN_TX_TRSW_SZ 1 -+#define RG_EN_SX_MSK 0x00008000 -+#define RG_EN_SX_I_MSK 0xffff7fff -+#define RG_EN_SX_SFT 15 -+#define RG_EN_SX_HI 15 -+#define RG_EN_SX_SZ 1 -+#define RG_EN_RX_LNA_MSK 0x00010000 -+#define RG_EN_RX_LNA_I_MSK 0xfffeffff -+#define RG_EN_RX_LNA_SFT 16 -+#define RG_EN_RX_LNA_HI 16 -+#define RG_EN_RX_LNA_SZ 1 -+#define RG_EN_RX_MIXER_MSK 0x00020000 -+#define RG_EN_RX_MIXER_I_MSK 0xfffdffff -+#define RG_EN_RX_MIXER_SFT 17 -+#define RG_EN_RX_MIXER_HI 17 -+#define RG_EN_RX_MIXER_SZ 1 -+#define RG_EN_RX_DIV2_MSK 0x00040000 -+#define RG_EN_RX_DIV2_I_MSK 0xfffbffff -+#define RG_EN_RX_DIV2_SFT 18 -+#define RG_EN_RX_DIV2_HI 18 -+#define RG_EN_RX_DIV2_SZ 1 -+#define RG_EN_RX_LOBUF_MSK 0x00080000 -+#define RG_EN_RX_LOBUF_I_MSK 0xfff7ffff -+#define RG_EN_RX_LOBUF_SFT 19 -+#define RG_EN_RX_LOBUF_HI 19 -+#define RG_EN_RX_LOBUF_SZ 1 -+#define RG_EN_RX_TZ_MSK 0x00100000 -+#define RG_EN_RX_TZ_I_MSK 0xffefffff -+#define RG_EN_RX_TZ_SFT 20 -+#define RG_EN_RX_TZ_HI 20 -+#define RG_EN_RX_TZ_SZ 1 -+#define RG_EN_RX_FILTER_MSK 0x00200000 -+#define RG_EN_RX_FILTER_I_MSK 0xffdfffff -+#define RG_EN_RX_FILTER_SFT 21 -+#define RG_EN_RX_FILTER_HI 21 -+#define RG_EN_RX_FILTER_SZ 1 -+#define RG_EN_RX_HPF_MSK 0x00400000 -+#define RG_EN_RX_HPF_I_MSK 0xffbfffff -+#define RG_EN_RX_HPF_SFT 22 -+#define RG_EN_RX_HPF_HI 22 -+#define RG_EN_RX_HPF_SZ 1 -+#define RG_EN_RX_RSSI_MSK 0x00800000 -+#define RG_EN_RX_RSSI_I_MSK 0xff7fffff -+#define RG_EN_RX_RSSI_SFT 23 -+#define RG_EN_RX_RSSI_HI 23 -+#define RG_EN_RX_RSSI_SZ 1 -+#define RG_EN_ADC_MSK 0x01000000 -+#define RG_EN_ADC_I_MSK 0xfeffffff -+#define RG_EN_ADC_SFT 24 -+#define RG_EN_ADC_HI 24 -+#define RG_EN_ADC_SZ 1 -+#define RG_EN_TX_MOD_MSK 0x02000000 -+#define RG_EN_TX_MOD_I_MSK 0xfdffffff -+#define RG_EN_TX_MOD_SFT 25 -+#define RG_EN_TX_MOD_HI 25 -+#define RG_EN_TX_MOD_SZ 1 -+#define RG_EN_TX_DIV2_MSK 0x04000000 -+#define RG_EN_TX_DIV2_I_MSK 0xfbffffff -+#define RG_EN_TX_DIV2_SFT 26 -+#define RG_EN_TX_DIV2_HI 26 -+#define RG_EN_TX_DIV2_SZ 1 -+#define RG_EN_TX_DIV2_BUF_MSK 0x08000000 -+#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff -+#define RG_EN_TX_DIV2_BUF_SFT 27 -+#define RG_EN_TX_DIV2_BUF_HI 27 -+#define RG_EN_TX_DIV2_BUF_SZ 1 -+#define RG_EN_TX_LOBF_MSK 0x10000000 -+#define RG_EN_TX_LOBF_I_MSK 0xefffffff -+#define RG_EN_TX_LOBF_SFT 28 -+#define RG_EN_TX_LOBF_HI 28 -+#define RG_EN_TX_LOBF_SZ 1 -+#define RG_EN_RX_LOBF_MSK 0x20000000 -+#define RG_EN_RX_LOBF_I_MSK 0xdfffffff -+#define RG_EN_RX_LOBF_SFT 29 -+#define RG_EN_RX_LOBF_HI 29 -+#define RG_EN_RX_LOBF_SZ 1 -+#define RG_SEL_DPLL_CLK_MSK 0x40000000 -+#define RG_SEL_DPLL_CLK_I_MSK 0xbfffffff -+#define RG_SEL_DPLL_CLK_SFT 30 -+#define RG_SEL_DPLL_CLK_HI 30 -+#define RG_SEL_DPLL_CLK_SZ 1 -+#define RG_EN_CLK_960MBY13_UART_MSK 0x80000000 -+#define RG_EN_CLK_960MBY13_UART_I_MSK 0x7fffffff -+#define RG_EN_CLK_960MBY13_UART_SFT 31 -+#define RG_EN_CLK_960MBY13_UART_HI 31 -+#define RG_EN_CLK_960MBY13_UART_SZ 1 -+#define RG_EN_TX_DPD_MSK 0x00000001 -+#define RG_EN_TX_DPD_I_MSK 0xfffffffe -+#define RG_EN_TX_DPD_SFT 0 -+#define RG_EN_TX_DPD_HI 0 -+#define RG_EN_TX_DPD_SZ 1 -+#define RG_EN_TX_TSSI_MSK 0x00000002 -+#define RG_EN_TX_TSSI_I_MSK 0xfffffffd -+#define RG_EN_TX_TSSI_SFT 1 -+#define RG_EN_TX_TSSI_HI 1 -+#define RG_EN_TX_TSSI_SZ 1 -+#define RG_EN_RX_IQCAL_MSK 0x00000004 -+#define RG_EN_RX_IQCAL_I_MSK 0xfffffffb -+#define RG_EN_RX_IQCAL_SFT 2 -+#define RG_EN_RX_IQCAL_HI 2 -+#define RG_EN_RX_IQCAL_SZ 1 -+#define RG_EN_TX_DAC_CAL_MSK 0x00000008 -+#define RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7 -+#define RG_EN_TX_DAC_CAL_SFT 3 -+#define RG_EN_TX_DAC_CAL_HI 3 -+#define RG_EN_TX_DAC_CAL_SZ 1 -+#define RG_EN_TX_SELF_MIXER_MSK 0x00000010 -+#define RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef -+#define RG_EN_TX_SELF_MIXER_SFT 4 -+#define RG_EN_TX_SELF_MIXER_HI 4 -+#define RG_EN_TX_SELF_MIXER_SZ 1 -+#define RG_EN_TX_DAC_OUT_MSK 0x00000020 -+#define RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf -+#define RG_EN_TX_DAC_OUT_SFT 5 -+#define RG_EN_TX_DAC_OUT_HI 5 -+#define RG_EN_TX_DAC_OUT_SZ 1 -+#define RG_EN_LDO_RX_FE_MSK 0x00000040 -+#define RG_EN_LDO_RX_FE_I_MSK 0xffffffbf -+#define RG_EN_LDO_RX_FE_SFT 6 -+#define RG_EN_LDO_RX_FE_HI 6 -+#define RG_EN_LDO_RX_FE_SZ 1 -+#define RG_EN_LDO_ABB_MSK 0x00000080 -+#define RG_EN_LDO_ABB_I_MSK 0xffffff7f -+#define RG_EN_LDO_ABB_SFT 7 -+#define RG_EN_LDO_ABB_HI 7 -+#define RG_EN_LDO_ABB_SZ 1 -+#define RG_EN_LDO_AFE_MSK 0x00000100 -+#define RG_EN_LDO_AFE_I_MSK 0xfffffeff -+#define RG_EN_LDO_AFE_SFT 8 -+#define RG_EN_LDO_AFE_HI 8 -+#define RG_EN_LDO_AFE_SZ 1 -+#define RG_EN_SX_CHPLDO_MSK 0x00000200 -+#define RG_EN_SX_CHPLDO_I_MSK 0xfffffdff -+#define RG_EN_SX_CHPLDO_SFT 9 -+#define RG_EN_SX_CHPLDO_HI 9 -+#define RG_EN_SX_CHPLDO_SZ 1 -+#define RG_EN_SX_LOBFLDO_MSK 0x00000400 -+#define RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff -+#define RG_EN_SX_LOBFLDO_SFT 10 -+#define RG_EN_SX_LOBFLDO_HI 10 -+#define RG_EN_SX_LOBFLDO_SZ 1 -+#define RG_EN_IREF_RX_MSK 0x00000800 -+#define RG_EN_IREF_RX_I_MSK 0xfffff7ff -+#define RG_EN_IREF_RX_SFT 11 -+#define RG_EN_IREF_RX_HI 11 -+#define RG_EN_IREF_RX_SZ 1 -+#define RG_EN_TX_DAC_VOUT_MSK 0x00002000 -+#define RG_EN_TX_DAC_VOUT_I_MSK 0xffffdfff -+#define RG_EN_TX_DAC_VOUT_SFT 13 -+#define RG_EN_TX_DAC_VOUT_HI 13 -+#define RG_EN_TX_DAC_VOUT_SZ 1 -+#define RG_EN_SX_LCK_BIN_MSK 0x00004000 -+#define RG_EN_SX_LCK_BIN_I_MSK 0xffffbfff -+#define RG_EN_SX_LCK_BIN_SFT 14 -+#define RG_EN_SX_LCK_BIN_HI 14 -+#define RG_EN_SX_LCK_BIN_SZ 1 -+#define RG_RTC_CAL_MODE_MSK 0x00010000 -+#define RG_RTC_CAL_MODE_I_MSK 0xfffeffff -+#define RG_RTC_CAL_MODE_SFT 16 -+#define RG_RTC_CAL_MODE_HI 16 -+#define RG_RTC_CAL_MODE_SZ 1 -+#define RG_EN_IQPAD_IOSW_MSK 0x00020000 -+#define RG_EN_IQPAD_IOSW_I_MSK 0xfffdffff -+#define RG_EN_IQPAD_IOSW_SFT 17 -+#define RG_EN_IQPAD_IOSW_HI 17 -+#define RG_EN_IQPAD_IOSW_SZ 1 -+#define RG_EN_TESTPAD_IOSW_MSK 0x00040000 -+#define RG_EN_TESTPAD_IOSW_I_MSK 0xfffbffff -+#define RG_EN_TESTPAD_IOSW_SFT 18 -+#define RG_EN_TESTPAD_IOSW_HI 18 -+#define RG_EN_TESTPAD_IOSW_SZ 1 -+#define RG_EN_TRXBF_BYPASS_MSK 0x00080000 -+#define RG_EN_TRXBF_BYPASS_I_MSK 0xfff7ffff -+#define RG_EN_TRXBF_BYPASS_SFT 19 -+#define RG_EN_TRXBF_BYPASS_HI 19 -+#define RG_EN_TRXBF_BYPASS_SZ 1 -+#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007 -+#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8 -+#define RG_LDO_LEVEL_RX_FE_SFT 0 -+#define RG_LDO_LEVEL_RX_FE_HI 2 -+#define RG_LDO_LEVEL_RX_FE_SZ 3 -+#define RG_LDO_LEVEL_ABB_MSK 0x00000038 -+#define RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7 -+#define RG_LDO_LEVEL_ABB_SFT 3 -+#define RG_LDO_LEVEL_ABB_HI 5 -+#define RG_LDO_LEVEL_ABB_SZ 3 -+#define RG_LDO_LEVEL_AFE_MSK 0x000001c0 -+#define RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f -+#define RG_LDO_LEVEL_AFE_SFT 6 -+#define RG_LDO_LEVEL_AFE_HI 8 -+#define RG_LDO_LEVEL_AFE_SZ 3 -+#define RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00 -+#define RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff -+#define RG_SX_LDO_CHP_LEVEL_SFT 9 -+#define RG_SX_LDO_CHP_LEVEL_HI 11 -+#define RG_SX_LDO_CHP_LEVEL_SZ 3 -+#define RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000 -+#define RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff -+#define RG_SX_LDO_LOBF_LEVEL_SFT 12 -+#define RG_SX_LDO_LOBF_LEVEL_HI 14 -+#define RG_SX_LDO_LOBF_LEVEL_SZ 3 -+#define RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000 -+#define RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff -+#define RG_SX_LDO_XOSC_LEVEL_SFT 15 -+#define RG_SX_LDO_XOSC_LEVEL_HI 17 -+#define RG_SX_LDO_XOSC_LEVEL_SZ 3 -+#define RG_DP_LDO_LEVEL_MSK 0x001c0000 -+#define RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff -+#define RG_DP_LDO_LEVEL_SFT 18 -+#define RG_DP_LDO_LEVEL_HI 20 -+#define RG_DP_LDO_LEVEL_SZ 3 -+#define RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000 -+#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff -+#define RG_SX_LDO_VCO_LEVEL_SFT 21 -+#define RG_SX_LDO_VCO_LEVEL_HI 23 -+#define RG_SX_LDO_VCO_LEVEL_SZ 3 -+#define RG_TX_LDO_TX_LEVEL_MSK 0x07000000 -+#define RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff -+#define RG_TX_LDO_TX_LEVEL_SFT 24 -+#define RG_TX_LDO_TX_LEVEL_HI 26 -+#define RG_TX_LDO_TX_LEVEL_SZ 3 -+#define RG_EN_RX_PADSW_MSK 0x00000001 -+#define RG_EN_RX_PADSW_I_MSK 0xfffffffe -+#define RG_EN_RX_PADSW_SFT 0 -+#define RG_EN_RX_PADSW_HI 0 -+#define RG_EN_RX_PADSW_SZ 1 -+#define RG_EN_RX_TESTNODE_MSK 0x00000002 -+#define RG_EN_RX_TESTNODE_I_MSK 0xfffffffd -+#define RG_EN_RX_TESTNODE_SFT 1 -+#define RG_EN_RX_TESTNODE_HI 1 -+#define RG_EN_RX_TESTNODE_SZ 1 -+#define RG_RX_ABBCFIX_MSK 0x00000004 -+#define RG_RX_ABBCFIX_I_MSK 0xfffffffb -+#define RG_RX_ABBCFIX_SFT 2 -+#define RG_RX_ABBCFIX_HI 2 -+#define RG_RX_ABBCFIX_SZ 1 -+#define RG_RX_ABBCTUNE_MSK 0x000001f8 -+#define RG_RX_ABBCTUNE_I_MSK 0xfffffe07 -+#define RG_RX_ABBCTUNE_SFT 3 -+#define RG_RX_ABBCTUNE_HI 8 -+#define RG_RX_ABBCTUNE_SZ 6 -+#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200 -+#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff -+#define RG_RX_ABBOUT_TRI_STATE_SFT 9 -+#define RG_RX_ABBOUT_TRI_STATE_HI 9 -+#define RG_RX_ABBOUT_TRI_STATE_SZ 1 -+#define RG_RX_ABB_N_MODE_MSK 0x00000400 -+#define RG_RX_ABB_N_MODE_I_MSK 0xfffffbff -+#define RG_RX_ABB_N_MODE_SFT 10 -+#define RG_RX_ABB_N_MODE_HI 10 -+#define RG_RX_ABB_N_MODE_SZ 1 -+#define RG_RX_EN_LOOPA_MSK 0x00000800 -+#define RG_RX_EN_LOOPA_I_MSK 0xfffff7ff -+#define RG_RX_EN_LOOPA_SFT 11 -+#define RG_RX_EN_LOOPA_HI 11 -+#define RG_RX_EN_LOOPA_SZ 1 -+#define RG_RX_FILTERI1ST_MSK 0x00003000 -+#define RG_RX_FILTERI1ST_I_MSK 0xffffcfff -+#define RG_RX_FILTERI1ST_SFT 12 -+#define RG_RX_FILTERI1ST_HI 13 -+#define RG_RX_FILTERI1ST_SZ 2 -+#define RG_RX_FILTERI2ND_MSK 0x0000c000 -+#define RG_RX_FILTERI2ND_I_MSK 0xffff3fff -+#define RG_RX_FILTERI2ND_SFT 14 -+#define RG_RX_FILTERI2ND_HI 15 -+#define RG_RX_FILTERI2ND_SZ 2 -+#define RG_RX_FILTERI3RD_MSK 0x00030000 -+#define RG_RX_FILTERI3RD_I_MSK 0xfffcffff -+#define RG_RX_FILTERI3RD_SFT 16 -+#define RG_RX_FILTERI3RD_HI 17 -+#define RG_RX_FILTERI3RD_SZ 2 -+#define RG_RX_FILTERI_COURSE_MSK 0x000c0000 -+#define RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff -+#define RG_RX_FILTERI_COURSE_SFT 18 -+#define RG_RX_FILTERI_COURSE_HI 19 -+#define RG_RX_FILTERI_COURSE_SZ 2 -+#define RG_RX_FILTERVCM_MSK 0x00300000 -+#define RG_RX_FILTERVCM_I_MSK 0xffcfffff -+#define RG_RX_FILTERVCM_SFT 20 -+#define RG_RX_FILTERVCM_HI 21 -+#define RG_RX_FILTERVCM_SZ 2 -+#define RG_RX_HPF3M_MSK 0x00400000 -+#define RG_RX_HPF3M_I_MSK 0xffbfffff -+#define RG_RX_HPF3M_SFT 22 -+#define RG_RX_HPF3M_HI 22 -+#define RG_RX_HPF3M_SZ 1 -+#define RG_RX_HPF300K_MSK 0x00800000 -+#define RG_RX_HPF300K_I_MSK 0xff7fffff -+#define RG_RX_HPF300K_SFT 23 -+#define RG_RX_HPF300K_HI 23 -+#define RG_RX_HPF300K_SZ 1 -+#define RG_RX_HPFI_MSK 0x03000000 -+#define RG_RX_HPFI_I_MSK 0xfcffffff -+#define RG_RX_HPFI_SFT 24 -+#define RG_RX_HPFI_HI 25 -+#define RG_RX_HPFI_SZ 2 -+#define RG_RX_HPF_FINALCORNER_MSK 0x0c000000 -+#define RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff -+#define RG_RX_HPF_FINALCORNER_SFT 26 -+#define RG_RX_HPF_FINALCORNER_HI 27 -+#define RG_RX_HPF_FINALCORNER_SZ 2 -+#define RG_RX_HPF_SETTLE1_C_MSK 0x30000000 -+#define RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff -+#define RG_RX_HPF_SETTLE1_C_SFT 28 -+#define RG_RX_HPF_SETTLE1_C_HI 29 -+#define RG_RX_HPF_SETTLE1_C_SZ 2 -+#define RG_RX_HPF_SETTLE1_R_MSK 0x00000003 -+#define RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc -+#define RG_RX_HPF_SETTLE1_R_SFT 0 -+#define RG_RX_HPF_SETTLE1_R_HI 1 -+#define RG_RX_HPF_SETTLE1_R_SZ 2 -+#define RG_RX_HPF_SETTLE2_C_MSK 0x0000000c -+#define RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3 -+#define RG_RX_HPF_SETTLE2_C_SFT 2 -+#define RG_RX_HPF_SETTLE2_C_HI 3 -+#define RG_RX_HPF_SETTLE2_C_SZ 2 -+#define RG_RX_HPF_SETTLE2_R_MSK 0x00000030 -+#define RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf -+#define RG_RX_HPF_SETTLE2_R_SFT 4 -+#define RG_RX_HPF_SETTLE2_R_HI 5 -+#define RG_RX_HPF_SETTLE2_R_SZ 2 -+#define RG_RX_HPF_VCMCON2_MSK 0x000000c0 -+#define RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f -+#define RG_RX_HPF_VCMCON2_SFT 6 -+#define RG_RX_HPF_VCMCON2_HI 7 -+#define RG_RX_HPF_VCMCON2_SZ 2 -+#define RG_RX_HPF_VCMCON_MSK 0x00000300 -+#define RG_RX_HPF_VCMCON_I_MSK 0xfffffcff -+#define RG_RX_HPF_VCMCON_SFT 8 -+#define RG_RX_HPF_VCMCON_HI 9 -+#define RG_RX_HPF_VCMCON_SZ 2 -+#define RG_RX_OUTVCM_MSK 0x00000c00 -+#define RG_RX_OUTVCM_I_MSK 0xfffff3ff -+#define RG_RX_OUTVCM_SFT 10 -+#define RG_RX_OUTVCM_HI 11 -+#define RG_RX_OUTVCM_SZ 2 -+#define RG_RX_TZI_MSK 0x00003000 -+#define RG_RX_TZI_I_MSK 0xffffcfff -+#define RG_RX_TZI_SFT 12 -+#define RG_RX_TZI_HI 13 -+#define RG_RX_TZI_SZ 2 -+#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000 -+#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff -+#define RG_RX_TZ_OUT_TRISTATE_SFT 14 -+#define RG_RX_TZ_OUT_TRISTATE_HI 14 -+#define RG_RX_TZ_OUT_TRISTATE_SZ 1 -+#define RG_RX_TZ_VCM_MSK 0x00018000 -+#define RG_RX_TZ_VCM_I_MSK 0xfffe7fff -+#define RG_RX_TZ_VCM_SFT 15 -+#define RG_RX_TZ_VCM_HI 16 -+#define RG_RX_TZ_VCM_SZ 2 -+#define RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000 -+#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff -+#define RG_EN_RX_RSSI_TESTNODE_SFT 17 -+#define RG_EN_RX_RSSI_TESTNODE_HI 19 -+#define RG_EN_RX_RSSI_TESTNODE_SZ 3 -+#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000 -+#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff -+#define RG_RX_ADCRSSI_CLKSEL_SFT 20 -+#define RG_RX_ADCRSSI_CLKSEL_HI 20 -+#define RG_RX_ADCRSSI_CLKSEL_SZ 1 -+#define RG_RX_ADCRSSI_VCM_MSK 0x00600000 -+#define RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff -+#define RG_RX_ADCRSSI_VCM_SFT 21 -+#define RG_RX_ADCRSSI_VCM_HI 22 -+#define RG_RX_ADCRSSI_VCM_SZ 2 -+#define RG_RX_REC_LPFCORNER_MSK 0x01800000 -+#define RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff -+#define RG_RX_REC_LPFCORNER_SFT 23 -+#define RG_RX_REC_LPFCORNER_HI 24 -+#define RG_RX_REC_LPFCORNER_SZ 2 -+#define RG_RSSI_CLOCK_GATING_MSK 0x02000000 -+#define RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff -+#define RG_RSSI_CLOCK_GATING_SFT 25 -+#define RG_RSSI_CLOCK_GATING_HI 25 -+#define RG_RSSI_CLOCK_GATING_SZ 1 -+#define RG_TXPGA_CAPSW_MSK 0x00000003 -+#define RG_TXPGA_CAPSW_I_MSK 0xfffffffc -+#define RG_TXPGA_CAPSW_SFT 0 -+#define RG_TXPGA_CAPSW_HI 1 -+#define RG_TXPGA_CAPSW_SZ 2 -+#define RG_TXPGA_MAIN_MSK 0x000000fc -+#define RG_TXPGA_MAIN_I_MSK 0xffffff03 -+#define RG_TXPGA_MAIN_SFT 2 -+#define RG_TXPGA_MAIN_HI 7 -+#define RG_TXPGA_MAIN_SZ 6 -+#define RG_TXPGA_STEER_MSK 0x00003f00 -+#define RG_TXPGA_STEER_I_MSK 0xffffc0ff -+#define RG_TXPGA_STEER_SFT 8 -+#define RG_TXPGA_STEER_HI 13 -+#define RG_TXPGA_STEER_SZ 6 -+#define RG_TXMOD_GMCELL_MSK 0x0000c000 -+#define RG_TXMOD_GMCELL_I_MSK 0xffff3fff -+#define RG_TXMOD_GMCELL_SFT 14 -+#define RG_TXMOD_GMCELL_HI 15 -+#define RG_TXMOD_GMCELL_SZ 2 -+#define RG_TXLPF_GMCELL_MSK 0x00030000 -+#define RG_TXLPF_GMCELL_I_MSK 0xfffcffff -+#define RG_TXLPF_GMCELL_SFT 16 -+#define RG_TXLPF_GMCELL_HI 17 -+#define RG_TXLPF_GMCELL_SZ 2 -+#define RG_PACELL_EN_MSK 0x001c0000 -+#define RG_PACELL_EN_I_MSK 0xffe3ffff -+#define RG_PACELL_EN_SFT 18 -+#define RG_PACELL_EN_HI 20 -+#define RG_PACELL_EN_SZ 3 -+#define RG_PABIAS_CTRL_MSK 0x01e00000 -+#define RG_PABIAS_CTRL_I_MSK 0xfe1fffff -+#define RG_PABIAS_CTRL_SFT 21 -+#define RG_PABIAS_CTRL_HI 24 -+#define RG_PABIAS_CTRL_SZ 4 -+#define RG_TX_DIV_VSET_MSK 0x0c000000 -+#define RG_TX_DIV_VSET_I_MSK 0xf3ffffff -+#define RG_TX_DIV_VSET_SFT 26 -+#define RG_TX_DIV_VSET_HI 27 -+#define RG_TX_DIV_VSET_SZ 2 -+#define RG_TX_LOBUF_VSET_MSK 0x30000000 -+#define RG_TX_LOBUF_VSET_I_MSK 0xcfffffff -+#define RG_TX_LOBUF_VSET_SFT 28 -+#define RG_TX_LOBUF_VSET_HI 29 -+#define RG_TX_LOBUF_VSET_SZ 2 -+#define RG_RX_SQDC_MSK 0x00000007 -+#define RG_RX_SQDC_I_MSK 0xfffffff8 -+#define RG_RX_SQDC_SFT 0 -+#define RG_RX_SQDC_HI 2 -+#define RG_RX_SQDC_SZ 3 -+#define RG_RX_DIV2_CORE_MSK 0x00000018 -+#define RG_RX_DIV2_CORE_I_MSK 0xffffffe7 -+#define RG_RX_DIV2_CORE_SFT 3 -+#define RG_RX_DIV2_CORE_HI 4 -+#define RG_RX_DIV2_CORE_SZ 2 -+#define RG_RX_LOBUF_MSK 0x00000060 -+#define RG_RX_LOBUF_I_MSK 0xffffff9f -+#define RG_RX_LOBUF_SFT 5 -+#define RG_RX_LOBUF_HI 6 -+#define RG_RX_LOBUF_SZ 2 -+#define RG_TX_DPDGM_BIAS_MSK 0x00000780 -+#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f -+#define RG_TX_DPDGM_BIAS_SFT 7 -+#define RG_TX_DPDGM_BIAS_HI 10 -+#define RG_TX_DPDGM_BIAS_SZ 4 -+#define RG_TX_DPD_DIV_MSK 0x00007800 -+#define RG_TX_DPD_DIV_I_MSK 0xffff87ff -+#define RG_TX_DPD_DIV_SFT 11 -+#define RG_TX_DPD_DIV_HI 14 -+#define RG_TX_DPD_DIV_SZ 4 -+#define RG_TX_TSSI_BIAS_MSK 0x00038000 -+#define RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff -+#define RG_TX_TSSI_BIAS_SFT 15 -+#define RG_TX_TSSI_BIAS_HI 17 -+#define RG_TX_TSSI_BIAS_SZ 3 -+#define RG_TX_TSSI_DIV_MSK 0x001c0000 -+#define RG_TX_TSSI_DIV_I_MSK 0xffe3ffff -+#define RG_TX_TSSI_DIV_SFT 18 -+#define RG_TX_TSSI_DIV_HI 20 -+#define RG_TX_TSSI_DIV_SZ 3 -+#define RG_TX_TSSI_TESTMODE_MSK 0x00200000 -+#define RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff -+#define RG_TX_TSSI_TESTMODE_SFT 21 -+#define RG_TX_TSSI_TESTMODE_HI 21 -+#define RG_TX_TSSI_TESTMODE_SZ 1 -+#define RG_TX_TSSI_TEST_MSK 0x00c00000 -+#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff -+#define RG_TX_TSSI_TEST_SFT 22 -+#define RG_TX_TSSI_TEST_HI 23 -+#define RG_TX_TSSI_TEST_SZ 2 -+#define RG_PACASCODE_CTRL_MSK 0x07000000 -+#define RG_PACASCODE_CTRL_I_MSK 0xf8ffffff -+#define RG_PACASCODE_CTRL_SFT 24 -+#define RG_PACASCODE_CTRL_HI 26 -+#define RG_PACASCODE_CTRL_SZ 3 -+#define RG_RX_HG_LNA_GC_MSK 0x00000003 -+#define RG_RX_HG_LNA_GC_I_MSK 0xfffffffc -+#define RG_RX_HG_LNA_GC_SFT 0 -+#define RG_RX_HG_LNA_GC_HI 1 -+#define RG_RX_HG_LNA_GC_SZ 2 -+#define RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c -+#define RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3 -+#define RG_RX_HG_LNAHGN_BIAS_SFT 2 -+#define RG_RX_HG_LNAHGN_BIAS_HI 5 -+#define RG_RX_HG_LNAHGN_BIAS_SZ 4 -+#define RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0 -+#define RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f -+#define RG_RX_HG_LNAHGP_BIAS_SFT 6 -+#define RG_RX_HG_LNAHGP_BIAS_HI 9 -+#define RG_RX_HG_LNAHGP_BIAS_SZ 4 -+#define RG_RX_HG_LNALG_BIAS_MSK 0x00003c00 -+#define RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff -+#define RG_RX_HG_LNALG_BIAS_SFT 10 -+#define RG_RX_HG_LNALG_BIAS_HI 13 -+#define RG_RX_HG_LNALG_BIAS_SZ 4 -+#define RG_RX_HG_TZ_GC_MSK 0x0000c000 -+#define RG_RX_HG_TZ_GC_I_MSK 0xffff3fff -+#define RG_RX_HG_TZ_GC_SFT 14 -+#define RG_RX_HG_TZ_GC_HI 15 -+#define RG_RX_HG_TZ_GC_SZ 2 -+#define RG_RX_HG_TZ_CAP_MSK 0x00070000 -+#define RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff -+#define RG_RX_HG_TZ_CAP_SFT 16 -+#define RG_RX_HG_TZ_CAP_HI 18 -+#define RG_RX_HG_TZ_CAP_SZ 3 -+#define RG_RX_MG_LNA_GC_MSK 0x00000003 -+#define RG_RX_MG_LNA_GC_I_MSK 0xfffffffc -+#define RG_RX_MG_LNA_GC_SFT 0 -+#define RG_RX_MG_LNA_GC_HI 1 -+#define RG_RX_MG_LNA_GC_SZ 2 -+#define RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c -+#define RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3 -+#define RG_RX_MG_LNAHGN_BIAS_SFT 2 -+#define RG_RX_MG_LNAHGN_BIAS_HI 5 -+#define RG_RX_MG_LNAHGN_BIAS_SZ 4 -+#define RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0 -+#define RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f -+#define RG_RX_MG_LNAHGP_BIAS_SFT 6 -+#define RG_RX_MG_LNAHGP_BIAS_HI 9 -+#define RG_RX_MG_LNAHGP_BIAS_SZ 4 -+#define RG_RX_MG_LNALG_BIAS_MSK 0x00003c00 -+#define RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff -+#define RG_RX_MG_LNALG_BIAS_SFT 10 -+#define RG_RX_MG_LNALG_BIAS_HI 13 -+#define RG_RX_MG_LNALG_BIAS_SZ 4 -+#define RG_RX_MG_TZ_GC_MSK 0x0000c000 -+#define RG_RX_MG_TZ_GC_I_MSK 0xffff3fff -+#define RG_RX_MG_TZ_GC_SFT 14 -+#define RG_RX_MG_TZ_GC_HI 15 -+#define RG_RX_MG_TZ_GC_SZ 2 -+#define RG_RX_MG_TZ_CAP_MSK 0x00070000 -+#define RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff -+#define RG_RX_MG_TZ_CAP_SFT 16 -+#define RG_RX_MG_TZ_CAP_HI 18 -+#define RG_RX_MG_TZ_CAP_SZ 3 -+#define RG_RX_LG_LNA_GC_MSK 0x00000003 -+#define RG_RX_LG_LNA_GC_I_MSK 0xfffffffc -+#define RG_RX_LG_LNA_GC_SFT 0 -+#define RG_RX_LG_LNA_GC_HI 1 -+#define RG_RX_LG_LNA_GC_SZ 2 -+#define RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c -+#define RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3 -+#define RG_RX_LG_LNAHGN_BIAS_SFT 2 -+#define RG_RX_LG_LNAHGN_BIAS_HI 5 -+#define RG_RX_LG_LNAHGN_BIAS_SZ 4 -+#define RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0 -+#define RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f -+#define RG_RX_LG_LNAHGP_BIAS_SFT 6 -+#define RG_RX_LG_LNAHGP_BIAS_HI 9 -+#define RG_RX_LG_LNAHGP_BIAS_SZ 4 -+#define RG_RX_LG_LNALG_BIAS_MSK 0x00003c00 -+#define RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff -+#define RG_RX_LG_LNALG_BIAS_SFT 10 -+#define RG_RX_LG_LNALG_BIAS_HI 13 -+#define RG_RX_LG_LNALG_BIAS_SZ 4 -+#define RG_RX_LG_TZ_GC_MSK 0x0000c000 -+#define RG_RX_LG_TZ_GC_I_MSK 0xffff3fff -+#define RG_RX_LG_TZ_GC_SFT 14 -+#define RG_RX_LG_TZ_GC_HI 15 -+#define RG_RX_LG_TZ_GC_SZ 2 -+#define RG_RX_LG_TZ_CAP_MSK 0x00070000 -+#define RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff -+#define RG_RX_LG_TZ_CAP_SFT 16 -+#define RG_RX_LG_TZ_CAP_HI 18 -+#define RG_RX_LG_TZ_CAP_SZ 3 -+#define RG_RX_ULG_LNA_GC_MSK 0x00000003 -+#define RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc -+#define RG_RX_ULG_LNA_GC_SFT 0 -+#define RG_RX_ULG_LNA_GC_HI 1 -+#define RG_RX_ULG_LNA_GC_SZ 2 -+#define RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c -+#define RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3 -+#define RG_RX_ULG_LNAHGN_BIAS_SFT 2 -+#define RG_RX_ULG_LNAHGN_BIAS_HI 5 -+#define RG_RX_ULG_LNAHGN_BIAS_SZ 4 -+#define RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0 -+#define RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f -+#define RG_RX_ULG_LNAHGP_BIAS_SFT 6 -+#define RG_RX_ULG_LNAHGP_BIAS_HI 9 -+#define RG_RX_ULG_LNAHGP_BIAS_SZ 4 -+#define RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00 -+#define RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff -+#define RG_RX_ULG_LNALG_BIAS_SFT 10 -+#define RG_RX_ULG_LNALG_BIAS_HI 13 -+#define RG_RX_ULG_LNALG_BIAS_SZ 4 -+#define RG_RX_ULG_TZ_GC_MSK 0x0000c000 -+#define RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff -+#define RG_RX_ULG_TZ_GC_SFT 14 -+#define RG_RX_ULG_TZ_GC_HI 15 -+#define RG_RX_ULG_TZ_GC_SZ 2 -+#define RG_RX_ULG_TZ_CAP_MSK 0x00070000 -+#define RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff -+#define RG_RX_ULG_TZ_CAP_SFT 16 -+#define RG_RX_ULG_TZ_CAP_HI 18 -+#define RG_RX_ULG_TZ_CAP_SZ 3 -+#define RG_HPF1_FAST_SET_X_MSK 0x00000001 -+#define RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe -+#define RG_HPF1_FAST_SET_X_SFT 0 -+#define RG_HPF1_FAST_SET_X_HI 0 -+#define RG_HPF1_FAST_SET_X_SZ 1 -+#define RG_HPF1_FAST_SET_Y_MSK 0x00000002 -+#define RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd -+#define RG_HPF1_FAST_SET_Y_SFT 1 -+#define RG_HPF1_FAST_SET_Y_HI 1 -+#define RG_HPF1_FAST_SET_Y_SZ 1 -+#define RG_HPF1_FAST_SET_Z_MSK 0x00000004 -+#define RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb -+#define RG_HPF1_FAST_SET_Z_SFT 2 -+#define RG_HPF1_FAST_SET_Z_HI 2 -+#define RG_HPF1_FAST_SET_Z_SZ 1 -+#define RG_HPF_T1A_MSK 0x00000018 -+#define RG_HPF_T1A_I_MSK 0xffffffe7 -+#define RG_HPF_T1A_SFT 3 -+#define RG_HPF_T1A_HI 4 -+#define RG_HPF_T1A_SZ 2 -+#define RG_HPF_T1B_MSK 0x00000060 -+#define RG_HPF_T1B_I_MSK 0xffffff9f -+#define RG_HPF_T1B_SFT 5 -+#define RG_HPF_T1B_HI 6 -+#define RG_HPF_T1B_SZ 2 -+#define RG_HPF_T1C_MSK 0x00000180 -+#define RG_HPF_T1C_I_MSK 0xfffffe7f -+#define RG_HPF_T1C_SFT 7 -+#define RG_HPF_T1C_HI 8 -+#define RG_HPF_T1C_SZ 2 -+#define RG_RX_LNA_TRI_SEL_MSK 0x00000600 -+#define RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff -+#define RG_RX_LNA_TRI_SEL_SFT 9 -+#define RG_RX_LNA_TRI_SEL_HI 10 -+#define RG_RX_LNA_TRI_SEL_SZ 2 -+#define RG_RX_LNA_SETTLE_MSK 0x00001800 -+#define RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff -+#define RG_RX_LNA_SETTLE_SFT 11 -+#define RG_RX_LNA_SETTLE_HI 12 -+#define RG_RX_LNA_SETTLE_SZ 2 -+#define RG_TXGAIN_PHYCTRL_MSK 0x00002000 -+#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffdfff -+#define RG_TXGAIN_PHYCTRL_SFT 13 -+#define RG_TXGAIN_PHYCTRL_HI 13 -+#define RG_TXGAIN_PHYCTRL_SZ 1 -+#define RG_TX_GAIN_MSK 0x003fc000 -+#define RG_TX_GAIN_I_MSK 0xffc03fff -+#define RG_TX_GAIN_SFT 14 -+#define RG_TX_GAIN_HI 21 -+#define RG_TX_GAIN_SZ 8 -+#define RG_TXGAIN_MANUAL_MSK 0x00400000 -+#define RG_TXGAIN_MANUAL_I_MSK 0xffbfffff -+#define RG_TXGAIN_MANUAL_SFT 22 -+#define RG_TXGAIN_MANUAL_HI 22 -+#define RG_TXGAIN_MANUAL_SZ 1 -+#define RG_TX_GAIN_OFFSET_MSK 0x07800000 -+#define RG_TX_GAIN_OFFSET_I_MSK 0xf87fffff -+#define RG_TX_GAIN_OFFSET_SFT 23 -+#define RG_TX_GAIN_OFFSET_HI 26 -+#define RG_TX_GAIN_OFFSET_SZ 4 -+#define RG_ADC_CLKSEL_MSK 0x00000001 -+#define RG_ADC_CLKSEL_I_MSK 0xfffffffe -+#define RG_ADC_CLKSEL_SFT 0 -+#define RG_ADC_CLKSEL_HI 0 -+#define RG_ADC_CLKSEL_SZ 1 -+#define RG_ADC_DIBIAS_MSK 0x00000006 -+#define RG_ADC_DIBIAS_I_MSK 0xfffffff9 -+#define RG_ADC_DIBIAS_SFT 1 -+#define RG_ADC_DIBIAS_HI 2 -+#define RG_ADC_DIBIAS_SZ 2 -+#define RG_ADC_DIVR_MSK 0x00000008 -+#define RG_ADC_DIVR_I_MSK 0xfffffff7 -+#define RG_ADC_DIVR_SFT 3 -+#define RG_ADC_DIVR_HI 3 -+#define RG_ADC_DIVR_SZ 1 -+#define RG_ADC_DVCMI_MSK 0x00000030 -+#define RG_ADC_DVCMI_I_MSK 0xffffffcf -+#define RG_ADC_DVCMI_SFT 4 -+#define RG_ADC_DVCMI_HI 5 -+#define RG_ADC_DVCMI_SZ 2 -+#define RG_ADC_SAMSEL_MSK 0x000003c0 -+#define RG_ADC_SAMSEL_I_MSK 0xfffffc3f -+#define RG_ADC_SAMSEL_SFT 6 -+#define RG_ADC_SAMSEL_HI 9 -+#define RG_ADC_SAMSEL_SZ 4 -+#define RG_ADC_STNBY_MSK 0x00000400 -+#define RG_ADC_STNBY_I_MSK 0xfffffbff -+#define RG_ADC_STNBY_SFT 10 -+#define RG_ADC_STNBY_HI 10 -+#define RG_ADC_STNBY_SZ 1 -+#define RG_ADC_TESTMODE_MSK 0x00000800 -+#define RG_ADC_TESTMODE_I_MSK 0xfffff7ff -+#define RG_ADC_TESTMODE_SFT 11 -+#define RG_ADC_TESTMODE_HI 11 -+#define RG_ADC_TESTMODE_SZ 1 -+#define RG_ADC_TSEL_MSK 0x0000f000 -+#define RG_ADC_TSEL_I_MSK 0xffff0fff -+#define RG_ADC_TSEL_SFT 12 -+#define RG_ADC_TSEL_HI 15 -+#define RG_ADC_TSEL_SZ 4 -+#define RG_ADC_VRSEL_MSK 0x00030000 -+#define RG_ADC_VRSEL_I_MSK 0xfffcffff -+#define RG_ADC_VRSEL_SFT 16 -+#define RG_ADC_VRSEL_HI 17 -+#define RG_ADC_VRSEL_SZ 2 -+#define RG_DICMP_MSK 0x000c0000 -+#define RG_DICMP_I_MSK 0xfff3ffff -+#define RG_DICMP_SFT 18 -+#define RG_DICMP_HI 19 -+#define RG_DICMP_SZ 2 -+#define RG_DIOP_MSK 0x00300000 -+#define RG_DIOP_I_MSK 0xffcfffff -+#define RG_DIOP_SFT 20 -+#define RG_DIOP_HI 21 -+#define RG_DIOP_SZ 2 -+#define RG_SARADC_VRSEL_MSK 0x00c00000 -+#define RG_SARADC_VRSEL_I_MSK 0xff3fffff -+#define RG_SARADC_VRSEL_SFT 22 -+#define RG_SARADC_VRSEL_HI 23 -+#define RG_SARADC_VRSEL_SZ 2 -+#define RG_EN_SAR_TEST_MSK 0x03000000 -+#define RG_EN_SAR_TEST_I_MSK 0xfcffffff -+#define RG_EN_SAR_TEST_SFT 24 -+#define RG_EN_SAR_TEST_HI 25 -+#define RG_EN_SAR_TEST_SZ 2 -+#define RG_SARADC_THERMAL_MSK 0x04000000 -+#define RG_SARADC_THERMAL_I_MSK 0xfbffffff -+#define RG_SARADC_THERMAL_SFT 26 -+#define RG_SARADC_THERMAL_HI 26 -+#define RG_SARADC_THERMAL_SZ 1 -+#define RG_SARADC_TSSI_MSK 0x08000000 -+#define RG_SARADC_TSSI_I_MSK 0xf7ffffff -+#define RG_SARADC_TSSI_SFT 27 -+#define RG_SARADC_TSSI_HI 27 -+#define RG_SARADC_TSSI_SZ 1 -+#define RG_CLK_SAR_SEL_MSK 0x30000000 -+#define RG_CLK_SAR_SEL_I_MSK 0xcfffffff -+#define RG_CLK_SAR_SEL_SFT 28 -+#define RG_CLK_SAR_SEL_HI 29 -+#define RG_CLK_SAR_SEL_SZ 2 -+#define RG_EN_SARADC_MSK 0x40000000 -+#define RG_EN_SARADC_I_MSK 0xbfffffff -+#define RG_EN_SARADC_SFT 30 -+#define RG_EN_SARADC_HI 30 -+#define RG_EN_SARADC_SZ 1 -+#define RG_DACI1ST_MSK 0x00000003 -+#define RG_DACI1ST_I_MSK 0xfffffffc -+#define RG_DACI1ST_SFT 0 -+#define RG_DACI1ST_HI 1 -+#define RG_DACI1ST_SZ 2 -+#define RG_TX_DACLPF_ICOURSE_MSK 0x0000000c -+#define RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3 -+#define RG_TX_DACLPF_ICOURSE_SFT 2 -+#define RG_TX_DACLPF_ICOURSE_HI 3 -+#define RG_TX_DACLPF_ICOURSE_SZ 2 -+#define RG_TX_DACLPF_IFINE_MSK 0x00000030 -+#define RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf -+#define RG_TX_DACLPF_IFINE_SFT 4 -+#define RG_TX_DACLPF_IFINE_HI 5 -+#define RG_TX_DACLPF_IFINE_SZ 2 -+#define RG_TX_DACLPF_VCM_MSK 0x000000c0 -+#define RG_TX_DACLPF_VCM_I_MSK 0xffffff3f -+#define RG_TX_DACLPF_VCM_SFT 6 -+#define RG_TX_DACLPF_VCM_HI 7 -+#define RG_TX_DACLPF_VCM_SZ 2 -+#define RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100 -+#define RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff -+#define RG_TX_DAC_CKEDGE_SEL_SFT 8 -+#define RG_TX_DAC_CKEDGE_SEL_HI 8 -+#define RG_TX_DAC_CKEDGE_SEL_SZ 1 -+#define RG_TX_DAC_IBIAS_MSK 0x00000600 -+#define RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff -+#define RG_TX_DAC_IBIAS_SFT 9 -+#define RG_TX_DAC_IBIAS_HI 10 -+#define RG_TX_DAC_IBIAS_SZ 2 -+#define RG_TX_DAC_OS_MSK 0x00003800 -+#define RG_TX_DAC_OS_I_MSK 0xffffc7ff -+#define RG_TX_DAC_OS_SFT 11 -+#define RG_TX_DAC_OS_HI 13 -+#define RG_TX_DAC_OS_SZ 3 -+#define RG_TX_DAC_RCAL_MSK 0x0000c000 -+#define RG_TX_DAC_RCAL_I_MSK 0xffff3fff -+#define RG_TX_DAC_RCAL_SFT 14 -+#define RG_TX_DAC_RCAL_HI 15 -+#define RG_TX_DAC_RCAL_SZ 2 -+#define RG_TX_DAC_TSEL_MSK 0x000f0000 -+#define RG_TX_DAC_TSEL_I_MSK 0xfff0ffff -+#define RG_TX_DAC_TSEL_SFT 16 -+#define RG_TX_DAC_TSEL_HI 19 -+#define RG_TX_DAC_TSEL_SZ 4 -+#define RG_TX_EN_VOLTAGE_IN_MSK 0x00100000 -+#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff -+#define RG_TX_EN_VOLTAGE_IN_SFT 20 -+#define RG_TX_EN_VOLTAGE_IN_HI 20 -+#define RG_TX_EN_VOLTAGE_IN_SZ 1 -+#define RG_TXLPF_BYPASS_MSK 0x00200000 -+#define RG_TXLPF_BYPASS_I_MSK 0xffdfffff -+#define RG_TXLPF_BYPASS_SFT 21 -+#define RG_TXLPF_BYPASS_HI 21 -+#define RG_TXLPF_BYPASS_SZ 1 -+#define RG_TXLPF_BOOSTI_MSK 0x00400000 -+#define RG_TXLPF_BOOSTI_I_MSK 0xffbfffff -+#define RG_TXLPF_BOOSTI_SFT 22 -+#define RG_TXLPF_BOOSTI_HI 22 -+#define RG_TXLPF_BOOSTI_SZ 1 -+#define RG_TX_DAC_IOFFSET_MSK 0x07800000 -+#define RG_TX_DAC_IOFFSET_I_MSK 0xf87fffff -+#define RG_TX_DAC_IOFFSET_SFT 23 -+#define RG_TX_DAC_IOFFSET_HI 26 -+#define RG_TX_DAC_IOFFSET_SZ 4 -+#define RG_TX_DAC_QOFFSET_MSK 0x78000000 -+#define RG_TX_DAC_QOFFSET_I_MSK 0x87ffffff -+#define RG_TX_DAC_QOFFSET_SFT 27 -+#define RG_TX_DAC_QOFFSET_HI 30 -+#define RG_TX_DAC_QOFFSET_SZ 4 -+#define RG_EN_SX_R3_MSK 0x00000001 -+#define RG_EN_SX_R3_I_MSK 0xfffffffe -+#define RG_EN_SX_R3_SFT 0 -+#define RG_EN_SX_R3_HI 0 -+#define RG_EN_SX_R3_SZ 1 -+#define RG_EN_SX_CH_MSK 0x00000002 -+#define RG_EN_SX_CH_I_MSK 0xfffffffd -+#define RG_EN_SX_CH_SFT 1 -+#define RG_EN_SX_CH_HI 1 -+#define RG_EN_SX_CH_SZ 1 -+#define RG_EN_SX_CHP_MSK 0x00000004 -+#define RG_EN_SX_CHP_I_MSK 0xfffffffb -+#define RG_EN_SX_CHP_SFT 2 -+#define RG_EN_SX_CHP_HI 2 -+#define RG_EN_SX_CHP_SZ 1 -+#define RG_EN_SX_DIVCK_MSK 0x00000008 -+#define RG_EN_SX_DIVCK_I_MSK 0xfffffff7 -+#define RG_EN_SX_DIVCK_SFT 3 -+#define RG_EN_SX_DIVCK_HI 3 -+#define RG_EN_SX_DIVCK_SZ 1 -+#define RG_EN_SX_VCOBF_MSK 0x00000010 -+#define RG_EN_SX_VCOBF_I_MSK 0xffffffef -+#define RG_EN_SX_VCOBF_SFT 4 -+#define RG_EN_SX_VCOBF_HI 4 -+#define RG_EN_SX_VCOBF_SZ 1 -+#define RG_EN_SX_VCO_MSK 0x00000020 -+#define RG_EN_SX_VCO_I_MSK 0xffffffdf -+#define RG_EN_SX_VCO_SFT 5 -+#define RG_EN_SX_VCO_HI 5 -+#define RG_EN_SX_VCO_SZ 1 -+#define RG_EN_SX_MOD_MSK 0x00000040 -+#define RG_EN_SX_MOD_I_MSK 0xffffffbf -+#define RG_EN_SX_MOD_SFT 6 -+#define RG_EN_SX_MOD_HI 6 -+#define RG_EN_SX_MOD_SZ 1 -+#define RG_EN_SX_DITHER_MSK 0x00000100 -+#define RG_EN_SX_DITHER_I_MSK 0xfffffeff -+#define RG_EN_SX_DITHER_SFT 8 -+#define RG_EN_SX_DITHER_HI 8 -+#define RG_EN_SX_DITHER_SZ 1 -+#define RG_EN_SX_VT_MON_MSK 0x00000800 -+#define RG_EN_SX_VT_MON_I_MSK 0xfffff7ff -+#define RG_EN_SX_VT_MON_SFT 11 -+#define RG_EN_SX_VT_MON_HI 11 -+#define RG_EN_SX_VT_MON_SZ 1 -+#define RG_EN_SX_VT_MON_DG_MSK 0x00001000 -+#define RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff -+#define RG_EN_SX_VT_MON_DG_SFT 12 -+#define RG_EN_SX_VT_MON_DG_HI 12 -+#define RG_EN_SX_VT_MON_DG_SZ 1 -+#define RG_EN_SX_DIV_MSK 0x00002000 -+#define RG_EN_SX_DIV_I_MSK 0xffffdfff -+#define RG_EN_SX_DIV_SFT 13 -+#define RG_EN_SX_DIV_HI 13 -+#define RG_EN_SX_DIV_SZ 1 -+#define RG_EN_SX_LPF_MSK 0x00004000 -+#define RG_EN_SX_LPF_I_MSK 0xffffbfff -+#define RG_EN_SX_LPF_SFT 14 -+#define RG_EN_SX_LPF_HI 14 -+#define RG_EN_SX_LPF_SZ 1 -+#define RG_EN_DPL_MOD_MSK 0x00008000 -+#define RG_EN_DPL_MOD_I_MSK 0xffff7fff -+#define RG_EN_DPL_MOD_SFT 15 -+#define RG_EN_DPL_MOD_HI 15 -+#define RG_EN_DPL_MOD_SZ 1 -+#define RG_DPL_MOD_ORDER_MSK 0x00030000 -+#define RG_DPL_MOD_ORDER_I_MSK 0xfffcffff -+#define RG_DPL_MOD_ORDER_SFT 16 -+#define RG_DPL_MOD_ORDER_HI 17 -+#define RG_DPL_MOD_ORDER_SZ 2 -+#define RG_SX_RFCTRL_F_MSK 0x00ffffff -+#define RG_SX_RFCTRL_F_I_MSK 0xff000000 -+#define RG_SX_RFCTRL_F_SFT 0 -+#define RG_SX_RFCTRL_F_HI 23 -+#define RG_SX_RFCTRL_F_SZ 24 -+#define RG_SX_SEL_CP_MSK 0x0f000000 -+#define RG_SX_SEL_CP_I_MSK 0xf0ffffff -+#define RG_SX_SEL_CP_SFT 24 -+#define RG_SX_SEL_CP_HI 27 -+#define RG_SX_SEL_CP_SZ 4 -+#define RG_SX_SEL_CS_MSK 0xf0000000 -+#define RG_SX_SEL_CS_I_MSK 0x0fffffff -+#define RG_SX_SEL_CS_SFT 28 -+#define RG_SX_SEL_CS_HI 31 -+#define RG_SX_SEL_CS_SZ 4 -+#define RG_SX_RFCTRL_CH_MSK 0x000007ff -+#define RG_SX_RFCTRL_CH_I_MSK 0xfffff800 -+#define RG_SX_RFCTRL_CH_SFT 0 -+#define RG_SX_RFCTRL_CH_HI 10 -+#define RG_SX_RFCTRL_CH_SZ 11 -+#define RG_SX_SEL_C3_MSK 0x00007800 -+#define RG_SX_SEL_C3_I_MSK 0xffff87ff -+#define RG_SX_SEL_C3_SFT 11 -+#define RG_SX_SEL_C3_HI 14 -+#define RG_SX_SEL_C3_SZ 4 -+#define RG_SX_SEL_RS_MSK 0x000f8000 -+#define RG_SX_SEL_RS_I_MSK 0xfff07fff -+#define RG_SX_SEL_RS_SFT 15 -+#define RG_SX_SEL_RS_HI 19 -+#define RG_SX_SEL_RS_SZ 5 -+#define RG_SX_SEL_R3_MSK 0x01f00000 -+#define RG_SX_SEL_R3_I_MSK 0xfe0fffff -+#define RG_SX_SEL_R3_SFT 20 -+#define RG_SX_SEL_R3_HI 24 -+#define RG_SX_SEL_R3_SZ 5 -+#define RG_SX_SEL_ICHP_MSK 0x0000001f -+#define RG_SX_SEL_ICHP_I_MSK 0xffffffe0 -+#define RG_SX_SEL_ICHP_SFT 0 -+#define RG_SX_SEL_ICHP_HI 4 -+#define RG_SX_SEL_ICHP_SZ 5 -+#define RG_SX_SEL_PCHP_MSK 0x000003e0 -+#define RG_SX_SEL_PCHP_I_MSK 0xfffffc1f -+#define RG_SX_SEL_PCHP_SFT 5 -+#define RG_SX_SEL_PCHP_HI 9 -+#define RG_SX_SEL_PCHP_SZ 5 -+#define RG_SX_SEL_CHP_REGOP_MSK 0x00003c00 -+#define RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff -+#define RG_SX_SEL_CHP_REGOP_SFT 10 -+#define RG_SX_SEL_CHP_REGOP_HI 13 -+#define RG_SX_SEL_CHP_REGOP_SZ 4 -+#define RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000 -+#define RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff -+#define RG_SX_SEL_CHP_UNIOP_SFT 14 -+#define RG_SX_SEL_CHP_UNIOP_HI 17 -+#define RG_SX_SEL_CHP_UNIOP_SZ 4 -+#define RG_SX_CHP_IOST_POL_MSK 0x00040000 -+#define RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff -+#define RG_SX_CHP_IOST_POL_SFT 18 -+#define RG_SX_CHP_IOST_POL_HI 18 -+#define RG_SX_CHP_IOST_POL_SZ 1 -+#define RG_SX_CHP_IOST_MSK 0x00380000 -+#define RG_SX_CHP_IOST_I_MSK 0xffc7ffff -+#define RG_SX_CHP_IOST_SFT 19 -+#define RG_SX_CHP_IOST_HI 21 -+#define RG_SX_CHP_IOST_SZ 3 -+#define RG_SX_PFDSEL_MSK 0x00400000 -+#define RG_SX_PFDSEL_I_MSK 0xffbfffff -+#define RG_SX_PFDSEL_SFT 22 -+#define RG_SX_PFDSEL_HI 22 -+#define RG_SX_PFDSEL_SZ 1 -+#define RG_SX_PFD_SET_MSK 0x00800000 -+#define RG_SX_PFD_SET_I_MSK 0xff7fffff -+#define RG_SX_PFD_SET_SFT 23 -+#define RG_SX_PFD_SET_HI 23 -+#define RG_SX_PFD_SET_SZ 1 -+#define RG_SX_PFD_SET1_MSK 0x01000000 -+#define RG_SX_PFD_SET1_I_MSK 0xfeffffff -+#define RG_SX_PFD_SET1_SFT 24 -+#define RG_SX_PFD_SET1_HI 24 -+#define RG_SX_PFD_SET1_SZ 1 -+#define RG_SX_PFD_SET2_MSK 0x02000000 -+#define RG_SX_PFD_SET2_I_MSK 0xfdffffff -+#define RG_SX_PFD_SET2_SFT 25 -+#define RG_SX_PFD_SET2_HI 25 -+#define RG_SX_PFD_SET2_SZ 1 -+#define RG_SX_VBNCAS_SEL_MSK 0x04000000 -+#define RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff -+#define RG_SX_VBNCAS_SEL_SFT 26 -+#define RG_SX_VBNCAS_SEL_HI 26 -+#define RG_SX_VBNCAS_SEL_SZ 1 -+#define RG_SX_PFD_RST_H_MSK 0x08000000 -+#define RG_SX_PFD_RST_H_I_MSK 0xf7ffffff -+#define RG_SX_PFD_RST_H_SFT 27 -+#define RG_SX_PFD_RST_H_HI 27 -+#define RG_SX_PFD_RST_H_SZ 1 -+#define RG_SX_PFD_TRUP_MSK 0x10000000 -+#define RG_SX_PFD_TRUP_I_MSK 0xefffffff -+#define RG_SX_PFD_TRUP_SFT 28 -+#define RG_SX_PFD_TRUP_HI 28 -+#define RG_SX_PFD_TRUP_SZ 1 -+#define RG_SX_PFD_TRDN_MSK 0x20000000 -+#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff -+#define RG_SX_PFD_TRDN_SFT 29 -+#define RG_SX_PFD_TRDN_HI 29 -+#define RG_SX_PFD_TRDN_SZ 1 -+#define RG_SX_PFD_TRSEL_MSK 0x40000000 -+#define RG_SX_PFD_TRSEL_I_MSK 0xbfffffff -+#define RG_SX_PFD_TRSEL_SFT 30 -+#define RG_SX_PFD_TRSEL_HI 30 -+#define RG_SX_PFD_TRSEL_SZ 1 -+#define RG_SX_VCOBA_R_MSK 0x00000007 -+#define RG_SX_VCOBA_R_I_MSK 0xfffffff8 -+#define RG_SX_VCOBA_R_SFT 0 -+#define RG_SX_VCOBA_R_HI 2 -+#define RG_SX_VCOBA_R_SZ 3 -+#define RG_SX_VCORSEL_MSK 0x000000f8 -+#define RG_SX_VCORSEL_I_MSK 0xffffff07 -+#define RG_SX_VCORSEL_SFT 3 -+#define RG_SX_VCORSEL_HI 7 -+#define RG_SX_VCORSEL_SZ 5 -+#define RG_SX_VCOCUSEL_MSK 0x00000f00 -+#define RG_SX_VCOCUSEL_I_MSK 0xfffff0ff -+#define RG_SX_VCOCUSEL_SFT 8 -+#define RG_SX_VCOCUSEL_HI 11 -+#define RG_SX_VCOCUSEL_SZ 4 -+#define RG_SX_RXBFSEL_MSK 0x0000f000 -+#define RG_SX_RXBFSEL_I_MSK 0xffff0fff -+#define RG_SX_RXBFSEL_SFT 12 -+#define RG_SX_RXBFSEL_HI 15 -+#define RG_SX_RXBFSEL_SZ 4 -+#define RG_SX_TXBFSEL_MSK 0x000f0000 -+#define RG_SX_TXBFSEL_I_MSK 0xfff0ffff -+#define RG_SX_TXBFSEL_SFT 16 -+#define RG_SX_TXBFSEL_HI 19 -+#define RG_SX_TXBFSEL_SZ 4 -+#define RG_SX_VCOBFSEL_MSK 0x00f00000 -+#define RG_SX_VCOBFSEL_I_MSK 0xff0fffff -+#define RG_SX_VCOBFSEL_SFT 20 -+#define RG_SX_VCOBFSEL_HI 23 -+#define RG_SX_VCOBFSEL_SZ 4 -+#define RG_SX_DIVBFSEL_MSK 0x0f000000 -+#define RG_SX_DIVBFSEL_I_MSK 0xf0ffffff -+#define RG_SX_DIVBFSEL_SFT 24 -+#define RG_SX_DIVBFSEL_HI 27 -+#define RG_SX_DIVBFSEL_SZ 4 -+#define RG_SX_GNDR_SEL_MSK 0xf0000000 -+#define RG_SX_GNDR_SEL_I_MSK 0x0fffffff -+#define RG_SX_GNDR_SEL_SFT 28 -+#define RG_SX_GNDR_SEL_HI 31 -+#define RG_SX_GNDR_SEL_SZ 4 -+#define RG_SX_DITHER_WEIGHT_MSK 0x00000003 -+#define RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc -+#define RG_SX_DITHER_WEIGHT_SFT 0 -+#define RG_SX_DITHER_WEIGHT_HI 1 -+#define RG_SX_DITHER_WEIGHT_SZ 2 -+#define RG_SX_MOD_ORDER_MSK 0x00000030 -+#define RG_SX_MOD_ORDER_I_MSK 0xffffffcf -+#define RG_SX_MOD_ORDER_SFT 4 -+#define RG_SX_MOD_ORDER_HI 5 -+#define RG_SX_MOD_ORDER_SZ 2 -+#define RG_SX_RST_H_DIV_MSK 0x00000200 -+#define RG_SX_RST_H_DIV_I_MSK 0xfffffdff -+#define RG_SX_RST_H_DIV_SFT 9 -+#define RG_SX_RST_H_DIV_HI 9 -+#define RG_SX_RST_H_DIV_SZ 1 -+#define RG_SX_SDM_EDGE_MSK 0x00000400 -+#define RG_SX_SDM_EDGE_I_MSK 0xfffffbff -+#define RG_SX_SDM_EDGE_SFT 10 -+#define RG_SX_SDM_EDGE_HI 10 -+#define RG_SX_SDM_EDGE_SZ 1 -+#define RG_SX_XO_GM_MSK 0x00001800 -+#define RG_SX_XO_GM_I_MSK 0xffffe7ff -+#define RG_SX_XO_GM_SFT 11 -+#define RG_SX_XO_GM_HI 12 -+#define RG_SX_XO_GM_SZ 2 -+#define RG_SX_REFBYTWO_MSK 0x00002000 -+#define RG_SX_REFBYTWO_I_MSK 0xffffdfff -+#define RG_SX_REFBYTWO_SFT 13 -+#define RG_SX_REFBYTWO_HI 13 -+#define RG_SX_REFBYTWO_SZ 1 -+#define RG_SX_LCKEN_MSK 0x00080000 -+#define RG_SX_LCKEN_I_MSK 0xfff7ffff -+#define RG_SX_LCKEN_SFT 19 -+#define RG_SX_LCKEN_HI 19 -+#define RG_SX_LCKEN_SZ 1 -+#define RG_SX_PREVDD_MSK 0x00f00000 -+#define RG_SX_PREVDD_I_MSK 0xff0fffff -+#define RG_SX_PREVDD_SFT 20 -+#define RG_SX_PREVDD_HI 23 -+#define RG_SX_PREVDD_SZ 4 -+#define RG_SX_PSCONTERVDD_MSK 0x0f000000 -+#define RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff -+#define RG_SX_PSCONTERVDD_SFT 24 -+#define RG_SX_PSCONTERVDD_HI 27 -+#define RG_SX_PSCONTERVDD_SZ 4 -+#define RG_SX_PH_MSK 0x00002000 -+#define RG_SX_PH_I_MSK 0xffffdfff -+#define RG_SX_PH_SFT 13 -+#define RG_SX_PH_HI 13 -+#define RG_SX_PH_SZ 1 -+#define RG_SX_PL_MSK 0x00004000 -+#define RG_SX_PL_I_MSK 0xffffbfff -+#define RG_SX_PL_SFT 14 -+#define RG_SX_PL_HI 14 -+#define RG_SX_PL_SZ 1 -+#define RG_XOSC_CBANK_XO_MSK 0x00078000 -+#define RG_XOSC_CBANK_XO_I_MSK 0xfff87fff -+#define RG_XOSC_CBANK_XO_SFT 15 -+#define RG_XOSC_CBANK_XO_HI 18 -+#define RG_XOSC_CBANK_XO_SZ 4 -+#define RG_XOSC_CBANK_XI_MSK 0x00780000 -+#define RG_XOSC_CBANK_XI_I_MSK 0xff87ffff -+#define RG_XOSC_CBANK_XI_SFT 19 -+#define RG_XOSC_CBANK_XI_HI 22 -+#define RG_XOSC_CBANK_XI_SZ 4 -+#define RG_SX_VT_MON_MODE_MSK 0x00000001 -+#define RG_SX_VT_MON_MODE_I_MSK 0xfffffffe -+#define RG_SX_VT_MON_MODE_SFT 0 -+#define RG_SX_VT_MON_MODE_HI 0 -+#define RG_SX_VT_MON_MODE_SZ 1 -+#define RG_SX_VT_TH_HI_MSK 0x00000006 -+#define RG_SX_VT_TH_HI_I_MSK 0xfffffff9 -+#define RG_SX_VT_TH_HI_SFT 1 -+#define RG_SX_VT_TH_HI_HI 2 -+#define RG_SX_VT_TH_HI_SZ 2 -+#define RG_SX_VT_TH_LO_MSK 0x00000018 -+#define RG_SX_VT_TH_LO_I_MSK 0xffffffe7 -+#define RG_SX_VT_TH_LO_SFT 3 -+#define RG_SX_VT_TH_LO_HI 4 -+#define RG_SX_VT_TH_LO_SZ 2 -+#define RG_SX_VT_SET_MSK 0x00000020 -+#define RG_SX_VT_SET_I_MSK 0xffffffdf -+#define RG_SX_VT_SET_SFT 5 -+#define RG_SX_VT_SET_HI 5 -+#define RG_SX_VT_SET_SZ 1 -+#define RG_SX_VT_MON_TMR_MSK 0x00007fc0 -+#define RG_SX_VT_MON_TMR_I_MSK 0xffff803f -+#define RG_SX_VT_MON_TMR_SFT 6 -+#define RG_SX_VT_MON_TMR_HI 14 -+#define RG_SX_VT_MON_TMR_SZ 9 -+#define RG_EN_DP_VT_MON_MSK 0x00000001 -+#define RG_EN_DP_VT_MON_I_MSK 0xfffffffe -+#define RG_EN_DP_VT_MON_SFT 0 -+#define RG_EN_DP_VT_MON_HI 0 -+#define RG_EN_DP_VT_MON_SZ 1 -+#define RG_DP_VT_TH_HI_MSK 0x00000006 -+#define RG_DP_VT_TH_HI_I_MSK 0xfffffff9 -+#define RG_DP_VT_TH_HI_SFT 1 -+#define RG_DP_VT_TH_HI_HI 2 -+#define RG_DP_VT_TH_HI_SZ 2 -+#define RG_DP_VT_TH_LO_MSK 0x00000018 -+#define RG_DP_VT_TH_LO_I_MSK 0xffffffe7 -+#define RG_DP_VT_TH_LO_SFT 3 -+#define RG_DP_VT_TH_LO_HI 4 -+#define RG_DP_VT_TH_LO_SZ 2 -+#define RG_DP_CK320BY2_MSK 0x00004000 -+#define RG_DP_CK320BY2_I_MSK 0xffffbfff -+#define RG_DP_CK320BY2_SFT 14 -+#define RG_DP_CK320BY2_HI 14 -+#define RG_DP_CK320BY2_SZ 1 -+#define RG_DP_OD_TEST_MSK 0x00200000 -+#define RG_DP_OD_TEST_I_MSK 0xffdfffff -+#define RG_DP_OD_TEST_SFT 21 -+#define RG_DP_OD_TEST_HI 21 -+#define RG_DP_OD_TEST_SZ 1 -+#define RG_DP_BBPLL_BP_MSK 0x00000001 -+#define RG_DP_BBPLL_BP_I_MSK 0xfffffffe -+#define RG_DP_BBPLL_BP_SFT 0 -+#define RG_DP_BBPLL_BP_HI 0 -+#define RG_DP_BBPLL_BP_SZ 1 -+#define RG_DP_BBPLL_ICP_MSK 0x00000006 -+#define RG_DP_BBPLL_ICP_I_MSK 0xfffffff9 -+#define RG_DP_BBPLL_ICP_SFT 1 -+#define RG_DP_BBPLL_ICP_HI 2 -+#define RG_DP_BBPLL_ICP_SZ 2 -+#define RG_DP_BBPLL_IDUAL_MSK 0x00000018 -+#define RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7 -+#define RG_DP_BBPLL_IDUAL_SFT 3 -+#define RG_DP_BBPLL_IDUAL_HI 4 -+#define RG_DP_BBPLL_IDUAL_SZ 2 -+#define RG_DP_BBPLL_OD_TEST_MSK 0x000001e0 -+#define RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f -+#define RG_DP_BBPLL_OD_TEST_SFT 5 -+#define RG_DP_BBPLL_OD_TEST_HI 8 -+#define RG_DP_BBPLL_OD_TEST_SZ 4 -+#define RG_DP_BBPLL_PD_MSK 0x00000200 -+#define RG_DP_BBPLL_PD_I_MSK 0xfffffdff -+#define RG_DP_BBPLL_PD_SFT 9 -+#define RG_DP_BBPLL_PD_HI 9 -+#define RG_DP_BBPLL_PD_SZ 1 -+#define RG_DP_BBPLL_TESTSEL_MSK 0x00001c00 -+#define RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff -+#define RG_DP_BBPLL_TESTSEL_SFT 10 -+#define RG_DP_BBPLL_TESTSEL_HI 12 -+#define RG_DP_BBPLL_TESTSEL_SZ 3 -+#define RG_DP_BBPLL_PFD_DLY_MSK 0x00006000 -+#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff -+#define RG_DP_BBPLL_PFD_DLY_SFT 13 -+#define RG_DP_BBPLL_PFD_DLY_HI 14 -+#define RG_DP_BBPLL_PFD_DLY_SZ 2 -+#define RG_DP_RP_MSK 0x00038000 -+#define RG_DP_RP_I_MSK 0xfffc7fff -+#define RG_DP_RP_SFT 15 -+#define RG_DP_RP_HI 17 -+#define RG_DP_RP_SZ 3 -+#define RG_DP_RHP_MSK 0x000c0000 -+#define RG_DP_RHP_I_MSK 0xfff3ffff -+#define RG_DP_RHP_SFT 18 -+#define RG_DP_RHP_HI 19 -+#define RG_DP_RHP_SZ 2 -+#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000 -+#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff -+#define RG_DP_BBPLL_SDM_EDGE_SFT 31 -+#define RG_DP_BBPLL_SDM_EDGE_HI 31 -+#define RG_DP_BBPLL_SDM_EDGE_SZ 1 -+#define RG_DP_FODIV_MSK 0x0007f000 -+#define RG_DP_FODIV_I_MSK 0xfff80fff -+#define RG_DP_FODIV_SFT 12 -+#define RG_DP_FODIV_HI 18 -+#define RG_DP_FODIV_SZ 7 -+#define RG_DP_REFDIV_MSK 0x1fc00000 -+#define RG_DP_REFDIV_I_MSK 0xe03fffff -+#define RG_DP_REFDIV_SFT 22 -+#define RG_DP_REFDIV_HI 28 -+#define RG_DP_REFDIV_SZ 7 -+#define RG_IDACAI_PGAG15_MSK 0x0000003f -+#define RG_IDACAI_PGAG15_I_MSK 0xffffffc0 -+#define RG_IDACAI_PGAG15_SFT 0 -+#define RG_IDACAI_PGAG15_HI 5 -+#define RG_IDACAI_PGAG15_SZ 6 -+#define RG_IDACAQ_PGAG15_MSK 0x00000fc0 -+#define RG_IDACAQ_PGAG15_I_MSK 0xfffff03f -+#define RG_IDACAQ_PGAG15_SFT 6 -+#define RG_IDACAQ_PGAG15_HI 11 -+#define RG_IDACAQ_PGAG15_SZ 6 -+#define RG_IDACAI_PGAG14_MSK 0x0003f000 -+#define RG_IDACAI_PGAG14_I_MSK 0xfffc0fff -+#define RG_IDACAI_PGAG14_SFT 12 -+#define RG_IDACAI_PGAG14_HI 17 -+#define RG_IDACAI_PGAG14_SZ 6 -+#define RG_IDACAQ_PGAG14_MSK 0x00fc0000 -+#define RG_IDACAQ_PGAG14_I_MSK 0xff03ffff -+#define RG_IDACAQ_PGAG14_SFT 18 -+#define RG_IDACAQ_PGAG14_HI 23 -+#define RG_IDACAQ_PGAG14_SZ 6 -+#define RG_DP_BBPLL_BS_MSK 0x3f000000 -+#define RG_DP_BBPLL_BS_I_MSK 0xc0ffffff -+#define RG_DP_BBPLL_BS_SFT 24 -+#define RG_DP_BBPLL_BS_HI 29 -+#define RG_DP_BBPLL_BS_SZ 6 -+#define RG_IDACAI_PGAG13_MSK 0x0000003f -+#define RG_IDACAI_PGAG13_I_MSK 0xffffffc0 -+#define RG_IDACAI_PGAG13_SFT 0 -+#define RG_IDACAI_PGAG13_HI 5 -+#define RG_IDACAI_PGAG13_SZ 6 -+#define RG_IDACAQ_PGAG13_MSK 0x00000fc0 -+#define RG_IDACAQ_PGAG13_I_MSK 0xfffff03f -+#define RG_IDACAQ_PGAG13_SFT 6 -+#define RG_IDACAQ_PGAG13_HI 11 -+#define RG_IDACAQ_PGAG13_SZ 6 -+#define RG_IDACAI_PGAG12_MSK 0x0003f000 -+#define RG_IDACAI_PGAG12_I_MSK 0xfffc0fff -+#define RG_IDACAI_PGAG12_SFT 12 -+#define RG_IDACAI_PGAG12_HI 17 -+#define RG_IDACAI_PGAG12_SZ 6 -+#define RG_IDACAQ_PGAG12_MSK 0x00fc0000 -+#define RG_IDACAQ_PGAG12_I_MSK 0xff03ffff -+#define RG_IDACAQ_PGAG12_SFT 18 -+#define RG_IDACAQ_PGAG12_HI 23 -+#define RG_IDACAQ_PGAG12_SZ 6 -+#define RG_IDACAI_PGAG11_MSK 0x0000003f -+#define RG_IDACAI_PGAG11_I_MSK 0xffffffc0 -+#define RG_IDACAI_PGAG11_SFT 0 -+#define RG_IDACAI_PGAG11_HI 5 -+#define RG_IDACAI_PGAG11_SZ 6 -+#define RG_IDACAQ_PGAG11_MSK 0x00000fc0 -+#define RG_IDACAQ_PGAG11_I_MSK 0xfffff03f -+#define RG_IDACAQ_PGAG11_SFT 6 -+#define RG_IDACAQ_PGAG11_HI 11 -+#define RG_IDACAQ_PGAG11_SZ 6 -+#define RG_IDACAI_PGAG10_MSK 0x0003f000 -+#define RG_IDACAI_PGAG10_I_MSK 0xfffc0fff -+#define RG_IDACAI_PGAG10_SFT 12 -+#define RG_IDACAI_PGAG10_HI 17 -+#define RG_IDACAI_PGAG10_SZ 6 -+#define RG_IDACAQ_PGAG10_MSK 0x00fc0000 -+#define RG_IDACAQ_PGAG10_I_MSK 0xff03ffff -+#define RG_IDACAQ_PGAG10_SFT 18 -+#define RG_IDACAQ_PGAG10_HI 23 -+#define RG_IDACAQ_PGAG10_SZ 6 -+#define RG_IDACAI_PGAG9_MSK 0x0000003f -+#define RG_IDACAI_PGAG9_I_MSK 0xffffffc0 -+#define RG_IDACAI_PGAG9_SFT 0 -+#define RG_IDACAI_PGAG9_HI 5 -+#define RG_IDACAI_PGAG9_SZ 6 -+#define RG_IDACAQ_PGAG9_MSK 0x00000fc0 -+#define RG_IDACAQ_PGAG9_I_MSK 0xfffff03f -+#define RG_IDACAQ_PGAG9_SFT 6 -+#define RG_IDACAQ_PGAG9_HI 11 -+#define RG_IDACAQ_PGAG9_SZ 6 -+#define RG_IDACAI_PGAG8_MSK 0x0003f000 -+#define RG_IDACAI_PGAG8_I_MSK 0xfffc0fff -+#define RG_IDACAI_PGAG8_SFT 12 -+#define RG_IDACAI_PGAG8_HI 17 -+#define RG_IDACAI_PGAG8_SZ 6 -+#define RG_IDACAQ_PGAG8_MSK 0x00fc0000 -+#define RG_IDACAQ_PGAG8_I_MSK 0xff03ffff -+#define RG_IDACAQ_PGAG8_SFT 18 -+#define RG_IDACAQ_PGAG8_HI 23 -+#define RG_IDACAQ_PGAG8_SZ 6 -+#define RG_IDACAI_PGAG7_MSK 0x0000003f -+#define RG_IDACAI_PGAG7_I_MSK 0xffffffc0 -+#define RG_IDACAI_PGAG7_SFT 0 -+#define RG_IDACAI_PGAG7_HI 5 -+#define RG_IDACAI_PGAG7_SZ 6 -+#define RG_IDACAQ_PGAG7_MSK 0x00000fc0 -+#define RG_IDACAQ_PGAG7_I_MSK 0xfffff03f -+#define RG_IDACAQ_PGAG7_SFT 6 -+#define RG_IDACAQ_PGAG7_HI 11 -+#define RG_IDACAQ_PGAG7_SZ 6 -+#define RG_IDACAI_PGAG6_MSK 0x0003f000 -+#define RG_IDACAI_PGAG6_I_MSK 0xfffc0fff -+#define RG_IDACAI_PGAG6_SFT 12 -+#define RG_IDACAI_PGAG6_HI 17 -+#define RG_IDACAI_PGAG6_SZ 6 -+#define RG_IDACAQ_PGAG6_MSK 0x00fc0000 -+#define RG_IDACAQ_PGAG6_I_MSK 0xff03ffff -+#define RG_IDACAQ_PGAG6_SFT 18 -+#define RG_IDACAQ_PGAG6_HI 23 -+#define RG_IDACAQ_PGAG6_SZ 6 -+#define RG_IDACAI_PGAG5_MSK 0x0000003f -+#define RG_IDACAI_PGAG5_I_MSK 0xffffffc0 -+#define RG_IDACAI_PGAG5_SFT 0 -+#define RG_IDACAI_PGAG5_HI 5 -+#define RG_IDACAI_PGAG5_SZ 6 -+#define RG_IDACAQ_PGAG5_MSK 0x00000fc0 -+#define RG_IDACAQ_PGAG5_I_MSK 0xfffff03f -+#define RG_IDACAQ_PGAG5_SFT 6 -+#define RG_IDACAQ_PGAG5_HI 11 -+#define RG_IDACAQ_PGAG5_SZ 6 -+#define RG_IDACAI_PGAG4_MSK 0x0003f000 -+#define RG_IDACAI_PGAG4_I_MSK 0xfffc0fff -+#define RG_IDACAI_PGAG4_SFT 12 -+#define RG_IDACAI_PGAG4_HI 17 -+#define RG_IDACAI_PGAG4_SZ 6 -+#define RG_IDACAQ_PGAG4_MSK 0x00fc0000 -+#define RG_IDACAQ_PGAG4_I_MSK 0xff03ffff -+#define RG_IDACAQ_PGAG4_SFT 18 -+#define RG_IDACAQ_PGAG4_HI 23 -+#define RG_IDACAQ_PGAG4_SZ 6 -+#define RG_IDACAI_PGAG3_MSK 0x0000003f -+#define RG_IDACAI_PGAG3_I_MSK 0xffffffc0 -+#define RG_IDACAI_PGAG3_SFT 0 -+#define RG_IDACAI_PGAG3_HI 5 -+#define RG_IDACAI_PGAG3_SZ 6 -+#define RG_IDACAQ_PGAG3_MSK 0x00000fc0 -+#define RG_IDACAQ_PGAG3_I_MSK 0xfffff03f -+#define RG_IDACAQ_PGAG3_SFT 6 -+#define RG_IDACAQ_PGAG3_HI 11 -+#define RG_IDACAQ_PGAG3_SZ 6 -+#define RG_IDACAI_PGAG2_MSK 0x0003f000 -+#define RG_IDACAI_PGAG2_I_MSK 0xfffc0fff -+#define RG_IDACAI_PGAG2_SFT 12 -+#define RG_IDACAI_PGAG2_HI 17 -+#define RG_IDACAI_PGAG2_SZ 6 -+#define RG_IDACAQ_PGAG2_MSK 0x00fc0000 -+#define RG_IDACAQ_PGAG2_I_MSK 0xff03ffff -+#define RG_IDACAQ_PGAG2_SFT 18 -+#define RG_IDACAQ_PGAG2_HI 23 -+#define RG_IDACAQ_PGAG2_SZ 6 -+#define RG_IDACAI_PGAG1_MSK 0x0000003f -+#define RG_IDACAI_PGAG1_I_MSK 0xffffffc0 -+#define RG_IDACAI_PGAG1_SFT 0 -+#define RG_IDACAI_PGAG1_HI 5 -+#define RG_IDACAI_PGAG1_SZ 6 -+#define RG_IDACAQ_PGAG1_MSK 0x00000fc0 -+#define RG_IDACAQ_PGAG1_I_MSK 0xfffff03f -+#define RG_IDACAQ_PGAG1_SFT 6 -+#define RG_IDACAQ_PGAG1_HI 11 -+#define RG_IDACAQ_PGAG1_SZ 6 -+#define RG_IDACAI_PGAG0_MSK 0x0003f000 -+#define RG_IDACAI_PGAG0_I_MSK 0xfffc0fff -+#define RG_IDACAI_PGAG0_SFT 12 -+#define RG_IDACAI_PGAG0_HI 17 -+#define RG_IDACAI_PGAG0_SZ 6 -+#define RG_IDACAQ_PGAG0_MSK 0x00fc0000 -+#define RG_IDACAQ_PGAG0_I_MSK 0xff03ffff -+#define RG_IDACAQ_PGAG0_SFT 18 -+#define RG_IDACAQ_PGAG0_HI 23 -+#define RG_IDACAQ_PGAG0_SZ 6 -+#define RG_EN_RCAL_MSK 0x00000001 -+#define RG_EN_RCAL_I_MSK 0xfffffffe -+#define RG_EN_RCAL_SFT 0 -+#define RG_EN_RCAL_HI 0 -+#define RG_EN_RCAL_SZ 1 -+#define RG_RCAL_SPD_MSK 0x00000002 -+#define RG_RCAL_SPD_I_MSK 0xfffffffd -+#define RG_RCAL_SPD_SFT 1 -+#define RG_RCAL_SPD_HI 1 -+#define RG_RCAL_SPD_SZ 1 -+#define RG_RCAL_TMR_MSK 0x000001fc -+#define RG_RCAL_TMR_I_MSK 0xfffffe03 -+#define RG_RCAL_TMR_SFT 2 -+#define RG_RCAL_TMR_HI 8 -+#define RG_RCAL_TMR_SZ 7 -+#define RG_RCAL_CODE_CWR_MSK 0x00000200 -+#define RG_RCAL_CODE_CWR_I_MSK 0xfffffdff -+#define RG_RCAL_CODE_CWR_SFT 9 -+#define RG_RCAL_CODE_CWR_HI 9 -+#define RG_RCAL_CODE_CWR_SZ 1 -+#define RG_RCAL_CODE_CWD_MSK 0x00007c00 -+#define RG_RCAL_CODE_CWD_I_MSK 0xffff83ff -+#define RG_RCAL_CODE_CWD_SFT 10 -+#define RG_RCAL_CODE_CWD_HI 14 -+#define RG_RCAL_CODE_CWD_SZ 5 -+#define RG_SX_SUB_SEL_CWR_MSK 0x00000001 -+#define RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe -+#define RG_SX_SUB_SEL_CWR_SFT 0 -+#define RG_SX_SUB_SEL_CWR_HI 0 -+#define RG_SX_SUB_SEL_CWR_SZ 1 -+#define RG_SX_SUB_SEL_CWD_MSK 0x000000fe -+#define RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01 -+#define RG_SX_SUB_SEL_CWD_SFT 1 -+#define RG_SX_SUB_SEL_CWD_HI 7 -+#define RG_SX_SUB_SEL_CWD_SZ 7 -+#define RG_SX_LCK_BIN_OFFSET_MSK 0x00078000 -+#define RG_SX_LCK_BIN_OFFSET_I_MSK 0xfff87fff -+#define RG_SX_LCK_BIN_OFFSET_SFT 15 -+#define RG_SX_LCK_BIN_OFFSET_HI 18 -+#define RG_SX_LCK_BIN_OFFSET_SZ 4 -+#define RG_SX_LCK_BIN_PRECISION_MSK 0x00080000 -+#define RG_SX_LCK_BIN_PRECISION_I_MSK 0xfff7ffff -+#define RG_SX_LCK_BIN_PRECISION_SFT 19 -+#define RG_SX_LCK_BIN_PRECISION_HI 19 -+#define RG_SX_LCK_BIN_PRECISION_SZ 1 -+#define RG_SX_LOCK_EN_N_MSK 0x00100000 -+#define RG_SX_LOCK_EN_N_I_MSK 0xffefffff -+#define RG_SX_LOCK_EN_N_SFT 20 -+#define RG_SX_LOCK_EN_N_HI 20 -+#define RG_SX_LOCK_EN_N_SZ 1 -+#define RG_SX_LOCK_MANUAL_MSK 0x00200000 -+#define RG_SX_LOCK_MANUAL_I_MSK 0xffdfffff -+#define RG_SX_LOCK_MANUAL_SFT 21 -+#define RG_SX_LOCK_MANUAL_HI 21 -+#define RG_SX_LOCK_MANUAL_SZ 1 -+#define RG_SX_SUB_MANUAL_MSK 0x00400000 -+#define RG_SX_SUB_MANUAL_I_MSK 0xffbfffff -+#define RG_SX_SUB_MANUAL_SFT 22 -+#define RG_SX_SUB_MANUAL_HI 22 -+#define RG_SX_SUB_MANUAL_SZ 1 -+#define RG_SX_SUB_SEL_MSK 0x3f800000 -+#define RG_SX_SUB_SEL_I_MSK 0xc07fffff -+#define RG_SX_SUB_SEL_SFT 23 -+#define RG_SX_SUB_SEL_HI 29 -+#define RG_SX_SUB_SEL_SZ 7 -+#define RG_SX_MUX_SEL_VTH_BINL_MSK 0x40000000 -+#define RG_SX_MUX_SEL_VTH_BINL_I_MSK 0xbfffffff -+#define RG_SX_MUX_SEL_VTH_BINL_SFT 30 -+#define RG_SX_MUX_SEL_VTH_BINL_HI 30 -+#define RG_SX_MUX_SEL_VTH_BINL_SZ 1 -+#define RG_TRX_DUMMMY_MSK 0xffffffff -+#define RG_TRX_DUMMMY_I_MSK 0x00000000 -+#define RG_TRX_DUMMMY_SFT 0 -+#define RG_TRX_DUMMMY_HI 31 -+#define RG_TRX_DUMMMY_SZ 32 -+#define RG_SX_DUMMMY_MSK 0xffffffff -+#define RG_SX_DUMMMY_I_MSK 0x00000000 -+#define RG_SX_DUMMMY_SFT 0 -+#define RG_SX_DUMMMY_HI 31 -+#define RG_SX_DUMMMY_SZ 32 -+#define RCAL_RDY_MSK 0x00000001 -+#define RCAL_RDY_I_MSK 0xfffffffe -+#define RCAL_RDY_SFT 0 -+#define RCAL_RDY_HI 0 -+#define RCAL_RDY_SZ 1 -+#define LCK_BIN_RDY_MSK 0x00000002 -+#define LCK_BIN_RDY_I_MSK 0xfffffffd -+#define LCK_BIN_RDY_SFT 1 -+#define LCK_BIN_RDY_HI 1 -+#define LCK_BIN_RDY_SZ 1 -+#define VT_MON_RDY_MSK 0x00000004 -+#define VT_MON_RDY_I_MSK 0xfffffffb -+#define VT_MON_RDY_SFT 2 -+#define VT_MON_RDY_HI 2 -+#define VT_MON_RDY_SZ 1 -+#define DA_R_CODE_LUT_MSK 0x000007c0 -+#define DA_R_CODE_LUT_I_MSK 0xfffff83f -+#define DA_R_CODE_LUT_SFT 6 -+#define DA_R_CODE_LUT_HI 10 -+#define DA_R_CODE_LUT_SZ 5 -+#define AD_SX_VT_MON_Q_MSK 0x00001800 -+#define AD_SX_VT_MON_Q_I_MSK 0xffffe7ff -+#define AD_SX_VT_MON_Q_SFT 11 -+#define AD_SX_VT_MON_Q_HI 12 -+#define AD_SX_VT_MON_Q_SZ 2 -+#define AD_DP_VT_MON_Q_MSK 0x00006000 -+#define AD_DP_VT_MON_Q_I_MSK 0xffff9fff -+#define AD_DP_VT_MON_Q_SFT 13 -+#define AD_DP_VT_MON_Q_HI 14 -+#define AD_DP_VT_MON_Q_SZ 2 -+#define RTC_CAL_RDY_MSK 0x00008000 -+#define RTC_CAL_RDY_I_MSK 0xffff7fff -+#define RTC_CAL_RDY_SFT 15 -+#define RTC_CAL_RDY_HI 15 -+#define RTC_CAL_RDY_SZ 1 -+#define RG_SARADC_BIT_MSK 0x003f0000 -+#define RG_SARADC_BIT_I_MSK 0xffc0ffff -+#define RG_SARADC_BIT_SFT 16 -+#define RG_SARADC_BIT_HI 21 -+#define RG_SARADC_BIT_SZ 6 -+#define SAR_ADC_FSM_RDY_MSK 0x00400000 -+#define SAR_ADC_FSM_RDY_I_MSK 0xffbfffff -+#define SAR_ADC_FSM_RDY_SFT 22 -+#define SAR_ADC_FSM_RDY_HI 22 -+#define SAR_ADC_FSM_RDY_SZ 1 -+#define AD_CIRCUIT_VERSION_MSK 0x07800000 -+#define AD_CIRCUIT_VERSION_I_MSK 0xf87fffff -+#define AD_CIRCUIT_VERSION_SFT 23 -+#define AD_CIRCUIT_VERSION_HI 26 -+#define AD_CIRCUIT_VERSION_SZ 4 -+#define DA_R_CAL_CODE_MSK 0x0000001f -+#define DA_R_CAL_CODE_I_MSK 0xffffffe0 -+#define DA_R_CAL_CODE_SFT 0 -+#define DA_R_CAL_CODE_HI 4 -+#define DA_R_CAL_CODE_SZ 5 -+#define DA_SX_SUB_SEL_MSK 0x00000fe0 -+#define DA_SX_SUB_SEL_I_MSK 0xfffff01f -+#define DA_SX_SUB_SEL_SFT 5 -+#define DA_SX_SUB_SEL_HI 11 -+#define DA_SX_SUB_SEL_SZ 7 -+#define RG_DPL_RFCTRL_CH_MSK 0x000007ff -+#define RG_DPL_RFCTRL_CH_I_MSK 0xfffff800 -+#define RG_DPL_RFCTRL_CH_SFT 0 -+#define RG_DPL_RFCTRL_CH_HI 10 -+#define RG_DPL_RFCTRL_CH_SZ 11 -+#define RG_RSSIADC_RO_BIT_MSK 0x00007800 -+#define RG_RSSIADC_RO_BIT_I_MSK 0xffff87ff -+#define RG_RSSIADC_RO_BIT_SFT 11 -+#define RG_RSSIADC_RO_BIT_HI 14 -+#define RG_RSSIADC_RO_BIT_SZ 4 -+#define RG_RX_ADC_I_RO_BIT_MSK 0x007f8000 -+#define RG_RX_ADC_I_RO_BIT_I_MSK 0xff807fff -+#define RG_RX_ADC_I_RO_BIT_SFT 15 -+#define RG_RX_ADC_I_RO_BIT_HI 22 -+#define RG_RX_ADC_I_RO_BIT_SZ 8 -+#define RG_RX_ADC_Q_RO_BIT_MSK 0x7f800000 -+#define RG_RX_ADC_Q_RO_BIT_I_MSK 0x807fffff -+#define RG_RX_ADC_Q_RO_BIT_SFT 23 -+#define RG_RX_ADC_Q_RO_BIT_HI 30 -+#define RG_RX_ADC_Q_RO_BIT_SZ 8 -+#define RG_DPL_RFCTRL_F_MSK 0x00ffffff -+#define RG_DPL_RFCTRL_F_I_MSK 0xff000000 -+#define RG_DPL_RFCTRL_F_SFT 0 -+#define RG_DPL_RFCTRL_F_HI 23 -+#define RG_DPL_RFCTRL_F_SZ 24 -+#define RG_SX_TARGET_CNT_MSK 0x00001fff -+#define RG_SX_TARGET_CNT_I_MSK 0xffffe000 -+#define RG_SX_TARGET_CNT_SFT 0 -+#define RG_SX_TARGET_CNT_HI 12 -+#define RG_SX_TARGET_CNT_SZ 13 -+#define RG_RTC_OFFSET_MSK 0x000000ff -+#define RG_RTC_OFFSET_I_MSK 0xffffff00 -+#define RG_RTC_OFFSET_SFT 0 -+#define RG_RTC_OFFSET_HI 7 -+#define RG_RTC_OFFSET_SZ 8 -+#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00 -+#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff -+#define RG_RTC_CAL_TARGET_COUNT_SFT 8 -+#define RG_RTC_CAL_TARGET_COUNT_HI 19 -+#define RG_RTC_CAL_TARGET_COUNT_SZ 12 -+#define RG_RF_D_REG_MSK 0x0000ffff -+#define RG_RF_D_REG_I_MSK 0xffff0000 -+#define RG_RF_D_REG_SFT 0 -+#define RG_RF_D_REG_HI 15 -+#define RG_RF_D_REG_SZ 16 -+#define DIRECT_MODE_MSK 0x00000001 -+#define DIRECT_MODE_I_MSK 0xfffffffe -+#define DIRECT_MODE_SFT 0 -+#define DIRECT_MODE_HI 0 -+#define DIRECT_MODE_SZ 1 -+#define TAG_INTERLEAVE_MD_MSK 0x00000002 -+#define TAG_INTERLEAVE_MD_I_MSK 0xfffffffd -+#define TAG_INTERLEAVE_MD_SFT 1 -+#define TAG_INTERLEAVE_MD_HI 1 -+#define TAG_INTERLEAVE_MD_SZ 1 -+#define DIS_DEMAND_MSK 0x00000004 -+#define DIS_DEMAND_I_MSK 0xfffffffb -+#define DIS_DEMAND_SFT 2 -+#define DIS_DEMAND_HI 2 -+#define DIS_DEMAND_SZ 1 -+#define SAME_ID_ALLOC_MD_MSK 0x00000008 -+#define SAME_ID_ALLOC_MD_I_MSK 0xfffffff7 -+#define SAME_ID_ALLOC_MD_SFT 3 -+#define SAME_ID_ALLOC_MD_HI 3 -+#define SAME_ID_ALLOC_MD_SZ 1 -+#define HS_ACCESS_MD_MSK 0x00000010 -+#define HS_ACCESS_MD_I_MSK 0xffffffef -+#define HS_ACCESS_MD_SFT 4 -+#define HS_ACCESS_MD_HI 4 -+#define HS_ACCESS_MD_SZ 1 -+#define SRAM_ACCESS_MD_MSK 0x00000020 -+#define SRAM_ACCESS_MD_I_MSK 0xffffffdf -+#define SRAM_ACCESS_MD_SFT 5 -+#define SRAM_ACCESS_MD_HI 5 -+#define SRAM_ACCESS_MD_SZ 1 -+#define NOHIT_RPASS_MD_MSK 0x00000040 -+#define NOHIT_RPASS_MD_I_MSK 0xffffffbf -+#define NOHIT_RPASS_MD_SFT 6 -+#define NOHIT_RPASS_MD_HI 6 -+#define NOHIT_RPASS_MD_SZ 1 -+#define DMN_FLAG_CLR_MSK 0x00000080 -+#define DMN_FLAG_CLR_I_MSK 0xffffff7f -+#define DMN_FLAG_CLR_SFT 7 -+#define DMN_FLAG_CLR_HI 7 -+#define DMN_FLAG_CLR_SZ 1 -+#define ERR_SW_RST_N_MSK 0x00000100 -+#define ERR_SW_RST_N_I_MSK 0xfffffeff -+#define ERR_SW_RST_N_SFT 8 -+#define ERR_SW_RST_N_HI 8 -+#define ERR_SW_RST_N_SZ 1 -+#define ALR_SW_RST_N_MSK 0x00000200 -+#define ALR_SW_RST_N_I_MSK 0xfffffdff -+#define ALR_SW_RST_N_SFT 9 -+#define ALR_SW_RST_N_HI 9 -+#define ALR_SW_RST_N_SZ 1 -+#define MCH_SW_RST_N_MSK 0x00000400 -+#define MCH_SW_RST_N_I_MSK 0xfffffbff -+#define MCH_SW_RST_N_SFT 10 -+#define MCH_SW_RST_N_HI 10 -+#define MCH_SW_RST_N_SZ 1 -+#define TAG_SW_RST_N_MSK 0x00000800 -+#define TAG_SW_RST_N_I_MSK 0xfffff7ff -+#define TAG_SW_RST_N_SFT 11 -+#define TAG_SW_RST_N_HI 11 -+#define TAG_SW_RST_N_SZ 1 -+#define ABT_SW_RST_N_MSK 0x00001000 -+#define ABT_SW_RST_N_I_MSK 0xffffefff -+#define ABT_SW_RST_N_SFT 12 -+#define ABT_SW_RST_N_HI 12 -+#define ABT_SW_RST_N_SZ 1 -+#define MMU_VER_MSK 0x0000e000 -+#define MMU_VER_I_MSK 0xffff1fff -+#define MMU_VER_SFT 13 -+#define MMU_VER_HI 15 -+#define MMU_VER_SZ 3 -+#define MMU_SHARE_MCU_MSK 0x00ff0000 -+#define MMU_SHARE_MCU_I_MSK 0xff00ffff -+#define MMU_SHARE_MCU_SFT 16 -+#define MMU_SHARE_MCU_HI 23 -+#define MMU_SHARE_MCU_SZ 8 -+#define HS_WR_MSK 0x00000001 -+#define HS_WR_I_MSK 0xfffffffe -+#define HS_WR_SFT 0 -+#define HS_WR_HI 0 -+#define HS_WR_SZ 1 -+#define HS_FLAG_MSK 0x00000010 -+#define HS_FLAG_I_MSK 0xffffffef -+#define HS_FLAG_SFT 4 -+#define HS_FLAG_HI 4 -+#define HS_FLAG_SZ 1 -+#define HS_ID_MSK 0x00007f00 -+#define HS_ID_I_MSK 0xffff80ff -+#define HS_ID_SFT 8 -+#define HS_ID_HI 14 -+#define HS_ID_SZ 7 -+#define HS_CHANNEL_MSK 0x000f0000 -+#define HS_CHANNEL_I_MSK 0xfff0ffff -+#define HS_CHANNEL_SFT 16 -+#define HS_CHANNEL_HI 19 -+#define HS_CHANNEL_SZ 4 -+#define HS_PAGE_MSK 0x00f00000 -+#define HS_PAGE_I_MSK 0xff0fffff -+#define HS_PAGE_SFT 20 -+#define HS_PAGE_HI 23 -+#define HS_PAGE_SZ 4 -+#define HS_DATA_MSK 0xff000000 -+#define HS_DATA_I_MSK 0x00ffffff -+#define HS_DATA_SFT 24 -+#define HS_DATA_HI 31 -+#define HS_DATA_SZ 8 -+#define CPU_POR0_MSK 0x0000000f -+#define CPU_POR0_I_MSK 0xfffffff0 -+#define CPU_POR0_SFT 0 -+#define CPU_POR0_HI 3 -+#define CPU_POR0_SZ 4 -+#define CPU_POR1_MSK 0x000000f0 -+#define CPU_POR1_I_MSK 0xffffff0f -+#define CPU_POR1_SFT 4 -+#define CPU_POR1_HI 7 -+#define CPU_POR1_SZ 4 -+#define CPU_POR2_MSK 0x00000f00 -+#define CPU_POR2_I_MSK 0xfffff0ff -+#define CPU_POR2_SFT 8 -+#define CPU_POR2_HI 11 -+#define CPU_POR2_SZ 4 -+#define CPU_POR3_MSK 0x0000f000 -+#define CPU_POR3_I_MSK 0xffff0fff -+#define CPU_POR3_SFT 12 -+#define CPU_POR3_HI 15 -+#define CPU_POR3_SZ 4 -+#define CPU_POR4_MSK 0x000f0000 -+#define CPU_POR4_I_MSK 0xfff0ffff -+#define CPU_POR4_SFT 16 -+#define CPU_POR4_HI 19 -+#define CPU_POR4_SZ 4 -+#define CPU_POR5_MSK 0x00f00000 -+#define CPU_POR5_I_MSK 0xff0fffff -+#define CPU_POR5_SFT 20 -+#define CPU_POR5_HI 23 -+#define CPU_POR5_SZ 4 -+#define CPU_POR6_MSK 0x0f000000 -+#define CPU_POR6_I_MSK 0xf0ffffff -+#define CPU_POR6_SFT 24 -+#define CPU_POR6_HI 27 -+#define CPU_POR6_SZ 4 -+#define CPU_POR7_MSK 0xf0000000 -+#define CPU_POR7_I_MSK 0x0fffffff -+#define CPU_POR7_SFT 28 -+#define CPU_POR7_HI 31 -+#define CPU_POR7_SZ 4 -+#define CPU_POR8_MSK 0x0000000f -+#define CPU_POR8_I_MSK 0xfffffff0 -+#define CPU_POR8_SFT 0 -+#define CPU_POR8_HI 3 -+#define CPU_POR8_SZ 4 -+#define CPU_POR9_MSK 0x000000f0 -+#define CPU_POR9_I_MSK 0xffffff0f -+#define CPU_POR9_SFT 4 -+#define CPU_POR9_HI 7 -+#define CPU_POR9_SZ 4 -+#define CPU_PORA_MSK 0x00000f00 -+#define CPU_PORA_I_MSK 0xfffff0ff -+#define CPU_PORA_SFT 8 -+#define CPU_PORA_HI 11 -+#define CPU_PORA_SZ 4 -+#define CPU_PORB_MSK 0x0000f000 -+#define CPU_PORB_I_MSK 0xffff0fff -+#define CPU_PORB_SFT 12 -+#define CPU_PORB_HI 15 -+#define CPU_PORB_SZ 4 -+#define CPU_PORC_MSK 0x000f0000 -+#define CPU_PORC_I_MSK 0xfff0ffff -+#define CPU_PORC_SFT 16 -+#define CPU_PORC_HI 19 -+#define CPU_PORC_SZ 4 -+#define CPU_PORD_MSK 0x00f00000 -+#define CPU_PORD_I_MSK 0xff0fffff -+#define CPU_PORD_SFT 20 -+#define CPU_PORD_HI 23 -+#define CPU_PORD_SZ 4 -+#define CPU_PORE_MSK 0x0f000000 -+#define CPU_PORE_I_MSK 0xf0ffffff -+#define CPU_PORE_SFT 24 -+#define CPU_PORE_HI 27 -+#define CPU_PORE_SZ 4 -+#define CPU_PORF_MSK 0xf0000000 -+#define CPU_PORF_I_MSK 0x0fffffff -+#define CPU_PORF_SFT 28 -+#define CPU_PORF_HI 31 -+#define CPU_PORF_SZ 4 -+#define ACC_WR_LEN_MSK 0x0000003f -+#define ACC_WR_LEN_I_MSK 0xffffffc0 -+#define ACC_WR_LEN_SFT 0 -+#define ACC_WR_LEN_HI 5 -+#define ACC_WR_LEN_SZ 6 -+#define ACC_RD_LEN_MSK 0x00003f00 -+#define ACC_RD_LEN_I_MSK 0xffffc0ff -+#define ACC_RD_LEN_SFT 8 -+#define ACC_RD_LEN_HI 13 -+#define ACC_RD_LEN_SZ 6 -+#define REQ_NACK_CLR_MSK 0x00008000 -+#define REQ_NACK_CLR_I_MSK 0xffff7fff -+#define REQ_NACK_CLR_SFT 15 -+#define REQ_NACK_CLR_HI 15 -+#define REQ_NACK_CLR_SZ 1 -+#define NACK_FLAG_BUS_MSK 0xffff0000 -+#define NACK_FLAG_BUS_I_MSK 0x0000ffff -+#define NACK_FLAG_BUS_SFT 16 -+#define NACK_FLAG_BUS_HI 31 -+#define NACK_FLAG_BUS_SZ 16 -+#define DMN_R_PASS_MSK 0x0000ffff -+#define DMN_R_PASS_I_MSK 0xffff0000 -+#define DMN_R_PASS_SFT 0 -+#define DMN_R_PASS_HI 15 -+#define DMN_R_PASS_SZ 16 -+#define PARA_ALC_RLS_MSK 0x00010000 -+#define PARA_ALC_RLS_I_MSK 0xfffeffff -+#define PARA_ALC_RLS_SFT 16 -+#define PARA_ALC_RLS_HI 16 -+#define PARA_ALC_RLS_SZ 1 -+#define REQ_PORNS_CHGEN_MSK 0x01000000 -+#define REQ_PORNS_CHGEN_I_MSK 0xfeffffff -+#define REQ_PORNS_CHGEN_SFT 24 -+#define REQ_PORNS_CHGEN_HI 24 -+#define REQ_PORNS_CHGEN_SZ 1 -+#define ALC_ABT_ID_MSK 0x0000007f -+#define ALC_ABT_ID_I_MSK 0xffffff80 -+#define ALC_ABT_ID_SFT 0 -+#define ALC_ABT_ID_HI 6 -+#define ALC_ABT_ID_SZ 7 -+#define ALC_ABT_INT_MSK 0x00008000 -+#define ALC_ABT_INT_I_MSK 0xffff7fff -+#define ALC_ABT_INT_SFT 15 -+#define ALC_ABT_INT_HI 15 -+#define ALC_ABT_INT_SZ 1 -+#define RLS_ABT_ID_MSK 0x007f0000 -+#define RLS_ABT_ID_I_MSK 0xff80ffff -+#define RLS_ABT_ID_SFT 16 -+#define RLS_ABT_ID_HI 22 -+#define RLS_ABT_ID_SZ 7 -+#define RLS_ABT_INT_MSK 0x80000000 -+#define RLS_ABT_INT_I_MSK 0x7fffffff -+#define RLS_ABT_INT_SFT 31 -+#define RLS_ABT_INT_HI 31 -+#define RLS_ABT_INT_SZ 1 -+#define DEBUG_CTL_MSK 0x000000ff -+#define DEBUG_CTL_I_MSK 0xffffff00 -+#define DEBUG_CTL_SFT 0 -+#define DEBUG_CTL_HI 7 -+#define DEBUG_CTL_SZ 8 -+#define DEBUG_H16_MSK 0x00000100 -+#define DEBUG_H16_I_MSK 0xfffffeff -+#define DEBUG_H16_SFT 8 -+#define DEBUG_H16_HI 8 -+#define DEBUG_H16_SZ 1 -+#define DEBUG_OUT_MSK 0xffffffff -+#define DEBUG_OUT_I_MSK 0x00000000 -+#define DEBUG_OUT_SFT 0 -+#define DEBUG_OUT_HI 31 -+#define DEBUG_OUT_SZ 32 -+#define ALC_ERR_MSK 0x00000001 -+#define ALC_ERR_I_MSK 0xfffffffe -+#define ALC_ERR_SFT 0 -+#define ALC_ERR_HI 0 -+#define ALC_ERR_SZ 1 -+#define RLS_ERR_MSK 0x00000002 -+#define RLS_ERR_I_MSK 0xfffffffd -+#define RLS_ERR_SFT 1 -+#define RLS_ERR_HI 1 -+#define RLS_ERR_SZ 1 -+#define AL_STATE_MSK 0x00000700 -+#define AL_STATE_I_MSK 0xfffff8ff -+#define AL_STATE_SFT 8 -+#define AL_STATE_HI 10 -+#define AL_STATE_SZ 3 -+#define RL_STATE_MSK 0x00007000 -+#define RL_STATE_I_MSK 0xffff8fff -+#define RL_STATE_SFT 12 -+#define RL_STATE_HI 14 -+#define RL_STATE_SZ 3 -+#define ALC_ERR_ID_MSK 0x007f0000 -+#define ALC_ERR_ID_I_MSK 0xff80ffff -+#define ALC_ERR_ID_SFT 16 -+#define ALC_ERR_ID_HI 22 -+#define ALC_ERR_ID_SZ 7 -+#define RLS_ERR_ID_MSK 0x7f000000 -+#define RLS_ERR_ID_I_MSK 0x80ffffff -+#define RLS_ERR_ID_SFT 24 -+#define RLS_ERR_ID_HI 30 -+#define RLS_ERR_ID_SZ 7 -+#define DMN_NOHIT_FLAG_MSK 0x00000001 -+#define DMN_NOHIT_FLAG_I_MSK 0xfffffffe -+#define DMN_NOHIT_FLAG_SFT 0 -+#define DMN_NOHIT_FLAG_HI 0 -+#define DMN_NOHIT_FLAG_SZ 1 -+#define DMN_FLAG_MSK 0x00000002 -+#define DMN_FLAG_I_MSK 0xfffffffd -+#define DMN_FLAG_SFT 1 -+#define DMN_FLAG_HI 1 -+#define DMN_FLAG_SZ 1 -+#define DMN_WR_MSK 0x00000008 -+#define DMN_WR_I_MSK 0xfffffff7 -+#define DMN_WR_SFT 3 -+#define DMN_WR_HI 3 -+#define DMN_WR_SZ 1 -+#define DMN_PORT_MSK 0x000000f0 -+#define DMN_PORT_I_MSK 0xffffff0f -+#define DMN_PORT_SFT 4 -+#define DMN_PORT_HI 7 -+#define DMN_PORT_SZ 4 -+#define DMN_NHIT_ID_MSK 0x00007f00 -+#define DMN_NHIT_ID_I_MSK 0xffff80ff -+#define DMN_NHIT_ID_SFT 8 -+#define DMN_NHIT_ID_HI 14 -+#define DMN_NHIT_ID_SZ 7 -+#define DMN_NHIT_ADDR_MSK 0xffff0000 -+#define DMN_NHIT_ADDR_I_MSK 0x0000ffff -+#define DMN_NHIT_ADDR_SFT 16 -+#define DMN_NHIT_ADDR_HI 31 -+#define DMN_NHIT_ADDR_SZ 16 -+#define TX_MOUNT_MSK 0x000000ff -+#define TX_MOUNT_I_MSK 0xffffff00 -+#define TX_MOUNT_SFT 0 -+#define TX_MOUNT_HI 7 -+#define TX_MOUNT_SZ 8 -+#define RX_MOUNT_MSK 0x0000ff00 -+#define RX_MOUNT_I_MSK 0xffff00ff -+#define RX_MOUNT_SFT 8 -+#define RX_MOUNT_HI 15 -+#define RX_MOUNT_SZ 8 -+#define AVA_TAG_MSK 0x01ff0000 -+#define AVA_TAG_I_MSK 0xfe00ffff -+#define AVA_TAG_SFT 16 -+#define AVA_TAG_HI 24 -+#define AVA_TAG_SZ 9 -+#define PKTBUF_FULL_MSK 0x80000000 -+#define PKTBUF_FULL_I_MSK 0x7fffffff -+#define PKTBUF_FULL_SFT 31 -+#define PKTBUF_FULL_HI 31 -+#define PKTBUF_FULL_SZ 1 -+#define DMN_NOHIT_MCU_MSK 0x00000001 -+#define DMN_NOHIT_MCU_I_MSK 0xfffffffe -+#define DMN_NOHIT_MCU_SFT 0 -+#define DMN_NOHIT_MCU_HI 0 -+#define DMN_NOHIT_MCU_SZ 1 -+#define DMN_MCU_FLAG_MSK 0x00000002 -+#define DMN_MCU_FLAG_I_MSK 0xfffffffd -+#define DMN_MCU_FLAG_SFT 1 -+#define DMN_MCU_FLAG_HI 1 -+#define DMN_MCU_FLAG_SZ 1 -+#define DMN_MCU_WR_MSK 0x00000008 -+#define DMN_MCU_WR_I_MSK 0xfffffff7 -+#define DMN_MCU_WR_SFT 3 -+#define DMN_MCU_WR_HI 3 -+#define DMN_MCU_WR_SZ 1 -+#define DMN_MCU_PORT_MSK 0x000000f0 -+#define DMN_MCU_PORT_I_MSK 0xffffff0f -+#define DMN_MCU_PORT_SFT 4 -+#define DMN_MCU_PORT_HI 7 -+#define DMN_MCU_PORT_SZ 4 -+#define DMN_MCU_ID_MSK 0x00007f00 -+#define DMN_MCU_ID_I_MSK 0xffff80ff -+#define DMN_MCU_ID_SFT 8 -+#define DMN_MCU_ID_HI 14 -+#define DMN_MCU_ID_SZ 7 -+#define DMN_MCU_ADDR_MSK 0xffff0000 -+#define DMN_MCU_ADDR_I_MSK 0x0000ffff -+#define DMN_MCU_ADDR_SFT 16 -+#define DMN_MCU_ADDR_HI 31 -+#define DMN_MCU_ADDR_SZ 16 -+#define MB_IDTBL_31_0_MSK 0xffffffff -+#define MB_IDTBL_31_0_I_MSK 0x00000000 -+#define MB_IDTBL_31_0_SFT 0 -+#define MB_IDTBL_31_0_HI 31 -+#define MB_IDTBL_31_0_SZ 32 -+#define MB_IDTBL_63_32_MSK 0xffffffff -+#define MB_IDTBL_63_32_I_MSK 0x00000000 -+#define MB_IDTBL_63_32_SFT 0 -+#define MB_IDTBL_63_32_HI 31 -+#define MB_IDTBL_63_32_SZ 32 -+#define MB_IDTBL_95_64_MSK 0xffffffff -+#define MB_IDTBL_95_64_I_MSK 0x00000000 -+#define MB_IDTBL_95_64_SFT 0 -+#define MB_IDTBL_95_64_HI 31 -+#define MB_IDTBL_95_64_SZ 32 -+#define MB_IDTBL_127_96_MSK 0xffffffff -+#define MB_IDTBL_127_96_I_MSK 0x00000000 -+#define MB_IDTBL_127_96_SFT 0 -+#define MB_IDTBL_127_96_HI 31 -+#define MB_IDTBL_127_96_SZ 32 -+#define PKT_IDTBL_31_0_MSK 0xffffffff -+#define PKT_IDTBL_31_0_I_MSK 0x00000000 -+#define PKT_IDTBL_31_0_SFT 0 -+#define PKT_IDTBL_31_0_HI 31 -+#define PKT_IDTBL_31_0_SZ 32 -+#define PKT_IDTBL_63_32_MSK 0xffffffff -+#define PKT_IDTBL_63_32_I_MSK 0x00000000 -+#define PKT_IDTBL_63_32_SFT 0 -+#define PKT_IDTBL_63_32_HI 31 -+#define PKT_IDTBL_63_32_SZ 32 -+#define PKT_IDTBL_95_64_MSK 0xffffffff -+#define PKT_IDTBL_95_64_I_MSK 0x00000000 -+#define PKT_IDTBL_95_64_SFT 0 -+#define PKT_IDTBL_95_64_HI 31 -+#define PKT_IDTBL_95_64_SZ 32 -+#define PKT_IDTBL_127_96_MSK 0xffffffff -+#define PKT_IDTBL_127_96_I_MSK 0x00000000 -+#define PKT_IDTBL_127_96_SFT 0 -+#define PKT_IDTBL_127_96_HI 31 -+#define PKT_IDTBL_127_96_SZ 32 -+#define DMN_IDTBL_31_0_MSK 0xffffffff -+#define DMN_IDTBL_31_0_I_MSK 0x00000000 -+#define DMN_IDTBL_31_0_SFT 0 -+#define DMN_IDTBL_31_0_HI 31 -+#define DMN_IDTBL_31_0_SZ 32 -+#define DMN_IDTBL_63_32_MSK 0xffffffff -+#define DMN_IDTBL_63_32_I_MSK 0x00000000 -+#define DMN_IDTBL_63_32_SFT 0 -+#define DMN_IDTBL_63_32_HI 31 -+#define DMN_IDTBL_63_32_SZ 32 -+#define DMN_IDTBL_95_64_MSK 0xffffffff -+#define DMN_IDTBL_95_64_I_MSK 0x00000000 -+#define DMN_IDTBL_95_64_SFT 0 -+#define DMN_IDTBL_95_64_HI 31 -+#define DMN_IDTBL_95_64_SZ 32 -+#define DMN_IDTBL_127_96_MSK 0xffffffff -+#define DMN_IDTBL_127_96_I_MSK 0x00000000 -+#define DMN_IDTBL_127_96_SFT 0 -+#define DMN_IDTBL_127_96_HI 31 -+#define DMN_IDTBL_127_96_SZ 32 -+#define NEQ_MB_ID_31_0_MSK 0xffffffff -+#define NEQ_MB_ID_31_0_I_MSK 0x00000000 -+#define NEQ_MB_ID_31_0_SFT 0 -+#define NEQ_MB_ID_31_0_HI 31 -+#define NEQ_MB_ID_31_0_SZ 32 -+#define NEQ_MB_ID_63_32_MSK 0xffffffff -+#define NEQ_MB_ID_63_32_I_MSK 0x00000000 -+#define NEQ_MB_ID_63_32_SFT 0 -+#define NEQ_MB_ID_63_32_HI 31 -+#define NEQ_MB_ID_63_32_SZ 32 -+#define NEQ_MB_ID_95_64_MSK 0xffffffff -+#define NEQ_MB_ID_95_64_I_MSK 0x00000000 -+#define NEQ_MB_ID_95_64_SFT 0 -+#define NEQ_MB_ID_95_64_HI 31 -+#define NEQ_MB_ID_95_64_SZ 32 -+#define NEQ_MB_ID_127_96_MSK 0xffffffff -+#define NEQ_MB_ID_127_96_I_MSK 0x00000000 -+#define NEQ_MB_ID_127_96_SFT 0 -+#define NEQ_MB_ID_127_96_HI 31 -+#define NEQ_MB_ID_127_96_SZ 32 -+#define NEQ_PKT_ID_31_0_MSK 0xffffffff -+#define NEQ_PKT_ID_31_0_I_MSK 0x00000000 -+#define NEQ_PKT_ID_31_0_SFT 0 -+#define NEQ_PKT_ID_31_0_HI 31 -+#define NEQ_PKT_ID_31_0_SZ 32 -+#define NEQ_PKT_ID_63_32_MSK 0xffffffff -+#define NEQ_PKT_ID_63_32_I_MSK 0x00000000 -+#define NEQ_PKT_ID_63_32_SFT 0 -+#define NEQ_PKT_ID_63_32_HI 31 -+#define NEQ_PKT_ID_63_32_SZ 32 -+#define NEQ_PKT_ID_95_64_MSK 0xffffffff -+#define NEQ_PKT_ID_95_64_I_MSK 0x00000000 -+#define NEQ_PKT_ID_95_64_SFT 0 -+#define NEQ_PKT_ID_95_64_HI 31 -+#define NEQ_PKT_ID_95_64_SZ 32 -+#define NEQ_PKT_ID_127_96_MSK 0xffffffff -+#define NEQ_PKT_ID_127_96_I_MSK 0x00000000 -+#define NEQ_PKT_ID_127_96_SFT 0 -+#define NEQ_PKT_ID_127_96_HI 31 -+#define NEQ_PKT_ID_127_96_SZ 32 -+#define ALC_NOCHG_ID_MSK 0x0000007f -+#define ALC_NOCHG_ID_I_MSK 0xffffff80 -+#define ALC_NOCHG_ID_SFT 0 -+#define ALC_NOCHG_ID_HI 6 -+#define ALC_NOCHG_ID_SZ 7 -+#define ALC_NOCHG_INT_MSK 0x00008000 -+#define ALC_NOCHG_INT_I_MSK 0xffff7fff -+#define ALC_NOCHG_INT_SFT 15 -+#define ALC_NOCHG_INT_HI 15 -+#define ALC_NOCHG_INT_SZ 1 -+#define NEQ_PKT_FLAG_MSK 0x00010000 -+#define NEQ_PKT_FLAG_I_MSK 0xfffeffff -+#define NEQ_PKT_FLAG_SFT 16 -+#define NEQ_PKT_FLAG_HI 16 -+#define NEQ_PKT_FLAG_SZ 1 -+#define NEQ_MB_FLAG_MSK 0x01000000 -+#define NEQ_MB_FLAG_I_MSK 0xfeffffff -+#define NEQ_MB_FLAG_SFT 24 -+#define NEQ_MB_FLAG_HI 24 -+#define NEQ_MB_FLAG_SZ 1 -+#define SRAM_TAG_0_MSK 0x0000ffff -+#define SRAM_TAG_0_I_MSK 0xffff0000 -+#define SRAM_TAG_0_SFT 0 -+#define SRAM_TAG_0_HI 15 -+#define SRAM_TAG_0_SZ 16 -+#define SRAM_TAG_1_MSK 0xffff0000 -+#define SRAM_TAG_1_I_MSK 0x0000ffff -+#define SRAM_TAG_1_SFT 16 -+#define SRAM_TAG_1_HI 31 -+#define SRAM_TAG_1_SZ 16 -+#define SRAM_TAG_2_MSK 0x0000ffff -+#define SRAM_TAG_2_I_MSK 0xffff0000 -+#define SRAM_TAG_2_SFT 0 -+#define SRAM_TAG_2_HI 15 -+#define SRAM_TAG_2_SZ 16 -+#define SRAM_TAG_3_MSK 0xffff0000 -+#define SRAM_TAG_3_I_MSK 0x0000ffff -+#define SRAM_TAG_3_SFT 16 -+#define SRAM_TAG_3_HI 31 -+#define SRAM_TAG_3_SZ 16 -+#define SRAM_TAG_4_MSK 0x0000ffff -+#define SRAM_TAG_4_I_MSK 0xffff0000 -+#define SRAM_TAG_4_SFT 0 -+#define SRAM_TAG_4_HI 15 -+#define SRAM_TAG_4_SZ 16 -+#define SRAM_TAG_5_MSK 0xffff0000 -+#define SRAM_TAG_5_I_MSK 0x0000ffff -+#define SRAM_TAG_5_SFT 16 -+#define SRAM_TAG_5_HI 31 -+#define SRAM_TAG_5_SZ 16 -+#define SRAM_TAG_6_MSK 0x0000ffff -+#define SRAM_TAG_6_I_MSK 0xffff0000 -+#define SRAM_TAG_6_SFT 0 -+#define SRAM_TAG_6_HI 15 -+#define SRAM_TAG_6_SZ 16 -+#define SRAM_TAG_7_MSK 0xffff0000 -+#define SRAM_TAG_7_I_MSK 0x0000ffff -+#define SRAM_TAG_7_SFT 16 -+#define SRAM_TAG_7_HI 31 -+#define SRAM_TAG_7_SZ 16 -+#define SRAM_TAG_8_MSK 0x0000ffff -+#define SRAM_TAG_8_I_MSK 0xffff0000 -+#define SRAM_TAG_8_SFT 0 -+#define SRAM_TAG_8_HI 15 -+#define SRAM_TAG_8_SZ 16 -+#define SRAM_TAG_9_MSK 0xffff0000 -+#define SRAM_TAG_9_I_MSK 0x0000ffff -+#define SRAM_TAG_9_SFT 16 -+#define SRAM_TAG_9_HI 31 -+#define SRAM_TAG_9_SZ 16 -+#define SRAM_TAG_10_MSK 0x0000ffff -+#define SRAM_TAG_10_I_MSK 0xffff0000 -+#define SRAM_TAG_10_SFT 0 -+#define SRAM_TAG_10_HI 15 -+#define SRAM_TAG_10_SZ 16 -+#define SRAM_TAG_11_MSK 0xffff0000 -+#define SRAM_TAG_11_I_MSK 0x0000ffff -+#define SRAM_TAG_11_SFT 16 -+#define SRAM_TAG_11_HI 31 -+#define SRAM_TAG_11_SZ 16 -+#define SRAM_TAG_12_MSK 0x0000ffff -+#define SRAM_TAG_12_I_MSK 0xffff0000 -+#define SRAM_TAG_12_SFT 0 -+#define SRAM_TAG_12_HI 15 -+#define SRAM_TAG_12_SZ 16 -+#define SRAM_TAG_13_MSK 0xffff0000 -+#define SRAM_TAG_13_I_MSK 0x0000ffff -+#define SRAM_TAG_13_SFT 16 -+#define SRAM_TAG_13_HI 31 -+#define SRAM_TAG_13_SZ 16 -+#define SRAM_TAG_14_MSK 0x0000ffff -+#define SRAM_TAG_14_I_MSK 0xffff0000 -+#define SRAM_TAG_14_SFT 0 -+#define SRAM_TAG_14_HI 15 -+#define SRAM_TAG_14_SZ 16 -+#define SRAM_TAG_15_MSK 0xffff0000 -+#define SRAM_TAG_15_I_MSK 0x0000ffff -+#define SRAM_TAG_15_SFT 16 -+#define SRAM_TAG_15_HI 31 -+#define SRAM_TAG_15_SZ 16 -diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_common.h b/drivers/net/wireless/ssv6051/include/ssv6200_common.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/include/ssv6200_common.h -@@ -0,0 +1,452 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV6200_COMMON_H_ -+#define _SSV6200_COMMON_H_ -+#define FW_VERSION_REG ADR_TX_SEG -+#define M_ENG_CPU 0x00 -+#define M_ENG_HWHCI 0x01 -+#define M_ENG_EMPTY 0x02 -+#define M_ENG_ENCRYPT 0x03 -+#define M_ENG_MACRX 0x04 -+#define M_ENG_MIC 0x05 -+#define M_ENG_TX_EDCA0 0x06 -+#define M_ENG_TX_EDCA1 0x07 -+#define M_ENG_TX_EDCA2 0x08 -+#define M_ENG_TX_EDCA3 0x09 -+#define M_ENG_TX_MNG 0x0A -+#define M_ENG_ENCRYPT_SEC 0x0B -+#define M_ENG_MIC_SEC 0x0C -+#define M_ENG_RESERVED_1 0x0D -+#define M_ENG_RESERVED_2 0x0E -+#define M_ENG_TRASH_CAN 0x0F -+#define M_ENG_MAX (M_ENG_TRASH_CAN+1) -+#define M_CPU_HWENG 0x00 -+#define M_CPU_TXL34CS 0x01 -+#define M_CPU_RXL34CS 0x02 -+#define M_CPU_DEFRAG 0x03 -+#define M_CPU_EDCATX 0x04 -+#define M_CPU_RXDATA 0x05 -+#define M_CPU_RXMGMT 0x06 -+#define M_CPU_RXCTRL 0x07 -+#define M_CPU_FRAG 0x08 -+#define M_CPU_TXTPUT 0x09 -+#ifndef ID_TRAP_SW_TXTPUT -+#define ID_TRAP_SW_TXTPUT 50 -+#endif -+#define M0_TXREQ 0 -+#define M1_TXREQ 1 -+#define M2_TXREQ 2 -+#define M0_RXEVENT 3 -+#define M2_RXEVENT 4 -+#define HOST_CMD 5 -+#define HOST_EVENT 6 -+#define TEST_CMD 7 -+#define SSV6XXX_RX_DESC_LEN \ -+ (sizeof(struct ssv6200_rx_desc) + \ -+ sizeof(struct ssv6200_rxphy_info)) -+#define SSV6XXX_TX_DESC_LEN \ -+ (sizeof(struct ssv6200_tx_desc) + 0) -+#define TXPB_OFFSET 80 -+#define RXPB_OFFSET 80 -+#define SSV6200_TX_PKT_RSVD_SETTING 0x3 -+#define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16 -+#define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD -+#define SSV62XX_TX_MAX_RATES 3 -+ -+enum ssv6xxx_sr_bhvr { -+ SUSPEND_RESUME_0, -+ SUSPEND_RESUME_1, -+ SUSPEND_RESUME_MAX -+}; -+ -+enum ssv6xxx_reboot_bhvr { -+ SSV_SYS_REBOOT = 1, -+ SSV_SYS_HALF, -+ SSV_SYS_POWER_OFF -+}; -+ -+struct fw_rc_retry_params { -+ u32 count:4; -+ u32 drate:6; -+ u32 crate:6; -+ u32 rts_cts_nav:16; -+ u32 frame_consume_time:10; -+ u32 dl_length:12; -+ u32 RSVD:10; -+} __attribute__((packed)); -+struct ssv6200_tx_desc { -+ u32 len:16; -+ u32 c_type:3; -+ u32 f80211:1; -+ u32 qos:1; -+ u32 ht:1; -+ u32 use_4addr:1; -+ u32 RSVD_0:3; -+ u32 bc_que:1; -+ u32 security:1; -+ u32 more_data:1; -+ u32 stype_b5b4:2; -+ u32 extra_info:1; -+ u32 fCmd; -+ u32 hdr_offset:8; -+ u32 frag:1; -+ u32 unicast:1; -+ u32 hdr_len:6; -+ u32 tx_report:1; -+ u32 tx_burst:1; -+ u32 ack_policy:2; -+ u32 aggregation:1; -+ u32 RSVD_1:3; -+ u32 do_rts_cts:2; -+ u32 reason:6; -+ u32 payload_offset:8; -+ u32 RSVD_4:7; -+ u32 RSVD_2:1; -+ u32 fCmdIdx:3; -+ u32 wsid:4; -+ u32 txq_idx:3; -+ u32 TxF_ID:6; -+ u32 rts_cts_nav:16; -+ u32 frame_consume_time:10; -+ u32 crate_idx:6; -+ u32 drate_idx:6; -+ u32 dl_length:12; -+ u32 RSVD_3:14; -+ u32 RESERVED[8]; -+ struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES]; -+}; -+struct ssv6200_rx_desc { -+ u32 len:16; -+ u32 c_type:3; -+ u32 f80211:1; -+ u32 qos:1; -+ u32 ht:1; -+ u32 use_4addr:1; -+ u32 l3cs_err:1; -+ u32 l4cs_err:1; -+ u32 align2:1; -+ u32 RSVD_0:2; -+ u32 psm:1; -+ u32 stype_b5b4:2; -+ u32 extra_info:1; -+ u32 edca0_used:4; -+ u32 edca1_used:5; -+ u32 edca2_used:5; -+ u32 edca3_used:5; -+ u32 mng_used:4; -+ u32 tx_page_used:9; -+ u32 hdr_offset:8; -+ u32 frag:1; -+ u32 unicast:1; -+ u32 hdr_len:6; -+ u32 RxResult:8; -+ u32 wildcard_bssid:1; -+ u32 RSVD_1:1; -+ u32 reason:6; -+ u32 payload_offset:8; -+ u32 tx_id_used:8; -+ u32 fCmdIdx:3; -+ u32 wsid:4; -+ u32 RSVD_3:3; -+ u32 rate_idx:6; -+}; -+struct ssv6200_rxphy_info { -+ u32 len:16; -+ u32 rsvd0:16; -+ u32 mode:3; -+ u32 ch_bw:3; -+ u32 preamble:1; -+ u32 ht_short_gi:1; -+ u32 rate:7; -+ u32 rsvd1:1; -+ u32 smoothing:1; -+ u32 no_sounding:1; -+ u32 aggregate:1; -+ u32 stbc:2; -+ u32 fec:1; -+ u32 n_ess:2; -+ u32 rsvd2:8; -+ u32 l_length:12; -+ u32 l_rate:3; -+ u32 rsvd3:17; -+ u32 rsvd4; -+ u32 rpci:8; -+ u32 snr:8; -+ u32 service:16; -+}; -+struct ssv6200_rxphy_info_padding { -+ u32 rpci:8; -+ u32 snr:8; -+ u32 RSVD:16; -+}; -+struct ssv6200_txphy_info { -+ u32 rsvd[7]; -+}; -+#ifdef CONFIG_P2P_NOA -+struct ssv6xxx_p2p_noa_param { -+ u32 duration; -+ u32 interval; -+ u32 start_time; -+ u32 enable:8; -+ u32 count:8; -+ u8 addr[6]; -+ u8 vif_id; -+} __attribute__((packed)); -+#endif -+typedef struct cfg_host_cmd { -+ u32 len:16; -+ u32 c_type:3; -+ u32 RSVD0:5; -+ u32 h_cmd:8; -+ u32 cmd_seq_no; -+ union { -+ u32 dummy; -+ u8 dat8[0]; -+ u16 dat16[0]; -+ u32 dat32[0]; -+ }; -+} HDR_HostCmd; -+#define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U) -+struct sdio_rxtput_cfg { -+ u32 size_per_frame; -+ u32 total_frames; -+}; -+typedef enum { -+ SSV6XXX_HOST_CMD_START = 0, -+ SSV6XXX_HOST_CMD_LOG, -+ SSV6XXX_HOST_CMD_PS, -+ SSV6XXX_HOST_CMD_INIT_CALI, -+ SSV6XXX_HOST_CMD_RX_TPUT, -+ SSV6XXX_HOST_CMD_TX_TPUT, -+ SSV6XXX_HOST_CMD_WATCHDOG_START, -+ SSV6XXX_HOST_CMD_WATCHDOG_STOP, -+ SSV6XXX_HOST_CMD_WSID_OP, -+#ifdef CONFIG_P2P_NOA -+ SSV6XXX_HOST_CMD_SET_NOA, -+#endif -+ SSV6XXX_HOST_SOC_CMD_MAXID, -+} ssv6xxx_host_cmd_id; -+#define SSV_NUM_HW_STA 2 -+typedef struct cfg_host_event { -+ u32 len:16; -+ u32 c_type:3; -+ u32 RSVD0:5; -+ u32 h_event:8; -+ u32 evt_seq_no; -+ u8 dat[0]; -+} HDR_HostEvent; -+typedef enum { -+#ifdef USE_CMD_RESP -+ SOC_EVT_CMD_RESP, -+ SOC_EVT_SCAN_RESULT, -+ SOC_EVT_DEAUTH, -+#else -+ SOC_EVT_GET_REG_RESP, -+#endif -+ SOC_EVT_NO_BA, -+ SOC_EVT_RC_MPDU_REPORT, -+ SOC_EVT_RC_AMPDU_REPORT, -+ SOC_EVT_LOG, -+#ifdef CONFIG_P2P_NOA -+ SOC_EVT_NOA, -+#endif -+ SOC_EVT_USER_END, -+ SOC_EVT_SDIO_TEST_COMMAND, -+ SOC_EVT_RESET_HOST, -+ SOC_EVT_SDIO_TXTPUT_RESULT, -+ SOC_EVT_WATCHDOG_TRIGGER, -+ SOC_EVT_TXLOOPBK_RESULT, -+ SOC_EVT_MAXID, -+} ssv6xxx_soc_event; -+#ifdef CONFIG_P2P_NOA -+typedef enum { -+ SSV6XXX_NOA_START = 0, -+ SSV6XXX_NOA_STOP, -+} ssv6xxx_host_noa_event; -+struct ssv62xx_noa_evt { -+ u8 evt_id; -+ u8 vif; -+} __attribute__((packed)); -+#endif -+typedef enum { -+ SSV6XXX_RC_COUNTER_CLEAR = 1, -+ SSV6XXX_RC_REPORT, -+} ssv6xxx_host_rate_control_event; -+#define MAX_AGGR_NUM (24) -+struct ssv62xx_tx_rate { -+ s8 data_rate; -+ u8 count; -+} __attribute__((packed)); -+struct ampdu_ba_notify_data { -+ u8 wsid; -+ struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES]; -+ u16 seq_no[MAX_AGGR_NUM]; -+} __attribute__((packed)); -+struct firmware_rate_control_report_data { -+ u8 wsid; -+ struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES]; -+ u16 ampdu_len; -+ u16 ampdu_ack_len; -+ int ack_signal; -+} __attribute__((packed)); -+#define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES) -+#define SSV_RC_RATE_MAX 39 -+enum SSV6XXX_WSID_OPS { -+ SSV6XXX_WSID_OPS_ADD, -+ SSV6XXX_WSID_OPS_DEL, -+ SSV6XXX_WSID_OPS_RESETALL, -+ SSV6XXX_WSID_OPS_ENABLE_CAPS, -+ SSV6XXX_WSID_OPS_DISABLE_CAPS, -+ SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE, -+ SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE, -+ SSV6XXX_WSID_OPS_MAX -+}; -+enum SSV6XXX_WSID_SEC { -+ SSV6XXX_WSID_SEC_NONE = 0, -+ SSV6XXX_WSID_SEC_PAIRWISE = 1 << 0, -+ SSV6XXX_WSID_SEC_GROUP = 1 << 1, -+}; -+enum SSV6XXX_WSID_SEC_TYPE { -+ SSV6XXX_WSID_SEC_SW, -+ SSV6XXX_WSID_SEC_HW, -+ SSV6XXX_WSID_SEC_TYPE_MAX -+}; -+enum SSV6XXX_RETURN_STATE { -+ SSV6XXX_STATE_OK, -+ SSV6XXX_STATE_NG, -+ SSV6XXX_STATE_MAX -+}; -+struct ssv6xxx_wsid_params { -+ u8 cmd; -+ u8 wsid_idx; -+ u8 target_wsid[6]; -+ u8 hw_security; -+}; -+struct ssv6xxx_iqk_cfg { -+ u32 cfg_xtal:8; -+ u32 cfg_pa:8; -+ u32 cfg_pabias_ctrl:8; -+ u32 cfg_pacascode_ctrl:8; -+ u32 cfg_tssi_trgt:8; -+ u32 cfg_tssi_div:8; -+ u32 cfg_def_tx_scale_11b:8; -+ u32 cfg_def_tx_scale_11b_p0d5:8; -+ u32 cfg_def_tx_scale_11g:8; -+ u32 cfg_def_tx_scale_11g_p0d5:8; -+ u32 cmd_sel; -+ union { -+ u32 fx_sel; -+ u32 argv; -+ }; -+ u32 phy_tbl_size; -+ u32 rf_tbl_size; -+}; -+#define PHY_SETTING_SIZE sizeof(phy_setting) -+struct ssv6xxx_ch_cfg { -+ u32 reg_addr; -+ u32 ch1_12_value; -+ u32 ch13_14_value; -+}; -+#define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg)) -+#define RF_SETTING_SIZE (sizeof(asic_rf_setting)) -+#define MAX_PHY_SETTING_TABLE_SIZE 1920 -+#define MAX_RF_SETTING_TABLE_SIZE 512 -+typedef enum { -+ SSV6XXX_VOLT_DCDC_CONVERT = 0, -+ SSV6XXX_VOLT_LDO_CONVERT, -+} ssv6xxx_cfg_volt; -+typedef enum { -+ SSV6XXX_VOLT_33V = 0, -+ SSV6XXX_VOLT_42V, -+} ssv6xxx_cfg_volt_value; -+typedef enum { -+ SSV6XXX_IQK_CFG_XTAL_26M = 0, -+ SSV6XXX_IQK_CFG_XTAL_40M, -+ SSV6XXX_IQK_CFG_XTAL_24M, -+ SSV6XXX_IQK_CFG_XTAL_MAX, -+} ssv6xxx_iqk_cfg_xtal; -+typedef enum { -+ SSV6XXX_IQK_CFG_PA_DEF = 0, -+ SSV6XXX_IQK_CFG_PA_LI_MPB, -+ SSV6XXX_IQK_CFG_PA_LI_EVB, -+ SSV6XXX_IQK_CFG_PA_HP, -+} ssv6xxx_iqk_cfg_pa; -+typedef enum { -+ SSV6XXX_IQK_CMD_INIT_CALI = 0, -+ SSV6XXX_IQK_CMD_RTBL_LOAD, -+ SSV6XXX_IQK_CMD_RTBL_LOAD_DEF, -+ SSV6XXX_IQK_CMD_RTBL_RESET, -+ SSV6XXX_IQK_CMD_RTBL_SET, -+ SSV6XXX_IQK_CMD_RTBL_EXPORT, -+ SSV6XXX_IQK_CMD_TK_EVM, -+ SSV6XXX_IQK_CMD_TK_TONE, -+ SSV6XXX_IQK_CMD_TK_CHCH, -+} ssv6xxx_iqk_cmd_sel; -+#define SSV6XXX_IQK_TEMPERATURE 0x00000004 -+#define SSV6XXX_IQK_RXDC 0x00000008 -+#define SSV6XXX_IQK_RXRC 0x00000010 -+#define SSV6XXX_IQK_TXDC 0x00000020 -+#define SSV6XXX_IQK_TXIQ 0x00000040 -+#define SSV6XXX_IQK_RXIQ 0x00000080 -+#define SSV6XXX_IQK_TSSI 0x00000100 -+#define SSV6XXX_IQK_PAPD 0x00000200 -+typedef struct ssv_cabrio_reg_st { -+ u32 address; -+ u32 data; -+} ssv_cabrio_reg; -+typedef enum __PBuf_Type_E { -+ NOTYPE_BUF = 0, -+ TX_BUF = 1, -+ RX_BUF = 2 -+} PBuf_Type_E; -+struct SKB_info_st { -+ struct ieee80211_sta *sta; -+ u16 mpdu_retry_counter; -+ unsigned long aggr_timestamp; -+ u16 ampdu_tx_status; -+ u16 ampdu_tx_final_retry_count; -+ u16 lowest_rate; -+ struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES]; -+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP -+ ktime_t timestamp; -+#endif -+}; -+typedef struct SKB_info_st SKB_info; -+typedef struct SKB_info_st *p_SKB_info; -+#define SSV_SKB_info_size (sizeof(struct SKB_info_st)) -+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP -+#define SKB_DURATION_TIMEOUT_MS 100 -+enum ssv_debug_skb_timestamp { -+ SKB_DURATION_STAGE_TX_ENQ, -+ SKB_DURATION_STAGE_TO_SDIO, -+ SKB_DURATION_STAGE_IN_HWQ, -+ SKB_DURATION_STAGE_END -+}; -+#endif -+#define SSV6051Q_P1 0x00000000 -+#define SSV6051Q_P2 0x70000000 -+#define SSV6051Z 0x71000000 -+#define SSV6051Q 0x73000000 -+#define SSV6051P 0x75000000 -+struct ssv6xxx_tx_loopback { -+ u32 reg; -+ u32 val; -+ u32 restore_val; -+ u8 restore; -+ u8 delay_ms; -+}; -+#endif -diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h -@@ -0,0 +1,317 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+static ssv_cabrio_reg phy_setting[] = { -+ {0xce0071bc, 0x565B565B}, -+ {0xce000008, 0x0000006a}, -+ {0xce00000c, 0x00000064}, -+ {0xce000010, 0x00007FFF}, -+ {0xce000014, 0x00000003}, -+ {0xce000018, 0x0055003C}, -+ {0xce00001c, 0x00000064}, -+ {0xce000020, 0x20000000}, -+ {0xce00002c, 0x00000000}, -+ {0xce000030, 0x80046072}, -+ {0xce000034, 0x1f300f6f}, -+ {0xce000038, 0x660F36D0}, -+ {0xce00003c, 0x106C0004}, -+ {0xce000040, 0x01601400}, -+ {0xce000044, 0x00600008}, -+ {0xce000048, 0xff000160}, -+ {0xce00004c, 0x00000840}, -+ {0xce000060, 0x01000405}, -+ {0xce000064, 0x06090813}, -+ {0xce000068, 0x12070000}, -+ {0xce00006c, 0x01000405}, -+ {0xce000070, 0x06090813}, -+ {0xce000074, 0x12010000}, -+ {0xce000078, 0x00000000}, -+ {0xce00007c, 0x10110003}, -+ {0xce000080, 0x0110000F}, -+ {0xce000084, 0x00000000}, -+ {0xce000088, 0x00000000}, -+ {0xce000094, 0x01012425}, -+ {0xce000098, 0x01010101}, -+ {0xce00009c, 0x00000011}, -+ {0xce0000a0, 0x1fff0000}, -+ {0xce0000a4, 0x1fff0000}, -+ {0xce0000a8, 0x1fff0000}, -+ {0xce0000ac, 0x1fff0000}, -+ {0xce0000b8, 0x0000fe3e}, -+ {0xce0000fc, 0xffffffff}, -+ {0xce000108, 0x0ead04f5}, -+ {0xce00010c, 0x0fd60080}, -+ {0xce000110, 0x00000009}, -+ {0xce0010a4, 0x0000002c}, -+ {0xce0010b4, 0x00003001}, -+ {0xce0010d4, 0x00000001}, -+ {0xce002000, 0x00000044}, -+ {0xce002004, 0x00040000}, -+ {0xce002008, 0x20300050}, -+ {0xce00200c, 0x00003467}, -+ {0xce002010, 0x00430000}, -+ {0xce002014, 0x20304015}, -+ {0xce002018, 0x00390005}, -+ {0xce00201c, 0x05555555}, -+ {0xce002020, 0x00570057}, -+ {0xce002024, 0x00570057}, -+ {0xce002028, 0x00236700}, -+ {0xce00202c, 0x000d1746}, -+ {0xce002030, 0x05061787}, -+ {0xce002034, 0x07800000}, -+ {0xce00209c, 0x00900008}, -+ {0xce0020a0, 0x00000000}, -+ {0xce0023f8, 0x00000000}, -+ {0xce0023fc, 0x00000001}, -+ {0xce0030a4, 0x00001901}, -+ {0xce0030b8, 0x5d08908e}, -+ {0xce004000, 0x00000044}, -+ {0xce004004, 0x00750075}, -+ {0xce004008, 0x00000075}, -+ {0xce00400c, 0x10000075}, -+ {0xce004010, 0x3F384905}, -+ {0xce004014, 0x40182000}, -+ {0xce004018, 0x20600000}, -+ {0xce00401c, 0x0C010120}, -+ {0xce004020, 0x50505050}, -+ {0xce004024, 0x50000000}, -+ {0xce004028, 0x50505050}, -+ {0xce00402c, 0x506070A0}, -+ {0xce004030, 0xF0000000}, -+ {0xce004034, 0x00002424}, -+ {0xce004038, 0x00001420}, -+ {0xce00409c, 0x0000300A}, -+ {0xce0040c0, 0x20000280}, -+ {0xce0040c4, 0x30023002}, -+ {0xce0040c8, 0x0000003a}, -+ {0xce004130, 0x40000000}, -+ {0xce004164, 0x009C007E}, -+ {0xce004180, 0x00044400}, -+ {0xce004188, 0x82000000}, -+ {0xce004190, 0x00000000}, -+ {0xce004194, 0xffffffff}, -+ {0xce004380, 0x00700010}, -+ {0xce004384, 0x00007575}, -+ {0xce004388, 0x0001fe3e}, -+ {0xce00438c, 0x0000fe3e}, -+ {0xce0043f8, 0x00000001}, -+ {0xce007000, 0x00000000}, -+ {0xce007004, 0x00008000}, -+ {0xce007008, 0x00000000}, -+ {0xce00700c, 0x00000000}, -+ {0xce007010, 0x00000000}, -+ {0xce007014, 0x00000000}, -+ {0xce007018, 0x00000000}, -+ {0xce00701c, 0x00000000}, -+ {0xce007020, 0x00000000}, -+ {0xce007024, 0x00000000}, -+ {0xce007028, 0x00000000}, -+ {0xce00702c, 0x00000000}, -+ {0xce007030, 0x00000000}, -+ {0xce007034, 0x00000000}, -+ {0xce007038, 0x00000000}, -+ {0xce00703c, 0x00000000}, -+ {0xce007040, 0x02000200}, -+ {0xce007048, 0x00000000}, -+ {0xce00704c, 0x00000000}, -+ {0xce007050, 0x00000000}, -+ {0xce007054, 0x00000000}, -+ {0xce007058, 0x000028ff}, -+ {0xce00705c, 0x00000000}, -+ {0xce007060, 0x00000000}, -+ {0xce007064, 0x00000000}, -+ {0xce007068, 0x00000000}, -+ {0xce00706c, 0x00000202}, -+ {0xce007070, 0x80ffc200}, -+ {0xce007074, 0x00000000}, -+ {0xce007078, 0x00000000}, -+ {0xce00707c, 0x00000000}, -+ {0xce007080, 0x00000000}, -+ {0xce007084, 0x00000000}, -+ {0xce007088, 0x00000000}, -+ {0xce00708c, 0x00000000}, -+ {0xce007090, 0x00000000}, -+ {0xce007094, 0x00000000}, -+ {0xce007098, 0x00000000}, -+ {0xce00709c, 0x00000000}, -+ {0xce0070a0, 0x00000000}, -+ {0xce0070a4, 0x00000000}, -+ {0xce0070a8, 0x00000000}, -+ {0xce0070ac, 0x00000000}, -+ {0xce0070b0, 0x00000000}, -+ {0xce0070b4, 0x00000000}, -+ {0xce0070b8, 0x00000000}, -+ {0xce0070bc, 0x00000000}, -+ {0xce0070c0, 0x00000000}, -+ {0xce0070c4, 0x00000000}, -+ {0xce0070c8, 0x00000000}, -+ {0xce0070cc, 0x00000000}, -+ {0xce0070d0, 0x00000000}, -+ {0xce0070d4, 0x00000000}, -+ {0xce0070d8, 0x00000000}, -+ {0xce0070dc, 0x00000000}, -+ {0xce0070e0, 0x00000000}, -+ {0xce0070e4, 0x00000000}, -+ {0xce0070e8, 0x00000000}, -+ {0xce0070ec, 0x00000000}, -+ {0xce0070f0, 0x00000000}, -+ {0xce0070f4, 0x00000000}, -+ {0xce0070f8, 0x00000000}, -+ {0xce0070fc, 0x00000000}, -+ {0xce007100, 0x00000000}, -+ {0xce007104, 0x00000000}, -+ {0xce007108, 0x00000000}, -+ {0xce00710c, 0x00000000}, -+ {0xce007110, 0x00000000}, -+ {0xce007114, 0x00000000}, -+ {0xce007118, 0x00000000}, -+ {0xce00711c, 0x00000000}, -+ {0xce007120, 0x02000200}, -+ {0xce007124, 0x02000200}, -+ {0xce007128, 0x02000200}, -+ {0xce00712c, 0x02000200}, -+ {0xce007130, 0x02000200}, -+ {0xce007134, 0x02000200}, -+ {0xce007138, 0x02000200}, -+ {0xce00713c, 0x02000200}, -+ {0xce007140, 0x02000200}, -+ {0xce007144, 0x02000200}, -+ {0xce007148, 0x02000200}, -+ {0xce00714c, 0x02000200}, -+ {0xce007150, 0x02000200}, -+ {0xce007154, 0x02000200}, -+ {0xce007158, 0x00000000}, -+ {0xce00715c, 0x00000000}, -+ {0xce007160, 0x00000000}, -+ {0xce007164, 0x00000000}, -+ {0xce007168, 0x00000000}, -+ {0xce00716c, 0x00000000}, -+ {0xce007170, 0x00000000}, -+ {0xce007174, 0x00000000}, -+ {0xce007178, 0x00000000}, -+ {0xce00717c, 0x00000000}, -+ {0xce007180, 0x00000000}, -+ {0xce007184, 0x00000000}, -+ {0xce007188, 0x00000000}, -+ {0xce00718c, 0x00000000}, -+ {0xce007190, 0x00000000}, -+ {0xce007194, 0x00000000}, -+ {0xce007198, 0x00000000}, -+ {0xce00719c, 0x00000000}, -+ {0xce0071a0, 0x00000000}, -+ {0xce0071a4, 0x00000000}, -+ {0xce0071a8, 0x00000000}, -+ {0xce0071ac, 0x00000000}, -+ {0xce0071b0, 0x00000000}, -+ {0xce0071b4, 0x00000100}, -+ {0xce0071b8, 0x00000000}, -+ {0xce0071c0, 0x00000000}, -+ {0xce0071c4, 0x00000000}, -+ {0xce0071c8, 0x00000000}, -+ {0xce0071cc, 0x00000000}, -+ {0xce0071d0, 0x00000000}, -+ {0xce0071d4, 0x00000000}, -+ {0xce0071d8, 0x00000000}, -+ {0xce0071dc, 0x00000000}, -+ {0xce0071e0, 0x00000000}, -+ {0xce0071e4, 0x00000000}, -+ {0xce0071e8, 0x00000000}, -+ {0xce0071ec, 0x00000000}, -+ {0xce0071f0, 0x00000000}, -+ {0xce0071f4, 0x00000000}, -+ {0xce0071f8, 0x00000000}, -+ {0xce0071fc, 0x00000000}, -+ {0xce0043fc, 0x000104E5}, -+ {0xce007044, 0x00028080}, -+ {0xce000000, 0x80000016}, -+}; -+ -+static const u32 wifi_tx_gain[] = { -+ 0x79807980, -+ 0x72797279, -+ 0x6C726C72, -+ 0x666C666C, -+ 0x60666066, -+ 0x5B605B60, -+ 0x565B565B, -+ 0x51565156, -+ 0x4C514C51, -+ 0x484C484C, -+ 0x44484448, -+ 0x40444044, -+ 0x3C403C40, -+ 0x3A3D3A3D, -+ 0x36393639, -+}; -+ -+static ssv_cabrio_reg asic_rf_setting[] = { -+ {0xCE010038, 0x0003E07C}, -+ {0xCE010060, 0x00406000}, -+ {0xCE01009C, 0x00000024}, -+ {0xCE0100A0, 0x00EC4CC5}, -+ {0xCE010000, 0x40002000}, -+ {0xCE010004, 0x00020FC0}, -+ {0xCE010008, 0x000DF69B}, -+ {0xCE010014, 0x3D3E84FE}, -+ {0xCE010018, 0x01457D79}, -+ {0xCE01001C, 0x000103A7}, -+ {0xCE010020, 0x000103A6}, -+ {0xCE01002C, 0x00032CA8}, -+ {0xCE010048, 0xFCCCCF27}, -+ {0xCE010050, 0x00444000}, -+ {0xCE01000C, 0x151558C5}, -+ {0xCE010010, 0x01011A88}, -+ {0xCE010024, 0x00012001}, -+ {0xCE010028, 0x00036000}, -+ {0xCE010030, 0x20EA0224}, -+ {0xCE010034, 0x44000755}, -+ {0xCE01003C, 0x55D89D8A}, -+ {0xCE010040, 0x005508BB}, -+ {0xCE010044, 0x07C08BFF}, -+ {0xCE01004C, 0x07700830}, -+ {0xCE010054, 0x00007FF4}, -+ {0xCE010058, 0x0000000E}, -+ {0xCE01005C, 0x00088018}, -+ {0xCE010064, 0x08820820}, -+ {0xCE010068, 0x00820820}, -+ {0xCE01006C, 0x00820820}, -+ {0xCE010070, 0x00820820}, -+ {0xCE010074, 0x00820820}, -+ {0xCE010078, 0x00820820}, -+ {0xCE01007C, 0x00820820}, -+ {0xCE010080, 0x00820820}, -+ {0xCE010084, 0x00004080}, -+ {0xCE010088, 0x200800FE}, -+ {0xCE01008C, 0xAAAAAAAA}, -+ {0xCE010090, 0xAAAAAAAA}, -+ {0xCE010094, 0x0000A487}, -+ {0xCE010098, 0x0000070E}, -+ {0xCE0100A4, 0x00000F43}, -+ {0xCE0100A8, 0x00098900}, -+ {0xCE0100AC, 0x00000000}, -+ {0xC00003AC, 0x00000000}, -+ {0xC00003B0, 0x00000000}, -+ {0xC00003B4, 0x00000000}, -+ {0xC00003BC, 0x00000000}, -+ {0xC0001D00, 0x5E000040}, -+ {0xC0001D04, 0x015D015D}, -+ {0xC0001D08, 0x00000001}, -+ {0xC0001D0C, 0x55550000}, -+ {0xC0001D20, 0x7FFF0000}, -+ {0xC0001D24, 0x00000003}, -+ {0xC0001D28, 0x00000000}, -+ {0xC0001D2C, 0x00000000}, -+}; -diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h -@@ -0,0 +1,9694 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#define SYS_REG_BASE 0xc0000000 -+#define WBOOT_REG_BASE 0xc0000100 -+#define TU0_US_REG_BASE 0xc0000200 -+#define TU1_US_REG_BASE 0xc0000210 -+#define TU2_US_REG_BASE 0xc0000220 -+#define TU3_US_REG_BASE 0xc0000230 -+#define TM0_MS_REG_BASE 0xc0000240 -+#define TM1_MS_REG_BASE 0xc0000250 -+#define TM2_MS_REG_BASE 0xc0000260 -+#define TM3_MS_REG_BASE 0xc0000270 -+#define MCU_WDT_REG_BASE 0xc0000280 -+#define SYS_WDT_REG_BASE 0xc0000284 -+#define GPIO_REG_BASE 0xc0000300 -+#define SD_REG_BASE 0xc0000800 -+#define SPI_REG_BASE 0xc0000a00 -+#define CSR_I2C_MST_BASE 0xc0000b00 -+#define UART_REG_BASE 0xc0000c00 -+#define DAT_UART_REG_BASE 0xc0000d00 -+#define INT_REG_BASE 0xc0000e00 -+#define DBG_SPI_REG_BASE 0xc0000f00 -+#define FLASH_SPI_REG_BASE 0xc0001000 -+#define DMA_REG_BASE 0xc0001c00 -+#define CSR_PMU_BASE 0xc0001d00 -+#define CSR_RTC_BASE 0xc0001d20 -+#define RTC_RAM_BASE 0xc0001d80 -+#define D2_DMA_REG_BASE 0xc0001e00 -+#define HCI_REG_BASE 0xc1000000 -+#define CO_REG_BASE 0xc2000000 -+#define EFS_REG_BASE 0xc2000100 -+#define SMS4_REG_BASE 0xc3000000 -+#define MRX_REG_BASE 0xc6000000 -+#define AMPDU_REG_BASE 0xc6001000 -+#define MT_REG_CSR_BASE 0xc6002000 -+#define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100 -+#define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200 -+#define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300 -+#define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400 -+#define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500 -+#define HIF_INFO_BASE 0xca000000 -+#define PHY_RATE_INFO_BASE 0xca000200 -+#define MAC_GLB_SET_BASE 0xca000300 -+#define BTCX_REG_BASE 0xca000400 -+#define MIB_REG_BASE 0xca000800 -+#define CBR_A_REG_BASE 0xcb000000 -+#define MB_REG_BASE 0xcd000000 -+#define ID_MNG_REG_BASE 0xcd010000 -+#define CSR_PHY_BASE 0xce000000 -+#define CSR_RF_BASE 0xce010000 -+#define MMU_REG_BASE 0xcf000000 -+#define SYS_REG_BANK_SIZE 0x000000b4 -+#define WBOOT_REG_BANK_SIZE 0x0000000c -+#define TU0_US_REG_BANK_SIZE 0x00000010 -+#define TU1_US_REG_BANK_SIZE 0x00000010 -+#define TU2_US_REG_BANK_SIZE 0x00000010 -+#define TU3_US_REG_BANK_SIZE 0x00000010 -+#define TM0_MS_REG_BANK_SIZE 0x00000010 -+#define TM1_MS_REG_BANK_SIZE 0x00000010 -+#define TM2_MS_REG_BANK_SIZE 0x00000010 -+#define TM3_MS_REG_BANK_SIZE 0x00000010 -+#define MCU_WDT_REG_BANK_SIZE 0x00000004 -+#define SYS_WDT_REG_BANK_SIZE 0x00000004 -+#define GPIO_REG_BANK_SIZE 0x000000d4 -+#define SD_REG_BANK_SIZE 0x00000180 -+#define SPI_REG_BANK_SIZE 0x00000040 -+#define CSR_I2C_MST_BANK_SIZE 0x00000018 -+#define UART_REG_BANK_SIZE 0x00000028 -+#define DAT_UART_REG_BANK_SIZE 0x00000028 -+#define INT_REG_BANK_SIZE 0x0000004c -+#define DBG_SPI_REG_BANK_SIZE 0x00000040 -+#define FLASH_SPI_REG_BANK_SIZE 0x0000002c -+#define DMA_REG_BANK_SIZE 0x00000014 -+#define CSR_PMU_BANK_SIZE 0x00000100 -+#define CSR_RTC_BANK_SIZE 0x000000e0 -+#define RTC_RAM_BANK_SIZE 0x00000080 -+#define D2_DMA_REG_BANK_SIZE 0x00000014 -+#define HCI_REG_BANK_SIZE 0x000000cc -+#define CO_REG_BANK_SIZE 0x000000ac -+#define EFS_REG_BANK_SIZE 0x0000006c -+#define SMS4_REG_BANK_SIZE 0x00000070 -+#define MRX_REG_BANK_SIZE 0x00000198 -+#define AMPDU_REG_BANK_SIZE 0x00000014 -+#define MT_REG_CSR_BANK_SIZE 0x00000100 -+#define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x0000001c -+#define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x0000001c -+#define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x0000001c -+#define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x0000001c -+#define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x0000001c -+#define HIF_INFO_BANK_SIZE 0x0000009c -+#define PHY_RATE_INFO_BANK_SIZE 0x000000b8 -+#define MAC_GLB_SET_BANK_SIZE 0x0000003c -+#define BTCX_REG_BANK_SIZE 0x0000000c -+#define MIB_REG_BANK_SIZE 0x00000480 -+#define CBR_A_REG_BANK_SIZE 0x001203fc -+#define MB_REG_BANK_SIZE 0x000000a0 -+#define ID_MNG_REG_BANK_SIZE 0x00000084 -+#define CSR_PHY_BANK_SIZE 0x000071c0 -+#define CSR_RF_BANK_SIZE 0x000000b0 -+#define MMU_REG_BANK_SIZE 0x000000c0 -+#define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000) -+#define ADR_BOOT (SYS_REG_BASE+0x00000004) -+#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008) -+#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c) -+#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010) -+#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014) -+#define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018) -+#define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c) -+#define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020) -+#define ADR_MCU_DBG_SEL (SYS_REG_BASE+0x00000024) -+#define ADR_MCU_DBG_DATA (SYS_REG_BASE+0x00000028) -+#define ADR_AHB_BRG_STATUS (SYS_REG_BASE+0x0000002c) -+#define ADR_BIST_BIST_CTRL (SYS_REG_BASE+0x00000030) -+#define ADR_BIST_MODE_REG_IN (SYS_REG_BASE+0x00000034) -+#define ADR_BIST_MODE_REG_OUT (SYS_REG_BASE+0x00000038) -+#define ADR_BIST_MONITOR_BUS_LSB (SYS_REG_BASE+0x0000003c) -+#define ADR_BIST_MONITOR_BUS_MSB (SYS_REG_BASE+0x00000040) -+#define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044) -+#define ADR_TB_RDATA (SYS_REG_BASE+0x00000048) -+#define ADR_UART_W2B (SYS_REG_BASE+0x0000004c) -+#define ADR_AHB_ILL_ADDR (SYS_REG_BASE+0x00000050) -+#define ADR_AHB_FEN_ADDR (SYS_REG_BASE+0x00000054) -+#define ADR_AHB_ILLFEN_STATUS (SYS_REG_BASE+0x00000058) -+#define ADR_PWM_A (SYS_REG_BASE+0x00000080) -+#define ADR_PWM_B (SYS_REG_BASE+0x00000084) -+#define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090) -+#define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094) -+#define ADR_PRESCALER_USTIMER (SYS_REG_BASE+0x000000a0) -+#define ADR_BIST_MODE_REG_IN_MMU (SYS_REG_BASE+0x000000a4) -+#define ADR_BIST_MODE_REG_OUT_MMU (SYS_REG_BASE+0x000000a8) -+#define ADR_BIST_MONITOR_BUS_MMU (SYS_REG_BASE+0x000000ac) -+#define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0) -+#define ADR_BOOT_INFO (WBOOT_REG_BASE+0x00000000) -+#define ADR_SD_INIT_CFG (WBOOT_REG_BASE+0x00000004) -+#define ADR_SPARE_UART_INFO (WBOOT_REG_BASE+0x00000008) -+#define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000) -+#define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004) -+#define ADR_TU0_DUMMY_BIT_0 (TU0_US_REG_BASE+0x00000008) -+#define ADR_TU0_DUMMY_BIT_1 (TU0_US_REG_BASE+0x0000000c) -+#define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000) -+#define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004) -+#define ADR_TU1_DUMMY_BIT_0 (TU1_US_REG_BASE+0x00000008) -+#define ADR_TU1_DUMMY_BIT_1 (TU1_US_REG_BASE+0x0000000c) -+#define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000) -+#define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004) -+#define ADR_TU2_DUMMY_BIT_0 (TU2_US_REG_BASE+0x00000008) -+#define ADR_TU2_DUMMY_BIT_1 (TU2_US_REG_BASE+0x0000000c) -+#define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000) -+#define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004) -+#define ADR_TU3_DUMMY_BIT_0 (TU3_US_REG_BASE+0x00000008) -+#define ADR_TU3_DUMMY_BIT_1 (TU3_US_REG_BASE+0x0000000c) -+#define ADR_TM0_MILISECOND_TIMER (TM0_MS_REG_BASE+0x00000000) -+#define ADR_TM0_CURRENT_MILISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004) -+#define ADR_TM0_DUMMY_BIT_0 (TM0_MS_REG_BASE+0x00000008) -+#define ADR_TM0_DUMMY_BIT_1 (TM0_MS_REG_BASE+0x0000000c) -+#define ADR_TM1_MILISECOND_TIMER (TM1_MS_REG_BASE+0x00000000) -+#define ADR_TM1_CURRENT_MILISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004) -+#define ADR_TM1_DUMMY_BIT_0 (TM1_MS_REG_BASE+0x00000008) -+#define ADR_TM1_DUMMY_BIT_1 (TM1_MS_REG_BASE+0x0000000c) -+#define ADR_TM2_MILISECOND_TIMER (TM2_MS_REG_BASE+0x00000000) -+#define ADR_TM2_CURRENT_MILISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004) -+#define ADR_TM2_DUMMY_BIT_0 (TM2_MS_REG_BASE+0x00000008) -+#define ADR_TM2_DUMMY_BIT_1 (TM2_MS_REG_BASE+0x0000000c) -+#define ADR_TM3_MILISECOND_TIMER (TM3_MS_REG_BASE+0x00000000) -+#define ADR_TM3_CURRENT_MILISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004) -+#define ADR_TM3_DUMMY_BIT_0 (TM3_MS_REG_BASE+0x00000008) -+#define ADR_TM3_DUMMY_BIT_1 (TM3_MS_REG_BASE+0x0000000c) -+#define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000) -+#define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000) -+#define ADR_PAD6 (GPIO_REG_BASE+0x00000000) -+#define ADR_PAD7 (GPIO_REG_BASE+0x00000004) -+#define ADR_PAD8 (GPIO_REG_BASE+0x00000008) -+#define ADR_PAD9 (GPIO_REG_BASE+0x0000000c) -+#define ADR_PAD11 (GPIO_REG_BASE+0x00000010) -+#define ADR_PAD15 (GPIO_REG_BASE+0x00000014) -+#define ADR_PAD16 (GPIO_REG_BASE+0x00000018) -+#define ADR_PAD17 (GPIO_REG_BASE+0x0000001c) -+#define ADR_PAD18 (GPIO_REG_BASE+0x00000020) -+#define ADR_PAD19 (GPIO_REG_BASE+0x00000024) -+#define ADR_PAD20 (GPIO_REG_BASE+0x00000028) -+#define ADR_PAD21 (GPIO_REG_BASE+0x0000002c) -+#define ADR_PAD22 (GPIO_REG_BASE+0x00000030) -+#define ADR_PAD24 (GPIO_REG_BASE+0x00000034) -+#define ADR_PAD25 (GPIO_REG_BASE+0x00000038) -+#define ADR_PAD27 (GPIO_REG_BASE+0x0000003c) -+#define ADR_PAD28 (GPIO_REG_BASE+0x00000040) -+#define ADR_PAD29 (GPIO_REG_BASE+0x00000044) -+#define ADR_PAD30 (GPIO_REG_BASE+0x00000048) -+#define ADR_PAD31 (GPIO_REG_BASE+0x0000004c) -+#define ADR_PAD32 (GPIO_REG_BASE+0x00000050) -+#define ADR_PAD33 (GPIO_REG_BASE+0x00000054) -+#define ADR_PAD34 (GPIO_REG_BASE+0x00000058) -+#define ADR_PAD42 (GPIO_REG_BASE+0x0000005c) -+#define ADR_PAD43 (GPIO_REG_BASE+0x00000060) -+#define ADR_PAD44 (GPIO_REG_BASE+0x00000064) -+#define ADR_PAD45 (GPIO_REG_BASE+0x00000068) -+#define ADR_PAD46 (GPIO_REG_BASE+0x0000006c) -+#define ADR_PAD47 (GPIO_REG_BASE+0x00000070) -+#define ADR_PAD48 (GPIO_REG_BASE+0x00000074) -+#define ADR_PAD49 (GPIO_REG_BASE+0x00000078) -+#define ADR_PAD50 (GPIO_REG_BASE+0x0000007c) -+#define ADR_PAD51 (GPIO_REG_BASE+0x00000080) -+#define ADR_PAD52 (GPIO_REG_BASE+0x00000084) -+#define ADR_PAD53 (GPIO_REG_BASE+0x00000088) -+#define ADR_PAD54 (GPIO_REG_BASE+0x0000008c) -+#define ADR_PAD56 (GPIO_REG_BASE+0x00000090) -+#define ADR_PAD57 (GPIO_REG_BASE+0x00000094) -+#define ADR_PAD58 (GPIO_REG_BASE+0x00000098) -+#define ADR_PAD59 (GPIO_REG_BASE+0x0000009c) -+#define ADR_PAD60 (GPIO_REG_BASE+0x000000a0) -+#define ADR_PAD61 (GPIO_REG_BASE+0x000000a4) -+#define ADR_PAD62 (GPIO_REG_BASE+0x000000a8) -+#define ADR_PAD64 (GPIO_REG_BASE+0x000000ac) -+#define ADR_PAD65 (GPIO_REG_BASE+0x000000b0) -+#define ADR_PAD66 (GPIO_REG_BASE+0x000000b4) -+#define ADR_PAD68 (GPIO_REG_BASE+0x000000b8) -+#define ADR_PAD67 (GPIO_REG_BASE+0x000000bc) -+#define ADR_PAD69 (GPIO_REG_BASE+0x000000c0) -+#define ADR_PAD70 (GPIO_REG_BASE+0x000000c4) -+#define ADR_PAD231 (GPIO_REG_BASE+0x000000c8) -+#define ADR_PIN_SEL_0 (GPIO_REG_BASE+0x000000cc) -+#define ADR_PIN_SEL_1 (GPIO_REG_BASE+0x000000d0) -+#define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000) -+#define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004) -+#define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008) -+#define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c) -+#define ADR_CARD_PKT_STATUS_TEST (SD_REG_BASE+0x00000010) -+#define ADR_SYSTEM_INFORMATION_REG (SD_REG_BASE+0x0000001c) -+#define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020) -+#define ADR_SDIO_FIFO_WR_THLD_REG (SD_REG_BASE+0x00000024) -+#define ADR_SDIO_FIFO_WR_LIMIT_REG (SD_REG_BASE+0x00000028) -+#define ADR_SDIO_TX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x0000002c) -+#define ADR_SDIO_THLD_FOR_CMD53RD_REG (SD_REG_BASE+0x00000030) -+#define ADR_SDIO_RX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x00000034) -+#define ADR_SDIO_LOG_START_END_DATA_REG (SD_REG_BASE+0x00000038) -+#define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040) -+#define ADR_SDIO_LAST_CMD_INDEX_CRC_REG (SD_REG_BASE+0x00000044) -+#define ADR_SDIO_LAST_CMD_ARG_REG (SD_REG_BASE+0x00000048) -+#define ADR_SDIO_BUS_STATE_DEBUG_MONITOR (SD_REG_BASE+0x0000004c) -+#define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050) -+#define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054) -+#define ADR_CMD52_DATA_FOR_LAST_TIME (SD_REG_BASE+0x0000005c) -+#define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060) -+#define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064) -+#define ADR_IO_REG_PORT_REG (SD_REG_BASE+0x00000070) -+#define ADR_SDIO_FIFO_ERROR_CNT (SD_REG_BASE+0x0000007c) -+#define ADR_SDIO_CRC7_CRC16_ERROR_REG (SD_REG_BASE+0x00000080) -+#define ADR_SDIO_BLOCK_CNT_INFO (SD_REG_BASE+0x00000084) -+#define ADR_RX_DATA_CMD52_ABORT_COUNT (SD_REG_BASE+0x0000008c) -+#define ADR_FIFO_PTR_READ_BLOCK_CNT (SD_REG_BASE+0x00000090) -+#define ADR_TX_TIME_OUT_READ_CTRL (SD_REG_BASE+0x00000094) -+#define ADR_SDIO_TX_ALLOC_REG (SD_REG_BASE+0x00000098) -+#define ADR_SDIO_TX_INFORM (SD_REG_BASE+0x0000009c) -+#define ADR_F1_BLOCK_SIZE_0_REG (SD_REG_BASE+0x000000a0) -+#define ADR_SDIO_COMMAND_LOG_DATA_31_0 (SD_REG_BASE+0x000000b0) -+#define ADR_SDIO_COMMAND_LOG_DATA_63_32 (SD_REG_BASE+0x000000b4) -+#define ADR_SYSTEM_INFORMATION_REGISTER (SD_REG_BASE+0x000000bc) -+#define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0) -+#define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4) -+#define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8) -+#define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0) -+#define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0) -+#define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8) -+#define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100) -+#define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104) -+#define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108) -+#define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c) -+#define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110) -+#define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114) -+#define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118) -+#define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c) -+#define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120) -+#define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124) -+#define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128) -+#define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c) -+#define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130) -+#define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134) -+#define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138) -+#define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c) -+#define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140) -+#define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144) -+#define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148) -+#define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c) -+#define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150) -+#define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154) -+#define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158) -+#define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c) -+#define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160) -+#define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164) -+#define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168) -+#define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c) -+#define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170) -+#define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174) -+#define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178) -+#define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c) -+#define ADR_SPI_MODE (SPI_REG_BASE+0x00000000) -+#define ADR_RX_QUOTA (SPI_REG_BASE+0x00000004) -+#define ADR_CONDITION_NUMBER (SPI_REG_BASE+0x00000008) -+#define ADR_HOST_PATH (SPI_REG_BASE+0x0000000c) -+#define ADR_TX_SEG (SPI_REG_BASE+0x00000010) -+#define ADR_DEBUG_BURST_MODE (SPI_REG_BASE+0x00000014) -+#define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018) -+#define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c) -+#define ADR_SPI_STS (SPI_REG_BASE+0x00000020) -+#define ADR_TX_ALLOC_SET (SPI_REG_BASE+0x00000024) -+#define ADR_TX_ALLOC (SPI_REG_BASE+0x00000028) -+#define ADR_DBG_CNT (SPI_REG_BASE+0x0000002c) -+#define ADR_DBG_CNT2 (SPI_REG_BASE+0x00000030) -+#define ADR_DBG_CNT3 (SPI_REG_BASE+0x00000034) -+#define ADR_DBG_CNT4 (SPI_REG_BASE+0x00000038) -+#define ADR_INT_TAG (SPI_REG_BASE+0x0000003c) -+#define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000000) -+#define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000004) -+#define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x00000008) -+#define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x0000000c) -+#define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000010) -+#define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000014) -+#define ADR_UART_DATA (UART_REG_BASE+0x00000000) -+#define ADR_UART_IER (UART_REG_BASE+0x00000004) -+#define ADR_UART_FCR (UART_REG_BASE+0x00000008) -+#define ADR_UART_LCR (UART_REG_BASE+0x0000000c) -+#define ADR_UART_MCR (UART_REG_BASE+0x00000010) -+#define ADR_UART_LSR (UART_REG_BASE+0x00000014) -+#define ADR_UART_MSR (UART_REG_BASE+0x00000018) -+#define ADR_UART_SPR (UART_REG_BASE+0x0000001c) -+#define ADR_UART_RTHR (UART_REG_BASE+0x00000020) -+#define ADR_UART_ISR (UART_REG_BASE+0x00000024) -+#define ADR_DAT_UART_DATA (DAT_UART_REG_BASE+0x00000000) -+#define ADR_DAT_UART_IER (DAT_UART_REG_BASE+0x00000004) -+#define ADR_DAT_UART_FCR (DAT_UART_REG_BASE+0x00000008) -+#define ADR_DAT_UART_LCR (DAT_UART_REG_BASE+0x0000000c) -+#define ADR_DAT_UART_MCR (DAT_UART_REG_BASE+0x00000010) -+#define ADR_DAT_UART_LSR (DAT_UART_REG_BASE+0x00000014) -+#define ADR_DAT_UART_MSR (DAT_UART_REG_BASE+0x00000018) -+#define ADR_DAT_UART_SPR (DAT_UART_REG_BASE+0x0000001c) -+#define ADR_DAT_UART_RTHR (DAT_UART_REG_BASE+0x00000020) -+#define ADR_DAT_UART_ISR (DAT_UART_REG_BASE+0x00000024) -+#define ADR_INT_MASK (INT_REG_BASE+0x00000000) -+#define ADR_INT_MODE (INT_REG_BASE+0x00000004) -+#define ADR_INT_IRQ_STS (INT_REG_BASE+0x00000008) -+#define ADR_INT_FIQ_STS (INT_REG_BASE+0x0000000c) -+#define ADR_INT_IRQ_RAW (INT_REG_BASE+0x00000010) -+#define ADR_INT_FIQ_RAW (INT_REG_BASE+0x00000014) -+#define ADR_INT_PERI_MASK (INT_REG_BASE+0x00000018) -+#define ADR_INT_PERI_STS (INT_REG_BASE+0x0000001c) -+#define ADR_INT_PERI_RAW (INT_REG_BASE+0x00000020) -+#define ADR_INT_GPI_CFG (INT_REG_BASE+0x00000024) -+#define ADR_SYS_INT_FOR_HOST (INT_REG_BASE+0x00000028) -+#define ADR_SPI_IPC (INT_REG_BASE+0x00000034) -+#define ADR_SDIO_IPC (INT_REG_BASE+0x00000038) -+#define ADR_SDIO_MASK (INT_REG_BASE+0x0000003c) -+#define ADR_SDIO_IRQ_STS (INT_REG_BASE+0x00000040) -+#define ADR_SD_PERI_MASK (INT_REG_BASE+0x00000044) -+#define ADR_SD_PERI_STS (INT_REG_BASE+0x00000048) -+#define ADR_DBG_SPI_MODE (DBG_SPI_REG_BASE+0x00000000) -+#define ADR_DBG_RX_QUOTA (DBG_SPI_REG_BASE+0x00000004) -+#define ADR_DBG_CONDITION_NUMBER (DBG_SPI_REG_BASE+0x00000008) -+#define ADR_DBG_HOST_PATH (DBG_SPI_REG_BASE+0x0000000c) -+#define ADR_DBG_TX_SEG (DBG_SPI_REG_BASE+0x00000010) -+#define ADR_DBG_DEBUG_BURST_MODE (DBG_SPI_REG_BASE+0x00000014) -+#define ADR_DBG_SPI_TO_PHY_PARAM1 (DBG_SPI_REG_BASE+0x00000018) -+#define ADR_DBG_SPI_TO_PHY_PARAM2 (DBG_SPI_REG_BASE+0x0000001c) -+#define ADR_DBG_SPI_STS (DBG_SPI_REG_BASE+0x00000020) -+#define ADR_DBG_TX_ALLOC_SET (DBG_SPI_REG_BASE+0x00000024) -+#define ADR_DBG_TX_ALLOC (DBG_SPI_REG_BASE+0x00000028) -+#define ADR_DBG_DBG_CNT (DBG_SPI_REG_BASE+0x0000002c) -+#define ADR_DBG_DBG_CNT2 (DBG_SPI_REG_BASE+0x00000030) -+#define ADR_DBG_DBG_CNT3 (DBG_SPI_REG_BASE+0x00000034) -+#define ADR_DBG_DBG_CNT4 (DBG_SPI_REG_BASE+0x00000038) -+#define ADR_DBG_INT_TAG (DBG_SPI_REG_BASE+0x0000003c) -+#define ADR_BOOT_ADDR (FLASH_SPI_REG_BASE+0x00000000) -+#define ADR_VERIFY_DATA (FLASH_SPI_REG_BASE+0x00000004) -+#define ADR_FLASH_ADDR (FLASH_SPI_REG_BASE+0x00000008) -+#define ADR_SRAM_ADDR (FLASH_SPI_REG_BASE+0x0000000c) -+#define ADR_LEN (FLASH_SPI_REG_BASE+0x00000010) -+#define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000014) -+#define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x00000018) -+#define ADR_CHECK_SUM_RESULT (FLASH_SPI_REG_BASE+0x0000001c) -+#define ADR_CHECK_SUM_IN_FILE (FLASH_SPI_REG_BASE+0x00000020) -+#define ADR_COMMAND_LEN (FLASH_SPI_REG_BASE+0x00000024) -+#define ADR_COMMAND_ADDR (FLASH_SPI_REG_BASE+0x00000028) -+#define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000) -+#define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004) -+#define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008) -+#define ADR_DMA_INT (DMA_REG_BASE+0x0000000c) -+#define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010) -+#define ADR_PMU_0 (CSR_PMU_BASE+0x00000000) -+#define ADR_PMU_1 (CSR_PMU_BASE+0x00000004) -+#define ADR_PMU_2 (CSR_PMU_BASE+0x00000008) -+#define ADR_PMU_3 (CSR_PMU_BASE+0x0000000c) -+#define ADR_RTC_1 (CSR_RTC_BASE+0x00000000) -+#define ADR_RTC_2 (CSR_RTC_BASE+0x00000004) -+#define ADR_RTC_3W (CSR_RTC_BASE+0x00000008) -+#define ADR_RTC_3R (CSR_RTC_BASE+0x00000008) -+#define ADR_RTC_4 (CSR_RTC_BASE+0x0000000c) -+#define ADR_RTC_RAM (RTC_RAM_BASE+0x00000000) -+#define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000) -+#define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004) -+#define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008) -+#define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c) -+#define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010) -+#define ADR_CONTROL (HCI_REG_BASE+0x00000000) -+#define ADR_SDIO_WAKE_MODE (HCI_REG_BASE+0x00000004) -+#define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008) -+#define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c) -+#define ADR_THREASHOLD (HCI_REG_BASE+0x00000018) -+#define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020) -+#define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028) -+#define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030) -+#define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034) -+#define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050) -+#define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054) -+#define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060) -+#define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064) -+#define ADR_PACKET_COUNTER_INFO_0 (HCI_REG_BASE+0x00000070) -+#define ADR_PACKET_COUNTER_INFO_1 (HCI_REG_BASE+0x00000074) -+#define ADR_PACKET_COUNTER_INFO_2 (HCI_REG_BASE+0x00000078) -+#define ADR_PACKET_COUNTER_INFO_3 (HCI_REG_BASE+0x0000007c) -+#define ADR_PACKET_COUNTER_INFO_4 (HCI_REG_BASE+0x00000080) -+#define ADR_PACKET_COUNTER_INFO_5 (HCI_REG_BASE+0x00000084) -+#define ADR_PACKET_COUNTER_INFO_6 (HCI_REG_BASE+0x00000088) -+#define ADR_PACKET_COUNTER_INFO_7 (HCI_REG_BASE+0x0000008c) -+#define ADR_SDIO_TX_RX_FAIL_COUNTER_0 (HCI_REG_BASE+0x00000090) -+#define ADR_SDIO_TX_RX_FAIL_COUNTER_1 (HCI_REG_BASE+0x00000094) -+#define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a0) -+#define ADR_HCI_STATE_DEBUG_MODE_1 (HCI_REG_BASE+0x000000a4) -+#define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000a8) -+#define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000ac) -+#define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b0) -+#define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000b4) -+#define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000b8) -+#define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000bc) -+#define ADR_HCI_STATE_DEBUG_MODE_8 (HCI_REG_BASE+0x000000c0) -+#define ADR_HCI_STATE_DEBUG_MODE_9 (HCI_REG_BASE+0x000000c4) -+#define ADR_HCI_STATE_DEBUG_MODE_10 (HCI_REG_BASE+0x000000c8) -+#define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000) -+#define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004) -+#define ADR_CS_CMD (CO_REG_BASE+0x00000008) -+#define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c) -+#define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010) -+#define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014) -+#define ADR_RAND_EN (CO_REG_BASE+0x00000018) -+#define ADR_RAND_NUM (CO_REG_BASE+0x0000001c) -+#define ADR_MUL_OP1 (CO_REG_BASE+0x00000060) -+#define ADR_MUL_OP2 (CO_REG_BASE+0x00000064) -+#define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068) -+#define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c) -+#define ADR_DMA_RDATA (CO_REG_BASE+0x00000070) -+#define ADR_DMA_WDATA (CO_REG_BASE+0x00000074) -+#define ADR_DMA_LEN (CO_REG_BASE+0x00000078) -+#define ADR_DMA_CLR (CO_REG_BASE+0x0000007c) -+#define ADR_NAV_DATA (CO_REG_BASE+0x00000080) -+#define ADR_CO_NAV (CO_REG_BASE+0x00000084) -+#define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0) -+#define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4) -+#define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8) -+#define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000) -+#define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004) -+#define ADR_EFUSE_AHB_RDATA_0 (EFS_REG_BASE+0x00000008) -+#define ADR_EFUSE_WDATA_0 (EFS_REG_BASE+0x00000008) -+#define ADR_EFUSE_AHB_RDATA_1 (EFS_REG_BASE+0x0000000c) -+#define ADR_EFUSE_WDATA_1 (EFS_REG_BASE+0x0000000c) -+#define ADR_EFUSE_AHB_RDATA_2 (EFS_REG_BASE+0x00000010) -+#define ADR_EFUSE_WDATA_2 (EFS_REG_BASE+0x00000010) -+#define ADR_EFUSE_AHB_RDATA_3 (EFS_REG_BASE+0x00000014) -+#define ADR_EFUSE_WDATA_3 (EFS_REG_BASE+0x00000014) -+#define ADR_EFUSE_AHB_RDATA_4 (EFS_REG_BASE+0x00000018) -+#define ADR_EFUSE_WDATA_4 (EFS_REG_BASE+0x00000018) -+#define ADR_EFUSE_AHB_RDATA_5 (EFS_REG_BASE+0x0000001c) -+#define ADR_EFUSE_WDATA_5 (EFS_REG_BASE+0x0000001c) -+#define ADR_EFUSE_AHB_RDATA_6 (EFS_REG_BASE+0x00000020) -+#define ADR_EFUSE_WDATA_6 (EFS_REG_BASE+0x00000020) -+#define ADR_EFUSE_AHB_RDATA_7 (EFS_REG_BASE+0x00000024) -+#define ADR_EFUSE_WDATA_7 (EFS_REG_BASE+0x00000024) -+#define ADR_EFUSE_SPI_RD0_EN (EFS_REG_BASE+0x00000028) -+#define ADR_EFUSE_SPI_RD1_EN (EFS_REG_BASE+0x0000002c) -+#define ADR_EFUSE_SPI_RD2_EN (EFS_REG_BASE+0x00000030) -+#define ADR_EFUSE_SPI_RD3_EN (EFS_REG_BASE+0x00000034) -+#define ADR_EFUSE_SPI_RD4_EN (EFS_REG_BASE+0x00000038) -+#define ADR_EFUSE_SPI_RD5_EN (EFS_REG_BASE+0x0000003c) -+#define ADR_EFUSE_SPI_RD6_EN (EFS_REG_BASE+0x00000040) -+#define ADR_EFUSE_SPI_RD7_EN (EFS_REG_BASE+0x00000044) -+#define ADR_EFUSE_SPI_BUSY (EFS_REG_BASE+0x00000048) -+#define ADR_EFUSE_SPI_RDATA_0 (EFS_REG_BASE+0x0000004c) -+#define ADR_EFUSE_SPI_RDATA_1 (EFS_REG_BASE+0x00000050) -+#define ADR_EFUSE_SPI_RDATA_2 (EFS_REG_BASE+0x00000054) -+#define ADR_EFUSE_SPI_RDATA_3 (EFS_REG_BASE+0x00000058) -+#define ADR_EFUSE_SPI_RDATA_4 (EFS_REG_BASE+0x0000005c) -+#define ADR_EFUSE_SPI_RDATA_5 (EFS_REG_BASE+0x00000060) -+#define ADR_EFUSE_SPI_RDATA_6 (EFS_REG_BASE+0x00000064) -+#define ADR_EFUSE_SPI_RDATA_7 (EFS_REG_BASE+0x00000068) -+#define ADR_SMS4_CFG1 (SMS4_REG_BASE+0x00000000) -+#define ADR_SMS4_CFG2 (SMS4_REG_BASE+0x00000004) -+#define ADR_SMS4_MODE1 (SMS4_REG_BASE+0x00000008) -+#define ADR_SMS4_TRIG (SMS4_REG_BASE+0x00000010) -+#define ADR_SMS4_STATUS1 (SMS4_REG_BASE+0x00000014) -+#define ADR_SMS4_STATUS2 (SMS4_REG_BASE+0x00000018) -+#define ADR_SMS4_DATA_IN0 (SMS4_REG_BASE+0x00000020) -+#define ADR_SMS4_DATA_IN1 (SMS4_REG_BASE+0x00000024) -+#define ADR_SMS4_DATA_IN2 (SMS4_REG_BASE+0x00000028) -+#define ADR_SMS4_DATA_IN3 (SMS4_REG_BASE+0x0000002c) -+#define ADR_SMS4_DATA_OUT0 (SMS4_REG_BASE+0x00000030) -+#define ADR_SMS4_DATA_OUT1 (SMS4_REG_BASE+0x00000034) -+#define ADR_SMS4_DATA_OUT2 (SMS4_REG_BASE+0x00000038) -+#define ADR_SMS4_DATA_OUT3 (SMS4_REG_BASE+0x0000003c) -+#define ADR_SMS4_KEY_0 (SMS4_REG_BASE+0x00000040) -+#define ADR_SMS4_KEY_1 (SMS4_REG_BASE+0x00000044) -+#define ADR_SMS4_KEY_2 (SMS4_REG_BASE+0x00000048) -+#define ADR_SMS4_KEY_3 (SMS4_REG_BASE+0x0000004c) -+#define ADR_SMS4_MODE_IV0 (SMS4_REG_BASE+0x00000050) -+#define ADR_SMS4_MODE_IV1 (SMS4_REG_BASE+0x00000054) -+#define ADR_SMS4_MODE_IV2 (SMS4_REG_BASE+0x00000058) -+#define ADR_SMS4_MODE_IV3 (SMS4_REG_BASE+0x0000005c) -+#define ADR_SMS4_OFB_ENC0 (SMS4_REG_BASE+0x00000060) -+#define ADR_SMS4_OFB_ENC1 (SMS4_REG_BASE+0x00000064) -+#define ADR_SMS4_OFB_ENC2 (SMS4_REG_BASE+0x00000068) -+#define ADR_SMS4_OFB_ENC3 (SMS4_REG_BASE+0x0000006c) -+#define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000) -+#define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004) -+#define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008) -+#define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c) -+#define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010) -+#define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014) -+#define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018) -+#define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c) -+#define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020) -+#define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024) -+#define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028) -+#define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c) -+#define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030) -+#define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034) -+#define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038) -+#define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c) -+#define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040) -+#define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044) -+#define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048) -+#define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c) -+#define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050) -+#define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054) -+#define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070) -+#define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074) -+#define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078) -+#define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c) -+#define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080) -+#define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084) -+#define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088) -+#define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c) -+#define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090) -+#define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094) -+#define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098) -+#define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c) -+#define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0) -+#define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4) -+#define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8) -+#define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac) -+#define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0) -+#define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4) -+#define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8) -+#define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc) -+#define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0) -+#define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4) -+#define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8) -+#define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc) -+#define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0) -+#define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4) -+#define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0) -+#define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4) -+#define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8) -+#define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec) -+#define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0) -+#define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4) -+#define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8) -+#define ADR_BA_CTRL (MRX_REG_BASE+0x00000100) -+#define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104) -+#define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108) -+#define ADR_BA_TID (MRX_REG_BASE+0x0000010c) -+#define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110) -+#define ADR_BA_SB0 (MRX_REG_BASE+0x00000114) -+#define ADR_BA_SB1 (MRX_REG_BASE+0x00000118) -+#define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c) -+#define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120) -+#define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124) -+#define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128) -+#define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c) -+#define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130) -+#define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134) -+#define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138) -+#define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c) -+#define ADR_WSID0_TID0_RX_SEQ (MRX_REG_BASE+0x00000140) -+#define ADR_WSID0_TID1_RX_SEQ (MRX_REG_BASE+0x00000144) -+#define ADR_WSID0_TID2_RX_SEQ (MRX_REG_BASE+0x00000148) -+#define ADR_WSID0_TID3_RX_SEQ (MRX_REG_BASE+0x0000014c) -+#define ADR_WSID0_TID4_RX_SEQ (MRX_REG_BASE+0x00000150) -+#define ADR_WSID0_TID5_RX_SEQ (MRX_REG_BASE+0x00000154) -+#define ADR_WSID0_TID6_RX_SEQ (MRX_REG_BASE+0x00000158) -+#define ADR_WSID0_TID7_RX_SEQ (MRX_REG_BASE+0x0000015c) -+#define ADR_WSID1_TID0_RX_SEQ (MRX_REG_BASE+0x00000170) -+#define ADR_WSID1_TID1_RX_SEQ (MRX_REG_BASE+0x00000174) -+#define ADR_WSID1_TID2_RX_SEQ (MRX_REG_BASE+0x00000178) -+#define ADR_WSID1_TID3_RX_SEQ (MRX_REG_BASE+0x0000017c) -+#define ADR_WSID1_TID4_RX_SEQ (MRX_REG_BASE+0x00000180) -+#define ADR_WSID1_TID5_RX_SEQ (MRX_REG_BASE+0x00000184) -+#define ADR_WSID1_TID6_RX_SEQ (MRX_REG_BASE+0x00000188) -+#define ADR_WSID1_TID7_RX_SEQ (MRX_REG_BASE+0x0000018c) -+#define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000190) -+#define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000194) -+#define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000) -+#define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004) -+#define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008) -+#define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c) -+#define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010) -+#define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000) -+#define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004) -+#define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008) -+#define ADR_MTX_EDCCA_TOUT (MT_REG_CSR_BASE+0x00000010) -+#define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0) -+#define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4) -+#define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8) -+#define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac) -+#define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0) -+#define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4) -+#define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8) -+#define ADR_MTX_BCN_CFG0 (MT_REG_CSR_BASE+0x000000bc) -+#define ADR_MTX_BCN_CFG1 (MT_REG_CSR_BASE+0x000000c0) -+#define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc) -+#define ADR_MTX_DBG_CTRL (MT_REG_CSR_BASE+0x000000d0) -+#define ADR_MTX_DBG_DAT0 (MT_REG_CSR_BASE+0x000000d4) -+#define ADR_MTX_DBG_DAT1 (MT_REG_CSR_BASE+0x000000d8) -+#define ADR_MTX_DBG_DAT2 (MT_REG_CSR_BASE+0x000000dc) -+#define ADR_MTX_DUR_TOUT (MT_REG_CSR_BASE+0x000000e0) -+#define ADR_MTX_DUR_IFS (MT_REG_CSR_BASE+0x000000e4) -+#define ADR_MTX_DUR_SIFS_G (MT_REG_CSR_BASE+0x000000e8) -+#define ADR_MTX_DBG_DAT3 (MT_REG_CSR_BASE+0x000000ec) -+#define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0) -+#define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x000000f4) -+#define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x000000f8) -+#define ADR_MTX_DBG_DAT4 (MT_REG_CSR_BASE+0x000000fc) -+#define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000) -+#define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004) -+#define ADR_TXQ0_MTX_Q_BKF_CNT (TXQ0_MT_Q_REG_CSR_BASE+0x00000008) -+#define ADR_TXQ0_MTX_Q_RC_LIMIT (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c) -+#define ADR_TXQ0_MTX_Q_ID_MAP_L (TXQ0_MT_Q_REG_CSR_BASE+0x00000010) -+#define ADR_TXQ0_MTX_Q_TXOP_CH_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000014) -+#define ADR_TXQ0_MTX_Q_TXOP_OV_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000018) -+#define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000) -+#define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004) -+#define ADR_TXQ1_MTX_Q_BKF_CNT (TXQ1_MT_Q_REG_CSR_BASE+0x00000008) -+#define ADR_TXQ1_MTX_Q_RC_LIMIT (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c) -+#define ADR_TXQ1_MTX_Q_ID_MAP_L (TXQ1_MT_Q_REG_CSR_BASE+0x00000010) -+#define ADR_TXQ1_MTX_Q_TXOP_CH_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000014) -+#define ADR_TXQ1_MTX_Q_TXOP_OV_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000018) -+#define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000) -+#define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004) -+#define ADR_TXQ2_MTX_Q_BKF_CNT (TXQ2_MT_Q_REG_CSR_BASE+0x00000008) -+#define ADR_TXQ2_MTX_Q_RC_LIMIT (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c) -+#define ADR_TXQ2_MTX_Q_ID_MAP_L (TXQ2_MT_Q_REG_CSR_BASE+0x00000010) -+#define ADR_TXQ2_MTX_Q_TXOP_CH_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000014) -+#define ADR_TXQ2_MTX_Q_TXOP_OV_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000018) -+#define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000) -+#define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004) -+#define ADR_TXQ3_MTX_Q_BKF_CNT (TXQ3_MT_Q_REG_CSR_BASE+0x00000008) -+#define ADR_TXQ3_MTX_Q_RC_LIMIT (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c) -+#define ADR_TXQ3_MTX_Q_ID_MAP_L (TXQ3_MT_Q_REG_CSR_BASE+0x00000010) -+#define ADR_TXQ3_MTX_Q_TXOP_CH_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000014) -+#define ADR_TXQ3_MTX_Q_TXOP_OV_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000018) -+#define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000) -+#define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004) -+#define ADR_TXQ4_MTX_Q_BKF_CNT (TXQ4_MT_Q_REG_CSR_BASE+0x00000008) -+#define ADR_TXQ4_MTX_Q_RC_LIMIT (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c) -+#define ADR_TXQ4_MTX_Q_ID_MAP_L (TXQ4_MT_Q_REG_CSR_BASE+0x00000010) -+#define ADR_TXQ4_MTX_Q_TXOP_CH_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000014) -+#define ADR_TXQ4_MTX_Q_TXOP_OV_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000018) -+#define ADR_WSID0 (HIF_INFO_BASE+0x00000000) -+#define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004) -+#define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008) -+#define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c) -+#define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010) -+#define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014) -+#define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018) -+#define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c) -+#define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020) -+#define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024) -+#define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028) -+#define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c) -+#define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030) -+#define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034) -+#define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038) -+#define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c) -+#define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040) -+#define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044) -+#define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048) -+#define ADR_WSID1 (HIF_INFO_BASE+0x00000050) -+#define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054) -+#define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058) -+#define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c) -+#define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060) -+#define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064) -+#define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068) -+#define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c) -+#define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070) -+#define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074) -+#define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078) -+#define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c) -+#define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080) -+#define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084) -+#define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088) -+#define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c) -+#define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090) -+#define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094) -+#define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098) -+#define ADR_INFO0 (PHY_RATE_INFO_BASE+0x00000000) -+#define ADR_INFO1 (PHY_RATE_INFO_BASE+0x00000004) -+#define ADR_INFO2 (PHY_RATE_INFO_BASE+0x00000008) -+#define ADR_INFO3 (PHY_RATE_INFO_BASE+0x0000000c) -+#define ADR_INFO4 (PHY_RATE_INFO_BASE+0x00000010) -+#define ADR_INFO5 (PHY_RATE_INFO_BASE+0x00000014) -+#define ADR_INFO6 (PHY_RATE_INFO_BASE+0x00000018) -+#define ADR_INFO7 (PHY_RATE_INFO_BASE+0x0000001c) -+#define ADR_INFO8 (PHY_RATE_INFO_BASE+0x00000020) -+#define ADR_INFO9 (PHY_RATE_INFO_BASE+0x00000024) -+#define ADR_INFO10 (PHY_RATE_INFO_BASE+0x00000028) -+#define ADR_INFO11 (PHY_RATE_INFO_BASE+0x0000002c) -+#define ADR_INFO12 (PHY_RATE_INFO_BASE+0x00000030) -+#define ADR_INFO13 (PHY_RATE_INFO_BASE+0x00000034) -+#define ADR_INFO14 (PHY_RATE_INFO_BASE+0x00000038) -+#define ADR_INFO15 (PHY_RATE_INFO_BASE+0x0000003c) -+#define ADR_INFO16 (PHY_RATE_INFO_BASE+0x00000040) -+#define ADR_INFO17 (PHY_RATE_INFO_BASE+0x00000044) -+#define ADR_INFO18 (PHY_RATE_INFO_BASE+0x00000048) -+#define ADR_INFO19 (PHY_RATE_INFO_BASE+0x0000004c) -+#define ADR_INFO20 (PHY_RATE_INFO_BASE+0x00000050) -+#define ADR_INFO21 (PHY_RATE_INFO_BASE+0x00000054) -+#define ADR_INFO22 (PHY_RATE_INFO_BASE+0x00000058) -+#define ADR_INFO23 (PHY_RATE_INFO_BASE+0x0000005c) -+#define ADR_INFO24 (PHY_RATE_INFO_BASE+0x00000060) -+#define ADR_INFO25 (PHY_RATE_INFO_BASE+0x00000064) -+#define ADR_INFO26 (PHY_RATE_INFO_BASE+0x00000068) -+#define ADR_INFO27 (PHY_RATE_INFO_BASE+0x0000006c) -+#define ADR_INFO28 (PHY_RATE_INFO_BASE+0x00000070) -+#define ADR_INFO29 (PHY_RATE_INFO_BASE+0x00000074) -+#define ADR_INFO30 (PHY_RATE_INFO_BASE+0x00000078) -+#define ADR_INFO31 (PHY_RATE_INFO_BASE+0x0000007c) -+#define ADR_INFO32 (PHY_RATE_INFO_BASE+0x00000080) -+#define ADR_INFO33 (PHY_RATE_INFO_BASE+0x00000084) -+#define ADR_INFO34 (PHY_RATE_INFO_BASE+0x00000088) -+#define ADR_INFO35 (PHY_RATE_INFO_BASE+0x0000008c) -+#define ADR_INFO36 (PHY_RATE_INFO_BASE+0x00000090) -+#define ADR_INFO37 (PHY_RATE_INFO_BASE+0x00000094) -+#define ADR_INFO38 (PHY_RATE_INFO_BASE+0x00000098) -+#define ADR_INFO_MASK (PHY_RATE_INFO_BASE+0x0000009c) -+#define ADR_INFO_RATE_OFFSET (PHY_RATE_INFO_BASE+0x000000a0) -+#define ADR_INFO_IDX_ADDR (PHY_RATE_INFO_BASE+0x000000a4) -+#define ADR_INFO_LEN_ADDR (PHY_RATE_INFO_BASE+0x000000a8) -+#define ADR_IC_TIME_TAG_0 (PHY_RATE_INFO_BASE+0x000000ac) -+#define ADR_IC_TIME_TAG_1 (PHY_RATE_INFO_BASE+0x000000b0) -+#define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x000000b4) -+#define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000) -+#define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004) -+#define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008) -+#define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c) -+#define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010) -+#define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014) -+#define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018) -+#define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c) -+#define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020) -+#define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024) -+#define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028) -+#define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c) -+#define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000002c) -+#define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030) -+#define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034) -+#define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038) -+#define ADR_BTCX0 (BTCX_REG_BASE+0x00000000) -+#define ADR_BTCX1 (BTCX_REG_BASE+0x00000004) -+#define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008) -+#define ADR_MIB_EN (MIB_REG_BASE+0x00000000) -+#define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118) -+#define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128) -+#define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138) -+#define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148) -+#define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c) -+#define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170) -+#define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174) -+#define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178) -+#define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c) -+#define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180) -+#define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184) -+#define ADR_MTX_FRM (MIB_REG_BASE+0x00000188) -+#define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c) -+#define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190) -+#define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194) -+#define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198) -+#define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c) -+#define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0) -+#define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4) -+#define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8) -+#define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac) -+#define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0) -+#define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4) -+#define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8) -+#define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc) -+#define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0) -+#define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4) -+#define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8) -+#define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc) -+#define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0) -+#define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4) -+#define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8) -+#define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc) -+#define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218) -+#define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c) -+#define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220) -+#define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224) -+#define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268) -+#define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c) -+#define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270) -+#define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274) -+#define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318) -+#define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c) -+#define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320) -+#define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324) -+#define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368) -+#define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c) -+#define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370) -+#define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374) -+#define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418) -+#define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c) -+#define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420) -+#define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424) -+#define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428) -+#define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468) -+#define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c) -+#define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470) -+#define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474) -+#define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478) -+#define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c) -+#define ADR_CBR_HARD_WIRE_PIN_REGISTER (CBR_A_REG_BASE+0x00110000) -+#define ADR_CBR_MANUAL_ENABLE_REGISTER (CBR_A_REG_BASE+0x00110004) -+#define ADR_CBR_LDO_REGISTER (CBR_A_REG_BASE+0x00110008) -+#define ADR_CBR_ABB_REGISTER_1 (CBR_A_REG_BASE+0x0011000c) -+#define ADR_CBR_ABB_REGISTER_2 (CBR_A_REG_BASE+0x00110010) -+#define ADR_CBR_TX_FE_REGISTER (CBR_A_REG_BASE+0x00110014) -+#define ADR_CBR_RX_FE_REGISTER_1 (CBR_A_REG_BASE+0x00110018) -+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1 (CBR_A_REG_BASE+0x0011001c) -+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2 (CBR_A_REG_BASE+0x00110020) -+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3 (CBR_A_REG_BASE+0x00110024) -+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4 (CBR_A_REG_BASE+0x00110028) -+#define ADR_CBR_RX_FSM_REGISTER (CBR_A_REG_BASE+0x0011002c) -+#define ADR_CBR_RX_ADC_REGISTER (CBR_A_REG_BASE+0x00110030) -+#define ADR_CBR_TX_DAC_REGISTER (CBR_A_REG_BASE+0x00110034) -+#define ADR_CBR_SX_ENABLE_RGISTER (CBR_A_REG_BASE+0x00110038) -+#define ADR_CBR_SYN_RGISTER_1 (CBR_A_REG_BASE+0x0011003c) -+#define ADR_CBR_SYN_RGISTER_2 (CBR_A_REG_BASE+0x00110040) -+#define ADR_CBR_SYN_PFD_CHP (CBR_A_REG_BASE+0x00110044) -+#define ADR_CBR_SYN_VCO_LOBF (CBR_A_REG_BASE+0x00110048) -+#define ADR_CBR_SYN_DIV_SDM_XOSC (CBR_A_REG_BASE+0x0011004c) -+#define ADR_CBR_SYN_LCK1 (CBR_A_REG_BASE+0x00110050) -+#define ADR_CBR_SYN_LCK2 (CBR_A_REG_BASE+0x00110054) -+#define ADR_CBR_DPLL_VCO_REGISTER (CBR_A_REG_BASE+0x00110058) -+#define ADR_CBR_DPLL_CP_PFD_REGISTER (CBR_A_REG_BASE+0x0011005c) -+#define ADR_CBR_DPLL_DIVIDER_REGISTER (CBR_A_REG_BASE+0x00110060) -+#define ADR_CBR_DCOC_IDAC_REGISTER1 (CBR_A_REG_BASE+0x00110064) -+#define ADR_CBR_DCOC_IDAC_REGISTER2 (CBR_A_REG_BASE+0x00110068) -+#define ADR_CBR_DCOC_IDAC_REGISTER3 (CBR_A_REG_BASE+0x0011006c) -+#define ADR_CBR_DCOC_IDAC_REGISTER4 (CBR_A_REG_BASE+0x00110070) -+#define ADR_CBR_DCOC_IDAC_REGISTER5 (CBR_A_REG_BASE+0x00110074) -+#define ADR_CBR_DCOC_IDAC_REGISTER6 (CBR_A_REG_BASE+0x00110078) -+#define ADR_CBR_DCOC_IDAC_REGISTER7 (CBR_A_REG_BASE+0x0011007c) -+#define ADR_CBR_DCOC_IDAC_REGISTER8 (CBR_A_REG_BASE+0x00110080) -+#define ADR_CBR_RCAL_REGISTER (CBR_A_REG_BASE+0x00110084) -+#define ADR_CBR_MANUAL_REGISTER (CBR_A_REG_BASE+0x00110088) -+#define ADR_CBR_TRX_DUMMY_REGISTER (CBR_A_REG_BASE+0x0011008c) -+#define ADR_CBR_SX_DUMMY_REGISTER (CBR_A_REG_BASE+0x00110090) -+#define ADR_CBR_READ_ONLY_FLAGS_1 (CBR_A_REG_BASE+0x00110094) -+#define ADR_CBR_READ_ONLY_FLAGS_2 (CBR_A_REG_BASE+0x00110098) -+#define ADR_CBR_RG_PKT_GEN_0 (CBR_A_REG_BASE+0x00120080) -+#define ADR_CBR_RG_PKT_GEN_1 (CBR_A_REG_BASE+0x00120084) -+#define ADR_CBR_RG_PKT_GEN_2 (CBR_A_REG_BASE+0x00120088) -+#define ADR_CBR_RG_INTEGRATION (CBR_A_REG_BASE+0x00120090) -+#define ADR_CBR_RG_PKT_GEN_TXCNT (CBR_A_REG_BASE+0x00120094) -+#define ADR_CBR_PATTERN_GEN (CBR_A_REG_BASE+0x001203f8) -+#define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004) -+#define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008) -+#define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c) -+#define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010) -+#define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010) -+#define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014) -+#define ADR_MCU_STATUS (MB_REG_BASE+0x00000018) -+#define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c) -+#define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020) -+#define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024) -+#define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c) -+#define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030) -+#define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034) -+#define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038) -+#define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c) -+#define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040) -+#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044) -+#define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048) -+#define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c) -+#define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050) -+#define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054) -+#define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c) -+#define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070) -+#define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074) -+#define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078) -+#define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c) -+#define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080) -+#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084) -+#define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088) -+#define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c) -+#define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090) -+#define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094) -+#define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098) -+#define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c) -+#define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000) -+#define ADR_GETID (ID_MNG_REG_BASE+0x00000000) -+#define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004) -+#define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008) -+#define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c) -+#define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010) -+#define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014) -+#define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018) -+#define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c) -+#define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020) -+#define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024) -+#define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028) -+#define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c) -+#define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030) -+#define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034) -+#define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038) -+#define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c) -+#define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040) -+#define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044) -+#define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048) -+#define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c) -+#define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050) -+#define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054) -+#define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058) -+#define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c) -+#define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060) -+#define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064) -+#define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068) -+#define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c) -+#define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070) -+#define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074) -+#define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078) -+#define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c) -+#define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080) -+#define ADR_PHY_EN_0 (CSR_PHY_BASE+0x00000000) -+#define ADR_PHY_EN_1 (CSR_PHY_BASE+0x00000004) -+#define ADR_SVN_VERSION_REG (CSR_PHY_BASE+0x00000008) -+#define ADR_PHY_PKT_GEN_0 (CSR_PHY_BASE+0x0000000c) -+#define ADR_PHY_PKT_GEN_1 (CSR_PHY_BASE+0x00000010) -+#define ADR_PHY_PKT_GEN_2 (CSR_PHY_BASE+0x00000014) -+#define ADR_PHY_PKT_GEN_3 (CSR_PHY_BASE+0x00000018) -+#define ADR_PHY_PKT_GEN_4 (CSR_PHY_BASE+0x0000001c) -+#define ADR_PHY_REG_00 (CSR_PHY_BASE+0x00000020) -+#define ADR_PHY_REG_01 (CSR_PHY_BASE+0x0000002c) -+#define ADR_PHY_REG_02_AGC (CSR_PHY_BASE+0x00000030) -+#define ADR_PHY_REG_03_AGC (CSR_PHY_BASE+0x00000034) -+#define ADR_PHY_REG_04_AGC (CSR_PHY_BASE+0x00000038) -+#define ADR_PHY_REG_05_AGC (CSR_PHY_BASE+0x0000003c) -+#define ADR_PHY_REG_06_11B_DAGC (CSR_PHY_BASE+0x00000040) -+#define ADR_PHY_REG_07_11B_DAGC (CSR_PHY_BASE+0x00000044) -+#define ADR_PHY_REG_08_11GN_DAGC (CSR_PHY_BASE+0x00000048) -+#define ADR_PHY_REG_09_11GN_DAGC (CSR_PHY_BASE+0x0000004c) -+#define ADR_PHY_READ_REG_00_DIG_PWR (CSR_PHY_BASE+0x00000050) -+#define ADR_PHY_READ_REG_01_RF_GAIN_PWR (CSR_PHY_BASE+0x00000054) -+#define ADR_PHY_READ_REG_02_RF_GAIN_PWR (CSR_PHY_BASE+0x00000058) -+#define ADR_PHY_READ_REG_03_RF_GAIN_PWR (CSR_PHY_BASE+0x0000005c) -+#define ADR_PHY_REG_10_TX_DES (CSR_PHY_BASE+0x00000060) -+#define ADR_PHY_REG_11_TX_DES (CSR_PHY_BASE+0x00000064) -+#define ADR_PHY_REG_12_TX_DES (CSR_PHY_BASE+0x00000068) -+#define ADR_PHY_REG_13_RX_DES (CSR_PHY_BASE+0x0000006c) -+#define ADR_PHY_REG_14_RX_DES (CSR_PHY_BASE+0x00000070) -+#define ADR_PHY_REG_15_RX_DES (CSR_PHY_BASE+0x00000074) -+#define ADR_PHY_REG_16_TX_DES_EXCP (CSR_PHY_BASE+0x00000078) -+#define ADR_PHY_REG_17_TX_DES_EXCP (CSR_PHY_BASE+0x0000007c) -+#define ADR_PHY_REG_18_RSSI_SNR (CSR_PHY_BASE+0x00000080) -+#define ADR_PHY_REG_19_DAC_MANUAL (CSR_PHY_BASE+0x00000084) -+#define ADR_PHY_REG_20_MRX_CNT (CSR_PHY_BASE+0x00000088) -+#define ADR_PHY_REG_21_TRX_RAMP (CSR_PHY_BASE+0x00000094) -+#define ADR_PHY_REG_22_TRX_RAMP (CSR_PHY_BASE+0x00000098) -+#define ADR_PHY_REG_23_ANT (CSR_PHY_BASE+0x0000009c) -+#define ADR_PHY_REG_24_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a0) -+#define ADR_PHY_REG_25_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a4) -+#define ADR_PHY_REG_26_MRX_LEN_CNT (CSR_PHY_BASE+0x000000a8) -+#define ADR_PHY_REG_27_MRX_LEN_CNT (CSR_PHY_BASE+0x000000ac) -+#define ADR_PHY_READ_REG_04 (CSR_PHY_BASE+0x000000b0) -+#define ADR_PHY_READ_REG_05 (CSR_PHY_BASE+0x000000b4) -+#define ADR_PHY_REG_28_BIST (CSR_PHY_BASE+0x000000b8) -+#define ADR_PHY_READ_REG_06_BIST (CSR_PHY_BASE+0x000000d8) -+#define ADR_PHY_READ_REG_07_BIST (CSR_PHY_BASE+0x000000f0) -+#define ADR_PHY_REG_29_MTRX_MAC (CSR_PHY_BASE+0x000000fc) -+#define ADR_PHY_READ_REG_08_MTRX_MAC (CSR_PHY_BASE+0x00000100) -+#define ADR_PHY_READ_REG_09_MTRX_MAC (CSR_PHY_BASE+0x00000104) -+#define ADR_PHY_REG_30_TX_UP_FIL (CSR_PHY_BASE+0x00000108) -+#define ADR_PHY_REG_31_TX_UP_FIL (CSR_PHY_BASE+0x0000010c) -+#define ADR_PHY_REG_32_TX_UP_FIL (CSR_PHY_BASE+0x00000110) -+#define ADR_PHY_READ_TBUS (CSR_PHY_BASE+0x000003fc) -+#define ADR_TX_11B_FIL_COEF_00 (CSR_PHY_BASE+0x00001000) -+#define ADR_TX_11B_FIL_COEF_01 (CSR_PHY_BASE+0x00001004) -+#define ADR_TX_11B_FIL_COEF_02 (CSR_PHY_BASE+0x00001008) -+#define ADR_TX_11B_FIL_COEF_03 (CSR_PHY_BASE+0x0000100c) -+#define ADR_TX_11B_FIL_COEF_04 (CSR_PHY_BASE+0x00001010) -+#define ADR_TX_11B_FIL_COEF_05 (CSR_PHY_BASE+0x00001014) -+#define ADR_TX_11B_FIL_COEF_06 (CSR_PHY_BASE+0x00001018) -+#define ADR_TX_11B_FIL_COEF_07 (CSR_PHY_BASE+0x0000101c) -+#define ADR_TX_11B_FIL_COEF_08 (CSR_PHY_BASE+0x00001020) -+#define ADR_TX_11B_FIL_COEF_09 (CSR_PHY_BASE+0x00001024) -+#define ADR_TX_11B_FIL_COEF_10 (CSR_PHY_BASE+0x00001028) -+#define ADR_TX_11B_FIL_COEF_11 (CSR_PHY_BASE+0x0000102c) -+#define ADR_TX_11B_FIL_COEF_12 (CSR_PHY_BASE+0x00001030) -+#define ADR_TX_11B_FIL_COEF_13 (CSR_PHY_BASE+0x00001034) -+#define ADR_TX_11B_FIL_COEF_14 (CSR_PHY_BASE+0x00001038) -+#define ADR_TX_11B_FIL_COEF_15 (CSR_PHY_BASE+0x0000103c) -+#define ADR_TX_11B_FIL_COEF_16 (CSR_PHY_BASE+0x00001040) -+#define ADR_TX_11B_FIL_COEF_17 (CSR_PHY_BASE+0x00001044) -+#define ADR_TX_11B_FIL_COEF_18 (CSR_PHY_BASE+0x00001048) -+#define ADR_TX_11B_FIL_COEF_19 (CSR_PHY_BASE+0x0000104c) -+#define ADR_TX_11B_FIL_COEF_20 (CSR_PHY_BASE+0x00001050) -+#define ADR_TX_11B_FIL_COEF_21 (CSR_PHY_BASE+0x00001054) -+#define ADR_TX_11B_FIL_COEF_22 (CSR_PHY_BASE+0x00001058) -+#define ADR_TX_11B_FIL_COEF_23 (CSR_PHY_BASE+0x0000105c) -+#define ADR_TX_11B_FIL_COEF_24 (CSR_PHY_BASE+0x00001060) -+#define ADR_TX_11B_FIL_COEF_25 (CSR_PHY_BASE+0x00001064) -+#define ADR_TX_11B_FIL_COEF_26 (CSR_PHY_BASE+0x00001068) -+#define ADR_TX_11B_FIL_COEF_27 (CSR_PHY_BASE+0x0000106c) -+#define ADR_TX_11B_FIL_COEF_28 (CSR_PHY_BASE+0x00001070) -+#define ADR_TX_11B_FIL_COEF_29 (CSR_PHY_BASE+0x00001074) -+#define ADR_TX_11B_FIL_COEF_30 (CSR_PHY_BASE+0x00001078) -+#define ADR_TX_11B_FIL_COEF_31 (CSR_PHY_BASE+0x0000107c) -+#define ADR_TX_11B_FIL_COEF_32 (CSR_PHY_BASE+0x00001080) -+#define ADR_TX_11B_FIL_COEF_33 (CSR_PHY_BASE+0x00001084) -+#define ADR_TX_11B_FIL_COEF_34 (CSR_PHY_BASE+0x00001088) -+#define ADR_TX_11B_FIL_COEF_35 (CSR_PHY_BASE+0x0000108c) -+#define ADR_TX_11B_FIL_COEF_36 (CSR_PHY_BASE+0x00001090) -+#define ADR_TX_11B_FIL_COEF_37 (CSR_PHY_BASE+0x00001094) -+#define ADR_TX_11B_FIL_COEF_38 (CSR_PHY_BASE+0x00001098) -+#define ADR_TX_11B_FIL_COEF_39 (CSR_PHY_BASE+0x0000109c) -+#define ADR_TX_11B_FIL_COEF_40 (CSR_PHY_BASE+0x000010a0) -+#define ADR_TX_11B_PLCP (CSR_PHY_BASE+0x000010a4) -+#define ADR_TX_11B_RAMP (CSR_PHY_BASE+0x000010b4) -+#define ADR_TX_11B_EN_CNT_RST_N (CSR_PHY_BASE+0x000010d4) -+#define ADR_TX_11B_EN_CNT (CSR_PHY_BASE+0x000010d8) -+#define ADR_TX_11B_PKT_GEN_CNT (CSR_PHY_BASE+0x00001c00) -+#define ADR_RX_11B_DES_DLY (CSR_PHY_BASE+0x00002000) -+#define ADR_RX_11B_CCA_0 (CSR_PHY_BASE+0x00002004) -+#define ADR_RX_11B_CCA_1 (CSR_PHY_BASE+0x00002008) -+#define ADR_RX_11B_TR_KP_KI_0 (CSR_PHY_BASE+0x0000200c) -+#define ADR_RX_11B_TR_KP_KI_1 (CSR_PHY_BASE+0x00002010) -+#define ADR_RX_11B_CE_CNT_THRESHOLD (CSR_PHY_BASE+0x00002014) -+#define ADR_RX_11B_CE_MU_0 (CSR_PHY_BASE+0x00002018) -+#define ADR_RX_11B_CE_MU_1 (CSR_PHY_BASE+0x0000201c) -+#define ADR_RX_11B_EQ_MU_0 (CSR_PHY_BASE+0x00002020) -+#define ADR_RX_11B_EQ_MU_1 (CSR_PHY_BASE+0x00002024) -+#define ADR_RX_11B_EQ_CR_KP_KI (CSR_PHY_BASE+0x00002028) -+#define ADR_RX_11B_LPF_RATE (CSR_PHY_BASE+0x0000202c) -+#define ADR_RX_11B_CIT_CNT_THRESHOLD (CSR_PHY_BASE+0x00002030) -+#define ADR_RX_11B_EQ_CH_MAIN_TAP (CSR_PHY_BASE+0x00002034) -+#define ADR_RX_11B_SEARCH_CNT_TH (CSR_PHY_BASE+0x0000209c) -+#define ADR_RX_11B_CCA_CONTROL (CSR_PHY_BASE+0x000020a0) -+#define ADR_RX_11B_FREQUENCY_OFFSET (CSR_PHY_BASE+0x000023d4) -+#define ADR_RX_11B_SNR_RSSI (CSR_PHY_BASE+0x000023d8) -+#define ADR_RX_11B_SFD_CRC_CNT (CSR_PHY_BASE+0x000023e4) -+#define ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT (CSR_PHY_BASE+0x000023e8) -+#define ADR_RX_11B_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000023ec) -+#define ADR_RX_11B_SFD_FILED_0 (CSR_PHY_BASE+0x000023f0) -+#define ADR_RX_11B_SFD_FIELD_1 (CSR_PHY_BASE+0x000023f4) -+#define ADR_RX_11B_PKT_STAT_EN (CSR_PHY_BASE+0x000023f8) -+#define ADR_RX_11B_SOFT_RST (CSR_PHY_BASE+0x000023fc) -+#define ADR_TX_11GN_RAMP (CSR_PHY_BASE+0x000030a4) -+#define ADR_TX_11GN_PLCP (CSR_PHY_BASE+0x000030b8) -+#define ADR_TX_11GN_PKT_GEN_CNT (CSR_PHY_BASE+0x00003c00) -+#define ADR_TX_11GN_PLCP_CRC_ERR_CNT (CSR_PHY_BASE+0x00003c08) -+#define ADR_RX_11GN_DES_DLY (CSR_PHY_BASE+0x00004000) -+#define ADR_RX_11GN_TR_0 (CSR_PHY_BASE+0x00004004) -+#define ADR_RX_11GN_TR_1 (CSR_PHY_BASE+0x00004008) -+#define ADR_RX_11GN_TR_2 (CSR_PHY_BASE+0x0000400c) -+#define ADR_RX_11GN_CCA_0 (CSR_PHY_BASE+0x00004010) -+#define ADR_RX_11GN_CCA_1 (CSR_PHY_BASE+0x00004014) -+#define ADR_RX_11GN_CCA_2 (CSR_PHY_BASE+0x00004018) -+#define ADR_RX_11GN_CCA_FFT_SCALE (CSR_PHY_BASE+0x0000401c) -+#define ADR_RX_11GN_SOFT_DEMAP_0 (CSR_PHY_BASE+0x00004020) -+#define ADR_RX_11GN_SOFT_DEMAP_1 (CSR_PHY_BASE+0x00004024) -+#define ADR_RX_11GN_SOFT_DEMAP_2 (CSR_PHY_BASE+0x00004028) -+#define ADR_RX_11GN_SOFT_DEMAP_3 (CSR_PHY_BASE+0x0000402c) -+#define ADR_RX_11GN_SOFT_DEMAP_4 (CSR_PHY_BASE+0x00004030) -+#define ADR_RX_11GN_SOFT_DEMAP_5 (CSR_PHY_BASE+0x00004034) -+#define ADR_RX_11GN_SYM_BOUND_0 (CSR_PHY_BASE+0x00004038) -+#define ADR_RX_11GN_SYM_BOUND_1 (CSR_PHY_BASE+0x0000409c) -+#define ADR_RX_11GN_CCA_PWR (CSR_PHY_BASE+0x000040c0) -+#define ADR_RX_11GN_CCA_CNT (CSR_PHY_BASE+0x000040c4) -+#define ADR_RX_11GN_CCA_ATCOR_RE_CHECK (CSR_PHY_BASE+0x000040c8) -+#define ADR_RX_11GN_VTB_TB (CSR_PHY_BASE+0x00004130) -+#define ADR_RX_11GN_ERR_UPDATE (CSR_PHY_BASE+0x00004164) -+#define ADR_RX_11GN_SHORT_GI (CSR_PHY_BASE+0x00004180) -+#define ADR_RX_11GN_CHANNEL_UPDATE (CSR_PHY_BASE+0x00004188) -+#define ADR_RX_11GN_PKT_FORMAT_0 (CSR_PHY_BASE+0x00004190) -+#define ADR_RX_11GN_PKT_FORMAT_1 (CSR_PHY_BASE+0x00004194) -+#define ADR_RX_11GN_TX_TIME (CSR_PHY_BASE+0x00004380) -+#define ADR_RX_11GN_STBC_TR_KP_KI (CSR_PHY_BASE+0x00004384) -+#define ADR_RX_11GN_BIST_0 (CSR_PHY_BASE+0x00004388) -+#define ADR_RX_11GN_BIST_1 (CSR_PHY_BASE+0x0000438c) -+#define ADR_RX_11GN_BIST_2 (CSR_PHY_BASE+0x000043c0) -+#define ADR_RX_11GN_BIST_3 (CSR_PHY_BASE+0x000043c4) -+#define ADR_RX_11GN_BIST_4 (CSR_PHY_BASE+0x000043c8) -+#define ADR_RX_11GN_BIST_5 (CSR_PHY_BASE+0x000043cc) -+#define ADR_RX_11GN_SPECTRUM_ANALYZER (CSR_PHY_BASE+0x000043d4) -+#define ADR_RX_11GN_READ_0 (CSR_PHY_BASE+0x000043d8) -+#define ADR_RX_11GN_FREQ_OFFSET (CSR_PHY_BASE+0x000043dc) -+#define ADR_RX_11GN_SIGNAL_FIELD_0 (CSR_PHY_BASE+0x000043e0) -+#define ADR_RX_11GN_SIGNAL_FIELD_1 (CSR_PHY_BASE+0x000043e4) -+#define ADR_RX_11GN_PKT_ERR_CNT (CSR_PHY_BASE+0x000043e8) -+#define ADR_RX_11GN_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000043ec) -+#define ADR_RX_11GN_SERVICE_LENGTH_FIELD (CSR_PHY_BASE+0x000043f0) -+#define ADR_RX_11GN_RATE (CSR_PHY_BASE+0x000043f4) -+#define ADR_RX_11GN_STAT_EN (CSR_PHY_BASE+0x000043f8) -+#define ADR_RX_11GN_SOFT_RST (CSR_PHY_BASE+0x000043fc) -+#define ADR_RF_CONTROL_0 (CSR_PHY_BASE+0x00007000) -+#define ADR_RF_CONTROL_1 (CSR_PHY_BASE+0x00007004) -+#define ADR_TX_IQ_CONTROL_0 (CSR_PHY_BASE+0x00007040) -+#define ADR_TX_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007044) -+#define ADR_TX_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007048) -+#define ADR_TX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x0000704c) -+#define ADR_RX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x00007050) -+#define ADR_RX_OBSERVATION_CIRCUIT_0 (CSR_PHY_BASE+0x00007058) -+#define ADR_RX_OBSERVATION_CIRCUIT_1 (CSR_PHY_BASE+0x0000705c) -+#define ADR_RX_OBSERVATION_CIRCUIT_2 (CSR_PHY_BASE+0x00007060) -+#define ADR_RX_OBSERVATION_CIRCUIT_3 (CSR_PHY_BASE+0x00007064) -+#define ADR_RF_IQ_CONTROL_0 (CSR_PHY_BASE+0x0000706c) -+#define ADR_RF_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007070) -+#define ADR_RF_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007074) -+#define ADR_RF_IQ_CONTROL_3 (CSR_PHY_BASE+0x00007078) -+#define ADR_DPD_CONTROL (CSR_PHY_BASE+0x0000711c) -+#define ADR_DPD_GAIN_TABLE_0 (CSR_PHY_BASE+0x00007120) -+#define ADR_DPD_GAIN_TABLE_1 (CSR_PHY_BASE+0x00007124) -+#define ADR_DPD_GAIN_TABLE_2 (CSR_PHY_BASE+0x00007128) -+#define ADR_DPD_GAIN_TABLE_3 (CSR_PHY_BASE+0x00007130) -+#define ADR_DPD_GAIN_TABLE_4 (CSR_PHY_BASE+0x00007134) -+#define ADR_DPD_GAIN_TABLE_5 (CSR_PHY_BASE+0x00007138) -+#define ADR_DPD_GAIN_TABLE_6 (CSR_PHY_BASE+0x0000713c) -+#define ADR_DPD_GAIN_TABLE_7 (CSR_PHY_BASE+0x00007140) -+#define ADR_DPD_GAIN_TABLE_8 (CSR_PHY_BASE+0x00007144) -+#define ADR_DPD_GAIN_TABLE_9 (CSR_PHY_BASE+0x00007148) -+#define ADR_DPD_GAIN_TABLE_A (CSR_PHY_BASE+0x0000714c) -+#define ADR_DPD_GAIN_TABLE_B (CSR_PHY_BASE+0x00007150) -+#define ADR_DPD_GAIN_TABLE_C (CSR_PHY_BASE+0x00007154) -+#define ADR_DPD_PH_TABLE_0 (CSR_PHY_BASE+0x00007170) -+#define ADR_DPD_PH_TABLE_1 (CSR_PHY_BASE+0x00007174) -+#define ADR_DPD_PH_TABLE_2 (CSR_PHY_BASE+0x00007178) -+#define ADR_DPD_PH_TABLE_3 (CSR_PHY_BASE+0x00007180) -+#define ADR_DPD_PH_TABLE_4 (CSR_PHY_BASE+0x00007184) -+#define ADR_DPD_PH_TABLE_5 (CSR_PHY_BASE+0x00007188) -+#define ADR_DPD_PH_TABLE_6 (CSR_PHY_BASE+0x0000718c) -+#define ADR_DPD_PH_TABLE_7 (CSR_PHY_BASE+0x00007190) -+#define ADR_DPD_PH_TABLE_8 (CSR_PHY_BASE+0x00007194) -+#define ADR_DPD_PH_TABLE_9 (CSR_PHY_BASE+0x00007198) -+#define ADR_DPD_PH_TABLE_A (CSR_PHY_BASE+0x0000719c) -+#define ADR_DPD_PH_TABLE_B (CSR_PHY_BASE+0x000071a0) -+#define ADR_DPD_PH_TABLE_C (CSR_PHY_BASE+0x000071a4) -+#define ADR_DPD_GAIN_ESTIMATION_0 (CSR_PHY_BASE+0x000071b0) -+#define ADR_DPD_GAIN_ESTIMATION_1 (CSR_PHY_BASE+0x000071b4) -+#define ADR_DPD_GAIN_ESTIMATION_2 (CSR_PHY_BASE+0x000071b8) -+#define ADR_TX_GAIN_FACTOR (CSR_PHY_BASE+0x000071bc) -+#define ADR_HARD_WIRE_PIN_REGISTER (CSR_RF_BASE+0x00000000) -+#define ADR_MANUAL_ENABLE_REGISTER (CSR_RF_BASE+0x00000004) -+#define ADR_LDO_REGISTER (CSR_RF_BASE+0x00000008) -+#define ADR_ABB_REGISTER_1 (CSR_RF_BASE+0x0000000c) -+#define ADR_ABB_REGISTER_2 (CSR_RF_BASE+0x00000010) -+#define ADR_TX_FE_REGISTER (CSR_RF_BASE+0x00000014) -+#define ADR_RX_FE_REGISTER_1 (CSR_RF_BASE+0x00000018) -+#define ADR_RX_FE_GAIN_DECODER_REGISTER_1 (CSR_RF_BASE+0x0000001c) -+#define ADR_RX_FE_GAIN_DECODER_REGISTER_2 (CSR_RF_BASE+0x00000020) -+#define ADR_RX_FE_GAIN_DECODER_REGISTER_3 (CSR_RF_BASE+0x00000024) -+#define ADR_RX_FE_GAIN_DECODER_REGISTER_4 (CSR_RF_BASE+0x00000028) -+#define ADR_RX_TX_FSM_REGISTER (CSR_RF_BASE+0x0000002c) -+#define ADR_RX_ADC_REGISTER (CSR_RF_BASE+0x00000030) -+#define ADR_TX_DAC_REGISTER (CSR_RF_BASE+0x00000034) -+#define ADR_SX_ENABLE_REGISTER (CSR_RF_BASE+0x00000038) -+#define ADR_SYN_REGISTER_1 (CSR_RF_BASE+0x0000003c) -+#define ADR_SYN_REGISTER_2 (CSR_RF_BASE+0x00000040) -+#define ADR_SYN_PFD_CHP (CSR_RF_BASE+0x00000044) -+#define ADR_SYN_VCO_LOBF (CSR_RF_BASE+0x00000048) -+#define ADR_SYN_DIV_SDM_XOSC (CSR_RF_BASE+0x0000004c) -+#define ADR_SYN_KVCO_XO_FINE_TUNE_CBANK (CSR_RF_BASE+0x00000050) -+#define ADR_SYN_LCK_VT (CSR_RF_BASE+0x00000054) -+#define ADR_DPLL_VCO_REGISTER (CSR_RF_BASE+0x00000058) -+#define ADR_DPLL_CP_PFD_REGISTER (CSR_RF_BASE+0x0000005c) -+#define ADR_DPLL_DIVIDER_REGISTER (CSR_RF_BASE+0x00000060) -+#define ADR_DCOC_IDAC_REGISTER1 (CSR_RF_BASE+0x00000064) -+#define ADR_DCOC_IDAC_REGISTER2 (CSR_RF_BASE+0x00000068) -+#define ADR_DCOC_IDAC_REGISTER3 (CSR_RF_BASE+0x0000006c) -+#define ADR_DCOC_IDAC_REGISTER4 (CSR_RF_BASE+0x00000070) -+#define ADR_DCOC_IDAC_REGISTER5 (CSR_RF_BASE+0x00000074) -+#define ADR_DCOC_IDAC_REGISTER6 (CSR_RF_BASE+0x00000078) -+#define ADR_DCOC_IDAC_REGISTER7 (CSR_RF_BASE+0x0000007c) -+#define ADR_DCOC_IDAC_REGISTER8 (CSR_RF_BASE+0x00000080) -+#define ADR_RCAL_REGISTER (CSR_RF_BASE+0x00000084) -+#define ADR_SX_LCK_BIN_REGISTERS_I (CSR_RF_BASE+0x00000088) -+#define ADR_TRX_DUMMY_REGISTER (CSR_RF_BASE+0x0000008c) -+#define ADR_SX_DUMMY_REGISTER (CSR_RF_BASE+0x00000090) -+#define ADR_READ_ONLY_FLAGS_1 (CSR_RF_BASE+0x00000094) -+#define ADR_READ_ONLY_FLAGS_2 (CSR_RF_BASE+0x00000098) -+#define ADR_DPLL_FB_DIVIDER_REGISTERS_I (CSR_RF_BASE+0x0000009c) -+#define ADR_DPLL_FB_DIVIDER_REGISTERS_II (CSR_RF_BASE+0x000000a0) -+#define ADR_SX_LCK_BIN_REGISTERS_II (CSR_RF_BASE+0x000000a4) -+#define ADR_RC_OSC_32K_CAL_REGISTERS (CSR_RF_BASE+0x000000a8) -+#define ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER (CSR_RF_BASE+0x000000ac) -+#define ADR_MMU_CTRL (MMU_REG_BASE+0x00000000) -+#define ADR_HS_CTRL (MMU_REG_BASE+0x00000004) -+#define ADR_CPU_POR0_7 (MMU_REG_BASE+0x00000008) -+#define ADR_CPU_POR8_F (MMU_REG_BASE+0x0000000c) -+#define ADR_REG_LEN_CTRL (MMU_REG_BASE+0x00000010) -+#define ADR_DMN_READ_BYPASS (MMU_REG_BASE+0x00000014) -+#define ADR_ALC_RLS_ABORT (MMU_REG_BASE+0x00000018) -+#define ADR_DEBUG_CTL (MMU_REG_BASE+0x00000020) -+#define ADR_DEBUG_OUT (MMU_REG_BASE+0x00000024) -+#define ADR_MMU_STATUS (MMU_REG_BASE+0x00000028) -+#define ADR_DMN_STATUS (MMU_REG_BASE+0x0000002c) -+#define ADR_TAG_STATUS (MMU_REG_BASE+0x00000030) -+#define ADR_DMN_MCU_STATUS (MMU_REG_BASE+0x00000034) -+#define ADR_MB_IDTBL_0_STATUS (MMU_REG_BASE+0x00000040) -+#define ADR_MB_IDTBL_1_STATUS (MMU_REG_BASE+0x00000044) -+#define ADR_MB_IDTBL_2_STATUS (MMU_REG_BASE+0x00000048) -+#define ADR_MB_IDTBL_3_STATUS (MMU_REG_BASE+0x0000004c) -+#define ADR_PKT_IDTBL_0_STATUS (MMU_REG_BASE+0x00000050) -+#define ADR_PKT_IDTBL_1_STATUS (MMU_REG_BASE+0x00000054) -+#define ADR_PKT_IDTBL_2_STATUS (MMU_REG_BASE+0x00000058) -+#define ADR_PKT_IDTBL_3_STATUS (MMU_REG_BASE+0x0000005c) -+#define ADR_DMN_IDTBL_0_STATUS (MMU_REG_BASE+0x00000060) -+#define ADR_DMN_IDTBL_1_STATUS (MMU_REG_BASE+0x00000064) -+#define ADR_DMN_IDTBL_2_STATUS (MMU_REG_BASE+0x00000068) -+#define ADR_DMN_IDTBL_3_STATUS (MMU_REG_BASE+0x0000006c) -+#define ADR_MB_NEQID_0_STATUS (MMU_REG_BASE+0x00000070) -+#define ADR_MB_NEQID_1_STATUS (MMU_REG_BASE+0x00000074) -+#define ADR_MB_NEQID_2_STATUS (MMU_REG_BASE+0x00000078) -+#define ADR_MB_NEQID_3_STATUS (MMU_REG_BASE+0x0000007c) -+#define ADR_PKT_NEQID_0_STATUS (MMU_REG_BASE+0x00000080) -+#define ADR_PKT_NEQID_1_STATUS (MMU_REG_BASE+0x00000084) -+#define ADR_PKT_NEQID_2_STATUS (MMU_REG_BASE+0x00000088) -+#define ADR_PKT_NEQID_3_STATUS (MMU_REG_BASE+0x0000008c) -+#define ADR_ALC_NOCHG_ID_STATUS (MMU_REG_BASE+0x00000090) -+#define ADR_TAG_SRAM0_F_STATUS_0 (MMU_REG_BASE+0x000000a0) -+#define ADR_TAG_SRAM0_F_STATUS_1 (MMU_REG_BASE+0x000000a4) -+#define ADR_TAG_SRAM0_F_STATUS_2 (MMU_REG_BASE+0x000000a8) -+#define ADR_TAG_SRAM0_F_STATUS_3 (MMU_REG_BASE+0x000000ac) -+#define ADR_TAG_SRAM0_F_STATUS_4 (MMU_REG_BASE+0x000000b0) -+#define ADR_TAG_SRAM0_F_STATUS_5 (MMU_REG_BASE+0x000000b4) -+#define ADR_TAG_SRAM0_F_STATUS_6 (MMU_REG_BASE+0x000000b8) -+#define ADR_TAG_SRAM0_F_STATUS_7 (MMU_REG_BASE+0x000000bc) -+#define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0) -+#define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1) -+#define GET_MCU_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2) -+#define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3) -+#define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4) -+#define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5) -+#define GET_DMA_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000040 ) >> 6) -+#define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7) -+#define GET_I2C_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000100 ) >> 8) -+#define GET_INT_CTL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000200 ) >> 9) -+#define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10) -+#define GET_GPIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000800 ) >> 11) -+#define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12) -+#define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13) -+#define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14) -+#define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15) -+#define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16) -+#define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17) -+#define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18) -+#define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19) -+#define GET_RF_BB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20) -+#define GET_SYS_ALL_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21) -+#define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22) -+#define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23) -+#define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0) -+#define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16) -+#define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17) -+#define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18) -+#define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0) -+#define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0) -+#define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0) -+#define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0) -+#define GET_CK_SEL_1_0 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000003 ) >> 0) -+#define GET_CK_SEL_2 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000004 ) >> 2) -+#define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0) -+#define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1) -+#define GET_MCU_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2) -+#define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3) -+#define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4) -+#define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5) -+#define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6) -+#define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7) -+#define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8) -+#define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9) -+#define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10) -+#define GET_GPIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11) -+#define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12) -+#define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13) -+#define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14) -+#define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15) -+#define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16) -+#define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17) -+#define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18) -+#define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19) -+#define GET_BIST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20) -+#define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23) -+#define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10) -+#define GET_MCU_DBG_SEL (((REG32(ADR_MCU_DBG_SEL)) & 0x0000003f ) >> 0) -+#define GET_MCU_STOP_NOGRANT (((REG32(ADR_MCU_DBG_SEL)) & 0x00000100 ) >> 8) -+#define GET_MCU_STOP_ANYTIME (((REG32(ADR_MCU_DBG_SEL)) & 0x00000200 ) >> 9) -+#define GET_MCU_DBG_DATA (((REG32(ADR_MCU_DBG_DATA)) & 0xffffffff ) >> 0) -+#define GET_AHB_SW_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000001 ) >> 0) -+#define GET_AHB_ERR_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000002 ) >> 1) -+#define GET_REG_AHB_DEBUG_MX (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000030 ) >> 4) -+#define GET_REG_PKT_W_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000100 ) >> 8) -+#define GET_REG_PKT_R_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000200 ) >> 9) -+#define GET_IQ_SRAM_SEL_0 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00001000 ) >> 12) -+#define GET_IQ_SRAM_SEL_1 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00002000 ) >> 13) -+#define GET_IQ_SRAM_SEL_2 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00004000 ) >> 14) -+#define GET_AHB_STATUS (((REG32(ADR_AHB_BRG_STATUS)) & 0xffff0000 ) >> 16) -+#define GET_PARALLEL_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000001 ) >> 0) -+#define GET_MBRUN (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000010 ) >> 4) -+#define GET_SHIFT_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000100 ) >> 8) -+#define GET_MODE_REG_SI (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000200 ) >> 9) -+#define GET_SIMULATION_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000400 ) >> 10) -+#define GET_DBIST_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000800 ) >> 11) -+#define GET_MODE_REG_IN (((REG32(ADR_BIST_MODE_REG_IN)) & 0x001fffff ) >> 0) -+#define GET_MODE_REG_OUT_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x001fffff ) >> 0) -+#define GET_MODE_REG_SO_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x80000000 ) >> 31) -+#define GET_MONITOR_BUS_MCU_31_0 (((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0xffffffff ) >> 0) -+#define GET_MONITOR_BUS_MCU_33_32 (((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0x00000003 ) >> 0) -+#define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0) -+#define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31) -+#define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0) -+#define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0) -+#define GET_DATA_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000010 ) >> 4) -+#define GET_AHB_ILL_ADDR (((REG32(ADR_AHB_ILL_ADDR)) & 0xffffffff ) >> 0) -+#define GET_AHB_FEN_ADDR (((REG32(ADR_AHB_FEN_ADDR)) & 0xffffffff ) >> 0) -+#define GET_ILL_ADDR_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000001 ) >> 0) -+#define GET_FENCE_HIT_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000002 ) >> 1) -+#define GET_ILL_ADDR_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000010 ) >> 4) -+#define GET_FENCE_HIT_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000020 ) >> 5) -+#define GET_PWM_INI_VALUE_P_A (((REG32(ADR_PWM_A)) & 0x000000ff ) >> 0) -+#define GET_PWM_INI_VALUE_N_A (((REG32(ADR_PWM_A)) & 0x0000ff00 ) >> 8) -+#define GET_PWM_POST_SCALER_A (((REG32(ADR_PWM_A)) & 0x000f0000 ) >> 16) -+#define GET_PWM_ALWAYSON_A (((REG32(ADR_PWM_A)) & 0x20000000 ) >> 29) -+#define GET_PWM_INVERT_A (((REG32(ADR_PWM_A)) & 0x40000000 ) >> 30) -+#define GET_PWM_ENABLE_A (((REG32(ADR_PWM_A)) & 0x80000000 ) >> 31) -+#define GET_PWM_INI_VALUE_P_B (((REG32(ADR_PWM_B)) & 0x000000ff ) >> 0) -+#define GET_PWM_INI_VALUE_N_B (((REG32(ADR_PWM_B)) & 0x0000ff00 ) >> 8) -+#define GET_PWM_POST_SCALER_B (((REG32(ADR_PWM_B)) & 0x000f0000 ) >> 16) -+#define GET_PWM_ALWAYSON_B (((REG32(ADR_PWM_B)) & 0x20000000 ) >> 29) -+#define GET_PWM_INVERT_B (((REG32(ADR_PWM_B)) & 0x40000000 ) >> 30) -+#define GET_PWM_ENABLE_B (((REG32(ADR_PWM_B)) & 0x80000000 ) >> 31) -+#define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0) -+#define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0) -+#define GET_PRESCALER_USTIMER (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0) -+#define GET_MODE_REG_IN_MMU (((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0x0000ffff ) >> 0) -+#define GET_MODE_REG_OUT_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x0000ffff ) >> 0) -+#define GET_MODE_REG_SO_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x80000000 ) >> 31) -+#define GET_MONITOR_BUS_MMU (((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0x0007ffff ) >> 0) -+#define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0) -+#define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1) -+#define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2) -+#define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3) -+#define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4) -+#define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5) -+#define GET_WDT_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0) -+#define GET_SD_HOST_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1) -+#define GET_ALLOW_SD_RESET (((REG32(ADR_SD_INIT_CFG)) & 0x00000001 ) >> 0) -+#define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0) -+#define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1) -+#define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0) -+#define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16) -+#define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17) -+#define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18) -+#define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) -+#define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0) -+#define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16) -+#define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17) -+#define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18) -+#define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) -+#define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0) -+#define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16) -+#define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17) -+#define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18) -+#define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) -+#define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0) -+#define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16) -+#define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17) -+#define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18) -+#define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) -+#define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x0000ffff ) >> 0) -+#define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00010000 ) >> 16) -+#define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00020000 ) >> 17) -+#define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00040000 ) >> 18) -+#define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) -+#define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x0000ffff ) >> 0) -+#define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00010000 ) >> 16) -+#define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00020000 ) >> 17) -+#define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00040000 ) >> 18) -+#define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) -+#define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x0000ffff ) >> 0) -+#define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00010000 ) >> 16) -+#define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00020000 ) >> 17) -+#define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00040000 ) >> 18) -+#define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) -+#define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x0000ffff ) >> 0) -+#define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00010000 ) >> 16) -+#define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00020000 ) >> 17) -+#define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00040000 ) >> 18) -+#define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) -+#define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0) -+#define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x00020000 ) >> 17) -+#define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31) -+#define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0) -+#define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x00020000 ) >> 17) -+#define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31) -+#define GET_XLNA_EN_O_OE (((REG32(ADR_PAD6)) & 0x00000001 ) >> 0) -+#define GET_XLNA_EN_O_PE (((REG32(ADR_PAD6)) & 0x00000002 ) >> 1) -+#define GET_PAD6_IE (((REG32(ADR_PAD6)) & 0x00000008 ) >> 3) -+#define GET_PAD6_SEL_I (((REG32(ADR_PAD6)) & 0x00000030 ) >> 4) -+#define GET_PAD6_OD (((REG32(ADR_PAD6)) & 0x00000100 ) >> 8) -+#define GET_PAD6_SEL_O (((REG32(ADR_PAD6)) & 0x00001000 ) >> 12) -+#define GET_XLNA_EN_O_C (((REG32(ADR_PAD6)) & 0x10000000 ) >> 28) -+#define GET_WIFI_TX_SW_O_OE (((REG32(ADR_PAD7)) & 0x00000001 ) >> 0) -+#define GET_WIFI_TX_SW_O_PE (((REG32(ADR_PAD7)) & 0x00000002 ) >> 1) -+#define GET_PAD7_IE (((REG32(ADR_PAD7)) & 0x00000008 ) >> 3) -+#define GET_PAD7_SEL_I (((REG32(ADR_PAD7)) & 0x00000030 ) >> 4) -+#define GET_PAD7_OD (((REG32(ADR_PAD7)) & 0x00000100 ) >> 8) -+#define GET_PAD7_SEL_O (((REG32(ADR_PAD7)) & 0x00001000 ) >> 12) -+#define GET_WIFI_TX_SW_O_C (((REG32(ADR_PAD7)) & 0x10000000 ) >> 28) -+#define GET_WIFI_RX_SW_O_OE (((REG32(ADR_PAD8)) & 0x00000001 ) >> 0) -+#define GET_WIFI_RX_SW_O_PE (((REG32(ADR_PAD8)) & 0x00000002 ) >> 1) -+#define GET_PAD8_IE (((REG32(ADR_PAD8)) & 0x00000008 ) >> 3) -+#define GET_PAD8_SEL_I (((REG32(ADR_PAD8)) & 0x00000030 ) >> 4) -+#define GET_PAD8_OD (((REG32(ADR_PAD8)) & 0x00000100 ) >> 8) -+#define GET_WIFI_RX_SW_O_C (((REG32(ADR_PAD8)) & 0x10000000 ) >> 28) -+#define GET_BT_SW_O_OE (((REG32(ADR_PAD9)) & 0x00000001 ) >> 0) -+#define GET_BT_SW_O_PE (((REG32(ADR_PAD9)) & 0x00000002 ) >> 1) -+#define GET_PAD9_IE (((REG32(ADR_PAD9)) & 0x00000008 ) >> 3) -+#define GET_PAD9_SEL_I (((REG32(ADR_PAD9)) & 0x00000030 ) >> 4) -+#define GET_PAD9_OD (((REG32(ADR_PAD9)) & 0x00000100 ) >> 8) -+#define GET_PAD9_SEL_O (((REG32(ADR_PAD9)) & 0x00001000 ) >> 12) -+#define GET_BT_SW_O_C (((REG32(ADR_PAD9)) & 0x10000000 ) >> 28) -+#define GET_XPA_EN_O_OE (((REG32(ADR_PAD11)) & 0x00000001 ) >> 0) -+#define GET_XPA_EN_O_PE (((REG32(ADR_PAD11)) & 0x00000002 ) >> 1) -+#define GET_PAD11_IE (((REG32(ADR_PAD11)) & 0x00000008 ) >> 3) -+#define GET_PAD11_SEL_I (((REG32(ADR_PAD11)) & 0x00000030 ) >> 4) -+#define GET_PAD11_OD (((REG32(ADR_PAD11)) & 0x00000100 ) >> 8) -+#define GET_PAD11_SEL_O (((REG32(ADR_PAD11)) & 0x00001000 ) >> 12) -+#define GET_XPA_EN_O_C (((REG32(ADR_PAD11)) & 0x10000000 ) >> 28) -+#define GET_PAD15_OE (((REG32(ADR_PAD15)) & 0x00000001 ) >> 0) -+#define GET_PAD15_PE (((REG32(ADR_PAD15)) & 0x00000002 ) >> 1) -+#define GET_PAD15_DS (((REG32(ADR_PAD15)) & 0x00000004 ) >> 2) -+#define GET_PAD15_IE (((REG32(ADR_PAD15)) & 0x00000008 ) >> 3) -+#define GET_PAD15_SEL_I (((REG32(ADR_PAD15)) & 0x00000030 ) >> 4) -+#define GET_PAD15_OD (((REG32(ADR_PAD15)) & 0x00000100 ) >> 8) -+#define GET_PAD15_SEL_O (((REG32(ADR_PAD15)) & 0x00001000 ) >> 12) -+#define GET_TEST_1_ID (((REG32(ADR_PAD15)) & 0x10000000 ) >> 28) -+#define GET_PAD16_OE (((REG32(ADR_PAD16)) & 0x00000001 ) >> 0) -+#define GET_PAD16_PE (((REG32(ADR_PAD16)) & 0x00000002 ) >> 1) -+#define GET_PAD16_DS (((REG32(ADR_PAD16)) & 0x00000004 ) >> 2) -+#define GET_PAD16_IE (((REG32(ADR_PAD16)) & 0x00000008 ) >> 3) -+#define GET_PAD16_SEL_I (((REG32(ADR_PAD16)) & 0x00000030 ) >> 4) -+#define GET_PAD16_OD (((REG32(ADR_PAD16)) & 0x00000100 ) >> 8) -+#define GET_PAD16_SEL_O (((REG32(ADR_PAD16)) & 0x00001000 ) >> 12) -+#define GET_TEST_2_ID (((REG32(ADR_PAD16)) & 0x10000000 ) >> 28) -+#define GET_PAD17_OE (((REG32(ADR_PAD17)) & 0x00000001 ) >> 0) -+#define GET_PAD17_PE (((REG32(ADR_PAD17)) & 0x00000002 ) >> 1) -+#define GET_PAD17_DS (((REG32(ADR_PAD17)) & 0x00000004 ) >> 2) -+#define GET_PAD17_IE (((REG32(ADR_PAD17)) & 0x00000008 ) >> 3) -+#define GET_PAD17_SEL_I (((REG32(ADR_PAD17)) & 0x00000030 ) >> 4) -+#define GET_PAD17_OD (((REG32(ADR_PAD17)) & 0x00000100 ) >> 8) -+#define GET_PAD17_SEL_O (((REG32(ADR_PAD17)) & 0x00001000 ) >> 12) -+#define GET_TEST_3_ID (((REG32(ADR_PAD17)) & 0x10000000 ) >> 28) -+#define GET_PAD18_OE (((REG32(ADR_PAD18)) & 0x00000001 ) >> 0) -+#define GET_PAD18_PE (((REG32(ADR_PAD18)) & 0x00000002 ) >> 1) -+#define GET_PAD18_DS (((REG32(ADR_PAD18)) & 0x00000004 ) >> 2) -+#define GET_PAD18_IE (((REG32(ADR_PAD18)) & 0x00000008 ) >> 3) -+#define GET_PAD18_SEL_I (((REG32(ADR_PAD18)) & 0x00000030 ) >> 4) -+#define GET_PAD18_OD (((REG32(ADR_PAD18)) & 0x00000100 ) >> 8) -+#define GET_PAD18_SEL_O (((REG32(ADR_PAD18)) & 0x00003000 ) >> 12) -+#define GET_TEST_4_ID (((REG32(ADR_PAD18)) & 0x10000000 ) >> 28) -+#define GET_PAD19_OE (((REG32(ADR_PAD19)) & 0x00000001 ) >> 0) -+#define GET_PAD19_PE (((REG32(ADR_PAD19)) & 0x00000002 ) >> 1) -+#define GET_PAD19_DS (((REG32(ADR_PAD19)) & 0x00000004 ) >> 2) -+#define GET_PAD19_IE (((REG32(ADR_PAD19)) & 0x00000008 ) >> 3) -+#define GET_PAD19_SEL_I (((REG32(ADR_PAD19)) & 0x00000030 ) >> 4) -+#define GET_PAD19_OD (((REG32(ADR_PAD19)) & 0x00000100 ) >> 8) -+#define GET_PAD19_SEL_O (((REG32(ADR_PAD19)) & 0x00007000 ) >> 12) -+#define GET_SHORT_TO_20_ID (((REG32(ADR_PAD19)) & 0x10000000 ) >> 28) -+#define GET_PAD20_OE (((REG32(ADR_PAD20)) & 0x00000001 ) >> 0) -+#define GET_PAD20_PE (((REG32(ADR_PAD20)) & 0x00000002 ) >> 1) -+#define GET_PAD20_DS (((REG32(ADR_PAD20)) & 0x00000004 ) >> 2) -+#define GET_PAD20_IE (((REG32(ADR_PAD20)) & 0x00000008 ) >> 3) -+#define GET_PAD20_SEL_I (((REG32(ADR_PAD20)) & 0x000000f0 ) >> 4) -+#define GET_PAD20_OD (((REG32(ADR_PAD20)) & 0x00000100 ) >> 8) -+#define GET_PAD20_SEL_O (((REG32(ADR_PAD20)) & 0x00003000 ) >> 12) -+#define GET_STRAP0 (((REG32(ADR_PAD20)) & 0x08000000 ) >> 27) -+#define GET_GPIO_TEST_1_ID (((REG32(ADR_PAD20)) & 0x10000000 ) >> 28) -+#define GET_PAD21_OE (((REG32(ADR_PAD21)) & 0x00000001 ) >> 0) -+#define GET_PAD21_PE (((REG32(ADR_PAD21)) & 0x00000002 ) >> 1) -+#define GET_PAD21_DS (((REG32(ADR_PAD21)) & 0x00000004 ) >> 2) -+#define GET_PAD21_IE (((REG32(ADR_PAD21)) & 0x00000008 ) >> 3) -+#define GET_PAD21_SEL_I (((REG32(ADR_PAD21)) & 0x00000070 ) >> 4) -+#define GET_PAD21_OD (((REG32(ADR_PAD21)) & 0x00000100 ) >> 8) -+#define GET_PAD21_SEL_O (((REG32(ADR_PAD21)) & 0x00003000 ) >> 12) -+#define GET_STRAP3 (((REG32(ADR_PAD21)) & 0x08000000 ) >> 27) -+#define GET_GPIO_TEST_2_ID (((REG32(ADR_PAD21)) & 0x10000000 ) >> 28) -+#define GET_PAD22_OE (((REG32(ADR_PAD22)) & 0x00000001 ) >> 0) -+#define GET_PAD22_PE (((REG32(ADR_PAD22)) & 0x00000002 ) >> 1) -+#define GET_PAD22_DS (((REG32(ADR_PAD22)) & 0x00000004 ) >> 2) -+#define GET_PAD22_IE (((REG32(ADR_PAD22)) & 0x00000008 ) >> 3) -+#define GET_PAD22_SEL_I (((REG32(ADR_PAD22)) & 0x00000070 ) >> 4) -+#define GET_PAD22_OD (((REG32(ADR_PAD22)) & 0x00000100 ) >> 8) -+#define GET_PAD22_SEL_O (((REG32(ADR_PAD22)) & 0x00007000 ) >> 12) -+#define GET_PAD22_SEL_OE (((REG32(ADR_PAD22)) & 0x00100000 ) >> 20) -+#define GET_GPIO_TEST_3_ID (((REG32(ADR_PAD22)) & 0x10000000 ) >> 28) -+#define GET_PAD24_OE (((REG32(ADR_PAD24)) & 0x00000001 ) >> 0) -+#define GET_PAD24_PE (((REG32(ADR_PAD24)) & 0x00000002 ) >> 1) -+#define GET_PAD24_DS (((REG32(ADR_PAD24)) & 0x00000004 ) >> 2) -+#define GET_PAD24_IE (((REG32(ADR_PAD24)) & 0x00000008 ) >> 3) -+#define GET_PAD24_SEL_I (((REG32(ADR_PAD24)) & 0x00000030 ) >> 4) -+#define GET_PAD24_OD (((REG32(ADR_PAD24)) & 0x00000100 ) >> 8) -+#define GET_PAD24_SEL_O (((REG32(ADR_PAD24)) & 0x00007000 ) >> 12) -+#define GET_GPIO_TEST_4_ID (((REG32(ADR_PAD24)) & 0x10000000 ) >> 28) -+#define GET_PAD25_OE (((REG32(ADR_PAD25)) & 0x00000001 ) >> 0) -+#define GET_PAD25_PE (((REG32(ADR_PAD25)) & 0x00000002 ) >> 1) -+#define GET_PAD25_DS (((REG32(ADR_PAD25)) & 0x00000004 ) >> 2) -+#define GET_PAD25_IE (((REG32(ADR_PAD25)) & 0x00000008 ) >> 3) -+#define GET_PAD25_SEL_I (((REG32(ADR_PAD25)) & 0x00000070 ) >> 4) -+#define GET_PAD25_OD (((REG32(ADR_PAD25)) & 0x00000100 ) >> 8) -+#define GET_PAD25_SEL_O (((REG32(ADR_PAD25)) & 0x00007000 ) >> 12) -+#define GET_PAD25_SEL_OE (((REG32(ADR_PAD25)) & 0x00100000 ) >> 20) -+#define GET_STRAP1 (((REG32(ADR_PAD25)) & 0x08000000 ) >> 27) -+#define GET_GPIO_1_ID (((REG32(ADR_PAD25)) & 0x10000000 ) >> 28) -+#define GET_PAD27_OE (((REG32(ADR_PAD27)) & 0x00000001 ) >> 0) -+#define GET_PAD27_PE (((REG32(ADR_PAD27)) & 0x00000002 ) >> 1) -+#define GET_PAD27_DS (((REG32(ADR_PAD27)) & 0x00000004 ) >> 2) -+#define GET_PAD27_IE (((REG32(ADR_PAD27)) & 0x00000008 ) >> 3) -+#define GET_PAD27_SEL_I (((REG32(ADR_PAD27)) & 0x00000070 ) >> 4) -+#define GET_PAD27_OD (((REG32(ADR_PAD27)) & 0x00000100 ) >> 8) -+#define GET_PAD27_SEL_O (((REG32(ADR_PAD27)) & 0x00007000 ) >> 12) -+#define GET_GPIO_2_ID (((REG32(ADR_PAD27)) & 0x10000000 ) >> 28) -+#define GET_PAD28_OE (((REG32(ADR_PAD28)) & 0x00000001 ) >> 0) -+#define GET_PAD28_PE (((REG32(ADR_PAD28)) & 0x00000002 ) >> 1) -+#define GET_PAD28_DS (((REG32(ADR_PAD28)) & 0x00000004 ) >> 2) -+#define GET_PAD28_IE (((REG32(ADR_PAD28)) & 0x00000008 ) >> 3) -+#define GET_PAD28_SEL_I (((REG32(ADR_PAD28)) & 0x00000070 ) >> 4) -+#define GET_PAD28_OD (((REG32(ADR_PAD28)) & 0x00000100 ) >> 8) -+#define GET_PAD28_SEL_O (((REG32(ADR_PAD28)) & 0x0000f000 ) >> 12) -+#define GET_PAD28_SEL_OE (((REG32(ADR_PAD28)) & 0x00100000 ) >> 20) -+#define GET_GPIO_3_ID (((REG32(ADR_PAD28)) & 0x10000000 ) >> 28) -+#define GET_PAD29_OE (((REG32(ADR_PAD29)) & 0x00000001 ) >> 0) -+#define GET_PAD29_PE (((REG32(ADR_PAD29)) & 0x00000002 ) >> 1) -+#define GET_PAD29_DS (((REG32(ADR_PAD29)) & 0x00000004 ) >> 2) -+#define GET_PAD29_IE (((REG32(ADR_PAD29)) & 0x00000008 ) >> 3) -+#define GET_PAD29_SEL_I (((REG32(ADR_PAD29)) & 0x00000070 ) >> 4) -+#define GET_PAD29_OD (((REG32(ADR_PAD29)) & 0x00000100 ) >> 8) -+#define GET_PAD29_SEL_O (((REG32(ADR_PAD29)) & 0x00007000 ) >> 12) -+#define GET_GPIO_TEST_5_ID (((REG32(ADR_PAD29)) & 0x10000000 ) >> 28) -+#define GET_PAD30_OE (((REG32(ADR_PAD30)) & 0x00000001 ) >> 0) -+#define GET_PAD30_PE (((REG32(ADR_PAD30)) & 0x00000002 ) >> 1) -+#define GET_PAD30_DS (((REG32(ADR_PAD30)) & 0x00000004 ) >> 2) -+#define GET_PAD30_IE (((REG32(ADR_PAD30)) & 0x00000008 ) >> 3) -+#define GET_PAD30_SEL_I (((REG32(ADR_PAD30)) & 0x00000030 ) >> 4) -+#define GET_PAD30_OD (((REG32(ADR_PAD30)) & 0x00000100 ) >> 8) -+#define GET_PAD30_SEL_O (((REG32(ADR_PAD30)) & 0x00003000 ) >> 12) -+#define GET_TEST_6_ID (((REG32(ADR_PAD30)) & 0x10000000 ) >> 28) -+#define GET_PAD31_OE (((REG32(ADR_PAD31)) & 0x00000001 ) >> 0) -+#define GET_PAD31_PE (((REG32(ADR_PAD31)) & 0x00000002 ) >> 1) -+#define GET_PAD31_DS (((REG32(ADR_PAD31)) & 0x00000004 ) >> 2) -+#define GET_PAD31_IE (((REG32(ADR_PAD31)) & 0x00000008 ) >> 3) -+#define GET_PAD31_SEL_I (((REG32(ADR_PAD31)) & 0x00000030 ) >> 4) -+#define GET_PAD31_OD (((REG32(ADR_PAD31)) & 0x00000100 ) >> 8) -+#define GET_PAD31_SEL_O (((REG32(ADR_PAD31)) & 0x00003000 ) >> 12) -+#define GET_TEST_7_ID (((REG32(ADR_PAD31)) & 0x10000000 ) >> 28) -+#define GET_PAD32_OE (((REG32(ADR_PAD32)) & 0x00000001 ) >> 0) -+#define GET_PAD32_PE (((REG32(ADR_PAD32)) & 0x00000002 ) >> 1) -+#define GET_PAD32_DS (((REG32(ADR_PAD32)) & 0x00000004 ) >> 2) -+#define GET_PAD32_IE (((REG32(ADR_PAD32)) & 0x00000008 ) >> 3) -+#define GET_PAD32_SEL_I (((REG32(ADR_PAD32)) & 0x00000030 ) >> 4) -+#define GET_PAD32_OD (((REG32(ADR_PAD32)) & 0x00000100 ) >> 8) -+#define GET_PAD32_SEL_O (((REG32(ADR_PAD32)) & 0x00003000 ) >> 12) -+#define GET_TEST_8_ID (((REG32(ADR_PAD32)) & 0x10000000 ) >> 28) -+#define GET_PAD33_OE (((REG32(ADR_PAD33)) & 0x00000001 ) >> 0) -+#define GET_PAD33_PE (((REG32(ADR_PAD33)) & 0x00000002 ) >> 1) -+#define GET_PAD33_DS (((REG32(ADR_PAD33)) & 0x00000004 ) >> 2) -+#define GET_PAD33_IE (((REG32(ADR_PAD33)) & 0x00000008 ) >> 3) -+#define GET_PAD33_SEL_I (((REG32(ADR_PAD33)) & 0x00000030 ) >> 4) -+#define GET_PAD33_OD (((REG32(ADR_PAD33)) & 0x00000100 ) >> 8) -+#define GET_PAD33_SEL_O (((REG32(ADR_PAD33)) & 0x00003000 ) >> 12) -+#define GET_TEST_9_ID (((REG32(ADR_PAD33)) & 0x10000000 ) >> 28) -+#define GET_PAD34_OE (((REG32(ADR_PAD34)) & 0x00000001 ) >> 0) -+#define GET_PAD34_PE (((REG32(ADR_PAD34)) & 0x00000002 ) >> 1) -+#define GET_PAD34_DS (((REG32(ADR_PAD34)) & 0x00000004 ) >> 2) -+#define GET_PAD34_IE (((REG32(ADR_PAD34)) & 0x00000008 ) >> 3) -+#define GET_PAD34_SEL_I (((REG32(ADR_PAD34)) & 0x00000030 ) >> 4) -+#define GET_PAD34_OD (((REG32(ADR_PAD34)) & 0x00000100 ) >> 8) -+#define GET_PAD34_SEL_O (((REG32(ADR_PAD34)) & 0x00003000 ) >> 12) -+#define GET_TEST_10_ID (((REG32(ADR_PAD34)) & 0x10000000 ) >> 28) -+#define GET_PAD42_OE (((REG32(ADR_PAD42)) & 0x00000001 ) >> 0) -+#define GET_PAD42_PE (((REG32(ADR_PAD42)) & 0x00000002 ) >> 1) -+#define GET_PAD42_DS (((REG32(ADR_PAD42)) & 0x00000004 ) >> 2) -+#define GET_PAD42_IE (((REG32(ADR_PAD42)) & 0x00000008 ) >> 3) -+#define GET_PAD42_SEL_I (((REG32(ADR_PAD42)) & 0x00000030 ) >> 4) -+#define GET_PAD42_OD (((REG32(ADR_PAD42)) & 0x00000100 ) >> 8) -+#define GET_PAD42_SEL_O (((REG32(ADR_PAD42)) & 0x00001000 ) >> 12) -+#define GET_TEST_11_ID (((REG32(ADR_PAD42)) & 0x10000000 ) >> 28) -+#define GET_PAD43_OE (((REG32(ADR_PAD43)) & 0x00000001 ) >> 0) -+#define GET_PAD43_PE (((REG32(ADR_PAD43)) & 0x00000002 ) >> 1) -+#define GET_PAD43_DS (((REG32(ADR_PAD43)) & 0x00000004 ) >> 2) -+#define GET_PAD43_IE (((REG32(ADR_PAD43)) & 0x00000008 ) >> 3) -+#define GET_PAD43_SEL_I (((REG32(ADR_PAD43)) & 0x00000030 ) >> 4) -+#define GET_PAD43_OD (((REG32(ADR_PAD43)) & 0x00000100 ) >> 8) -+#define GET_PAD43_SEL_O (((REG32(ADR_PAD43)) & 0x00001000 ) >> 12) -+#define GET_TEST_12_ID (((REG32(ADR_PAD43)) & 0x10000000 ) >> 28) -+#define GET_PAD44_OE (((REG32(ADR_PAD44)) & 0x00000001 ) >> 0) -+#define GET_PAD44_PE (((REG32(ADR_PAD44)) & 0x00000002 ) >> 1) -+#define GET_PAD44_DS (((REG32(ADR_PAD44)) & 0x00000004 ) >> 2) -+#define GET_PAD44_IE (((REG32(ADR_PAD44)) & 0x00000008 ) >> 3) -+#define GET_PAD44_SEL_I (((REG32(ADR_PAD44)) & 0x00000030 ) >> 4) -+#define GET_PAD44_OD (((REG32(ADR_PAD44)) & 0x00000100 ) >> 8) -+#define GET_PAD44_SEL_O (((REG32(ADR_PAD44)) & 0x00003000 ) >> 12) -+#define GET_TEST_13_ID (((REG32(ADR_PAD44)) & 0x10000000 ) >> 28) -+#define GET_PAD45_OE (((REG32(ADR_PAD45)) & 0x00000001 ) >> 0) -+#define GET_PAD45_PE (((REG32(ADR_PAD45)) & 0x00000002 ) >> 1) -+#define GET_PAD45_DS (((REG32(ADR_PAD45)) & 0x00000004 ) >> 2) -+#define GET_PAD45_IE (((REG32(ADR_PAD45)) & 0x00000008 ) >> 3) -+#define GET_PAD45_SEL_I (((REG32(ADR_PAD45)) & 0x00000030 ) >> 4) -+#define GET_PAD45_OD (((REG32(ADR_PAD45)) & 0x00000100 ) >> 8) -+#define GET_PAD45_SEL_O (((REG32(ADR_PAD45)) & 0x00003000 ) >> 12) -+#define GET_TEST_14_ID (((REG32(ADR_PAD45)) & 0x10000000 ) >> 28) -+#define GET_PAD46_OE (((REG32(ADR_PAD46)) & 0x00000001 ) >> 0) -+#define GET_PAD46_PE (((REG32(ADR_PAD46)) & 0x00000002 ) >> 1) -+#define GET_PAD46_DS (((REG32(ADR_PAD46)) & 0x00000004 ) >> 2) -+#define GET_PAD46_IE (((REG32(ADR_PAD46)) & 0x00000008 ) >> 3) -+#define GET_PAD46_SEL_I (((REG32(ADR_PAD46)) & 0x00000030 ) >> 4) -+#define GET_PAD46_OD (((REG32(ADR_PAD46)) & 0x00000100 ) >> 8) -+#define GET_PAD46_SEL_O (((REG32(ADR_PAD46)) & 0x00003000 ) >> 12) -+#define GET_TEST_15_ID (((REG32(ADR_PAD46)) & 0x10000000 ) >> 28) -+#define GET_PAD47_OE (((REG32(ADR_PAD47)) & 0x00000001 ) >> 0) -+#define GET_PAD47_PE (((REG32(ADR_PAD47)) & 0x00000002 ) >> 1) -+#define GET_PAD47_DS (((REG32(ADR_PAD47)) & 0x00000004 ) >> 2) -+#define GET_PAD47_SEL_I (((REG32(ADR_PAD47)) & 0x00000030 ) >> 4) -+#define GET_PAD47_OD (((REG32(ADR_PAD47)) & 0x00000100 ) >> 8) -+#define GET_PAD47_SEL_O (((REG32(ADR_PAD47)) & 0x00003000 ) >> 12) -+#define GET_PAD47_SEL_OE (((REG32(ADR_PAD47)) & 0x00100000 ) >> 20) -+#define GET_GPIO_9_ID (((REG32(ADR_PAD47)) & 0x10000000 ) >> 28) -+#define GET_PAD48_OE (((REG32(ADR_PAD48)) & 0x00000001 ) >> 0) -+#define GET_PAD48_PE (((REG32(ADR_PAD48)) & 0x00000002 ) >> 1) -+#define GET_PAD48_DS (((REG32(ADR_PAD48)) & 0x00000004 ) >> 2) -+#define GET_PAD48_IE (((REG32(ADR_PAD48)) & 0x00000008 ) >> 3) -+#define GET_PAD48_SEL_I (((REG32(ADR_PAD48)) & 0x00000070 ) >> 4) -+#define GET_PAD48_OD (((REG32(ADR_PAD48)) & 0x00000100 ) >> 8) -+#define GET_PAD48_PE_SEL (((REG32(ADR_PAD48)) & 0x00000800 ) >> 11) -+#define GET_PAD48_SEL_O (((REG32(ADR_PAD48)) & 0x00003000 ) >> 12) -+#define GET_PAD48_SEL_OE (((REG32(ADR_PAD48)) & 0x00100000 ) >> 20) -+#define GET_GPIO_10_ID (((REG32(ADR_PAD48)) & 0x10000000 ) >> 28) -+#define GET_PAD49_OE (((REG32(ADR_PAD49)) & 0x00000001 ) >> 0) -+#define GET_PAD49_PE (((REG32(ADR_PAD49)) & 0x00000002 ) >> 1) -+#define GET_PAD49_DS (((REG32(ADR_PAD49)) & 0x00000004 ) >> 2) -+#define GET_PAD49_IE (((REG32(ADR_PAD49)) & 0x00000008 ) >> 3) -+#define GET_PAD49_SEL_I (((REG32(ADR_PAD49)) & 0x00000070 ) >> 4) -+#define GET_PAD49_OD (((REG32(ADR_PAD49)) & 0x00000100 ) >> 8) -+#define GET_PAD49_SEL_O (((REG32(ADR_PAD49)) & 0x00003000 ) >> 12) -+#define GET_PAD49_SEL_OE (((REG32(ADR_PAD49)) & 0x00100000 ) >> 20) -+#define GET_GPIO_11_ID (((REG32(ADR_PAD49)) & 0x10000000 ) >> 28) -+#define GET_PAD50_OE (((REG32(ADR_PAD50)) & 0x00000001 ) >> 0) -+#define GET_PAD50_PE (((REG32(ADR_PAD50)) & 0x00000002 ) >> 1) -+#define GET_PAD50_DS (((REG32(ADR_PAD50)) & 0x00000004 ) >> 2) -+#define GET_PAD50_IE (((REG32(ADR_PAD50)) & 0x00000008 ) >> 3) -+#define GET_PAD50_SEL_I (((REG32(ADR_PAD50)) & 0x00000070 ) >> 4) -+#define GET_PAD50_OD (((REG32(ADR_PAD50)) & 0x00000100 ) >> 8) -+#define GET_PAD50_SEL_O (((REG32(ADR_PAD50)) & 0x00003000 ) >> 12) -+#define GET_PAD50_SEL_OE (((REG32(ADR_PAD50)) & 0x00100000 ) >> 20) -+#define GET_GPIO_12_ID (((REG32(ADR_PAD50)) & 0x10000000 ) >> 28) -+#define GET_PAD51_OE (((REG32(ADR_PAD51)) & 0x00000001 ) >> 0) -+#define GET_PAD51_PE (((REG32(ADR_PAD51)) & 0x00000002 ) >> 1) -+#define GET_PAD51_DS (((REG32(ADR_PAD51)) & 0x00000004 ) >> 2) -+#define GET_PAD51_IE (((REG32(ADR_PAD51)) & 0x00000008 ) >> 3) -+#define GET_PAD51_SEL_I (((REG32(ADR_PAD51)) & 0x00000030 ) >> 4) -+#define GET_PAD51_OD (((REG32(ADR_PAD51)) & 0x00000100 ) >> 8) -+#define GET_PAD51_SEL_O (((REG32(ADR_PAD51)) & 0x00001000 ) >> 12) -+#define GET_PAD51_SEL_OE (((REG32(ADR_PAD51)) & 0x00100000 ) >> 20) -+#define GET_GPIO_13_ID (((REG32(ADR_PAD51)) & 0x10000000 ) >> 28) -+#define GET_PAD52_OE (((REG32(ADR_PAD52)) & 0x00000001 ) >> 0) -+#define GET_PAD52_PE (((REG32(ADR_PAD52)) & 0x00000002 ) >> 1) -+#define GET_PAD52_DS (((REG32(ADR_PAD52)) & 0x00000004 ) >> 2) -+#define GET_PAD52_SEL_I (((REG32(ADR_PAD52)) & 0x00000030 ) >> 4) -+#define GET_PAD52_OD (((REG32(ADR_PAD52)) & 0x00000100 ) >> 8) -+#define GET_PAD52_SEL_O (((REG32(ADR_PAD52)) & 0x00001000 ) >> 12) -+#define GET_PAD52_SEL_OE (((REG32(ADR_PAD52)) & 0x00100000 ) >> 20) -+#define GET_GPIO_14_ID (((REG32(ADR_PAD52)) & 0x10000000 ) >> 28) -+#define GET_PAD53_OE (((REG32(ADR_PAD53)) & 0x00000001 ) >> 0) -+#define GET_PAD53_PE (((REG32(ADR_PAD53)) & 0x00000002 ) >> 1) -+#define GET_PAD53_DS (((REG32(ADR_PAD53)) & 0x00000004 ) >> 2) -+#define GET_PAD53_IE (((REG32(ADR_PAD53)) & 0x00000008 ) >> 3) -+#define GET_PAD53_SEL_I (((REG32(ADR_PAD53)) & 0x00000030 ) >> 4) -+#define GET_PAD53_OD (((REG32(ADR_PAD53)) & 0x00000100 ) >> 8) -+#define GET_PAD53_SEL_O (((REG32(ADR_PAD53)) & 0x00001000 ) >> 12) -+#define GET_JTAG_TMS_ID (((REG32(ADR_PAD53)) & 0x10000000 ) >> 28) -+#define GET_PAD54_OE (((REG32(ADR_PAD54)) & 0x00000001 ) >> 0) -+#define GET_PAD54_PE (((REG32(ADR_PAD54)) & 0x00000002 ) >> 1) -+#define GET_PAD54_DS (((REG32(ADR_PAD54)) & 0x00000004 ) >> 2) -+#define GET_PAD54_OD (((REG32(ADR_PAD54)) & 0x00000100 ) >> 8) -+#define GET_PAD54_SEL_O (((REG32(ADR_PAD54)) & 0x00003000 ) >> 12) -+#define GET_JTAG_TCK_ID (((REG32(ADR_PAD54)) & 0x10000000 ) >> 28) -+#define GET_PAD56_PE (((REG32(ADR_PAD56)) & 0x00000002 ) >> 1) -+#define GET_PAD56_DS (((REG32(ADR_PAD56)) & 0x00000004 ) >> 2) -+#define GET_PAD56_SEL_I (((REG32(ADR_PAD56)) & 0x00000010 ) >> 4) -+#define GET_PAD56_OD (((REG32(ADR_PAD56)) & 0x00000100 ) >> 8) -+#define GET_JTAG_TDI_ID (((REG32(ADR_PAD56)) & 0x10000000 ) >> 28) -+#define GET_PAD57_OE (((REG32(ADR_PAD57)) & 0x00000001 ) >> 0) -+#define GET_PAD57_PE (((REG32(ADR_PAD57)) & 0x00000002 ) >> 1) -+#define GET_PAD57_DS (((REG32(ADR_PAD57)) & 0x00000004 ) >> 2) -+#define GET_PAD57_IE (((REG32(ADR_PAD57)) & 0x00000008 ) >> 3) -+#define GET_PAD57_SEL_I (((REG32(ADR_PAD57)) & 0x00000030 ) >> 4) -+#define GET_PAD57_OD (((REG32(ADR_PAD57)) & 0x00000100 ) >> 8) -+#define GET_PAD57_SEL_O (((REG32(ADR_PAD57)) & 0x00003000 ) >> 12) -+#define GET_PAD57_SEL_OE (((REG32(ADR_PAD57)) & 0x00100000 ) >> 20) -+#define GET_JTAG_TDO_ID (((REG32(ADR_PAD57)) & 0x10000000 ) >> 28) -+#define GET_PAD58_OE (((REG32(ADR_PAD58)) & 0x00000001 ) >> 0) -+#define GET_PAD58_PE (((REG32(ADR_PAD58)) & 0x00000002 ) >> 1) -+#define GET_PAD58_DS (((REG32(ADR_PAD58)) & 0x00000004 ) >> 2) -+#define GET_PAD58_IE (((REG32(ADR_PAD58)) & 0x00000008 ) >> 3) -+#define GET_PAD58_SEL_I (((REG32(ADR_PAD58)) & 0x00000030 ) >> 4) -+#define GET_PAD58_OD (((REG32(ADR_PAD58)) & 0x00000100 ) >> 8) -+#define GET_PAD58_SEL_O (((REG32(ADR_PAD58)) & 0x00001000 ) >> 12) -+#define GET_TEST_16_ID (((REG32(ADR_PAD58)) & 0x10000000 ) >> 28) -+#define GET_PAD59_OE (((REG32(ADR_PAD59)) & 0x00000001 ) >> 0) -+#define GET_PAD59_PE (((REG32(ADR_PAD59)) & 0x00000002 ) >> 1) -+#define GET_PAD59_DS (((REG32(ADR_PAD59)) & 0x00000004 ) >> 2) -+#define GET_PAD59_IE (((REG32(ADR_PAD59)) & 0x00000008 ) >> 3) -+#define GET_PAD59_SEL_I (((REG32(ADR_PAD59)) & 0x00000030 ) >> 4) -+#define GET_PAD59_OD (((REG32(ADR_PAD59)) & 0x00000100 ) >> 8) -+#define GET_PAD59_SEL_O (((REG32(ADR_PAD59)) & 0x00001000 ) >> 12) -+#define GET_TEST_17_ID (((REG32(ADR_PAD59)) & 0x10000000 ) >> 28) -+#define GET_PAD60_OE (((REG32(ADR_PAD60)) & 0x00000001 ) >> 0) -+#define GET_PAD60_PE (((REG32(ADR_PAD60)) & 0x00000002 ) >> 1) -+#define GET_PAD60_DS (((REG32(ADR_PAD60)) & 0x00000004 ) >> 2) -+#define GET_PAD60_IE (((REG32(ADR_PAD60)) & 0x00000008 ) >> 3) -+#define GET_PAD60_SEL_I (((REG32(ADR_PAD60)) & 0x00000030 ) >> 4) -+#define GET_PAD60_OD (((REG32(ADR_PAD60)) & 0x00000100 ) >> 8) -+#define GET_PAD60_SEL_O (((REG32(ADR_PAD60)) & 0x00001000 ) >> 12) -+#define GET_TEST_18_ID (((REG32(ADR_PAD60)) & 0x10000000 ) >> 28) -+#define GET_PAD61_OE (((REG32(ADR_PAD61)) & 0x00000001 ) >> 0) -+#define GET_PAD61_PE (((REG32(ADR_PAD61)) & 0x00000002 ) >> 1) -+#define GET_PAD61_DS (((REG32(ADR_PAD61)) & 0x00000004 ) >> 2) -+#define GET_PAD61_IE (((REG32(ADR_PAD61)) & 0x00000008 ) >> 3) -+#define GET_PAD61_SEL_I (((REG32(ADR_PAD61)) & 0x00000010 ) >> 4) -+#define GET_PAD61_OD (((REG32(ADR_PAD61)) & 0x00000100 ) >> 8) -+#define GET_PAD61_SEL_O (((REG32(ADR_PAD61)) & 0x00003000 ) >> 12) -+#define GET_TEST_19_ID (((REG32(ADR_PAD61)) & 0x10000000 ) >> 28) -+#define GET_PAD62_OE (((REG32(ADR_PAD62)) & 0x00000001 ) >> 0) -+#define GET_PAD62_PE (((REG32(ADR_PAD62)) & 0x00000002 ) >> 1) -+#define GET_PAD62_DS (((REG32(ADR_PAD62)) & 0x00000004 ) >> 2) -+#define GET_PAD62_IE (((REG32(ADR_PAD62)) & 0x00000008 ) >> 3) -+#define GET_PAD62_SEL_I (((REG32(ADR_PAD62)) & 0x00000010 ) >> 4) -+#define GET_PAD62_OD (((REG32(ADR_PAD62)) & 0x00000100 ) >> 8) -+#define GET_PAD62_SEL_O (((REG32(ADR_PAD62)) & 0x00001000 ) >> 12) -+#define GET_TEST_20_ID (((REG32(ADR_PAD62)) & 0x10000000 ) >> 28) -+#define GET_PAD64_OE (((REG32(ADR_PAD64)) & 0x00000001 ) >> 0) -+#define GET_PAD64_PE (((REG32(ADR_PAD64)) & 0x00000002 ) >> 1) -+#define GET_PAD64_DS (((REG32(ADR_PAD64)) & 0x00000004 ) >> 2) -+#define GET_PAD64_IE (((REG32(ADR_PAD64)) & 0x00000008 ) >> 3) -+#define GET_PAD64_SEL_I (((REG32(ADR_PAD64)) & 0x00000070 ) >> 4) -+#define GET_PAD64_OD (((REG32(ADR_PAD64)) & 0x00000100 ) >> 8) -+#define GET_PAD64_SEL_O (((REG32(ADR_PAD64)) & 0x00003000 ) >> 12) -+#define GET_PAD64_SEL_OE (((REG32(ADR_PAD64)) & 0x00100000 ) >> 20) -+#define GET_GPIO_15_IP_ID (((REG32(ADR_PAD64)) & 0x10000000 ) >> 28) -+#define GET_PAD65_OE (((REG32(ADR_PAD65)) & 0x00000001 ) >> 0) -+#define GET_PAD65_PE (((REG32(ADR_PAD65)) & 0x00000002 ) >> 1) -+#define GET_PAD65_DS (((REG32(ADR_PAD65)) & 0x00000004 ) >> 2) -+#define GET_PAD65_IE (((REG32(ADR_PAD65)) & 0x00000008 ) >> 3) -+#define GET_PAD65_SEL_I (((REG32(ADR_PAD65)) & 0x00000070 ) >> 4) -+#define GET_PAD65_OD (((REG32(ADR_PAD65)) & 0x00000100 ) >> 8) -+#define GET_PAD65_SEL_O (((REG32(ADR_PAD65)) & 0x00001000 ) >> 12) -+#define GET_GPIO_TEST_7_IN_ID (((REG32(ADR_PAD65)) & 0x10000000 ) >> 28) -+#define GET_PAD66_OE (((REG32(ADR_PAD66)) & 0x00000001 ) >> 0) -+#define GET_PAD66_PE (((REG32(ADR_PAD66)) & 0x00000002 ) >> 1) -+#define GET_PAD66_DS (((REG32(ADR_PAD66)) & 0x00000004 ) >> 2) -+#define GET_PAD66_IE (((REG32(ADR_PAD66)) & 0x00000008 ) >> 3) -+#define GET_PAD66_SEL_I (((REG32(ADR_PAD66)) & 0x00000030 ) >> 4) -+#define GET_PAD66_OD (((REG32(ADR_PAD66)) & 0x00000100 ) >> 8) -+#define GET_PAD66_SEL_O (((REG32(ADR_PAD66)) & 0x00003000 ) >> 12) -+#define GET_GPIO_17_QP_ID (((REG32(ADR_PAD66)) & 0x10000000 ) >> 28) -+#define GET_PAD68_OE (((REG32(ADR_PAD68)) & 0x00000001 ) >> 0) -+#define GET_PAD68_PE (((REG32(ADR_PAD68)) & 0x00000002 ) >> 1) -+#define GET_PAD68_DS (((REG32(ADR_PAD68)) & 0x00000004 ) >> 2) -+#define GET_PAD68_IE (((REG32(ADR_PAD68)) & 0x00000008 ) >> 3) -+#define GET_PAD68_OD (((REG32(ADR_PAD68)) & 0x00000100 ) >> 8) -+#define GET_PAD68_SEL_O (((REG32(ADR_PAD68)) & 0x00001000 ) >> 12) -+#define GET_GPIO_19_ID (((REG32(ADR_PAD68)) & 0x10000000 ) >> 28) -+#define GET_PAD67_OE (((REG32(ADR_PAD67)) & 0x00000001 ) >> 0) -+#define GET_PAD67_PE (((REG32(ADR_PAD67)) & 0x00000002 ) >> 1) -+#define GET_PAD67_DS (((REG32(ADR_PAD67)) & 0x00000004 ) >> 2) -+#define GET_PAD67_IE (((REG32(ADR_PAD67)) & 0x00000008 ) >> 3) -+#define GET_PAD67_SEL_I (((REG32(ADR_PAD67)) & 0x00000070 ) >> 4) -+#define GET_PAD67_OD (((REG32(ADR_PAD67)) & 0x00000100 ) >> 8) -+#define GET_PAD67_SEL_O (((REG32(ADR_PAD67)) & 0x00003000 ) >> 12) -+#define GET_GPIO_TEST_8_QN_ID (((REG32(ADR_PAD67)) & 0x10000000 ) >> 28) -+#define GET_PAD69_OE (((REG32(ADR_PAD69)) & 0x00000001 ) >> 0) -+#define GET_PAD69_PE (((REG32(ADR_PAD69)) & 0x00000002 ) >> 1) -+#define GET_PAD69_DS (((REG32(ADR_PAD69)) & 0x00000004 ) >> 2) -+#define GET_PAD69_IE (((REG32(ADR_PAD69)) & 0x00000008 ) >> 3) -+#define GET_PAD69_SEL_I (((REG32(ADR_PAD69)) & 0x00000030 ) >> 4) -+#define GET_PAD69_OD (((REG32(ADR_PAD69)) & 0x00000100 ) >> 8) -+#define GET_PAD69_SEL_O (((REG32(ADR_PAD69)) & 0x00001000 ) >> 12) -+#define GET_STRAP2 (((REG32(ADR_PAD69)) & 0x08000000 ) >> 27) -+#define GET_GPIO_20_ID (((REG32(ADR_PAD69)) & 0x10000000 ) >> 28) -+#define GET_PAD70_OE (((REG32(ADR_PAD70)) & 0x00000001 ) >> 0) -+#define GET_PAD70_PE (((REG32(ADR_PAD70)) & 0x00000002 ) >> 1) -+#define GET_PAD70_DS (((REG32(ADR_PAD70)) & 0x00000004 ) >> 2) -+#define GET_PAD70_IE (((REG32(ADR_PAD70)) & 0x00000008 ) >> 3) -+#define GET_PAD70_SEL_I (((REG32(ADR_PAD70)) & 0x00000030 ) >> 4) -+#define GET_PAD70_OD (((REG32(ADR_PAD70)) & 0x00000100 ) >> 8) -+#define GET_PAD70_SEL_O (((REG32(ADR_PAD70)) & 0x00007000 ) >> 12) -+#define GET_GPIO_21_ID (((REG32(ADR_PAD70)) & 0x10000000 ) >> 28) -+#define GET_PAD231_OE (((REG32(ADR_PAD231)) & 0x00000001 ) >> 0) -+#define GET_PAD231_PE (((REG32(ADR_PAD231)) & 0x00000002 ) >> 1) -+#define GET_PAD231_DS (((REG32(ADR_PAD231)) & 0x00000004 ) >> 2) -+#define GET_PAD231_IE (((REG32(ADR_PAD231)) & 0x00000008 ) >> 3) -+#define GET_PAD231_OD (((REG32(ADR_PAD231)) & 0x00000100 ) >> 8) -+#define GET_PIN_40_OR_56_ID (((REG32(ADR_PAD231)) & 0x10000000 ) >> 28) -+#define GET_MP_PHY2RX_DATA__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000001 ) >> 0) -+#define GET_MP_PHY2RX_DATA__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000002 ) >> 1) -+#define GET_MP_TX_FF_RPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000004 ) >> 2) -+#define GET_MP_RX_FF_WPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000008 ) >> 3) -+#define GET_MP_RX_FF_WPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000010 ) >> 4) -+#define GET_MP_RX_FF_WPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000020 ) >> 5) -+#define GET_MP_PHY2RX_DATA__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000040 ) >> 6) -+#define GET_MP_PHY2RX_DATA__4_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000080 ) >> 7) -+#define GET_I2CM_SDA_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000300 ) >> 8) -+#define GET_CRYSTAL_OUT_REQ_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000400 ) >> 10) -+#define GET_MP_PHY2RX_DATA__5_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000800 ) >> 11) -+#define GET_MP_PHY2RX_DATA__3_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00001000 ) >> 12) -+#define GET_UART_RXD_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00006000 ) >> 13) -+#define GET_MP_PHY2RX_DATA__6_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00008000 ) >> 15) -+#define GET_DAT_UART_NCTS_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00010000 ) >> 16) -+#define GET_GPIO_LOG_STOP_SEL (((REG32(ADR_PIN_SEL_0)) & 0x000e0000 ) >> 17) -+#define GET_MP_TX_FF_RPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00100000 ) >> 20) -+#define GET_MP_PHY_RX_WRST_N_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00200000 ) >> 21) -+#define GET_EXT_32K_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00c00000 ) >> 22) -+#define GET_MP_PHY2RX_DATA__7_SEL (((REG32(ADR_PIN_SEL_0)) & 0x01000000 ) >> 24) -+#define GET_MP_TX_FF_RPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x02000000 ) >> 25) -+#define GET_PMUINT_WAKE_SEL (((REG32(ADR_PIN_SEL_0)) & 0x1c000000 ) >> 26) -+#define GET_I2CM_SCL_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x20000000 ) >> 29) -+#define GET_MP_MRX_RX_EN_SEL (((REG32(ADR_PIN_SEL_0)) & 0x40000000 ) >> 30) -+#define GET_DAT_UART_RXD_SEL_0 (((REG32(ADR_PIN_SEL_0)) & 0x80000000 ) >> 31) -+#define GET_DAT_UART_RXD_SEL_1 (((REG32(ADR_PIN_SEL_1)) & 0x00000001 ) >> 0) -+#define GET_SPI_DI_SEL (((REG32(ADR_PIN_SEL_1)) & 0x00000002 ) >> 1) -+#define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0) -+#define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0) -+#define GET_MASK_TX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1) -+#define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2) -+#define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3) -+#define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4) -+#define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5) -+#define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6) -+#define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7) -+#define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0) -+#define GET_TX_COMPLETE_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1) -+#define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2) -+#define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3) -+#define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4) -+#define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5) -+#define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6) -+#define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7) -+#define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8) -+#define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9) -+#define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10) -+#define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11) -+#define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0) -+#define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1) -+#define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2) -+#define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3) -+#define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4) -+#define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5) -+#define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7) -+#define GET_RX_PACKET_LENGTH (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x0000ffff ) >> 0) -+#define GET_CARD_FW_DL_STATUS (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x00ff0000 ) >> 16) -+#define GET_TX_RX_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x01000000 ) >> 24) -+#define GET_SDIO_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x02000000 ) >> 25) -+#define GET_CMD52_ABORT_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x10000000 ) >> 28) -+#define GET_CMD52_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x20000000 ) >> 29) -+#define GET_SDIO_PARTIAL_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x40000000 ) >> 30) -+#define GET_SDIO_ALL_RESE_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x80000000 ) >> 31) -+#define GET_RX_PACKET_LENGTH2 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x0000ffff ) >> 0) -+#define GET_RX_INT1 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00010000 ) >> 16) -+#define GET_TX_DONE (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00020000 ) >> 17) -+#define GET_HCI_TRX_FINISH (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00040000 ) >> 18) -+#define GET_ALLOCATE_STATUS (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00080000 ) >> 19) -+#define GET_HCI_INPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00f00000 ) >> 20) -+#define GET_HCI_OUTPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x1f000000 ) >> 24) -+#define GET_AHB_HANG4 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x20000000 ) >> 29) -+#define GET_HCI_IN_QUE_EMPTY (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x40000000 ) >> 30) -+#define GET_SYSTEM_INT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x80000000 ) >> 31) -+#define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0) -+#define GET_SDIO_FIFO_WR_THLD_REG (((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0x000001ff ) >> 0) -+#define GET_SDIO_FIFO_WR_LIMIT_REG (((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0x000001ff ) >> 0) -+#define GET_SDIO_TX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0) -+#define GET_SDIO_THLD_FOR_CMD53RD_REG (((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0x000001ff ) >> 0) -+#define GET_SDIO_RX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0) -+#define GET_START_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x000000ff ) >> 0) -+#define GET_END_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x0000ff00 ) >> 8) -+#define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0) -+#define GET_SDIO_LAST_CMD_INDEX_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x0000003f ) >> 0) -+#define GET_SDIO_LAST_CMD_CRC_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x00007f00 ) >> 8) -+#define GET_SDIO_LAST_CMD_ARG_REG (((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0xffffffff ) >> 0) -+#define GET_SDIO_BUS_STATE_REG (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000001f ) >> 0) -+#define GET_SDIO_BUSY_LONG_CNT (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffff0000 ) >> 16) -+#define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0) -+#define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0) -+#define GET_RESP_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000100 ) >> 8) -+#define GET_DAT_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000200 ) >> 9) -+#define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16) -+#define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17) -+#define GET_WRITE_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x000000ff ) >> 0) -+#define GET_WRITE_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x0000ff00 ) >> 8) -+#define GET_READ_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ff0000 ) >> 16) -+#define GET_READ_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff000000 ) >> 24) -+#define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0) -+#define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0) -+#define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8) -+#define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9) -+#define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10) -+#define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11) -+#define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12) -+#define GET_IO_REG_PORT_REG (((REG32(ADR_IO_REG_PORT_REG)) & 0x0001ffff ) >> 0) -+#define GET_SDIO_FIFO_EMPTY_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff ) >> 0) -+#define GET_SDIO_FIFO_FULL_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000 ) >> 16) -+#define GET_SDIO_CRC7_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff ) >> 0) -+#define GET_SDIO_CRC16_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000 ) >> 16) -+#define GET_SDIO_RD_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x000001ff ) >> 0) -+#define GET_SDIO_WR_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x01ff0000 ) >> 16) -+#define GET_CMD52_RD_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x000f0000 ) >> 16) -+#define GET_CMD52_WR_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x00f00000 ) >> 20) -+#define GET_SDIO_FIFO_WR_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x000000ff ) >> 0) -+#define GET_SDIO_FIFO_RD_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x0000ff00 ) >> 8) -+#define GET_SDIO_READ_DATA_CTRL (((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0x00010000 ) >> 16) -+#define GET_TX_SIZE_BEFORE_SHIFT (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x000000ff ) >> 0) -+#define GET_TX_SIZE_SHIFT_BITS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00000700 ) >> 8) -+#define GET_SDIO_TX_ALLOC_STATE (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00001000 ) >> 12) -+#define GET_ALLOCATE_STATUS2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00010000 ) >> 16) -+#define GET_NO_ALLOCATE_SEND_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00020000 ) >> 17) -+#define GET_DOUBLE_ALLOCATE_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00040000 ) >> 18) -+#define GET_TX_DONE_STATUS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00080000 ) >> 19) -+#define GET_AHB_HANG2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00100000 ) >> 20) -+#define GET_HCI_TRX_FINISH2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00200000 ) >> 21) -+#define GET_INTR_RX (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00400000 ) >> 22) -+#define GET_HCI_INPUT_QUEUE_FULL (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00800000 ) >> 23) -+#define GET_ALLOCATESTATUS (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000001 ) >> 0) -+#define GET_HCI_TRX_FINISH3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000002 ) >> 1) -+#define GET_HCI_IN_QUE_EMPTY2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000004 ) >> 2) -+#define GET_MTX_MNG_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000008 ) >> 3) -+#define GET_EDCA0_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000010 ) >> 4) -+#define GET_EDCA1_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000020 ) >> 5) -+#define GET_EDCA2_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000040 ) >> 6) -+#define GET_EDCA3_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000080 ) >> 7) -+#define GET_TX_PAGE_REMAIN2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0000ff00 ) >> 8) -+#define GET_TX_ID_REMAIN3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x007f0000 ) >> 16) -+#define GET_HCI_OUTPUT_FF_CNT_0 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00800000 ) >> 23) -+#define GET_HCI_OUTPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0f000000 ) >> 24) -+#define GET_HCI_INPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0xf0000000 ) >> 28) -+#define GET_F1_BLOCK_SIZE_0_REG (((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0x00000fff ) >> 0) -+#define GET_START_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x000000ff ) >> 0) -+#define GET_COMMAND_COUNTER (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ff00 ) >> 8) -+#define GET_CMD_LOG_PART1 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff0000 ) >> 16) -+#define GET_CMD_LOG_PART2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff ) >> 0) -+#define GET_END_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000 ) >> 24) -+#define GET_RX_PACKET_LENGTH3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x0000ffff ) >> 0) -+#define GET_RX_INT3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00010000 ) >> 16) -+#define GET_TX_ID_REMAIN2 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00fe0000 ) >> 17) -+#define GET_TX_PAGE_REMAIN3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff000000 ) >> 24) -+#define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0) -+#define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16) -+#define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24) -+#define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0) -+#define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8) -+#define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16) -+#define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24) -+#define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0) -+#define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1) -+#define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2) -+#define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3) -+#define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4) -+#define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5) -+#define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6) -+#define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7) -+#define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8) -+#define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24) -+#define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25) -+#define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0) -+#define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6) -+#define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7) -+#define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8) -+#define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8) -+#define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0) -+#define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0) -+#define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0) -+#define GET_SPI_MODE (((REG32(ADR_SPI_MODE)) & 0xffffffff ) >> 0) -+#define GET_RX_QUOTA (((REG32(ADR_RX_QUOTA)) & 0x0000ffff ) >> 0) -+#define GET_CONDI_NUM (((REG32(ADR_CONDITION_NUMBER)) & 0x000000ff ) >> 0) -+#define GET_HOST_PATH (((REG32(ADR_HOST_PATH)) & 0x00000001 ) >> 0) -+#define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0) -+#define GET_BRST_MODE (((REG32(ADR_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0) -+#define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0) -+#define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16) -+#define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0) -+#define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16) -+#define GET_RX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000002 ) >> 1) -+#define GET_RX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000004 ) >> 2) -+#define GET_TX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000008 ) >> 3) -+#define GET_TX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000010 ) >> 4) -+#define GET_SPI_DOUBLE_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000020 ) >> 5) -+#define GET_SPI_TX_NO_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000040 ) >> 6) -+#define GET_RDATA_RDY (((REG32(ADR_SPI_STS)) & 0x00000080 ) >> 7) -+#define GET_SPI_ALLOC_STATUS (((REG32(ADR_SPI_STS)) & 0x00000100 ) >> 8) -+#define GET_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_SPI_STS)) & 0x00000200 ) >> 9) -+#define GET_RX_LEN (((REG32(ADR_SPI_STS)) & 0xffff0000 ) >> 16) -+#define GET_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_TX_ALLOC_SET)) & 0x00000007 ) >> 0) -+#define GET_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_TX_ALLOC_SET)) & 0x00000100 ) >> 8) -+#define GET_SPI_TX_ALLOC_SIZE (((REG32(ADR_TX_ALLOC)) & 0x000000ff ) >> 0) -+#define GET_RD_DAT_CNT (((REG32(ADR_DBG_CNT)) & 0x0000ffff ) >> 0) -+#define GET_RD_STS_CNT (((REG32(ADR_DBG_CNT)) & 0xffff0000 ) >> 16) -+#define GET_JUDGE_CNT (((REG32(ADR_DBG_CNT2)) & 0x0000ffff ) >> 0) -+#define GET_RD_STS_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00010000 ) >> 16) -+#define GET_RD_DAT_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00020000 ) >> 17) -+#define GET_JUDGE_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00040000 ) >> 18) -+#define GET_TX_DONE_CNT (((REG32(ADR_DBG_CNT3)) & 0x0000ffff ) >> 0) -+#define GET_TX_DISCARD_CNT (((REG32(ADR_DBG_CNT3)) & 0xffff0000 ) >> 16) -+#define GET_TX_SET_CNT (((REG32(ADR_DBG_CNT4)) & 0x0000ffff ) >> 0) -+#define GET_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00010000 ) >> 16) -+#define GET_TX_DONE_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00020000 ) >> 17) -+#define GET_TX_SET_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00040000 ) >> 18) -+#define GET_DAT_MODE_OFF (((REG32(ADR_DBG_CNT4)) & 0x00080000 ) >> 19) -+#define GET_TX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x00700000 ) >> 20) -+#define GET_RX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x07000000 ) >> 24) -+#define GET_RX_RDY (((REG32(ADR_INT_TAG)) & 0x00000001 ) >> 0) -+#define GET_SDIO_SYS_INT (((REG32(ADR_INT_TAG)) & 0x00000004 ) >> 2) -+#define GET_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000008 ) >> 3) -+#define GET_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000010 ) >> 4) -+#define GET_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000020 ) >> 5) -+#define GET_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000040 ) >> 6) -+#define GET_TX_LIMIT_INT_IN (((REG32(ADR_INT_TAG)) & 0x00000080 ) >> 7) -+#define GET_SPI_FN1 (((REG32(ADR_INT_TAG)) & 0x00007f00 ) >> 8) -+#define GET_SPI_CLK_EN_INT (((REG32(ADR_INT_TAG)) & 0x00008000 ) >> 15) -+#define GET_SPI_HOST_MASK (((REG32(ADR_INT_TAG)) & 0x00ff0000 ) >> 16) -+#define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0) -+#define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1) -+#define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2) -+#define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3) -+#define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4) -+#define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16) -+#define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17) -+#define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18) -+#define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0) -+#define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14) -+#define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15) -+#define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0) -+#define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16) -+#define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24) -+#define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0) -+#define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0) -+#define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0) -+#define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16) -+#define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17) -+#define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0) -+#define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0) -+#define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1) -+#define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2) -+#define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3) -+#define GET_DMA_RXEND_IE (((REG32(ADR_UART_IER)) & 0x00000040 ) >> 6) -+#define GET_DMA_TXEND_IE (((REG32(ADR_UART_IER)) & 0x00000080 ) >> 7) -+#define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0) -+#define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1) -+#define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2) -+#define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3) -+#define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4) -+#define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5) -+#define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6) -+#define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0) -+#define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2) -+#define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3) -+#define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4) -+#define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5) -+#define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6) -+#define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7) -+#define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0) -+#define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1) -+#define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2) -+#define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3) -+#define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4) -+#define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0) -+#define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1) -+#define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2) -+#define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3) -+#define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4) -+#define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5) -+#define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6) -+#define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7) -+#define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0) -+#define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1) -+#define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2) -+#define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3) -+#define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4) -+#define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5) -+#define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6) -+#define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7) -+#define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0) -+#define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0) -+#define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4) -+#define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0) -+#define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6) -+#define GET_DAT_UART_DATA (((REG32(ADR_DAT_UART_DATA)) & 0x000000ff ) >> 0) -+#define GET_DAT_DATA_RDY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000001 ) >> 0) -+#define GET_DAT_THR_EMPTY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000002 ) >> 1) -+#define GET_DAT_RX_LINESTS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000004 ) >> 2) -+#define GET_DAT_MDM_STS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000008 ) >> 3) -+#define GET_DAT_DMA_RXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000040 ) >> 6) -+#define GET_DAT_DMA_TXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000080 ) >> 7) -+#define GET_DAT_FIFO_EN (((REG32(ADR_DAT_UART_FCR)) & 0x00000001 ) >> 0) -+#define GET_DAT_RXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000002 ) >> 1) -+#define GET_DAT_TXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000004 ) >> 2) -+#define GET_DAT_DMA_MODE (((REG32(ADR_DAT_UART_FCR)) & 0x00000008 ) >> 3) -+#define GET_DAT_EN_AUTO_RTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000010 ) >> 4) -+#define GET_DAT_EN_AUTO_CTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000020 ) >> 5) -+#define GET_DAT_RXFIFO_TRGLVL (((REG32(ADR_DAT_UART_FCR)) & 0x000000c0 ) >> 6) -+#define GET_DAT_WORD_LEN (((REG32(ADR_DAT_UART_LCR)) & 0x00000003 ) >> 0) -+#define GET_DAT_STOP_BIT (((REG32(ADR_DAT_UART_LCR)) & 0x00000004 ) >> 2) -+#define GET_DAT_PARITY_EN (((REG32(ADR_DAT_UART_LCR)) & 0x00000008 ) >> 3) -+#define GET_DAT_EVEN_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000010 ) >> 4) -+#define GET_DAT_FORCE_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000020 ) >> 5) -+#define GET_DAT_SET_BREAK (((REG32(ADR_DAT_UART_LCR)) & 0x00000040 ) >> 6) -+#define GET_DAT_DLAB (((REG32(ADR_DAT_UART_LCR)) & 0x00000080 ) >> 7) -+#define GET_DAT_DTR (((REG32(ADR_DAT_UART_MCR)) & 0x00000001 ) >> 0) -+#define GET_DAT_RTS (((REG32(ADR_DAT_UART_MCR)) & 0x00000002 ) >> 1) -+#define GET_DAT_OUT_1 (((REG32(ADR_DAT_UART_MCR)) & 0x00000004 ) >> 2) -+#define GET_DAT_OUT_2 (((REG32(ADR_DAT_UART_MCR)) & 0x00000008 ) >> 3) -+#define GET_DAT_LOOP_BACK (((REG32(ADR_DAT_UART_MCR)) & 0x00000010 ) >> 4) -+#define GET_DAT_DATA_RDY (((REG32(ADR_DAT_UART_LSR)) & 0x00000001 ) >> 0) -+#define GET_DAT_OVERRUN_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000002 ) >> 1) -+#define GET_DAT_PARITY_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000004 ) >> 2) -+#define GET_DAT_FRAMING_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000008 ) >> 3) -+#define GET_DAT_BREAK_INT (((REG32(ADR_DAT_UART_LSR)) & 0x00000010 ) >> 4) -+#define GET_DAT_THR_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000020 ) >> 5) -+#define GET_DAT_TX_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000040 ) >> 6) -+#define GET_DAT_FIFODATA_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000080 ) >> 7) -+#define GET_DAT_DELTA_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000001 ) >> 0) -+#define GET_DAT_DELTA_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000002 ) >> 1) -+#define GET_DAT_TRAILEDGE_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000004 ) >> 2) -+#define GET_DAT_DELTA_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000008 ) >> 3) -+#define GET_DAT_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000010 ) >> 4) -+#define GET_DAT_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000020 ) >> 5) -+#define GET_DAT_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000040 ) >> 6) -+#define GET_DAT_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000080 ) >> 7) -+#define GET_DAT_BRDC_DIV (((REG32(ADR_DAT_UART_SPR)) & 0x0000ffff ) >> 0) -+#define GET_DAT_RTHR_L (((REG32(ADR_DAT_UART_RTHR)) & 0x0000000f ) >> 0) -+#define GET_DAT_RTHR_H (((REG32(ADR_DAT_UART_RTHR)) & 0x000000f0 ) >> 4) -+#define GET_DAT_INT_IDCODE (((REG32(ADR_DAT_UART_ISR)) & 0x0000000f ) >> 0) -+#define GET_DAT_FIFOS_ENABLED (((REG32(ADR_DAT_UART_ISR)) & 0x000000c0 ) >> 6) -+#define GET_MASK_TOP (((REG32(ADR_INT_MASK)) & 0xffffffff ) >> 0) -+#define GET_INT_MODE (((REG32(ADR_INT_MODE)) & 0xffffffff ) >> 0) -+#define GET_IRQ_PHY_0 (((REG32(ADR_INT_IRQ_STS)) & 0x00000001 ) >> 0) -+#define GET_IRQ_PHY_1 (((REG32(ADR_INT_IRQ_STS)) & 0x00000002 ) >> 1) -+#define GET_IRQ_SDIO (((REG32(ADR_INT_IRQ_STS)) & 0x00000004 ) >> 2) -+#define GET_IRQ_BEACON_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000008 ) >> 3) -+#define GET_IRQ_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000010 ) >> 4) -+#define GET_IRQ_PRE_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000020 ) >> 5) -+#define GET_IRQ_EDCA0_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000040 ) >> 6) -+#define GET_IRQ_EDCA1_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000080 ) >> 7) -+#define GET_IRQ_EDCA2_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000100 ) >> 8) -+#define GET_IRQ_EDCA3_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000200 ) >> 9) -+#define GET_IRQ_EDCA4_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000400 ) >> 10) -+#define GET_IRQ_BEACON_DTIM (((REG32(ADR_INT_IRQ_STS)) & 0x00001000 ) >> 12) -+#define GET_IRQ_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00002000 ) >> 13) -+#define GET_IRQ_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00004000 ) >> 14) -+#define GET_IRQ_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00008000 ) >> 15) -+#define GET_IRQ_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00010000 ) >> 16) -+#define GET_IRQ_FENCE_HIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00020000 ) >> 17) -+#define GET_IRQ_ILL_ADDR_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00040000 ) >> 18) -+#define GET_IRQ_MBOX (((REG32(ADR_INT_IRQ_STS)) & 0x00080000 ) >> 19) -+#define GET_IRQ_US_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x00100000 ) >> 20) -+#define GET_IRQ_US_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x00200000 ) >> 21) -+#define GET_IRQ_US_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x00400000 ) >> 22) -+#define GET_IRQ_US_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x00800000 ) >> 23) -+#define GET_IRQ_MS_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x01000000 ) >> 24) -+#define GET_IRQ_MS_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x02000000 ) >> 25) -+#define GET_IRQ_MS_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x04000000 ) >> 26) -+#define GET_IRQ_MS_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x08000000 ) >> 27) -+#define GET_IRQ_TX_LIMIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x10000000 ) >> 28) -+#define GET_IRQ_DMA0 (((REG32(ADR_INT_IRQ_STS)) & 0x20000000 ) >> 29) -+#define GET_IRQ_CO_DMA (((REG32(ADR_INT_IRQ_STS)) & 0x40000000 ) >> 30) -+#define GET_IRQ_PERI_GROUP (((REG32(ADR_INT_IRQ_STS)) & 0x80000000 ) >> 31) -+#define GET_FIQ_STATUS (((REG32(ADR_INT_FIQ_STS)) & 0xffffffff ) >> 0) -+#define GET_IRQ_RAW (((REG32(ADR_INT_IRQ_RAW)) & 0xffffffff ) >> 0) -+#define GET_FIQ_RAW (((REG32(ADR_INT_FIQ_RAW)) & 0xffffffff ) >> 0) -+#define GET_INT_PERI_MASK (((REG32(ADR_INT_PERI_MASK)) & 0xffffffff ) >> 0) -+#define GET_PERI_RTC (((REG32(ADR_INT_PERI_STS)) & 0x00000001 ) >> 0) -+#define GET_IRQ_UART0_TX (((REG32(ADR_INT_PERI_STS)) & 0x00000002 ) >> 1) -+#define GET_IRQ_UART0_RX (((REG32(ADR_INT_PERI_STS)) & 0x00000004 ) >> 2) -+#define GET_PERI_GPI_2 (((REG32(ADR_INT_PERI_STS)) & 0x00000008 ) >> 3) -+#define GET_IRQ_SPI_IPC (((REG32(ADR_INT_PERI_STS)) & 0x00000010 ) >> 4) -+#define GET_PERI_GPI_1_0 (((REG32(ADR_INT_PERI_STS)) & 0x00000060 ) >> 5) -+#define GET_SCRT_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000080 ) >> 7) -+#define GET_MMU_ALC_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000100 ) >> 8) -+#define GET_MMU_RLS_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000200 ) >> 9) -+#define GET_ID_MNG_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000400 ) >> 10) -+#define GET_MBOX_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000800 ) >> 11) -+#define GET_MBOX_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00001000 ) >> 12) -+#define GET_MBOX_INT_3 (((REG32(ADR_INT_PERI_STS)) & 0x00002000 ) >> 13) -+#define GET_HCI_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00004000 ) >> 14) -+#define GET_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x00008000 ) >> 15) -+#define GET_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x00010000 ) >> 16) -+#define GET_ID_MNG_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00020000 ) >> 17) -+#define GET_DMN_NOHIT_INT (((REG32(ADR_INT_PERI_STS)) & 0x00040000 ) >> 18) -+#define GET_ID_THOLD_RX (((REG32(ADR_INT_PERI_STS)) & 0x00080000 ) >> 19) -+#define GET_ID_THOLD_TX (((REG32(ADR_INT_PERI_STS)) & 0x00100000 ) >> 20) -+#define GET_ID_DOUBLE_RLS (((REG32(ADR_INT_PERI_STS)) & 0x00200000 ) >> 21) -+#define GET_RX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00400000 ) >> 22) -+#define GET_TX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00800000 ) >> 23) -+#define GET_ALL_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x01000000 ) >> 24) -+#define GET_DMN_MCU_INT (((REG32(ADR_INT_PERI_STS)) & 0x02000000 ) >> 25) -+#define GET_IRQ_DAT_UART_TX (((REG32(ADR_INT_PERI_STS)) & 0x04000000 ) >> 26) -+#define GET_IRQ_DAT_UART_RX (((REG32(ADR_INT_PERI_STS)) & 0x08000000 ) >> 27) -+#define GET_DAT_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x10000000 ) >> 28) -+#define GET_DAT_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x20000000 ) >> 29) -+#define GET_ALR_ABT_NOCHG_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x40000000 ) >> 30) -+#define GET_TBLNEQ_MNGPKT_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x80000000 ) >> 31) -+#define GET_INTR_PERI_RAW (((REG32(ADR_INT_PERI_RAW)) & 0xffffffff ) >> 0) -+#define GET_INTR_GPI00_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x00000003 ) >> 0) -+#define GET_INTR_GPI01_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x0000000c ) >> 2) -+#define GET_SYS_RST_INT (((REG32(ADR_SYS_INT_FOR_HOST)) & 0x00000001 ) >> 0) -+#define GET_SPI_IPC_ADDR (((REG32(ADR_SPI_IPC)) & 0xffffffff ) >> 0) -+#define GET_SD_MASK_TOP (((REG32(ADR_SDIO_MASK)) & 0xffffffff ) >> 0) -+#define GET_IRQ_PHY_0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000001 ) >> 0) -+#define GET_IRQ_PHY_1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000002 ) >> 1) -+#define GET_IRQ_SDIO_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000004 ) >> 2) -+#define GET_IRQ_BEACON_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000008 ) >> 3) -+#define GET_IRQ_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000010 ) >> 4) -+#define GET_IRQ_PRE_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000020 ) >> 5) -+#define GET_IRQ_EDCA0_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000040 ) >> 6) -+#define GET_IRQ_EDCA1_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000080 ) >> 7) -+#define GET_IRQ_EDCA2_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000100 ) >> 8) -+#define GET_IRQ_EDCA3_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000200 ) >> 9) -+#define GET_IRQ_EDCA4_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000400 ) >> 10) -+#define GET_IRQ_BEACON_DTIM_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00001000 ) >> 12) -+#define GET_IRQ_EDCA0_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00002000 ) >> 13) -+#define GET_IRQ_EDCA1_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00004000 ) >> 14) -+#define GET_IRQ_EDCA2_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00008000 ) >> 15) -+#define GET_IRQ_EDCA3_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00010000 ) >> 16) -+#define GET_IRQ_FENCE_HIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00020000 ) >> 17) -+#define GET_IRQ_ILL_ADDR_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00040000 ) >> 18) -+#define GET_IRQ_MBOX_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00080000 ) >> 19) -+#define GET_IRQ_US_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00100000 ) >> 20) -+#define GET_IRQ_US_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00200000 ) >> 21) -+#define GET_IRQ_US_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00400000 ) >> 22) -+#define GET_IRQ_US_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00800000 ) >> 23) -+#define GET_IRQ_MS_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x01000000 ) >> 24) -+#define GET_IRQ_MS_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x02000000 ) >> 25) -+#define GET_IRQ_MS_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x04000000 ) >> 26) -+#define GET_IRQ_MS_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x08000000 ) >> 27) -+#define GET_IRQ_TX_LIMIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x10000000 ) >> 28) -+#define GET_IRQ_DMA0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x20000000 ) >> 29) -+#define GET_IRQ_CO_DMA_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x40000000 ) >> 30) -+#define GET_IRQ_PERI_GROUP_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x80000000 ) >> 31) -+#define GET_INT_PERI_MASK_SD (((REG32(ADR_SD_PERI_MASK)) & 0xffffffff ) >> 0) -+#define GET_PERI_RTC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000001 ) >> 0) -+#define GET_IRQ_UART0_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000002 ) >> 1) -+#define GET_IRQ_UART0_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000004 ) >> 2) -+#define GET_PERI_GPI_SD_2 (((REG32(ADR_SD_PERI_STS)) & 0x00000008 ) >> 3) -+#define GET_IRQ_SPI_IPC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000010 ) >> 4) -+#define GET_PERI_GPI_SD_1_0 (((REG32(ADR_SD_PERI_STS)) & 0x00000060 ) >> 5) -+#define GET_SCRT_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000080 ) >> 7) -+#define GET_MMU_ALC_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000100 ) >> 8) -+#define GET_MMU_RLS_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000200 ) >> 9) -+#define GET_ID_MNG_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000400 ) >> 10) -+#define GET_MBOX_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000800 ) >> 11) -+#define GET_MBOX_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00001000 ) >> 12) -+#define GET_MBOX_INT_3_SD (((REG32(ADR_SD_PERI_STS)) & 0x00002000 ) >> 13) -+#define GET_HCI_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00004000 ) >> 14) -+#define GET_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00008000 ) >> 15) -+#define GET_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x00010000 ) >> 16) -+#define GET_ID_MNG_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00020000 ) >> 17) -+#define GET_DMN_NOHIT_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00040000 ) >> 18) -+#define GET_ID_THOLD_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00080000 ) >> 19) -+#define GET_ID_THOLD_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00100000 ) >> 20) -+#define GET_ID_DOUBLE_RLS_SD (((REG32(ADR_SD_PERI_STS)) & 0x00200000 ) >> 21) -+#define GET_RX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00400000 ) >> 22) -+#define GET_TX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00800000 ) >> 23) -+#define GET_ALL_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x01000000 ) >> 24) -+#define GET_DMN_MCU_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x02000000 ) >> 25) -+#define GET_IRQ_DAT_UART_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x04000000 ) >> 26) -+#define GET_IRQ_DAT_UART_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x08000000 ) >> 27) -+#define GET_DAT_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x10000000 ) >> 28) -+#define GET_DAT_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x20000000 ) >> 29) -+#define GET_ALR_ABT_NOCHG_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x40000000 ) >> 30) -+#define GET_TBLNEQ_MNGPKT_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x80000000 ) >> 31) -+#define GET_DBG_SPI_MODE (((REG32(ADR_DBG_SPI_MODE)) & 0xffffffff ) >> 0) -+#define GET_DBG_RX_QUOTA (((REG32(ADR_DBG_RX_QUOTA)) & 0x0000ffff ) >> 0) -+#define GET_DBG_CONDI_NUM (((REG32(ADR_DBG_CONDITION_NUMBER)) & 0x000000ff ) >> 0) -+#define GET_DBG_HOST_PATH (((REG32(ADR_DBG_HOST_PATH)) & 0x00000001 ) >> 0) -+#define GET_DBG_TX_SEG (((REG32(ADR_DBG_TX_SEG)) & 0xffffffff ) >> 0) -+#define GET_DBG_BRST_MODE (((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0) -+#define GET_DBG_CLK_WIDTH (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0) -+#define GET_DBG_CSN_INTER (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16) -+#define GET_DBG_BACK_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0) -+#define GET_DBG_FRONT_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16) -+#define GET_DBG_RX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000002 ) >> 1) -+#define GET_DBG_RX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000004 ) >> 2) -+#define GET_DBG_TX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000008 ) >> 3) -+#define GET_DBG_TX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000010 ) >> 4) -+#define GET_DBG_SPI_DOUBLE_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000020 ) >> 5) -+#define GET_DBG_SPI_TX_NO_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000040 ) >> 6) -+#define GET_DBG_RDATA_RDY (((REG32(ADR_DBG_SPI_STS)) & 0x00000080 ) >> 7) -+#define GET_DBG_SPI_ALLOC_STATUS (((REG32(ADR_DBG_SPI_STS)) & 0x00000100 ) >> 8) -+#define GET_DBG_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_DBG_SPI_STS)) & 0x00000200 ) >> 9) -+#define GET_DBG_RX_LEN (((REG32(ADR_DBG_SPI_STS)) & 0xffff0000 ) >> 16) -+#define GET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000007 ) >> 0) -+#define GET_DBG_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000100 ) >> 8) -+#define GET_DBG_SPI_TX_ALLOC_SIZE (((REG32(ADR_DBG_TX_ALLOC)) & 0x000000ff ) >> 0) -+#define GET_DBG_RD_DAT_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff ) >> 0) -+#define GET_DBG_RD_STS_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000 ) >> 16) -+#define GET_DBG_JUDGE_CNT (((REG32(ADR_DBG_DBG_CNT2)) & 0x0000ffff ) >> 0) -+#define GET_DBG_RD_STS_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00010000 ) >> 16) -+#define GET_DBG_RD_DAT_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00020000 ) >> 17) -+#define GET_DBG_JUDGE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00040000 ) >> 18) -+#define GET_DBG_TX_DONE_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff ) >> 0) -+#define GET_DBG_TX_DISCARD_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000 ) >> 16) -+#define GET_DBG_TX_SET_CNT (((REG32(ADR_DBG_DBG_CNT4)) & 0x0000ffff ) >> 0) -+#define GET_DBG_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00010000 ) >> 16) -+#define GET_DBG_TX_DONE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00020000 ) >> 17) -+#define GET_DBG_TX_SET_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00040000 ) >> 18) -+#define GET_DBG_DAT_MODE_OFF (((REG32(ADR_DBG_DBG_CNT4)) & 0x00080000 ) >> 19) -+#define GET_DBG_TX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x00700000 ) >> 20) -+#define GET_DBG_RX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x07000000 ) >> 24) -+#define GET_DBG_RX_RDY (((REG32(ADR_DBG_INT_TAG)) & 0x00000001 ) >> 0) -+#define GET_DBG_SDIO_SYS_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000004 ) >> 2) -+#define GET_DBG_EDCA0_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000008 ) >> 3) -+#define GET_DBG_EDCA1_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000010 ) >> 4) -+#define GET_DBG_EDCA2_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000020 ) >> 5) -+#define GET_DBG_EDCA3_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000040 ) >> 6) -+#define GET_DBG_TX_LIMIT_INT_IN (((REG32(ADR_DBG_INT_TAG)) & 0x00000080 ) >> 7) -+#define GET_DBG_SPI_FN1 (((REG32(ADR_DBG_INT_TAG)) & 0x00007f00 ) >> 8) -+#define GET_DBG_SPI_CLK_EN_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00008000 ) >> 15) -+#define GET_DBG_SPI_HOST_MASK (((REG32(ADR_DBG_INT_TAG)) & 0x00ff0000 ) >> 16) -+#define GET_BOOT_ADDR (((REG32(ADR_BOOT_ADDR)) & 0x00ffffff ) >> 0) -+#define GET_CHECK_SUM_FAIL (((REG32(ADR_BOOT_ADDR)) & 0x80000000 ) >> 31) -+#define GET_VERIFY_DATA (((REG32(ADR_VERIFY_DATA)) & 0xffffffff ) >> 0) -+#define GET_FLASH_ADDR (((REG32(ADR_FLASH_ADDR)) & 0x00ffffff ) >> 0) -+#define GET_FLASH_CMD_CLR (((REG32(ADR_FLASH_ADDR)) & 0x10000000 ) >> 28) -+#define GET_FLASH_DMA_CLR (((REG32(ADR_FLASH_ADDR)) & 0x20000000 ) >> 29) -+#define GET_DMA_EN (((REG32(ADR_FLASH_ADDR)) & 0x40000000 ) >> 30) -+#define GET_DMA_BUSY (((REG32(ADR_FLASH_ADDR)) & 0x80000000 ) >> 31) -+#define GET_SRAM_ADDR (((REG32(ADR_SRAM_ADDR)) & 0xffffffff ) >> 0) -+#define GET_FLASH_DMA_LEN (((REG32(ADR_LEN)) & 0xffffffff ) >> 0) -+#define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000ffff ) >> 0) -+#define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0xffff0000 ) >> 16) -+#define GET_FLASH_CLK_WIDTH (((REG32(ADR_SPI_PARAM2)) & 0x0000ffff ) >> 0) -+#define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00010000 ) >> 16) -+#define GET_FLS_REMAP (((REG32(ADR_SPI_PARAM2)) & 0x00020000 ) >> 17) -+#define GET_PBUS_SWP (((REG32(ADR_SPI_PARAM2)) & 0x00040000 ) >> 18) -+#define GET_BIT_MODE1 (((REG32(ADR_SPI_PARAM2)) & 0x00080000 ) >> 19) -+#define GET_BIT_MODE2 (((REG32(ADR_SPI_PARAM2)) & 0x00100000 ) >> 20) -+#define GET_BIT_MODE4 (((REG32(ADR_SPI_PARAM2)) & 0x00200000 ) >> 21) -+#define GET_BOOT_CHECK_SUM (((REG32(ADR_CHECK_SUM_RESULT)) & 0xffffffff ) >> 0) -+#define GET_CHECK_SUM_TAG (((REG32(ADR_CHECK_SUM_IN_FILE)) & 0xffffffff ) >> 0) -+#define GET_CMD_LEN (((REG32(ADR_COMMAND_LEN)) & 0x0000ffff ) >> 0) -+#define GET_CMD_ADDR (((REG32(ADR_COMMAND_ADDR)) & 0xffffffff ) >> 0) -+#define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0) -+#define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0) -+#define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0) -+#define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3) -+#define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4) -+#define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7) -+#define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8) -+#define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12) -+#define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13) -+#define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16) -+#define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0) -+#define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8) -+#define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31) -+#define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0) -+#define GET_SLEEP_WAKE_CNT (((REG32(ADR_PMU_0)) & 0x00ffffff ) >> 0) -+#define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_0)) & 0x07000000 ) >> 24) -+#define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_0)) & 0x08000000 ) >> 27) -+#define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_0)) & 0x70000000 ) >> 28) -+#define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_0)) & 0x80000000 ) >> 31) -+#define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_1)) & 0x000003ff ) >> 0) -+#define GET_RG_RTC_OSC_RES_SW (((REG32(ADR_PMU_1)) & 0x03ff0000 ) >> 16) -+#define GET_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_1)) & 0x80000000 ) >> 31) -+#define GET_RG_DCDC_MODE (((REG32(ADR_PMU_2)) & 0x00000001 ) >> 0) -+#define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_2)) & 0x00000010 ) >> 4) -+#define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_2)) & 0x00000100 ) >> 8) -+#define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_2)) & 0x00001000 ) >> 12) -+#define GET_RG_RTC_RDY_DEGLITCH_TIMER (((REG32(ADR_PMU_2)) & 0x00006000 ) >> 13) -+#define GET_RTC_CAL_ENA (((REG32(ADR_PMU_2)) & 0x00010000 ) >> 16) -+#define GET_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_3)) & 0x00000003 ) >> 0) -+#define GET_DIGI_TOP_POR_MASK (((REG32(ADR_PMU_3)) & 0x00000010 ) >> 4) -+#define GET_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_3)) & 0x00000100 ) >> 8) -+#define GET_RG_RTC_DUMMIES (((REG32(ADR_PMU_3)) & 0xffff0000 ) >> 16) -+#define GET_RTC_EN (((REG32(ADR_RTC_1)) & 0x00000001 ) >> 0) -+#define GET_RTC_SRC (((REG32(ADR_RTC_1)) & 0x00000002 ) >> 1) -+#define GET_RTC_TICK_CNT (((REG32(ADR_RTC_1)) & 0x7fff0000 ) >> 16) -+#define GET_RTC_INT_SEC_MASK (((REG32(ADR_RTC_2)) & 0x00000001 ) >> 0) -+#define GET_RTC_INT_ALARM_MASK (((REG32(ADR_RTC_2)) & 0x00000002 ) >> 1) -+#define GET_RTC_INT_SEC (((REG32(ADR_RTC_2)) & 0x00010000 ) >> 16) -+#define GET_RTC_INT_ALARM (((REG32(ADR_RTC_2)) & 0x00020000 ) >> 17) -+#define GET_RTC_SEC_START_CNT (((REG32(ADR_RTC_3W)) & 0xffffffff ) >> 0) -+#define GET_RTC_SEC_CNT (((REG32(ADR_RTC_3R)) & 0xffffffff ) >> 0) -+#define GET_RTC_SEC_ALARM_VALUE (((REG32(ADR_RTC_4)) & 0xffffffff ) >> 0) -+#define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0) -+#define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0) -+#define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0) -+#define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3) -+#define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4) -+#define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7) -+#define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8) -+#define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12) -+#define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13) -+#define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16) -+#define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0) -+#define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8) -+#define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31) -+#define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0) -+#define GET_TRAP_UNKNOWN_TYPE (((REG32(ADR_CONTROL)) & 0x00000001 ) >> 0) -+#define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1) -+#define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2) -+#define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3) -+#define GET_BYPASSS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4) -+#define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5) -+#define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6) -+#define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8) -+#define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12) -+#define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16) -+#define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20) -+#define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21) -+#define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22) -+#define GET_RX_GET_TX_QUEUE_EN (((REG32(ADR_CONTROL)) & 0x02000000 ) >> 25) -+#define GET_HCI_INQ_SEL (((REG32(ADR_CONTROL)) & 0x04000000 ) >> 26) -+#define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28) -+#define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_WAKE_MODE)) & 0x00000001 ) >> 0) -+#define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0) -+#define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16) -+#define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0) -+#define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THREASHOLD)) & 0xffff0000 ) >> 16) -+#define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0) -+#define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0) -+#define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0) -+#define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8) -+#define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16) -+#define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24) -+#define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0) -+#define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8) -+#define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0) -+#define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16) -+#define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0) -+#define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16) -+#define GET_TX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0xffffffff ) >> 0) -+#define GET_RX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0xffffffff ) >> 0) -+#define GET_HOST_CMD_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0x000000ff ) >> 0) -+#define GET_HOST_EVENT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0x000000ff ) >> 0) -+#define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0x000000ff ) >> 0) -+#define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0x000000ff ) >> 0) -+#define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0x000000ff ) >> 0) -+#define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0x000000ff ) >> 0) -+#define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0x000000ff ) >> 0) -+#define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0x000000ff ) >> 0) -+#define GET_HCI_STATE_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0) -+#define GET_HCI_ST_TIMEOUT_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0xffffffff ) >> 0) -+#define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0) -+#define GET_HCI_MONITOR_REG1 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0) -+#define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0) -+#define GET_HCI_TX_ALLOC_TIME_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0) -+#define GET_HCI_TX_ALLOC_TIME_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x0000ffff ) >> 0) -+#define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x00ff0000 ) >> 16) -+#define GET_HCI_TX_ALLOC_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0xffffffff ) >> 0) -+#define GET_HCI_TX_ALLOC_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x0000ffff ) >> 0) -+#define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ff0000 ) >> 16) -+#define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff000000 ) >> 24) -+#define GET_SDIO_TX_INVALID_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0xffffffff ) >> 0) -+#define GET_SDIO_TX_INVALID_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0x0000ffff ) >> 0) -+#define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0) -+#define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16) -+#define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0) -+#define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0) -+#define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1) -+#define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0) -+#define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0) -+#define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16) -+#define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0) -+#define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0) -+#define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0) -+#define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0) -+#define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0) -+#define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0) -+#define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0) -+#define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0) -+#define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16) -+#define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0) -+#define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16) -+#define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0) -+#define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0) -+#define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0) -+#define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2) -+#define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3) -+#define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4) -+#define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12) -+#define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16) -+#define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0) -+#define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0) -+#define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0) -+#define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0) -+#define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1) -+#define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0) -+#define GET_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16) -+#define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20) -+#define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28) -+#define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0) -+#define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16) -+#define GET_EFS_RDATA_0 (((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0xffffffff ) >> 0) -+#define GET_EFS_WDATA_0 (((REG32(ADR_EFUSE_WDATA_0)) & 0xffffffff ) >> 0) -+#define GET_EFS_RDATA_1 (((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0xffffffff ) >> 0) -+#define GET_EFS_WDATA_1 (((REG32(ADR_EFUSE_WDATA_1)) & 0xffffffff ) >> 0) -+#define GET_EFS_RDATA_2 (((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0xffffffff ) >> 0) -+#define GET_EFS_WDATA_2 (((REG32(ADR_EFUSE_WDATA_2)) & 0xffffffff ) >> 0) -+#define GET_EFS_RDATA_3 (((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0xffffffff ) >> 0) -+#define GET_EFS_WDATA_3 (((REG32(ADR_EFUSE_WDATA_3)) & 0xffffffff ) >> 0) -+#define GET_EFS_RDATA_4 (((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0xffffffff ) >> 0) -+#define GET_EFS_WDATA_4 (((REG32(ADR_EFUSE_WDATA_4)) & 0xffffffff ) >> 0) -+#define GET_EFS_RDATA_5 (((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0xffffffff ) >> 0) -+#define GET_EFS_WDATA_5 (((REG32(ADR_EFUSE_WDATA_5)) & 0xffffffff ) >> 0) -+#define GET_EFS_RDATA_6 (((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0xffffffff ) >> 0) -+#define GET_EFS_WDATA_6 (((REG32(ADR_EFUSE_WDATA_6)) & 0xffffffff ) >> 0) -+#define GET_EFS_RDATA_7 (((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0xffffffff ) >> 0) -+#define GET_EFS_WDATA_7 (((REG32(ADR_EFUSE_WDATA_7)) & 0xffffffff ) >> 0) -+#define GET_EFS_SPI_RD0_EN (((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0x00000001 ) >> 0) -+#define GET_EFS_SPI_RD1_EN (((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0x00000001 ) >> 0) -+#define GET_EFS_SPI_RD2_EN (((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0x00000001 ) >> 0) -+#define GET_EFS_SPI_RD3_EN (((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0x00000001 ) >> 0) -+#define GET_EFS_SPI_RD4_EN (((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0x00000001 ) >> 0) -+#define GET_EFS_SPI_RD5_EN (((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0x00000001 ) >> 0) -+#define GET_EFS_SPI_RD6_EN (((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0x00000001 ) >> 0) -+#define GET_EFS_SPI_RD7_EN (((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0x00000001 ) >> 0) -+#define GET_EFS_SPI_RBUSY (((REG32(ADR_EFUSE_SPI_BUSY)) & 0x00000001 ) >> 0) -+#define GET_EFS_SPI_RDATA_0 (((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0xffffffff ) >> 0) -+#define GET_EFS_SPI_RDATA_1 (((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0xffffffff ) >> 0) -+#define GET_EFS_SPI_RDATA_2 (((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0xffffffff ) >> 0) -+#define GET_EFS_SPI_RDATA_3 (((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0xffffffff ) >> 0) -+#define GET_EFS_SPI_RDATA_4 (((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0xffffffff ) >> 0) -+#define GET_EFS_SPI_RDATA_5 (((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0xffffffff ) >> 0) -+#define GET_EFS_SPI_RDATA_6 (((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0xffffffff ) >> 0) -+#define GET_EFS_SPI_RDATA_7 (((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0xffffffff ) >> 0) -+#define GET_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000001 ) >> 0) -+#define GET_FORCE_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000002 ) >> 1) -+#define GET_SMS4_DESCRY_EN (((REG32(ADR_SMS4_CFG1)) & 0x00000010 ) >> 4) -+#define GET_DEC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000001 ) >> 0) -+#define GET_DEC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000002 ) >> 1) -+#define GET_ENC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000004 ) >> 2) -+#define GET_ENC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000008 ) >> 3) -+#define GET_KEY_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000010 ) >> 4) -+#define GET_SMS4_CBC_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000001 ) >> 0) -+#define GET_SMS4_CFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000002 ) >> 1) -+#define GET_SMS4_OFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000004 ) >> 2) -+#define GET_SMS4_START_TRIG (((REG32(ADR_SMS4_TRIG)) & 0x00000001 ) >> 0) -+#define GET_SMS4_BUSY (((REG32(ADR_SMS4_STATUS1)) & 0x00000001 ) >> 0) -+#define GET_SMS4_DONE (((REG32(ADR_SMS4_STATUS2)) & 0x00000001 ) >> 0) -+#define GET_SMS4_DATAIN_0 (((REG32(ADR_SMS4_DATA_IN0)) & 0xffffffff ) >> 0) -+#define GET_SMS4_DATAIN_1 (((REG32(ADR_SMS4_DATA_IN1)) & 0xffffffff ) >> 0) -+#define GET_SMS4_DATAIN_2 (((REG32(ADR_SMS4_DATA_IN2)) & 0xffffffff ) >> 0) -+#define GET_SMS4_DATAIN_3 (((REG32(ADR_SMS4_DATA_IN3)) & 0xffffffff ) >> 0) -+#define GET_SMS4_DATAOUT_0 (((REG32(ADR_SMS4_DATA_OUT0)) & 0xffffffff ) >> 0) -+#define GET_SMS4_DATAOUT_1 (((REG32(ADR_SMS4_DATA_OUT1)) & 0xffffffff ) >> 0) -+#define GET_SMS4_DATAOUT_2 (((REG32(ADR_SMS4_DATA_OUT2)) & 0xffffffff ) >> 0) -+#define GET_SMS4_DATAOUT_3 (((REG32(ADR_SMS4_DATA_OUT3)) & 0xffffffff ) >> 0) -+#define GET_SMS4_KEY_0 (((REG32(ADR_SMS4_KEY_0)) & 0xffffffff ) >> 0) -+#define GET_SMS4_KEY_1 (((REG32(ADR_SMS4_KEY_1)) & 0xffffffff ) >> 0) -+#define GET_SMS4_KEY_2 (((REG32(ADR_SMS4_KEY_2)) & 0xffffffff ) >> 0) -+#define GET_SMS4_KEY_3 (((REG32(ADR_SMS4_KEY_3)) & 0xffffffff ) >> 0) -+#define GET_SMS4_MODE_IV0 (((REG32(ADR_SMS4_MODE_IV0)) & 0xffffffff ) >> 0) -+#define GET_SMS4_MODE_IV1 (((REG32(ADR_SMS4_MODE_IV1)) & 0xffffffff ) >> 0) -+#define GET_SMS4_MODE_IV2 (((REG32(ADR_SMS4_MODE_IV2)) & 0xffffffff ) >> 0) -+#define GET_SMS4_MODE_IV3 (((REG32(ADR_SMS4_MODE_IV3)) & 0xffffffff ) >> 0) -+#define GET_SMS4_OFB_ENC0 (((REG32(ADR_SMS4_OFB_ENC0)) & 0xffffffff ) >> 0) -+#define GET_SMS4_OFB_ENC1 (((REG32(ADR_SMS4_OFB_ENC1)) & 0xffffffff ) >> 0) -+#define GET_SMS4_OFB_ENC2 (((REG32(ADR_SMS4_OFB_ENC2)) & 0xffffffff ) >> 0) -+#define GET_SMS4_OFB_ENC3 (((REG32(ADR_SMS4_OFB_ENC3)) & 0xffffffff ) >> 0) -+#define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0) -+#define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0) -+#define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0) -+#define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0) -+#define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0) -+#define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0) -+#define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0) -+#define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0) -+#define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0) -+#define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0) -+#define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0) -+#define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0) -+#define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0) -+#define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0) -+#define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8) -+#define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0) -+#define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0) -+#define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0) -+#define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0) -+#define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0) -+#define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0) -+#define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0) -+#define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0) -+#define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0) -+#define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0) -+#define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0) -+#define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0) -+#define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0) -+#define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0) -+#define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0) -+#define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8) -+#define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31) -+#define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31) -+#define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31) -+#define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0) -+#define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2) -+#define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3) -+#define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0) -+#define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0) -+#define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0) -+#define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0) -+#define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0) -+#define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0) -+#define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0) -+#define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0) -+#define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1) -+#define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0) -+#define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x003f0000 ) >> 16) -+#define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0) -+#define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0) -+#define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0) -+#define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0) -+#define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0) -+#define GET_W0_T0_SEQ (((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W0_T1_SEQ (((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W0_T2_SEQ (((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W0_T3_SEQ (((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W0_T4_SEQ (((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W0_T5_SEQ (((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W0_T6_SEQ (((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W0_T7_SEQ (((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W1_T0_SEQ (((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W1_T1_SEQ (((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W1_T2_SEQ (((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W1_T3_SEQ (((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W1_T4_SEQ (((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W1_T5_SEQ (((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W1_T6_SEQ (((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_W1_T7_SEQ (((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0x0000ffff ) >> 0) -+#define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0) -+#define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2) -+#define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4) -+#define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6) -+#define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8) -+#define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10) -+#define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12) -+#define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0) -+#define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0) -+#define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0) -+#define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0) -+#define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0) -+#define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0) -+#define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16) -+#define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17) -+#define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18) -+#define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19) -+#define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20) -+#define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21) -+#define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22) -+#define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23) -+#define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24) -+#define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25) -+#define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16) -+#define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17) -+#define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18) -+#define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19) -+#define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20) -+#define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21) -+#define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22) -+#define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23) -+#define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24) -+#define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25) -+#define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0) -+#define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1) -+#define GET_MTX_AMPDU_CRC_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5) -+#define GET_MTX_FAST_RSP_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6) -+#define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7) -+#define GET_MTX_ACK_DUR0 (((REG32(ADR_MTX_MISC_EN)) & 0x00000100 ) >> 8) -+#define GET_MTX_TSF_AUTO_BCN (((REG32(ADR_MTX_MISC_EN)) & 0x00000400 ) >> 10) -+#define GET_MTX_TSF_AUTO_MISC (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11) -+#define GET_MTX_FORCE_CS_IDLE (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12) -+#define GET_MTX_FORCE_BKF_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13) -+#define GET_MTX_FORCE_DMA_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14) -+#define GET_MTX_FORCE_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15) -+#define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x003f0000 ) >> 16) -+#define GET_MTX_CTS_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00400000 ) >> 22) -+#define GET_MTX_AMPDU_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00800000 ) >> 23) -+#define GET_MTX_EDCCA_TOUT (((REG32(ADR_MTX_EDCCA_TOUT)) & 0x000003ff ) >> 0) -+#define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000002 ) >> 1) -+#define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000008 ) >> 3) -+#define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1) -+#define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3) -+#define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0) -+#define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1) -+#define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5) -+#define GET_MTX_HALT_MNG_UNTIL_DTIM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000040 ) >> 6) -+#define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x0000ff00 ) >> 8) -+#define GET_MTX_AUTO_FLUSH_Q4 (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16) -+#define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0) -+#define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1) -+#define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3) -+#define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16) -+#define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0) -+#define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_PRD)) & 0xff000000 ) >> 24) -+#define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0) -+#define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0) -+#define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x0000007f ) >> 0) -+#define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x03ff0000 ) >> 16) -+#define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x0000007f ) >> 0) -+#define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x03ff0000 ) >> 16) -+#define GET_MTX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000001 ) >> 0) -+#define GET_MRX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000002 ) >> 1) -+#define GET_MTX_DMA_FSM (((REG32(ADR_MTX_STATUS)) & 0x0000001c ) >> 2) -+#define GET_CH_ST_FSM (((REG32(ADR_MTX_STATUS)) & 0x000000e0 ) >> 5) -+#define GET_MTX_GNT_LOCK (((REG32(ADR_MTX_STATUS)) & 0x00000100 ) >> 8) -+#define GET_MTX_DMA_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000200 ) >> 9) -+#define GET_MTX_Q_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000400 ) >> 10) -+#define GET_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00000800 ) >> 11) -+#define GET_MRX_RX_EN (((REG32(ADR_MTX_STATUS)) & 0x00001000 ) >> 12) -+#define GET_DBG_PRTC_PRD (((REG32(ADR_MTX_STATUS)) & 0x00002000 ) >> 13) -+#define GET_DBG_DMA_RDY (((REG32(ADR_MTX_STATUS)) & 0x00004000 ) >> 14) -+#define GET_DBG_WAIT_RSP (((REG32(ADR_MTX_STATUS)) & 0x00008000 ) >> 15) -+#define GET_DBG_CFRM_BUSY (((REG32(ADR_MTX_STATUS)) & 0x00010000 ) >> 16) -+#define GET_DBG_RST (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000001 ) >> 0) -+#define GET_DBG_MODE (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000002 ) >> 1) -+#define GET_MB_REQ_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff ) >> 0) -+#define GET_RX_EN_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000 ) >> 16) -+#define GET_RX_CS_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff ) >> 0) -+#define GET_TX_CCA_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000 ) >> 16) -+#define GET_Q_REQ_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff ) >> 0) -+#define GET_CH_STA0_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000 ) >> 16) -+#define GET_MTX_DUR_RSP_TOUT_B (((REG32(ADR_MTX_DUR_TOUT)) & 0x000000ff ) >> 0) -+#define GET_MTX_DUR_RSP_TOUT_G (((REG32(ADR_MTX_DUR_TOUT)) & 0x0000ff00 ) >> 8) -+#define GET_MTX_DUR_RSP_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x000000ff ) >> 0) -+#define GET_MTX_DUR_BURST_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x0000ff00 ) >> 8) -+#define GET_MTX_DUR_SLOT (((REG32(ADR_MTX_DUR_IFS)) & 0x003f0000 ) >> 16) -+#define GET_MTX_DUR_RSP_EIFS (((REG32(ADR_MTX_DUR_IFS)) & 0xffc00000 ) >> 22) -+#define GET_MTX_DUR_RSP_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x000000ff ) >> 0) -+#define GET_MTX_DUR_BURST_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x0000ff00 ) >> 8) -+#define GET_MTX_DUR_SLOT_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003f0000 ) >> 16) -+#define GET_MTX_DUR_RSP_EIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc00000 ) >> 22) -+#define GET_CH_STA1_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff ) >> 0) -+#define GET_CH_STA2_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000 ) >> 16) -+#define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0) -+#define GET_MTX_MIB_CNT0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x3fffffff ) >> 0) -+#define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30) -+#define GET_MTX_MIB_CNT1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x3fffffff ) >> 0) -+#define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30) -+#define GET_CH_STA3_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff ) >> 0) -+#define GET_CH_STA4_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000 ) >> 16) -+#define GET_TXQ0_MTX_Q_PRE_LD (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1) -+#define GET_TXQ0_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2) -+#define GET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3) -+#define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) -+#define GET_TXQ0_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5) -+#define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6) -+#define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) -+#define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) -+#define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) -+#define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) -+#define GET_TXQ0_MTX_Q_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0) -+#define GET_TXQ0_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0) -+#define GET_TXQ0_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8) -+#define GET_TXQ0_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0) -+#define GET_TXQ0_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0) -+#define GET_TXQ0_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0) -+#define GET_TXQ1_MTX_Q_PRE_LD (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1) -+#define GET_TXQ1_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2) -+#define GET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3) -+#define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) -+#define GET_TXQ1_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5) -+#define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6) -+#define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) -+#define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) -+#define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) -+#define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) -+#define GET_TXQ1_MTX_Q_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0) -+#define GET_TXQ1_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0) -+#define GET_TXQ1_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8) -+#define GET_TXQ1_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0) -+#define GET_TXQ1_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0) -+#define GET_TXQ1_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0) -+#define GET_TXQ2_MTX_Q_PRE_LD (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1) -+#define GET_TXQ2_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2) -+#define GET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3) -+#define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) -+#define GET_TXQ2_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5) -+#define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6) -+#define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) -+#define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) -+#define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) -+#define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) -+#define GET_TXQ2_MTX_Q_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0) -+#define GET_TXQ2_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0) -+#define GET_TXQ2_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8) -+#define GET_TXQ2_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0) -+#define GET_TXQ2_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0) -+#define GET_TXQ2_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0) -+#define GET_TXQ3_MTX_Q_PRE_LD (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1) -+#define GET_TXQ3_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2) -+#define GET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3) -+#define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) -+#define GET_TXQ3_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5) -+#define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6) -+#define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) -+#define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) -+#define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) -+#define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) -+#define GET_TXQ3_MTX_Q_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0) -+#define GET_TXQ3_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0) -+#define GET_TXQ3_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8) -+#define GET_TXQ3_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0) -+#define GET_TXQ3_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0) -+#define GET_TXQ3_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0) -+#define GET_TXQ4_MTX_Q_PRE_LD (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1) -+#define GET_TXQ4_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2) -+#define GET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3) -+#define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) -+#define GET_TXQ4_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5) -+#define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6) -+#define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) -+#define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) -+#define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) -+#define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) -+#define GET_TXQ4_MTX_Q_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0) -+#define GET_TXQ4_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0) -+#define GET_TXQ4_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8) -+#define GET_TXQ4_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0) -+#define GET_TXQ4_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0) -+#define GET_TXQ4_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0) -+#define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0) -+#define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1) -+#define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2) -+#define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4) -+#define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0) -+#define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0) -+#define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0) -+#define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0) -+#define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1) -+#define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2) -+#define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4) -+#define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0) -+#define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0) -+#define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0) -+#define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0) -+#define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0) -+#define GET_INFO0 (((REG32(ADR_INFO0)) & 0xffffffff ) >> 0) -+#define GET_INFO1 (((REG32(ADR_INFO1)) & 0xffffffff ) >> 0) -+#define GET_INFO2 (((REG32(ADR_INFO2)) & 0xffffffff ) >> 0) -+#define GET_INFO3 (((REG32(ADR_INFO3)) & 0xffffffff ) >> 0) -+#define GET_INFO4 (((REG32(ADR_INFO4)) & 0xffffffff ) >> 0) -+#define GET_INFO5 (((REG32(ADR_INFO5)) & 0xffffffff ) >> 0) -+#define GET_INFO6 (((REG32(ADR_INFO6)) & 0xffffffff ) >> 0) -+#define GET_INFO7 (((REG32(ADR_INFO7)) & 0xffffffff ) >> 0) -+#define GET_INFO8 (((REG32(ADR_INFO8)) & 0xffffffff ) >> 0) -+#define GET_INFO9 (((REG32(ADR_INFO9)) & 0xffffffff ) >> 0) -+#define GET_INFO10 (((REG32(ADR_INFO10)) & 0xffffffff ) >> 0) -+#define GET_INFO11 (((REG32(ADR_INFO11)) & 0xffffffff ) >> 0) -+#define GET_INFO12 (((REG32(ADR_INFO12)) & 0xffffffff ) >> 0) -+#define GET_INFO13 (((REG32(ADR_INFO13)) & 0xffffffff ) >> 0) -+#define GET_INFO14 (((REG32(ADR_INFO14)) & 0xffffffff ) >> 0) -+#define GET_INFO15 (((REG32(ADR_INFO15)) & 0xffffffff ) >> 0) -+#define GET_INFO16 (((REG32(ADR_INFO16)) & 0xffffffff ) >> 0) -+#define GET_INFO17 (((REG32(ADR_INFO17)) & 0xffffffff ) >> 0) -+#define GET_INFO18 (((REG32(ADR_INFO18)) & 0xffffffff ) >> 0) -+#define GET_INFO19 (((REG32(ADR_INFO19)) & 0xffffffff ) >> 0) -+#define GET_INFO20 (((REG32(ADR_INFO20)) & 0xffffffff ) >> 0) -+#define GET_INFO21 (((REG32(ADR_INFO21)) & 0xffffffff ) >> 0) -+#define GET_INFO22 (((REG32(ADR_INFO22)) & 0xffffffff ) >> 0) -+#define GET_INFO23 (((REG32(ADR_INFO23)) & 0xffffffff ) >> 0) -+#define GET_INFO24 (((REG32(ADR_INFO24)) & 0xffffffff ) >> 0) -+#define GET_INFO25 (((REG32(ADR_INFO25)) & 0xffffffff ) >> 0) -+#define GET_INFO26 (((REG32(ADR_INFO26)) & 0xffffffff ) >> 0) -+#define GET_INFO27 (((REG32(ADR_INFO27)) & 0xffffffff ) >> 0) -+#define GET_INFO28 (((REG32(ADR_INFO28)) & 0xffffffff ) >> 0) -+#define GET_INFO29 (((REG32(ADR_INFO29)) & 0xffffffff ) >> 0) -+#define GET_INFO30 (((REG32(ADR_INFO30)) & 0xffffffff ) >> 0) -+#define GET_INFO31 (((REG32(ADR_INFO31)) & 0xffffffff ) >> 0) -+#define GET_INFO32 (((REG32(ADR_INFO32)) & 0xffffffff ) >> 0) -+#define GET_INFO33 (((REG32(ADR_INFO33)) & 0xffffffff ) >> 0) -+#define GET_INFO34 (((REG32(ADR_INFO34)) & 0xffffffff ) >> 0) -+#define GET_INFO35 (((REG32(ADR_INFO35)) & 0xffffffff ) >> 0) -+#define GET_INFO36 (((REG32(ADR_INFO36)) & 0xffffffff ) >> 0) -+#define GET_INFO37 (((REG32(ADR_INFO37)) & 0xffffffff ) >> 0) -+#define GET_INFO38 (((REG32(ADR_INFO38)) & 0xffffffff ) >> 0) -+#define GET_INFO_MASK (((REG32(ADR_INFO_MASK)) & 0xffffffff ) >> 0) -+#define GET_INFO_DEF_RATE (((REG32(ADR_INFO_RATE_OFFSET)) & 0x0000003f ) >> 0) -+#define GET_INFO_MRX_OFFSET (((REG32(ADR_INFO_RATE_OFFSET)) & 0x000f0000 ) >> 16) -+#define GET_BCAST_RATEUNKNOW (((REG32(ADR_INFO_RATE_OFFSET)) & 0x3f000000 ) >> 24) -+#define GET_INFO_IDX_TBL_ADDR (((REG32(ADR_INFO_IDX_ADDR)) & 0xffffffff ) >> 0) -+#define GET_INFO_LEN_TBL_ADDR (((REG32(ADR_INFO_LEN_ADDR)) & 0xffffffff ) >> 0) -+#define GET_IC_TAG_31_0 (((REG32(ADR_IC_TIME_TAG_0)) & 0xffffffff ) >> 0) -+#define GET_IC_TAG_63_32 (((REG32(ADR_IC_TIME_TAG_1)) & 0xffffffff ) >> 0) -+#define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0) -+#define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8) -+#define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16) -+#define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0) -+#define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1) -+#define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2) -+#define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3) -+#define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4) -+#define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5) -+#define GET_ASIC_TAG (((REG32(ADR_MAC_MODE)) & 0xff000000 ) >> 24) -+#define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0) -+#define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1) -+#define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3) -+#define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4) -+#define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5) -+#define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6) -+#define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7) -+#define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8) -+#define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9) -+#define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11) -+#define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12) -+#define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13) -+#define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14) -+#define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1) -+#define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3) -+#define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4) -+#define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5) -+#define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6) -+#define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7) -+#define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8) -+#define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14) -+#define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15) -+#define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16) -+#define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17) -+#define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1) -+#define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3) -+#define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4) -+#define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5) -+#define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6) -+#define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7) -+#define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8) -+#define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9) -+#define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10) -+#define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11) -+#define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13) -+#define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14) -+#define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15) -+#define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0) -+#define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1) -+#define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3) -+#define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4) -+#define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5) -+#define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6) -+#define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7) -+#define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9) -+#define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10) -+#define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11) -+#define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12) -+#define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13) -+#define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0) -+#define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1) -+#define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3) -+#define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4) -+#define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5) -+#define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6) -+#define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12) -+#define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13) -+#define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14) -+#define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15) -+#define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1) -+#define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10) -+#define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11) -+#define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13) -+#define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14) -+#define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15) -+#define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0) -+#define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2) -+#define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4) -+#define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8) -+#define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16) -+#define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17) -+#define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18) -+#define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21) -+#define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0) -+#define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0) -+#define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0) -+#define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0) -+#define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0) -+#define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0) -+#define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0) -+#define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0) -+#define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3) -+#define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6) -+#define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16) -+#define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0) -+#define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1) -+#define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4) -+#define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5) -+#define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8) -+#define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9) -+#define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10) -+#define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11) -+#define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12) -+#define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16) -+#define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17) -+#define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18) -+#define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19) -+#define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0) -+#define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8) -+#define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16) -+#define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24) -+#define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0) -+#define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1) -+#define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2) -+#define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3) -+#define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4) -+#define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5) -+#define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8) -+#define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9) -+#define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2) -+#define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3) -+#define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4) -+#define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5) -+#define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6) -+#define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7) -+#define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8) -+#define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9) -+#define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10) -+#define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11) -+#define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12) -+#define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13) -+#define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14) -+#define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15) -+#define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16) -+#define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17) -+#define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0) -+#define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0) -+#define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0) -+#define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0) -+#define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0) -+#define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0) -+#define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0) -+#define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0) -+#define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0) -+#define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0) -+#define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0) -+#define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0) -+#define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0) -+#define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0) -+#define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0) -+#define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0) -+#define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0) -+#define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0) -+#define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0) -+#define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0) -+#define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0) -+#define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0) -+#define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0) -+#define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0) -+#define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0) -+#define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0) -+#define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0) -+#define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0) -+#define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0) -+#define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0) -+#define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0) -+#define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0) -+#define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0) -+#define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0) -+#define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0) -+#define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0) -+#define GET_CBR_RG_EN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_TX_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1) -+#define GET_CBR_RG_TX_PA_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2) -+#define GET_CBR_RG_TX_DAC_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3) -+#define GET_CBR_RG_RX_AGC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4) -+#define GET_CBR_RG_RX_GAIN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5) -+#define GET_CBR_RG_RFG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6) -+#define GET_CBR_RG_PGAG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8) -+#define GET_CBR_RG_MODE (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12) -+#define GET_CBR_RG_EN_TX_TRSW (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14) -+#define GET_CBR_RG_EN_SX (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15) -+#define GET_CBR_RG_EN_RX_LNA (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16) -+#define GET_CBR_RG_EN_RX_MIXER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17) -+#define GET_CBR_RG_EN_RX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18) -+#define GET_CBR_RG_EN_RX_LOBUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19) -+#define GET_CBR_RG_EN_RX_TZ (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20) -+#define GET_CBR_RG_EN_RX_FILTER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21) -+#define GET_CBR_RG_EN_RX_HPF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22) -+#define GET_CBR_RG_EN_RX_RSSI (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23) -+#define GET_CBR_RG_EN_ADC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24) -+#define GET_CBR_RG_EN_TX_MOD (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25) -+#define GET_CBR_RG_EN_TX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26) -+#define GET_CBR_RG_EN_TX_DIV2_BUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27) -+#define GET_CBR_RG_EN_TX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28) -+#define GET_CBR_RG_EN_RX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29) -+#define GET_CBR_RG_SEL_DPLL_CLK (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30) -+#define GET_CBR_RG_EN_TX_DPD (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_EN_TX_TSSI (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1) -+#define GET_CBR_RG_EN_RX_IQCAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2) -+#define GET_CBR_RG_EN_TX_DAC_CAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3) -+#define GET_CBR_RG_EN_TX_SELF_MIXER (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4) -+#define GET_CBR_RG_EN_TX_DAC_OUT (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5) -+#define GET_CBR_RG_EN_LDO_RX_FE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6) -+#define GET_CBR_RG_EN_LDO_ABB (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7) -+#define GET_CBR_RG_EN_LDO_AFE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8) -+#define GET_CBR_RG_EN_SX_CHPLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9) -+#define GET_CBR_RG_EN_SX_LOBFLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10) -+#define GET_CBR_RG_EN_IREF_RX (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11) -+#define GET_CBR_RG_DCDC_MODE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12) -+#define GET_CBR_RG_LDO_LEVEL_RX_FE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000007 ) >> 0) -+#define GET_CBR_RG_LDO_LEVEL_ABB (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000038 ) >> 3) -+#define GET_CBR_RG_LDO_LEVEL_AFE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x000001c0 ) >> 6) -+#define GET_CBR_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000e00 ) >> 9) -+#define GET_CBR_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00007000 ) >> 12) -+#define GET_CBR_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00038000 ) >> 15) -+#define GET_CBR_RG_DP_LDO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x001c0000 ) >> 18) -+#define GET_CBR_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00e00000 ) >> 21) -+#define GET_CBR_RG_TX_LDO_TX_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x07000000 ) >> 24) -+#define GET_CBR_RG_BUCK_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x38000000 ) >> 27) -+#define GET_CBR_RG_EN_RX_PADSW (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_EN_RX_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000002 ) >> 1) -+#define GET_CBR_RG_RX_ABBCFIX (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000004 ) >> 2) -+#define GET_CBR_RG_RX_ABBCTUNE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3) -+#define GET_CBR_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000200 ) >> 9) -+#define GET_CBR_RG_RX_ABB_N_MODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000400 ) >> 10) -+#define GET_CBR_RG_RX_EN_LOOPA (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000800 ) >> 11) -+#define GET_CBR_RG_RX_FILTERI1ST (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00003000 ) >> 12) -+#define GET_CBR_RG_RX_FILTERI2ND (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14) -+#define GET_CBR_RG_RX_FILTERI3RD (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00030000 ) >> 16) -+#define GET_CBR_RG_RX_FILTERI_COURSE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18) -+#define GET_CBR_RG_RX_FILTERVCM (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00300000 ) >> 20) -+#define GET_CBR_RG_RX_HPF3M (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00400000 ) >> 22) -+#define GET_CBR_RG_RX_HPF300K (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00800000 ) >> 23) -+#define GET_CBR_RG_RX_HPFI (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x03000000 ) >> 24) -+#define GET_CBR_RG_RX_HPF_FINALCORNER (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26) -+#define GET_CBR_RG_RX_HPF_SETTLE1_C (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x30000000 ) >> 28) -+#define GET_CBR_RG_RX_HPF_SETTLE1_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000003 ) >> 0) -+#define GET_CBR_RG_RX_HPF_SETTLE2_C (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x0000000c ) >> 2) -+#define GET_CBR_RG_RX_HPF_SETTLE2_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000030 ) >> 4) -+#define GET_CBR_RG_RX_HPF_VCMCON2 (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6) -+#define GET_CBR_RG_RX_HPF_VCMCON (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000300 ) >> 8) -+#define GET_CBR_RG_RX_OUTVCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10) -+#define GET_CBR_RG_RX_TZI (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00003000 ) >> 12) -+#define GET_CBR_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00004000 ) >> 14) -+#define GET_CBR_RG_RX_TZ_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00018000 ) >> 15) -+#define GET_CBR_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17) -+#define GET_CBR_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00100000 ) >> 20) -+#define GET_CBR_RG_RX_ADCRSSI_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00600000 ) >> 21) -+#define GET_CBR_RG_RX_REC_LPFCORNER (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x01800000 ) >> 23) -+#define GET_CBR_RG_RSSI_CLOCK_GATING (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x02000000 ) >> 25) -+#define GET_CBR_RG_TXPGA_CAPSW (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00000003 ) >> 0) -+#define GET_CBR_RG_TXPGA_MAIN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x000000fc ) >> 2) -+#define GET_CBR_RG_TXPGA_STEER (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8) -+#define GET_CBR_RG_TXMOD_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14) -+#define GET_CBR_RG_TXLPF_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00030000 ) >> 16) -+#define GET_CBR_RG_PACELL_EN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18) -+#define GET_CBR_RG_PABIAS_CTRL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21) -+#define GET_CBR_RG_PABIAS_AB (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x02000000 ) >> 25) -+#define GET_CBR_RG_TX_DIV_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26) -+#define GET_CBR_RG_TX_LOBUF_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x30000000 ) >> 28) -+#define GET_CBR_RG_RX_SQDC (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0) -+#define GET_CBR_RG_RX_DIV2_CORE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3) -+#define GET_CBR_RG_RX_LOBUF (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5) -+#define GET_CBR_RG_TX_DPDGM_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7) -+#define GET_CBR_RG_TX_DPD_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11) -+#define GET_CBR_RG_TX_TSSI_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15) -+#define GET_CBR_RG_TX_TSSI_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18) -+#define GET_CBR_RG_TX_TSSI_TESTMODE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21) -+#define GET_CBR_RG_TX_TSSI_TEST (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22) -+#define GET_CBR_RG_RX_HG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0) -+#define GET_CBR_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2) -+#define GET_CBR_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6) -+#define GET_CBR_RG_RX_HG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10) -+#define GET_CBR_RG_RX_HG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14) -+#define GET_CBR_RG_RX_HG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16) -+#define GET_CBR_RG_RX_MG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0) -+#define GET_CBR_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2) -+#define GET_CBR_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6) -+#define GET_CBR_RG_RX_MG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10) -+#define GET_CBR_RG_RX_MG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14) -+#define GET_CBR_RG_RX_MG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16) -+#define GET_CBR_RG_RX_LG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0) -+#define GET_CBR_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2) -+#define GET_CBR_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6) -+#define GET_CBR_RG_RX_LG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10) -+#define GET_CBR_RG_RX_LG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14) -+#define GET_CBR_RG_RX_LG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16) -+#define GET_CBR_RG_RX_ULG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0) -+#define GET_CBR_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2) -+#define GET_CBR_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6) -+#define GET_CBR_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10) -+#define GET_CBR_RG_RX_ULG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14) -+#define GET_CBR_RG_RX_ULG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16) -+#define GET_CBR_RG_HPF1_FAST_SET_X (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_HPF1_FAST_SET_Y (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000002 ) >> 1) -+#define GET_CBR_RG_HPF1_FAST_SET_Z (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000004 ) >> 2) -+#define GET_CBR_RG_HPF_T1A (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000018 ) >> 3) -+#define GET_CBR_RG_HPF_T1B (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000060 ) >> 5) -+#define GET_CBR_RG_HPF_T1C (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000180 ) >> 7) -+#define GET_CBR_RG_RX_LNA_TRI_SEL (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000600 ) >> 9) -+#define GET_CBR_RG_RX_LNA_SETTLE (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00001800 ) >> 11) -+#define GET_CBR_RG_ADC_CLKSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_ADC_DIBIAS (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1) -+#define GET_CBR_RG_ADC_DIVR (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3) -+#define GET_CBR_RG_ADC_DVCMI (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4) -+#define GET_CBR_RG_ADC_SAMSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6) -+#define GET_CBR_RG_ADC_STNBY (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10) -+#define GET_CBR_RG_ADC_TESTMODE (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11) -+#define GET_CBR_RG_ADC_TSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12) -+#define GET_CBR_RG_ADC_VRSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16) -+#define GET_CBR_RG_DICMP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18) -+#define GET_CBR_RG_DIOP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20) -+#define GET_CBR_RG_DACI1ST (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0) -+#define GET_CBR_RG_TX_DACLPF_ICOURSE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2) -+#define GET_CBR_RG_TX_DACLPF_IFINE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4) -+#define GET_CBR_RG_TX_DACLPF_VCM (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6) -+#define GET_CBR_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8) -+#define GET_CBR_RG_TX_DAC_IBIAS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9) -+#define GET_CBR_RG_TX_DAC_OS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11) -+#define GET_CBR_RG_TX_DAC_RCAL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14) -+#define GET_CBR_RG_TX_DAC_TSEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16) -+#define GET_CBR_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20) -+#define GET_CBR_RG_TXLPF_BYPASS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21) -+#define GET_CBR_RG_TXLPF_BOOSTI (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22) -+#define GET_CBR_RG_EN_SX_R3 (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_EN_SX_CH (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000002 ) >> 1) -+#define GET_CBR_RG_EN_SX_CHP (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000004 ) >> 2) -+#define GET_CBR_RG_EN_SX_DIVCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000008 ) >> 3) -+#define GET_CBR_RG_EN_SX_VCOBF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000010 ) >> 4) -+#define GET_CBR_RG_EN_SX_VCO (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000020 ) >> 5) -+#define GET_CBR_RG_EN_SX_MOD (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000040 ) >> 6) -+#define GET_CBR_RG_EN_SX_LCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000080 ) >> 7) -+#define GET_CBR_RG_EN_SX_DITHER (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000100 ) >> 8) -+#define GET_CBR_RG_EN_SX_DELCAL (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000200 ) >> 9) -+#define GET_CBR_RG_EN_SX_PC_BYPASS (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000400 ) >> 10) -+#define GET_CBR_RG_EN_SX_VT_MON (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000800 ) >> 11) -+#define GET_CBR_RG_EN_SX_VT_MON_DG (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00001000 ) >> 12) -+#define GET_CBR_RG_EN_SX_DIV (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00002000 ) >> 13) -+#define GET_CBR_RG_EN_SX_LPF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00004000 ) >> 14) -+#define GET_CBR_RG_SX_RFCTRL_F (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x00ffffff ) >> 0) -+#define GET_CBR_RG_SX_SEL_CP (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0f000000 ) >> 24) -+#define GET_CBR_RG_SX_SEL_CS (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0000000 ) >> 28) -+#define GET_CBR_RG_SX_RFCTRL_CH (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000007ff ) >> 0) -+#define GET_CBR_RG_SX_SEL_C3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x00007800 ) >> 11) -+#define GET_CBR_RG_SX_SEL_RS (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000f8000 ) >> 15) -+#define GET_CBR_RG_SX_SEL_R3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x01f00000 ) >> 20) -+#define GET_CBR_RG_SX_SEL_ICHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0000001f ) >> 0) -+#define GET_CBR_RG_SX_SEL_PCHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5) -+#define GET_CBR_RG_SX_SEL_CHP_REGOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10) -+#define GET_CBR_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14) -+#define GET_CBR_RG_SX_CHP_IOST_POL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00040000 ) >> 18) -+#define GET_CBR_RG_SX_CHP_IOST (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00380000 ) >> 19) -+#define GET_CBR_RG_SX_PFDSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00400000 ) >> 22) -+#define GET_CBR_RG_SX_PFD_SET (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00800000 ) >> 23) -+#define GET_CBR_RG_SX_PFD_SET1 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x01000000 ) >> 24) -+#define GET_CBR_RG_SX_PFD_SET2 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x02000000 ) >> 25) -+#define GET_CBR_RG_SX_VBNCAS_SEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x04000000 ) >> 26) -+#define GET_CBR_RG_SX_PFD_RST_H (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x08000000 ) >> 27) -+#define GET_CBR_RG_SX_PFD_TRUP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x10000000 ) >> 28) -+#define GET_CBR_RG_SX_PFD_TRDN (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x20000000 ) >> 29) -+#define GET_CBR_RG_SX_PFD_TRSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x40000000 ) >> 30) -+#define GET_CBR_RG_SX_VCOBA_R (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0) -+#define GET_CBR_RG_SX_VCORSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3) -+#define GET_CBR_RG_SX_VCOCUSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8) -+#define GET_CBR_RG_SX_RXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12) -+#define GET_CBR_RG_SX_TXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16) -+#define GET_CBR_RG_SX_VCOBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20) -+#define GET_CBR_RG_SX_DIVBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24) -+#define GET_CBR_RG_SX_GNDR_SEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28) -+#define GET_CBR_RG_SX_DITHER_WEIGHT (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0) -+#define GET_CBR_RG_SX_MOD_ERRCMP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0000000c ) >> 2) -+#define GET_CBR_RG_SX_MOD_ORDER (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4) -+#define GET_CBR_RG_SX_SDM_D1 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000040 ) >> 6) -+#define GET_CBR_RG_SX_SDM_D2 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000080 ) >> 7) -+#define GET_CBR_RG_SDM_PASS (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000100 ) >> 8) -+#define GET_CBR_RG_SX_RST_H_DIV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9) -+#define GET_CBR_RG_SX_SDM_EDGE (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10) -+#define GET_CBR_RG_SX_XO_GM (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11) -+#define GET_CBR_RG_SX_REFBYTWO (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13) -+#define GET_CBR_RG_SX_XO_SWCAP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0003c000 ) >> 14) -+#define GET_CBR_RG_SX_SDMLUT_INV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00040000 ) >> 18) -+#define GET_CBR_RG_SX_LCKEN (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19) -+#define GET_CBR_RG_SX_PREVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20) -+#define GET_CBR_RG_SX_PSCONTERVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24) -+#define GET_CBR_RG_SX_MOD_ERR_DELAY (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x30000000 ) >> 28) -+#define GET_CBR_RG_SX_MODDB (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x40000000 ) >> 30) -+#define GET_CBR_RG_SX_CV_CURVE_SEL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000003 ) >> 0) -+#define GET_CBR_RG_SX_SEL_DELAY (((REG32(ADR_CBR_SYN_LCK1)) & 0x0000007c ) >> 2) -+#define GET_CBR_RG_SX_REF_CYCLE (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000780 ) >> 7) -+#define GET_CBR_RG_SX_VCOBY16 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000800 ) >> 11) -+#define GET_CBR_RG_SX_VCOBY32 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00001000 ) >> 12) -+#define GET_CBR_RG_SX_PH (((REG32(ADR_CBR_SYN_LCK1)) & 0x00002000 ) >> 13) -+#define GET_CBR_RG_SX_PL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00004000 ) >> 14) -+#define GET_CBR_RG_SX_VT_MON_MODE (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_SX_VT_TH_HI (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000006 ) >> 1) -+#define GET_CBR_RG_SX_VT_TH_LO (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000018 ) >> 3) -+#define GET_CBR_RG_SX_VT_SET (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000020 ) >> 5) -+#define GET_CBR_RG_SX_VT_MON_TMR (((REG32(ADR_CBR_SYN_LCK2)) & 0x00007fc0 ) >> 6) -+#define GET_CBR_RG_IDEAL_CYCLE (((REG32(ADR_CBR_SYN_LCK2)) & 0x0fff8000 ) >> 15) -+#define GET_CBR_RG_EN_DP_VT_MON (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_DP_VT_TH_HI (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1) -+#define GET_CBR_RG_DP_VT_TH_LO (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3) -+#define GET_CBR_RG_DP_VT_MON_TMR (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00003fe0 ) >> 5) -+#define GET_CBR_RG_DP_CK320BY2 (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14) -+#define GET_CBR_RG_SX_DELCTRL (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x001f8000 ) >> 15) -+#define GET_CBR_RG_DP_OD_TEST (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21) -+#define GET_CBR_RG_DP_BBPLL_BP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_DP_BBPLL_ICP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1) -+#define GET_CBR_RG_DP_BBPLL_IDUAL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3) -+#define GET_CBR_RG_DP_BBPLL_OD_TEST (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5) -+#define GET_CBR_RG_DP_BBPLL_PD (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9) -+#define GET_CBR_RG_DP_BBPLL_TESTSEL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10) -+#define GET_CBR_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13) -+#define GET_CBR_RG_DP_RP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15) -+#define GET_CBR_RG_DP_RHP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18) -+#define GET_CBR_RG_DP_DR3 (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00700000 ) >> 20) -+#define GET_CBR_RG_DP_DCP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x07800000 ) >> 23) -+#define GET_CBR_RG_DP_DCS (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x78000000 ) >> 27) -+#define GET_CBR_RG_DP_FBDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x00000fff ) >> 0) -+#define GET_CBR_RG_DP_FODIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003ff000 ) >> 12) -+#define GET_CBR_RG_DP_REFDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00000 ) >> 22) -+#define GET_CBR_RG_IDACAI_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0) -+#define GET_CBR_RG_IDACAQ_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6) -+#define GET_CBR_RG_IDACAI_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12) -+#define GET_CBR_RG_IDACAQ_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18) -+#define GET_CBR_RG_IDACAI_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0) -+#define GET_CBR_RG_IDACAQ_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6) -+#define GET_CBR_RG_IDACAI_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12) -+#define GET_CBR_RG_IDACAQ_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18) -+#define GET_CBR_RG_IDACAI_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0) -+#define GET_CBR_RG_IDACAQ_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6) -+#define GET_CBR_RG_IDACAI_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12) -+#define GET_CBR_RG_IDACAQ_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18) -+#define GET_CBR_RG_IDACAI_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0) -+#define GET_CBR_RG_IDACAQ_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6) -+#define GET_CBR_RG_IDACAI_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12) -+#define GET_CBR_RG_IDACAQ_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18) -+#define GET_CBR_RG_IDACAI_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0) -+#define GET_CBR_RG_IDACAQ_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6) -+#define GET_CBR_RG_IDACAI_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12) -+#define GET_CBR_RG_IDACAQ_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18) -+#define GET_CBR_RG_IDACAI_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0) -+#define GET_CBR_RG_IDACAQ_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6) -+#define GET_CBR_RG_IDACAI_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12) -+#define GET_CBR_RG_IDACAQ_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18) -+#define GET_CBR_RG_IDACAI_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0) -+#define GET_CBR_RG_IDACAQ_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6) -+#define GET_CBR_RG_IDACAI_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12) -+#define GET_CBR_RG_IDACAQ_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18) -+#define GET_CBR_RG_IDACAI_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0) -+#define GET_CBR_RG_IDACAQ_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6) -+#define GET_CBR_RG_IDACAI_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12) -+#define GET_CBR_RG_IDACAQ_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18) -+#define GET_CBR_RG_EN_RCAL (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_RCAL_SPD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000002 ) >> 1) -+#define GET_CBR_RG_RCAL_TMR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x000001fc ) >> 2) -+#define GET_CBR_RG_RCAL_CODE_CWR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000200 ) >> 9) -+#define GET_CBR_RG_RCAL_CODE_CWD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00007c00 ) >> 10) -+#define GET_CBR_RG_SX_SUB_SEL_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_SX_SUB_SEL_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x000000fe ) >> 1) -+#define GET_CBR_RG_DP_BBPLL_BS_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000100 ) >> 8) -+#define GET_CBR_RG_DP_BBPLL_BS_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00007e00 ) >> 9) -+#define GET_CBR_RCAL_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0) -+#define GET_CBR_DA_LCK_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1) -+#define GET_CBR_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2) -+#define GET_CBR_DP_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000008 ) >> 3) -+#define GET_CBR_CH_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000010 ) >> 4) -+#define GET_CBR_DA_R_CODE_LUT (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6) -+#define GET_CBR_AD_SX_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11) -+#define GET_CBR_AD_DP_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13) -+#define GET_CBR_DA_R_CAL_CODE (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0) -+#define GET_CBR_DA_SX_SUB_SEL (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5) -+#define GET_CBR_DA_DP_BBPLL_BS (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0003f000 ) >> 12) -+#define GET_CBR_TX_EN (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000001 ) >> 0) -+#define GET_CBR_TX_CNT_RST (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000002 ) >> 1) -+#define GET_CBR_IFS_TIME (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000000fc ) >> 2) -+#define GET_CBR_LENGTH_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000fff00 ) >> 8) -+#define GET_CBR_TX_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xff000000 ) >> 24) -+#define GET_CBR_TC_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0x00ffffff ) >> 0) -+#define GET_CBR_PLCP_PSDU_DATA_MEM (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x000000ff ) >> 0) -+#define GET_CBR_PLCP_PSDU_PREAMBLE_SHORT (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00000100 ) >> 8) -+#define GET_CBR_PLCP_BYTE_LENGTH (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x001ffe00 ) >> 9) -+#define GET_CBR_PLCP_PSDU_RATE (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00600000 ) >> 21) -+#define GET_CBR_TAIL_TIME (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x1f800000 ) >> 23) -+#define GET_CBR_RG_O_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000001 ) >> 0) -+#define GET_CBR_RG_I_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000002 ) >> 1) -+#define GET_CBR_SEL_ADCKP_INV (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000004 ) >> 2) -+#define GET_CBR_RG_PAD_DS (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000008 ) >> 3) -+#define GET_CBR_SEL_ADCKP_MUX (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000010 ) >> 4) -+#define GET_CBR_RG_PAD_DS_CLK (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000020 ) >> 5) -+#define GET_CBR_INTP_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000200 ) >> 9) -+#define GET_CBR_IQ_SWP (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000400 ) >> 10) -+#define GET_CBR_RG_EN_EXT_DA (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000800 ) >> 11) -+#define GET_CBR_RG_DIS_DA_OFFSET (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00001000 ) >> 12) -+#define GET_CBR_DBG_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x000f0000 ) >> 16) -+#define GET_CBR_DBG_EN (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00100000 ) >> 20) -+#define GET_CBR_RG_PKT_GEN_TX_CNT (((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0xffffffff ) >> 0) -+#define GET_CBR_TP_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x0000001f ) >> 0) -+#define GET_CBR_IDEAL_IQ_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000020 ) >> 5) -+#define GET_CBR_DATA_OUT_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x000001c0 ) >> 6) -+#define GET_CBR_TWO_TONE_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000200 ) >> 9) -+#define GET_CBR_FREQ_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ff0000 ) >> 16) -+#define GET_CBR_IQ_SCALE (((REG32(ADR_CBR_PATTERN_GEN)) & 0xff000000 ) >> 24) -+#define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0) -+#define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2) -+#define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0) -+#define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0) -+#define GET_HW_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x000007ff ) >> 0) -+#define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0) -+#define GET_PRI_HW_PKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x000007ff ) >> 0) -+#define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0) -+#define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1) -+#define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9) -+#define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10) -+#define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11) -+#define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16) -+#define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24) -+#define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0) -+#define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5) -+#define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11) -+#define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17) -+#define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20) -+#define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23) -+#define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26) -+#define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29) -+#define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0) -+#define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3) -+#define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6) -+#define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000600 ) >> 9) -+#define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00001800 ) >> 11) -+#define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00006000 ) >> 13) -+#define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000f8000 ) >> 15) -+#define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00700000 ) >> 20) -+#define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1) -+#define GET_CH2_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2) -+#define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3) -+#define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4) -+#define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5) -+#define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6) -+#define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7) -+#define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8) -+#define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9) -+#define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10) -+#define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11) -+#define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12) -+#define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13) -+#define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14) -+#define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15) -+#define GET_HALT_CH0 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000001 ) >> 0) -+#define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1) -+#define GET_HALT_CH2 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000004 ) >> 2) -+#define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3) -+#define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4) -+#define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5) -+#define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6) -+#define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7) -+#define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8) -+#define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9) -+#define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10) -+#define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11) -+#define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12) -+#define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13) -+#define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14) -+#define GET_HALT_CH15 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00008000 ) >> 15) -+#define GET_STOP_MBOX (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16) -+#define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20) -+#define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21) -+#define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_CFG)) & 0xff000000 ) >> 24) -+#define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0) -+#define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16) -+#define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18) -+#define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19) -+#define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24) -+#define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31) -+#define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0) -+#define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16) -+#define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0) -+#define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0) -+#define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1) -+#define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2) -+#define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3) -+#define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4) -+#define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5) -+#define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6) -+#define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7) -+#define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8) -+#define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9) -+#define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10) -+#define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11) -+#define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12) -+#define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13) -+#define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14) -+#define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15) -+#define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16) -+#define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17) -+#define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18) -+#define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19) -+#define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20) -+#define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21) -+#define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22) -+#define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23) -+#define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24) -+#define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25) -+#define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26) -+#define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27) -+#define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28) -+#define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29) -+#define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30) -+#define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31) -+#define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1) -+#define GET_CH0_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000001 ) >> 0) -+#define GET_CH1_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000002 ) >> 1) -+#define GET_CH2_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000004 ) >> 2) -+#define GET_CH3_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000008 ) >> 3) -+#define GET_CH4_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000010 ) >> 4) -+#define GET_CH5_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000020 ) >> 5) -+#define GET_CH6_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000040 ) >> 6) -+#define GET_CH7_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000080 ) >> 7) -+#define GET_CH8_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000100 ) >> 8) -+#define GET_CH9_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000200 ) >> 9) -+#define GET_CH10_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000400 ) >> 10) -+#define GET_CH11_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000800 ) >> 11) -+#define GET_CH12_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00001000 ) >> 12) -+#define GET_CH13_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00002000 ) >> 13) -+#define GET_CH14_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00004000 ) >> 14) -+#define GET_CH15_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00008000 ) >> 15) -+#define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0) -+#define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5) -+#define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00000c00 ) >> 10) -+#define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15) -+#define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20) -+#define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25) -+#define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0) -+#define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5) -+#define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10) -+#define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15) -+#define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20) -+#define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25) -+#define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0) -+#define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5) -+#define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000c00 ) >> 10) -+#define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x001f8000 ) >> 15) -+#define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0) -+#define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1) -+#define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2) -+#define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3) -+#define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4) -+#define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5) -+#define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6) -+#define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7) -+#define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8) -+#define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9) -+#define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10) -+#define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11) -+#define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12) -+#define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13) -+#define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14) -+#define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15) -+#define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0) -+#define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1) -+#define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2) -+#define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3) -+#define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4) -+#define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5) -+#define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6) -+#define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7) -+#define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8) -+#define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9) -+#define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10) -+#define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11) -+#define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12) -+#define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13) -+#define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14) -+#define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15) -+#define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31) -+#define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0) -+#define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8) -+#define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16) -+#define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24) -+#define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0) -+#define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8) -+#define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16) -+#define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24) -+#define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0) -+#define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8) -+#define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16) -+#define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24) -+#define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0) -+#define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8) -+#define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16) -+#define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24) -+#define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0) -+#define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1) -+#define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4) -+#define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16) -+#define GET_CH0_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000001 ) >> 0) -+#define GET_CH1_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000002 ) >> 1) -+#define GET_CH2_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000004 ) >> 2) -+#define GET_CH3_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000008 ) >> 3) -+#define GET_CH4_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000010 ) >> 4) -+#define GET_CH5_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000020 ) >> 5) -+#define GET_CH6_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000040 ) >> 6) -+#define GET_CH7_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000080 ) >> 7) -+#define GET_CH8_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000100 ) >> 8) -+#define GET_CH9_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000200 ) >> 9) -+#define GET_CH10_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000400 ) >> 10) -+#define GET_CH11_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000800 ) >> 11) -+#define GET_CH12_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00001000 ) >> 12) -+#define GET_CH13_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00002000 ) >> 13) -+#define GET_CH14_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00004000 ) >> 14) -+#define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0) -+#define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0) -+#define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0) -+#define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0) -+#define GET_GPIO_STOP_EN (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000010 ) >> 4) -+#define GET_GPIO_STOP_POL (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000020 ) >> 5) -+#define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16) -+#define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0) -+#define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0) -+#define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0) -+#define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20) -+#define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0) -+#define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0) -+#define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4) -+#define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8) -+#define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12) -+#define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0) -+#define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0) -+#define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4) -+#define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5) -+#define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6) -+#define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7) -+#define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0) -+#define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1) -+#define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2) -+#define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4) -+#define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5) -+#define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6) -+#define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7) -+#define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8) -+#define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9) -+#define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0) -+#define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1) -+#define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2) -+#define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4) -+#define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5) -+#define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6) -+#define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7) -+#define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8) -+#define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16) -+#define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30) -+#define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31) -+#define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0) -+#define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8) -+#define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0) -+#define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8) -+#define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16) -+#define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17) -+#define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20) -+#define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21) -+#define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24) -+#define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0) -+#define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0) -+#define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0) -+#define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0) -+#define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0) -+#define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1) -+#define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8) -+#define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0) -+#define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1) -+#define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2) -+#define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3) -+#define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4) -+#define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13) -+#define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22) -+#define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0) -+#define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9) -+#define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18) -+#define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0) -+#define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4) -+#define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8) -+#define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12) -+#define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16) -+#define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0) -+#define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8) -+#define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0) -+#define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0) -+#define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16) -+#define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30) -+#define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31) -+#define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0) -+#define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8) -+#define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14) -+#define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18) -+#define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22) -+#define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27) -+#define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0) -+#define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0) -+#define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0) -+#define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0) -+#define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0) -+#define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0) -+#define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0) -+#define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9) -+#define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17) -+#define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0) -+#define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9) -+#define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x03e00000 ) >> 21) -+#define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x3c000000 ) >> 26) -+#define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0) -+#define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9) -+#define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17) -+#define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22) -+#define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0) -+#define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16) -+#define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0) -+#define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8) -+#define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16) -+#define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0) -+#define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9) -+#define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18) -+#define GET_RG_PMDLBK (((REG32(ADR_PHY_EN_0)) & 0x00000001 ) >> 0) -+#define GET_RG_RDYACK_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000006 ) >> 1) -+#define GET_RG_ADEDGE_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000008 ) >> 3) -+#define GET_RG_SIGN_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000010 ) >> 4) -+#define GET_RG_IQ_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000020 ) >> 5) -+#define GET_RG_Q_INV (((REG32(ADR_PHY_EN_0)) & 0x00000040 ) >> 6) -+#define GET_RG_I_INV (((REG32(ADR_PHY_EN_0)) & 0x00000080 ) >> 7) -+#define GET_RG_BYPASS_ACI (((REG32(ADR_PHY_EN_0)) & 0x00000100 ) >> 8) -+#define GET_RG_LBK_ANA_PATH (((REG32(ADR_PHY_EN_0)) & 0x00000200 ) >> 9) -+#define GET_RG_SPECTRUM_LEAKY_FACTOR (((REG32(ADR_PHY_EN_0)) & 0x00000c00 ) >> 10) -+#define GET_RG_SPECTRUM_BW (((REG32(ADR_PHY_EN_0)) & 0x00003000 ) >> 12) -+#define GET_RG_SPECTRUM_FREQ_MANUAL (((REG32(ADR_PHY_EN_0)) & 0x00004000 ) >> 14) -+#define GET_RG_SPECTRUM_EN (((REG32(ADR_PHY_EN_0)) & 0x00008000 ) >> 15) -+#define GET_RG_TXPWRLVL_SET (((REG32(ADR_PHY_EN_0)) & 0x00ff0000 ) >> 16) -+#define GET_RG_TXPWRLVL_SEL (((REG32(ADR_PHY_EN_0)) & 0x01000000 ) >> 24) -+#define GET_RG_RF_BB_CLK_SEL (((REG32(ADR_PHY_EN_0)) & 0x80000000 ) >> 31) -+#define GET_RG_PHY_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000001 ) >> 0) -+#define GET_RG_PHYRX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000002 ) >> 1) -+#define GET_RG_PHYTX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000004 ) >> 2) -+#define GET_RG_PHY11GN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000008 ) >> 3) -+#define GET_RG_PHY11B_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000010 ) >> 4) -+#define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000020 ) >> 5) -+#define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000040 ) >> 6) -+#define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000100 ) >> 8) -+#define GET_RG_FORCE_11GN_EN (((REG32(ADR_PHY_EN_1)) & 0x00001000 ) >> 12) -+#define GET_RG_FORCE_11B_EN (((REG32(ADR_PHY_EN_1)) & 0x00002000 ) >> 13) -+#define GET_RG_FFT_MEM_CLK_EN_RX (((REG32(ADR_PHY_EN_1)) & 0x00004000 ) >> 14) -+#define GET_RG_FFT_MEM_CLK_EN_TX (((REG32(ADR_PHY_EN_1)) & 0x00008000 ) >> 15) -+#define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_PHY_EN_1)) & 0x000f0000 ) >> 16) -+#define GET_RG_SPECTRUM_FREQ (((REG32(ADR_PHY_EN_1)) & 0x3ff00000 ) >> 20) -+#define GET_SVN_VERSION (((REG32(ADR_SVN_VERSION_REG)) & 0xffffffff ) >> 0) -+#define GET_RG_LENGTH (((REG32(ADR_PHY_PKT_GEN_0)) & 0x0000ffff ) >> 0) -+#define GET_RG_PKT_MODE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00070000 ) >> 16) -+#define GET_RG_CH_BW (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00380000 ) >> 19) -+#define GET_RG_PRM (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00400000 ) >> 22) -+#define GET_RG_SHORTGI (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00800000 ) >> 23) -+#define GET_RG_RATE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x7f000000 ) >> 24) -+#define GET_RG_L_LENGTH (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00000fff ) >> 0) -+#define GET_RG_L_RATE (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00007000 ) >> 12) -+#define GET_RG_SERVICE (((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff0000 ) >> 16) -+#define GET_RG_SMOOTHING (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000001 ) >> 0) -+#define GET_RG_NO_SOUND (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000002 ) >> 1) -+#define GET_RG_AGGREGATE (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000004 ) >> 2) -+#define GET_RG_STBC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000018 ) >> 3) -+#define GET_RG_FEC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000020 ) >> 5) -+#define GET_RG_N_ESS (((REG32(ADR_PHY_PKT_GEN_2)) & 0x000000c0 ) >> 6) -+#define GET_RG_TXPWRLVL (((REG32(ADR_PHY_PKT_GEN_2)) & 0x0000ff00 ) >> 8) -+#define GET_RG_TX_START (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000001 ) >> 0) -+#define GET_RG_IFS_TIME (((REG32(ADR_PHY_PKT_GEN_3)) & 0x000000fc ) >> 2) -+#define GET_RG_CONTINUOUS_DATA (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000100 ) >> 8) -+#define GET_RG_DATA_SEL (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000600 ) >> 9) -+#define GET_RG_TX_D (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00ff0000 ) >> 16) -+#define GET_RG_TX_CNT_TARGET (((REG32(ADR_PHY_PKT_GEN_4)) & 0xffffffff ) >> 0) -+#define GET_RG_FFT_IFFT_MODE (((REG32(ADR_PHY_REG_00)) & 0x000000c0 ) >> 6) -+#define GET_RG_DAC_DBG_MODE (((REG32(ADR_PHY_REG_00)) & 0x00000100 ) >> 8) -+#define GET_RG_DAC_SGN_SWAP (((REG32(ADR_PHY_REG_00)) & 0x00000200 ) >> 9) -+#define GET_RG_TXD_SEL (((REG32(ADR_PHY_REG_00)) & 0x00000c00 ) >> 10) -+#define GET_RG_UP8X (((REG32(ADR_PHY_REG_00)) & 0x00ff0000 ) >> 16) -+#define GET_RG_IQ_DC_BYP (((REG32(ADR_PHY_REG_00)) & 0x01000000 ) >> 24) -+#define GET_RG_IQ_DC_LEAKY_FACTOR (((REG32(ADR_PHY_REG_00)) & 0x30000000 ) >> 28) -+#define GET_RG_DAC_DCEN (((REG32(ADR_PHY_REG_01)) & 0x00000001 ) >> 0) -+#define GET_RG_DAC_DCQ (((REG32(ADR_PHY_REG_01)) & 0x00003ff0 ) >> 4) -+#define GET_RG_DAC_DCI (((REG32(ADR_PHY_REG_01)) & 0x03ff0000 ) >> 16) -+#define GET_RG_PGA_REFDB_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0x0000007f ) >> 0) -+#define GET_RG_PGA_REFDB_TOP (((REG32(ADR_PHY_REG_02_AGC)) & 0x00007f00 ) >> 8) -+#define GET_RG_PGA_REF_UND (((REG32(ADR_PHY_REG_02_AGC)) & 0x03ff0000 ) >> 16) -+#define GET_RG_RF_REF_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0xf0000000 ) >> 28) -+#define GET_RG_PGAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x0000000f ) >> 0) -+#define GET_RG_PGAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000010 ) >> 4) -+#define GET_RG_RFGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000060 ) >> 5) -+#define GET_RG_RFGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000080 ) >> 7) -+#define GET_RG_WAIT_T_RXAGC (((REG32(ADR_PHY_REG_03_AGC)) & 0x00003f00 ) >> 8) -+#define GET_RG_RXAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00004000 ) >> 14) -+#define GET_RG_RXAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00008000 ) >> 15) -+#define GET_RG_WAIT_T_FINAL (((REG32(ADR_PHY_REG_03_AGC)) & 0x003f0000 ) >> 16) -+#define GET_RG_WAIT_T (((REG32(ADR_PHY_REG_03_AGC)) & 0x3f000000 ) >> 24) -+#define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000000f ) >> 0) -+#define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000000f0 ) >> 4) -+#define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00000f00 ) >> 8) -+#define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000f000 ) >> 12) -+#define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000f0000 ) >> 16) -+#define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00f00000 ) >> 20) -+#define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0f000000 ) >> 24) -+#define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0xf0000000 ) >> 28) -+#define GET_RG_MG_PGA_JB_TH (((REG32(ADR_PHY_REG_05_AGC)) & 0x0000000f ) >> 0) -+#define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x001f0000 ) >> 16) -+#define GET_RG_WR_RFGC_INIT_SET (((REG32(ADR_PHY_REG_05_AGC)) & 0x00600000 ) >> 21) -+#define GET_RG_WR_RFGC_INIT_EN (((REG32(ADR_PHY_REG_05_AGC)) & 0x00800000 ) >> 23) -+#define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x1f000000 ) >> 24) -+#define GET_RG_AGC_THRESHOLD (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x00003fff ) >> 0) -+#define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x007f0000 ) >> 16) -+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x03000000 ) >> 24) -+#define GET_RG_WR_ACI_GAIN_INI_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x000000ff ) >> 0) -+#define GET_RG_WR_ACI_GAIN_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x0000ff00 ) >> 8) -+#define GET_RG_ACI_DAGC_SET_VALUE_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x007f0000 ) >> 16) -+#define GET_RG_WR_ACI_GAIN_OW_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x80000000 ) >> 31) -+#define GET_RG_ACI_POINT_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x000000ff ) >> 0) -+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00000300 ) >> 8) -+#define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xff000000 ) >> 24) -+#define GET_RG_ACI_DAGC_SET_VALUE_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000007f ) >> 0) -+#define GET_RG_ACI_GAIN_INI_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000ff00 ) >> 8) -+#define GET_RG_ACI_GAIN_OW_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x00ff0000 ) >> 16) -+#define GET_RG_ACI_GAIN_OW_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x80000000 ) >> 31) -+#define GET_RO_CCA_PWR_MA_11GN (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x0000007f ) >> 0) -+#define GET_RO_ED_STATE (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x00008000 ) >> 15) -+#define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x007f0000 ) >> 16) -+#define GET_RO_PGA_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x00003fff ) >> 0) -+#define GET_RO_RF_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x000f0000 ) >> 16) -+#define GET_RO_PGAGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x0f000000 ) >> 24) -+#define GET_RO_RFGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x30000000 ) >> 28) -+#define GET_RO_PGA_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x00003fff ) >> 0) -+#define GET_RO_RF_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x000f0000 ) >> 16) -+#define GET_RO_PGAGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x0f000000 ) >> 24) -+#define GET_RO_RFGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x30000000 ) >> 28) -+#define GET_RO_PGA_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x00003fff ) >> 0) -+#define GET_RO_RF_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x000f0000 ) >> 16) -+#define GET_RO_PGAGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x0f000000 ) >> 24) -+#define GET_RO_RFGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x30000000 ) >> 28) -+#define GET_RG_TX_DES_RATE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x0000001f ) >> 0) -+#define GET_RG_TX_DES_MODE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x00001f00 ) >> 8) -+#define GET_RG_TX_DES_LEN_LO (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x001f0000 ) >> 16) -+#define GET_RG_TX_DES_LEN_UP (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x1f000000 ) >> 24) -+#define GET_RG_TX_DES_SRVC_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x0000001f ) >> 0) -+#define GET_RG_TX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x00001f00 ) >> 8) -+#define GET_RG_TX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x001f0000 ) >> 16) -+#define GET_RG_TX_DES_TYPE (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x1f000000 ) >> 24) -+#define GET_RG_TX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000001 ) >> 0) -+#define GET_RG_TX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000010 ) >> 4) -+#define GET_RG_TX_DES_RATE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000100 ) >> 8) -+#define GET_RG_TX_DES_MODE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00001000 ) >> 12) -+#define GET_RG_TX_DES_PWRLVL (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x001f0000 ) >> 16) -+#define GET_RG_TX_DES_SRVC_LO (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x1f000000 ) >> 24) -+#define GET_RG_RX_DES_RATE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x0000003f ) >> 0) -+#define GET_RG_RX_DES_MODE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x00003f00 ) >> 8) -+#define GET_RG_RX_DES_LEN_LO (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x003f0000 ) >> 16) -+#define GET_RG_RX_DES_LEN_UP (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x3f000000 ) >> 24) -+#define GET_RG_RX_DES_SRVC_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x0000003f ) >> 0) -+#define GET_RG_RX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x00003f00 ) >> 8) -+#define GET_RG_RX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x003f0000 ) >> 16) -+#define GET_RG_RX_DES_TYPE (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x3f000000 ) >> 24) -+#define GET_RG_RX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000001 ) >> 0) -+#define GET_RG_RX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000010 ) >> 4) -+#define GET_RG_RX_DES_RATE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000100 ) >> 8) -+#define GET_RG_RX_DES_MODE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00001000 ) >> 12) -+#define GET_RG_RX_DES_SNR (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x000f0000 ) >> 16) -+#define GET_RG_RX_DES_RCPI (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00f00000 ) >> 20) -+#define GET_RG_RX_DES_SRVC_LO (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x3f000000 ) >> 24) -+#define GET_RO_TX_DES_EXCP_RATE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x000000ff ) >> 0) -+#define GET_RO_TX_DES_EXCP_CH_BW_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x0000ff00 ) >> 8) -+#define GET_RO_TX_DES_EXCP_MODE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x00ff0000 ) >> 16) -+#define GET_RG_TX_DES_EXCP_RATE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x07000000 ) >> 24) -+#define GET_RG_TX_DES_EXCP_MODE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x70000000 ) >> 28) -+#define GET_RG_TX_DES_EXCP_CLR (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x80000000 ) >> 31) -+#define GET_RG_TX_DES_ACK_WIDTH (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x00000001 ) >> 0) -+#define GET_RG_TX_DES_ACK_PRD (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x0000000e ) >> 1) -+#define GET_RG_RX_DES_SNR_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x003f0000 ) >> 16) -+#define GET_RG_RX_DES_RCPI_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x3f000000 ) >> 24) -+#define GET_RG_TST_TBUS_SEL (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x0000000f ) >> 0) -+#define GET_RG_RSSI_OFFSET (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x00ff0000 ) >> 16) -+#define GET_RG_RSSI_INV (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x01000000 ) >> 24) -+#define GET_RG_TST_ADC_ON (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x40000000 ) >> 30) -+#define GET_RG_TST_EXT_GAIN (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x80000000 ) >> 31) -+#define GET_RG_DAC_Q_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x000003ff ) >> 0) -+#define GET_RG_DAC_I_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x003ff000 ) >> 12) -+#define GET_RG_DAC_EN_MAN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x10000000 ) >> 28) -+#define GET_RG_IQC_FFT_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x20000000 ) >> 29) -+#define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x40000000 ) >> 30) -+#define GET_RG_DAC_MAN_I_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x80000000 ) >> 31) -+#define GET_RO_MRX_EN_CNT (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x0000ffff ) >> 0) -+#define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x80000000 ) >> 31) -+#define GET_RG_PA_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x000000ff ) >> 0) -+#define GET_RG_RFTX_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x0000ff00 ) >> 8) -+#define GET_RG_DAC_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ff0000 ) >> 16) -+#define GET_RG_SW_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff000000 ) >> 24) -+#define GET_RG_PA_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x000000ff ) >> 0) -+#define GET_RG_RFTX_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x0000ff00 ) >> 8) -+#define GET_RG_DAC_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ff0000 ) >> 16) -+#define GET_RG_SW_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff000000 ) >> 24) -+#define GET_RG_ANT_SW_0 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000007 ) >> 0) -+#define GET_RG_ANT_SW_1 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000038 ) >> 3) -+#define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x00001fff ) >> 0) -+#define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16) -+#define GET_RG_MTX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x80000000 ) >> 31) -+#define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x00001fff ) >> 0) -+#define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16) -+#define GET_RG_MTX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x80000000 ) >> 31) -+#define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x00001fff ) >> 0) -+#define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16) -+#define GET_RG_MRX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x80000000 ) >> 31) -+#define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x00001fff ) >> 0) -+#define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16) -+#define GET_RG_MRX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x80000000 ) >> 31) -+#define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff ) >> 0) -+#define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000 ) >> 16) -+#define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff ) >> 0) -+#define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000 ) >> 16) -+#define GET_RG_MODE_REG_IN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x0000ffff ) >> 0) -+#define GET_RG_PARALLEL_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x00100000 ) >> 20) -+#define GET_RG_MBRUN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x01000000 ) >> 24) -+#define GET_RG_SHIFT_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x10000000 ) >> 28) -+#define GET_RG_MODE_REG_SI_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x20000000 ) >> 29) -+#define GET_RG_SIMULATION_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x40000000 ) >> 30) -+#define GET_RG_DBIST_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x80000000 ) >> 31) -+#define GET_RO_MODE_REG_OUT_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x0000ffff ) >> 0) -+#define GET_RO_MODE_REG_SO_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x01000000 ) >> 24) -+#define GET_RO_MONITOR_BUS_16 (((REG32(ADR_PHY_READ_REG_07_BIST)) & 0x0007ffff ) >> 0) -+#define GET_RG_MRX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x000000ff ) >> 0) -+#define GET_RG_MRX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x0000ff00 ) >> 8) -+#define GET_RG_MTX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ff0000 ) >> 16) -+#define GET_RG_MTX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff000000 ) >> 24) -+#define GET_RO_MTX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff ) >> 0) -+#define GET_RO_MTX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000 ) >> 16) -+#define GET_RO_MRX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff ) >> 0) -+#define GET_RO_MRX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000 ) >> 16) -+#define GET_RG_HB_COEF0 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x00000fff ) >> 0) -+#define GET_RG_HB_COEF1 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x0fff0000 ) >> 16) -+#define GET_RG_HB_COEF2 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x00000fff ) >> 0) -+#define GET_RG_HB_COEF3 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x0fff0000 ) >> 16) -+#define GET_RG_HB_COEF4 (((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0x00000fff ) >> 0) -+#define GET_RO_TBUS_O (((REG32(ADR_PHY_READ_TBUS)) & 0x000fffff ) >> 0) -+#define GET_RG_LPF4_00 (((REG32(ADR_TX_11B_FIL_COEF_00)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_01 (((REG32(ADR_TX_11B_FIL_COEF_01)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_02 (((REG32(ADR_TX_11B_FIL_COEF_02)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_03 (((REG32(ADR_TX_11B_FIL_COEF_03)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_04 (((REG32(ADR_TX_11B_FIL_COEF_04)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_05 (((REG32(ADR_TX_11B_FIL_COEF_05)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_06 (((REG32(ADR_TX_11B_FIL_COEF_06)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_07 (((REG32(ADR_TX_11B_FIL_COEF_07)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_08 (((REG32(ADR_TX_11B_FIL_COEF_08)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_09 (((REG32(ADR_TX_11B_FIL_COEF_09)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_10 (((REG32(ADR_TX_11B_FIL_COEF_10)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_11 (((REG32(ADR_TX_11B_FIL_COEF_11)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_12 (((REG32(ADR_TX_11B_FIL_COEF_12)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_13 (((REG32(ADR_TX_11B_FIL_COEF_13)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_14 (((REG32(ADR_TX_11B_FIL_COEF_14)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_15 (((REG32(ADR_TX_11B_FIL_COEF_15)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_16 (((REG32(ADR_TX_11B_FIL_COEF_16)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_17 (((REG32(ADR_TX_11B_FIL_COEF_17)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_18 (((REG32(ADR_TX_11B_FIL_COEF_18)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_19 (((REG32(ADR_TX_11B_FIL_COEF_19)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_20 (((REG32(ADR_TX_11B_FIL_COEF_20)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_21 (((REG32(ADR_TX_11B_FIL_COEF_21)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_22 (((REG32(ADR_TX_11B_FIL_COEF_22)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_23 (((REG32(ADR_TX_11B_FIL_COEF_23)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_24 (((REG32(ADR_TX_11B_FIL_COEF_24)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_25 (((REG32(ADR_TX_11B_FIL_COEF_25)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_26 (((REG32(ADR_TX_11B_FIL_COEF_26)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_27 (((REG32(ADR_TX_11B_FIL_COEF_27)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_28 (((REG32(ADR_TX_11B_FIL_COEF_28)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_29 (((REG32(ADR_TX_11B_FIL_COEF_29)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_30 (((REG32(ADR_TX_11B_FIL_COEF_30)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_31 (((REG32(ADR_TX_11B_FIL_COEF_31)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_32 (((REG32(ADR_TX_11B_FIL_COEF_32)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_33 (((REG32(ADR_TX_11B_FIL_COEF_33)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_34 (((REG32(ADR_TX_11B_FIL_COEF_34)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_35 (((REG32(ADR_TX_11B_FIL_COEF_35)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_36 (((REG32(ADR_TX_11B_FIL_COEF_36)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_37 (((REG32(ADR_TX_11B_FIL_COEF_37)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_38 (((REG32(ADR_TX_11B_FIL_COEF_38)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_39 (((REG32(ADR_TX_11B_FIL_COEF_39)) & 0x00001fff ) >> 0) -+#define GET_RG_LPF4_40 (((REG32(ADR_TX_11B_FIL_COEF_40)) & 0x00001fff ) >> 0) -+#define GET_RG_BP_SMB (((REG32(ADR_TX_11B_PLCP)) & 0x00002000 ) >> 13) -+#define GET_RG_EN_SRVC (((REG32(ADR_TX_11B_PLCP)) & 0x00004000 ) >> 14) -+#define GET_RG_DES_SPD (((REG32(ADR_TX_11B_PLCP)) & 0x00030000 ) >> 16) -+#define GET_RG_BB_11B_RISE_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x000000ff ) >> 0) -+#define GET_RG_BB_11B_FALL_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x0000ff00 ) >> 8) -+#define GET_RG_WR_TX_EN_CNT_RST_N (((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0x00000001 ) >> 0) -+#define GET_RO_TX_EN_CNT (((REG32(ADR_TX_11B_EN_CNT)) & 0x0000ffff ) >> 0) -+#define GET_RO_TX_CNT (((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0xffffffff ) >> 0) -+#define GET_RG_POS_DES_11B_L_EXT (((REG32(ADR_RX_11B_DES_DLY)) & 0x0000000f ) >> 0) -+#define GET_RG_PRE_DES_11B_DLY (((REG32(ADR_RX_11B_DES_DLY)) & 0x000000f0 ) >> 4) -+#define GET_RG_CNT_CCA_LMT (((REG32(ADR_RX_11B_CCA_0)) & 0x000f0000 ) >> 16) -+#define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_RX_11B_CCA_0)) & 0x20000000 ) >> 29) -+#define GET_RG_BYPASS_AGC (((REG32(ADR_RX_11B_CCA_0)) & 0x80000000 ) >> 31) -+#define GET_RG_CCA_BIT_CNT_LMT_RX (((REG32(ADR_RX_11B_CCA_1)) & 0x000000f0 ) >> 4) -+#define GET_RG_CCA_SCALE_BF (((REG32(ADR_RX_11B_CCA_1)) & 0x007f0000 ) >> 16) -+#define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_RX_11B_CCA_1)) & 0x30000000 ) >> 28) -+#define GET_RG_TR_KI_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000007 ) >> 0) -+#define GET_RG_TR_KP_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000070 ) >> 4) -+#define GET_RG_TR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000700 ) >> 8) -+#define GET_RG_TR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00007000 ) >> 12) -+#define GET_RG_CR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00070000 ) >> 16) -+#define GET_RG_CR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00700000 ) >> 20) -+#define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000001f ) >> 0) -+#define GET_RG_CE_T4_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000ff00 ) >> 8) -+#define GET_RG_CE_T3_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ff0000 ) >> 16) -+#define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff000000 ) >> 24) -+#define GET_RG_CE_MU_T1 (((REG32(ADR_RX_11B_CE_MU_0)) & 0x00000007 ) >> 0) -+#define GET_RG_CE_DLY_SEL (((REG32(ADR_RX_11B_CE_MU_0)) & 0x003f0000 ) >> 16) -+#define GET_RG_CE_MU_T8 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000007 ) >> 0) -+#define GET_RG_CE_MU_T7 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000070 ) >> 4) -+#define GET_RG_CE_MU_T6 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000700 ) >> 8) -+#define GET_RG_CE_MU_T5 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00007000 ) >> 12) -+#define GET_RG_CE_MU_T4 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00070000 ) >> 16) -+#define GET_RG_CE_MU_T3 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00700000 ) >> 20) -+#define GET_RG_CE_MU_T2 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x07000000 ) >> 24) -+#define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x0000000f ) >> 0) -+#define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000000f0 ) >> 4) -+#define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000f0000 ) >> 16) -+#define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x00f00000 ) >> 20) -+#define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x0000000f ) >> 0) -+#define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000000f0 ) >> 4) -+#define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000f0000 ) >> 16) -+#define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x00f00000 ) >> 20) -+#define GET_RG_EQ_KI_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00000700 ) >> 8) -+#define GET_RG_EQ_KP_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00007000 ) >> 12) -+#define GET_RG_EQ_KI_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00070000 ) >> 16) -+#define GET_RG_EQ_KP_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00700000 ) >> 20) -+#define GET_RG_TR_LPF_RATE (((REG32(ADR_RX_11B_LPF_RATE)) & 0x003fffff ) >> 0) -+#define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x0000007f ) >> 0) -+#define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00000080 ) >> 7) -+#define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00007f00 ) >> 8) -+#define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x007f0000 ) >> 16) -+#define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x7f000000 ) >> 24) -+#define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x00000001 ) >> 0) -+#define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x07ff0000 ) >> 16) -+#define GET_RG_PWRON_DLY_TH_11B (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x000000ff ) >> 0) -+#define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x00ff0000 ) >> 16) -+#define GET_RG_CCA_PWR_TH_RX (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x00007fff ) >> 0) -+#define GET_RG_CCA_PWR_CNT_TH (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x001f0000 ) >> 16) -+#define GET_B_FREQ_OS (((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0x000007ff ) >> 0) -+#define GET_B_SNR (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x0000007f ) >> 0) -+#define GET_B_RCPI (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x007f0000 ) >> 16) -+#define GET_CRC_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff ) >> 0) -+#define GET_SFD_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000 ) >> 16) -+#define GET_B_PACKET_ERR_CNT (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x0000ffff ) >> 0) -+#define GET_PACKET_ERR (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x00010000 ) >> 16) -+#define GET_B_PACKET_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0) -+#define GET_B_CCA_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16) -+#define GET_B_LENGTH_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff ) >> 0) -+#define GET_SFD_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000 ) >> 16) -+#define GET_SIGNAL_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x000000ff ) >> 0) -+#define GET_B_SERVICE_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x0000ff00 ) >> 8) -+#define GET_CRC_CORRECT (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x00010000 ) >> 16) -+#define GET_DEBUG_SEL (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x0000000f ) >> 0) -+#define GET_RG_PACKET_STAT_EN_11B (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00100000 ) >> 20) -+#define GET_RG_BIT_REVERSE (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00200000 ) >> 21) -+#define GET_RX_PHY_11B_SOFT_RST_N (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000001 ) >> 0) -+#define GET_RG_CE_BYPASS_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x000000f0 ) >> 4) -+#define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000f00 ) >> 8) -+#define GET_RG_BB_11GN_RISE_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x000000ff ) >> 0) -+#define GET_RG_BB_11GN_FALL_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x0000ff00 ) >> 8) -+#define GET_RG_HTCARR52_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x000003ff ) >> 0) -+#define GET_RG_HTCARR56_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x003ff000 ) >> 12) -+#define GET_RG_PACKET_STAT_EN (((REG32(ADR_TX_11GN_PLCP)) & 0x00800000 ) >> 23) -+#define GET_RG_SMB_DEF (((REG32(ADR_TX_11GN_PLCP)) & 0x7f000000 ) >> 24) -+#define GET_RG_CONTINUOUS_DATA_11GN (((REG32(ADR_TX_11GN_PLCP)) & 0x80000000 ) >> 31) -+#define GET_RO_TX_CNT_R (((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0xffffffff ) >> 0) -+#define GET_RO_PACKET_ERR_CNT (((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0x0000ffff ) >> 0) -+#define GET_RG_POS_DES_11GN_L_EXT (((REG32(ADR_RX_11GN_DES_DLY)) & 0x0000000f ) >> 0) -+#define GET_RG_PRE_DES_11GN_DLY (((REG32(ADR_RX_11GN_DES_DLY)) & 0x000000f0 ) >> 4) -+#define GET_RG_TR_LPF_KI_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000000f ) >> 0) -+#define GET_RG_TR_LPF_KP_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x000000f0 ) >> 4) -+#define GET_RG_TR_CNT_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000ff00 ) >> 8) -+#define GET_RG_TR_LPF_KI_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x000f0000 ) >> 16) -+#define GET_RG_TR_LPF_KP_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x00f00000 ) >> 20) -+#define GET_RG_TR_CNT_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0xff000000 ) >> 24) -+#define GET_RG_TR_LPF_KI_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000000f ) >> 0) -+#define GET_RG_TR_LPF_KP_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x000000f0 ) >> 4) -+#define GET_RG_TR_CNT_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000ff00 ) >> 8) -+#define GET_RG_TR_LPF_KI_G (((REG32(ADR_RX_11GN_TR_2)) & 0x0000000f ) >> 0) -+#define GET_RG_TR_LPF_KP_G (((REG32(ADR_RX_11GN_TR_2)) & 0x000000f0 ) >> 4) -+#define GET_RG_TR_LPF_RATE_G (((REG32(ADR_RX_11GN_TR_2)) & 0x3fffff00 ) >> 8) -+#define GET_RG_CR_LPF_KI_G (((REG32(ADR_RX_11GN_CCA_0)) & 0x00000007 ) >> 0) -+#define GET_RG_SYM_BOUND_CNT (((REG32(ADR_RX_11GN_CCA_0)) & 0x00007f00 ) >> 8) -+#define GET_RG_XSCOR32_RATIO (((REG32(ADR_RX_11GN_CCA_0)) & 0x007f0000 ) >> 16) -+#define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_RX_11GN_CCA_0)) & 0x7f000000 ) >> 24) -+#define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_1)) & 0x00007f00 ) >> 8) -+#define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_1)) & 0x007f0000 ) >> 16) -+#define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_RX_11GN_CCA_1)) & 0x7f000000 ) >> 24) -+#define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_2)) & 0x007f0000 ) >> 16) -+#define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_2)) & 0x7f000000 ) >> 24) -+#define GET_RG_RX_FFT_SCALE (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x000003ff ) >> 0) -+#define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x00010000 ) >> 16) -+#define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x0f000000 ) >> 24) -+#define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x000000ff ) >> 0) -+#define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x0000ff00 ) >> 8) -+#define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ff0000 ) >> 16) -+#define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff000000 ) >> 24) -+#define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0xff000000 ) >> 24) -+#define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x000000ff ) >> 0) -+#define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x0000ff00 ) >> 8) -+#define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ff0000 ) >> 16) -+#define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff000000 ) >> 24) -+#define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x000000ff ) >> 0) -+#define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x0000ff00 ) >> 8) -+#define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ff0000 ) >> 16) -+#define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff000000 ) >> 24) -+#define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0xff000000 ) >> 24) -+#define GET_RG_SNR_TH_64QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x0000007f ) >> 0) -+#define GET_RG_SNR_TH_16QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x00007f00 ) >> 8) -+#define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x0000007f ) >> 0) -+#define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00007f00 ) >> 8) -+#define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00030000 ) >> 16) -+#define GET_RG_PWRON_DLY_TH_11GN (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x000000ff ) >> 0) -+#define GET_RG_SB_START_CNT (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x00007f00 ) >> 8) -+#define GET_RG_POW16_CNT_TH (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x000000f0 ) >> 4) -+#define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x00000700 ) >> 8) -+#define GET_RG_POW16_TH_L (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x7f000000 ) >> 24) -+#define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00000007 ) >> 0) -+#define GET_RG_XSCOR16_RATIO (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00007f00 ) >> 8) -+#define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00070000 ) >> 16) -+#define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x7f000000 ) >> 24) -+#define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x0000007f ) >> 0) -+#define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x00070000 ) >> 16) -+#define GET_RG_VITERBI_TB_BITS (((REG32(ADR_RX_11GN_VTB_TB)) & 0xff000000 ) >> 24) -+#define GET_RG_CR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x000000ff ) >> 0) -+#define GET_RG_TR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x00ff0000 ) >> 16) -+#define GET_RG_BYPASS_CPE_MA (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000010 ) >> 4) -+#define GET_RG_PILOT_BNDRY_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000700 ) >> 8) -+#define GET_RG_EQ_SHORT_GI_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00007000 ) >> 12) -+#define GET_RG_FFT_WDW_SHORT_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00070000 ) >> 16) -+#define GET_RG_CHSMTH_COEF (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00030000 ) >> 16) -+#define GET_RG_CHSMTH_EN (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00040000 ) >> 18) -+#define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x07000000 ) >> 24) -+#define GET_RG_CH_UPDATE (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x80000000 ) >> 31) -+#define GET_RG_FMT_DET_MM_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x000000ff ) >> 0) -+#define GET_RG_FMT_DET_GF_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x0000ff00 ) >> 8) -+#define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x02000000 ) >> 25) -+#define GET_RG_FMT_DET_LENGTH_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff ) >> 0) -+#define GET_RG_L_LENGTH_MAX (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000 ) >> 16) -+#define GET_RG_TX_TIME_EXT (((REG32(ADR_RX_11GN_TX_TIME)) & 0x000000ff ) >> 0) -+#define GET_RG_MAC_DES_SPACE (((REG32(ADR_RX_11GN_TX_TIME)) & 0x00f00000 ) >> 20) -+#define GET_RG_TR_LPF_STBC_GF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000000f ) >> 0) -+#define GET_RG_TR_LPF_STBC_GF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x000000f0 ) >> 4) -+#define GET_RG_TR_LPF_STBC_MF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x00000f00 ) >> 8) -+#define GET_RG_TR_LPF_STBC_MF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000f000 ) >> 12) -+#define GET_RG_MODE_REG_IN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x0001ffff ) >> 0) -+#define GET_RG_PARALLEL_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x00100000 ) >> 20) -+#define GET_RG_MBRUN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x01000000 ) >> 24) -+#define GET_RG_SHIFT_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x10000000 ) >> 28) -+#define GET_RG_MODE_REG_SI_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x20000000 ) >> 29) -+#define GET_RG_SIMULATION_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x40000000 ) >> 30) -+#define GET_RG_DBIST_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x80000000 ) >> 31) -+#define GET_RG_MODE_REG_IN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x0000ffff ) >> 0) -+#define GET_RG_PARALLEL_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x00100000 ) >> 20) -+#define GET_RG_MBRUN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x01000000 ) >> 24) -+#define GET_RG_SHIFT_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x10000000 ) >> 28) -+#define GET_RG_MODE_REG_SI_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x20000000 ) >> 29) -+#define GET_RG_SIMULATION_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x40000000 ) >> 30) -+#define GET_RG_DBIST_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x80000000 ) >> 31) -+#define GET_RO_MODE_REG_OUT_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x0001ffff ) >> 0) -+#define GET_RO_MODE_REG_SO_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x01000000 ) >> 24) -+#define GET_RO_MONITOR_BUS_80 (((REG32(ADR_RX_11GN_BIST_3)) & 0x003fffff ) >> 0) -+#define GET_RO_MODE_REG_OUT_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x0000ffff ) >> 0) -+#define GET_RO_MODE_REG_SO_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x01000000 ) >> 24) -+#define GET_RO_MONITOR_BUS_64 (((REG32(ADR_RX_11GN_BIST_5)) & 0x0007ffff ) >> 0) -+#define GET_RO_SPECTRUM_DATA (((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0xffffffff ) >> 0) -+#define GET_GN_SNR (((REG32(ADR_RX_11GN_READ_0)) & 0x0000007f ) >> 0) -+#define GET_GN_NOISE_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x00007f00 ) >> 8) -+#define GET_GN_RCPI (((REG32(ADR_RX_11GN_READ_0)) & 0x007f0000 ) >> 16) -+#define GET_GN_SIGNAL_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x7f000000 ) >> 24) -+#define GET_RO_FREQ_OS_LTS (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x00007fff ) >> 0) -+#define GET_CSTATE (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x000f0000 ) >> 16) -+#define GET_SIGNAL_FIELD0 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0x00ffffff ) >> 0) -+#define GET_SIGNAL_FIELD1 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0x00ffffff ) >> 0) -+#define GET_GN_PACKET_ERR_CNT (((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0x0000ffff ) >> 0) -+#define GET_GN_PACKET_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0) -+#define GET_GN_CCA_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16) -+#define GET_GN_LENGTH_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff ) >> 0) -+#define GET_GN_SERVICE_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000 ) >> 16) -+#define GET_RO_HT_MCS_40M (((REG32(ADR_RX_11GN_RATE)) & 0x0000007f ) >> 0) -+#define GET_RO_L_RATE_40M (((REG32(ADR_RX_11GN_RATE)) & 0x00003f00 ) >> 8) -+#define GET_RG_DAGC_CNT_TH (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00000003 ) >> 0) -+#define GET_RG_PACKET_STAT_EN_11GN (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00100000 ) >> 20) -+#define GET_RX_PHY_11GN_SOFT_RST_N (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000001 ) >> 0) -+#define GET_RG_RIFS_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000002 ) >> 1) -+#define GET_RG_STBC_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000004 ) >> 2) -+#define GET_RG_COR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000008 ) >> 3) -+#define GET_RG_INI_PHASE (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000030 ) >> 4) -+#define GET_RG_HT_LTF_SEL_EQ (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000040 ) >> 6) -+#define GET_RG_HT_LTF_SEL_PILOT (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000080 ) >> 7) -+#define GET_RG_CCA_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000200 ) >> 9) -+#define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000400 ) >> 10) -+#define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000800 ) >> 11) -+#define GET_RG_DEBUG_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x0000f000 ) >> 12) -+#define GET_RG_POST_CLK_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00010000 ) >> 16) -+#define GET_IQCAL_RF_TX_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000001 ) >> 0) -+#define GET_IQCAL_RF_TX_PA_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000002 ) >> 1) -+#define GET_IQCAL_RF_TX_DAC_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000004 ) >> 2) -+#define GET_IQCAL_RF_RX_AGC (((REG32(ADR_RF_CONTROL_0)) & 0x00000008 ) >> 3) -+#define GET_IQCAL_RF_PGAG (((REG32(ADR_RF_CONTROL_0)) & 0x00000f00 ) >> 8) -+#define GET_IQCAL_RF_RFG (((REG32(ADR_RF_CONTROL_0)) & 0x00003000 ) >> 12) -+#define GET_RG_TONEGEN_FREQ (((REG32(ADR_RF_CONTROL_0)) & 0x007f0000 ) >> 16) -+#define GET_RG_TONEGEN_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00800000 ) >> 23) -+#define GET_RG_TONEGEN_INIT_PH (((REG32(ADR_RF_CONTROL_0)) & 0x7f000000 ) >> 24) -+#define GET_RG_TONEGEN2_FREQ (((REG32(ADR_RF_CONTROL_1)) & 0x0000007f ) >> 0) -+#define GET_RG_TONEGEN2_EN (((REG32(ADR_RF_CONTROL_1)) & 0x00000080 ) >> 7) -+#define GET_RG_TONEGEN2_SCALE (((REG32(ADR_RF_CONTROL_1)) & 0x0000ff00 ) >> 8) -+#define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x000003ff ) >> 0) -+#define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x03ff0000 ) >> 16) -+#define GET_RG_TX_I_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x000000ff ) >> 0) -+#define GET_RG_TX_Q_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x0000ff00 ) >> 8) -+#define GET_RG_TX_IQ_SWP (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00010000 ) >> 16) -+#define GET_RG_TX_SGN_OUT (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00020000 ) >> 17) -+#define GET_RG_TXIQ_EMU_IDX (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x003c0000 ) >> 18) -+#define GET_RG_TX_IQ_SRC (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x03000000 ) >> 24) -+#define GET_RG_TX_I_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x000003ff ) >> 0) -+#define GET_RG_TX_Q_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x03ff0000 ) >> 16) -+#define GET_RG_TX_IQ_THETA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0) -+#define GET_RG_TX_IQ_ALPHA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8) -+#define GET_RG_TXIQ_NOSHRINK (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13) -+#define GET_RG_TX_I_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ff0000 ) >> 16) -+#define GET_RG_TX_Q_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff000000 ) >> 24) -+#define GET_RG_RX_IQ_THETA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0) -+#define GET_RG_RX_IQ_ALPHA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8) -+#define GET_RG_RXIQ_NOSHRINK (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13) -+#define GET_RG_MA_DPTH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x0000000f ) >> 0) -+#define GET_RG_INTG_PH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x000003f0 ) >> 4) -+#define GET_RG_INTG_PRD (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00001c00 ) >> 10) -+#define GET_RG_INTG_MU (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00006000 ) >> 13) -+#define GET_RG_IQCAL_SPRM_SELQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00010000 ) >> 16) -+#define GET_RG_IQCAL_SPRM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00020000 ) >> 17) -+#define GET_RG_IQCAL_SPRM_FREQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00fc0000 ) >> 18) -+#define GET_RG_IQCAL_IQCOL_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x01000000 ) >> 24) -+#define GET_RG_IQCAL_ALPHA_ESTM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x02000000 ) >> 25) -+#define GET_RG_IQCAL_DC_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x04000000 ) >> 26) -+#define GET_RG_PHEST_STBY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x08000000 ) >> 27) -+#define GET_RG_PHEST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x10000000 ) >> 28) -+#define GET_RG_GP_DIV_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x20000000 ) >> 29) -+#define GET_RG_DPD_GAIN_EST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x40000000 ) >> 30) -+#define GET_RG_IQCAL_MULT_OP0 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x000003ff ) >> 0) -+#define GET_RG_IQCAL_MULT_OP1 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x03ff0000 ) >> 16) -+#define GET_RO_IQCAL_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x000fffff ) >> 0) -+#define GET_RO_IQCAL_SPRM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00100000 ) >> 20) -+#define GET_RO_IQCAL_IQCOL_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00200000 ) >> 21) -+#define GET_RO_IQCAL_ALPHA_ESTM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00400000 ) >> 22) -+#define GET_RO_IQCAL_DC_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00800000 ) >> 23) -+#define GET_RO_IQCAL_MULT_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x01000000 ) >> 24) -+#define GET_RO_FFT_ENRG_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x02000000 ) >> 25) -+#define GET_RO_PHEST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x04000000 ) >> 26) -+#define GET_RO_GP_DIV_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x08000000 ) >> 27) -+#define GET_RO_GAIN_EST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x10000000 ) >> 28) -+#define GET_RO_AMP_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0x000001ff ) >> 0) -+#define GET_RG_RX_I_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x000000ff ) >> 0) -+#define GET_RG_RX_Q_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x0000ff00 ) >> 8) -+#define GET_RG_RX_I_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ff0000 ) >> 16) -+#define GET_RG_RX_Q_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff000000 ) >> 24) -+#define GET_RG_RX_IQ_SWP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000001 ) >> 0) -+#define GET_RG_RX_SGN_IN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000002 ) >> 1) -+#define GET_RG_RX_IQ_SRC (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x0000000c ) >> 2) -+#define GET_RG_ACI_GAIN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000ff0 ) >> 4) -+#define GET_RG_FFT_EN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00001000 ) >> 12) -+#define GET_RG_FFT_MOD (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00002000 ) >> 13) -+#define GET_RG_FFT_SCALE (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00ffc000 ) >> 14) -+#define GET_RG_FFT_ENRG_FREQ (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x3f000000 ) >> 24) -+#define GET_RG_FPGA_80M_PH_UP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x40000000 ) >> 30) -+#define GET_RG_FPGA_80M_PH_STP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x80000000 ) >> 31) -+#define GET_RG_ADC2LA_SEL (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000001 ) >> 0) -+#define GET_RG_ADC2LA_CLKPH (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000002 ) >> 1) -+#define GET_RG_RXIQ_EMU_IDX (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x0000000f ) >> 0) -+#define GET_RG_IQCAL_BP_ACI (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x00000010 ) >> 4) -+#define GET_RG_DPD_AM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000001 ) >> 0) -+#define GET_RG_DPD_PM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000002 ) >> 1) -+#define GET_RG_DPD_PM_AMSEL (((REG32(ADR_DPD_CONTROL)) & 0x00000004 ) >> 2) -+#define GET_RG_DPD_020_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_040_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_060_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_080_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_0A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_0C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_0D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_0E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_0F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_100_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_110_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_120_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_130_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_140_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_150_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_160_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_170_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_180_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_190_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_1A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_1B0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_1C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_1D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_1E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_1F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_200_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x03ff0000 ) >> 16) -+#define GET_RG_DPD_020_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_040_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_060_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_080_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_0A0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_0C0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_0D0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_0E0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_0F0_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_100_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_110_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_120_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_130_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_140_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_150_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_160_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_170_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_180_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_190_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_1A0_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_1B0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_1C0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_1D0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_1E0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_1F0_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x00001fff ) >> 0) -+#define GET_RG_DPD_200_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x1fff0000 ) >> 16) -+#define GET_RG_DPD_GAIN_EST_Y0 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x000001ff ) >> 0) -+#define GET_RG_DPD_GAIN_EST_Y1 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x01ff0000 ) >> 16) -+#define GET_RG_DPD_LOOP_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0x000003ff ) >> 0) -+#define GET_RG_DPD_GAIN_EST_X0 (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x000001ff ) >> 0) -+#define GET_RO_DPD_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x03ff0000 ) >> 16) -+#define GET_TX_SCALE_11B (((REG32(ADR_TX_GAIN_FACTOR)) & 0x000000ff ) >> 0) -+#define GET_TX_SCALE_11B_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0x0000ff00 ) >> 8) -+#define GET_TX_SCALE_11G (((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ff0000 ) >> 16) -+#define GET_TX_SCALE_11G_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0xff000000 ) >> 24) -+#define GET_RG_EN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_RG_TX_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1) -+#define GET_RG_TX_PA_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2) -+#define GET_RG_TX_DAC_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3) -+#define GET_RG_RX_AGC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4) -+#define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5) -+#define GET_RG_RFG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6) -+#define GET_RG_PGAG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8) -+#define GET_RG_MODE (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12) -+#define GET_RG_EN_TX_TRSW (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14) -+#define GET_RG_EN_SX (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15) -+#define GET_RG_EN_RX_LNA (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16) -+#define GET_RG_EN_RX_MIXER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17) -+#define GET_RG_EN_RX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18) -+#define GET_RG_EN_RX_LOBUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19) -+#define GET_RG_EN_RX_TZ (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20) -+#define GET_RG_EN_RX_FILTER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21) -+#define GET_RG_EN_RX_HPF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22) -+#define GET_RG_EN_RX_RSSI (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23) -+#define GET_RG_EN_ADC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24) -+#define GET_RG_EN_TX_MOD (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25) -+#define GET_RG_EN_TX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26) -+#define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27) -+#define GET_RG_EN_TX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28) -+#define GET_RG_EN_RX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29) -+#define GET_RG_SEL_DPLL_CLK (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30) -+#define GET_RG_EN_CLK_960MBY13_UART (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x80000000 ) >> 31) -+#define GET_RG_EN_TX_DPD (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_RG_EN_TX_TSSI (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1) -+#define GET_RG_EN_RX_IQCAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2) -+#define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3) -+#define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4) -+#define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5) -+#define GET_RG_EN_LDO_RX_FE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6) -+#define GET_RG_EN_LDO_ABB (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7) -+#define GET_RG_EN_LDO_AFE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8) -+#define GET_RG_EN_SX_CHPLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9) -+#define GET_RG_EN_SX_LOBFLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10) -+#define GET_RG_EN_IREF_RX (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11) -+#define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13) -+#define GET_RG_EN_SX_LCK_BIN (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14) -+#define GET_RG_RTC_CAL_MODE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16) -+#define GET_RG_EN_IQPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17) -+#define GET_RG_EN_TESTPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18) -+#define GET_RG_EN_TRXBF_BYPASS (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19) -+#define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_LDO_REGISTER)) & 0x00000007 ) >> 0) -+#define GET_RG_LDO_LEVEL_ABB (((REG32(ADR_LDO_REGISTER)) & 0x00000038 ) >> 3) -+#define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_LDO_REGISTER)) & 0x000001c0 ) >> 6) -+#define GET_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00000e00 ) >> 9) -+#define GET_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00007000 ) >> 12) -+#define GET_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00038000 ) >> 15) -+#define GET_RG_DP_LDO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x001c0000 ) >> 18) -+#define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00e00000 ) >> 21) -+#define GET_RG_TX_LDO_TX_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x07000000 ) >> 24) -+#define GET_RG_EN_RX_PADSW (((REG32(ADR_ABB_REGISTER_1)) & 0x00000001 ) >> 0) -+#define GET_RG_EN_RX_TESTNODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000002 ) >> 1) -+#define GET_RG_RX_ABBCFIX (((REG32(ADR_ABB_REGISTER_1)) & 0x00000004 ) >> 2) -+#define GET_RG_RX_ABBCTUNE (((REG32(ADR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3) -+#define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000200 ) >> 9) -+#define GET_RG_RX_ABB_N_MODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000400 ) >> 10) -+#define GET_RG_RX_EN_LOOPA (((REG32(ADR_ABB_REGISTER_1)) & 0x00000800 ) >> 11) -+#define GET_RG_RX_FILTERI1ST (((REG32(ADR_ABB_REGISTER_1)) & 0x00003000 ) >> 12) -+#define GET_RG_RX_FILTERI2ND (((REG32(ADR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14) -+#define GET_RG_RX_FILTERI3RD (((REG32(ADR_ABB_REGISTER_1)) & 0x00030000 ) >> 16) -+#define GET_RG_RX_FILTERI_COURSE (((REG32(ADR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18) -+#define GET_RG_RX_FILTERVCM (((REG32(ADR_ABB_REGISTER_1)) & 0x00300000 ) >> 20) -+#define GET_RG_RX_HPF3M (((REG32(ADR_ABB_REGISTER_1)) & 0x00400000 ) >> 22) -+#define GET_RG_RX_HPF300K (((REG32(ADR_ABB_REGISTER_1)) & 0x00800000 ) >> 23) -+#define GET_RG_RX_HPFI (((REG32(ADR_ABB_REGISTER_1)) & 0x03000000 ) >> 24) -+#define GET_RG_RX_HPF_FINALCORNER (((REG32(ADR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26) -+#define GET_RG_RX_HPF_SETTLE1_C (((REG32(ADR_ABB_REGISTER_1)) & 0x30000000 ) >> 28) -+#define GET_RG_RX_HPF_SETTLE1_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000003 ) >> 0) -+#define GET_RG_RX_HPF_SETTLE2_C (((REG32(ADR_ABB_REGISTER_2)) & 0x0000000c ) >> 2) -+#define GET_RG_RX_HPF_SETTLE2_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000030 ) >> 4) -+#define GET_RG_RX_HPF_VCMCON2 (((REG32(ADR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6) -+#define GET_RG_RX_HPF_VCMCON (((REG32(ADR_ABB_REGISTER_2)) & 0x00000300 ) >> 8) -+#define GET_RG_RX_OUTVCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10) -+#define GET_RG_RX_TZI (((REG32(ADR_ABB_REGISTER_2)) & 0x00003000 ) >> 12) -+#define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_ABB_REGISTER_2)) & 0x00004000 ) >> 14) -+#define GET_RG_RX_TZ_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00018000 ) >> 15) -+#define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17) -+#define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_ABB_REGISTER_2)) & 0x00100000 ) >> 20) -+#define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00600000 ) >> 21) -+#define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_ABB_REGISTER_2)) & 0x01800000 ) >> 23) -+#define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_ABB_REGISTER_2)) & 0x02000000 ) >> 25) -+#define GET_RG_TXPGA_CAPSW (((REG32(ADR_TX_FE_REGISTER)) & 0x00000003 ) >> 0) -+#define GET_RG_TXPGA_MAIN (((REG32(ADR_TX_FE_REGISTER)) & 0x000000fc ) >> 2) -+#define GET_RG_TXPGA_STEER (((REG32(ADR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8) -+#define GET_RG_TXMOD_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14) -+#define GET_RG_TXLPF_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x00030000 ) >> 16) -+#define GET_RG_PACELL_EN (((REG32(ADR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18) -+#define GET_RG_PABIAS_CTRL (((REG32(ADR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21) -+#define GET_RG_TX_DIV_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26) -+#define GET_RG_TX_LOBUF_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x30000000 ) >> 28) -+#define GET_RG_RX_SQDC (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0) -+#define GET_RG_RX_DIV2_CORE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3) -+#define GET_RG_RX_LOBUF (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5) -+#define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7) -+#define GET_RG_TX_DPD_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11) -+#define GET_RG_TX_TSSI_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15) -+#define GET_RG_TX_TSSI_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18) -+#define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21) -+#define GET_RG_TX_TSSI_TEST (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22) -+#define GET_RG_PACASCODE_CTRL (((REG32(ADR_RX_FE_REGISTER_1)) & 0x07000000 ) >> 24) -+#define GET_RG_RX_HG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0) -+#define GET_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2) -+#define GET_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6) -+#define GET_RG_RX_HG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10) -+#define GET_RG_RX_HG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14) -+#define GET_RG_RX_HG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16) -+#define GET_RG_RX_MG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0) -+#define GET_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2) -+#define GET_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6) -+#define GET_RG_RX_MG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10) -+#define GET_RG_RX_MG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14) -+#define GET_RG_RX_MG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16) -+#define GET_RG_RX_LG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0) -+#define GET_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2) -+#define GET_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6) -+#define GET_RG_RX_LG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10) -+#define GET_RG_RX_LG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14) -+#define GET_RG_RX_LG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16) -+#define GET_RG_RX_ULG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0) -+#define GET_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2) -+#define GET_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6) -+#define GET_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10) -+#define GET_RG_RX_ULG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14) -+#define GET_RG_RX_ULG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16) -+#define GET_RG_HPF1_FAST_SET_X (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_RG_HPF1_FAST_SET_Y (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000002 ) >> 1) -+#define GET_RG_HPF1_FAST_SET_Z (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000004 ) >> 2) -+#define GET_RG_HPF_T1A (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000018 ) >> 3) -+#define GET_RG_HPF_T1B (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000060 ) >> 5) -+#define GET_RG_HPF_T1C (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000180 ) >> 7) -+#define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000600 ) >> 9) -+#define GET_RG_RX_LNA_SETTLE (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00001800 ) >> 11) -+#define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00002000 ) >> 13) -+#define GET_RG_TX_GAIN (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x003fc000 ) >> 14) -+#define GET_RG_TXGAIN_MANUAL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00400000 ) >> 22) -+#define GET_RG_TX_GAIN_OFFSET (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x07800000 ) >> 23) -+#define GET_RG_ADC_CLKSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_RG_ADC_DIBIAS (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1) -+#define GET_RG_ADC_DIVR (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3) -+#define GET_RG_ADC_DVCMI (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4) -+#define GET_RG_ADC_SAMSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6) -+#define GET_RG_ADC_STNBY (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10) -+#define GET_RG_ADC_TESTMODE (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11) -+#define GET_RG_ADC_TSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12) -+#define GET_RG_ADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16) -+#define GET_RG_DICMP (((REG32(ADR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18) -+#define GET_RG_DIOP (((REG32(ADR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20) -+#define GET_RG_SARADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00c00000 ) >> 22) -+#define GET_RG_EN_SAR_TEST (((REG32(ADR_RX_ADC_REGISTER)) & 0x03000000 ) >> 24) -+#define GET_RG_SARADC_THERMAL (((REG32(ADR_RX_ADC_REGISTER)) & 0x04000000 ) >> 26) -+#define GET_RG_SARADC_TSSI (((REG32(ADR_RX_ADC_REGISTER)) & 0x08000000 ) >> 27) -+#define GET_RG_CLK_SAR_SEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x30000000 ) >> 28) -+#define GET_RG_EN_SARADC (((REG32(ADR_RX_ADC_REGISTER)) & 0x40000000 ) >> 30) -+#define GET_RG_DACI1ST (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0) -+#define GET_RG_TX_DACLPF_ICOURSE (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2) -+#define GET_RG_TX_DACLPF_IFINE (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4) -+#define GET_RG_TX_DACLPF_VCM (((REG32(ADR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6) -+#define GET_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8) -+#define GET_RG_TX_DAC_IBIAS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9) -+#define GET_RG_TX_DAC_OS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11) -+#define GET_RG_TX_DAC_RCAL (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14) -+#define GET_RG_TX_DAC_TSEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16) -+#define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20) -+#define GET_RG_TXLPF_BYPASS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21) -+#define GET_RG_TXLPF_BOOSTI (((REG32(ADR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22) -+#define GET_RG_TX_DAC_IOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x07800000 ) >> 23) -+#define GET_RG_TX_DAC_QOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x78000000 ) >> 27) -+#define GET_RG_EN_SX_R3 (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_RG_EN_SX_CH (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000002 ) >> 1) -+#define GET_RG_EN_SX_CHP (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000004 ) >> 2) -+#define GET_RG_EN_SX_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000008 ) >> 3) -+#define GET_RG_EN_SX_VCOBF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000010 ) >> 4) -+#define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000020 ) >> 5) -+#define GET_RG_EN_SX_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000040 ) >> 6) -+#define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000100 ) >> 8) -+#define GET_RG_EN_SX_VT_MON (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000800 ) >> 11) -+#define GET_RG_EN_SX_VT_MON_DG (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00001000 ) >> 12) -+#define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00002000 ) >> 13) -+#define GET_RG_EN_SX_LPF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00004000 ) >> 14) -+#define GET_RG_EN_DPL_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00008000 ) >> 15) -+#define GET_RG_DPL_MOD_ORDER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00030000 ) >> 16) -+#define GET_RG_SX_RFCTRL_F (((REG32(ADR_SYN_REGISTER_1)) & 0x00ffffff ) >> 0) -+#define GET_RG_SX_SEL_CP (((REG32(ADR_SYN_REGISTER_1)) & 0x0f000000 ) >> 24) -+#define GET_RG_SX_SEL_CS (((REG32(ADR_SYN_REGISTER_1)) & 0xf0000000 ) >> 28) -+#define GET_RG_SX_RFCTRL_CH (((REG32(ADR_SYN_REGISTER_2)) & 0x000007ff ) >> 0) -+#define GET_RG_SX_SEL_C3 (((REG32(ADR_SYN_REGISTER_2)) & 0x00007800 ) >> 11) -+#define GET_RG_SX_SEL_RS (((REG32(ADR_SYN_REGISTER_2)) & 0x000f8000 ) >> 15) -+#define GET_RG_SX_SEL_R3 (((REG32(ADR_SYN_REGISTER_2)) & 0x01f00000 ) >> 20) -+#define GET_RG_SX_SEL_ICHP (((REG32(ADR_SYN_PFD_CHP)) & 0x0000001f ) >> 0) -+#define GET_RG_SX_SEL_PCHP (((REG32(ADR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5) -+#define GET_RG_SX_SEL_CHP_REGOP (((REG32(ADR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10) -+#define GET_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14) -+#define GET_RG_SX_CHP_IOST_POL (((REG32(ADR_SYN_PFD_CHP)) & 0x00040000 ) >> 18) -+#define GET_RG_SX_CHP_IOST (((REG32(ADR_SYN_PFD_CHP)) & 0x00380000 ) >> 19) -+#define GET_RG_SX_PFDSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x00400000 ) >> 22) -+#define GET_RG_SX_PFD_SET (((REG32(ADR_SYN_PFD_CHP)) & 0x00800000 ) >> 23) -+#define GET_RG_SX_PFD_SET1 (((REG32(ADR_SYN_PFD_CHP)) & 0x01000000 ) >> 24) -+#define GET_RG_SX_PFD_SET2 (((REG32(ADR_SYN_PFD_CHP)) & 0x02000000 ) >> 25) -+#define GET_RG_SX_VBNCAS_SEL (((REG32(ADR_SYN_PFD_CHP)) & 0x04000000 ) >> 26) -+#define GET_RG_SX_PFD_RST_H (((REG32(ADR_SYN_PFD_CHP)) & 0x08000000 ) >> 27) -+#define GET_RG_SX_PFD_TRUP (((REG32(ADR_SYN_PFD_CHP)) & 0x10000000 ) >> 28) -+#define GET_RG_SX_PFD_TRDN (((REG32(ADR_SYN_PFD_CHP)) & 0x20000000 ) >> 29) -+#define GET_RG_SX_PFD_TRSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x40000000 ) >> 30) -+#define GET_RG_SX_VCOBA_R (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0) -+#define GET_RG_SX_VCORSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3) -+#define GET_RG_SX_VCOCUSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8) -+#define GET_RG_SX_RXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12) -+#define GET_RG_SX_TXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16) -+#define GET_RG_SX_VCOBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20) -+#define GET_RG_SX_DIVBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24) -+#define GET_RG_SX_GNDR_SEL (((REG32(ADR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28) -+#define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0) -+#define GET_RG_SX_MOD_ORDER (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4) -+#define GET_RG_SX_RST_H_DIV (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9) -+#define GET_RG_SX_SDM_EDGE (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10) -+#define GET_RG_SX_XO_GM (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11) -+#define GET_RG_SX_REFBYTWO (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13) -+#define GET_RG_SX_LCKEN (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19) -+#define GET_RG_SX_PREVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20) -+#define GET_RG_SX_PSCONTERVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24) -+#define GET_RG_SX_PH (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00002000 ) >> 13) -+#define GET_RG_SX_PL (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00004000 ) >> 14) -+#define GET_RG_XOSC_CBANK_XO (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00078000 ) >> 15) -+#define GET_RG_XOSC_CBANK_XI (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00780000 ) >> 19) -+#define GET_RG_SX_VT_MON_MODE (((REG32(ADR_SYN_LCK_VT)) & 0x00000001 ) >> 0) -+#define GET_RG_SX_VT_TH_HI (((REG32(ADR_SYN_LCK_VT)) & 0x00000006 ) >> 1) -+#define GET_RG_SX_VT_TH_LO (((REG32(ADR_SYN_LCK_VT)) & 0x00000018 ) >> 3) -+#define GET_RG_SX_VT_SET (((REG32(ADR_SYN_LCK_VT)) & 0x00000020 ) >> 5) -+#define GET_RG_SX_VT_MON_TMR (((REG32(ADR_SYN_LCK_VT)) & 0x00007fc0 ) >> 6) -+#define GET_RG_EN_DP_VT_MON (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_RG_DP_VT_TH_HI (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1) -+#define GET_RG_DP_VT_TH_LO (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3) -+#define GET_RG_DP_CK320BY2 (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14) -+#define GET_RG_DP_OD_TEST (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21) -+#define GET_RG_DP_BBPLL_BP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_RG_DP_BBPLL_ICP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1) -+#define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3) -+#define GET_RG_DP_BBPLL_OD_TEST (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5) -+#define GET_RG_DP_BBPLL_PD (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9) -+#define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10) -+#define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13) -+#define GET_RG_DP_RP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15) -+#define GET_RG_DP_RHP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18) -+#define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x80000000 ) >> 31) -+#define GET_RG_DP_FODIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x0007f000 ) >> 12) -+#define GET_RG_DP_REFDIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x1fc00000 ) >> 22) -+#define GET_RG_IDACAI_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0) -+#define GET_RG_IDACAQ_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6) -+#define GET_RG_IDACAI_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12) -+#define GET_RG_IDACAQ_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18) -+#define GET_RG_DP_BBPLL_BS (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24) -+#define GET_RG_IDACAI_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0) -+#define GET_RG_IDACAQ_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6) -+#define GET_RG_IDACAI_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12) -+#define GET_RG_IDACAQ_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18) -+#define GET_RG_IDACAI_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0) -+#define GET_RG_IDACAQ_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6) -+#define GET_RG_IDACAI_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12) -+#define GET_RG_IDACAQ_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18) -+#define GET_RG_IDACAI_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0) -+#define GET_RG_IDACAQ_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6) -+#define GET_RG_IDACAI_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12) -+#define GET_RG_IDACAQ_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18) -+#define GET_RG_IDACAI_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0) -+#define GET_RG_IDACAQ_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6) -+#define GET_RG_IDACAI_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12) -+#define GET_RG_IDACAQ_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18) -+#define GET_RG_IDACAI_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0) -+#define GET_RG_IDACAQ_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6) -+#define GET_RG_IDACAI_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12) -+#define GET_RG_IDACAQ_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18) -+#define GET_RG_IDACAI_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0) -+#define GET_RG_IDACAQ_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6) -+#define GET_RG_IDACAI_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12) -+#define GET_RG_IDACAQ_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18) -+#define GET_RG_IDACAI_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0) -+#define GET_RG_IDACAQ_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6) -+#define GET_RG_IDACAI_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12) -+#define GET_RG_IDACAQ_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18) -+#define GET_RG_EN_RCAL (((REG32(ADR_RCAL_REGISTER)) & 0x00000001 ) >> 0) -+#define GET_RG_RCAL_SPD (((REG32(ADR_RCAL_REGISTER)) & 0x00000002 ) >> 1) -+#define GET_RG_RCAL_TMR (((REG32(ADR_RCAL_REGISTER)) & 0x000001fc ) >> 2) -+#define GET_RG_RCAL_CODE_CWR (((REG32(ADR_RCAL_REGISTER)) & 0x00000200 ) >> 9) -+#define GET_RG_RCAL_CODE_CWD (((REG32(ADR_RCAL_REGISTER)) & 0x00007c00 ) >> 10) -+#define GET_RG_SX_SUB_SEL_CWR (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00000001 ) >> 0) -+#define GET_RG_SX_SUB_SEL_CWD (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x000000fe ) >> 1) -+#define GET_RG_SX_LCK_BIN_OFFSET (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00078000 ) >> 15) -+#define GET_RG_SX_LCK_BIN_PRECISION (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00080000 ) >> 19) -+#define GET_RG_SX_LOCK_EN_N (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00100000 ) >> 20) -+#define GET_RG_SX_LOCK_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00200000 ) >> 21) -+#define GET_RG_SX_SUB_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00400000 ) >> 22) -+#define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x3f800000 ) >> 23) -+#define GET_RG_SX_MUX_SEL_VTH_BINL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x40000000 ) >> 30) -+#define GET_RG_TRX_DUMMMY (((REG32(ADR_TRX_DUMMY_REGISTER)) & 0xffffffff ) >> 0) -+#define GET_RG_SX_DUMMMY (((REG32(ADR_SX_DUMMY_REGISTER)) & 0xffffffff ) >> 0) -+#define GET_RCAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0) -+#define GET_LCK_BIN_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1) -+#define GET_VT_MON_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2) -+#define GET_DA_R_CODE_LUT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6) -+#define GET_AD_SX_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11) -+#define GET_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13) -+#define GET_RTC_CAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00008000 ) >> 15) -+#define GET_RG_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x003f0000 ) >> 16) -+#define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00400000 ) >> 22) -+#define GET_AD_CIRCUIT_VERSION (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x07800000 ) >> 23) -+#define GET_DA_R_CAL_CODE (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0) -+#define GET_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5) -+#define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x000007ff ) >> 0) -+#define GET_RG_RSSIADC_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x00007800 ) >> 11) -+#define GET_RG_RX_ADC_I_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x007f8000 ) >> 15) -+#define GET_RG_RX_ADC_Q_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x7f800000 ) >> 23) -+#define GET_RG_DPL_RFCTRL_F (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0x00ffffff ) >> 0) -+#define GET_RG_SX_TARGET_CNT (((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0x00001fff ) >> 0) -+#define GET_RG_RTC_OFFSET (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000000ff ) >> 0) -+#define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000fff00 ) >> 8) -+#define GET_RG_RF_D_REG (((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0x0000ffff ) >> 0) -+#define GET_DIRECT_MODE (((REG32(ADR_MMU_CTRL)) & 0x00000001 ) >> 0) -+#define GET_TAG_INTERLEAVE_MD (((REG32(ADR_MMU_CTRL)) & 0x00000002 ) >> 1) -+#define GET_DIS_DEMAND (((REG32(ADR_MMU_CTRL)) & 0x00000004 ) >> 2) -+#define GET_SAME_ID_ALLOC_MD (((REG32(ADR_MMU_CTRL)) & 0x00000008 ) >> 3) -+#define GET_HS_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000010 ) >> 4) -+#define GET_SRAM_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000020 ) >> 5) -+#define GET_NOHIT_RPASS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000040 ) >> 6) -+#define GET_DMN_FLAG_CLR (((REG32(ADR_MMU_CTRL)) & 0x00000080 ) >> 7) -+#define GET_ERR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000100 ) >> 8) -+#define GET_ALR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000200 ) >> 9) -+#define GET_MCH_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000400 ) >> 10) -+#define GET_TAG_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000800 ) >> 11) -+#define GET_ABT_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00001000 ) >> 12) -+#define GET_MMU_VER (((REG32(ADR_MMU_CTRL)) & 0x0000e000 ) >> 13) -+#define GET_MMU_SHARE_MCU (((REG32(ADR_MMU_CTRL)) & 0x00ff0000 ) >> 16) -+#define GET_HS_WR (((REG32(ADR_HS_CTRL)) & 0x00000001 ) >> 0) -+#define GET_HS_FLAG (((REG32(ADR_HS_CTRL)) & 0x00000010 ) >> 4) -+#define GET_HS_ID (((REG32(ADR_HS_CTRL)) & 0x00007f00 ) >> 8) -+#define GET_HS_CHANNEL (((REG32(ADR_HS_CTRL)) & 0x000f0000 ) >> 16) -+#define GET_HS_PAGE (((REG32(ADR_HS_CTRL)) & 0x00f00000 ) >> 20) -+#define GET_HS_DATA (((REG32(ADR_HS_CTRL)) & 0xff000000 ) >> 24) -+#define GET_CPU_POR0 (((REG32(ADR_CPU_POR0_7)) & 0x0000000f ) >> 0) -+#define GET_CPU_POR1 (((REG32(ADR_CPU_POR0_7)) & 0x000000f0 ) >> 4) -+#define GET_CPU_POR2 (((REG32(ADR_CPU_POR0_7)) & 0x00000f00 ) >> 8) -+#define GET_CPU_POR3 (((REG32(ADR_CPU_POR0_7)) & 0x0000f000 ) >> 12) -+#define GET_CPU_POR4 (((REG32(ADR_CPU_POR0_7)) & 0x000f0000 ) >> 16) -+#define GET_CPU_POR5 (((REG32(ADR_CPU_POR0_7)) & 0x00f00000 ) >> 20) -+#define GET_CPU_POR6 (((REG32(ADR_CPU_POR0_7)) & 0x0f000000 ) >> 24) -+#define GET_CPU_POR7 (((REG32(ADR_CPU_POR0_7)) & 0xf0000000 ) >> 28) -+#define GET_CPU_POR8 (((REG32(ADR_CPU_POR8_F)) & 0x0000000f ) >> 0) -+#define GET_CPU_POR9 (((REG32(ADR_CPU_POR8_F)) & 0x000000f0 ) >> 4) -+#define GET_CPU_PORA (((REG32(ADR_CPU_POR8_F)) & 0x00000f00 ) >> 8) -+#define GET_CPU_PORB (((REG32(ADR_CPU_POR8_F)) & 0x0000f000 ) >> 12) -+#define GET_CPU_PORC (((REG32(ADR_CPU_POR8_F)) & 0x000f0000 ) >> 16) -+#define GET_CPU_PORD (((REG32(ADR_CPU_POR8_F)) & 0x00f00000 ) >> 20) -+#define GET_CPU_PORE (((REG32(ADR_CPU_POR8_F)) & 0x0f000000 ) >> 24) -+#define GET_CPU_PORF (((REG32(ADR_CPU_POR8_F)) & 0xf0000000 ) >> 28) -+#define GET_ACC_WR_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x0000003f ) >> 0) -+#define GET_ACC_RD_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x00003f00 ) >> 8) -+#define GET_REQ_NACK_CLR (((REG32(ADR_REG_LEN_CTRL)) & 0x00008000 ) >> 15) -+#define GET_NACK_FLAG_BUS (((REG32(ADR_REG_LEN_CTRL)) & 0xffff0000 ) >> 16) -+#define GET_DMN_R_PASS (((REG32(ADR_DMN_READ_BYPASS)) & 0x0000ffff ) >> 0) -+#define GET_PARA_ALC_RLS (((REG32(ADR_DMN_READ_BYPASS)) & 0x00010000 ) >> 16) -+#define GET_REQ_PORNS_CHGEN (((REG32(ADR_DMN_READ_BYPASS)) & 0x01000000 ) >> 24) -+#define GET_ALC_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x0000007f ) >> 0) -+#define GET_ALC_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x00008000 ) >> 15) -+#define GET_RLS_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x007f0000 ) >> 16) -+#define GET_RLS_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x80000000 ) >> 31) -+#define GET_DEBUG_CTL (((REG32(ADR_DEBUG_CTL)) & 0x000000ff ) >> 0) -+#define GET_DEBUG_H16 (((REG32(ADR_DEBUG_CTL)) & 0x00000100 ) >> 8) -+#define GET_DEBUG_OUT (((REG32(ADR_DEBUG_OUT)) & 0xffffffff ) >> 0) -+#define GET_ALC_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000001 ) >> 0) -+#define GET_RLS_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000002 ) >> 1) -+#define GET_AL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00000700 ) >> 8) -+#define GET_RL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00007000 ) >> 12) -+#define GET_ALC_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x007f0000 ) >> 16) -+#define GET_RLS_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x7f000000 ) >> 24) -+#define GET_DMN_NOHIT_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0) -+#define GET_DMN_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1) -+#define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000008 ) >> 3) -+#define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4) -+#define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8) -+#define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0xffff0000 ) >> 16) -+#define GET_TX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x000000ff ) >> 0) -+#define GET_RX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x0000ff00 ) >> 8) -+#define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x01ff0000 ) >> 16) -+#define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x80000000 ) >> 31) -+#define GET_DMN_NOHIT_MCU (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000001 ) >> 0) -+#define GET_DMN_MCU_FLAG (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000002 ) >> 1) -+#define GET_DMN_MCU_WR (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000008 ) >> 3) -+#define GET_DMN_MCU_PORT (((REG32(ADR_DMN_MCU_STATUS)) & 0x000000f0 ) >> 4) -+#define GET_DMN_MCU_ID (((REG32(ADR_DMN_MCU_STATUS)) & 0x00007f00 ) >> 8) -+#define GET_DMN_MCU_ADDR (((REG32(ADR_DMN_MCU_STATUS)) & 0xffff0000 ) >> 16) -+#define GET_MB_IDTBL_31_0 (((REG32(ADR_MB_IDTBL_0_STATUS)) & 0xffffffff ) >> 0) -+#define GET_MB_IDTBL_63_32 (((REG32(ADR_MB_IDTBL_1_STATUS)) & 0xffffffff ) >> 0) -+#define GET_MB_IDTBL_95_64 (((REG32(ADR_MB_IDTBL_2_STATUS)) & 0xffffffff ) >> 0) -+#define GET_MB_IDTBL_127_96 (((REG32(ADR_MB_IDTBL_3_STATUS)) & 0xffffffff ) >> 0) -+#define GET_PKT_IDTBL_31_0 (((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0xffffffff ) >> 0) -+#define GET_PKT_IDTBL_63_32 (((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0xffffffff ) >> 0) -+#define GET_PKT_IDTBL_95_64 (((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0xffffffff ) >> 0) -+#define GET_PKT_IDTBL_127_96 (((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0xffffffff ) >> 0) -+#define GET_DMN_IDTBL_31_0 (((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0xffffffff ) >> 0) -+#define GET_DMN_IDTBL_63_32 (((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0xffffffff ) >> 0) -+#define GET_DMN_IDTBL_95_64 (((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0xffffffff ) >> 0) -+#define GET_DMN_IDTBL_127_96 (((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0xffffffff ) >> 0) -+#define GET_NEQ_MB_ID_31_0 (((REG32(ADR_MB_NEQID_0_STATUS)) & 0xffffffff ) >> 0) -+#define GET_NEQ_MB_ID_63_32 (((REG32(ADR_MB_NEQID_1_STATUS)) & 0xffffffff ) >> 0) -+#define GET_NEQ_MB_ID_95_64 (((REG32(ADR_MB_NEQID_2_STATUS)) & 0xffffffff ) >> 0) -+#define GET_NEQ_MB_ID_127_96 (((REG32(ADR_MB_NEQID_3_STATUS)) & 0xffffffff ) >> 0) -+#define GET_NEQ_PKT_ID_31_0 (((REG32(ADR_PKT_NEQID_0_STATUS)) & 0xffffffff ) >> 0) -+#define GET_NEQ_PKT_ID_63_32 (((REG32(ADR_PKT_NEQID_1_STATUS)) & 0xffffffff ) >> 0) -+#define GET_NEQ_PKT_ID_95_64 (((REG32(ADR_PKT_NEQID_2_STATUS)) & 0xffffffff ) >> 0) -+#define GET_NEQ_PKT_ID_127_96 (((REG32(ADR_PKT_NEQID_3_STATUS)) & 0xffffffff ) >> 0) -+#define GET_ALC_NOCHG_ID (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x0000007f ) >> 0) -+#define GET_ALC_NOCHG_INT (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00008000 ) >> 15) -+#define GET_NEQ_PKT_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00010000 ) >> 16) -+#define GET_NEQ_MB_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x01000000 ) >> 24) -+#define GET_SRAM_TAG_0 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff ) >> 0) -+#define GET_SRAM_TAG_1 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000 ) >> 16) -+#define GET_SRAM_TAG_2 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff ) >> 0) -+#define GET_SRAM_TAG_3 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000 ) >> 16) -+#define GET_SRAM_TAG_4 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff ) >> 0) -+#define GET_SRAM_TAG_5 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000 ) >> 16) -+#define GET_SRAM_TAG_6 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff ) >> 0) -+#define GET_SRAM_TAG_7 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000 ) >> 16) -+#define GET_SRAM_TAG_8 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff ) >> 0) -+#define GET_SRAM_TAG_9 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000 ) >> 16) -+#define GET_SRAM_TAG_10 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff ) >> 0) -+#define GET_SRAM_TAG_11 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000 ) >> 16) -+#define GET_SRAM_TAG_12 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff ) >> 0) -+#define GET_SRAM_TAG_13 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000 ) >> 16) -+#define GET_SRAM_TAG_14 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff ) >> 0) -+#define GET_SRAM_TAG_15 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000 ) >> 16) -+#define SET_MCU_ENABLE(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 0) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffe)) -+#define SET_MAC_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 1) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffd)) -+#define SET_MCU_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 2) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffb)) -+#define SET_SDIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 3) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffff7)) -+#define SET_SPI_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 4) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffef)) -+#define SET_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 5) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffdf)) -+#define SET_DMA_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 6) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffbf)) -+#define SET_WDT_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 7) | ((REG32(ADR_BRG_SW_RST)) & 0xffffff7f)) -+#define SET_I2C_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 8) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffeff)) -+#define SET_INT_CTL_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 9) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffdff)) -+#define SET_BTCX_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 10) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffbff)) -+#define SET_GPIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 11) | ((REG32(ADR_BRG_SW_RST)) & 0xfffff7ff)) -+#define SET_US0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 12) | ((REG32(ADR_BRG_SW_RST)) & 0xffffefff)) -+#define SET_US1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 13) | ((REG32(ADR_BRG_SW_RST)) & 0xffffdfff)) -+#define SET_US2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 14) | ((REG32(ADR_BRG_SW_RST)) & 0xffffbfff)) -+#define SET_US3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 15) | ((REG32(ADR_BRG_SW_RST)) & 0xffff7fff)) -+#define SET_MS0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 16) | ((REG32(ADR_BRG_SW_RST)) & 0xfffeffff)) -+#define SET_MS1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 17) | ((REG32(ADR_BRG_SW_RST)) & 0xfffdffff)) -+#define SET_MS2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 18) | ((REG32(ADR_BRG_SW_RST)) & 0xfffbffff)) -+#define SET_MS3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 19) | ((REG32(ADR_BRG_SW_RST)) & 0xfff7ffff)) -+#define SET_RF_BB_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 20) | ((REG32(ADR_BRG_SW_RST)) & 0xffefffff)) -+#define SET_SYS_ALL_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 21) | ((REG32(ADR_BRG_SW_RST)) & 0xffdfffff)) -+#define SET_DAT_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 22) | ((REG32(ADR_BRG_SW_RST)) & 0xffbfffff)) -+#define SET_I2C_MST_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 23) | ((REG32(ADR_BRG_SW_RST)) & 0xff7fffff)) -+#define SET_RG_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT)) & 0xfffffffe)) -+#define SET_TRAP_IMG_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 16) | ((REG32(ADR_BOOT)) & 0xfffeffff)) -+#define SET_TRAP_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 17) | ((REG32(ADR_BOOT)) & 0xfffdffff)) -+#define SET_TRAP_BOOT_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 18) | ((REG32(ADR_BOOT)) & 0xfffbffff)) -+#define SET_CHIP_ID_31_0(_VAL_) (REG32(ADR_CHIP_ID_0)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_0)) & 0x00000000)) -+#define SET_CHIP_ID_63_32(_VAL_) (REG32(ADR_CHIP_ID_1)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_1)) & 0x00000000)) -+#define SET_CHIP_ID_95_64(_VAL_) (REG32(ADR_CHIP_ID_2)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_2)) & 0x00000000)) -+#define SET_CHIP_ID_127_96(_VAL_) (REG32(ADR_CHIP_ID_3)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_3)) & 0x00000000)) -+#define SET_CK_SEL_1_0(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 0) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffc)) -+#define SET_CK_SEL_2(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 2) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffb)) -+#define SET_SYS_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffe)) -+#define SET_MAC_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffd)) -+#define SET_MCU_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 2) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffb)) -+#define SET_SDIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffff7)) -+#define SET_SPI_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffef)) -+#define SET_UART_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffdf)) -+#define SET_DMA_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffbf)) -+#define SET_WDT_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffff7f)) -+#define SET_I2C_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 8) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffeff)) -+#define SET_INT_CTL_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffdff)) -+#define SET_BTCX_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffbff)) -+#define SET_GPIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffff7ff)) -+#define SET_US0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffefff)) -+#define SET_US1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffdfff)) -+#define SET_US2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffbfff)) -+#define SET_US3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffff7fff)) -+#define SET_MS0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 16) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffeffff)) -+#define SET_MS1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 17) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffdffff)) -+#define SET_MS2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 18) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffbffff)) -+#define SET_MS3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 19) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfff7ffff)) -+#define SET_BIST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 20) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffefffff)) -+#define SET_I2C_MST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 23) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xff7fffff)) -+#define SET_BTCX_CSR_CLK_EN(_VAL_) (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0xfffffbff)) -+#define SET_MCU_DBG_SEL(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_SEL)) & 0xffffffc0)) -+#define SET_MCU_STOP_NOGRANT(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffeff)) -+#define SET_MCU_STOP_ANYTIME(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffdff)) -+#define SET_MCU_DBG_DATA(_VAL_) (REG32(ADR_MCU_DBG_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_DATA)) & 0x00000000)) -+#define SET_AHB_SW_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffe)) -+#define SET_AHB_ERR_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffd)) -+#define SET_REG_AHB_DEBUG_MX(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffffcf)) -+#define SET_REG_PKT_W_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffeff)) -+#define SET_REG_PKT_R_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffdff)) -+#define SET_IQ_SRAM_SEL_0(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffefff)) -+#define SET_IQ_SRAM_SEL_1(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffdfff)) -+#define SET_IQ_SRAM_SEL_2(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffbfff)) -+#define SET_AHB_STATUS(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_AHB_BRG_STATUS)) & 0x0000ffff)) -+#define SET_PARALLEL_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffffe)) -+#define SET_MBRUN(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xffffffef)) -+#define SET_SHIFT_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffeff)) -+#define SET_MODE_REG_SI(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffdff)) -+#define SET_SIMULATION_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffbff)) -+#define SET_DBIST_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffff7ff)) -+#define SET_MODE_REG_IN(_VAL_) (REG32(ADR_BIST_MODE_REG_IN)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN)) & 0xffe00000)) -+#define SET_MODE_REG_OUT_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0xffe00000)) -+#define SET_MODE_REG_SO_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0x7fffffff)) -+#define SET_MONITOR_BUS_MCU_31_0(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0x00000000)) -+#define SET_MONITOR_BUS_MCU_33_32(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0xfffffffc)) -+#define SET_TB_ADR_SEL(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_TB_ADR_SEL)) & 0xffff0000)) -+#define SET_TB_CS(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 31) | ((REG32(ADR_TB_ADR_SEL)) & 0x7fffffff)) -+#define SET_TB_RDATA(_VAL_) (REG32(ADR_TB_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_TB_RDATA)) & 0x00000000)) -+#define SET_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 0) | ((REG32(ADR_UART_W2B)) & 0xfffffffe)) -+#define SET_DATA_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 4) | ((REG32(ADR_UART_W2B)) & 0xffffffef)) -+#define SET_AHB_ILL_ADDR(_VAL_) (REG32(ADR_AHB_ILL_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILL_ADDR)) & 0x00000000)) -+#define SET_AHB_FEN_ADDR(_VAL_) (REG32(ADR_AHB_FEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_FEN_ADDR)) & 0x00000000)) -+#define SET_ILL_ADDR_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffe)) -+#define SET_FENCE_HIT_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffd)) -+#define SET_ILL_ADDR_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffef)) -+#define SET_FENCE_HIT_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffdf)) -+#define SET_PWM_INI_VALUE_P_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_A)) & 0xffffff00)) -+#define SET_PWM_INI_VALUE_N_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_A)) & 0xffff00ff)) -+#define SET_PWM_POST_SCALER_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_A)) & 0xfff0ffff)) -+#define SET_PWM_ALWAYSON_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_A)) & 0xdfffffff)) -+#define SET_PWM_INVERT_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_A)) & 0xbfffffff)) -+#define SET_PWM_ENABLE_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_A)) & 0x7fffffff)) -+#define SET_PWM_INI_VALUE_P_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_B)) & 0xffffff00)) -+#define SET_PWM_INI_VALUE_N_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_B)) & 0xffff00ff)) -+#define SET_PWM_POST_SCALER_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_B)) & 0xfff0ffff)) -+#define SET_PWM_ALWAYSON_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_B)) & 0xdfffffff)) -+#define SET_PWM_INVERT_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_B)) & 0xbfffffff)) -+#define SET_PWM_ENABLE_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_B)) & 0x7fffffff)) -+#define SET_HBUSREQ_LOCK(_VAL_) (REG32(ADR_HBUSREQ_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBUSREQ_LOCK)) & 0xffffe000)) -+#define SET_HBURST_LOCK(_VAL_) (REG32(ADR_HBURST_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBURST_LOCK)) & 0xffffe000)) -+#define SET_PRESCALER_USTIMER(_VAL_) (REG32(ADR_PRESCALER_USTIMER)) = (((_VAL_) << 0) | ((REG32(ADR_PRESCALER_USTIMER)) & 0xfffffe00)) -+#define SET_MODE_REG_IN_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0xffff0000)) -+#define SET_MODE_REG_OUT_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0xffff0000)) -+#define SET_MODE_REG_SO_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x7fffffff)) -+#define SET_MONITOR_BUS_MMU(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0xfff80000)) -+#define SET_TEST_MODE0(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_TEST_MODE)) & 0xfffffffe)) -+#define SET_TEST_MODE1(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_TEST_MODE)) & 0xfffffffd)) -+#define SET_TEST_MODE2(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_TEST_MODE)) & 0xfffffffb)) -+#define SET_TEST_MODE3(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_TEST_MODE)) & 0xfffffff7)) -+#define SET_TEST_MODE4(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_TEST_MODE)) & 0xffffffef)) -+#define SET_TEST_MODE_ALL(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_TEST_MODE)) & 0xffffffdf)) -+#define SET_WDT_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffe)) -+#define SET_SD_HOST_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffd)) -+#define SET_ALLOW_SD_RESET(_VAL_) (REG32(ADR_SD_INIT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_SD_INIT_CFG)) & 0xfffffffe)) -+#define SET_UART_NRTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffe)) -+#define SET_UART_NCTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffd)) -+#define SET_TU0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xffff0000)) -+#define SET_TU0_TM_MODE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffeffff)) -+#define SET_TU0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffdffff)) -+#define SET_TU0_TM_INT_MASK(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffbffff)) -+#define SET_TU0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000)) -+#define SET_TU1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xffff0000)) -+#define SET_TU1_TM_MODE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffeffff)) -+#define SET_TU1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffdffff)) -+#define SET_TU1_TM_INT_MASK(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffbffff)) -+#define SET_TU1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000)) -+#define SET_TU2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xffff0000)) -+#define SET_TU2_TM_MODE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffeffff)) -+#define SET_TU2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffdffff)) -+#define SET_TU2_TM_INT_MASK(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffbffff)) -+#define SET_TU2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000)) -+#define SET_TU3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xffff0000)) -+#define SET_TU3_TM_MODE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffeffff)) -+#define SET_TU3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffdffff)) -+#define SET_TU3_TM_INT_MASK(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffbffff)) -+#define SET_TU3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000)) -+#define SET_TM0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xffff0000)) -+#define SET_TM0_TM_MODE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffeffff)) -+#define SET_TM0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffdffff)) -+#define SET_TM0_TM_INT_MASK(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffbffff)) -+#define SET_TM0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000)) -+#define SET_TM1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xffff0000)) -+#define SET_TM1_TM_MODE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffeffff)) -+#define SET_TM1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffdffff)) -+#define SET_TM1_TM_INT_MASK(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffbffff)) -+#define SET_TM1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000)) -+#define SET_TM2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xffff0000)) -+#define SET_TM2_TM_MODE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffeffff)) -+#define SET_TM2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffdffff)) -+#define SET_TM2_TM_INT_MASK(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffbffff)) -+#define SET_TM2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000)) -+#define SET_TM3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xffff0000)) -+#define SET_TM3_TM_MODE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffeffff)) -+#define SET_TM3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffdffff)) -+#define SET_TM3_TM_INT_MASK(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffbffff)) -+#define SET_TM3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000)) -+#define SET_MCU_WDT_TIME_CNT(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_WDOG_REG)) & 0xffff0000)) -+#define SET_MCU_WDT_STATUS(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_MCU_WDOG_REG)) & 0xfffdffff)) -+#define SET_MCU_WDOG_ENA(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_MCU_WDOG_REG)) & 0x7fffffff)) -+#define SET_SYS_WDT_TIME_CNT(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_WDOG_REG)) & 0xffff0000)) -+#define SET_SYS_WDT_STATUS(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYS_WDOG_REG)) & 0xfffdffff)) -+#define SET_SYS_WDOG_ENA(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYS_WDOG_REG)) & 0x7fffffff)) -+#define SET_XLNA_EN_O_OE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 0) | ((REG32(ADR_PAD6)) & 0xfffffffe)) -+#define SET_XLNA_EN_O_PE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 1) | ((REG32(ADR_PAD6)) & 0xfffffffd)) -+#define SET_PAD6_IE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 3) | ((REG32(ADR_PAD6)) & 0xfffffff7)) -+#define SET_PAD6_SEL_I(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 4) | ((REG32(ADR_PAD6)) & 0xffffffcf)) -+#define SET_PAD6_OD(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 8) | ((REG32(ADR_PAD6)) & 0xfffffeff)) -+#define SET_PAD6_SEL_O(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 12) | ((REG32(ADR_PAD6)) & 0xffffefff)) -+#define SET_XLNA_EN_O_C(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 28) | ((REG32(ADR_PAD6)) & 0xefffffff)) -+#define SET_WIFI_TX_SW_O_OE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 0) | ((REG32(ADR_PAD7)) & 0xfffffffe)) -+#define SET_WIFI_TX_SW_O_PE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 1) | ((REG32(ADR_PAD7)) & 0xfffffffd)) -+#define SET_PAD7_IE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 3) | ((REG32(ADR_PAD7)) & 0xfffffff7)) -+#define SET_PAD7_SEL_I(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 4) | ((REG32(ADR_PAD7)) & 0xffffffcf)) -+#define SET_PAD7_OD(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 8) | ((REG32(ADR_PAD7)) & 0xfffffeff)) -+#define SET_PAD7_SEL_O(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 12) | ((REG32(ADR_PAD7)) & 0xffffefff)) -+#define SET_WIFI_TX_SW_O_C(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 28) | ((REG32(ADR_PAD7)) & 0xefffffff)) -+#define SET_WIFI_RX_SW_O_OE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 0) | ((REG32(ADR_PAD8)) & 0xfffffffe)) -+#define SET_WIFI_RX_SW_O_PE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 1) | ((REG32(ADR_PAD8)) & 0xfffffffd)) -+#define SET_PAD8_IE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 3) | ((REG32(ADR_PAD8)) & 0xfffffff7)) -+#define SET_PAD8_SEL_I(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 4) | ((REG32(ADR_PAD8)) & 0xffffffcf)) -+#define SET_PAD8_OD(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 8) | ((REG32(ADR_PAD8)) & 0xfffffeff)) -+#define SET_WIFI_RX_SW_O_C(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 28) | ((REG32(ADR_PAD8)) & 0xefffffff)) -+#define SET_BT_SW_O_OE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 0) | ((REG32(ADR_PAD9)) & 0xfffffffe)) -+#define SET_BT_SW_O_PE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 1) | ((REG32(ADR_PAD9)) & 0xfffffffd)) -+#define SET_PAD9_IE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 3) | ((REG32(ADR_PAD9)) & 0xfffffff7)) -+#define SET_PAD9_SEL_I(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 4) | ((REG32(ADR_PAD9)) & 0xffffffcf)) -+#define SET_PAD9_OD(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 8) | ((REG32(ADR_PAD9)) & 0xfffffeff)) -+#define SET_PAD9_SEL_O(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 12) | ((REG32(ADR_PAD9)) & 0xffffefff)) -+#define SET_BT_SW_O_C(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 28) | ((REG32(ADR_PAD9)) & 0xefffffff)) -+#define SET_XPA_EN_O_OE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 0) | ((REG32(ADR_PAD11)) & 0xfffffffe)) -+#define SET_XPA_EN_O_PE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 1) | ((REG32(ADR_PAD11)) & 0xfffffffd)) -+#define SET_PAD11_IE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 3) | ((REG32(ADR_PAD11)) & 0xfffffff7)) -+#define SET_PAD11_SEL_I(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 4) | ((REG32(ADR_PAD11)) & 0xffffffcf)) -+#define SET_PAD11_OD(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 8) | ((REG32(ADR_PAD11)) & 0xfffffeff)) -+#define SET_PAD11_SEL_O(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 12) | ((REG32(ADR_PAD11)) & 0xffffefff)) -+#define SET_XPA_EN_O_C(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 28) | ((REG32(ADR_PAD11)) & 0xefffffff)) -+#define SET_PAD15_OE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 0) | ((REG32(ADR_PAD15)) & 0xfffffffe)) -+#define SET_PAD15_PE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 1) | ((REG32(ADR_PAD15)) & 0xfffffffd)) -+#define SET_PAD15_DS(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 2) | ((REG32(ADR_PAD15)) & 0xfffffffb)) -+#define SET_PAD15_IE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 3) | ((REG32(ADR_PAD15)) & 0xfffffff7)) -+#define SET_PAD15_SEL_I(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 4) | ((REG32(ADR_PAD15)) & 0xffffffcf)) -+#define SET_PAD15_OD(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 8) | ((REG32(ADR_PAD15)) & 0xfffffeff)) -+#define SET_PAD15_SEL_O(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 12) | ((REG32(ADR_PAD15)) & 0xffffefff)) -+#define SET_TEST_1_ID(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 28) | ((REG32(ADR_PAD15)) & 0xefffffff)) -+#define SET_PAD16_OE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 0) | ((REG32(ADR_PAD16)) & 0xfffffffe)) -+#define SET_PAD16_PE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 1) | ((REG32(ADR_PAD16)) & 0xfffffffd)) -+#define SET_PAD16_DS(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 2) | ((REG32(ADR_PAD16)) & 0xfffffffb)) -+#define SET_PAD16_IE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 3) | ((REG32(ADR_PAD16)) & 0xfffffff7)) -+#define SET_PAD16_SEL_I(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 4) | ((REG32(ADR_PAD16)) & 0xffffffcf)) -+#define SET_PAD16_OD(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 8) | ((REG32(ADR_PAD16)) & 0xfffffeff)) -+#define SET_PAD16_SEL_O(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 12) | ((REG32(ADR_PAD16)) & 0xffffefff)) -+#define SET_TEST_2_ID(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 28) | ((REG32(ADR_PAD16)) & 0xefffffff)) -+#define SET_PAD17_OE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 0) | ((REG32(ADR_PAD17)) & 0xfffffffe)) -+#define SET_PAD17_PE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 1) | ((REG32(ADR_PAD17)) & 0xfffffffd)) -+#define SET_PAD17_DS(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 2) | ((REG32(ADR_PAD17)) & 0xfffffffb)) -+#define SET_PAD17_IE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 3) | ((REG32(ADR_PAD17)) & 0xfffffff7)) -+#define SET_PAD17_SEL_I(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 4) | ((REG32(ADR_PAD17)) & 0xffffffcf)) -+#define SET_PAD17_OD(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 8) | ((REG32(ADR_PAD17)) & 0xfffffeff)) -+#define SET_PAD17_SEL_O(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 12) | ((REG32(ADR_PAD17)) & 0xffffefff)) -+#define SET_TEST_3_ID(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 28) | ((REG32(ADR_PAD17)) & 0xefffffff)) -+#define SET_PAD18_OE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 0) | ((REG32(ADR_PAD18)) & 0xfffffffe)) -+#define SET_PAD18_PE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 1) | ((REG32(ADR_PAD18)) & 0xfffffffd)) -+#define SET_PAD18_DS(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 2) | ((REG32(ADR_PAD18)) & 0xfffffffb)) -+#define SET_PAD18_IE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 3) | ((REG32(ADR_PAD18)) & 0xfffffff7)) -+#define SET_PAD18_SEL_I(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 4) | ((REG32(ADR_PAD18)) & 0xffffffcf)) -+#define SET_PAD18_OD(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 8) | ((REG32(ADR_PAD18)) & 0xfffffeff)) -+#define SET_PAD18_SEL_O(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 12) | ((REG32(ADR_PAD18)) & 0xffffcfff)) -+#define SET_TEST_4_ID(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 28) | ((REG32(ADR_PAD18)) & 0xefffffff)) -+#define SET_PAD19_OE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 0) | ((REG32(ADR_PAD19)) & 0xfffffffe)) -+#define SET_PAD19_PE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 1) | ((REG32(ADR_PAD19)) & 0xfffffffd)) -+#define SET_PAD19_DS(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 2) | ((REG32(ADR_PAD19)) & 0xfffffffb)) -+#define SET_PAD19_IE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 3) | ((REG32(ADR_PAD19)) & 0xfffffff7)) -+#define SET_PAD19_SEL_I(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 4) | ((REG32(ADR_PAD19)) & 0xffffffcf)) -+#define SET_PAD19_OD(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 8) | ((REG32(ADR_PAD19)) & 0xfffffeff)) -+#define SET_PAD19_SEL_O(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 12) | ((REG32(ADR_PAD19)) & 0xffff8fff)) -+#define SET_SHORT_TO_20_ID(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 28) | ((REG32(ADR_PAD19)) & 0xefffffff)) -+#define SET_PAD20_OE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 0) | ((REG32(ADR_PAD20)) & 0xfffffffe)) -+#define SET_PAD20_PE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 1) | ((REG32(ADR_PAD20)) & 0xfffffffd)) -+#define SET_PAD20_DS(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 2) | ((REG32(ADR_PAD20)) & 0xfffffffb)) -+#define SET_PAD20_IE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 3) | ((REG32(ADR_PAD20)) & 0xfffffff7)) -+#define SET_PAD20_SEL_I(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 4) | ((REG32(ADR_PAD20)) & 0xffffff0f)) -+#define SET_PAD20_OD(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 8) | ((REG32(ADR_PAD20)) & 0xfffffeff)) -+#define SET_PAD20_SEL_O(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 12) | ((REG32(ADR_PAD20)) & 0xffffcfff)) -+#define SET_STRAP0(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 27) | ((REG32(ADR_PAD20)) & 0xf7ffffff)) -+#define SET_GPIO_TEST_1_ID(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 28) | ((REG32(ADR_PAD20)) & 0xefffffff)) -+#define SET_PAD21_OE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 0) | ((REG32(ADR_PAD21)) & 0xfffffffe)) -+#define SET_PAD21_PE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 1) | ((REG32(ADR_PAD21)) & 0xfffffffd)) -+#define SET_PAD21_DS(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 2) | ((REG32(ADR_PAD21)) & 0xfffffffb)) -+#define SET_PAD21_IE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 3) | ((REG32(ADR_PAD21)) & 0xfffffff7)) -+#define SET_PAD21_SEL_I(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 4) | ((REG32(ADR_PAD21)) & 0xffffff8f)) -+#define SET_PAD21_OD(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 8) | ((REG32(ADR_PAD21)) & 0xfffffeff)) -+#define SET_PAD21_SEL_O(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 12) | ((REG32(ADR_PAD21)) & 0xffffcfff)) -+#define SET_STRAP3(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 27) | ((REG32(ADR_PAD21)) & 0xf7ffffff)) -+#define SET_GPIO_TEST_2_ID(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 28) | ((REG32(ADR_PAD21)) & 0xefffffff)) -+#define SET_PAD22_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 0) | ((REG32(ADR_PAD22)) & 0xfffffffe)) -+#define SET_PAD22_PE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 1) | ((REG32(ADR_PAD22)) & 0xfffffffd)) -+#define SET_PAD22_DS(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 2) | ((REG32(ADR_PAD22)) & 0xfffffffb)) -+#define SET_PAD22_IE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 3) | ((REG32(ADR_PAD22)) & 0xfffffff7)) -+#define SET_PAD22_SEL_I(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 4) | ((REG32(ADR_PAD22)) & 0xffffff8f)) -+#define SET_PAD22_OD(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 8) | ((REG32(ADR_PAD22)) & 0xfffffeff)) -+#define SET_PAD22_SEL_O(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 12) | ((REG32(ADR_PAD22)) & 0xffff8fff)) -+#define SET_PAD22_SEL_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 20) | ((REG32(ADR_PAD22)) & 0xffefffff)) -+#define SET_GPIO_TEST_3_ID(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 28) | ((REG32(ADR_PAD22)) & 0xefffffff)) -+#define SET_PAD24_OE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 0) | ((REG32(ADR_PAD24)) & 0xfffffffe)) -+#define SET_PAD24_PE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 1) | ((REG32(ADR_PAD24)) & 0xfffffffd)) -+#define SET_PAD24_DS(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 2) | ((REG32(ADR_PAD24)) & 0xfffffffb)) -+#define SET_PAD24_IE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 3) | ((REG32(ADR_PAD24)) & 0xfffffff7)) -+#define SET_PAD24_SEL_I(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 4) | ((REG32(ADR_PAD24)) & 0xffffffcf)) -+#define SET_PAD24_OD(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 8) | ((REG32(ADR_PAD24)) & 0xfffffeff)) -+#define SET_PAD24_SEL_O(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 12) | ((REG32(ADR_PAD24)) & 0xffff8fff)) -+#define SET_GPIO_TEST_4_ID(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 28) | ((REG32(ADR_PAD24)) & 0xefffffff)) -+#define SET_PAD25_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 0) | ((REG32(ADR_PAD25)) & 0xfffffffe)) -+#define SET_PAD25_PE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 1) | ((REG32(ADR_PAD25)) & 0xfffffffd)) -+#define SET_PAD25_DS(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 2) | ((REG32(ADR_PAD25)) & 0xfffffffb)) -+#define SET_PAD25_IE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 3) | ((REG32(ADR_PAD25)) & 0xfffffff7)) -+#define SET_PAD25_SEL_I(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 4) | ((REG32(ADR_PAD25)) & 0xffffff8f)) -+#define SET_PAD25_OD(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 8) | ((REG32(ADR_PAD25)) & 0xfffffeff)) -+#define SET_PAD25_SEL_O(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 12) | ((REG32(ADR_PAD25)) & 0xffff8fff)) -+#define SET_PAD25_SEL_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 20) | ((REG32(ADR_PAD25)) & 0xffefffff)) -+#define SET_STRAP1(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 27) | ((REG32(ADR_PAD25)) & 0xf7ffffff)) -+#define SET_GPIO_1_ID(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 28) | ((REG32(ADR_PAD25)) & 0xefffffff)) -+#define SET_PAD27_OE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 0) | ((REG32(ADR_PAD27)) & 0xfffffffe)) -+#define SET_PAD27_PE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 1) | ((REG32(ADR_PAD27)) & 0xfffffffd)) -+#define SET_PAD27_DS(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 2) | ((REG32(ADR_PAD27)) & 0xfffffffb)) -+#define SET_PAD27_IE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 3) | ((REG32(ADR_PAD27)) & 0xfffffff7)) -+#define SET_PAD27_SEL_I(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 4) | ((REG32(ADR_PAD27)) & 0xffffff8f)) -+#define SET_PAD27_OD(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 8) | ((REG32(ADR_PAD27)) & 0xfffffeff)) -+#define SET_PAD27_SEL_O(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 12) | ((REG32(ADR_PAD27)) & 0xffff8fff)) -+#define SET_GPIO_2_ID(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 28) | ((REG32(ADR_PAD27)) & 0xefffffff)) -+#define SET_PAD28_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 0) | ((REG32(ADR_PAD28)) & 0xfffffffe)) -+#define SET_PAD28_PE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 1) | ((REG32(ADR_PAD28)) & 0xfffffffd)) -+#define SET_PAD28_DS(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 2) | ((REG32(ADR_PAD28)) & 0xfffffffb)) -+#define SET_PAD28_IE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 3) | ((REG32(ADR_PAD28)) & 0xfffffff7)) -+#define SET_PAD28_SEL_I(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 4) | ((REG32(ADR_PAD28)) & 0xffffff8f)) -+#define SET_PAD28_OD(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 8) | ((REG32(ADR_PAD28)) & 0xfffffeff)) -+#define SET_PAD28_SEL_O(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 12) | ((REG32(ADR_PAD28)) & 0xffff0fff)) -+#define SET_PAD28_SEL_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 20) | ((REG32(ADR_PAD28)) & 0xffefffff)) -+#define SET_GPIO_3_ID(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 28) | ((REG32(ADR_PAD28)) & 0xefffffff)) -+#define SET_PAD29_OE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 0) | ((REG32(ADR_PAD29)) & 0xfffffffe)) -+#define SET_PAD29_PE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 1) | ((REG32(ADR_PAD29)) & 0xfffffffd)) -+#define SET_PAD29_DS(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 2) | ((REG32(ADR_PAD29)) & 0xfffffffb)) -+#define SET_PAD29_IE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 3) | ((REG32(ADR_PAD29)) & 0xfffffff7)) -+#define SET_PAD29_SEL_I(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 4) | ((REG32(ADR_PAD29)) & 0xffffff8f)) -+#define SET_PAD29_OD(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 8) | ((REG32(ADR_PAD29)) & 0xfffffeff)) -+#define SET_PAD29_SEL_O(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 12) | ((REG32(ADR_PAD29)) & 0xffff8fff)) -+#define SET_GPIO_TEST_5_ID(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 28) | ((REG32(ADR_PAD29)) & 0xefffffff)) -+#define SET_PAD30_OE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 0) | ((REG32(ADR_PAD30)) & 0xfffffffe)) -+#define SET_PAD30_PE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 1) | ((REG32(ADR_PAD30)) & 0xfffffffd)) -+#define SET_PAD30_DS(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 2) | ((REG32(ADR_PAD30)) & 0xfffffffb)) -+#define SET_PAD30_IE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 3) | ((REG32(ADR_PAD30)) & 0xfffffff7)) -+#define SET_PAD30_SEL_I(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 4) | ((REG32(ADR_PAD30)) & 0xffffffcf)) -+#define SET_PAD30_OD(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 8) | ((REG32(ADR_PAD30)) & 0xfffffeff)) -+#define SET_PAD30_SEL_O(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 12) | ((REG32(ADR_PAD30)) & 0xffffcfff)) -+#define SET_TEST_6_ID(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 28) | ((REG32(ADR_PAD30)) & 0xefffffff)) -+#define SET_PAD31_OE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 0) | ((REG32(ADR_PAD31)) & 0xfffffffe)) -+#define SET_PAD31_PE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 1) | ((REG32(ADR_PAD31)) & 0xfffffffd)) -+#define SET_PAD31_DS(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 2) | ((REG32(ADR_PAD31)) & 0xfffffffb)) -+#define SET_PAD31_IE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 3) | ((REG32(ADR_PAD31)) & 0xfffffff7)) -+#define SET_PAD31_SEL_I(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 4) | ((REG32(ADR_PAD31)) & 0xffffffcf)) -+#define SET_PAD31_OD(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 8) | ((REG32(ADR_PAD31)) & 0xfffffeff)) -+#define SET_PAD31_SEL_O(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 12) | ((REG32(ADR_PAD31)) & 0xffffcfff)) -+#define SET_TEST_7_ID(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 28) | ((REG32(ADR_PAD31)) & 0xefffffff)) -+#define SET_PAD32_OE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 0) | ((REG32(ADR_PAD32)) & 0xfffffffe)) -+#define SET_PAD32_PE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 1) | ((REG32(ADR_PAD32)) & 0xfffffffd)) -+#define SET_PAD32_DS(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 2) | ((REG32(ADR_PAD32)) & 0xfffffffb)) -+#define SET_PAD32_IE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 3) | ((REG32(ADR_PAD32)) & 0xfffffff7)) -+#define SET_PAD32_SEL_I(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 4) | ((REG32(ADR_PAD32)) & 0xffffffcf)) -+#define SET_PAD32_OD(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 8) | ((REG32(ADR_PAD32)) & 0xfffffeff)) -+#define SET_PAD32_SEL_O(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 12) | ((REG32(ADR_PAD32)) & 0xffffcfff)) -+#define SET_TEST_8_ID(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 28) | ((REG32(ADR_PAD32)) & 0xefffffff)) -+#define SET_PAD33_OE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 0) | ((REG32(ADR_PAD33)) & 0xfffffffe)) -+#define SET_PAD33_PE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 1) | ((REG32(ADR_PAD33)) & 0xfffffffd)) -+#define SET_PAD33_DS(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 2) | ((REG32(ADR_PAD33)) & 0xfffffffb)) -+#define SET_PAD33_IE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 3) | ((REG32(ADR_PAD33)) & 0xfffffff7)) -+#define SET_PAD33_SEL_I(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 4) | ((REG32(ADR_PAD33)) & 0xffffffcf)) -+#define SET_PAD33_OD(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 8) | ((REG32(ADR_PAD33)) & 0xfffffeff)) -+#define SET_PAD33_SEL_O(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 12) | ((REG32(ADR_PAD33)) & 0xffffcfff)) -+#define SET_TEST_9_ID(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 28) | ((REG32(ADR_PAD33)) & 0xefffffff)) -+#define SET_PAD34_OE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 0) | ((REG32(ADR_PAD34)) & 0xfffffffe)) -+#define SET_PAD34_PE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 1) | ((REG32(ADR_PAD34)) & 0xfffffffd)) -+#define SET_PAD34_DS(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 2) | ((REG32(ADR_PAD34)) & 0xfffffffb)) -+#define SET_PAD34_IE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 3) | ((REG32(ADR_PAD34)) & 0xfffffff7)) -+#define SET_PAD34_SEL_I(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 4) | ((REG32(ADR_PAD34)) & 0xffffffcf)) -+#define SET_PAD34_OD(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 8) | ((REG32(ADR_PAD34)) & 0xfffffeff)) -+#define SET_PAD34_SEL_O(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 12) | ((REG32(ADR_PAD34)) & 0xffffcfff)) -+#define SET_TEST_10_ID(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 28) | ((REG32(ADR_PAD34)) & 0xefffffff)) -+#define SET_PAD42_OE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 0) | ((REG32(ADR_PAD42)) & 0xfffffffe)) -+#define SET_PAD42_PE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 1) | ((REG32(ADR_PAD42)) & 0xfffffffd)) -+#define SET_PAD42_DS(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 2) | ((REG32(ADR_PAD42)) & 0xfffffffb)) -+#define SET_PAD42_IE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 3) | ((REG32(ADR_PAD42)) & 0xfffffff7)) -+#define SET_PAD42_SEL_I(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 4) | ((REG32(ADR_PAD42)) & 0xffffffcf)) -+#define SET_PAD42_OD(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 8) | ((REG32(ADR_PAD42)) & 0xfffffeff)) -+#define SET_PAD42_SEL_O(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 12) | ((REG32(ADR_PAD42)) & 0xffffefff)) -+#define SET_TEST_11_ID(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 28) | ((REG32(ADR_PAD42)) & 0xefffffff)) -+#define SET_PAD43_OE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 0) | ((REG32(ADR_PAD43)) & 0xfffffffe)) -+#define SET_PAD43_PE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 1) | ((REG32(ADR_PAD43)) & 0xfffffffd)) -+#define SET_PAD43_DS(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 2) | ((REG32(ADR_PAD43)) & 0xfffffffb)) -+#define SET_PAD43_IE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 3) | ((REG32(ADR_PAD43)) & 0xfffffff7)) -+#define SET_PAD43_SEL_I(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 4) | ((REG32(ADR_PAD43)) & 0xffffffcf)) -+#define SET_PAD43_OD(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 8) | ((REG32(ADR_PAD43)) & 0xfffffeff)) -+#define SET_PAD43_SEL_O(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 12) | ((REG32(ADR_PAD43)) & 0xffffefff)) -+#define SET_TEST_12_ID(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 28) | ((REG32(ADR_PAD43)) & 0xefffffff)) -+#define SET_PAD44_OE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 0) | ((REG32(ADR_PAD44)) & 0xfffffffe)) -+#define SET_PAD44_PE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 1) | ((REG32(ADR_PAD44)) & 0xfffffffd)) -+#define SET_PAD44_DS(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 2) | ((REG32(ADR_PAD44)) & 0xfffffffb)) -+#define SET_PAD44_IE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 3) | ((REG32(ADR_PAD44)) & 0xfffffff7)) -+#define SET_PAD44_SEL_I(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 4) | ((REG32(ADR_PAD44)) & 0xffffffcf)) -+#define SET_PAD44_OD(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 8) | ((REG32(ADR_PAD44)) & 0xfffffeff)) -+#define SET_PAD44_SEL_O(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 12) | ((REG32(ADR_PAD44)) & 0xffffcfff)) -+#define SET_TEST_13_ID(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 28) | ((REG32(ADR_PAD44)) & 0xefffffff)) -+#define SET_PAD45_OE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 0) | ((REG32(ADR_PAD45)) & 0xfffffffe)) -+#define SET_PAD45_PE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 1) | ((REG32(ADR_PAD45)) & 0xfffffffd)) -+#define SET_PAD45_DS(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 2) | ((REG32(ADR_PAD45)) & 0xfffffffb)) -+#define SET_PAD45_IE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 3) | ((REG32(ADR_PAD45)) & 0xfffffff7)) -+#define SET_PAD45_SEL_I(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 4) | ((REG32(ADR_PAD45)) & 0xffffffcf)) -+#define SET_PAD45_OD(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 8) | ((REG32(ADR_PAD45)) & 0xfffffeff)) -+#define SET_PAD45_SEL_O(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 12) | ((REG32(ADR_PAD45)) & 0xffffcfff)) -+#define SET_TEST_14_ID(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 28) | ((REG32(ADR_PAD45)) & 0xefffffff)) -+#define SET_PAD46_OE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 0) | ((REG32(ADR_PAD46)) & 0xfffffffe)) -+#define SET_PAD46_PE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 1) | ((REG32(ADR_PAD46)) & 0xfffffffd)) -+#define SET_PAD46_DS(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 2) | ((REG32(ADR_PAD46)) & 0xfffffffb)) -+#define SET_PAD46_IE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 3) | ((REG32(ADR_PAD46)) & 0xfffffff7)) -+#define SET_PAD46_SEL_I(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 4) | ((REG32(ADR_PAD46)) & 0xffffffcf)) -+#define SET_PAD46_OD(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 8) | ((REG32(ADR_PAD46)) & 0xfffffeff)) -+#define SET_PAD46_SEL_O(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 12) | ((REG32(ADR_PAD46)) & 0xffffcfff)) -+#define SET_TEST_15_ID(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 28) | ((REG32(ADR_PAD46)) & 0xefffffff)) -+#define SET_PAD47_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 0) | ((REG32(ADR_PAD47)) & 0xfffffffe)) -+#define SET_PAD47_PE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 1) | ((REG32(ADR_PAD47)) & 0xfffffffd)) -+#define SET_PAD47_DS(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 2) | ((REG32(ADR_PAD47)) & 0xfffffffb)) -+#define SET_PAD47_SEL_I(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 4) | ((REG32(ADR_PAD47)) & 0xffffffcf)) -+#define SET_PAD47_OD(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 8) | ((REG32(ADR_PAD47)) & 0xfffffeff)) -+#define SET_PAD47_SEL_O(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 12) | ((REG32(ADR_PAD47)) & 0xffffcfff)) -+#define SET_PAD47_SEL_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 20) | ((REG32(ADR_PAD47)) & 0xffefffff)) -+#define SET_GPIO_9_ID(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 28) | ((REG32(ADR_PAD47)) & 0xefffffff)) -+#define SET_PAD48_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 0) | ((REG32(ADR_PAD48)) & 0xfffffffe)) -+#define SET_PAD48_PE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 1) | ((REG32(ADR_PAD48)) & 0xfffffffd)) -+#define SET_PAD48_DS(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 2) | ((REG32(ADR_PAD48)) & 0xfffffffb)) -+#define SET_PAD48_IE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 3) | ((REG32(ADR_PAD48)) & 0xfffffff7)) -+#define SET_PAD48_SEL_I(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 4) | ((REG32(ADR_PAD48)) & 0xffffff8f)) -+#define SET_PAD48_OD(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 8) | ((REG32(ADR_PAD48)) & 0xfffffeff)) -+#define SET_PAD48_PE_SEL(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 11) | ((REG32(ADR_PAD48)) & 0xfffff7ff)) -+#define SET_PAD48_SEL_O(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 12) | ((REG32(ADR_PAD48)) & 0xffffcfff)) -+#define SET_PAD48_SEL_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 20) | ((REG32(ADR_PAD48)) & 0xffefffff)) -+#define SET_GPIO_10_ID(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 28) | ((REG32(ADR_PAD48)) & 0xefffffff)) -+#define SET_PAD49_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 0) | ((REG32(ADR_PAD49)) & 0xfffffffe)) -+#define SET_PAD49_PE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 1) | ((REG32(ADR_PAD49)) & 0xfffffffd)) -+#define SET_PAD49_DS(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 2) | ((REG32(ADR_PAD49)) & 0xfffffffb)) -+#define SET_PAD49_IE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 3) | ((REG32(ADR_PAD49)) & 0xfffffff7)) -+#define SET_PAD49_SEL_I(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 4) | ((REG32(ADR_PAD49)) & 0xffffff8f)) -+#define SET_PAD49_OD(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 8) | ((REG32(ADR_PAD49)) & 0xfffffeff)) -+#define SET_PAD49_SEL_O(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 12) | ((REG32(ADR_PAD49)) & 0xffffcfff)) -+#define SET_PAD49_SEL_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 20) | ((REG32(ADR_PAD49)) & 0xffefffff)) -+#define SET_GPIO_11_ID(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 28) | ((REG32(ADR_PAD49)) & 0xefffffff)) -+#define SET_PAD50_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 0) | ((REG32(ADR_PAD50)) & 0xfffffffe)) -+#define SET_PAD50_PE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 1) | ((REG32(ADR_PAD50)) & 0xfffffffd)) -+#define SET_PAD50_DS(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 2) | ((REG32(ADR_PAD50)) & 0xfffffffb)) -+#define SET_PAD50_IE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 3) | ((REG32(ADR_PAD50)) & 0xfffffff7)) -+#define SET_PAD50_SEL_I(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 4) | ((REG32(ADR_PAD50)) & 0xffffff8f)) -+#define SET_PAD50_OD(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 8) | ((REG32(ADR_PAD50)) & 0xfffffeff)) -+#define SET_PAD50_SEL_O(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 12) | ((REG32(ADR_PAD50)) & 0xffffcfff)) -+#define SET_PAD50_SEL_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 20) | ((REG32(ADR_PAD50)) & 0xffefffff)) -+#define SET_GPIO_12_ID(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 28) | ((REG32(ADR_PAD50)) & 0xefffffff)) -+#define SET_PAD51_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 0) | ((REG32(ADR_PAD51)) & 0xfffffffe)) -+#define SET_PAD51_PE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 1) | ((REG32(ADR_PAD51)) & 0xfffffffd)) -+#define SET_PAD51_DS(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 2) | ((REG32(ADR_PAD51)) & 0xfffffffb)) -+#define SET_PAD51_IE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 3) | ((REG32(ADR_PAD51)) & 0xfffffff7)) -+#define SET_PAD51_SEL_I(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 4) | ((REG32(ADR_PAD51)) & 0xffffffcf)) -+#define SET_PAD51_OD(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 8) | ((REG32(ADR_PAD51)) & 0xfffffeff)) -+#define SET_PAD51_SEL_O(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 12) | ((REG32(ADR_PAD51)) & 0xffffefff)) -+#define SET_PAD51_SEL_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 20) | ((REG32(ADR_PAD51)) & 0xffefffff)) -+#define SET_GPIO_13_ID(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 28) | ((REG32(ADR_PAD51)) & 0xefffffff)) -+#define SET_PAD52_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 0) | ((REG32(ADR_PAD52)) & 0xfffffffe)) -+#define SET_PAD52_PE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 1) | ((REG32(ADR_PAD52)) & 0xfffffffd)) -+#define SET_PAD52_DS(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 2) | ((REG32(ADR_PAD52)) & 0xfffffffb)) -+#define SET_PAD52_SEL_I(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 4) | ((REG32(ADR_PAD52)) & 0xffffffcf)) -+#define SET_PAD52_OD(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 8) | ((REG32(ADR_PAD52)) & 0xfffffeff)) -+#define SET_PAD52_SEL_O(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 12) | ((REG32(ADR_PAD52)) & 0xffffefff)) -+#define SET_PAD52_SEL_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 20) | ((REG32(ADR_PAD52)) & 0xffefffff)) -+#define SET_GPIO_14_ID(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 28) | ((REG32(ADR_PAD52)) & 0xefffffff)) -+#define SET_PAD53_OE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 0) | ((REG32(ADR_PAD53)) & 0xfffffffe)) -+#define SET_PAD53_PE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 1) | ((REG32(ADR_PAD53)) & 0xfffffffd)) -+#define SET_PAD53_DS(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 2) | ((REG32(ADR_PAD53)) & 0xfffffffb)) -+#define SET_PAD53_IE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 3) | ((REG32(ADR_PAD53)) & 0xfffffff7)) -+#define SET_PAD53_SEL_I(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 4) | ((REG32(ADR_PAD53)) & 0xffffffcf)) -+#define SET_PAD53_OD(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 8) | ((REG32(ADR_PAD53)) & 0xfffffeff)) -+#define SET_PAD53_SEL_O(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 12) | ((REG32(ADR_PAD53)) & 0xffffefff)) -+#define SET_JTAG_TMS_ID(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 28) | ((REG32(ADR_PAD53)) & 0xefffffff)) -+#define SET_PAD54_OE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 0) | ((REG32(ADR_PAD54)) & 0xfffffffe)) -+#define SET_PAD54_PE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 1) | ((REG32(ADR_PAD54)) & 0xfffffffd)) -+#define SET_PAD54_DS(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 2) | ((REG32(ADR_PAD54)) & 0xfffffffb)) -+#define SET_PAD54_OD(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 8) | ((REG32(ADR_PAD54)) & 0xfffffeff)) -+#define SET_PAD54_SEL_O(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 12) | ((REG32(ADR_PAD54)) & 0xffffcfff)) -+#define SET_JTAG_TCK_ID(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 28) | ((REG32(ADR_PAD54)) & 0xefffffff)) -+#define SET_PAD56_PE(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 1) | ((REG32(ADR_PAD56)) & 0xfffffffd)) -+#define SET_PAD56_DS(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 2) | ((REG32(ADR_PAD56)) & 0xfffffffb)) -+#define SET_PAD56_SEL_I(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 4) | ((REG32(ADR_PAD56)) & 0xffffffef)) -+#define SET_PAD56_OD(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 8) | ((REG32(ADR_PAD56)) & 0xfffffeff)) -+#define SET_JTAG_TDI_ID(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 28) | ((REG32(ADR_PAD56)) & 0xefffffff)) -+#define SET_PAD57_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 0) | ((REG32(ADR_PAD57)) & 0xfffffffe)) -+#define SET_PAD57_PE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 1) | ((REG32(ADR_PAD57)) & 0xfffffffd)) -+#define SET_PAD57_DS(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 2) | ((REG32(ADR_PAD57)) & 0xfffffffb)) -+#define SET_PAD57_IE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 3) | ((REG32(ADR_PAD57)) & 0xfffffff7)) -+#define SET_PAD57_SEL_I(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 4) | ((REG32(ADR_PAD57)) & 0xffffffcf)) -+#define SET_PAD57_OD(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 8) | ((REG32(ADR_PAD57)) & 0xfffffeff)) -+#define SET_PAD57_SEL_O(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 12) | ((REG32(ADR_PAD57)) & 0xffffcfff)) -+#define SET_PAD57_SEL_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 20) | ((REG32(ADR_PAD57)) & 0xffefffff)) -+#define SET_JTAG_TDO_ID(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 28) | ((REG32(ADR_PAD57)) & 0xefffffff)) -+#define SET_PAD58_OE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 0) | ((REG32(ADR_PAD58)) & 0xfffffffe)) -+#define SET_PAD58_PE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 1) | ((REG32(ADR_PAD58)) & 0xfffffffd)) -+#define SET_PAD58_DS(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 2) | ((REG32(ADR_PAD58)) & 0xfffffffb)) -+#define SET_PAD58_IE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 3) | ((REG32(ADR_PAD58)) & 0xfffffff7)) -+#define SET_PAD58_SEL_I(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 4) | ((REG32(ADR_PAD58)) & 0xffffffcf)) -+#define SET_PAD58_OD(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 8) | ((REG32(ADR_PAD58)) & 0xfffffeff)) -+#define SET_PAD58_SEL_O(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 12) | ((REG32(ADR_PAD58)) & 0xffffefff)) -+#define SET_TEST_16_ID(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 28) | ((REG32(ADR_PAD58)) & 0xefffffff)) -+#define SET_PAD59_OE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 0) | ((REG32(ADR_PAD59)) & 0xfffffffe)) -+#define SET_PAD59_PE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 1) | ((REG32(ADR_PAD59)) & 0xfffffffd)) -+#define SET_PAD59_DS(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 2) | ((REG32(ADR_PAD59)) & 0xfffffffb)) -+#define SET_PAD59_IE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 3) | ((REG32(ADR_PAD59)) & 0xfffffff7)) -+#define SET_PAD59_SEL_I(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 4) | ((REG32(ADR_PAD59)) & 0xffffffcf)) -+#define SET_PAD59_OD(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 8) | ((REG32(ADR_PAD59)) & 0xfffffeff)) -+#define SET_PAD59_SEL_O(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 12) | ((REG32(ADR_PAD59)) & 0xffffefff)) -+#define SET_TEST_17_ID(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 28) | ((REG32(ADR_PAD59)) & 0xefffffff)) -+#define SET_PAD60_OE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 0) | ((REG32(ADR_PAD60)) & 0xfffffffe)) -+#define SET_PAD60_PE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 1) | ((REG32(ADR_PAD60)) & 0xfffffffd)) -+#define SET_PAD60_DS(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 2) | ((REG32(ADR_PAD60)) & 0xfffffffb)) -+#define SET_PAD60_IE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 3) | ((REG32(ADR_PAD60)) & 0xfffffff7)) -+#define SET_PAD60_SEL_I(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 4) | ((REG32(ADR_PAD60)) & 0xffffffcf)) -+#define SET_PAD60_OD(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 8) | ((REG32(ADR_PAD60)) & 0xfffffeff)) -+#define SET_PAD60_SEL_O(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 12) | ((REG32(ADR_PAD60)) & 0xffffefff)) -+#define SET_TEST_18_ID(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 28) | ((REG32(ADR_PAD60)) & 0xefffffff)) -+#define SET_PAD61_OE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 0) | ((REG32(ADR_PAD61)) & 0xfffffffe)) -+#define SET_PAD61_PE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 1) | ((REG32(ADR_PAD61)) & 0xfffffffd)) -+#define SET_PAD61_DS(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 2) | ((REG32(ADR_PAD61)) & 0xfffffffb)) -+#define SET_PAD61_IE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 3) | ((REG32(ADR_PAD61)) & 0xfffffff7)) -+#define SET_PAD61_SEL_I(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 4) | ((REG32(ADR_PAD61)) & 0xffffffef)) -+#define SET_PAD61_OD(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 8) | ((REG32(ADR_PAD61)) & 0xfffffeff)) -+#define SET_PAD61_SEL_O(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 12) | ((REG32(ADR_PAD61)) & 0xffffcfff)) -+#define SET_TEST_19_ID(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 28) | ((REG32(ADR_PAD61)) & 0xefffffff)) -+#define SET_PAD62_OE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 0) | ((REG32(ADR_PAD62)) & 0xfffffffe)) -+#define SET_PAD62_PE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 1) | ((REG32(ADR_PAD62)) & 0xfffffffd)) -+#define SET_PAD62_DS(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 2) | ((REG32(ADR_PAD62)) & 0xfffffffb)) -+#define SET_PAD62_IE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 3) | ((REG32(ADR_PAD62)) & 0xfffffff7)) -+#define SET_PAD62_SEL_I(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 4) | ((REG32(ADR_PAD62)) & 0xffffffef)) -+#define SET_PAD62_OD(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 8) | ((REG32(ADR_PAD62)) & 0xfffffeff)) -+#define SET_PAD62_SEL_O(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 12) | ((REG32(ADR_PAD62)) & 0xffffefff)) -+#define SET_TEST_20_ID(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 28) | ((REG32(ADR_PAD62)) & 0xefffffff)) -+#define SET_PAD64_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 0) | ((REG32(ADR_PAD64)) & 0xfffffffe)) -+#define SET_PAD64_PE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 1) | ((REG32(ADR_PAD64)) & 0xfffffffd)) -+#define SET_PAD64_DS(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 2) | ((REG32(ADR_PAD64)) & 0xfffffffb)) -+#define SET_PAD64_IE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 3) | ((REG32(ADR_PAD64)) & 0xfffffff7)) -+#define SET_PAD64_SEL_I(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 4) | ((REG32(ADR_PAD64)) & 0xffffff8f)) -+#define SET_PAD64_OD(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 8) | ((REG32(ADR_PAD64)) & 0xfffffeff)) -+#define SET_PAD64_SEL_O(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 12) | ((REG32(ADR_PAD64)) & 0xffffcfff)) -+#define SET_PAD64_SEL_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 20) | ((REG32(ADR_PAD64)) & 0xffefffff)) -+#define SET_GPIO_15_IP_ID(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 28) | ((REG32(ADR_PAD64)) & 0xefffffff)) -+#define SET_PAD65_OE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 0) | ((REG32(ADR_PAD65)) & 0xfffffffe)) -+#define SET_PAD65_PE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 1) | ((REG32(ADR_PAD65)) & 0xfffffffd)) -+#define SET_PAD65_DS(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 2) | ((REG32(ADR_PAD65)) & 0xfffffffb)) -+#define SET_PAD65_IE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 3) | ((REG32(ADR_PAD65)) & 0xfffffff7)) -+#define SET_PAD65_SEL_I(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 4) | ((REG32(ADR_PAD65)) & 0xffffff8f)) -+#define SET_PAD65_OD(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 8) | ((REG32(ADR_PAD65)) & 0xfffffeff)) -+#define SET_PAD65_SEL_O(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 12) | ((REG32(ADR_PAD65)) & 0xffffefff)) -+#define SET_GPIO_TEST_7_IN_ID(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 28) | ((REG32(ADR_PAD65)) & 0xefffffff)) -+#define SET_PAD66_OE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 0) | ((REG32(ADR_PAD66)) & 0xfffffffe)) -+#define SET_PAD66_PE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 1) | ((REG32(ADR_PAD66)) & 0xfffffffd)) -+#define SET_PAD66_DS(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 2) | ((REG32(ADR_PAD66)) & 0xfffffffb)) -+#define SET_PAD66_IE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 3) | ((REG32(ADR_PAD66)) & 0xfffffff7)) -+#define SET_PAD66_SEL_I(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 4) | ((REG32(ADR_PAD66)) & 0xffffffcf)) -+#define SET_PAD66_OD(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 8) | ((REG32(ADR_PAD66)) & 0xfffffeff)) -+#define SET_PAD66_SEL_O(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 12) | ((REG32(ADR_PAD66)) & 0xffffcfff)) -+#define SET_GPIO_17_QP_ID(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 28) | ((REG32(ADR_PAD66)) & 0xefffffff)) -+#define SET_PAD68_OE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 0) | ((REG32(ADR_PAD68)) & 0xfffffffe)) -+#define SET_PAD68_PE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 1) | ((REG32(ADR_PAD68)) & 0xfffffffd)) -+#define SET_PAD68_DS(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 2) | ((REG32(ADR_PAD68)) & 0xfffffffb)) -+#define SET_PAD68_IE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 3) | ((REG32(ADR_PAD68)) & 0xfffffff7)) -+#define SET_PAD68_OD(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 8) | ((REG32(ADR_PAD68)) & 0xfffffeff)) -+#define SET_PAD68_SEL_O(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 12) | ((REG32(ADR_PAD68)) & 0xffffefff)) -+#define SET_GPIO_19_ID(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 28) | ((REG32(ADR_PAD68)) & 0xefffffff)) -+#define SET_PAD67_OE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 0) | ((REG32(ADR_PAD67)) & 0xfffffffe)) -+#define SET_PAD67_PE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 1) | ((REG32(ADR_PAD67)) & 0xfffffffd)) -+#define SET_PAD67_DS(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 2) | ((REG32(ADR_PAD67)) & 0xfffffffb)) -+#define SET_PAD67_IE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 3) | ((REG32(ADR_PAD67)) & 0xfffffff7)) -+#define SET_PAD67_SEL_I(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 4) | ((REG32(ADR_PAD67)) & 0xffffff8f)) -+#define SET_PAD67_OD(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 8) | ((REG32(ADR_PAD67)) & 0xfffffeff)) -+#define SET_PAD67_SEL_O(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 12) | ((REG32(ADR_PAD67)) & 0xffffcfff)) -+#define SET_GPIO_TEST_8_QN_ID(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 28) | ((REG32(ADR_PAD67)) & 0xefffffff)) -+#define SET_PAD69_OE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 0) | ((REG32(ADR_PAD69)) & 0xfffffffe)) -+#define SET_PAD69_PE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 1) | ((REG32(ADR_PAD69)) & 0xfffffffd)) -+#define SET_PAD69_DS(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 2) | ((REG32(ADR_PAD69)) & 0xfffffffb)) -+#define SET_PAD69_IE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 3) | ((REG32(ADR_PAD69)) & 0xfffffff7)) -+#define SET_PAD69_SEL_I(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 4) | ((REG32(ADR_PAD69)) & 0xffffffcf)) -+#define SET_PAD69_OD(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 8) | ((REG32(ADR_PAD69)) & 0xfffffeff)) -+#define SET_PAD69_SEL_O(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 12) | ((REG32(ADR_PAD69)) & 0xffffefff)) -+#define SET_STRAP2(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 27) | ((REG32(ADR_PAD69)) & 0xf7ffffff)) -+#define SET_GPIO_20_ID(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 28) | ((REG32(ADR_PAD69)) & 0xefffffff)) -+#define SET_PAD70_OE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 0) | ((REG32(ADR_PAD70)) & 0xfffffffe)) -+#define SET_PAD70_PE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 1) | ((REG32(ADR_PAD70)) & 0xfffffffd)) -+#define SET_PAD70_DS(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 2) | ((REG32(ADR_PAD70)) & 0xfffffffb)) -+#define SET_PAD70_IE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 3) | ((REG32(ADR_PAD70)) & 0xfffffff7)) -+#define SET_PAD70_SEL_I(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 4) | ((REG32(ADR_PAD70)) & 0xffffffcf)) -+#define SET_PAD70_OD(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 8) | ((REG32(ADR_PAD70)) & 0xfffffeff)) -+#define SET_PAD70_SEL_O(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 12) | ((REG32(ADR_PAD70)) & 0xffff8fff)) -+#define SET_GPIO_21_ID(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 28) | ((REG32(ADR_PAD70)) & 0xefffffff)) -+#define SET_PAD231_OE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 0) | ((REG32(ADR_PAD231)) & 0xfffffffe)) -+#define SET_PAD231_PE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 1) | ((REG32(ADR_PAD231)) & 0xfffffffd)) -+#define SET_PAD231_DS(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 2) | ((REG32(ADR_PAD231)) & 0xfffffffb)) -+#define SET_PAD231_IE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 3) | ((REG32(ADR_PAD231)) & 0xfffffff7)) -+#define SET_PAD231_OD(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 8) | ((REG32(ADR_PAD231)) & 0xfffffeff)) -+#define SET_PIN_40_OR_56_ID(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 28) | ((REG32(ADR_PAD231)) & 0xefffffff)) -+#define SET_MP_PHY2RX_DATA__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffe)) -+#define SET_MP_PHY2RX_DATA__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffd)) -+#define SET_MP_TX_FF_RPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 2) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffb)) -+#define SET_MP_RX_FF_WPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 3) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffff7)) -+#define SET_MP_RX_FF_WPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 4) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffef)) -+#define SET_MP_RX_FF_WPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 5) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffdf)) -+#define SET_MP_PHY2RX_DATA__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 6) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffbf)) -+#define SET_MP_PHY2RX_DATA__4_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 7) | ((REG32(ADR_PIN_SEL_0)) & 0xffffff7f)) -+#define SET_I2CM_SDA_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 8) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffcff)) -+#define SET_CRYSTAL_OUT_REQ_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 10) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffbff)) -+#define SET_MP_PHY2RX_DATA__5_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 11) | ((REG32(ADR_PIN_SEL_0)) & 0xfffff7ff)) -+#define SET_MP_PHY2RX_DATA__3_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 12) | ((REG32(ADR_PIN_SEL_0)) & 0xffffefff)) -+#define SET_UART_RXD_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 13) | ((REG32(ADR_PIN_SEL_0)) & 0xffff9fff)) -+#define SET_MP_PHY2RX_DATA__6_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 15) | ((REG32(ADR_PIN_SEL_0)) & 0xffff7fff)) -+#define SET_DAT_UART_NCTS_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 16) | ((REG32(ADR_PIN_SEL_0)) & 0xfffeffff)) -+#define SET_GPIO_LOG_STOP_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 17) | ((REG32(ADR_PIN_SEL_0)) & 0xfff1ffff)) -+#define SET_MP_TX_FF_RPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 20) | ((REG32(ADR_PIN_SEL_0)) & 0xffefffff)) -+#define SET_MP_PHY_RX_WRST_N_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 21) | ((REG32(ADR_PIN_SEL_0)) & 0xffdfffff)) -+#define SET_EXT_32K_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 22) | ((REG32(ADR_PIN_SEL_0)) & 0xff3fffff)) -+#define SET_MP_PHY2RX_DATA__7_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 24) | ((REG32(ADR_PIN_SEL_0)) & 0xfeffffff)) -+#define SET_MP_TX_FF_RPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 25) | ((REG32(ADR_PIN_SEL_0)) & 0xfdffffff)) -+#define SET_PMUINT_WAKE_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 26) | ((REG32(ADR_PIN_SEL_0)) & 0xe3ffffff)) -+#define SET_I2CM_SCL_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 29) | ((REG32(ADR_PIN_SEL_0)) & 0xdfffffff)) -+#define SET_MP_MRX_RX_EN_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 30) | ((REG32(ADR_PIN_SEL_0)) & 0xbfffffff)) -+#define SET_DAT_UART_RXD_SEL_0(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 31) | ((REG32(ADR_PIN_SEL_0)) & 0x7fffffff)) -+#define SET_DAT_UART_RXD_SEL_1(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffe)) -+#define SET_SPI_DI_SEL(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffd)) -+#define SET_IO_PORT_REG(_VAL_) (REG32(ADR_IO_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_PORT_REG)) & 0xfffe0000)) -+#define SET_MASK_RX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffe)) -+#define SET_MASK_TX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffd)) -+#define SET_MASK_SOC_SYSTEM_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffb)) -+#define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffff7)) -+#define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffef)) -+#define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffdf)) -+#define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffbf)) -+#define SET_TX_LIMIT_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_MASK_REG)) & 0xffffff7f)) -+#define SET_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffe)) -+#define SET_TX_COMPLETE_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffd)) -+#define SET_SOC_SYSTEM_INT_STATUS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffb)) -+#define SET_EDCA0_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffff7)) -+#define SET_EDCA1_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffef)) -+#define SET_EDCA2_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffdf)) -+#define SET_EDCA3_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffbf)) -+#define SET_TX_LIMIT_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffff7f)) -+#define SET_HOST_TRIGGERED_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffeff)) -+#define SET_HOST_TRIGGERED_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 9) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffdff)) -+#define SET_SOC_TRIGGER_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 10) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffbff)) -+#define SET_SOC_TRIGGER_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 11) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffff7ff)) -+#define SET_RDY_FOR_TX_RX(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffe)) -+#define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffd)) -+#define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffb)) -+#define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffff7)) -+#define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffffef)) -+#define SET_TRIGGER_FUNCTION_SETTING(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff9f)) -+#define SET_CMD52_ABORT_RESPONSE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff7f)) -+#define SET_RX_PACKET_LENGTH(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xffff0000)) -+#define SET_CARD_FW_DL_STATUS(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 16) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xff00ffff)) -+#define SET_TX_RX_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 24) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfeffffff)) -+#define SET_SDIO_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 25) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfdffffff)) -+#define SET_CMD52_ABORT_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 28) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xefffffff)) -+#define SET_CMD52_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 29) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xdfffffff)) -+#define SET_SDIO_PARTIAL_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 30) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xbfffffff)) -+#define SET_SDIO_ALL_RESE_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 31) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x7fffffff)) -+#define SET_RX_PACKET_LENGTH2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xffff0000)) -+#define SET_RX_INT1(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffeffff)) -+#define SET_TX_DONE(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffdffff)) -+#define SET_HCI_TRX_FINISH(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffbffff)) -+#define SET_ALLOCATE_STATUS(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfff7ffff)) -+#define SET_HCI_INPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xff0fffff)) -+#define SET_HCI_OUTPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xe0ffffff)) -+#define SET_AHB_HANG4(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 29) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xdfffffff)) -+#define SET_HCI_IN_QUE_EMPTY(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 30) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xbfffffff)) -+#define SET_SYSTEM_INT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x7fffffff)) -+#define SET_CARD_RCA_REG(_VAL_) (REG32(ADR_CARD_RCA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_RCA_REG)) & 0xffff0000)) -+#define SET_SDIO_FIFO_WR_THLD_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0xfffffe00)) -+#define SET_SDIO_FIFO_WR_LIMIT_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0xfffffe00)) -+#define SET_SDIO_TX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0xfffffe00)) -+#define SET_SDIO_THLD_FOR_CMD53RD_REG(_VAL_) (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0xfffffe00)) -+#define SET_SDIO_RX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0xfffffe00)) -+#define SET_START_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffffff00)) -+#define SET_END_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffff00ff)) -+#define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0xffffff00)) -+#define SET_SDIO_LAST_CMD_INDEX_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffffffc0)) -+#define SET_SDIO_LAST_CMD_CRC_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffff80ff)) -+#define SET_SDIO_LAST_CMD_ARG_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0x00000000)) -+#define SET_SDIO_BUS_STATE_REG(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffffffe0)) -+#define SET_SDIO_BUSY_LONG_CNT(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000ffff)) -+#define SET_SDIO_CARD_STATUS_REG(_VAL_) (REG32(ADR_SDIO_CARD_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0x00000000)) -+#define SET_R5_RESPONSE_FLAG(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 0) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xffffff00)) -+#define SET_RESP_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 8) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffeff)) -+#define SET_DAT_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 9) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffdff)) -+#define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 16) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffeffff)) -+#define SET_INT_THROUGH_PIN(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 17) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffdffff)) -+#define SET_WRITE_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffffff00)) -+#define SET_WRITE_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 8) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffff00ff)) -+#define SET_READ_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff00ffff)) -+#define SET_READ_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 24) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ffffff)) -+#define SET_FN1_DMA_START_ADDR_REG(_VAL_) (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0x00000000)) -+#define SET_SDIO_TO_MCU_INFO(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffff00)) -+#define SET_SDIO_PARTIAL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffeff)) -+#define SET_SDIO_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffdff)) -+#define SET_PERI_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffbff)) -+#define SET_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffff7ff)) -+#define SET_AHB_BRIDGE_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffefff)) -+#define SET_IO_REG_PORT_REG(_VAL_) (REG32(ADR_IO_REG_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_REG_PORT_REG)) & 0xfffe0000)) -+#define SET_SDIO_FIFO_EMPTY_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000)) -+#define SET_SDIO_FIFO_FULL_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff)) -+#define SET_SDIO_CRC7_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000)) -+#define SET_SDIO_CRC16_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff)) -+#define SET_SDIO_RD_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfffffe00)) -+#define SET_SDIO_WR_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfe00ffff)) -+#define SET_CMD52_RD_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xfff0ffff)) -+#define SET_CMD52_WR_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 20) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xff0fffff)) -+#define SET_SDIO_FIFO_WR_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffffff00)) -+#define SET_SDIO_FIFO_RD_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffff00ff)) -+#define SET_SDIO_READ_DATA_CTRL(_VAL_) (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0xfffeffff)) -+#define SET_TX_SIZE_BEFORE_SHIFT(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffff00)) -+#define SET_TX_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffff8ff)) -+#define SET_SDIO_TX_ALLOC_STATE(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffefff)) -+#define SET_ALLOCATE_STATUS2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffeffff)) -+#define SET_NO_ALLOCATE_SEND_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffdffff)) -+#define SET_DOUBLE_ALLOCATE_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffbffff)) -+#define SET_TX_DONE_STATUS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfff7ffff)) -+#define SET_AHB_HANG2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffefffff)) -+#define SET_HCI_TRX_FINISH2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffdfffff)) -+#define SET_INTR_RX(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffbfffff)) -+#define SET_HCI_INPUT_QUEUE_FULL(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xff7fffff)) -+#define SET_ALLOCATESTATUS(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffe)) -+#define SET_HCI_TRX_FINISH3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffd)) -+#define SET_HCI_IN_QUE_EMPTY2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffb)) -+#define SET_MTX_MNG_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffff7)) -+#define SET_EDCA0_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffef)) -+#define SET_EDCA1_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffdf)) -+#define SET_EDCA2_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffbf)) -+#define SET_EDCA3_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffff7f)) -+#define SET_TX_PAGE_REMAIN2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffff00ff)) -+#define SET_TX_ID_REMAIN3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff80ffff)) -+#define SET_HCI_OUTPUT_FF_CNT_0(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff7fffff)) -+#define SET_HCI_OUTPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xf0ffffff)) -+#define SET_HCI_INPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_TX_INFORM)) & 0x0fffffff)) -+#define SET_F1_BLOCK_SIZE_0_REG(_VAL_) (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (((_VAL_) << 0) | ((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0xfffff000)) -+#define SET_START_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffffff00)) -+#define SET_COMMAND_COUNTER(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff00ff)) -+#define SET_CMD_LOG_PART1(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ffff)) -+#define SET_CMD_LOG_PART2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000)) -+#define SET_END_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff)) -+#define SET_RX_PACKET_LENGTH3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xffff0000)) -+#define SET_RX_INT3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xfffeffff)) -+#define SET_TX_ID_REMAIN2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff01ffff)) -+#define SET_TX_PAGE_REMAIN3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00ffffff)) -+#define SET_CCCR_00H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_00H_REG)) & 0xffffff00)) -+#define SET_CCCR_02H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_00H_REG)) & 0xff00ffff)) -+#define SET_CCCR_03H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_00H_REG)) & 0x00ffffff)) -+#define SET_CCCR_04H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_04H_REG)) & 0xffffff00)) -+#define SET_CCCR_05H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_04H_REG)) & 0xffff00ff)) -+#define SET_CCCR_06H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_04H_REG)) & 0xfff0ffff)) -+#define SET_CCCR_07H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_04H_REG)) & 0x00ffffff)) -+#define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffe)) -+#define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 1) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffd)) -+#define SET_SUPPORT_READ_WAIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 2) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffb)) -+#define SET_SUPPORT_BUS_CONTROL(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 3) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffff7)) -+#define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 4) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffef)) -+#define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 5) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffdf)) -+#define SET_LOW_SPEED_CARD(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffbf)) -+#define SET_LOW_SPEED_CARD_4BIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffff7f)) -+#define SET_COMMON_CIS_PONTER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_08H_REG)) & 0xfe0000ff)) -+#define SET_SUPPORT_HIGH_SPEED(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_13H_REG)) & 0xfeffffff)) -+#define SET_BSS(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 25) | ((REG32(ADR_CCCR_13H_REG)) & 0xf1ffffff)) -+#define SET_FBR_100H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FBR_100H_REG)) & 0xfffffff0)) -+#define SET_CSASUPPORT(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_FBR_100H_REG)) & 0xffffffbf)) -+#define SET_ENABLECSA(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FBR_100H_REG)) & 0xffffff7f)) -+#define SET_FBR_101H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_100H_REG)) & 0xffff00ff)) -+#define SET_FBR_109H_REG(_VAL_) (REG32(ADR_FBR_109H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_109H_REG)) & 0xfe0000ff)) -+#define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0x00000000)) -+#define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0x00000000)) -+#define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0x00000000)) -+#define SET_SPI_MODE(_VAL_) (REG32(ADR_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_MODE)) & 0x00000000)) -+#define SET_RX_QUOTA(_VAL_) (REG32(ADR_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_QUOTA)) & 0xffff0000)) -+#define SET_CONDI_NUM(_VAL_) (REG32(ADR_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_CONDITION_NUMBER)) & 0xffffff00)) -+#define SET_HOST_PATH(_VAL_) (REG32(ADR_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_HOST_PATH)) & 0xfffffffe)) -+#define SET_TX_SEG(_VAL_) (REG32(ADR_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEG)) & 0x00000000)) -+#define SET_BRST_MODE(_VAL_) (REG32(ADR_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_BURST_MODE)) & 0xfffffffe)) -+#define SET_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000)) -+#define SET_CSN_INTER(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff)) -+#define SET_BACK_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000)) -+#define SET_FRONT_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff)) -+#define SET_RX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SPI_STS)) & 0xfffffffd)) -+#define SET_RX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SPI_STS)) & 0xfffffffb)) -+#define SET_TX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SPI_STS)) & 0xfffffff7)) -+#define SET_TX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SPI_STS)) & 0xffffffef)) -+#define SET_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SPI_STS)) & 0xffffffdf)) -+#define SET_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SPI_STS)) & 0xffffffbf)) -+#define SET_RDATA_RDY(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SPI_STS)) & 0xffffff7f)) -+#define SET_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SPI_STS)) & 0xfffffeff)) -+#define SET_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SPI_STS)) & 0xfffffdff)) -+#define SET_RX_LEN(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_STS)) & 0x0000ffff)) -+#define SET_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffff8)) -+#define SET_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffeff)) -+#define SET_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC)) & 0xffffff00)) -+#define SET_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT)) & 0xffff0000)) -+#define SET_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT)) & 0x0000ffff)) -+#define SET_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT2)) & 0xffff0000)) -+#define SET_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT2)) & 0xfffeffff)) -+#define SET_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT2)) & 0xfffdffff)) -+#define SET_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT2)) & 0xfffbffff)) -+#define SET_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT3)) & 0xffff0000)) -+#define SET_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT3)) & 0x0000ffff)) -+#define SET_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT4)) & 0xffff0000)) -+#define SET_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT4)) & 0xfffeffff)) -+#define SET_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT4)) & 0xfffdffff)) -+#define SET_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT4)) & 0xfffbffff)) -+#define SET_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_CNT4)) & 0xfff7ffff)) -+#define SET_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_CNT4)) & 0xff8fffff)) -+#define SET_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_CNT4)) & 0xf8ffffff)) -+#define SET_RX_RDY(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_TAG)) & 0xfffffffe)) -+#define SET_SDIO_SYS_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_TAG)) & 0xfffffffb)) -+#define SET_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_TAG)) & 0xfffffff7)) -+#define SET_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_TAG)) & 0xffffffef)) -+#define SET_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_TAG)) & 0xffffffdf)) -+#define SET_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_TAG)) & 0xffffffbf)) -+#define SET_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_TAG)) & 0xffffff7f)) -+#define SET_SPI_FN1(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_TAG)) & 0xffff80ff)) -+#define SET_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_INT_TAG)) & 0xffff7fff)) -+#define SET_SPI_HOST_MASK(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_INT_TAG)) & 0xff00ffff)) -+#define SET_I2CM_INT_WDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN)) & 0xfffffffe)) -+#define SET_I2CM_INT_RDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 1) | ((REG32(ADR_I2CM_EN)) & 0xfffffffd)) -+#define SET_I2CM_IDLE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 2) | ((REG32(ADR_I2CM_EN)) & 0xfffffffb)) -+#define SET_I2CM_INT_MISMATCH(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 3) | ((REG32(ADR_I2CM_EN)) & 0xfffffff7)) -+#define SET_I2CM_PSCL(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 4) | ((REG32(ADR_I2CM_EN)) & 0xffffc00f)) -+#define SET_I2CM_MANUAL_MODE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN)) & 0xfffeffff)) -+#define SET_I2CM_INT_WDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN)) & 0xfffdffff)) -+#define SET_I2CM_INT_RDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 18) | ((REG32(ADR_I2CM_EN)) & 0xfffbffff)) -+#define SET_I2CM_DEV_A(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_DEV_A)) & 0xfffffc00)) -+#define SET_I2CM_DEV_A10B(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 14) | ((REG32(ADR_I2CM_DEV_A)) & 0xffffbfff)) -+#define SET_I2CM_RX(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 15) | ((REG32(ADR_I2CM_DEV_A)) & 0xffff7fff)) -+#define SET_I2CM_LEN(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_LEN)) & 0xffff0000)) -+#define SET_I2CM_T_LEFT(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_LEN)) & 0xfff8ffff)) -+#define SET_I2CM_R_GET(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 24) | ((REG32(ADR_I2CM_LEN)) & 0xf8ffffff)) -+#define SET_I2CM_WDAT(_VAL_) (REG32(ADR_I2CM_WDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_WDAT)) & 0x00000000)) -+#define SET_I2CM_RDAT(_VAL_) (REG32(ADR_I2CM_RDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_RDAT)) & 0x00000000)) -+#define SET_I2CM_SR_LEN(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN_2)) & 0xffff0000)) -+#define SET_I2CM_SR_RX(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN_2)) & 0xfffeffff)) -+#define SET_I2CM_REPEAT_START(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN_2)) & 0xfffdffff)) -+#define SET_UART_DATA(_VAL_) (REG32(ADR_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_UART_DATA)) & 0xffffff00)) -+#define SET_DATA_RDY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_UART_IER)) & 0xfffffffe)) -+#define SET_THR_EMPTY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_UART_IER)) & 0xfffffffd)) -+#define SET_RX_LINESTS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_UART_IER)) & 0xfffffffb)) -+#define SET_MDM_STS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_UART_IER)) & 0xfffffff7)) -+#define SET_DMA_RXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_UART_IER)) & 0xffffffbf)) -+#define SET_DMA_TXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_UART_IER)) & 0xffffff7f)) -+#define SET_FIFO_EN(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_FCR)) & 0xfffffffe)) -+#define SET_RXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_FCR)) & 0xfffffffd)) -+#define SET_TXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_FCR)) & 0xfffffffb)) -+#define SET_DMA_MODE(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_FCR)) & 0xfffffff7)) -+#define SET_EN_AUTO_RTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_FCR)) & 0xffffffef)) -+#define SET_EN_AUTO_CTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_FCR)) & 0xffffffdf)) -+#define SET_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_FCR)) & 0xffffff3f)) -+#define SET_WORD_LEN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LCR)) & 0xfffffffc)) -+#define SET_STOP_BIT(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LCR)) & 0xfffffffb)) -+#define SET_PARITY_EN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LCR)) & 0xfffffff7)) -+#define SET_EVEN_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LCR)) & 0xffffffef)) -+#define SET_FORCE_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LCR)) & 0xffffffdf)) -+#define SET_SET_BREAK(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LCR)) & 0xffffffbf)) -+#define SET_DLAB(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LCR)) & 0xffffff7f)) -+#define SET_DTR(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MCR)) & 0xfffffffe)) -+#define SET_RTS(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MCR)) & 0xfffffffd)) -+#define SET_OUT_1(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MCR)) & 0xfffffffb)) -+#define SET_OUT_2(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MCR)) & 0xfffffff7)) -+#define SET_LOOP_BACK(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MCR)) & 0xffffffef)) -+#define SET_DATA_RDY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LSR)) & 0xfffffffe)) -+#define SET_OVERRUN_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_LSR)) & 0xfffffffd)) -+#define SET_PARITY_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LSR)) & 0xfffffffb)) -+#define SET_FRAMING_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LSR)) & 0xfffffff7)) -+#define SET_BREAK_INT(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LSR)) & 0xffffffef)) -+#define SET_THR_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LSR)) & 0xffffffdf)) -+#define SET_TX_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LSR)) & 0xffffffbf)) -+#define SET_FIFODATA_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LSR)) & 0xffffff7f)) -+#define SET_DELTA_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MSR)) & 0xfffffffe)) -+#define SET_DELTA_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MSR)) & 0xfffffffd)) -+#define SET_TRAILEDGE_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MSR)) & 0xfffffffb)) -+#define SET_DELTA_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MSR)) & 0xfffffff7)) -+#define SET_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MSR)) & 0xffffffef)) -+#define SET_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_MSR)) & 0xffffffdf)) -+#define SET_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_MSR)) & 0xffffffbf)) -+#define SET_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_MSR)) & 0xffffff7f)) -+#define SET_BRDC_DIV(_VAL_) (REG32(ADR_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_SPR)) & 0xffff0000)) -+#define SET_RTHR_L(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_RTHR)) & 0xfffffff0)) -+#define SET_RTHR_H(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_RTHR)) & 0xffffff0f)) -+#define SET_INT_IDCODE(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_ISR)) & 0xfffffff0)) -+#define SET_FIFOS_ENABLED(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_ISR)) & 0xffffff3f)) -+#define SET_DAT_UART_DATA(_VAL_) (REG32(ADR_DAT_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_DATA)) & 0xffffff00)) -+#define SET_DAT_DATA_RDY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffe)) -+#define SET_DAT_THR_EMPTY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffd)) -+#define SET_DAT_RX_LINESTS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffb)) -+#define SET_DAT_MDM_STS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffff7)) -+#define SET_DAT_DMA_RXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_IER)) & 0xffffffbf)) -+#define SET_DAT_DMA_TXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_IER)) & 0xffffff7f)) -+#define SET_DAT_FIFO_EN(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffe)) -+#define SET_DAT_RXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffd)) -+#define SET_DAT_TXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffb)) -+#define SET_DAT_DMA_MODE(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffff7)) -+#define SET_DAT_EN_AUTO_RTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffef)) -+#define SET_DAT_EN_AUTO_CTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffdf)) -+#define SET_DAT_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffff3f)) -+#define SET_DAT_WORD_LEN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffc)) -+#define SET_DAT_STOP_BIT(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffb)) -+#define SET_DAT_PARITY_EN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffff7)) -+#define SET_DAT_EVEN_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffef)) -+#define SET_DAT_FORCE_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffdf)) -+#define SET_DAT_SET_BREAK(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffbf)) -+#define SET_DAT_DLAB(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffff7f)) -+#define SET_DAT_DTR(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffe)) -+#define SET_DAT_RTS(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffd)) -+#define SET_DAT_OUT_1(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffb)) -+#define SET_DAT_OUT_2(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffff7)) -+#define SET_DAT_LOOP_BACK(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MCR)) & 0xffffffef)) -+#define SET_DAT_DATA_RDY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffe)) -+#define SET_DAT_OVERRUN_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffd)) -+#define SET_DAT_PARITY_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffb)) -+#define SET_DAT_FRAMING_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffff7)) -+#define SET_DAT_BREAK_INT(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffef)) -+#define SET_DAT_THR_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffdf)) -+#define SET_DAT_TX_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffbf)) -+#define SET_DAT_FIFODATA_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffff7f)) -+#define SET_DAT_DELTA_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffe)) -+#define SET_DAT_DELTA_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffd)) -+#define SET_DAT_TRAILEDGE_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffb)) -+#define SET_DAT_DELTA_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffff7)) -+#define SET_DAT_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffef)) -+#define SET_DAT_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffdf)) -+#define SET_DAT_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffbf)) -+#define SET_DAT_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffff7f)) -+#define SET_DAT_BRDC_DIV(_VAL_) (REG32(ADR_DAT_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_SPR)) & 0xffff0000)) -+#define SET_DAT_RTHR_L(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_RTHR)) & 0xfffffff0)) -+#define SET_DAT_RTHR_H(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_RTHR)) & 0xffffff0f)) -+#define SET_DAT_INT_IDCODE(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_ISR)) & 0xfffffff0)) -+#define SET_DAT_FIFOS_ENABLED(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_ISR)) & 0xffffff3f)) -+#define SET_MASK_TOP(_VAL_) (REG32(ADR_INT_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK)) & 0x00000000)) -+#define SET_INT_MODE(_VAL_) (REG32(ADR_INT_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MODE)) & 0x00000000)) -+#define SET_IRQ_PHY_0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffe)) -+#define SET_IRQ_PHY_1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffd)) -+#define SET_IRQ_SDIO(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffb)) -+#define SET_IRQ_BEACON_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffff7)) -+#define SET_IRQ_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffef)) -+#define SET_IRQ_PRE_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffdf)) -+#define SET_IRQ_EDCA0_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffbf)) -+#define SET_IRQ_EDCA1_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffff7f)) -+#define SET_IRQ_EDCA2_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffeff)) -+#define SET_IRQ_EDCA3_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffdff)) -+#define SET_IRQ_EDCA4_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffbff)) -+#define SET_IRQ_BEACON_DTIM(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffefff)) -+#define SET_IRQ_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffdfff)) -+#define SET_IRQ_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffbfff)) -+#define SET_IRQ_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_IRQ_STS)) & 0xffff7fff)) -+#define SET_IRQ_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffeffff)) -+#define SET_IRQ_FENCE_HIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffdffff)) -+#define SET_IRQ_ILL_ADDR_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffbffff)) -+#define SET_IRQ_MBOX(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_IRQ_STS)) & 0xfff7ffff)) -+#define SET_IRQ_US_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_IRQ_STS)) & 0xffefffff)) -+#define SET_IRQ_US_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_IRQ_STS)) & 0xffdfffff)) -+#define SET_IRQ_US_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_IRQ_STS)) & 0xffbfffff)) -+#define SET_IRQ_US_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_IRQ_STS)) & 0xff7fffff)) -+#define SET_IRQ_MS_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_IRQ_STS)) & 0xfeffffff)) -+#define SET_IRQ_MS_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_IRQ_STS)) & 0xfdffffff)) -+#define SET_IRQ_MS_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_IRQ_STS)) & 0xfbffffff)) -+#define SET_IRQ_MS_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_IRQ_STS)) & 0xf7ffffff)) -+#define SET_IRQ_TX_LIMIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_IRQ_STS)) & 0xefffffff)) -+#define SET_IRQ_DMA0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_IRQ_STS)) & 0xdfffffff)) -+#define SET_IRQ_CO_DMA(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_IRQ_STS)) & 0xbfffffff)) -+#define SET_IRQ_PERI_GROUP(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_IRQ_STS)) & 0x7fffffff)) -+#define SET_FIQ_STATUS(_VAL_) (REG32(ADR_INT_FIQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_STS)) & 0x00000000)) -+#define SET_IRQ_RAW(_VAL_) (REG32(ADR_INT_IRQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_RAW)) & 0x00000000)) -+#define SET_FIQ_RAW(_VAL_) (REG32(ADR_INT_FIQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_RAW)) & 0x00000000)) -+#define SET_INT_PERI_MASK(_VAL_) (REG32(ADR_INT_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_MASK)) & 0x00000000)) -+#define SET_PERI_RTC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffe)) -+#define SET_IRQ_UART0_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffd)) -+#define SET_IRQ_UART0_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffb)) -+#define SET_PERI_GPI_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffff7)) -+#define SET_IRQ_SPI_IPC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_PERI_STS)) & 0xffffffef)) -+#define SET_PERI_GPI_1_0(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff9f)) -+#define SET_SCRT_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff7f)) -+#define SET_MMU_ALC_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffeff)) -+#define SET_MMU_RLS_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffdff)) -+#define SET_ID_MNG_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffbff)) -+#define SET_MBOX_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_INT_PERI_STS)) & 0xfffff7ff)) -+#define SET_MBOX_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_PERI_STS)) & 0xffffefff)) -+#define SET_MBOX_INT_3(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_PERI_STS)) & 0xffffdfff)) -+#define SET_HCI_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_PERI_STS)) & 0xffffbfff)) -+#define SET_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_PERI_STS)) & 0xffff7fff)) -+#define SET_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_PERI_STS)) & 0xfffeffff)) -+#define SET_ID_MNG_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_PERI_STS)) & 0xfffdffff)) -+#define SET_DMN_NOHIT_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_PERI_STS)) & 0xfffbffff)) -+#define SET_ID_THOLD_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_PERI_STS)) & 0xfff7ffff)) -+#define SET_ID_THOLD_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_PERI_STS)) & 0xffefffff)) -+#define SET_ID_DOUBLE_RLS(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_PERI_STS)) & 0xffdfffff)) -+#define SET_RX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_PERI_STS)) & 0xffbfffff)) -+#define SET_TX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_PERI_STS)) & 0xff7fffff)) -+#define SET_ALL_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_PERI_STS)) & 0xfeffffff)) -+#define SET_DMN_MCU_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_PERI_STS)) & 0xfdffffff)) -+#define SET_IRQ_DAT_UART_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_PERI_STS)) & 0xfbffffff)) -+#define SET_IRQ_DAT_UART_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_PERI_STS)) & 0xf7ffffff)) -+#define SET_DAT_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_PERI_STS)) & 0xefffffff)) -+#define SET_DAT_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_PERI_STS)) & 0xdfffffff)) -+#define SET_ALR_ABT_NOCHG_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_PERI_STS)) & 0xbfffffff)) -+#define SET_TBLNEQ_MNGPKT_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_PERI_STS)) & 0x7fffffff)) -+#define SET_INTR_PERI_RAW(_VAL_) (REG32(ADR_INT_PERI_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_RAW)) & 0x00000000)) -+#define SET_INTR_GPI00_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffffc)) -+#define SET_INTR_GPI01_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffff3)) -+#define SET_SYS_RST_INT(_VAL_) (REG32(ADR_SYS_INT_FOR_HOST)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_INT_FOR_HOST)) & 0xfffffffe)) -+#define SET_SPI_IPC_ADDR(_VAL_) (REG32(ADR_SPI_IPC)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_IPC)) & 0x00000000)) -+#define SET_SD_MASK_TOP(_VAL_) (REG32(ADR_SDIO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_MASK)) & 0x00000000)) -+#define SET_IRQ_PHY_0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffe)) -+#define SET_IRQ_PHY_1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffd)) -+#define SET_IRQ_SDIO_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffb)) -+#define SET_IRQ_BEACON_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffff7)) -+#define SET_IRQ_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffef)) -+#define SET_IRQ_PRE_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffdf)) -+#define SET_IRQ_EDCA0_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffbf)) -+#define SET_IRQ_EDCA1_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffff7f)) -+#define SET_IRQ_EDCA2_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffeff)) -+#define SET_IRQ_EDCA3_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffdff)) -+#define SET_IRQ_EDCA4_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffbff)) -+#define SET_IRQ_BEACON_DTIM_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffefff)) -+#define SET_IRQ_EDCA0_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffdfff)) -+#define SET_IRQ_EDCA1_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffbfff)) -+#define SET_IRQ_EDCA2_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffff7fff)) -+#define SET_IRQ_EDCA3_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffeffff)) -+#define SET_IRQ_FENCE_HIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffdffff)) -+#define SET_IRQ_ILL_ADDR_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffbffff)) -+#define SET_IRQ_MBOX_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfff7ffff)) -+#define SET_IRQ_US_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffefffff)) -+#define SET_IRQ_US_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffdfffff)) -+#define SET_IRQ_US_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffbfffff)) -+#define SET_IRQ_US_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xff7fffff)) -+#define SET_IRQ_MS_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfeffffff)) -+#define SET_IRQ_MS_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfdffffff)) -+#define SET_IRQ_MS_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfbffffff)) -+#define SET_IRQ_MS_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xf7ffffff)) -+#define SET_IRQ_TX_LIMIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xefffffff)) -+#define SET_IRQ_DMA0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xdfffffff)) -+#define SET_IRQ_CO_DMA_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xbfffffff)) -+#define SET_IRQ_PERI_GROUP_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SDIO_IRQ_STS)) & 0x7fffffff)) -+#define SET_INT_PERI_MASK_SD(_VAL_) (REG32(ADR_SD_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_MASK)) & 0x00000000)) -+#define SET_PERI_RTC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffe)) -+#define SET_IRQ_UART0_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffd)) -+#define SET_IRQ_UART0_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffb)) -+#define SET_PERI_GPI_SD_2(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffff7)) -+#define SET_IRQ_SPI_IPC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SD_PERI_STS)) & 0xffffffef)) -+#define SET_PERI_GPI_SD_1_0(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff9f)) -+#define SET_SCRT_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff7f)) -+#define SET_MMU_ALC_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffeff)) -+#define SET_MMU_RLS_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffdff)) -+#define SET_ID_MNG_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffbff)) -+#define SET_MBOX_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_SD_PERI_STS)) & 0xfffff7ff)) -+#define SET_MBOX_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SD_PERI_STS)) & 0xffffefff)) -+#define SET_MBOX_INT_3_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SD_PERI_STS)) & 0xffffdfff)) -+#define SET_HCI_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SD_PERI_STS)) & 0xffffbfff)) -+#define SET_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SD_PERI_STS)) & 0xffff7fff)) -+#define SET_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SD_PERI_STS)) & 0xfffeffff)) -+#define SET_ID_MNG_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SD_PERI_STS)) & 0xfffdffff)) -+#define SET_DMN_NOHIT_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SD_PERI_STS)) & 0xfffbffff)) -+#define SET_ID_THOLD_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SD_PERI_STS)) & 0xfff7ffff)) -+#define SET_ID_THOLD_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SD_PERI_STS)) & 0xffefffff)) -+#define SET_ID_DOUBLE_RLS_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SD_PERI_STS)) & 0xffdfffff)) -+#define SET_RX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SD_PERI_STS)) & 0xffbfffff)) -+#define SET_TX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SD_PERI_STS)) & 0xff7fffff)) -+#define SET_ALL_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SD_PERI_STS)) & 0xfeffffff)) -+#define SET_DMN_MCU_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SD_PERI_STS)) & 0xfdffffff)) -+#define SET_IRQ_DAT_UART_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SD_PERI_STS)) & 0xfbffffff)) -+#define SET_IRQ_DAT_UART_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SD_PERI_STS)) & 0xf7ffffff)) -+#define SET_DAT_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SD_PERI_STS)) & 0xefffffff)) -+#define SET_DAT_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SD_PERI_STS)) & 0xdfffffff)) -+#define SET_ALR_ABT_NOCHG_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SD_PERI_STS)) & 0xbfffffff)) -+#define SET_TBLNEQ_MNGPKT_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SD_PERI_STS)) & 0x7fffffff)) -+#define SET_DBG_SPI_MODE(_VAL_) (REG32(ADR_DBG_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_MODE)) & 0x00000000)) -+#define SET_DBG_RX_QUOTA(_VAL_) (REG32(ADR_DBG_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_RX_QUOTA)) & 0xffff0000)) -+#define SET_DBG_CONDI_NUM(_VAL_) (REG32(ADR_DBG_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CONDITION_NUMBER)) & 0xffffff00)) -+#define SET_DBG_HOST_PATH(_VAL_) (REG32(ADR_DBG_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_HOST_PATH)) & 0xfffffffe)) -+#define SET_DBG_TX_SEG(_VAL_) (REG32(ADR_DBG_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_SEG)) & 0x00000000)) -+#define SET_DBG_BRST_MODE(_VAL_) (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0xfffffffe)) -+#define SET_DBG_CLK_WIDTH(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000)) -+#define SET_DBG_CSN_INTER(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff)) -+#define SET_DBG_BACK_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000)) -+#define SET_DBG_FRONT_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff)) -+#define SET_DBG_RX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffd)) -+#define SET_DBG_RX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffb)) -+#define SET_DBG_TX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffff7)) -+#define SET_DBG_TX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffef)) -+#define SET_DBG_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffdf)) -+#define SET_DBG_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffbf)) -+#define SET_DBG_RDATA_RDY(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffff7f)) -+#define SET_DBG_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffeff)) -+#define SET_DBG_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffdff)) -+#define SET_DBG_RX_LEN(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_STS)) & 0x0000ffff)) -+#define SET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffff8)) -+#define SET_DBG_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffeff)) -+#define SET_DBG_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_DBG_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC)) & 0xffffff00)) -+#define SET_DBG_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000)) -+#define SET_DBG_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff)) -+#define SET_DBG_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xffff0000)) -+#define SET_DBG_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffeffff)) -+#define SET_DBG_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffdffff)) -+#define SET_DBG_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffbffff)) -+#define SET_DBG_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000)) -+#define SET_DBG_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff)) -+#define SET_DBG_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xffff0000)) -+#define SET_DBG_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffeffff)) -+#define SET_DBG_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffdffff)) -+#define SET_DBG_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffbffff)) -+#define SET_DBG_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfff7ffff)) -+#define SET_DBG_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xff8fffff)) -+#define SET_DBG_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xf8ffffff)) -+#define SET_DBG_RX_RDY(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffe)) -+#define SET_DBG_SDIO_SYS_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffb)) -+#define SET_DBG_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffff7)) -+#define SET_DBG_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffef)) -+#define SET_DBG_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffdf)) -+#define SET_DBG_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffbf)) -+#define SET_DBG_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffff7f)) -+#define SET_DBG_SPI_FN1(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff80ff)) -+#define SET_DBG_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff7fff)) -+#define SET_DBG_SPI_HOST_MASK(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_INT_TAG)) & 0xff00ffff)) -+#define SET_BOOT_ADDR(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_ADDR)) & 0xff000000)) -+#define SET_CHECK_SUM_FAIL(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_BOOT_ADDR)) & 0x7fffffff)) -+#define SET_VERIFY_DATA(_VAL_) (REG32(ADR_VERIFY_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_VERIFY_DATA)) & 0x00000000)) -+#define SET_FLASH_ADDR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_FLASH_ADDR)) & 0xff000000)) -+#define SET_FLASH_CMD_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 28) | ((REG32(ADR_FLASH_ADDR)) & 0xefffffff)) -+#define SET_FLASH_DMA_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 29) | ((REG32(ADR_FLASH_ADDR)) & 0xdfffffff)) -+#define SET_DMA_EN(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 30) | ((REG32(ADR_FLASH_ADDR)) & 0xbfffffff)) -+#define SET_DMA_BUSY(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_FLASH_ADDR)) & 0x7fffffff)) -+#define SET_SRAM_ADDR(_VAL_) (REG32(ADR_SRAM_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SRAM_ADDR)) & 0x00000000)) -+#define SET_FLASH_DMA_LEN(_VAL_) (REG32(ADR_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_LEN)) & 0x00000000)) -+#define SET_FLASH_FRONT_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM)) & 0xffff0000)) -+#define SET_FLASH_BACK_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM)) & 0x0000ffff)) -+#define SET_FLASH_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM2)) & 0xffff0000)) -+#define SET_SPI_BUSY(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM2)) & 0xfffeffff)) -+#define SET_FLS_REMAP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 17) | ((REG32(ADR_SPI_PARAM2)) & 0xfffdffff)) -+#define SET_PBUS_SWP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 18) | ((REG32(ADR_SPI_PARAM2)) & 0xfffbffff)) -+#define SET_BIT_MODE1(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 19) | ((REG32(ADR_SPI_PARAM2)) & 0xfff7ffff)) -+#define SET_BIT_MODE2(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 20) | ((REG32(ADR_SPI_PARAM2)) & 0xffefffff)) -+#define SET_BIT_MODE4(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 21) | ((REG32(ADR_SPI_PARAM2)) & 0xffdfffff)) -+#define SET_BOOT_CHECK_SUM(_VAL_) (REG32(ADR_CHECK_SUM_RESULT)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_RESULT)) & 0x00000000)) -+#define SET_CHECK_SUM_TAG(_VAL_) (REG32(ADR_CHECK_SUM_IN_FILE)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_IN_FILE)) & 0x00000000)) -+#define SET_CMD_LEN(_VAL_) (REG32(ADR_COMMAND_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_LEN)) & 0xffff0000)) -+#define SET_CMD_ADDR(_VAL_) (REG32(ADR_COMMAND_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_ADDR)) & 0x00000000)) -+#define SET_DMA_ADR_SRC(_VAL_) (REG32(ADR_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_SRC)) & 0x00000000)) -+#define SET_DMA_ADR_DST(_VAL_) (REG32(ADR_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_DST)) & 0x00000000)) -+#define SET_DMA_SRC_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff8)) -+#define SET_DMA_SRC_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff7)) -+#define SET_DMA_DST_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_DMA_CTRL)) & 0xffffff8f)) -+#define SET_DMA_DST_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_DMA_CTRL)) & 0xffffff7f)) -+#define SET_DMA_FAST_FILL(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_CTRL)) & 0xfffffeff)) -+#define SET_DMA_SDIO_KICK(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_DMA_CTRL)) & 0xffffefff)) -+#define SET_DMA_BADR_EN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_DMA_CTRL)) & 0xffffdfff)) -+#define SET_DMA_LEN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_CTRL)) & 0x0000ffff)) -+#define SET_DMA_INT_MASK(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_INT)) & 0xfffffffe)) -+#define SET_DMA_STS(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_INT)) & 0xfffffeff)) -+#define SET_DMA_FINISH(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_DMA_INT)) & 0x7fffffff)) -+#define SET_DMA_CONST(_VAL_) (REG32(ADR_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_FILL_CONST)) & 0x00000000)) -+#define SET_SLEEP_WAKE_CNT(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_0)) & 0xff000000)) -+#define SET_RG_DLDO_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 24) | ((REG32(ADR_PMU_0)) & 0xf8ffffff)) -+#define SET_RG_DLDO_BOOST_IQ(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 27) | ((REG32(ADR_PMU_0)) & 0xf7ffffff)) -+#define SET_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 28) | ((REG32(ADR_PMU_0)) & 0x8fffffff)) -+#define SET_RG_BUCK_VREF_SEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_0)) & 0x7fffffff)) -+#define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_1)) & 0xfffffc00)) -+#define SET_RG_RTC_OSC_RES_SW(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_1)) & 0xfc00ffff)) -+#define SET_RTC_OSC_CAL_RES_RDY(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_1)) & 0x7fffffff)) -+#define SET_RG_DCDC_MODE(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_2)) & 0xfffffffe)) -+#define SET_RG_BUCK_EN_PSM(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_2)) & 0xffffffef)) -+#define SET_RG_BUCK_PSM_VTH(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_2)) & 0xfffffeff)) -+#define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 12) | ((REG32(ADR_PMU_2)) & 0xffffefff)) -+#define SET_RG_RTC_RDY_DEGLITCH_TIMER(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 13) | ((REG32(ADR_PMU_2)) & 0xffff9fff)) -+#define SET_RTC_CAL_ENA(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_2)) & 0xfffeffff)) -+#define SET_PMU_WAKE_TRIG_EVENT(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_3)) & 0xfffffffc)) -+#define SET_DIGI_TOP_POR_MASK(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_3)) & 0xffffffef)) -+#define SET_PMU_ENTER_SLEEP_MODE(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_3)) & 0xfffffeff)) -+#define SET_RG_RTC_DUMMIES(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_3)) & 0x0000ffff)) -+#define SET_RTC_EN(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_1)) & 0xfffffffe)) -+#define SET_RTC_SRC(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_1)) & 0xfffffffd)) -+#define SET_RTC_TICK_CNT(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_1)) & 0x8000ffff)) -+#define SET_RTC_INT_SEC_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_2)) & 0xfffffffe)) -+#define SET_RTC_INT_ALARM_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_2)) & 0xfffffffd)) -+#define SET_RTC_INT_SEC(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_2)) & 0xfffeffff)) -+#define SET_RTC_INT_ALARM(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 17) | ((REG32(ADR_RTC_2)) & 0xfffdffff)) -+#define SET_RTC_SEC_START_CNT(_VAL_) (REG32(ADR_RTC_3W)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3W)) & 0x00000000)) -+#define SET_RTC_SEC_CNT(_VAL_) (REG32(ADR_RTC_3R)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3R)) & 0x00000000)) -+#define SET_RTC_SEC_ALARM_VALUE(_VAL_) (REG32(ADR_RTC_4)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_4)) & 0x00000000)) -+#define SET_D2_DMA_ADR_SRC(_VAL_) (REG32(ADR_D2_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_SRC)) & 0x00000000)) -+#define SET_D2_DMA_ADR_DST(_VAL_) (REG32(ADR_D2_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_DST)) & 0x00000000)) -+#define SET_D2_DMA_SRC_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff8)) -+#define SET_D2_DMA_SRC_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff7)) -+#define SET_D2_DMA_DST_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff8f)) -+#define SET_D2_DMA_DST_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff7f)) -+#define SET_D2_DMA_FAST_FILL(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffeff)) -+#define SET_D2_DMA_SDIO_KICK(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffefff)) -+#define SET_D2_DMA_BADR_EN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffdfff)) -+#define SET_D2_DMA_LEN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_D2_DMA_CTRL)) & 0x0000ffff)) -+#define SET_D2_DMA_INT_MASK(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffffe)) -+#define SET_D2_DMA_STS(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffeff)) -+#define SET_D2_DMA_FINISH(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_D2_DMA_INT)) & 0x7fffffff)) -+#define SET_D2_DMA_CONST(_VAL_) (REG32(ADR_D2_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_FILL_CONST)) & 0x00000000)) -+#define SET_TRAP_UNKNOWN_TYPE(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_CONTROL)) & 0xfffffffe)) -+#define SET_TX_ON_DEMAND_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_CONTROL)) & 0xfffffffd)) -+#define SET_RX_2_HOST(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_CONTROL)) & 0xfffffffb)) -+#define SET_AUTO_SEQNO(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 3) | ((REG32(ADR_CONTROL)) & 0xfffffff7)) -+#define SET_BYPASSS_TX_PARSER_ENCAP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 4) | ((REG32(ADR_CONTROL)) & 0xffffffef)) -+#define SET_HDR_STRIP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 5) | ((REG32(ADR_CONTROL)) & 0xffffffdf)) -+#define SET_ERP_PROTECT(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 6) | ((REG32(ADR_CONTROL)) & 0xffffff3f)) -+#define SET_PRO_VER(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_CONTROL)) & 0xfffffcff)) -+#define SET_TXQ_ID0(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 12) | ((REG32(ADR_CONTROL)) & 0xffff8fff)) -+#define SET_TXQ_ID1(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_CONTROL)) & 0xfff8ffff)) -+#define SET_TX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 20) | ((REG32(ADR_CONTROL)) & 0xffefffff)) -+#define SET_RX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 21) | ((REG32(ADR_CONTROL)) & 0xffdfffff)) -+#define SET_RX_NULL_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 22) | ((REG32(ADR_CONTROL)) & 0xffbfffff)) -+#define SET_RX_GET_TX_QUEUE_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 25) | ((REG32(ADR_CONTROL)) & 0xfdffffff)) -+#define SET_HCI_INQ_SEL(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 26) | ((REG32(ADR_CONTROL)) & 0xfbffffff)) -+#define SET_TRX_DEBUG_CNT_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 28) | ((REG32(ADR_CONTROL)) & 0xefffffff)) -+#define SET_WAKE_SOON_WITH_SCK(_VAL_) (REG32(ADR_SDIO_WAKE_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_WAKE_MODE)) & 0xfffffffe)) -+#define SET_TX_FLOW_CTRL(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_0)) & 0xffff0000)) -+#define SET_TX_FLOW_MGMT(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FLOW_0)) & 0x0000ffff)) -+#define SET_TX_FLOW_DATA(_VAL_) (REG32(ADR_TX_FLOW_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_1)) & 0x00000000)) -+#define SET_DOT11RTSTHRESHOLD(_VAL_) (REG32(ADR_THREASHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_THREASHOLD)) & 0x0000ffff)) -+#define SET_TXF_ID(_VAL_) (REG32(ADR_TXFID_INCREASE)) = (((_VAL_) << 0) | ((REG32(ADR_TXFID_INCREASE)) & 0xffffffc0)) -+#define SET_SEQ_CTRL(_VAL_) (REG32(ADR_GLOBAL_SEQUENCE)) = (((_VAL_) << 0) | ((REG32(ADR_GLOBAL_SEQUENCE)) & 0xffff0000)) -+#define SET_TX_PBOFFSET(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffffff00)) -+#define SET_TX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffff00ff)) -+#define SET_RX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff00ffff)) -+#define SET_RX_LAST_PHY_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ffffff)) -+#define SET_TX_INFO_CLEAR_SIZE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xffffffc0)) -+#define SET_TX_INFO_CLEAR_ENABLE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xfffffeff)) -+#define SET_TXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000)) -+#define SET_TXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff)) -+#define SET_RXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000)) -+#define SET_RXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff)) -+#define SET_TX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_0)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0x00000000)) -+#define SET_RX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_1)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0x00000000)) -+#define SET_HOST_CMD_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_2)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0xffffff00)) -+#define SET_HOST_EVENT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_3)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0xffffff00)) -+#define SET_TX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_4)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0xffffff00)) -+#define SET_RX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_5)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0xffffff00)) -+#define SET_TX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_6)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0xffffff00)) -+#define SET_RX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_7)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0xffffff00)) -+#define SET_HOST_TX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0xffffff00)) -+#define SET_HOST_RX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0xffffff00)) -+#define SET_HCI_STATE_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0x00000000)) -+#define SET_HCI_ST_TIMEOUT_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0x00000000)) -+#define SET_TX_ON_DEMAND_LENGTH(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0x00000000)) -+#define SET_HCI_MONITOR_REG1(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0x00000000)) -+#define SET_HCI_MONITOR_REG2(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0x00000000)) -+#define SET_HCI_TX_ALLOC_TIME_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0x00000000)) -+#define SET_HCI_TX_ALLOC_TIME_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffff0000)) -+#define SET_HCI_MB_MAX_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xff00ffff)) -+#define SET_HCI_TX_ALLOC_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00000000)) -+#define SET_HCI_TX_ALLOC_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xffff0000)) -+#define SET_HCI_PROC_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff00ffff)) -+#define SET_SDIO_TRANS_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ffffff)) -+#define SET_SDIO_TX_INVALID_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0x00000000)) -+#define SET_SDIO_TX_INVALID_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0xffff0000)) -+#define SET_CS_START_ADDR(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_CS_START_ADDR)) & 0xffff0000)) -+#define SET_CS_PKT_ID(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 16) | ((REG32(ADR_CS_START_ADDR)) & 0xff80ffff)) -+#define SET_ADD_LEN(_VAL_) (REG32(ADR_CS_ADD_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_CS_ADD_LEN)) & 0xffff0000)) -+#define SET_CS_ADDER_EN(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CMD)) & 0xfffffffe)) -+#define SET_PSEUDO(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 1) | ((REG32(ADR_CS_CMD)) & 0xfffffffd)) -+#define SET_CALCULATE(_VAL_) (REG32(ADR_CS_INI_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_INI_BUF)) & 0x00000000)) -+#define SET_L4_LEN(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xffff0000)) -+#define SET_L4_PROTOL(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 16) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xff00ffff)) -+#define SET_CHECK_SUM(_VAL_) (REG32(ADR_CS_CHECK_SUM)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CHECK_SUM)) & 0xffff0000)) -+#define SET_RAND_EN(_VAL_) (REG32(ADR_RAND_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_EN)) & 0xfffffffe)) -+#define SET_RAND_NUM(_VAL_) (REG32(ADR_RAND_NUM)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_NUM)) & 0x00000000)) -+#define SET_MUL_OP1(_VAL_) (REG32(ADR_MUL_OP1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP1)) & 0x00000000)) -+#define SET_MUL_OP2(_VAL_) (REG32(ADR_MUL_OP2)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP2)) & 0x00000000)) -+#define SET_MUL_ANS0(_VAL_) (REG32(ADR_MUL_ANS0)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS0)) & 0x00000000)) -+#define SET_MUL_ANS1(_VAL_) (REG32(ADR_MUL_ANS1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS1)) & 0x00000000)) -+#define SET_RD_ADDR(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_RDATA)) & 0xffff0000)) -+#define SET_RD_ID(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_RDATA)) & 0xff80ffff)) -+#define SET_WR_ADDR(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_WDATA)) & 0xffff0000)) -+#define SET_WR_ID(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_WDATA)) & 0xff80ffff)) -+#define SET_LEN(_VAL_) (REG32(ADR_DMA_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_LEN)) & 0xffff0000)) -+#define SET_CLR(_VAL_) (REG32(ADR_DMA_CLR)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CLR)) & 0xfffffffe)) -+#define SET_PHY_MODE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_NAV_DATA)) & 0xfffffffc)) -+#define SET_SHRT_PREAM(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 2) | ((REG32(ADR_NAV_DATA)) & 0xfffffffb)) -+#define SET_SHRT_GI(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 3) | ((REG32(ADR_NAV_DATA)) & 0xfffffff7)) -+#define SET_DATA_RATE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 4) | ((REG32(ADR_NAV_DATA)) & 0xfffff80f)) -+#define SET_MCS(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 12) | ((REG32(ADR_NAV_DATA)) & 0xffff8fff)) -+#define SET_FRAME_LEN(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 16) | ((REG32(ADR_NAV_DATA)) & 0x0000ffff)) -+#define SET_DURATION(_VAL_) (REG32(ADR_CO_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_CO_NAV)) & 0xffff0000)) -+#define SET_SHA_DST_ADDR(_VAL_) (REG32(ADR_SHA_DST_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_DST_ADDR)) & 0x00000000)) -+#define SET_SHA_SRC_ADDR(_VAL_) (REG32(ADR_SHA_SRC_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SRC_ADDR)) & 0x00000000)) -+#define SET_SHA_BUSY(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffe)) -+#define SET_SHA_ENDIAN(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 1) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffd)) -+#define SET_EFS_CLKFREQ(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffff000)) -+#define SET_LOW_ACTIVE(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffeffff)) -+#define SET_EFS_CLKFREQ_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 20) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf00fffff)) -+#define SET_EFS_PRE_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 28) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0fffffff)) -+#define SET_EFS_LDO_ON(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000)) -+#define SET_EFS_LDO_OFF(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff)) -+#define SET_EFS_RDATA_0(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0x00000000)) -+#define SET_EFS_WDATA_0(_VAL_) (REG32(ADR_EFUSE_WDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_0)) & 0x00000000)) -+#define SET_EFS_RDATA_1(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0x00000000)) -+#define SET_EFS_WDATA_1(_VAL_) (REG32(ADR_EFUSE_WDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_1)) & 0x00000000)) -+#define SET_EFS_RDATA_2(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0x00000000)) -+#define SET_EFS_WDATA_2(_VAL_) (REG32(ADR_EFUSE_WDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_2)) & 0x00000000)) -+#define SET_EFS_RDATA_3(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0x00000000)) -+#define SET_EFS_WDATA_3(_VAL_) (REG32(ADR_EFUSE_WDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_3)) & 0x00000000)) -+#define SET_EFS_RDATA_4(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0x00000000)) -+#define SET_EFS_WDATA_4(_VAL_) (REG32(ADR_EFUSE_WDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_4)) & 0x00000000)) -+#define SET_EFS_RDATA_5(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0x00000000)) -+#define SET_EFS_WDATA_5(_VAL_) (REG32(ADR_EFUSE_WDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_5)) & 0x00000000)) -+#define SET_EFS_RDATA_6(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0x00000000)) -+#define SET_EFS_WDATA_6(_VAL_) (REG32(ADR_EFUSE_WDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_6)) & 0x00000000)) -+#define SET_EFS_RDATA_7(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0x00000000)) -+#define SET_EFS_WDATA_7(_VAL_) (REG32(ADR_EFUSE_WDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_7)) & 0x00000000)) -+#define SET_EFS_SPI_RD0_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD0_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0xfffffffe)) -+#define SET_EFS_SPI_RD1_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD1_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0xfffffffe)) -+#define SET_EFS_SPI_RD2_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD2_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0xfffffffe)) -+#define SET_EFS_SPI_RD3_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD3_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0xfffffffe)) -+#define SET_EFS_SPI_RD4_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD4_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0xfffffffe)) -+#define SET_EFS_SPI_RD5_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD5_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0xfffffffe)) -+#define SET_EFS_SPI_RD6_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD6_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0xfffffffe)) -+#define SET_EFS_SPI_RD7_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD7_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0xfffffffe)) -+#define SET_EFS_SPI_RBUSY(_VAL_) (REG32(ADR_EFUSE_SPI_BUSY)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_BUSY)) & 0xfffffffe)) -+#define SET_EFS_SPI_RDATA_0(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0x00000000)) -+#define SET_EFS_SPI_RDATA_1(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0x00000000)) -+#define SET_EFS_SPI_RDATA_2(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0x00000000)) -+#define SET_EFS_SPI_RDATA_3(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0x00000000)) -+#define SET_EFS_SPI_RDATA_4(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0x00000000)) -+#define SET_EFS_SPI_RDATA_5(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0x00000000)) -+#define SET_EFS_SPI_RDATA_6(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0x00000000)) -+#define SET_EFS_SPI_RDATA_7(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0x00000000)) -+#define SET_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffe)) -+#define SET_FORCE_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffd)) -+#define SET_SMS4_DESCRY_EN(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG1)) & 0xffffffef)) -+#define SET_DEC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffe)) -+#define SET_DEC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffd)) -+#define SET_ENC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffb)) -+#define SET_ENC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 3) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffff7)) -+#define SET_KEY_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG2)) & 0xffffffef)) -+#define SET_SMS4_CBC_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffe)) -+#define SET_SMS4_CFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffd)) -+#define SET_SMS4_OFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffb)) -+#define SET_SMS4_START_TRIG(_VAL_) (REG32(ADR_SMS4_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_TRIG)) & 0xfffffffe)) -+#define SET_SMS4_BUSY(_VAL_) (REG32(ADR_SMS4_STATUS1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS1)) & 0xfffffffe)) -+#define SET_SMS4_DONE(_VAL_) (REG32(ADR_SMS4_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS2)) & 0xfffffffe)) -+#define SET_SMS4_DATAIN_0(_VAL_) (REG32(ADR_SMS4_DATA_IN0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN0)) & 0x00000000)) -+#define SET_SMS4_DATAIN_1(_VAL_) (REG32(ADR_SMS4_DATA_IN1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN1)) & 0x00000000)) -+#define SET_SMS4_DATAIN_2(_VAL_) (REG32(ADR_SMS4_DATA_IN2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN2)) & 0x00000000)) -+#define SET_SMS4_DATAIN_3(_VAL_) (REG32(ADR_SMS4_DATA_IN3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN3)) & 0x00000000)) -+#define SET_SMS4_DATAOUT_0(_VAL_) (REG32(ADR_SMS4_DATA_OUT0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT0)) & 0x00000000)) -+#define SET_SMS4_DATAOUT_1(_VAL_) (REG32(ADR_SMS4_DATA_OUT1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT1)) & 0x00000000)) -+#define SET_SMS4_DATAOUT_2(_VAL_) (REG32(ADR_SMS4_DATA_OUT2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT2)) & 0x00000000)) -+#define SET_SMS4_DATAOUT_3(_VAL_) (REG32(ADR_SMS4_DATA_OUT3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT3)) & 0x00000000)) -+#define SET_SMS4_KEY_0(_VAL_) (REG32(ADR_SMS4_KEY_0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_0)) & 0x00000000)) -+#define SET_SMS4_KEY_1(_VAL_) (REG32(ADR_SMS4_KEY_1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_1)) & 0x00000000)) -+#define SET_SMS4_KEY_2(_VAL_) (REG32(ADR_SMS4_KEY_2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_2)) & 0x00000000)) -+#define SET_SMS4_KEY_3(_VAL_) (REG32(ADR_SMS4_KEY_3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_3)) & 0x00000000)) -+#define SET_SMS4_MODE_IV0(_VAL_) (REG32(ADR_SMS4_MODE_IV0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV0)) & 0x00000000)) -+#define SET_SMS4_MODE_IV1(_VAL_) (REG32(ADR_SMS4_MODE_IV1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV1)) & 0x00000000)) -+#define SET_SMS4_MODE_IV2(_VAL_) (REG32(ADR_SMS4_MODE_IV2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV2)) & 0x00000000)) -+#define SET_SMS4_MODE_IV3(_VAL_) (REG32(ADR_SMS4_MODE_IV3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV3)) & 0x00000000)) -+#define SET_SMS4_OFB_ENC0(_VAL_) (REG32(ADR_SMS4_OFB_ENC0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC0)) & 0x00000000)) -+#define SET_SMS4_OFB_ENC1(_VAL_) (REG32(ADR_SMS4_OFB_ENC1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC1)) & 0x00000000)) -+#define SET_SMS4_OFB_ENC2(_VAL_) (REG32(ADR_SMS4_OFB_ENC2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC2)) & 0x00000000)) -+#define SET_SMS4_OFB_ENC3(_VAL_) (REG32(ADR_SMS4_OFB_ENC3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC3)) & 0x00000000)) -+#define SET_MRX_MCAST_TB0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_0)) & 0x00000000)) -+#define SET_MRX_MCAST_TB0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_1)) & 0xffff0000)) -+#define SET_MRX_MCAST_MASK0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_0)) & 0x00000000)) -+#define SET_MRX_MCAST_MASK0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_1)) & 0xffff0000)) -+#define SET_MRX_MCAST_CTRL_0(_VAL_) (REG32(ADR_MRX_MCAST_CTRL0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL0)) & 0xfffffffc)) -+#define SET_MRX_MCAST_TB1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_0)) & 0x00000000)) -+#define SET_MRX_MCAST_TB1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_1)) & 0xffff0000)) -+#define SET_MRX_MCAST_MASK1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_0)) & 0x00000000)) -+#define SET_MRX_MCAST_MASK1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_1)) & 0xffff0000)) -+#define SET_MRX_MCAST_CTRL_1(_VAL_) (REG32(ADR_MRX_MCAST_CTRL1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL1)) & 0xfffffffc)) -+#define SET_MRX_MCAST_TB2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_0)) & 0x00000000)) -+#define SET_MRX_MCAST_TB2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_1)) & 0xffff0000)) -+#define SET_MRX_MCAST_MASK2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_0)) & 0x00000000)) -+#define SET_MRX_MCAST_MASK2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_1)) & 0xffff0000)) -+#define SET_MRX_MCAST_CTRL_2(_VAL_) (REG32(ADR_MRX_MCAST_CTRL2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL2)) & 0xfffffffc)) -+#define SET_MRX_MCAST_TB3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_0)) & 0x00000000)) -+#define SET_MRX_MCAST_TB3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_1)) & 0xffff0000)) -+#define SET_MRX_MCAST_MASK3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_0)) & 0x00000000)) -+#define SET_MRX_MCAST_MASK3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_1)) & 0xffff0000)) -+#define SET_MRX_MCAST_CTRL_3(_VAL_) (REG32(ADR_MRX_MCAST_CTRL3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL3)) & 0xfffffffc)) -+#define SET_MRX_PHY_INFO(_VAL_) (REG32(ADR_MRX_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_PHY_INFO)) & 0x00000000)) -+#define SET_DBG_BA_TYPE(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_DBG)) & 0xffffffc0)) -+#define SET_DBG_BA_SEQ(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 8) | ((REG32(ADR_MRX_BA_DBG)) & 0xfff000ff)) -+#define SET_MRX_FLT_TB0(_VAL_) (REG32(ADR_MRX_FLT_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB0)) & 0xffff8000)) -+#define SET_MRX_FLT_TB1(_VAL_) (REG32(ADR_MRX_FLT_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB1)) & 0xffff8000)) -+#define SET_MRX_FLT_TB2(_VAL_) (REG32(ADR_MRX_FLT_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB2)) & 0xffff8000)) -+#define SET_MRX_FLT_TB3(_VAL_) (REG32(ADR_MRX_FLT_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB3)) & 0xffff8000)) -+#define SET_MRX_FLT_TB4(_VAL_) (REG32(ADR_MRX_FLT_TB4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB4)) & 0xffff8000)) -+#define SET_MRX_FLT_TB5(_VAL_) (REG32(ADR_MRX_FLT_TB5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB5)) & 0xffff8000)) -+#define SET_MRX_FLT_TB6(_VAL_) (REG32(ADR_MRX_FLT_TB6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB6)) & 0xffff8000)) -+#define SET_MRX_FLT_TB7(_VAL_) (REG32(ADR_MRX_FLT_TB7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB7)) & 0xffff8000)) -+#define SET_MRX_FLT_TB8(_VAL_) (REG32(ADR_MRX_FLT_TB8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB8)) & 0xffff8000)) -+#define SET_MRX_FLT_TB9(_VAL_) (REG32(ADR_MRX_FLT_TB9)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB9)) & 0xffff8000)) -+#define SET_MRX_FLT_TB10(_VAL_) (REG32(ADR_MRX_FLT_TB10)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB10)) & 0xffff8000)) -+#define SET_MRX_FLT_TB11(_VAL_) (REG32(ADR_MRX_FLT_TB11)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB11)) & 0xffff8000)) -+#define SET_MRX_FLT_TB12(_VAL_) (REG32(ADR_MRX_FLT_TB12)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB12)) & 0xffff8000)) -+#define SET_MRX_FLT_TB13(_VAL_) (REG32(ADR_MRX_FLT_TB13)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB13)) & 0xffff8000)) -+#define SET_MRX_FLT_TB14(_VAL_) (REG32(ADR_MRX_FLT_TB14)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB14)) & 0xffff8000)) -+#define SET_MRX_FLT_TB15(_VAL_) (REG32(ADR_MRX_FLT_TB15)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB15)) & 0xffff8000)) -+#define SET_MRX_FLT_EN0(_VAL_) (REG32(ADR_MRX_FLT_EN0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN0)) & 0xffff0000)) -+#define SET_MRX_FLT_EN1(_VAL_) (REG32(ADR_MRX_FLT_EN1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN1)) & 0xffff0000)) -+#define SET_MRX_FLT_EN2(_VAL_) (REG32(ADR_MRX_FLT_EN2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN2)) & 0xffff0000)) -+#define SET_MRX_FLT_EN3(_VAL_) (REG32(ADR_MRX_FLT_EN3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN3)) & 0xffff0000)) -+#define SET_MRX_FLT_EN4(_VAL_) (REG32(ADR_MRX_FLT_EN4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN4)) & 0xffff0000)) -+#define SET_MRX_FLT_EN5(_VAL_) (REG32(ADR_MRX_FLT_EN5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN5)) & 0xffff0000)) -+#define SET_MRX_FLT_EN6(_VAL_) (REG32(ADR_MRX_FLT_EN6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN6)) & 0xffff0000)) -+#define SET_MRX_FLT_EN7(_VAL_) (REG32(ADR_MRX_FLT_EN7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN7)) & 0xffff0000)) -+#define SET_MRX_FLT_EN8(_VAL_) (REG32(ADR_MRX_FLT_EN8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN8)) & 0xffff0000)) -+#define SET_MRX_LEN_FLT(_VAL_) (REG32(ADR_MRX_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_LEN_FLT)) & 0xffff0000)) -+#define SET_RX_FLOW_DATA(_VAL_) (REG32(ADR_RX_FLOW_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_DATA)) & 0x00000000)) -+#define SET_RX_FLOW_MNG(_VAL_) (REG32(ADR_RX_FLOW_MNG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_MNG)) & 0xffff0000)) -+#define SET_RX_FLOW_CTRL(_VAL_) (REG32(ADR_RX_FLOW_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_CTRL)) & 0xffff0000)) -+#define SET_MRX_STP_EN(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xfffffffe)) -+#define SET_MRX_STP_OFST(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xffff00ff)) -+#define SET_DBG_FF_FULL(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_FF_FULL)) & 0xffff0000)) -+#define SET_DBG_FF_FULL_CLR(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_FF_FULL)) & 0x7fffffff)) -+#define SET_DBG_WFF_FULL(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_WFF_FULL)) & 0xffff0000)) -+#define SET_DBG_WFF_FULL_CLR(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_WFF_FULL)) & 0x7fffffff)) -+#define SET_DBG_MB_FULL(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_MB_FULL)) & 0xffff0000)) -+#define SET_DBG_MB_FULL_CLR(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_MB_FULL)) & 0x7fffffff)) -+#define SET_BA_CTRL(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BA_CTRL)) & 0xfffffffc)) -+#define SET_BA_DBG_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_BA_CTRL)) & 0xfffffffb)) -+#define SET_BA_AGRE_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_BA_CTRL)) & 0xfffffff7)) -+#define SET_BA_TA_31_0(_VAL_) (REG32(ADR_BA_TA_0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_0)) & 0x00000000)) -+#define SET_BA_TA_47_32(_VAL_) (REG32(ADR_BA_TA_1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_1)) & 0xffff0000)) -+#define SET_BA_TID(_VAL_) (REG32(ADR_BA_TID)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TID)) & 0xfffffff0)) -+#define SET_BA_ST_SEQ(_VAL_) (REG32(ADR_BA_ST_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_BA_ST_SEQ)) & 0xfffff000)) -+#define SET_BA_SB0(_VAL_) (REG32(ADR_BA_SB0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB0)) & 0x00000000)) -+#define SET_BA_SB1(_VAL_) (REG32(ADR_BA_SB1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB1)) & 0x00000000)) -+#define SET_MRX_WD(_VAL_) (REG32(ADR_MRX_WATCH_DOG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_WATCH_DOG)) & 0xfffe0000)) -+#define SET_ACK_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffe)) -+#define SET_BA_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 1) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffd)) -+#define SET_ACK_GEN_DUR(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffff0000)) -+#define SET_ACK_GEN_INFO(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 16) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffc0ffff)) -+#define SET_ACK_GEN_RA_31_0(_VAL_) (REG32(ADR_ACK_GEN_RA_0)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_0)) & 0x00000000)) -+#define SET_ACK_GEN_RA_47_32(_VAL_) (REG32(ADR_ACK_GEN_RA_1)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_1)) & 0xffff0000)) -+#define SET_MIB_LEN_FAIL(_VAL_) (REG32(ADR_MIB_LEN_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_LEN_FAIL)) & 0xffff0000)) -+#define SET_TRAP_HW_ID(_VAL_) (REG32(ADR_TRAP_HW_ID)) = (((_VAL_) << 0) | ((REG32(ADR_TRAP_HW_ID)) & 0xfffffff0)) -+#define SET_ID_IN_USE(_VAL_) (REG32(ADR_ID_IN_USE)) = (((_VAL_) << 0) | ((REG32(ADR_ID_IN_USE)) & 0xffffff00)) -+#define SET_MRX_ERR(_VAL_) (REG32(ADR_MRX_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ERR)) & 0x00000000)) -+#define SET_W0_T0_SEQ(_VAL_) (REG32(ADR_WSID0_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0xffff0000)) -+#define SET_W0_T1_SEQ(_VAL_) (REG32(ADR_WSID0_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0xffff0000)) -+#define SET_W0_T2_SEQ(_VAL_) (REG32(ADR_WSID0_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0xffff0000)) -+#define SET_W0_T3_SEQ(_VAL_) (REG32(ADR_WSID0_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0xffff0000)) -+#define SET_W0_T4_SEQ(_VAL_) (REG32(ADR_WSID0_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0xffff0000)) -+#define SET_W0_T5_SEQ(_VAL_) (REG32(ADR_WSID0_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0xffff0000)) -+#define SET_W0_T6_SEQ(_VAL_) (REG32(ADR_WSID0_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0xffff0000)) -+#define SET_W0_T7_SEQ(_VAL_) (REG32(ADR_WSID0_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0xffff0000)) -+#define SET_W1_T0_SEQ(_VAL_) (REG32(ADR_WSID1_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0xffff0000)) -+#define SET_W1_T1_SEQ(_VAL_) (REG32(ADR_WSID1_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0xffff0000)) -+#define SET_W1_T2_SEQ(_VAL_) (REG32(ADR_WSID1_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0xffff0000)) -+#define SET_W1_T3_SEQ(_VAL_) (REG32(ADR_WSID1_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0xffff0000)) -+#define SET_W1_T4_SEQ(_VAL_) (REG32(ADR_WSID1_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0xffff0000)) -+#define SET_W1_T5_SEQ(_VAL_) (REG32(ADR_WSID1_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0xffff0000)) -+#define SET_W1_T6_SEQ(_VAL_) (REG32(ADR_WSID1_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0xffff0000)) -+#define SET_W1_T7_SEQ(_VAL_) (REG32(ADR_WSID1_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0xffff0000)) -+#define SET_ADDR1A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffffc)) -+#define SET_ADDR2A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 2) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffff3)) -+#define SET_ADDR3A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 4) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffffcf)) -+#define SET_ADDR1B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 6) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffff3f)) -+#define SET_ADDR2B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffcff)) -+#define SET_ADDR3B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 10) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffff3ff)) -+#define SET_ADDR3C_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 12) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffcfff)) -+#define SET_FRM_CTRL(_VAL_) (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (((_VAL_) << 0) | ((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0xffffffc0)) -+#define SET_CSR_PHY_INFO(_VAL_) (REG32(ADR_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_INFO)) & 0xffff8000)) -+#define SET_AMPDU_SIG(_VAL_) (REG32(ADR_AMPDU_SIG)) = (((_VAL_) << 0) | ((REG32(ADR_AMPDU_SIG)) & 0xffffff00)) -+#define SET_MIB_AMPDU(_VAL_) (REG32(ADR_MIB_AMPDU)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_AMPDU)) & 0x00000000)) -+#define SET_LEN_FLT(_VAL_) (REG32(ADR_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_LEN_FLT)) & 0xffff0000)) -+#define SET_MIB_DELIMITER(_VAL_) (REG32(ADR_MIB_DELIMITER)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_DELIMITER)) & 0xffff0000)) -+#define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_STS)) & 0xfffeffff)) -+#define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_STS)) & 0xfffdffff)) -+#define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_STS)) & 0xfffbffff)) -+#define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_STS)) & 0xfff7ffff)) -+#define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_STS)) & 0xffefffff)) -+#define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_STS)) & 0xffdfffff)) -+#define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_STS)) & 0xffbfffff)) -+#define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_STS)) & 0xff7fffff)) -+#define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_STS)) & 0xfeffffff)) -+#define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_STS)) & 0xfdffffff)) -+#define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_EN)) & 0xfffeffff)) -+#define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_EN)) & 0xfffdffff)) -+#define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_EN)) & 0xfffbffff)) -+#define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_EN)) & 0xfff7ffff)) -+#define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_EN)) & 0xffefffff)) -+#define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_EN)) & 0xffdfffff)) -+#define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_EN)) & 0xffbfffff)) -+#define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_EN)) & 0xff7fffff)) -+#define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_EN)) & 0xfeffffff)) -+#define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_EN)) & 0xfdffffff)) -+#define SET_MTX_MTX2PHY_SLOW(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffffe)) -+#define SET_MTX_M2M_SLOW_PRD(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffff1)) -+#define SET_MTX_AMPDU_CRC_AUTO(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffdf)) -+#define SET_MTX_FAST_RSP_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffbf)) -+#define SET_MTX_RAW_DATA_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffff7f)) -+#define SET_MTX_ACK_DUR0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffeff)) -+#define SET_MTX_TSF_AUTO_BCN(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffbff)) -+#define SET_MTX_TSF_AUTO_MISC(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffff7ff)) -+#define SET_MTX_FORCE_CS_IDLE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffefff)) -+#define SET_MTX_FORCE_BKF_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffdfff)) -+#define SET_MTX_FORCE_DMA_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffbfff)) -+#define SET_MTX_FORCE_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_MISC_EN)) & 0xffff7fff)) -+#define SET_MTX_HALT_Q_MB(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_MISC_EN)) & 0xffc0ffff)) -+#define SET_MTX_CTS_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_MISC_EN)) & 0xffbfffff)) -+#define SET_MTX_AMPDU_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_MISC_EN)) & 0xff7fffff)) -+#define SET_MTX_EDCCA_TOUT(_VAL_) (REG32(ADR_MTX_EDCCA_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_EDCCA_TOUT)) & 0xfffffc00)) -+#define SET_MTX_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffffd)) -+#define SET_MTX_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffff7)) -+#define SET_MTX_EN_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffffd)) -+#define SET_MTX_EN_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffff7)) -+#define SET_MTX_BCN_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffe)) -+#define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffd)) -+#define SET_MTX_TSF_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffdf)) -+#define SET_MTX_HALT_MNG_UNTIL_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffbf)) -+#define SET_MTX_INT_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffff00ff)) -+#define SET_MTX_AUTO_FLUSH_Q4(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffeffff)) -+#define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffffe)) -+#define SET_MTX_BCN_CFG_VLD(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff9)) -+#define SET_MTX_AUTO_BCN_ONGOING(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff7)) -+#define SET_MTX_BCN_TIMER(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_MISC)) & 0x0000ffff)) -+#define SET_MTX_BCN_PERIOD(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_PRD)) & 0xffff0000)) -+#define SET_MTX_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_BCN_PRD)) & 0x00ffffff)) -+#define SET_MTX_BCN_TSF_L(_VAL_) (REG32(ADR_MTX_BCN_TSF_L)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_L)) & 0x00000000)) -+#define SET_MTX_BCN_TSF_U(_VAL_) (REG32(ADR_MTX_BCN_TSF_U)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_U)) & 0x00000000)) -+#define SET_MTX_BCN_PKT_ID0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xffffff80)) -+#define SET_MTX_DTIM_OFST0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xfc00ffff)) -+#define SET_MTX_BCN_PKT_ID1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xffffff80)) -+#define SET_MTX_DTIM_OFST1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xfc00ffff)) -+#define SET_MTX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffe)) -+#define SET_MRX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffd)) -+#define SET_MTX_DMA_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 2) | ((REG32(ADR_MTX_STATUS)) & 0xffffffe3)) -+#define SET_CH_ST_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_STATUS)) & 0xffffff1f)) -+#define SET_MTX_GNT_LOCK(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_STATUS)) & 0xfffffeff)) -+#define SET_MTX_DMA_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MTX_STATUS)) & 0xfffffdff)) -+#define SET_MTX_Q_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_STATUS)) & 0xfffffbff)) -+#define SET_MTX_TX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_STATUS)) & 0xfffff7ff)) -+#define SET_MRX_RX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_STATUS)) & 0xffffefff)) -+#define SET_DBG_PRTC_PRD(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_STATUS)) & 0xffffdfff)) -+#define SET_DBG_DMA_RDY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_STATUS)) & 0xffffbfff)) -+#define SET_DBG_WAIT_RSP(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_STATUS)) & 0xffff7fff)) -+#define SET_DBG_CFRM_BUSY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_STATUS)) & 0xfffeffff)) -+#define SET_DBG_RST(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffe)) -+#define SET_DBG_MODE(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffd)) -+#define SET_MB_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000)) -+#define SET_RX_EN_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff)) -+#define SET_RX_CS_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000)) -+#define SET_TX_CCA_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff)) -+#define SET_Q_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000)) -+#define SET_CH_STA0_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff)) -+#define SET_MTX_DUR_RSP_TOUT_B(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffffff00)) -+#define SET_MTX_DUR_RSP_TOUT_G(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffff00ff)) -+#define SET_MTX_DUR_RSP_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffffff00)) -+#define SET_MTX_DUR_BURST_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffff00ff)) -+#define SET_MTX_DUR_SLOT(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffc0ffff)) -+#define SET_MTX_DUR_RSP_EIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_IFS)) & 0x003fffff)) -+#define SET_MTX_DUR_RSP_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffffff00)) -+#define SET_MTX_DUR_BURST_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffff00ff)) -+#define SET_MTX_DUR_SLOT_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc0ffff)) -+#define SET_MTX_DUR_RSP_EIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003fffff)) -+#define SET_CH_STA1_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000)) -+#define SET_CH_STA2_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff)) -+#define SET_MTX_NAV(_VAL_) (REG32(ADR_MTX_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_NAV)) & 0xffff0000)) -+#define SET_MTX_MIB_CNT0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xc0000000)) -+#define SET_MTX_MIB_EN0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xbfffffff)) -+#define SET_MTX_MIB_CNT1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xc0000000)) -+#define SET_MTX_MIB_EN1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xbfffffff)) -+#define SET_CH_STA3_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000)) -+#define SET_CH_STA4_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff)) -+#define SET_TXQ0_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffd)) -+#define SET_TXQ0_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffb)) -+#define SET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffff7)) -+#define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffef)) -+#define SET_TXQ0_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffdf)) -+#define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffff3f)) -+#define SET_TXQ0_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffffff0)) -+#define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffff0ff)) -+#define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0fff)) -+#define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000ffff)) -+#define SET_TXQ0_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0xffff0000)) -+#define SET_TXQ0_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffffff00)) -+#define SET_TXQ0_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffff00ff)) -+#define SET_TXQ0_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0x00000000)) -+#define SET_TXQ0_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0xffff0000)) -+#define SET_TXQ0_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0xffff0000)) -+#define SET_TXQ1_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffd)) -+#define SET_TXQ1_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffb)) -+#define SET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffff7)) -+#define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffef)) -+#define SET_TXQ1_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffdf)) -+#define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffff3f)) -+#define SET_TXQ1_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffffff0)) -+#define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffff0ff)) -+#define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0fff)) -+#define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000ffff)) -+#define SET_TXQ1_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0xffff0000)) -+#define SET_TXQ1_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffffff00)) -+#define SET_TXQ1_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffff00ff)) -+#define SET_TXQ1_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0x00000000)) -+#define SET_TXQ1_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0xffff0000)) -+#define SET_TXQ1_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0xffff0000)) -+#define SET_TXQ2_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffd)) -+#define SET_TXQ2_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffb)) -+#define SET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffff7)) -+#define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffef)) -+#define SET_TXQ2_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffdf)) -+#define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffff3f)) -+#define SET_TXQ2_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffffff0)) -+#define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffff0ff)) -+#define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0fff)) -+#define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000ffff)) -+#define SET_TXQ2_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0xffff0000)) -+#define SET_TXQ2_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffffff00)) -+#define SET_TXQ2_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffff00ff)) -+#define SET_TXQ2_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0x00000000)) -+#define SET_TXQ2_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0xffff0000)) -+#define SET_TXQ2_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0xffff0000)) -+#define SET_TXQ3_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffd)) -+#define SET_TXQ3_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffb)) -+#define SET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffff7)) -+#define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffef)) -+#define SET_TXQ3_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffdf)) -+#define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffff3f)) -+#define SET_TXQ3_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffffff0)) -+#define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffff0ff)) -+#define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0fff)) -+#define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000ffff)) -+#define SET_TXQ3_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0xffff0000)) -+#define SET_TXQ3_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffffff00)) -+#define SET_TXQ3_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffff00ff)) -+#define SET_TXQ3_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0x00000000)) -+#define SET_TXQ3_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0xffff0000)) -+#define SET_TXQ3_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0xffff0000)) -+#define SET_TXQ4_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffd)) -+#define SET_TXQ4_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffb)) -+#define SET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffff7)) -+#define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffef)) -+#define SET_TXQ4_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffdf)) -+#define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffff3f)) -+#define SET_TXQ4_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffffff0)) -+#define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffff0ff)) -+#define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0fff)) -+#define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000ffff)) -+#define SET_TXQ4_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0xffff0000)) -+#define SET_TXQ4_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffffff00)) -+#define SET_TXQ4_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffff00ff)) -+#define SET_TXQ4_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0x00000000)) -+#define SET_TXQ4_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0xffff0000)) -+#define SET_TXQ4_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0xffff0000)) -+#define SET_VALID0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0)) & 0xfffffffe)) -+#define SET_PEER_QOS_EN0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 1) | ((REG32(ADR_WSID0)) & 0xfffffffd)) -+#define SET_PEER_OP_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 2) | ((REG32(ADR_WSID0)) & 0xfffffff3)) -+#define SET_PEER_HT_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 4) | ((REG32(ADR_WSID0)) & 0xffffffcf)) -+#define SET_PEER_MAC0_31_0(_VAL_) (REG32(ADR_PEER_MAC0_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_0)) & 0x00000000)) -+#define SET_PEER_MAC0_47_32(_VAL_) (REG32(ADR_PEER_MAC0_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_1)) & 0xffff0000)) -+#define SET_TX_ACK_POLICY_0_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_0)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_0_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_0_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_1)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_0_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_0_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_2)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_0_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_0_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_3)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_0_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_0_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_4)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_0_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_0_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_5)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_0_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_0_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_6)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_0_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_0_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_7)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_0_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0xfffff000)) -+#define SET_VALID1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1)) & 0xfffffffe)) -+#define SET_PEER_QOS_EN1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 1) | ((REG32(ADR_WSID1)) & 0xfffffffd)) -+#define SET_PEER_OP_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 2) | ((REG32(ADR_WSID1)) & 0xfffffff3)) -+#define SET_PEER_HT_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 4) | ((REG32(ADR_WSID1)) & 0xffffffcf)) -+#define SET_PEER_MAC1_31_0(_VAL_) (REG32(ADR_PEER_MAC1_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_0)) & 0x00000000)) -+#define SET_PEER_MAC1_47_32(_VAL_) (REG32(ADR_PEER_MAC1_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_1)) & 0xffff0000)) -+#define SET_TX_ACK_POLICY_1_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_0)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_1_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_1_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_1)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_1_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_1_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_2)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_1_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_1_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_3)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_1_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_1_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_4)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_1_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_1_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_5)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_1_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_1_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_6)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_1_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0xfffff000)) -+#define SET_TX_ACK_POLICY_1_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_7)) & 0xfffffffc)) -+#define SET_TX_SEQ_CTRL_1_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0xfffff000)) -+#define SET_INFO0(_VAL_) (REG32(ADR_INFO0)) = (((_VAL_) << 0) | ((REG32(ADR_INFO0)) & 0x00000000)) -+#define SET_INFO1(_VAL_) (REG32(ADR_INFO1)) = (((_VAL_) << 0) | ((REG32(ADR_INFO1)) & 0x00000000)) -+#define SET_INFO2(_VAL_) (REG32(ADR_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_INFO2)) & 0x00000000)) -+#define SET_INFO3(_VAL_) (REG32(ADR_INFO3)) = (((_VAL_) << 0) | ((REG32(ADR_INFO3)) & 0x00000000)) -+#define SET_INFO4(_VAL_) (REG32(ADR_INFO4)) = (((_VAL_) << 0) | ((REG32(ADR_INFO4)) & 0x00000000)) -+#define SET_INFO5(_VAL_) (REG32(ADR_INFO5)) = (((_VAL_) << 0) | ((REG32(ADR_INFO5)) & 0x00000000)) -+#define SET_INFO6(_VAL_) (REG32(ADR_INFO6)) = (((_VAL_) << 0) | ((REG32(ADR_INFO6)) & 0x00000000)) -+#define SET_INFO7(_VAL_) (REG32(ADR_INFO7)) = (((_VAL_) << 0) | ((REG32(ADR_INFO7)) & 0x00000000)) -+#define SET_INFO8(_VAL_) (REG32(ADR_INFO8)) = (((_VAL_) << 0) | ((REG32(ADR_INFO8)) & 0x00000000)) -+#define SET_INFO9(_VAL_) (REG32(ADR_INFO9)) = (((_VAL_) << 0) | ((REG32(ADR_INFO9)) & 0x00000000)) -+#define SET_INFO10(_VAL_) (REG32(ADR_INFO10)) = (((_VAL_) << 0) | ((REG32(ADR_INFO10)) & 0x00000000)) -+#define SET_INFO11(_VAL_) (REG32(ADR_INFO11)) = (((_VAL_) << 0) | ((REG32(ADR_INFO11)) & 0x00000000)) -+#define SET_INFO12(_VAL_) (REG32(ADR_INFO12)) = (((_VAL_) << 0) | ((REG32(ADR_INFO12)) & 0x00000000)) -+#define SET_INFO13(_VAL_) (REG32(ADR_INFO13)) = (((_VAL_) << 0) | ((REG32(ADR_INFO13)) & 0x00000000)) -+#define SET_INFO14(_VAL_) (REG32(ADR_INFO14)) = (((_VAL_) << 0) | ((REG32(ADR_INFO14)) & 0x00000000)) -+#define SET_INFO15(_VAL_) (REG32(ADR_INFO15)) = (((_VAL_) << 0) | ((REG32(ADR_INFO15)) & 0x00000000)) -+#define SET_INFO16(_VAL_) (REG32(ADR_INFO16)) = (((_VAL_) << 0) | ((REG32(ADR_INFO16)) & 0x00000000)) -+#define SET_INFO17(_VAL_) (REG32(ADR_INFO17)) = (((_VAL_) << 0) | ((REG32(ADR_INFO17)) & 0x00000000)) -+#define SET_INFO18(_VAL_) (REG32(ADR_INFO18)) = (((_VAL_) << 0) | ((REG32(ADR_INFO18)) & 0x00000000)) -+#define SET_INFO19(_VAL_) (REG32(ADR_INFO19)) = (((_VAL_) << 0) | ((REG32(ADR_INFO19)) & 0x00000000)) -+#define SET_INFO20(_VAL_) (REG32(ADR_INFO20)) = (((_VAL_) << 0) | ((REG32(ADR_INFO20)) & 0x00000000)) -+#define SET_INFO21(_VAL_) (REG32(ADR_INFO21)) = (((_VAL_) << 0) | ((REG32(ADR_INFO21)) & 0x00000000)) -+#define SET_INFO22(_VAL_) (REG32(ADR_INFO22)) = (((_VAL_) << 0) | ((REG32(ADR_INFO22)) & 0x00000000)) -+#define SET_INFO23(_VAL_) (REG32(ADR_INFO23)) = (((_VAL_) << 0) | ((REG32(ADR_INFO23)) & 0x00000000)) -+#define SET_INFO24(_VAL_) (REG32(ADR_INFO24)) = (((_VAL_) << 0) | ((REG32(ADR_INFO24)) & 0x00000000)) -+#define SET_INFO25(_VAL_) (REG32(ADR_INFO25)) = (((_VAL_) << 0) | ((REG32(ADR_INFO25)) & 0x00000000)) -+#define SET_INFO26(_VAL_) (REG32(ADR_INFO26)) = (((_VAL_) << 0) | ((REG32(ADR_INFO26)) & 0x00000000)) -+#define SET_INFO27(_VAL_) (REG32(ADR_INFO27)) = (((_VAL_) << 0) | ((REG32(ADR_INFO27)) & 0x00000000)) -+#define SET_INFO28(_VAL_) (REG32(ADR_INFO28)) = (((_VAL_) << 0) | ((REG32(ADR_INFO28)) & 0x00000000)) -+#define SET_INFO29(_VAL_) (REG32(ADR_INFO29)) = (((_VAL_) << 0) | ((REG32(ADR_INFO29)) & 0x00000000)) -+#define SET_INFO30(_VAL_) (REG32(ADR_INFO30)) = (((_VAL_) << 0) | ((REG32(ADR_INFO30)) & 0x00000000)) -+#define SET_INFO31(_VAL_) (REG32(ADR_INFO31)) = (((_VAL_) << 0) | ((REG32(ADR_INFO31)) & 0x00000000)) -+#define SET_INFO32(_VAL_) (REG32(ADR_INFO32)) = (((_VAL_) << 0) | ((REG32(ADR_INFO32)) & 0x00000000)) -+#define SET_INFO33(_VAL_) (REG32(ADR_INFO33)) = (((_VAL_) << 0) | ((REG32(ADR_INFO33)) & 0x00000000)) -+#define SET_INFO34(_VAL_) (REG32(ADR_INFO34)) = (((_VAL_) << 0) | ((REG32(ADR_INFO34)) & 0x00000000)) -+#define SET_INFO35(_VAL_) (REG32(ADR_INFO35)) = (((_VAL_) << 0) | ((REG32(ADR_INFO35)) & 0x00000000)) -+#define SET_INFO36(_VAL_) (REG32(ADR_INFO36)) = (((_VAL_) << 0) | ((REG32(ADR_INFO36)) & 0x00000000)) -+#define SET_INFO37(_VAL_) (REG32(ADR_INFO37)) = (((_VAL_) << 0) | ((REG32(ADR_INFO37)) & 0x00000000)) -+#define SET_INFO38(_VAL_) (REG32(ADR_INFO38)) = (((_VAL_) << 0) | ((REG32(ADR_INFO38)) & 0x00000000)) -+#define SET_INFO_MASK(_VAL_) (REG32(ADR_INFO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_MASK)) & 0x00000000)) -+#define SET_INFO_DEF_RATE(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xffffffc0)) -+#define SET_INFO_MRX_OFFSET(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xfff0ffff)) -+#define SET_BCAST_RATEUNKNOW(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 24) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xc0ffffff)) -+#define SET_INFO_IDX_TBL_ADDR(_VAL_) (REG32(ADR_INFO_IDX_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_IDX_ADDR)) & 0x00000000)) -+#define SET_INFO_LEN_TBL_ADDR(_VAL_) (REG32(ADR_INFO_LEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_LEN_ADDR)) & 0x00000000)) -+#define SET_IC_TAG_31_0(_VAL_) (REG32(ADR_IC_TIME_TAG_0)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_0)) & 0x00000000)) -+#define SET_IC_TAG_63_32(_VAL_) (REG32(ADR_IC_TIME_TAG_1)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_1)) & 0x00000000)) -+#define SET_CH1_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffffc)) -+#define SET_CH2_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 8) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffcff)) -+#define SET_CH3_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 16) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffcffff)) -+#define SET_RG_MAC_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_MODE)) & 0xfffffffe)) -+#define SET_RG_MAC_M2M(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_MODE)) & 0xfffffffd)) -+#define SET_RG_PHY_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_MAC_MODE)) & 0xfffffffb)) -+#define SET_RG_LPBK_RX_EN(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_MODE)) & 0xfffffff7)) -+#define SET_EXT_MAC_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_MODE)) & 0xffffffef)) -+#define SET_EXT_PHY_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_MODE)) & 0xffffffdf)) -+#define SET_ASIC_TAG(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 24) | ((REG32(ADR_MAC_MODE)) & 0x00ffffff)) -+#define SET_HCI_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffe)) -+#define SET_CO_PROC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffd)) -+#define SET_MTX_MISC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffff7)) -+#define SET_MTX_QUE_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffef)) -+#define SET_MTX_CHST_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffdf)) -+#define SET_MTX_BCN_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffbf)) -+#define SET_MRX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffff7f)) -+#define SET_AMPDU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffeff)) -+#define SET_MMU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffdff)) -+#define SET_ID_MNG_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffff7ff)) -+#define SET_MBOX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffefff)) -+#define SET_SCRT_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffdfff)) -+#define SET_MIC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffbfff)) -+#define SET_CO_PROC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffffd)) -+#define SET_MTX_MISC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffff7)) -+#define SET_MTX_QUE_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffef)) -+#define SET_MTX_CHST_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffdf)) -+#define SET_MTX_BCN_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffbf)) -+#define SET_MRX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffff7f)) -+#define SET_AMPDU_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffeff)) -+#define SET_ID_MNG_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffbfff)) -+#define SET_MBOX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffff7fff)) -+#define SET_SCRT_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 16) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffeffff)) -+#define SET_MIC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 17) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffdffff)) -+#define SET_CO_PROC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffffd)) -+#define SET_MTX_MISC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffff7)) -+#define SET_MTX_QUE0_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffef)) -+#define SET_MTX_QUE1_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffdf)) -+#define SET_MTX_QUE2_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffbf)) -+#define SET_MTX_QUE3_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffff7f)) -+#define SET_MTX_QUE4_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffeff)) -+#define SET_MTX_QUE5_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffdff)) -+#define SET_MRX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffbff)) -+#define SET_AMPDU_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffff7ff)) -+#define SET_SCRT_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffdfff)) -+#define SET_ID_MNG_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffbfff)) -+#define SET_MBOX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffff7fff)) -+#define SET_HCI_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffe)) -+#define SET_CO_PROC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffd)) -+#define SET_MTX_MISC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffff7)) -+#define SET_MTX_QUE_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffef)) -+#define SET_MRX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffdf)) -+#define SET_AMPDU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffbf)) -+#define SET_MMU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffff7f)) -+#define SET_ID_MNG_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffdff)) -+#define SET_MBOX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffbff)) -+#define SET_SCRT_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffff7ff)) -+#define SET_MIC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffefff)) -+#define SET_MIB_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffdfff)) -+#define SET_HCI_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffe)) -+#define SET_CO_PROC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffd)) -+#define SET_MTX_MISC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffff7)) -+#define SET_MTX_QUE_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffef)) -+#define SET_MRX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffdf)) -+#define SET_AMPDU_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffbf)) -+#define SET_ID_MNG_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffefff)) -+#define SET_MBOX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffdfff)) -+#define SET_SCRT_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffbfff)) -+#define SET_MIC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffff7fff)) -+#define SET_CO_PROC_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffffd)) -+#define SET_MRX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffbff)) -+#define SET_AMPDU_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffff7ff)) -+#define SET_SCRT_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffdfff)) -+#define SET_ID_MNG_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffbfff)) -+#define SET_MBOX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffff7fff)) -+#define SET_OP_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 0) | ((REG32(ADR_GLBLE_SET)) & 0xfffffffc)) -+#define SET_HT_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 2) | ((REG32(ADR_GLBLE_SET)) & 0xfffffff3)) -+#define SET_QOS_EN(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 4) | ((REG32(ADR_GLBLE_SET)) & 0xffffffef)) -+#define SET_PB_OFFSET(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 8) | ((REG32(ADR_GLBLE_SET)) & 0xffff00ff)) -+#define SET_SNIFFER_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 16) | ((REG32(ADR_GLBLE_SET)) & 0xfffeffff)) -+#define SET_DUP_FLT(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 17) | ((REG32(ADR_GLBLE_SET)) & 0xfffdffff)) -+#define SET_TX_PKT_RSVD(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 18) | ((REG32(ADR_GLBLE_SET)) & 0xffe3ffff)) -+#define SET_AMPDU_SNIFFER(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 21) | ((REG32(ADR_GLBLE_SET)) & 0xffdfffff)) -+#define SET_REASON_TRAP0(_VAL_) (REG32(ADR_REASON_TRAP0)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP0)) & 0x00000000)) -+#define SET_REASON_TRAP1(_VAL_) (REG32(ADR_REASON_TRAP1)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP1)) & 0x00000000)) -+#define SET_BSSID_31_0(_VAL_) (REG32(ADR_BSSID_0)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_0)) & 0x00000000)) -+#define SET_BSSID_47_32(_VAL_) (REG32(ADR_BSSID_1)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_1)) & 0xffff0000)) -+#define SET_SCRT_STATE(_VAL_) (REG32(ADR_SCRT_STATE)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_STATE)) & 0xfffffff0)) -+#define SET_STA_MAC_31_0(_VAL_) (REG32(ADR_STA_MAC_0)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_0)) & 0x00000000)) -+#define SET_STA_MAC_47_32(_VAL_) (REG32(ADR_STA_MAC_1)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_1)) & 0xffff0000)) -+#define SET_PAIR_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_SET)) & 0xfffffff8)) -+#define SET_GRP_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 3) | ((REG32(ADR_SCRT_SET)) & 0xffffffc7)) -+#define SET_SCRT_PKT_ID(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 6) | ((REG32(ADR_SCRT_SET)) & 0xffffe03f)) -+#define SET_SCRT_RPLY_IGNORE(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 16) | ((REG32(ADR_SCRT_SET)) & 0xfffeffff)) -+#define SET_COEXIST_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX0)) & 0xfffffffe)) -+#define SET_WIRE_MODE(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 1) | ((REG32(ADR_BTCX0)) & 0xfffffff1)) -+#define SET_WL_RX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 4) | ((REG32(ADR_BTCX0)) & 0xffffffef)) -+#define SET_WL_TX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 5) | ((REG32(ADR_BTCX0)) & 0xffffffdf)) -+#define SET_GURAN_USE_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX0)) & 0xfffffeff)) -+#define SET_GURAN_USE_CTRL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 9) | ((REG32(ADR_BTCX0)) & 0xfffffdff)) -+#define SET_BEACON_TIMEOUT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 10) | ((REG32(ADR_BTCX0)) & 0xfffffbff)) -+#define SET_WLAN_ACT_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 11) | ((REG32(ADR_BTCX0)) & 0xfffff7ff)) -+#define SET_DUAL_ANT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 12) | ((REG32(ADR_BTCX0)) & 0xffffefff)) -+#define SET_TRSW_PHY_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX0)) & 0xfffeffff)) -+#define SET_WIFI_TX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 17) | ((REG32(ADR_BTCX0)) & 0xfffdffff)) -+#define SET_WIFI_RX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 18) | ((REG32(ADR_BTCX0)) & 0xfffbffff)) -+#define SET_BT_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 19) | ((REG32(ADR_BTCX0)) & 0xfff7ffff)) -+#define SET_BT_PRI_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX1)) & 0xffffff00)) -+#define SET_BT_STA_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX1)) & 0xffff00ff)) -+#define SET_BEACON_TIMEOUT(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX1)) & 0xff00ffff)) -+#define SET_WLAN_REMAIN_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 24) | ((REG32(ADR_BTCX1)) & 0x00ffffff)) -+#define SET_SW_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffe)) -+#define SET_SW_WL_TX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 1) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffd)) -+#define SET_SW_WL_RX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 2) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffb)) -+#define SET_SW_BT_TRX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 3) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffff7)) -+#define SET_BT_TXBAR_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 4) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffef)) -+#define SET_BT_TXBAR_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 5) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffdf)) -+#define SET_BT_BUSY_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffeff)) -+#define SET_BT_BUSY_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 9) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffdff)) -+#define SET_G0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 2) | ((REG32(ADR_MIB_EN)) & 0xfffffffb)) -+#define SET_G0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 3) | ((REG32(ADR_MIB_EN)) & 0xfffffff7)) -+#define SET_G1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 4) | ((REG32(ADR_MIB_EN)) & 0xffffffef)) -+#define SET_G1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MIB_EN)) & 0xffffffdf)) -+#define SET_Q0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MIB_EN)) & 0xffffffbf)) -+#define SET_Q0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MIB_EN)) & 0xffffff7f)) -+#define SET_Q1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MIB_EN)) & 0xfffffeff)) -+#define SET_Q1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 9) | ((REG32(ADR_MIB_EN)) & 0xfffffdff)) -+#define SET_Q2_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MIB_EN)) & 0xfffffbff)) -+#define SET_Q2_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MIB_EN)) & 0xfffff7ff)) -+#define SET_Q3_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MIB_EN)) & 0xffffefff)) -+#define SET_Q3_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MIB_EN)) & 0xffffdfff)) -+#define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MIB_EN)) & 0xffffbfff)) -+#define SET_SCRT_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MIB_EN)) & 0xffff7fff)) -+#define SET_MISC_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MIB_EN)) & 0xfffeffff)) -+#define SET_MISC_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MIB_EN)) & 0xfffdffff)) -+#define SET_MTX_WSID0_SUCC(_VAL_) (REG32(ADR_MTX_WSID0_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_SUCC)) & 0xffff0000)) -+#define SET_MTX_WSID0_FRM(_VAL_) (REG32(ADR_MTX_WSID0_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_FRM)) & 0xffff0000)) -+#define SET_MTX_WSID0_RETRY(_VAL_) (REG32(ADR_MTX_WSID0_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_RETRY)) & 0xffff0000)) -+#define SET_MTX_WSID0_TOTAL(_VAL_) (REG32(ADR_MTX_WSID0_TOTAL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_TOTAL)) & 0xffff0000)) -+#define SET_MTX_GRP(_VAL_) (REG32(ADR_MTX_GROUP)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_GROUP)) & 0xfff00000)) -+#define SET_MTX_FAIL(_VAL_) (REG32(ADR_MTX_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FAIL)) & 0xffff0000)) -+#define SET_MTX_RETRY(_VAL_) (REG32(ADR_MTX_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RETRY)) & 0xfff00000)) -+#define SET_MTX_MULTI_RETRY(_VAL_) (REG32(ADR_MTX_MULTI_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MULTI_RETRY)) & 0xfff00000)) -+#define SET_MTX_RTS_SUCC(_VAL_) (REG32(ADR_MTX_RTS_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_SUCCESS)) & 0xffff0000)) -+#define SET_MTX_RTS_FAIL(_VAL_) (REG32(ADR_MTX_RTS_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_FAIL)) & 0xffff0000)) -+#define SET_MTX_ACK_FAIL(_VAL_) (REG32(ADR_MTX_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_FAIL)) & 0xffff0000)) -+#define SET_MTX_FRM(_VAL_) (REG32(ADR_MTX_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FRM)) & 0xfff00000)) -+#define SET_MTX_ACK_TX(_VAL_) (REG32(ADR_MTX_ACK_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_TX)) & 0xffff0000)) -+#define SET_MTX_CTS_TX(_VAL_) (REG32(ADR_MTX_CTS_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_CTS_TX)) & 0xffff0000)) -+#define SET_MRX_DUP(_VAL_) (REG32(ADR_MRX_DUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DUP_FRM)) & 0xffff0000)) -+#define SET_MRX_FRG(_VAL_) (REG32(ADR_MRX_FRG_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FRG_FRM)) & 0xfff00000)) -+#define SET_MRX_GRP(_VAL_) (REG32(ADR_MRX_GROUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_GROUP_FRM)) & 0xfff00000)) -+#define SET_MRX_FCS_ERR(_VAL_) (REG32(ADR_MRX_FCS_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_ERR)) & 0xffff0000)) -+#define SET_MRX_FCS_SUC(_VAL_) (REG32(ADR_MRX_FCS_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_SUCC)) & 0xffff0000)) -+#define SET_MRX_MISS(_VAL_) (REG32(ADR_MRX_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MISS)) & 0xffff0000)) -+#define SET_MRX_ALC_FAIL(_VAL_) (REG32(ADR_MRX_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ALC_FAIL)) & 0xffff0000)) -+#define SET_MRX_DAT_NTF(_VAL_) (REG32(ADR_MRX_DAT_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_NTF)) & 0xffff0000)) -+#define SET_MRX_RTS_NTF(_VAL_) (REG32(ADR_MRX_RTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_RTS_NTF)) & 0xffff0000)) -+#define SET_MRX_CTS_NTF(_VAL_) (REG32(ADR_MRX_CTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CTS_NTF)) & 0xffff0000)) -+#define SET_MRX_ACK_NTF(_VAL_) (REG32(ADR_MRX_ACK_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ACK_NTF)) & 0xffff0000)) -+#define SET_MRX_BA_NTF(_VAL_) (REG32(ADR_MRX_BA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_NTF)) & 0xffff0000)) -+#define SET_MRX_DATA_NTF(_VAL_) (REG32(ADR_MRX_DATA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DATA_NTF)) & 0xffff0000)) -+#define SET_MRX_MNG_NTF(_VAL_) (REG32(ADR_MRX_MNG_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MNG_NTF)) & 0xffff0000)) -+#define SET_MRX_DAT_CRC_NTF(_VAL_) (REG32(ADR_MRX_DAT_CRC_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_CRC_NTF)) & 0xffff0000)) -+#define SET_MRX_BAR_NTF(_VAL_) (REG32(ADR_MRX_BAR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BAR_NTF)) & 0xffff0000)) -+#define SET_MRX_MB_MISS(_VAL_) (REG32(ADR_MRX_MB_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MB_MISS)) & 0xffff0000)) -+#define SET_MRX_NIDLE_MISS(_VAL_) (REG32(ADR_MRX_NIDLE_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_NIDLE_MISS)) & 0xffff0000)) -+#define SET_MRX_CSR_NTF(_VAL_) (REG32(ADR_MRX_CSR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CSR_NTF)) & 0xffff0000)) -+#define SET_DBG_Q0_SUCC(_VAL_) (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0xffff0000)) -+#define SET_DBG_Q0_FAIL(_VAL_) (REG32(ADR_DBG_Q0_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0xffff0000)) -+#define SET_DBG_Q0_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0xffff0000)) -+#define SET_DBG_Q0_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q0_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0xffff0000)) -+#define SET_DBG_Q1_SUCC(_VAL_) (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0xffff0000)) -+#define SET_DBG_Q1_FAIL(_VAL_) (REG32(ADR_DBG_Q1_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0xffff0000)) -+#define SET_DBG_Q1_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0xffff0000)) -+#define SET_DBG_Q1_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q1_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0xffff0000)) -+#define SET_DBG_Q2_SUCC(_VAL_) (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0xffff0000)) -+#define SET_DBG_Q2_FAIL(_VAL_) (REG32(ADR_DBG_Q2_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0xffff0000)) -+#define SET_DBG_Q2_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0xffff0000)) -+#define SET_DBG_Q2_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q2_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0xffff0000)) -+#define SET_DBG_Q3_SUCC(_VAL_) (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0xffff0000)) -+#define SET_DBG_Q3_FAIL(_VAL_) (REG32(ADR_DBG_Q3_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0xffff0000)) -+#define SET_DBG_Q3_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0xffff0000)) -+#define SET_DBG_Q3_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q3_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0xffff0000)) -+#define SET_SCRT_TKIP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP0)) & 0xfff00000)) -+#define SET_SCRT_TKIP_MIC_ERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP1)) & 0xfff00000)) -+#define SET_SCRT_TKIP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_TKIP2)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP2)) & 0xfff00000)) -+#define SET_SCRT_CCMP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_CCMP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP0)) & 0xfff00000)) -+#define SET_SCRT_CCMP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_CCMP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP1)) & 0xfff00000)) -+#define SET_DBG_LEN_CRC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_CRC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0xffff0000)) -+#define SET_DBG_LEN_ALC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0xffff0000)) -+#define SET_DBG_AMPDU_PASS(_VAL_) (REG32(ADR_DBG_AMPDU_PASS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_PASS)) & 0xffff0000)) -+#define SET_DBG_AMPDU_FAIL(_VAL_) (REG32(ADR_DBG_AMPDU_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_FAIL)) & 0xffff0000)) -+#define SET_RXID_ALC_CNT_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL1)) & 0xffff0000)) -+#define SET_RXID_ALC_LEN_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL2)) & 0xffff0000)) -+#define SET_CBR_RG_EN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe)) -+#define SET_CBR_RG_TX_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd)) -+#define SET_CBR_RG_TX_PA_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb)) -+#define SET_CBR_RG_TX_DAC_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7)) -+#define SET_CBR_RG_RX_AGC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef)) -+#define SET_CBR_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf)) -+#define SET_CBR_RG_RFG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f)) -+#define SET_CBR_RG_PGAG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff)) -+#define SET_CBR_RG_MODE(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff)) -+#define SET_CBR_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff)) -+#define SET_CBR_RG_EN_SX(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff)) -+#define SET_CBR_RG_EN_RX_LNA(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff)) -+#define SET_CBR_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff)) -+#define SET_CBR_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff)) -+#define SET_CBR_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff)) -+#define SET_CBR_RG_EN_RX_TZ(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff)) -+#define SET_CBR_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff)) -+#define SET_CBR_RG_EN_RX_HPF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff)) -+#define SET_CBR_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff)) -+#define SET_CBR_RG_EN_ADC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff)) -+#define SET_CBR_RG_EN_TX_MOD(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff)) -+#define SET_CBR_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff)) -+#define SET_CBR_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff)) -+#define SET_CBR_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff)) -+#define SET_CBR_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff)) -+#define SET_CBR_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff)) -+#define SET_CBR_RG_EN_TX_DPD(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe)) -+#define SET_CBR_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd)) -+#define SET_CBR_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb)) -+#define SET_CBR_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7)) -+#define SET_CBR_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffef)) -+#define SET_CBR_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf)) -+#define SET_CBR_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf)) -+#define SET_CBR_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f)) -+#define SET_CBR_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff)) -+#define SET_CBR_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff)) -+#define SET_CBR_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff)) -+#define SET_CBR_RG_EN_IREF_RX(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff)) -+#define SET_CBR_RG_DCDC_MODE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffefff)) -+#define SET_CBR_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffff8)) -+#define SET_CBR_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffffffc7)) -+#define SET_CBR_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffe3f)) -+#define SET_CBR_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffff1ff)) -+#define SET_CBR_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffff8fff)) -+#define SET_CBR_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffc7fff)) -+#define SET_CBR_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffe3ffff)) -+#define SET_CBR_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xff1fffff)) -+#define SET_CBR_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xf8ffffff)) -+#define SET_CBR_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xc7ffffff)) -+#define SET_CBR_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffe)) -+#define SET_CBR_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffd)) -+#define SET_CBR_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffb)) -+#define SET_CBR_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffe07)) -+#define SET_CBR_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffdff)) -+#define SET_CBR_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffbff)) -+#define SET_CBR_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffff7ff)) -+#define SET_CBR_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffffcfff)) -+#define SET_CBR_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffff3fff)) -+#define SET_CBR_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffcffff)) -+#define SET_CBR_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfff3ffff)) -+#define SET_CBR_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffcfffff)) -+#define SET_CBR_RG_RX_HPF3M(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffbfffff)) -+#define SET_CBR_RG_RX_HPF300K(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xff7fffff)) -+#define SET_CBR_RG_RX_HPFI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfcffffff)) -+#define SET_CBR_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xf3ffffff)) -+#define SET_CBR_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xcfffffff)) -+#define SET_CBR_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffffc)) -+#define SET_CBR_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffff3)) -+#define SET_CBR_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffffcf)) -+#define SET_CBR_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffff3f)) -+#define SET_CBR_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffcff)) -+#define SET_CBR_RG_RX_OUTVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffff3ff)) -+#define SET_CBR_RG_RX_TZI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffcfff)) -+#define SET_CBR_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffbfff)) -+#define SET_CBR_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffe7fff)) -+#define SET_CBR_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfff1ffff)) -+#define SET_CBR_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffefffff)) -+#define SET_CBR_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xff9fffff)) -+#define SET_CBR_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfe7fffff)) -+#define SET_CBR_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfdffffff)) -+#define SET_CBR_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffffffc)) -+#define SET_CBR_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffff03)) -+#define SET_CBR_RG_TXPGA_STEER(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffc0ff)) -+#define SET_CBR_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffff3fff)) -+#define SET_CBR_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffcffff)) -+#define SET_CBR_RG_PACELL_EN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffe3ffff)) -+#define SET_CBR_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfe1fffff)) -+#define SET_CBR_RG_PABIAS_AB(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfdffffff)) -+#define SET_CBR_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xf3ffffff)) -+#define SET_CBR_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xcfffffff)) -+#define SET_CBR_RG_RX_SQDC(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffffff8)) -+#define SET_CBR_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffffe7)) -+#define SET_CBR_RG_RX_LOBUF(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffff9f)) -+#define SET_CBR_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffff87f)) -+#define SET_CBR_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffff87ff)) -+#define SET_CBR_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffc7fff)) -+#define SET_CBR_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffe3ffff)) -+#define SET_CBR_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffdfffff)) -+#define SET_CBR_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xff3fffff)) -+#define SET_CBR_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc)) -+#define SET_CBR_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3)) -+#define SET_CBR_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f)) -+#define SET_CBR_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff)) -+#define SET_CBR_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff)) -+#define SET_CBR_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff)) -+#define SET_CBR_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc)) -+#define SET_CBR_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3)) -+#define SET_CBR_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f)) -+#define SET_CBR_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff)) -+#define SET_CBR_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff)) -+#define SET_CBR_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff)) -+#define SET_CBR_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc)) -+#define SET_CBR_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3)) -+#define SET_CBR_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f)) -+#define SET_CBR_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff)) -+#define SET_CBR_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff)) -+#define SET_CBR_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff)) -+#define SET_CBR_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc)) -+#define SET_CBR_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3)) -+#define SET_CBR_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f)) -+#define SET_CBR_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff)) -+#define SET_CBR_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff)) -+#define SET_CBR_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff)) -+#define SET_CBR_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffe)) -+#define SET_CBR_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffd)) -+#define SET_CBR_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffb)) -+#define SET_CBR_RG_HPF_T1A(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffffe7)) -+#define SET_CBR_RG_HPF_T1B(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffff9f)) -+#define SET_CBR_RG_HPF_T1C(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffe7f)) -+#define SET_CBR_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffff9ff)) -+#define SET_CBR_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffe7ff)) -+#define SET_CBR_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffffe)) -+#define SET_CBR_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff9)) -+#define SET_CBR_RG_ADC_DIVR(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff7)) -+#define SET_CBR_RG_ADC_DVCMI(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffffffcf)) -+#define SET_CBR_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffc3f)) -+#define SET_CBR_RG_ADC_STNBY(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffbff)) -+#define SET_CBR_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffff7ff)) -+#define SET_CBR_RG_ADC_TSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffff0fff)) -+#define SET_CBR_RG_ADC_VRSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffcffff)) -+#define SET_CBR_RG_DICMP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfff3ffff)) -+#define SET_CBR_RG_DIOP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffcfffff)) -+#define SET_CBR_RG_DACI1ST(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffffc)) -+#define SET_CBR_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffff3)) -+#define SET_CBR_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffffcf)) -+#define SET_CBR_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffff3f)) -+#define SET_CBR_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffeff)) -+#define SET_CBR_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffff9ff)) -+#define SET_CBR_RG_TX_DAC_OS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffc7ff)) -+#define SET_CBR_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffff3fff)) -+#define SET_CBR_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfff0ffff)) -+#define SET_CBR_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffefffff)) -+#define SET_CBR_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffdfffff)) -+#define SET_CBR_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffbfffff)) -+#define SET_CBR_RG_EN_SX_R3(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffe)) -+#define SET_CBR_RG_EN_SX_CH(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffd)) -+#define SET_CBR_RG_EN_SX_CHP(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffb)) -+#define SET_CBR_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffff7)) -+#define SET_CBR_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffef)) -+#define SET_CBR_RG_EN_SX_VCO(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffdf)) -+#define SET_CBR_RG_EN_SX_MOD(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffbf)) -+#define SET_CBR_RG_EN_SX_LCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffff7f)) -+#define SET_CBR_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffeff)) -+#define SET_CBR_RG_EN_SX_DELCAL(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffdff)) -+#define SET_CBR_RG_EN_SX_PC_BYPASS(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffbff)) -+#define SET_CBR_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffff7ff)) -+#define SET_CBR_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffefff)) -+#define SET_CBR_RG_EN_SX_DIV(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffdfff)) -+#define SET_CBR_RG_EN_SX_LPF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffbfff)) -+#define SET_CBR_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xff000000)) -+#define SET_CBR_RG_SX_SEL_CP(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0ffffff)) -+#define SET_CBR_RG_SX_SEL_CS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0fffffff)) -+#define SET_CBR_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfffff800)) -+#define SET_CBR_RG_SX_SEL_C3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xffff87ff)) -+#define SET_CBR_RG_SX_SEL_RS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfff07fff)) -+#define SET_CBR_RG_SX_SEL_R3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfe0fffff)) -+#define SET_CBR_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffffe0)) -+#define SET_CBR_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffffc1f)) -+#define SET_CBR_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffc3ff)) -+#define SET_CBR_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffc3fff)) -+#define SET_CBR_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffbffff)) -+#define SET_CBR_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffc7ffff)) -+#define SET_CBR_RG_SX_PFDSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffbfffff)) -+#define SET_CBR_RG_SX_PFD_SET(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xff7fffff)) -+#define SET_CBR_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfeffffff)) -+#define SET_CBR_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfdffffff)) -+#define SET_CBR_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfbffffff)) -+#define SET_CBR_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xf7ffffff)) -+#define SET_CBR_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xefffffff)) -+#define SET_CBR_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xdfffffff)) -+#define SET_CBR_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xbfffffff)) -+#define SET_CBR_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffffff8)) -+#define SET_CBR_RG_SX_VCORSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffffff07)) -+#define SET_CBR_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffff0ff)) -+#define SET_CBR_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffff0fff)) -+#define SET_CBR_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfff0ffff)) -+#define SET_CBR_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xff0fffff)) -+#define SET_CBR_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0ffffff)) -+#define SET_CBR_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0fffffff)) -+#define SET_CBR_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffffc)) -+#define SET_CBR_RG_SX_MOD_ERRCMP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffff3)) -+#define SET_CBR_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffcf)) -+#define SET_CBR_RG_SX_SDM_D1(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffbf)) -+#define SET_CBR_RG_SX_SDM_D2(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffff7f)) -+#define SET_CBR_RG_SDM_PASS(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffeff)) -+#define SET_CBR_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffdff)) -+#define SET_CBR_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffbff)) -+#define SET_CBR_RG_SX_XO_GM(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff)) -+#define SET_CBR_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffdfff)) -+#define SET_CBR_RG_SX_XO_SWCAP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffc3fff)) -+#define SET_CBR_RG_SX_SDMLUT_INV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffbffff)) -+#define SET_CBR_RG_SX_LCKEN(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff)) -+#define SET_CBR_RG_SX_PREVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xff0fffff)) -+#define SET_CBR_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff)) -+#define SET_CBR_RG_SX_MOD_ERR_DELAY(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xcfffffff)) -+#define SET_CBR_RG_SX_MODDB(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xbfffffff)) -+#define SET_CBR_RG_SX_CV_CURVE_SEL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffffffc)) -+#define SET_CBR_RG_SX_SEL_DELAY(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffff83)) -+#define SET_CBR_RG_SX_REF_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff87f)) -+#define SET_CBR_RG_SX_VCOBY16(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff7ff)) -+#define SET_CBR_RG_SX_VCOBY32(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffefff)) -+#define SET_CBR_RG_SX_PH(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffdfff)) -+#define SET_CBR_RG_SX_PL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffbfff)) -+#define SET_CBR_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffffe)) -+#define SET_CBR_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffff9)) -+#define SET_CBR_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffe7)) -+#define SET_CBR_RG_SX_VT_SET(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffdf)) -+#define SET_CBR_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffff803f)) -+#define SET_CBR_RG_IDEAL_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xf0007fff)) -+#define SET_CBR_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffffe)) -+#define SET_CBR_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffff9)) -+#define SET_CBR_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffffe7)) -+#define SET_CBR_RG_DP_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffc01f)) -+#define SET_CBR_RG_DP_CK320BY2(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffbfff)) -+#define SET_CBR_RG_SX_DELCTRL(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffe07fff)) -+#define SET_CBR_RG_DP_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffdfffff)) -+#define SET_CBR_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe)) -+#define SET_CBR_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9)) -+#define SET_CBR_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7)) -+#define SET_CBR_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f)) -+#define SET_CBR_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff)) -+#define SET_CBR_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff)) -+#define SET_CBR_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff)) -+#define SET_CBR_RG_DP_RP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff)) -+#define SET_CBR_RG_DP_RHP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff)) -+#define SET_CBR_RG_DP_DR3(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xff8fffff)) -+#define SET_CBR_RG_DP_DCP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xf87fffff)) -+#define SET_CBR_RG_DP_DCS(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x87ffffff)) -+#define SET_CBR_RG_DP_FBDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xfffff000)) -+#define SET_CBR_RG_DP_FODIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00fff)) -+#define SET_CBR_RG_DP_REFDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003fffff)) -+#define SET_CBR_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xffffffc0)) -+#define SET_CBR_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffff03f)) -+#define SET_CBR_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff)) -+#define SET_CBR_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xff03ffff)) -+#define SET_CBR_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xffffffc0)) -+#define SET_CBR_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffff03f)) -+#define SET_CBR_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff)) -+#define SET_CBR_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xff03ffff)) -+#define SET_CBR_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xffffffc0)) -+#define SET_CBR_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffff03f)) -+#define SET_CBR_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff)) -+#define SET_CBR_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xff03ffff)) -+#define SET_CBR_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xffffffc0)) -+#define SET_CBR_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffff03f)) -+#define SET_CBR_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff)) -+#define SET_CBR_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xff03ffff)) -+#define SET_CBR_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xffffffc0)) -+#define SET_CBR_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffff03f)) -+#define SET_CBR_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff)) -+#define SET_CBR_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xff03ffff)) -+#define SET_CBR_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xffffffc0)) -+#define SET_CBR_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffff03f)) -+#define SET_CBR_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff)) -+#define SET_CBR_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xff03ffff)) -+#define SET_CBR_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xffffffc0)) -+#define SET_CBR_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffff03f)) -+#define SET_CBR_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff)) -+#define SET_CBR_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xff03ffff)) -+#define SET_CBR_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xffffffc0)) -+#define SET_CBR_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffff03f)) -+#define SET_CBR_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff)) -+#define SET_CBR_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xff03ffff)) -+#define SET_CBR_RG_EN_RCAL(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffe)) -+#define SET_CBR_RG_RCAL_SPD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffd)) -+#define SET_CBR_RG_RCAL_TMR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffe03)) -+#define SET_CBR_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffdff)) -+#define SET_CBR_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xffff83ff)) -+#define SET_CBR_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffffe)) -+#define SET_CBR_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffffff01)) -+#define SET_CBR_RG_DP_BBPLL_BS_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffeff)) -+#define SET_CBR_RG_DP_BBPLL_BS_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffff81ff)) -+#define SET_CBR_RCAL_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffe)) -+#define SET_CBR_DA_LCK_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffd)) -+#define SET_CBR_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffb)) -+#define SET_CBR_DP_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffff7)) -+#define SET_CBR_CH_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffffef)) -+#define SET_CBR_DA_R_CODE_LUT(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffff83f)) -+#define SET_CBR_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffe7ff)) -+#define SET_CBR_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffff9fff)) -+#define SET_CBR_DA_R_CAL_CODE(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xffffffe0)) -+#define SET_CBR_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffff01f)) -+#define SET_CBR_DA_DP_BBPLL_BS(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffc0fff)) -+#define SET_CBR_TX_EN(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffe)) -+#define SET_CBR_TX_CNT_RST(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffd)) -+#define SET_CBR_IFS_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xffffff03)) -+#define SET_CBR_LENGTH_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfff000ff)) -+#define SET_CBR_TX_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00ffffff)) -+#define SET_CBR_TC_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0xff000000)) -+#define SET_CBR_PLCP_PSDU_DATA_MEM(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffffff00)) -+#define SET_CBR_PLCP_PSDU_PREAMBLE_SHORT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xfffffeff)) -+#define SET_CBR_PLCP_BYTE_LENGTH(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffe001ff)) -+#define SET_CBR_PLCP_PSDU_RATE(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xff9fffff)) -+#define SET_CBR_TAIL_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xe07fffff)) -+#define SET_CBR_RG_O_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffe)) -+#define SET_CBR_RG_I_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffd)) -+#define SET_CBR_SEL_ADCKP_INV(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffb)) -+#define SET_CBR_RG_PAD_DS(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffff7)) -+#define SET_CBR_SEL_ADCKP_MUX(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffef)) -+#define SET_CBR_RG_PAD_DS_CLK(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffdf)) -+#define SET_CBR_INTP_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffdff)) -+#define SET_CBR_IQ_SWP(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffbff)) -+#define SET_CBR_RG_EN_EXT_DA(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffff7ff)) -+#define SET_CBR_RG_DIS_DA_OFFSET(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffefff)) -+#define SET_CBR_DBG_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfff0ffff)) -+#define SET_CBR_DBG_EN(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffefffff)) -+#define SET_CBR_RG_PKT_GEN_TX_CNT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0x00000000)) -+#define SET_CBR_TP_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffe0)) -+#define SET_CBR_IDEAL_IQ_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffdf)) -+#define SET_CBR_DATA_OUT_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffe3f)) -+#define SET_CBR_TWO_TONE_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffdff)) -+#define SET_CBR_FREQ_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xff00ffff)) -+#define SET_CBR_IQ_SCALE(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ffffff)) -+#define SET_CPU_QUE_POP(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 0) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffe)) -+#define SET_CPU_INT(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 2) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffb)) -+#define SET_CPU_ID_TB0(_VAL_) (REG32(ADR_CPU_ID_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB0)) & 0x00000000)) -+#define SET_CPU_ID_TB1(_VAL_) (REG32(ADR_CPU_ID_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB1)) & 0x00000000)) -+#define SET_HW_PKTID(_VAL_) (REG32(ADR_CH0_TRIG_1)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_1)) & 0xfffff800)) -+#define SET_CH0_INT_ADDR(_VAL_) (REG32(ADR_CH0_TRIG_0)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_0)) & 0x00000000)) -+#define SET_PRI_HW_PKTID(_VAL_) (REG32(ADR_CH0_PRI_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_PRI_TRIG)) & 0xfffff800)) -+#define SET_CH0_FULL(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffe)) -+#define SET_FF0_EMPTY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffd)) -+#define SET_RLS_BUSY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_STATUS)) & 0xfffffdff)) -+#define SET_RLS_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MCU_STATUS)) & 0xfffffbff)) -+#define SET_RTN_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MCU_STATUS)) & 0xfffff7ff)) -+#define SET_RLS_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MCU_STATUS)) & 0xff00ffff)) -+#define SET_RTN_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MCU_STATUS)) & 0x00ffffff)) -+#define SET_FF0_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffffe0)) -+#define SET_FF1_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfffffe1f)) -+#define SET_FF3_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffc7ff)) -+#define SET_FF5_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 17) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfff1ffff)) -+#define SET_FF6_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xff8fffff)) -+#define SET_FF7_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 23) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfc7fffff)) -+#define SET_FF8_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 26) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xe3ffffff)) -+#define SET_FF9_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 29) | ((REG32(ADR_RD_IN_FFCNT1)) & 0x1fffffff)) -+#define SET_FF10_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffff8)) -+#define SET_FF11_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 3) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffffc7)) -+#define SET_FF12_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 6) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffe3f)) -+#define SET_FF13_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 9) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffff9ff)) -+#define SET_FF14_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffe7ff)) -+#define SET_FF15_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 13) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffff9fff)) -+#define SET_FF4_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfff07fff)) -+#define SET_FF2_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xff8fffff)) -+#define SET_CH1_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffd)) -+#define SET_CH2_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffb)) -+#define SET_CH3_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffff7)) -+#define SET_CH4_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffef)) -+#define SET_CH5_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffdf)) -+#define SET_CH6_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffbf)) -+#define SET_CH7_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffff7f)) -+#define SET_CH8_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffeff)) -+#define SET_CH9_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffdff)) -+#define SET_CH10_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffbff)) -+#define SET_CH11_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffff7ff)) -+#define SET_CH12_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffefff)) -+#define SET_CH13_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffdfff)) -+#define SET_CH14_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffbfff)) -+#define SET_CH15_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffff7fff)) -+#define SET_HALT_CH0(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffe)) -+#define SET_HALT_CH1(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffd)) -+#define SET_HALT_CH2(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffb)) -+#define SET_HALT_CH3(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 3) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffff7)) -+#define SET_HALT_CH4(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffef)) -+#define SET_HALT_CH5(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffdf)) -+#define SET_HALT_CH6(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffbf)) -+#define SET_HALT_CH7(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffff7f)) -+#define SET_HALT_CH8(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffeff)) -+#define SET_HALT_CH9(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 9) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffdff)) -+#define SET_HALT_CH10(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 10) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffbff)) -+#define SET_HALT_CH11(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 11) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffff7ff)) -+#define SET_HALT_CH12(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 12) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffefff)) -+#define SET_HALT_CH13(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 13) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffdfff)) -+#define SET_HALT_CH14(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 14) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffbfff)) -+#define SET_HALT_CH15(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 15) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffff7fff)) -+#define SET_STOP_MBOX(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffeffff)) -+#define SET_MB_ERR_AUTO_HALT_EN(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 20) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffefffff)) -+#define SET_MB_EXCEPT_CLR(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 21) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffdfffff)) -+#define SET_MB_EXCEPT_CASE(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 24) | ((REG32(ADR_MBOX_HALT_CFG)) & 0x00ffffff)) -+#define SET_MB_DBG_TIME_STEP(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG1)) & 0xffff0000)) -+#define SET_DBG_TYPE(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffcffff)) -+#define SET_MB_DBG_CLR(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffbffff)) -+#define SET_DBG_ALC_LOG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfff7ffff)) -+#define SET_MB_DBG_COUNTER_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfeffffff)) -+#define SET_MB_DBG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG1)) & 0x7fffffff)) -+#define SET_MB_DBG_RECORD_CNT(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000)) -+#define SET_MB_DBG_LENGTH(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff)) -+#define SET_MB_DBG_CFG_ADDR(_VAL_) (REG32(ADR_MB_DBG_CFG3)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG3)) & 0x00000000)) -+#define SET_DBG_HWID0_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffe)) -+#define SET_DBG_HWID1_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 1) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffd)) -+#define SET_DBG_HWID2_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 2) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffb)) -+#define SET_DBG_HWID3_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 3) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffff7)) -+#define SET_DBG_HWID4_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 4) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffef)) -+#define SET_DBG_HWID5_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 5) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffdf)) -+#define SET_DBG_HWID6_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 6) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffbf)) -+#define SET_DBG_HWID7_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 7) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffff7f)) -+#define SET_DBG_HWID8_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 8) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffeff)) -+#define SET_DBG_HWID9_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 9) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffdff)) -+#define SET_DBG_HWID10_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 10) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffbff)) -+#define SET_DBG_HWID11_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 11) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffff7ff)) -+#define SET_DBG_HWID12_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 12) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffefff)) -+#define SET_DBG_HWID13_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 13) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffdfff)) -+#define SET_DBG_HWID14_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 14) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffbfff)) -+#define SET_DBG_HWID15_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 15) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffff7fff)) -+#define SET_DBG_HWID0_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffeffff)) -+#define SET_DBG_HWID1_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 17) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffdffff)) -+#define SET_DBG_HWID2_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffbffff)) -+#define SET_DBG_HWID3_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfff7ffff)) -+#define SET_DBG_HWID4_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 20) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffefffff)) -+#define SET_DBG_HWID5_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 21) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffdfffff)) -+#define SET_DBG_HWID6_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 22) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffbfffff)) -+#define SET_DBG_HWID7_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 23) | ((REG32(ADR_MB_DBG_CFG4)) & 0xff7fffff)) -+#define SET_DBG_HWID8_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfeffffff)) -+#define SET_DBG_HWID9_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 25) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfdffffff)) -+#define SET_DBG_HWID10_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 26) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfbffffff)) -+#define SET_DBG_HWID11_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 27) | ((REG32(ADR_MB_DBG_CFG4)) & 0xf7ffffff)) -+#define SET_DBG_HWID12_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 28) | ((REG32(ADR_MB_DBG_CFG4)) & 0xefffffff)) -+#define SET_DBG_HWID13_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 29) | ((REG32(ADR_MB_DBG_CFG4)) & 0xdfffffff)) -+#define SET_DBG_HWID14_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 30) | ((REG32(ADR_MB_DBG_CFG4)) & 0xbfffffff)) -+#define SET_DBG_HWID15_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG4)) & 0x7fffffff)) -+#define SET_MB_OUT_QUEUE_EN(_VAL_) (REG32(ADR_MB_OUT_QUEUE_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0xfffffffd)) -+#define SET_CH0_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffe)) -+#define SET_CH1_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffd)) -+#define SET_CH2_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffb)) -+#define SET_CH3_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffff7)) -+#define SET_CH4_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffef)) -+#define SET_CH5_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffdf)) -+#define SET_CH6_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffbf)) -+#define SET_CH7_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffff7f)) -+#define SET_CH8_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffeff)) -+#define SET_CH9_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffdff)) -+#define SET_CH10_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffbff)) -+#define SET_CH11_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffff7ff)) -+#define SET_CH12_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffefff)) -+#define SET_CH13_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffdfff)) -+#define SET_CH14_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffbfff)) -+#define SET_CH15_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 15) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffff7fff)) -+#define SET_FFO0_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffffffe0)) -+#define SET_FFO1_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffffc1f)) -+#define SET_FFO2_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffff3ff)) -+#define SET_FFO3_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfff07fff)) -+#define SET_FFO4_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffcfffff)) -+#define SET_FFO5_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xf1ffffff)) -+#define SET_FFO6_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffff0)) -+#define SET_FFO7_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffc1f)) -+#define SET_FFO8_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xffff83ff)) -+#define SET_FFO9_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfff07fff)) -+#define SET_FFO10_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xff0fffff)) -+#define SET_FFO11_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xc1ffffff)) -+#define SET_FFO12_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffffff8)) -+#define SET_FFO13_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffffff9f)) -+#define SET_FFO14_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffff3ff)) -+#define SET_FFO15_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffe07fff)) -+#define SET_CH0_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffe)) -+#define SET_CH1_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffd)) -+#define SET_CH2_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffb)) -+#define SET_CH3_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffff7)) -+#define SET_CH4_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffef)) -+#define SET_CH5_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffdf)) -+#define SET_CH6_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffbf)) -+#define SET_CH7_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffff7f)) -+#define SET_CH8_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffeff)) -+#define SET_CH9_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffdff)) -+#define SET_CH10_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffbff)) -+#define SET_CH11_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffff7ff)) -+#define SET_CH12_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffefff)) -+#define SET_CH13_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffdfff)) -+#define SET_CH14_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffbfff)) -+#define SET_CH15_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffff7fff)) -+#define SET_CH0_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffe)) -+#define SET_CH1_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 1) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffd)) -+#define SET_CH2_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 2) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffb)) -+#define SET_CH3_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 3) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffff7)) -+#define SET_CH4_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 4) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffef)) -+#define SET_CH5_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 5) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffdf)) -+#define SET_CH6_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 6) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffbf)) -+#define SET_CH7_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 7) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffff7f)) -+#define SET_CH8_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffeff)) -+#define SET_CH9_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 9) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffdff)) -+#define SET_CH10_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 10) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffbff)) -+#define SET_CH11_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 11) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffff7ff)) -+#define SET_CH12_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 12) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffefff)) -+#define SET_CH13_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 13) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffdfff)) -+#define SET_CH14_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 14) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffbfff)) -+#define SET_CH15_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 15) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffff7fff)) -+#define SET_MB_LOW_THOLD_EN(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 31) | ((REG32(ADR_MB_THRESHOLD6)) & 0x7fffffff)) -+#define SET_CH0_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffffe0)) -+#define SET_CH1_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffe0ff)) -+#define SET_CH2_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffe0ffff)) -+#define SET_CH3_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD7)) & 0xe0ffffff)) -+#define SET_CH4_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffffe0)) -+#define SET_CH5_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffe0ff)) -+#define SET_CH6_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffe0ffff)) -+#define SET_CH7_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD8)) & 0xe0ffffff)) -+#define SET_CH8_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffffe0)) -+#define SET_CH9_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffe0ff)) -+#define SET_CH10_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffe0ffff)) -+#define SET_CH11_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD9)) & 0xe0ffffff)) -+#define SET_CH12_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffffe0)) -+#define SET_CH13_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffe0ff)) -+#define SET_CH14_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffe0ffff)) -+#define SET_CH15_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD10)) & 0xe0ffffff)) -+#define SET_TRASH_TIMEOUT_EN(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffe)) -+#define SET_TRASH_CAN_INT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffd)) -+#define SET_TRASH_INT_ID(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffff80f)) -+#define SET_TRASH_TIMEOUT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfc00ffff)) -+#define SET_CH0_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffe)) -+#define SET_CH1_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffd)) -+#define SET_CH2_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffb)) -+#define SET_CH3_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffff7)) -+#define SET_CH4_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffef)) -+#define SET_CH5_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffdf)) -+#define SET_CH6_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffbf)) -+#define SET_CH7_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffff7f)) -+#define SET_CH8_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffeff)) -+#define SET_CH9_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffdff)) -+#define SET_CH10_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffbff)) -+#define SET_CH11_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffff7ff)) -+#define SET_CH12_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffefff)) -+#define SET_CH13_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffdfff)) -+#define SET_CH14_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffbfff)) -+#define SET_CPU_ID_TB2(_VAL_) (REG32(ADR_CPU_ID_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB2)) & 0x00000000)) -+#define SET_CPU_ID_TB3(_VAL_) (REG32(ADR_CPU_ID_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB3)) & 0x00000000)) -+#define SET_IQ_LOG_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0xfffffffe)) -+#define SET_IQ_LOG_STOP_MODE(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xfffffffe)) -+#define SET_GPIO_STOP_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffef)) -+#define SET_GPIO_STOP_POL(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffdf)) -+#define SET_IQ_LOG_TIMER(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x0000ffff)) -+#define SET_IQ_LOG_LEN(_VAL_) (REG32(ADR_PHY_IQ_LOG_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000)) -+#define SET_IQ_LOG_TAIL_ADR(_VAL_) (REG32(ADR_PHY_IQ_LOG_PTR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_PTR)) & 0xffff0000)) -+#define SET_ALC_LENG(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 0) | ((REG32(ADR_WR_ALC)) & 0xfffc0000)) -+#define SET_CH0_DYN_PRI(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 20) | ((REG32(ADR_WR_ALC)) & 0xffcfffff)) -+#define SET_MCU_PKTID(_VAL_) (REG32(ADR_GETID)) = (((_VAL_) << 0) | ((REG32(ADR_GETID)) & 0x00000000)) -+#define SET_CH0_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffffc)) -+#define SET_CH1_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_STA_PRI)) & 0xffffffcf)) -+#define SET_CH2_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffcff)) -+#define SET_CH3_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_STA_PRI)) & 0xffffcfff)) -+#define SET_ID_TB0(_VAL_) (REG32(ADR_RD_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID0)) & 0x00000000)) -+#define SET_ID_TB1(_VAL_) (REG32(ADR_RD_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID1)) & 0x00000000)) -+#define SET_ID_MNG_HALT(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_CFG)) & 0xffffffef)) -+#define SET_ID_MNG_ERR_HALT_EN(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_CFG)) & 0xffffffdf)) -+#define SET_ID_EXCEPT_FLG_CLR(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_CFG)) & 0xffffffbf)) -+#define SET_ID_EXCEPT_FLG(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_CFG)) & 0xffffff7f)) -+#define SET_ID_FULL(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 0) | ((REG32(ADR_IMD_STA)) & 0xfffffffe)) -+#define SET_ID_MNG_BUSY(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 1) | ((REG32(ADR_IMD_STA)) & 0xfffffffd)) -+#define SET_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 2) | ((REG32(ADR_IMD_STA)) & 0xfffffffb)) -+#define SET_CH0_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_STA)) & 0xffffffef)) -+#define SET_CH1_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_STA)) & 0xffffffdf)) -+#define SET_CH2_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_STA)) & 0xffffffbf)) -+#define SET_CH3_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_STA)) & 0xffffff7f)) -+#define SET_REQ_LOCK_INT_EN(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 8) | ((REG32(ADR_IMD_STA)) & 0xfffffeff)) -+#define SET_REQ_LOCK_INT(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 9) | ((REG32(ADR_IMD_STA)) & 0xfffffdff)) -+#define SET_MCU_ALC_READY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_STA)) & 0xfffffffe)) -+#define SET_ALC_FAIL(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 1) | ((REG32(ADR_ALC_STA)) & 0xfffffffd)) -+#define SET_ALC_BUSY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 2) | ((REG32(ADR_ALC_STA)) & 0xfffffffb)) -+#define SET_CH0_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 4) | ((REG32(ADR_ALC_STA)) & 0xffffffef)) -+#define SET_CH1_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 5) | ((REG32(ADR_ALC_STA)) & 0xffffffdf)) -+#define SET_CH2_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 6) | ((REG32(ADR_ALC_STA)) & 0xffffffbf)) -+#define SET_CH3_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 7) | ((REG32(ADR_ALC_STA)) & 0xffffff7f)) -+#define SET_ALC_INT_ID(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_STA)) & 0xffff80ff)) -+#define SET_ALC_TIMEOUT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_STA)) & 0xfc00ffff)) -+#define SET_ALC_TIMEOUT_INT_EN(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 30) | ((REG32(ADR_ALC_STA)) & 0xbfffffff)) -+#define SET_ALC_TIMEOUT_INT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_STA)) & 0x7fffffff)) -+#define SET_TX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffffff00)) -+#define SET_RX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffff00ff)) -+#define SET_TX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffffff00)) -+#define SET_RX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffff00ff)) -+#define SET_ID_THOLD_RX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfffeffff)) -+#define SET_RX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 17) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfff1ffff)) -+#define SET_ID_THOLD_TX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 20) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffefffff)) -+#define SET_TX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 21) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xff1fffff)) -+#define SET_ID_THOLD_INT_EN(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfeffffff)) -+#define SET_TX_ID_TB0(_VAL_) (REG32(ADR_TX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID0)) & 0x00000000)) -+#define SET_TX_ID_TB1(_VAL_) (REG32(ADR_TX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID1)) & 0x00000000)) -+#define SET_RX_ID_TB0(_VAL_) (REG32(ADR_RX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID0)) & 0x00000000)) -+#define SET_RX_ID_TB1(_VAL_) (REG32(ADR_RX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID1)) & 0x00000000)) -+#define SET_DOUBLE_RLS_INT_EN(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 0) | ((REG32(ADR_RTN_STA)) & 0xfffffffe)) -+#define SET_ID_DOUBLE_RLS_INT(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 1) | ((REG32(ADR_RTN_STA)) & 0xfffffffd)) -+#define SET_DOUBLE_RLS_ID(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 8) | ((REG32(ADR_RTN_STA)) & 0xffff80ff)) -+#define SET_ID_LEN_THOLD_INT_EN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffe)) -+#define SET_ALL_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 1) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffd)) -+#define SET_TX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 2) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffb)) -+#define SET_RX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 3) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffff7)) -+#define SET_ID_TX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 4) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffffe00f)) -+#define SET_ID_RX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 13) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffc01fff)) -+#define SET_ID_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 22) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x803fffff)) -+#define SET_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffffe00)) -+#define SET_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 9) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffc01ff)) -+#define SET_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 18) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xf803ffff)) -+#define SET_CH_ARB_EN(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffffe)) -+#define SET_CH_PRI1(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffffcf)) -+#define SET_CH_PRI2(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffcff)) -+#define SET_CH_PRI3(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffcfff)) -+#define SET_CH_PRI4(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 16) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffcffff)) -+#define SET_TX_ID_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xffffff80)) -+#define SET_TX_PAGE_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xfffe00ff)) -+#define SET_ID_PAGE_MAX_SIZE(_VAL_) (REG32(ADR_ID_INFO_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ID_INFO_STA)) & 0xfffffe00)) -+#define SET_TX_PAGE_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xfffffe00)) -+#define SET_TX_COUNT_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xff00ffff)) -+#define SET_TX_LIMIT_INT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 30) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xbfffffff)) -+#define SET_TX_LIMIT_INT_EN(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 31) | ((REG32(ADR_TX_LIMIT_INTR)) & 0x7fffffff)) -+#define SET_TX_PAGE_USE_7_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffff00)) -+#define SET_TX_ID_USE_5_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffc0ff)) -+#define SET_EDCA0_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 14) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xfffc3fff)) -+#define SET_EDCA1_FFO_CNT_3_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 18) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffc3ffff)) -+#define SET_EDCA2_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xf83fffff)) -+#define SET_EDCA3_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 27) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0x07ffffff)) -+#define SET_ID_TB2(_VAL_) (REG32(ADR_RD_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID2)) & 0x00000000)) -+#define SET_ID_TB3(_VAL_) (REG32(ADR_RD_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID3)) & 0x00000000)) -+#define SET_TX_ID_TB2(_VAL_) (REG32(ADR_TX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID2)) & 0x00000000)) -+#define SET_TX_ID_TB3(_VAL_) (REG32(ADR_TX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID3)) & 0x00000000)) -+#define SET_RX_ID_TB2(_VAL_) (REG32(ADR_RX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID2)) & 0x00000000)) -+#define SET_RX_ID_TB3(_VAL_) (REG32(ADR_RX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID3)) & 0x00000000)) -+#define SET_TX_PAGE_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffffe00)) -+#define SET_TX_ID_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffe01ff)) -+#define SET_EDCA4_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xffe1ffff)) -+#define SET_TX_PAGE_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffffe00)) -+#define SET_TX_ID_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffe01ff)) -+#define SET_EDCA1_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 21) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfc1fffff)) -+#define SET_EDCA4_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 26) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xc3ffffff)) -+#define SET_TX_PAGE_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffffe00)) -+#define SET_TX_ID_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffe01ff)) -+#define SET_EDCA2_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xffc1ffff)) -+#define SET_EDCA3_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xf83fffff)) -+#define SET_TX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfffffe00)) -+#define SET_RX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfe00ffff)) -+#define SET_MAX_ALL_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INFO)) & 0xffffff00)) -+#define SET_MAX_TX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_ID_INFO)) & 0xffff00ff)) -+#define SET_MAX_RX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_ID_INFO)) & 0xff00ffff)) -+#define SET_MAX_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffffe00)) -+#define SET_MAX_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 9) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffc01ff)) -+#define SET_MAX_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 18) | ((REG32(ADR_ALC_ID_INF1)) & 0xf803ffff)) -+#define SET_RG_PMDLBK(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_0)) & 0xfffffffe)) -+#define SET_RG_RDYACK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff9)) -+#define SET_RG_ADEDGE_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff7)) -+#define SET_RG_SIGN_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_0)) & 0xffffffef)) -+#define SET_RG_IQ_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_0)) & 0xffffffdf)) -+#define SET_RG_Q_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_0)) & 0xffffffbf)) -+#define SET_RG_I_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_EN_0)) & 0xffffff7f)) -+#define SET_RG_BYPASS_ACI(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_0)) & 0xfffffeff)) -+#define SET_RG_LBK_ANA_PATH(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_EN_0)) & 0xfffffdff)) -+#define SET_RG_SPECTRUM_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_EN_0)) & 0xfffff3ff)) -+#define SET_RG_SPECTRUM_BW(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_0)) & 0xffffcfff)) -+#define SET_RG_SPECTRUM_FREQ_MANUAL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_0)) & 0xffffbfff)) -+#define SET_RG_SPECTRUM_EN(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_0)) & 0xffff7fff)) -+#define SET_RG_TXPWRLVL_SET(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_0)) & 0xff00ffff)) -+#define SET_RG_TXPWRLVL_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_EN_0)) & 0xfeffffff)) -+#define SET_RG_RF_BB_CLK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_EN_0)) & 0x7fffffff)) -+#define SET_RG_PHY_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffe)) -+#define SET_RG_PHYRX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffd)) -+#define SET_RG_PHYTX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffb)) -+#define SET_RG_PHY11GN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_1)) & 0xfffffff7)) -+#define SET_RG_PHY11B_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_1)) & 0xffffffef)) -+#define SET_RG_PHYRXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_1)) & 0xffffffdf)) -+#define SET_RG_PHYTXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_1)) & 0xffffffbf)) -+#define SET_RG_PHY11BGN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_1)) & 0xfffffeff)) -+#define SET_RG_FORCE_11GN_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_1)) & 0xffffefff)) -+#define SET_RG_FORCE_11B_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 13) | ((REG32(ADR_PHY_EN_1)) & 0xffffdfff)) -+#define SET_RG_FFT_MEM_CLK_EN_RX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_1)) & 0xffffbfff)) -+#define SET_RG_FFT_MEM_CLK_EN_TX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_1)) & 0xffff7fff)) -+#define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_1)) & 0xfff0ffff)) -+#define SET_RG_SPECTRUM_FREQ(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_EN_1)) & 0xc00fffff)) -+#define SET_SVN_VERSION(_VAL_) (REG32(ADR_SVN_VERSION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SVN_VERSION_REG)) & 0x00000000)) -+#define SET_RG_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffff0000)) -+#define SET_RG_PKT_MODE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xfff8ffff)) -+#define SET_RG_CH_BW(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 19) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffc7ffff)) -+#define SET_RG_PRM(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 22) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffbfffff)) -+#define SET_RG_SHORTGI(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xff7fffff)) -+#define SET_RG_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0x80ffffff)) -+#define SET_RG_L_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xfffff000)) -+#define SET_RG_L_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff8fff)) -+#define SET_RG_SERVICE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0x0000ffff)) -+#define SET_RG_SMOOTHING(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffe)) -+#define SET_RG_NO_SOUND(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffd)) -+#define SET_RG_AGGREGATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffb)) -+#define SET_RG_STBC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffe7)) -+#define SET_RG_FEC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffdf)) -+#define SET_RG_N_ESS(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffff3f)) -+#define SET_RG_TXPWRLVL(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffff00ff)) -+#define SET_RG_TX_START(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffffe)) -+#define SET_RG_IFS_TIME(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xffffff03)) -+#define SET_RG_CONTINUOUS_DATA(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffeff)) -+#define SET_RG_DATA_SEL(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffff9ff)) -+#define SET_RG_TX_D(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xff00ffff)) -+#define SET_RG_TX_CNT_TARGET(_VAL_) (REG32(ADR_PHY_PKT_GEN_4)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_4)) & 0x00000000)) -+#define SET_RG_FFT_IFFT_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_REG_00)) & 0xffffff3f)) -+#define SET_RG_DAC_DBG_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_00)) & 0xfffffeff)) -+#define SET_RG_DAC_SGN_SWAP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_REG_00)) & 0xfffffdff)) -+#define SET_RG_TXD_SEL(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_REG_00)) & 0xfffff3ff)) -+#define SET_RG_UP8X(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_00)) & 0xff00ffff)) -+#define SET_RG_IQ_DC_BYP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_00)) & 0xfeffffff)) -+#define SET_RG_IQ_DC_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_00)) & 0xcfffffff)) -+#define SET_RG_DAC_DCEN(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_01)) & 0xfffffffe)) -+#define SET_RG_DAC_DCQ(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_01)) & 0xffffc00f)) -+#define SET_RG_DAC_DCI(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_01)) & 0xfc00ffff)) -+#define SET_RG_PGA_REFDB_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffffff80)) -+#define SET_RG_PGA_REFDB_TOP(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffff80ff)) -+#define SET_RG_PGA_REF_UND(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xfc00ffff)) -+#define SET_RG_RF_REF_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_02_AGC)) & 0x0fffffff)) -+#define SET_RG_PGAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xfffffff0)) -+#define SET_RG_PGAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffffef)) -+#define SET_RG_RFGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff9f)) -+#define SET_RG_RFGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff7f)) -+#define SET_RG_WAIT_T_RXAGC(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffc0ff)) -+#define SET_RG_RXAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffbfff)) -+#define SET_RG_RXAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffff7fff)) -+#define SET_RG_WAIT_T_FINAL(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffc0ffff)) -+#define SET_RG_WAIT_T(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xc0ffffff)) -+#define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffffff0)) -+#define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffffff0f)) -+#define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffff0ff)) -+#define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffff0fff)) -+#define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfff0ffff)) -+#define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xff0fffff)) -+#define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xf0ffffff)) -+#define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_04_AGC)) & 0x0fffffff)) -+#define SET_RG_MG_PGA_JB_TH(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xfffffff0)) -+#define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xffe0ffff)) -+#define SET_RG_WR_RFGC_INIT_SET(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 21) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff9fffff)) -+#define SET_RG_WR_RFGC_INIT_EN(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff7fffff)) -+#define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xe0ffffff)) -+#define SET_RG_AGC_THRESHOLD(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xffffc000)) -+#define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xff80ffff)) -+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xfcffffff)) -+#define SET_RG_WR_ACI_GAIN_INI_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffffff00)) -+#define SET_RG_WR_ACI_GAIN_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffff00ff)) -+#define SET_RG_ACI_DAGC_SET_VALUE_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xff80ffff)) -+#define SET_RG_WR_ACI_GAIN_OW_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x7fffffff)) -+#define SET_RG_ACI_POINT_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xffffff00)) -+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xfffffcff)) -+#define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00ffffff)) -+#define SET_RG_ACI_DAGC_SET_VALUE_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffffff80)) -+#define SET_RG_ACI_GAIN_INI_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffff00ff)) -+#define SET_RG_ACI_GAIN_OW_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xff00ffff)) -+#define SET_RG_ACI_GAIN_OW_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x7fffffff)) -+#define SET_RO_CCA_PWR_MA_11GN(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffffff80)) -+#define SET_RO_ED_STATE(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffff7fff)) -+#define SET_RO_CCA_PWR_MA_11B(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xff80ffff)) -+#define SET_RO_PGA_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xffffc000)) -+#define SET_RO_RF_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xfff0ffff)) -+#define SET_RO_PGAGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xf0ffffff)) -+#define SET_RO_RFGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xcfffffff)) -+#define SET_RO_PGA_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xffffc000)) -+#define SET_RO_RF_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xfff0ffff)) -+#define SET_RO_PGAGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xf0ffffff)) -+#define SET_RO_RFGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xcfffffff)) -+#define SET_RO_PGA_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xffffc000)) -+#define SET_RO_RF_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xfff0ffff)) -+#define SET_RO_PGAGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xf0ffffff)) -+#define SET_RO_RFGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xcfffffff)) -+#define SET_RG_TX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffffe0)) -+#define SET_RG_TX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffe0ff)) -+#define SET_RG_TX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffe0ffff)) -+#define SET_RG_TX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xe0ffffff)) -+#define SET_RG_TX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffffe0)) -+#define SET_RG_TX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffe0ff)) -+#define SET_RG_TX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffe0ffff)) -+#define SET_RG_TX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xe0ffffff)) -+#define SET_RG_TX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffffe)) -+#define SET_RG_TX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffffef)) -+#define SET_RG_TX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffeff)) -+#define SET_RG_TX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffefff)) -+#define SET_RG_TX_DES_PWRLVL(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffe0ffff)) -+#define SET_RG_TX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xe0ffffff)) -+#define SET_RG_RX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffffc0)) -+#define SET_RG_RX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffc0ff)) -+#define SET_RG_RX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffc0ffff)) -+#define SET_RG_RX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xc0ffffff)) -+#define SET_RG_RX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffffc0)) -+#define SET_RG_RX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffc0ff)) -+#define SET_RG_RX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffc0ffff)) -+#define SET_RG_RX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xc0ffffff)) -+#define SET_RG_RX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffffe)) -+#define SET_RG_RX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffffef)) -+#define SET_RG_RX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffeff)) -+#define SET_RG_RX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffefff)) -+#define SET_RG_RX_DES_SNR(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfff0ffff)) -+#define SET_RG_RX_DES_RCPI(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xff0fffff)) -+#define SET_RG_RX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xc0ffffff)) -+#define SET_RO_TX_DES_EXCP_RATE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffffff00)) -+#define SET_RO_TX_DES_EXCP_CH_BW_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffff00ff)) -+#define SET_RO_TX_DES_EXCP_MODE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xff00ffff)) -+#define SET_RG_TX_DES_EXCP_RATE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xf8ffffff)) -+#define SET_RG_TX_DES_EXCP_MODE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x8fffffff)) -+#define SET_RG_TX_DES_EXCP_CLR(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x7fffffff)) -+#define SET_RG_TX_DES_ACK_WIDTH(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffffe)) -+#define SET_RG_TX_DES_ACK_PRD(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffff1)) -+#define SET_RG_RX_DES_SNR_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xffc0ffff)) -+#define SET_RG_RX_DES_RCPI_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xc0ffffff)) -+#define SET_RG_TST_TBUS_SEL(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfffffff0)) -+#define SET_RG_RSSI_OFFSET(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xff00ffff)) -+#define SET_RG_RSSI_INV(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfeffffff)) -+#define SET_RG_TST_ADC_ON(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xbfffffff)) -+#define SET_RG_TST_EXT_GAIN(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x7fffffff)) -+#define SET_RG_DAC_Q_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xfffffc00)) -+#define SET_RG_DAC_I_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xffc00fff)) -+#define SET_RG_DAC_EN_MAN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xefffffff)) -+#define SET_RG_IQC_FFT_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xdfffffff)) -+#define SET_RG_DAC_MAN_Q_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xbfffffff)) -+#define SET_RG_DAC_MAN_I_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x7fffffff)) -+#define SET_RO_MRX_EN_CNT(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0xffff0000)) -+#define SET_RG_MRX_EN_CNT_RST_N(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x7fffffff)) -+#define SET_RG_PA_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffffff00)) -+#define SET_RG_RFTX_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffff00ff)) -+#define SET_RG_DAC_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff00ffff)) -+#define SET_RG_SW_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ffffff)) -+#define SET_RG_PA_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffffff00)) -+#define SET_RG_RFTX_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffff00ff)) -+#define SET_RG_DAC_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff00ffff)) -+#define SET_RG_SW_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ffffff)) -+#define SET_RG_ANT_SW_0(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xfffffff8)) -+#define SET_RG_ANT_SW_1(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xffffffc7)) -+#define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xffffe000)) -+#define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xe000ffff)) -+#define SET_RG_MTX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x7fffffff)) -+#define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xffffe000)) -+#define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xe000ffff)) -+#define SET_RG_MTX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x7fffffff)) -+#define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xffffe000)) -+#define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xe000ffff)) -+#define SET_RG_MRX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x7fffffff)) -+#define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xffffe000)) -+#define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xe000ffff)) -+#define SET_RG_MRX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x7fffffff)) -+#define SET_RO_MTX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000)) -+#define SET_RO_MTX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff)) -+#define SET_RO_MRX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000)) -+#define SET_RO_MRX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff)) -+#define SET_RG_MODE_REG_IN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffff0000)) -+#define SET_RG_PARALLEL_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffefffff)) -+#define SET_RG_MBRUN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xfeffffff)) -+#define SET_RG_SHIFT_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xefffffff)) -+#define SET_RG_MODE_REG_SI_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xdfffffff)) -+#define SET_RG_SIMULATION_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xbfffffff)) -+#define SET_RG_DBIST_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_28_BIST)) & 0x7fffffff)) -+#define SET_RO_MODE_REG_OUT_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xffff0000)) -+#define SET_RO_MODE_REG_SO_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xfeffffff)) -+#define SET_RO_MONITOR_BUS_16(_VAL_) (REG32(ADR_PHY_READ_REG_07_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_07_BIST)) & 0xfff80000)) -+#define SET_RG_MRX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffffff00)) -+#define SET_RG_MRX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffff00ff)) -+#define SET_RG_MTX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff00ffff)) -+#define SET_RG_MTX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ffffff)) -+#define SET_RO_MTX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000)) -+#define SET_RO_MTX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff)) -+#define SET_RO_MRX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000)) -+#define SET_RO_MRX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff)) -+#define SET_RG_HB_COEF0(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xfffff000)) -+#define SET_RG_HB_COEF1(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xf000ffff)) -+#define SET_RG_HB_COEF2(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xfffff000)) -+#define SET_RG_HB_COEF3(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xf000ffff)) -+#define SET_RG_HB_COEF4(_VAL_) (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0xfffff000)) -+#define SET_RO_TBUS_O(_VAL_) (REG32(ADR_PHY_READ_TBUS)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_TBUS)) & 0xfff00000)) -+#define SET_RG_LPF4_00(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_00)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_00)) & 0xffffe000)) -+#define SET_RG_LPF4_01(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_01)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_01)) & 0xffffe000)) -+#define SET_RG_LPF4_02(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_02)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_02)) & 0xffffe000)) -+#define SET_RG_LPF4_03(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_03)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_03)) & 0xffffe000)) -+#define SET_RG_LPF4_04(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_04)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_04)) & 0xffffe000)) -+#define SET_RG_LPF4_05(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_05)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_05)) & 0xffffe000)) -+#define SET_RG_LPF4_06(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_06)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_06)) & 0xffffe000)) -+#define SET_RG_LPF4_07(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_07)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_07)) & 0xffffe000)) -+#define SET_RG_LPF4_08(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_08)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_08)) & 0xffffe000)) -+#define SET_RG_LPF4_09(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_09)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_09)) & 0xffffe000)) -+#define SET_RG_LPF4_10(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_10)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_10)) & 0xffffe000)) -+#define SET_RG_LPF4_11(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_11)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_11)) & 0xffffe000)) -+#define SET_RG_LPF4_12(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_12)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_12)) & 0xffffe000)) -+#define SET_RG_LPF4_13(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_13)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_13)) & 0xffffe000)) -+#define SET_RG_LPF4_14(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_14)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_14)) & 0xffffe000)) -+#define SET_RG_LPF4_15(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_15)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_15)) & 0xffffe000)) -+#define SET_RG_LPF4_16(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_16)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_16)) & 0xffffe000)) -+#define SET_RG_LPF4_17(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_17)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_17)) & 0xffffe000)) -+#define SET_RG_LPF4_18(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_18)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_18)) & 0xffffe000)) -+#define SET_RG_LPF4_19(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_19)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_19)) & 0xffffe000)) -+#define SET_RG_LPF4_20(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_20)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_20)) & 0xffffe000)) -+#define SET_RG_LPF4_21(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_21)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_21)) & 0xffffe000)) -+#define SET_RG_LPF4_22(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_22)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_22)) & 0xffffe000)) -+#define SET_RG_LPF4_23(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_23)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_23)) & 0xffffe000)) -+#define SET_RG_LPF4_24(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_24)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_24)) & 0xffffe000)) -+#define SET_RG_LPF4_25(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_25)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_25)) & 0xffffe000)) -+#define SET_RG_LPF4_26(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_26)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_26)) & 0xffffe000)) -+#define SET_RG_LPF4_27(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_27)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_27)) & 0xffffe000)) -+#define SET_RG_LPF4_28(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_28)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_28)) & 0xffffe000)) -+#define SET_RG_LPF4_29(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_29)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_29)) & 0xffffe000)) -+#define SET_RG_LPF4_30(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_30)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_30)) & 0xffffe000)) -+#define SET_RG_LPF4_31(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_31)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_31)) & 0xffffe000)) -+#define SET_RG_LPF4_32(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_32)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_32)) & 0xffffe000)) -+#define SET_RG_LPF4_33(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_33)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_33)) & 0xffffe000)) -+#define SET_RG_LPF4_34(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_34)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_34)) & 0xffffe000)) -+#define SET_RG_LPF4_35(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_35)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_35)) & 0xffffe000)) -+#define SET_RG_LPF4_36(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_36)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_36)) & 0xffffe000)) -+#define SET_RG_LPF4_37(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_37)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_37)) & 0xffffe000)) -+#define SET_RG_LPF4_38(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_38)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_38)) & 0xffffe000)) -+#define SET_RG_LPF4_39(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_39)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_39)) & 0xffffe000)) -+#define SET_RG_LPF4_40(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_40)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_40)) & 0xffffe000)) -+#define SET_RG_BP_SMB(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 13) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffdfff)) -+#define SET_RG_EN_SRVC(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 14) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffbfff)) -+#define SET_RG_DES_SPD(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 16) | ((REG32(ADR_TX_11B_PLCP)) & 0xfffcffff)) -+#define SET_RG_BB_11B_RISE_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_RAMP)) & 0xffffff00)) -+#define SET_RG_BB_11B_FALL_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11B_RAMP)) & 0xffff00ff)) -+#define SET_RG_WR_TX_EN_CNT_RST_N(_VAL_) (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0xfffffffe)) -+#define SET_RO_TX_EN_CNT(_VAL_) (REG32(ADR_TX_11B_EN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT)) & 0xffff0000)) -+#define SET_RO_TX_CNT(_VAL_) (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0x00000000)) -+#define SET_RG_POS_DES_11B_L_EXT(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xfffffff0)) -+#define SET_RG_PRE_DES_11B_DLY(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xffffff0f)) -+#define SET_RG_CNT_CCA_LMT(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_0)) & 0xfff0ffff)) -+#define SET_RG_BYPASS_DESCRAMBLER(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11B_CCA_0)) & 0xdfffffff)) -+#define SET_RG_BYPASS_AGC(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11B_CCA_0)) & 0x7fffffff)) -+#define SET_RG_CCA_BIT_CNT_LMT_RX(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CCA_1)) & 0xffffff0f)) -+#define SET_RG_CCA_SCALE_BF(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_1)) & 0xff80ffff)) -+#define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11B_CCA_1)) & 0xcfffffff)) -+#define SET_RG_TR_KI_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffffff8)) -+#define SET_RG_TR_KP_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffffff8f)) -+#define SET_RG_TR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffff8ff)) -+#define SET_RG_TR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffff8fff)) -+#define SET_RG_CR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xfff8ffff)) -+#define SET_RG_CR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xff8fffff)) -+#define SET_RG_CHIP_CNT_SLICER(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffffffe0)) -+#define SET_RG_CE_T4_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffff00ff)) -+#define SET_RG_CE_T3_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff00ffff)) -+#define SET_RG_CE_T2_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ffffff)) -+#define SET_RG_CE_MU_T1(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xfffffff8)) -+#define SET_RG_CE_DLY_SEL(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xffc0ffff)) -+#define SET_RG_CE_MU_T8(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffffff8)) -+#define SET_RG_CE_MU_T7(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffffff8f)) -+#define SET_RG_CE_MU_T6(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffff8ff)) -+#define SET_RG_CE_MU_T5(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffff8fff)) -+#define SET_RG_CE_MU_T4(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfff8ffff)) -+#define SET_RG_CE_MU_T3(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xff8fffff)) -+#define SET_RG_CE_MU_T2(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xf8ffffff)) -+#define SET_RG_EQ_MU_FB_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfffffff0)) -+#define SET_RG_EQ_MU_FF_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xffffff0f)) -+#define SET_RG_EQ_MU_FB_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfff0ffff)) -+#define SET_RG_EQ_MU_FF_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xff0fffff)) -+#define SET_RG_EQ_MU_FB_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfffffff0)) -+#define SET_RG_EQ_MU_FF_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xffffff0f)) -+#define SET_RG_EQ_MU_FB_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfff0ffff)) -+#define SET_RG_EQ_MU_FF_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xff0fffff)) -+#define SET_RG_EQ_KI_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfffff8ff)) -+#define SET_RG_EQ_KP_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xffff8fff)) -+#define SET_RG_EQ_KI_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfff8ffff)) -+#define SET_RG_EQ_KP_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xff8fffff)) -+#define SET_RG_TR_LPF_RATE(_VAL_) (REG32(ADR_RX_11B_LPF_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_LPF_RATE)) & 0xffc00000)) -+#define SET_RG_CE_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff80)) -+#define SET_RG_CE_CH_MAIN_SET(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff7f)) -+#define SET_RG_TC_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffff80ff)) -+#define SET_RG_CR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xff80ffff)) -+#define SET_RG_TR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x80ffffff)) -+#define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xfffffffe)) -+#define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xf800ffff)) -+#define SET_RG_PWRON_DLY_TH_11B(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xffffff00)) -+#define SET_RG_SFD_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xff00ffff)) -+#define SET_RG_CCA_PWR_TH_RX(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffff8000)) -+#define SET_RG_CCA_PWR_CNT_TH(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffe0ffff)) -+#define SET_B_FREQ_OS(_VAL_) (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0xfffff800)) -+#define SET_B_SNR(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xffffff80)) -+#define SET_B_RCPI(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xff80ffff)) -+#define SET_CRC_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000)) -+#define SET_SFD_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff)) -+#define SET_B_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xffff0000)) -+#define SET_PACKET_ERR(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xfffeffff)) -+#define SET_B_PACKET_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000)) -+#define SET_B_CCA_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff)) -+#define SET_B_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000)) -+#define SET_SFD_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff)) -+#define SET_SIGNAL_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffffff00)) -+#define SET_B_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffff00ff)) -+#define SET_CRC_CORRECT(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xfffeffff)) -+#define SET_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xfffffff0)) -+#define SET_RG_PACKET_STAT_EN_11B(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffefffff)) -+#define SET_RG_BIT_REVERSE(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffdfffff)) -+#define SET_RX_PHY_11B_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffffffe)) -+#define SET_RG_CE_BYPASS_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xffffff0f)) -+#define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffff0ff)) -+#define SET_RG_BB_11GN_RISE_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffffff00)) -+#define SET_RG_BB_11GN_FALL_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffff00ff)) -+#define SET_RG_HTCARR52_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP)) & 0xfffffc00)) -+#define SET_RG_HTCARR56_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 12) | ((REG32(ADR_TX_11GN_PLCP)) & 0xffc00fff)) -+#define SET_RG_PACKET_STAT_EN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 23) | ((REG32(ADR_TX_11GN_PLCP)) & 0xff7fffff)) -+#define SET_RG_SMB_DEF(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 24) | ((REG32(ADR_TX_11GN_PLCP)) & 0x80ffffff)) -+#define SET_RG_CONTINUOUS_DATA_11GN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 31) | ((REG32(ADR_TX_11GN_PLCP)) & 0x7fffffff)) -+#define SET_RO_TX_CNT_R(_VAL_) (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0x00000000)) -+#define SET_RO_PACKET_ERR_CNT(_VAL_) (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0xffff0000)) -+#define SET_RG_POS_DES_11GN_L_EXT(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xfffffff0)) -+#define SET_RG_PRE_DES_11GN_DLY(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xffffff0f)) -+#define SET_RG_TR_LPF_KI_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfffffff0)) -+#define SET_RG_TR_LPF_KP_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffffff0f)) -+#define SET_RG_TR_CNT_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffff00ff)) -+#define SET_RG_TR_LPF_KI_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfff0ffff)) -+#define SET_RG_TR_LPF_KP_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TR_0)) & 0xff0fffff)) -+#define SET_RG_TR_CNT_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_TR_0)) & 0x00ffffff)) -+#define SET_RG_TR_LPF_KI_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_1)) & 0xfffffff0)) -+#define SET_RG_TR_LPF_KP_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffffff0f)) -+#define SET_RG_TR_CNT_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffff00ff)) -+#define SET_RG_TR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_2)) & 0xfffffff0)) -+#define SET_RG_TR_LPF_KP_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_2)) & 0xffffff0f)) -+#define SET_RG_TR_LPF_RATE_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_2)) & 0xc00000ff)) -+#define SET_RG_CR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xfffffff8)) -+#define SET_RG_SYM_BOUND_CNT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xffff80ff)) -+#define SET_RG_XSCOR32_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xff80ffff)) -+#define SET_RG_ATCOR64_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_0)) & 0x80ffffff)) -+#define SET_RG_ATCOR16_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xffff80ff)) -+#define SET_RG_ATCOR16_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xff80ffff)) -+#define SET_RG_ATCOR16_RATIO_SB(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_1)) & 0x80ffffff)) -+#define SET_RG_XSCOR64_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_2)) & 0xff80ffff)) -+#define SET_RG_XSCOR64_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_2)) & 0x80ffffff)) -+#define SET_RG_RX_FFT_SCALE(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffffc00)) -+#define SET_RG_VITERBI_AB_SWAP(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffeffff)) -+#define SET_RG_ATCOR16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xf0ffffff)) -+#define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffffff00)) -+#define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffff00ff)) -+#define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff00ffff)) -+#define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ffffff)) -+#define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0x00ffffff)) -+#define SET_RG_NORMSQUARE_SNR_3(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffffff00)) -+#define SET_RG_NORMSQUARE_SNR_2(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffff00ff)) -+#define SET_RG_NORMSQUARE_SNR_1(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff00ffff)) -+#define SET_RG_NORMSQUARE_SNR_0(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ffffff)) -+#define SET_RG_NORMSQUARE_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffffff00)) -+#define SET_RG_NORMSQUARE_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffff00ff)) -+#define SET_RG_NORMSQUARE_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff00ffff)) -+#define SET_RG_NORMSQUARE_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ffffff)) -+#define SET_RG_NORMSQUARE_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0x00ffffff)) -+#define SET_RG_SNR_TH_64QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffffff80)) -+#define SET_RG_SNR_TH_16QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffff80ff)) -+#define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffffff80)) -+#define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffff80ff)) -+#define SET_RG_SYM_BOUND_METHOD(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xfffcffff)) -+#define SET_RG_PWRON_DLY_TH_11GN(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffffff00)) -+#define SET_RG_SB_START_CNT(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffff80ff)) -+#define SET_RG_POW16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xffffff0f)) -+#define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xfffff8ff)) -+#define SET_RG_POW16_TH_L(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0x80ffffff)) -+#define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfffffff8)) -+#define SET_RG_XSCOR16_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xffff80ff)) -+#define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfff8ffff)) -+#define SET_RG_ATCOR16_RATIO_CCD(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0x80ffffff)) -+#define SET_RG_ATCOR64_ACC_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xffffff80)) -+#define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xfff8ffff)) -+#define SET_RG_VITERBI_TB_BITS(_VAL_) (REG32(ADR_RX_11GN_VTB_TB)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_VTB_TB)) & 0x00ffffff)) -+#define SET_RG_CR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xffffff00)) -+#define SET_RG_TR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xff00ffff)) -+#define SET_RG_BYPASS_CPE_MA(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffffffef)) -+#define SET_RG_PILOT_BNDRY_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfffff8ff)) -+#define SET_RG_EQ_SHORT_GI_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffff8fff)) -+#define SET_RG_FFT_WDW_SHORT_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfff8ffff)) -+#define SET_RG_CHSMTH_COEF(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffcffff)) -+#define SET_RG_CHSMTH_EN(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 18) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffbffff)) -+#define SET_RG_CHEST_DD_FACTOR(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xf8ffffff)) -+#define SET_RG_CH_UPDATE(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x7fffffff)) -+#define SET_RG_FMT_DET_MM_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffffff00)) -+#define SET_RG_FMT_DET_GF_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffff00ff)) -+#define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xfdffffff)) -+#define SET_RG_FMT_DET_LENGTH_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000)) -+#define SET_RG_L_LENGTH_MAX(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff)) -+#define SET_RG_TX_TIME_EXT(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xffffff00)) -+#define SET_RG_MAC_DES_SPACE(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xff0fffff)) -+#define SET_RG_TR_LPF_STBC_GF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffffff0)) -+#define SET_RG_TR_LPF_STBC_GF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffffff0f)) -+#define SET_RG_TR_LPF_STBC_MF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffff0ff)) -+#define SET_RG_TR_LPF_STBC_MF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffff0fff)) -+#define SET_RG_MODE_REG_IN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfffe0000)) -+#define SET_RG_PARALLEL_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xffefffff)) -+#define SET_RG_MBRUN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfeffffff)) -+#define SET_RG_SHIFT_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xefffffff)) -+#define SET_RG_MODE_REG_SI_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xdfffffff)) -+#define SET_RG_SIMULATION_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xbfffffff)) -+#define SET_RG_DBIST_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_0)) & 0x7fffffff)) -+#define SET_RG_MODE_REG_IN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffff0000)) -+#define SET_RG_PARALLEL_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffefffff)) -+#define SET_RG_MBRUN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xfeffffff)) -+#define SET_RG_SHIFT_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xefffffff)) -+#define SET_RG_MODE_REG_SI_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xdfffffff)) -+#define SET_RG_SIMULATION_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xbfffffff)) -+#define SET_RG_DBIST_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_1)) & 0x7fffffff)) -+#define SET_RO_MODE_REG_OUT_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfffe0000)) -+#define SET_RO_MODE_REG_SO_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfeffffff)) -+#define SET_RO_MONITOR_BUS_80(_VAL_) (REG32(ADR_RX_11GN_BIST_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_3)) & 0xffc00000)) -+#define SET_RO_MODE_REG_OUT_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xffff0000)) -+#define SET_RO_MODE_REG_SO_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xfeffffff)) -+#define SET_RO_MONITOR_BUS_64(_VAL_) (REG32(ADR_RX_11GN_BIST_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_5)) & 0xfff80000)) -+#define SET_RO_SPECTRUM_DATA(_VAL_) (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0x00000000)) -+#define SET_GN_SNR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffffff80)) -+#define SET_GN_NOISE_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffff80ff)) -+#define SET_GN_RCPI(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_READ_0)) & 0xff80ffff)) -+#define SET_GN_SIGNAL_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_READ_0)) & 0x80ffffff)) -+#define SET_RO_FREQ_OS_LTS(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xffff8000)) -+#define SET_CSTATE(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xfff0ffff)) -+#define SET_SIGNAL_FIELD0(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0xff000000)) -+#define SET_SIGNAL_FIELD1(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0xff000000)) -+#define SET_GN_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0xffff0000)) -+#define SET_GN_PACKET_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000)) -+#define SET_GN_CCA_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff)) -+#define SET_GN_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000)) -+#define SET_GN_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff)) -+#define SET_RO_HT_MCS_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffff80)) -+#define SET_RO_L_RATE_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffc0ff)) -+#define SET_RG_DAGC_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xfffffffc)) -+#define SET_RG_PACKET_STAT_EN_11GN(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xffefffff)) -+#define SET_RX_PHY_11GN_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffe)) -+#define SET_RG_RIFS_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 1) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffd)) -+#define SET_RG_STBC_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 2) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffb)) -+#define SET_RG_COR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 3) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffff7)) -+#define SET_RG_INI_PHASE(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffcf)) -+#define SET_RG_HT_LTF_SEL_EQ(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 6) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffbf)) -+#define SET_RG_HT_LTF_SEL_PILOT(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffff7f)) -+#define SET_RG_CCA_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 9) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffdff)) -+#define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 10) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffbff)) -+#define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 11) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffff7ff)) -+#define SET_RG_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffff0fff)) -+#define SET_RG_POST_CLK_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffeffff)) -+#define SET_IQCAL_RF_TX_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffe)) -+#define SET_IQCAL_RF_TX_PA_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 1) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffd)) -+#define SET_IQCAL_RF_TX_DAC_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 2) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffb)) -+#define SET_IQCAL_RF_RX_AGC(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 3) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffff7)) -+#define SET_IQCAL_RF_PGAG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffff0ff)) -+#define SET_IQCAL_RF_RFG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 12) | ((REG32(ADR_RF_CONTROL_0)) & 0xffffcfff)) -+#define SET_RG_TONEGEN_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_CONTROL_0)) & 0xff80ffff)) -+#define SET_RG_TONEGEN_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 23) | ((REG32(ADR_RF_CONTROL_0)) & 0xff7fffff)) -+#define SET_RG_TONEGEN_INIT_PH(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_CONTROL_0)) & 0x80ffffff)) -+#define SET_RG_TONEGEN2_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff80)) -+#define SET_RG_TONEGEN2_EN(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 7) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff7f)) -+#define SET_RG_TONEGEN2_SCALE(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_1)) & 0xffff00ff)) -+#define SET_RG_TXIQ_CLP_THD_I(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfffffc00)) -+#define SET_RG_TXIQ_CLP_THD_Q(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfc00ffff)) -+#define SET_RG_TX_I_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffffff00)) -+#define SET_RG_TX_Q_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffff00ff)) -+#define SET_RG_TX_IQ_SWP(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffeffff)) -+#define SET_RG_TX_SGN_OUT(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 17) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffdffff)) -+#define SET_RG_TXIQ_EMU_IDX(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 18) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffc3ffff)) -+#define SET_RG_TX_IQ_SRC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfcffffff)) -+#define SET_RG_TX_I_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfffffc00)) -+#define SET_RG_TX_Q_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfc00ffff)) -+#define SET_RG_TX_IQ_THETA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffffe0)) -+#define SET_RG_TX_IQ_ALPHA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffe0ff)) -+#define SET_RG_TXIQ_NOSHRINK(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffdfff)) -+#define SET_RG_TX_I_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff00ffff)) -+#define SET_RG_TX_Q_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 24) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ffffff)) -+#define SET_RG_RX_IQ_THETA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffffe0)) -+#define SET_RG_RX_IQ_ALPHA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffe0ff)) -+#define SET_RG_RXIQ_NOSHRINK(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffdfff)) -+#define SET_RG_MA_DPTH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffff0)) -+#define SET_RG_INTG_PH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffc0f)) -+#define SET_RG_INTG_PRD(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 10) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffffe3ff)) -+#define SET_RG_INTG_MU(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 13) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffff9fff)) -+#define SET_RG_IQCAL_SPRM_SELQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffeffff)) -+#define SET_RG_IQCAL_SPRM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 17) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffdffff)) -+#define SET_RG_IQCAL_SPRM_FREQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 18) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xff03ffff)) -+#define SET_RG_IQCAL_IQCOL_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfeffffff)) -+#define SET_RG_IQCAL_ALPHA_ESTM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfdffffff)) -+#define SET_RG_IQCAL_DC_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfbffffff)) -+#define SET_RG_PHEST_STBY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xf7ffffff)) -+#define SET_RG_PHEST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xefffffff)) -+#define SET_RG_GP_DIV_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xdfffffff)) -+#define SET_RG_DPD_GAIN_EST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xbfffffff)) -+#define SET_RG_IQCAL_MULT_OP0(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfffffc00)) -+#define SET_RG_IQCAL_MULT_OP1(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfc00ffff)) -+#define SET_RO_IQCAL_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfff00000)) -+#define SET_RO_IQCAL_SPRM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 20) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffefffff)) -+#define SET_RO_IQCAL_IQCOL_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 21) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffdfffff)) -+#define SET_RO_IQCAL_ALPHA_ESTM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 22) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffbfffff)) -+#define SET_RO_IQCAL_DC_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 23) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xff7fffff)) -+#define SET_RO_IQCAL_MULT_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfeffffff)) -+#define SET_RO_FFT_ENRG_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfdffffff)) -+#define SET_RO_PHEST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfbffffff)) -+#define SET_RO_GP_DIV_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xf7ffffff)) -+#define SET_RO_GAIN_EST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xefffffff)) -+#define SET_RO_AMP_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0xfffffe00)) -+#define SET_RG_RX_I_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffffff00)) -+#define SET_RG_RX_Q_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffff00ff)) -+#define SET_RG_RX_I_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff00ffff)) -+#define SET_RG_RX_Q_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ffffff)) -+#define SET_RG_RX_IQ_SWP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffe)) -+#define SET_RG_RX_SGN_IN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffd)) -+#define SET_RG_RX_IQ_SRC(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 2) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffff3)) -+#define SET_RG_ACI_GAIN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffff00f)) -+#define SET_RG_FFT_EN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 12) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffefff)) -+#define SET_RG_FFT_MOD(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 13) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffdfff)) -+#define SET_RG_FFT_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 14) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xff003fff)) -+#define SET_RG_FFT_ENRG_FREQ(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xc0ffffff)) -+#define SET_RG_FPGA_80M_PH_UP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 30) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xbfffffff)) -+#define SET_RG_FPGA_80M_PH_STP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 31) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0x7fffffff)) -+#define SET_RG_ADC2LA_SEL(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffe)) -+#define SET_RG_ADC2LA_CLKPH(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffd)) -+#define SET_RG_RXIQ_EMU_IDX(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xfffffff0)) -+#define SET_RG_IQCAL_BP_ACI(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xffffffef)) -+#define SET_RG_DPD_AM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffe)) -+#define SET_RG_DPD_PM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffd)) -+#define SET_RG_DPD_PM_AMSEL(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffb)) -+#define SET_RG_DPD_020_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfffffc00)) -+#define SET_RG_DPD_040_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfc00ffff)) -+#define SET_RG_DPD_060_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfffffc00)) -+#define SET_RG_DPD_080_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfc00ffff)) -+#define SET_RG_DPD_0A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfffffc00)) -+#define SET_RG_DPD_0C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfc00ffff)) -+#define SET_RG_DPD_0D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfffffc00)) -+#define SET_RG_DPD_0E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfc00ffff)) -+#define SET_RG_DPD_0F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfffffc00)) -+#define SET_RG_DPD_100_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfc00ffff)) -+#define SET_RG_DPD_110_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfffffc00)) -+#define SET_RG_DPD_120_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfc00ffff)) -+#define SET_RG_DPD_130_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfffffc00)) -+#define SET_RG_DPD_140_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfc00ffff)) -+#define SET_RG_DPD_150_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfffffc00)) -+#define SET_RG_DPD_160_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfc00ffff)) -+#define SET_RG_DPD_170_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfffffc00)) -+#define SET_RG_DPD_180_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfc00ffff)) -+#define SET_RG_DPD_190_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfffffc00)) -+#define SET_RG_DPD_1A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfc00ffff)) -+#define SET_RG_DPD_1B0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfffffc00)) -+#define SET_RG_DPD_1C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfc00ffff)) -+#define SET_RG_DPD_1D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfffffc00)) -+#define SET_RG_DPD_1E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfc00ffff)) -+#define SET_RG_DPD_1F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfffffc00)) -+#define SET_RG_DPD_200_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfc00ffff)) -+#define SET_RG_DPD_020_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xffffe000)) -+#define SET_RG_DPD_040_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xe000ffff)) -+#define SET_RG_DPD_060_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xffffe000)) -+#define SET_RG_DPD_080_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xe000ffff)) -+#define SET_RG_DPD_0A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xffffe000)) -+#define SET_RG_DPD_0C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xe000ffff)) -+#define SET_RG_DPD_0D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xffffe000)) -+#define SET_RG_DPD_0E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xe000ffff)) -+#define SET_RG_DPD_0F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xffffe000)) -+#define SET_RG_DPD_100_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xe000ffff)) -+#define SET_RG_DPD_110_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xffffe000)) -+#define SET_RG_DPD_120_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xe000ffff)) -+#define SET_RG_DPD_130_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xffffe000)) -+#define SET_RG_DPD_140_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xe000ffff)) -+#define SET_RG_DPD_150_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xffffe000)) -+#define SET_RG_DPD_160_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xe000ffff)) -+#define SET_RG_DPD_170_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xffffe000)) -+#define SET_RG_DPD_180_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xe000ffff)) -+#define SET_RG_DPD_190_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xffffe000)) -+#define SET_RG_DPD_1A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xe000ffff)) -+#define SET_RG_DPD_1B0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xffffe000)) -+#define SET_RG_DPD_1C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xe000ffff)) -+#define SET_RG_DPD_1D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xffffe000)) -+#define SET_RG_DPD_1E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xe000ffff)) -+#define SET_RG_DPD_1F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xffffe000)) -+#define SET_RG_DPD_200_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xe000ffff)) -+#define SET_RG_DPD_GAIN_EST_Y0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfffffe00)) -+#define SET_RG_DPD_GAIN_EST_Y1(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfe00ffff)) -+#define SET_RG_DPD_LOOP_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0xfffffc00)) -+#define SET_RG_DPD_GAIN_EST_X0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfffffe00)) -+#define SET_RO_DPD_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfc00ffff)) -+#define SET_TX_SCALE_11B(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffffff00)) -+#define SET_TX_SCALE_11B_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 8) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffff00ff)) -+#define SET_TX_SCALE_11G(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xff00ffff)) -+#define SET_TX_SCALE_11G_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 24) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ffffff)) -+#define SET_RG_EN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe)) -+#define SET_RG_TX_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd)) -+#define SET_RG_TX_PA_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb)) -+#define SET_RG_TX_DAC_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7)) -+#define SET_RG_RX_AGC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef)) -+#define SET_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf)) -+#define SET_RG_RFG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f)) -+#define SET_RG_PGAG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff)) -+#define SET_RG_MODE(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff)) -+#define SET_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff)) -+#define SET_RG_EN_SX(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff)) -+#define SET_RG_EN_RX_LNA(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff)) -+#define SET_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff)) -+#define SET_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff)) -+#define SET_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff)) -+#define SET_RG_EN_RX_TZ(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff)) -+#define SET_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff)) -+#define SET_RG_EN_RX_HPF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff)) -+#define SET_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff)) -+#define SET_RG_EN_ADC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff)) -+#define SET_RG_EN_TX_MOD(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff)) -+#define SET_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff)) -+#define SET_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff)) -+#define SET_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff)) -+#define SET_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff)) -+#define SET_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff)) -+#define SET_RG_EN_CLK_960MBY13_UART(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x7fffffff)) -+#define SET_RG_EN_TX_DPD(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe)) -+#define SET_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd)) -+#define SET_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb)) -+#define SET_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7)) -+#define SET_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffef)) -+#define SET_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf)) -+#define SET_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf)) -+#define SET_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f)) -+#define SET_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff)) -+#define SET_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff)) -+#define SET_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff)) -+#define SET_RG_EN_IREF_RX(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff)) -+#define SET_RG_EN_TX_DAC_VOUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffdfff)) -+#define SET_RG_EN_SX_LCK_BIN(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffbfff)) -+#define SET_RG_RTC_CAL_MODE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffeffff)) -+#define SET_RG_EN_IQPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffdffff)) -+#define SET_RG_EN_TESTPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffbffff)) -+#define SET_RG_EN_TRXBF_BYPASS(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfff7ffff)) -+#define SET_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffff8)) -+#define SET_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_LDO_REGISTER)) & 0xffffffc7)) -+#define SET_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffe3f)) -+#define SET_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_LDO_REGISTER)) & 0xfffff1ff)) -+#define SET_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_LDO_REGISTER)) & 0xffff8fff)) -+#define SET_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_LDO_REGISTER)) & 0xfffc7fff)) -+#define SET_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_LDO_REGISTER)) & 0xffe3ffff)) -+#define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_LDO_REGISTER)) & 0xff1fffff)) -+#define SET_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_LDO_REGISTER)) & 0xf8ffffff)) -+#define SET_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffe)) -+#define SET_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffd)) -+#define SET_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffb)) -+#define SET_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffe07)) -+#define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffdff)) -+#define SET_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffbff)) -+#define SET_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffff7ff)) -+#define SET_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffffcfff)) -+#define SET_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffff3fff)) -+#define SET_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffcffff)) -+#define SET_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfff3ffff)) -+#define SET_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffcfffff)) -+#define SET_RG_RX_HPF3M(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffbfffff)) -+#define SET_RG_RX_HPF300K(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_1)) & 0xff7fffff)) -+#define SET_RG_RX_HPFI(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfcffffff)) -+#define SET_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_ABB_REGISTER_1)) & 0xf3ffffff)) -+#define SET_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_ABB_REGISTER_1)) & 0xcfffffff)) -+#define SET_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffffc)) -+#define SET_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffff3)) -+#define SET_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffffcf)) -+#define SET_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffff3f)) -+#define SET_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffcff)) -+#define SET_RG_RX_OUTVCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffff3ff)) -+#define SET_RG_RX_TZI(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffcfff)) -+#define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffbfff)) -+#define SET_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffe7fff)) -+#define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfff1ffff)) -+#define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffefffff)) -+#define SET_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_ABB_REGISTER_2)) & 0xff9fffff)) -+#define SET_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfe7fffff)) -+#define SET_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfdffffff)) -+#define SET_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffffffc)) -+#define SET_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffff03)) -+#define SET_RG_TXPGA_STEER(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffc0ff)) -+#define SET_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffff3fff)) -+#define SET_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffcffff)) -+#define SET_RG_PACELL_EN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffe3ffff)) -+#define SET_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfe1fffff)) -+#define SET_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_TX_FE_REGISTER)) & 0xf3ffffff)) -+#define SET_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_TX_FE_REGISTER)) & 0xcfffffff)) -+#define SET_RG_RX_SQDC(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffffff8)) -+#define SET_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffffe7)) -+#define SET_RG_RX_LOBUF(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffff9f)) -+#define SET_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffff87f)) -+#define SET_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffff87ff)) -+#define SET_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffc7fff)) -+#define SET_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffe3ffff)) -+#define SET_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffdfffff)) -+#define SET_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xff3fffff)) -+#define SET_RG_PACASCODE_CTRL(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xf8ffffff)) -+#define SET_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc)) -+#define SET_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3)) -+#define SET_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f)) -+#define SET_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff)) -+#define SET_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff)) -+#define SET_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff)) -+#define SET_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc)) -+#define SET_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3)) -+#define SET_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f)) -+#define SET_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff)) -+#define SET_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff)) -+#define SET_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff)) -+#define SET_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc)) -+#define SET_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3)) -+#define SET_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f)) -+#define SET_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff)) -+#define SET_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff)) -+#define SET_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff)) -+#define SET_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc)) -+#define SET_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3)) -+#define SET_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f)) -+#define SET_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff)) -+#define SET_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff)) -+#define SET_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff)) -+#define SET_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffe)) -+#define SET_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffd)) -+#define SET_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffb)) -+#define SET_RG_HPF_T1A(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffffe7)) -+#define SET_RG_HPF_T1B(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffff9f)) -+#define SET_RG_HPF_T1C(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffe7f)) -+#define SET_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffff9ff)) -+#define SET_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffe7ff)) -+#define SET_RG_TXGAIN_PHYCTRL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffdfff)) -+#define SET_RG_TX_GAIN(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffc03fff)) -+#define SET_RG_TXGAIN_MANUAL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffbfffff)) -+#define SET_RG_TX_GAIN_OFFSET(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xf87fffff)) -+#define SET_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffffe)) -+#define SET_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff9)) -+#define SET_RG_ADC_DIVR(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff7)) -+#define SET_RG_ADC_DVCMI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffffffcf)) -+#define SET_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffc3f)) -+#define SET_RG_ADC_STNBY(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffbff)) -+#define SET_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffff7ff)) -+#define SET_RG_ADC_TSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffff0fff)) -+#define SET_RG_ADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffcffff)) -+#define SET_RG_DICMP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfff3ffff)) -+#define SET_RG_DIOP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffcfffff)) -+#define SET_RG_SARADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xff3fffff)) -+#define SET_RG_EN_SAR_TEST(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfcffffff)) -+#define SET_RG_SARADC_THERMAL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfbffffff)) -+#define SET_RG_SARADC_TSSI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xf7ffffff)) -+#define SET_RG_CLK_SAR_SEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xcfffffff)) -+#define SET_RG_EN_SARADC(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xbfffffff)) -+#define SET_RG_DACI1ST(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffffc)) -+#define SET_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffff3)) -+#define SET_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffffcf)) -+#define SET_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffff3f)) -+#define SET_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffeff)) -+#define SET_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffff9ff)) -+#define SET_RG_TX_DAC_OS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffc7ff)) -+#define SET_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffff3fff)) -+#define SET_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfff0ffff)) -+#define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffefffff)) -+#define SET_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffdfffff)) -+#define SET_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffbfffff)) -+#define SET_RG_TX_DAC_IOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xf87fffff)) -+#define SET_RG_TX_DAC_QOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_TX_DAC_REGISTER)) & 0x87ffffff)) -+#define SET_RG_EN_SX_R3(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffe)) -+#define SET_RG_EN_SX_CH(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffd)) -+#define SET_RG_EN_SX_CHP(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffb)) -+#define SET_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffff7)) -+#define SET_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffef)) -+#define SET_RG_EN_SX_VCO(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffdf)) -+#define SET_RG_EN_SX_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffbf)) -+#define SET_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffeff)) -+#define SET_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffff7ff)) -+#define SET_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffefff)) -+#define SET_RG_EN_SX_DIV(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffdfff)) -+#define SET_RG_EN_SX_LPF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffbfff)) -+#define SET_RG_EN_DPL_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffff7fff)) -+#define SET_RG_DPL_MOD_ORDER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffcffff)) -+#define SET_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_1)) & 0xff000000)) -+#define SET_RG_SX_SEL_CP(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_REGISTER_1)) & 0xf0ffffff)) -+#define SET_RG_SX_SEL_CS(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_REGISTER_1)) & 0x0fffffff)) -+#define SET_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfffff800)) -+#define SET_RG_SX_SEL_C3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_REGISTER_2)) & 0xffff87ff)) -+#define SET_RG_SX_SEL_RS(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfff07fff)) -+#define SET_RG_SX_SEL_R3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfe0fffff)) -+#define SET_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffffe0)) -+#define SET_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffffc1f)) -+#define SET_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffc3ff)) -+#define SET_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffc3fff)) -+#define SET_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffbffff)) -+#define SET_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffc7ffff)) -+#define SET_RG_SX_PFDSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffbfffff)) -+#define SET_RG_SX_PFD_SET(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_SYN_PFD_CHP)) & 0xff7fffff)) -+#define SET_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfeffffff)) -+#define SET_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfdffffff)) -+#define SET_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfbffffff)) -+#define SET_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_SYN_PFD_CHP)) & 0xf7ffffff)) -+#define SET_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_PFD_CHP)) & 0xefffffff)) -+#define SET_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_SYN_PFD_CHP)) & 0xdfffffff)) -+#define SET_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_SYN_PFD_CHP)) & 0xbfffffff)) -+#define SET_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffffff8)) -+#define SET_RG_SX_VCORSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffffff07)) -+#define SET_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffff0ff)) -+#define SET_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffff0fff)) -+#define SET_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfff0ffff)) -+#define SET_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xff0fffff)) -+#define SET_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xf0ffffff)) -+#define SET_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_VCO_LOBF)) & 0x0fffffff)) -+#define SET_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffffc)) -+#define SET_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffffcf)) -+#define SET_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffdff)) -+#define SET_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffbff)) -+#define SET_RG_SX_XO_GM(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff)) -+#define SET_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffdfff)) -+#define SET_RG_SX_LCKEN(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff)) -+#define SET_RG_SX_PREVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xff0fffff)) -+#define SET_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff)) -+#define SET_RG_SX_PH(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffdfff)) -+#define SET_RG_SX_PL(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffbfff)) -+#define SET_RG_XOSC_CBANK_XO(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xfff87fff)) -+#define SET_RG_XOSC_CBANK_XI(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xff87ffff)) -+#define SET_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffffe)) -+#define SET_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 1) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffff9)) -+#define SET_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffe7)) -+#define SET_RG_SX_VT_SET(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffdf)) -+#define SET_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 6) | ((REG32(ADR_SYN_LCK_VT)) & 0xffff803f)) -+#define SET_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffffe)) -+#define SET_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffff9)) -+#define SET_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffffe7)) -+#define SET_RG_DP_CK320BY2(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffbfff)) -+#define SET_RG_DP_OD_TEST(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffdfffff)) -+#define SET_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe)) -+#define SET_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9)) -+#define SET_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7)) -+#define SET_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f)) -+#define SET_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff)) -+#define SET_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff)) -+#define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff)) -+#define SET_RG_DP_RP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff)) -+#define SET_RG_DP_RHP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff)) -+#define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x7fffffff)) -+#define SET_RG_DP_FODIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xfff80fff)) -+#define SET_RG_DP_REFDIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xe03fffff)) -+#define SET_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xffffffc0)) -+#define SET_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffff03f)) -+#define SET_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff)) -+#define SET_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xff03ffff)) -+#define SET_RG_DP_BBPLL_BS(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 24) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xc0ffffff)) -+#define SET_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xffffffc0)) -+#define SET_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffff03f)) -+#define SET_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff)) -+#define SET_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xff03ffff)) -+#define SET_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xffffffc0)) -+#define SET_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffff03f)) -+#define SET_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff)) -+#define SET_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xff03ffff)) -+#define SET_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xffffffc0)) -+#define SET_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffff03f)) -+#define SET_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff)) -+#define SET_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xff03ffff)) -+#define SET_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xffffffc0)) -+#define SET_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffff03f)) -+#define SET_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff)) -+#define SET_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xff03ffff)) -+#define SET_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xffffffc0)) -+#define SET_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffff03f)) -+#define SET_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff)) -+#define SET_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xff03ffff)) -+#define SET_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xffffffc0)) -+#define SET_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffff03f)) -+#define SET_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff)) -+#define SET_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xff03ffff)) -+#define SET_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xffffffc0)) -+#define SET_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffff03f)) -+#define SET_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff)) -+#define SET_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xff03ffff)) -+#define SET_RG_EN_RCAL(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffe)) -+#define SET_RG_RCAL_SPD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffd)) -+#define SET_RG_RCAL_TMR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffe03)) -+#define SET_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffdff)) -+#define SET_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RCAL_REGISTER)) & 0xffff83ff)) -+#define SET_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfffffffe)) -+#define SET_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 1) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffffff01)) -+#define SET_RG_SX_LCK_BIN_OFFSET(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff87fff)) -+#define SET_RG_SX_LCK_BIN_PRECISION(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 19) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff7ffff)) -+#define SET_RG_SX_LOCK_EN_N(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 20) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffefffff)) -+#define SET_RG_SX_LOCK_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 21) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffdfffff)) -+#define SET_RG_SX_SUB_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 22) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffbfffff)) -+#define SET_RG_SX_SUB_SEL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xc07fffff)) -+#define SET_RG_SX_MUX_SEL_VTH_BINL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 30) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xbfffffff)) -+#define SET_RG_TRX_DUMMMY(_VAL_) (REG32(ADR_TRX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_DUMMY_REGISTER)) & 0x00000000)) -+#define SET_RG_SX_DUMMMY(_VAL_) (REG32(ADR_SX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_DUMMY_REGISTER)) & 0x00000000)) -+#define SET_RCAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffe)) -+#define SET_LCK_BIN_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffd)) -+#define SET_VT_MON_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffb)) -+#define SET_DA_R_CODE_LUT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffff83f)) -+#define SET_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffffe7ff)) -+#define SET_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff9fff)) -+#define SET_RTC_CAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 15) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff7fff)) -+#define SET_RG_SARADC_BIT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 16) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffc0ffff)) -+#define SET_SAR_ADC_FSM_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 22) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffbfffff)) -+#define SET_AD_CIRCUIT_VERSION(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 23) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xf87fffff)) -+#define SET_DA_R_CAL_CODE(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xffffffe0)) -+#define SET_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xfffff01f)) -+#define SET_RG_DPL_RFCTRL_CH(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xfffff800)) -+#define SET_RG_RSSIADC_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 11) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xffff87ff)) -+#define SET_RG_RX_ADC_I_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xff807fff)) -+#define SET_RG_RX_ADC_Q_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x807fffff)) -+#define SET_RG_DPL_RFCTRL_F(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0xff000000)) -+#define SET_RG_SX_TARGET_CNT(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0xffffe000)) -+#define SET_RG_RTC_OFFSET(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 0) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xffffff00)) -+#define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 8) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xfff000ff)) -+#define SET_RG_RF_D_REG(_VAL_) (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0xffff0000)) -+#define SET_DIRECT_MODE(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffe)) -+#define SET_TAG_INTERLEAVE_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffd)) -+#define SET_DIS_DEMAND(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffb)) -+#define SET_SAME_ID_ALLOC_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_MMU_CTRL)) & 0xfffffff7)) -+#define SET_HS_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_MMU_CTRL)) & 0xffffffef)) -+#define SET_SRAM_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 5) | ((REG32(ADR_MMU_CTRL)) & 0xffffffdf)) -+#define SET_NOHIT_RPASS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 6) | ((REG32(ADR_MMU_CTRL)) & 0xffffffbf)) -+#define SET_DMN_FLAG_CLR(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_MMU_CTRL)) & 0xffffff7f)) -+#define SET_ERR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_CTRL)) & 0xfffffeff)) -+#define SET_ALR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_MMU_CTRL)) & 0xfffffdff)) -+#define SET_MCH_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_MMU_CTRL)) & 0xfffffbff)) -+#define SET_TAG_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_MMU_CTRL)) & 0xfffff7ff)) -+#define SET_ABT_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_CTRL)) & 0xffffefff)) -+#define SET_MMU_VER(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_MMU_CTRL)) & 0xffff1fff)) -+#define SET_MMU_SHARE_MCU(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_CTRL)) & 0xff00ffff)) -+#define SET_HS_WR(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_HS_CTRL)) & 0xfffffffe)) -+#define SET_HS_FLAG(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_HS_CTRL)) & 0xffffffef)) -+#define SET_HS_ID(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_HS_CTRL)) & 0xffff80ff)) -+#define SET_HS_CHANNEL(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_HS_CTRL)) & 0xfff0ffff)) -+#define SET_HS_PAGE(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 20) | ((REG32(ADR_HS_CTRL)) & 0xff0fffff)) -+#define SET_HS_DATA(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 24) | ((REG32(ADR_HS_CTRL)) & 0x00ffffff)) -+#define SET_CPU_POR0(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR0_7)) & 0xfffffff0)) -+#define SET_CPU_POR1(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR0_7)) & 0xffffff0f)) -+#define SET_CPU_POR2(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR0_7)) & 0xfffff0ff)) -+#define SET_CPU_POR3(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR0_7)) & 0xffff0fff)) -+#define SET_CPU_POR4(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR0_7)) & 0xfff0ffff)) -+#define SET_CPU_POR5(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR0_7)) & 0xff0fffff)) -+#define SET_CPU_POR6(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR0_7)) & 0xf0ffffff)) -+#define SET_CPU_POR7(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR0_7)) & 0x0fffffff)) -+#define SET_CPU_POR8(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR8_F)) & 0xfffffff0)) -+#define SET_CPU_POR9(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR8_F)) & 0xffffff0f)) -+#define SET_CPU_PORA(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR8_F)) & 0xfffff0ff)) -+#define SET_CPU_PORB(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR8_F)) & 0xffff0fff)) -+#define SET_CPU_PORC(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR8_F)) & 0xfff0ffff)) -+#define SET_CPU_PORD(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR8_F)) & 0xff0fffff)) -+#define SET_CPU_PORE(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR8_F)) & 0xf0ffffff)) -+#define SET_CPU_PORF(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR8_F)) & 0x0fffffff)) -+#define SET_ACC_WR_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffffc0)) -+#define SET_ACC_RD_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffc0ff)) -+#define SET_REQ_NACK_CLR(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 15) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffff7fff)) -+#define SET_NACK_FLAG_BUS(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_REG_LEN_CTRL)) & 0x0000ffff)) -+#define SET_DMN_R_PASS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xffff0000)) -+#define SET_PARA_ALC_RLS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfffeffff)) -+#define SET_REQ_PORNS_CHGEN(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 24) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfeffffff)) -+#define SET_ALC_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffffff80)) -+#define SET_ALC_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffff7fff)) -+#define SET_RLS_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xff80ffff)) -+#define SET_RLS_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_RLS_ABORT)) & 0x7fffffff)) -+#define SET_DEBUG_CTL(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_CTL)) & 0xffffff00)) -+#define SET_DEBUG_H16(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_DEBUG_CTL)) & 0xfffffeff)) -+#define SET_DEBUG_OUT(_VAL_) (REG32(ADR_DEBUG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_OUT)) & 0x00000000)) -+#define SET_ALC_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffe)) -+#define SET_RLS_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffd)) -+#define SET_AL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_STATUS)) & 0xfffff8ff)) -+#define SET_RL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_STATUS)) & 0xffff8fff)) -+#define SET_ALC_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_STATUS)) & 0xff80ffff)) -+#define SET_RLS_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MMU_STATUS)) & 0x80ffffff)) -+#define SET_DMN_NOHIT_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffe)) -+#define SET_DMN_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffd)) -+#define SET_DMN_WR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_STATUS)) & 0xfffffff7)) -+#define SET_DMN_PORT(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_STATUS)) & 0xffffff0f)) -+#define SET_DMN_NHIT_ID(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_STATUS)) & 0xffff80ff)) -+#define SET_DMN_NHIT_ADDR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_STATUS)) & 0x0000ffff)) -+#define SET_TX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_STATUS)) & 0xffffff00)) -+#define SET_RX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TAG_STATUS)) & 0xffff00ff)) -+#define SET_AVA_TAG(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_STATUS)) & 0xfe00ffff)) -+#define SET_PKTBUF_FULL(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 31) | ((REG32(ADR_TAG_STATUS)) & 0x7fffffff)) -+#define SET_DMN_NOHIT_MCU(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffe)) -+#define SET_DMN_MCU_FLAG(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffd)) -+#define SET_DMN_MCU_WR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffff7)) -+#define SET_DMN_MCU_PORT(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffffff0f)) -+#define SET_DMN_MCU_ID(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffff80ff)) -+#define SET_DMN_MCU_ADDR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_MCU_STATUS)) & 0x0000ffff)) -+#define SET_MB_IDTBL_31_0(_VAL_) (REG32(ADR_MB_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_0_STATUS)) & 0x00000000)) -+#define SET_MB_IDTBL_63_32(_VAL_) (REG32(ADR_MB_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_1_STATUS)) & 0x00000000)) -+#define SET_MB_IDTBL_95_64(_VAL_) (REG32(ADR_MB_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_2_STATUS)) & 0x00000000)) -+#define SET_MB_IDTBL_127_96(_VAL_) (REG32(ADR_MB_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_3_STATUS)) & 0x00000000)) -+#define SET_PKT_IDTBL_31_0(_VAL_) (REG32(ADR_PKT_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0x00000000)) -+#define SET_PKT_IDTBL_63_32(_VAL_) (REG32(ADR_PKT_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0x00000000)) -+#define SET_PKT_IDTBL_95_64(_VAL_) (REG32(ADR_PKT_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0x00000000)) -+#define SET_PKT_IDTBL_127_96(_VAL_) (REG32(ADR_PKT_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0x00000000)) -+#define SET_DMN_IDTBL_31_0(_VAL_) (REG32(ADR_DMN_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0x00000000)) -+#define SET_DMN_IDTBL_63_32(_VAL_) (REG32(ADR_DMN_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0x00000000)) -+#define SET_DMN_IDTBL_95_64(_VAL_) (REG32(ADR_DMN_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0x00000000)) -+#define SET_DMN_IDTBL_127_96(_VAL_) (REG32(ADR_DMN_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0x00000000)) -+#define SET_NEQ_MB_ID_31_0(_VAL_) (REG32(ADR_MB_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_0_STATUS)) & 0x00000000)) -+#define SET_NEQ_MB_ID_63_32(_VAL_) (REG32(ADR_MB_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_1_STATUS)) & 0x00000000)) -+#define SET_NEQ_MB_ID_95_64(_VAL_) (REG32(ADR_MB_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_2_STATUS)) & 0x00000000)) -+#define SET_NEQ_MB_ID_127_96(_VAL_) (REG32(ADR_MB_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_3_STATUS)) & 0x00000000)) -+#define SET_NEQ_PKT_ID_31_0(_VAL_) (REG32(ADR_PKT_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_0_STATUS)) & 0x00000000)) -+#define SET_NEQ_PKT_ID_63_32(_VAL_) (REG32(ADR_PKT_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_1_STATUS)) & 0x00000000)) -+#define SET_NEQ_PKT_ID_95_64(_VAL_) (REG32(ADR_PKT_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_2_STATUS)) & 0x00000000)) -+#define SET_NEQ_PKT_ID_127_96(_VAL_) (REG32(ADR_PKT_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_3_STATUS)) & 0x00000000)) -+#define SET_ALC_NOCHG_ID(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffffff80)) -+#define SET_ALC_NOCHG_INT(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffff7fff)) -+#define SET_NEQ_PKT_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfffeffff)) -+#define SET_NEQ_MB_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfeffffff)) -+#define SET_SRAM_TAG_0(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000)) -+#define SET_SRAM_TAG_1(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff)) -+#define SET_SRAM_TAG_2(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000)) -+#define SET_SRAM_TAG_3(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff)) -+#define SET_SRAM_TAG_4(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000)) -+#define SET_SRAM_TAG_5(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff)) -+#define SET_SRAM_TAG_6(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000)) -+#define SET_SRAM_TAG_7(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff)) -+#define SET_SRAM_TAG_8(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000)) -+#define SET_SRAM_TAG_9(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff)) -+#define SET_SRAM_TAG_10(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000)) -+#define SET_SRAM_TAG_11(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff)) -+#define SET_SRAM_TAG_12(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000)) -+#define SET_SRAM_TAG_13(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff)) -+#define SET_SRAM_TAG_14(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000)) -+#define SET_SRAM_TAG_15(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff)) -+#define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000) -+#define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000) -+#define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x31333131) -+#define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x322d3230) -+#define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x32303041) -+#define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636) -+#define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000000) -+#define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x008fffff) -+#define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000400) -+#define DEF_MCU_DBG_SEL() (REG32(ADR_MCU_DBG_SEL)) = (0x00000000) -+#define DEF_MCU_DBG_DATA() (REG32(ADR_MCU_DBG_DATA)) = (0x00000000) -+#define DEF_AHB_BRG_STATUS() (REG32(ADR_AHB_BRG_STATUS)) = (0x00000000) -+#define DEF_BIST_BIST_CTRL() (REG32(ADR_BIST_BIST_CTRL)) = (0x00000000) -+#define DEF_BIST_MODE_REG_IN() (REG32(ADR_BIST_MODE_REG_IN)) = (0x001ffe3e) -+#define DEF_BIST_MODE_REG_OUT() (REG32(ADR_BIST_MODE_REG_OUT)) = (0x00000000) -+#define DEF_BIST_MONITOR_BUS_LSB() (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (0x00000000) -+#define DEF_BIST_MONITOR_BUS_MSB() (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (0x00000000) -+#define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000) -+#define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000) -+#define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000) -+#define DEF_AHB_ILL_ADDR() (REG32(ADR_AHB_ILL_ADDR)) = (0x00000000) -+#define DEF_AHB_FEN_ADDR() (REG32(ADR_AHB_FEN_ADDR)) = (0x00000000) -+#define DEF_AHB_ILLFEN_STATUS() (REG32(ADR_AHB_ILLFEN_STATUS)) = (0x00000000) -+#define DEF_PWM_A() (REG32(ADR_PWM_A)) = (0x400a1010) -+#define DEF_PWM_B() (REG32(ADR_PWM_B)) = (0x400a1010) -+#define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd) -+#define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000) -+#define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028) -+#define DEF_BIST_MODE_REG_IN_MMU() (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (0x0000fe3e) -+#define DEF_BIST_MODE_REG_OUT_MMU() (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (0x00000000) -+#define DEF_BIST_MONITOR_BUS_MMU() (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (0x00000000) -+#define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000) -+#define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000) -+#define DEF_SD_INIT_CFG() (REG32(ADR_SD_INIT_CFG)) = (0x00000000) -+#define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000) -+#define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000) -+#define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000) -+#define DEF_TU0_DUMMY_BIT_0() (REG32(ADR_TU0_DUMMY_BIT_0)) = (0x00000000) -+#define DEF_TU0_DUMMY_BIT_1() (REG32(ADR_TU0_DUMMY_BIT_1)) = (0x00000000) -+#define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000) -+#define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000) -+#define DEF_TU1_DUMMY_BIT_0() (REG32(ADR_TU1_DUMMY_BIT_0)) = (0x00000000) -+#define DEF_TU1_DUMMY_BIT_1() (REG32(ADR_TU1_DUMMY_BIT_1)) = (0x00000000) -+#define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000) -+#define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000) -+#define DEF_TU2_DUMMY_BIT_0() (REG32(ADR_TU2_DUMMY_BIT_0)) = (0x00000000) -+#define DEF_TU2_DUMMY_BIT_1() (REG32(ADR_TU2_DUMMY_BIT_1)) = (0x00000000) -+#define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000) -+#define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000) -+#define DEF_TU3_DUMMY_BIT_0() (REG32(ADR_TU3_DUMMY_BIT_0)) = (0x00000000) -+#define DEF_TU3_DUMMY_BIT_1() (REG32(ADR_TU3_DUMMY_BIT_1)) = (0x00000000) -+#define DEF_TM0_MILISECOND_TIMER() (REG32(ADR_TM0_MILISECOND_TIMER)) = (0x00000000) -+#define DEF_TM0_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000) -+#define DEF_TM0_DUMMY_BIT_0() (REG32(ADR_TM0_DUMMY_BIT_0)) = (0x00000000) -+#define DEF_TM0_DUMMY_BIT_1() (REG32(ADR_TM0_DUMMY_BIT_1)) = (0x00000000) -+#define DEF_TM1_MILISECOND_TIMER() (REG32(ADR_TM1_MILISECOND_TIMER)) = (0x00000000) -+#define DEF_TM1_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000) -+#define DEF_TM1_DUMMY_BIT_0() (REG32(ADR_TM1_DUMMY_BIT_0)) = (0x00000000) -+#define DEF_TM1_DUMMY_BIT_1() (REG32(ADR_TM1_DUMMY_BIT_1)) = (0x00000000) -+#define DEF_TM2_MILISECOND_TIMER() (REG32(ADR_TM2_MILISECOND_TIMER)) = (0x00000000) -+#define DEF_TM2_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000) -+#define DEF_TM2_DUMMY_BIT_0() (REG32(ADR_TM2_DUMMY_BIT_0)) = (0x00000000) -+#define DEF_TM2_DUMMY_BIT_1() (REG32(ADR_TM2_DUMMY_BIT_1)) = (0x00000000) -+#define DEF_TM3_MILISECOND_TIMER() (REG32(ADR_TM3_MILISECOND_TIMER)) = (0x00000000) -+#define DEF_TM3_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000) -+#define DEF_TM3_DUMMY_BIT_0() (REG32(ADR_TM3_DUMMY_BIT_0)) = (0x00000000) -+#define DEF_TM3_DUMMY_BIT_1() (REG32(ADR_TM3_DUMMY_BIT_1)) = (0x00000000) -+#define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00000000) -+#define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00000000) -+#define DEF_PAD6() (REG32(ADR_PAD6)) = (0x00000008) -+#define DEF_PAD7() (REG32(ADR_PAD7)) = (0x00000008) -+#define DEF_PAD8() (REG32(ADR_PAD8)) = (0x00000008) -+#define DEF_PAD9() (REG32(ADR_PAD9)) = (0x00000008) -+#define DEF_PAD11() (REG32(ADR_PAD11)) = (0x00000008) -+#define DEF_PAD15() (REG32(ADR_PAD15)) = (0x0000000a) -+#define DEF_PAD16() (REG32(ADR_PAD16)) = (0x0000000a) -+#define DEF_PAD17() (REG32(ADR_PAD17)) = (0x0000000a) -+#define DEF_PAD18() (REG32(ADR_PAD18)) = (0x0000000a) -+#define DEF_PAD19() (REG32(ADR_PAD19)) = (0x00007000) -+#define DEF_PAD20() (REG32(ADR_PAD20)) = (0x0000000a) -+#define DEF_PAD21() (REG32(ADR_PAD21)) = (0x0000000a) -+#define DEF_PAD22() (REG32(ADR_PAD22)) = (0x00000009) -+#define DEF_PAD24() (REG32(ADR_PAD24)) = (0x00000008) -+#define DEF_PAD25() (REG32(ADR_PAD25)) = (0x0000000b) -+#define DEF_PAD27() (REG32(ADR_PAD27)) = (0x00000008) -+#define DEF_PAD28() (REG32(ADR_PAD28)) = (0x00000008) -+#define DEF_PAD29() (REG32(ADR_PAD29)) = (0x00000009) -+#define DEF_PAD30() (REG32(ADR_PAD30)) = (0x0000000a) -+#define DEF_PAD31() (REG32(ADR_PAD31)) = (0x0000000a) -+#define DEF_PAD32() (REG32(ADR_PAD32)) = (0x0000000a) -+#define DEF_PAD33() (REG32(ADR_PAD33)) = (0x0000000a) -+#define DEF_PAD34() (REG32(ADR_PAD34)) = (0x0000000a) -+#define DEF_PAD42() (REG32(ADR_PAD42)) = (0x0000000a) -+#define DEF_PAD43() (REG32(ADR_PAD43)) = (0x0000000a) -+#define DEF_PAD44() (REG32(ADR_PAD44)) = (0x0000000a) -+#define DEF_PAD45() (REG32(ADR_PAD45)) = (0x0000000a) -+#define DEF_PAD46() (REG32(ADR_PAD46)) = (0x0000000a) -+#define DEF_PAD47() (REG32(ADR_PAD47)) = (0x00100000) -+#define DEF_PAD48() (REG32(ADR_PAD48)) = (0x00100808) -+#define DEF_PAD49() (REG32(ADR_PAD49)) = (0x00100008) -+#define DEF_PAD50() (REG32(ADR_PAD50)) = (0x00100008) -+#define DEF_PAD51() (REG32(ADR_PAD51)) = (0x00100008) -+#define DEF_PAD52() (REG32(ADR_PAD52)) = (0x00100000) -+#define DEF_PAD53() (REG32(ADR_PAD53)) = (0x0000000a) -+#define DEF_PAD54() (REG32(ADR_PAD54)) = (0x00000000) -+#define DEF_PAD56() (REG32(ADR_PAD56)) = (0x00000000) -+#define DEF_PAD57() (REG32(ADR_PAD57)) = (0x00000008) -+#define DEF_PAD58() (REG32(ADR_PAD58)) = (0x0000000a) -+#define DEF_PAD59() (REG32(ADR_PAD59)) = (0x0000000a) -+#define DEF_PAD60() (REG32(ADR_PAD60)) = (0x0000000a) -+#define DEF_PAD61() (REG32(ADR_PAD61)) = (0x0000000a) -+#define DEF_PAD62() (REG32(ADR_PAD62)) = (0x0000000a) -+#define DEF_PAD64() (REG32(ADR_PAD64)) = (0x00000009) -+#define DEF_PAD65() (REG32(ADR_PAD65)) = (0x00000009) -+#define DEF_PAD66() (REG32(ADR_PAD66)) = (0x00000008) -+#define DEF_PAD68() (REG32(ADR_PAD68)) = (0x00000008) -+#define DEF_PAD67() (REG32(ADR_PAD67)) = (0x00000159) -+#define DEF_PAD69() (REG32(ADR_PAD69)) = (0x0000000b) -+#define DEF_PAD70() (REG32(ADR_PAD70)) = (0x00000008) -+#define DEF_PAD231() (REG32(ADR_PAD231)) = (0x00000008) -+#define DEF_PIN_SEL_0() (REG32(ADR_PIN_SEL_0)) = (0x00000000) -+#define DEF_PIN_SEL_1() (REG32(ADR_PIN_SEL_1)) = (0x00000000) -+#define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000) -+#define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff) -+#define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000) -+#define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000) -+#define DEF_CARD_PKT_STATUS_TEST() (REG32(ADR_CARD_PKT_STATUS_TEST)) = (0x00000000) -+#define DEF_SYSTEM_INFORMATION_REG() (REG32(ADR_SYSTEM_INFORMATION_REG)) = (0x00000000) -+#define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000) -+#define DEF_SDIO_FIFO_WR_THLD_REG() (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (0x00000000) -+#define DEF_SDIO_FIFO_WR_LIMIT_REG() (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (0x00000000) -+#define DEF_SDIO_TX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (0x00000000) -+#define DEF_SDIO_THLD_FOR_CMD53RD_REG() (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (0x00000000) -+#define DEF_SDIO_RX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (0x00000000) -+#define DEF_SDIO_LOG_START_END_DATA_REG() (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (0x00000000) -+#define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000) -+#define DEF_SDIO_LAST_CMD_INDEX_CRC_REG() (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (0x00000000) -+#define DEF_SDIO_LAST_CMD_ARG_REG() (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (0x00000000) -+#define DEF_SDIO_BUS_STATE_DEBUG_MONITOR() (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (0x00000000) -+#define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000) -+#define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00000000) -+#define DEF_CMD52_DATA_FOR_LAST_TIME() (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (0x00000000) -+#define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000) -+#define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000) -+#define DEF_IO_REG_PORT_REG() (REG32(ADR_IO_REG_PORT_REG)) = (0x00010020) -+#define DEF_SDIO_FIFO_ERROR_CNT() (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (0x00000000) -+#define DEF_SDIO_CRC7_CRC16_ERROR_REG() (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (0x00000000) -+#define DEF_SDIO_BLOCK_CNT_INFO() (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (0x00000000) -+#define DEF_RX_DATA_CMD52_ABORT_COUNT() (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (0x00000000) -+#define DEF_FIFO_PTR_READ_BLOCK_CNT() (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (0x00000000) -+#define DEF_TX_TIME_OUT_READ_CTRL() (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (0x00000000) -+#define DEF_SDIO_TX_ALLOC_REG() (REG32(ADR_SDIO_TX_ALLOC_REG)) = (0x00000000) -+#define DEF_SDIO_TX_INFORM() (REG32(ADR_SDIO_TX_INFORM)) = (0x00000000) -+#define DEF_F1_BLOCK_SIZE_0_REG() (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (0x00000000) -+#define DEF_SDIO_COMMAND_LOG_DATA_31_0() (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (0x000000ec) -+#define DEF_SDIO_COMMAND_LOG_DATA_63_32() (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (0xce000000) -+#define DEF_SYSTEM_INFORMATION_REGISTER() (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (0x00000000) -+#define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000) -+#define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000) -+#define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000) -+#define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x00000000) -+#define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000) -+#define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000) -+#define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000) -+#define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000) -+#define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000) -+#define DEF_RX_QUOTA() (REG32(ADR_RX_QUOTA)) = (0x00000000) -+#define DEF_CONDITION_NUMBER() (REG32(ADR_CONDITION_NUMBER)) = (0x00000004) -+#define DEF_HOST_PATH() (REG32(ADR_HOST_PATH)) = (0x00000001) -+#define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000) -+#define DEF_DEBUG_BURST_MODE() (REG32(ADR_DEBUG_BURST_MODE)) = (0x00000000) -+#define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006) -+#define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e) -+#define DEF_SPI_STS() (REG32(ADR_SPI_STS)) = (0x00000000) -+#define DEF_TX_ALLOC_SET() (REG32(ADR_TX_ALLOC_SET)) = (0x00000000) -+#define DEF_TX_ALLOC() (REG32(ADR_TX_ALLOC)) = (0x00000000) -+#define DEF_DBG_CNT() (REG32(ADR_DBG_CNT)) = (0x00000000) -+#define DEF_DBG_CNT2() (REG32(ADR_DBG_CNT2)) = (0x00000000) -+#define DEF_DBG_CNT3() (REG32(ADR_DBG_CNT3)) = (0x00000000) -+#define DEF_DBG_CNT4() (REG32(ADR_DBG_CNT4)) = (0x00000000) -+#define DEF_INT_TAG() (REG32(ADR_INT_TAG)) = (0x00000000) -+#define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x00000074) -+#define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000) -+#define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000) -+#define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000) -+#define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000) -+#define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000) -+#define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000) -+#define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000) -+#define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001) -+#define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003) -+#define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000) -+#define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000) -+#define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000) -+#define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x00000000) -+#define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8) -+#define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1) -+#define DEF_DAT_UART_DATA() (REG32(ADR_DAT_UART_DATA)) = (0x00000000) -+#define DEF_DAT_UART_IER() (REG32(ADR_DAT_UART_IER)) = (0x00000000) -+#define DEF_DAT_UART_FCR() (REG32(ADR_DAT_UART_FCR)) = (0x00000001) -+#define DEF_DAT_UART_LCR() (REG32(ADR_DAT_UART_LCR)) = (0x00000003) -+#define DEF_DAT_UART_MCR() (REG32(ADR_DAT_UART_MCR)) = (0x00000000) -+#define DEF_DAT_UART_LSR() (REG32(ADR_DAT_UART_LSR)) = (0x00000000) -+#define DEF_DAT_UART_MSR() (REG32(ADR_DAT_UART_MSR)) = (0x00000000) -+#define DEF_DAT_UART_SPR() (REG32(ADR_DAT_UART_SPR)) = (0x00000000) -+#define DEF_DAT_UART_RTHR() (REG32(ADR_DAT_UART_RTHR)) = (0x000000c8) -+#define DEF_DAT_UART_ISR() (REG32(ADR_DAT_UART_ISR)) = (0x000000c1) -+#define DEF_INT_MASK() (REG32(ADR_INT_MASK)) = (0xffffffff) -+#define DEF_INT_MODE() (REG32(ADR_INT_MODE)) = (0x00000000) -+#define DEF_INT_IRQ_STS() (REG32(ADR_INT_IRQ_STS)) = (0x00000000) -+#define DEF_INT_FIQ_STS() (REG32(ADR_INT_FIQ_STS)) = (0x00000000) -+#define DEF_INT_IRQ_RAW() (REG32(ADR_INT_IRQ_RAW)) = (0x00000000) -+#define DEF_INT_FIQ_RAW() (REG32(ADR_INT_FIQ_RAW)) = (0x00000000) -+#define DEF_INT_PERI_MASK() (REG32(ADR_INT_PERI_MASK)) = (0xffffffff) -+#define DEF_INT_PERI_STS() (REG32(ADR_INT_PERI_STS)) = (0x00000000) -+#define DEF_INT_PERI_RAW() (REG32(ADR_INT_PERI_RAW)) = (0x00000000) -+#define DEF_INT_GPI_CFG() (REG32(ADR_INT_GPI_CFG)) = (0x00000000) -+#define DEF_SYS_INT_FOR_HOST() (REG32(ADR_SYS_INT_FOR_HOST)) = (0x00000001) -+#define DEF_SPI_IPC() (REG32(ADR_SPI_IPC)) = (0x00000000) -+#define DEF_SDIO_IPC() (REG32(ADR_SDIO_IPC)) = (0x00000000) -+#define DEF_SDIO_MASK() (REG32(ADR_SDIO_MASK)) = (0xffffffff) -+#define DEF_SDIO_IRQ_STS() (REG32(ADR_SDIO_IRQ_STS)) = (0x00000000) -+#define DEF_SD_PERI_MASK() (REG32(ADR_SD_PERI_MASK)) = (0xffffffff) -+#define DEF_SD_PERI_STS() (REG32(ADR_SD_PERI_STS)) = (0x00000000) -+#define DEF_DBG_SPI_MODE() (REG32(ADR_DBG_SPI_MODE)) = (0x00000000) -+#define DEF_DBG_RX_QUOTA() (REG32(ADR_DBG_RX_QUOTA)) = (0x00000000) -+#define DEF_DBG_CONDITION_NUMBER() (REG32(ADR_DBG_CONDITION_NUMBER)) = (0x00000004) -+#define DEF_DBG_HOST_PATH() (REG32(ADR_DBG_HOST_PATH)) = (0x00000001) -+#define DEF_DBG_TX_SEG() (REG32(ADR_DBG_TX_SEG)) = (0x00000000) -+#define DEF_DBG_DEBUG_BURST_MODE() (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (0x00000000) -+#define DEF_DBG_SPI_TO_PHY_PARAM1() (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (0x000e0006) -+#define DEF_DBG_SPI_TO_PHY_PARAM2() (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (0x000e000e) -+#define DEF_DBG_SPI_STS() (REG32(ADR_DBG_SPI_STS)) = (0x00000000) -+#define DEF_DBG_TX_ALLOC_SET() (REG32(ADR_DBG_TX_ALLOC_SET)) = (0x00000000) -+#define DEF_DBG_TX_ALLOC() (REG32(ADR_DBG_TX_ALLOC)) = (0x00000000) -+#define DEF_DBG_DBG_CNT() (REG32(ADR_DBG_DBG_CNT)) = (0x00000000) -+#define DEF_DBG_DBG_CNT2() (REG32(ADR_DBG_DBG_CNT2)) = (0x00000000) -+#define DEF_DBG_DBG_CNT3() (REG32(ADR_DBG_DBG_CNT3)) = (0x00000000) -+#define DEF_DBG_DBG_CNT4() (REG32(ADR_DBG_DBG_CNT4)) = (0x00000000) -+#define DEF_DBG_INT_TAG() (REG32(ADR_DBG_INT_TAG)) = (0x00000000) -+#define DEF_BOOT_ADDR() (REG32(ADR_BOOT_ADDR)) = (0x00000000) -+#define DEF_VERIFY_DATA() (REG32(ADR_VERIFY_DATA)) = (0x5e11aa11) -+#define DEF_FLASH_ADDR() (REG32(ADR_FLASH_ADDR)) = (0x00000000) -+#define DEF_SRAM_ADDR() (REG32(ADR_SRAM_ADDR)) = (0x00000000) -+#define DEF_LEN() (REG32(ADR_LEN)) = (0x00000000) -+#define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x000f000f) -+#define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00040001) -+#define DEF_CHECK_SUM_RESULT() (REG32(ADR_CHECK_SUM_RESULT)) = (0x00000000) -+#define DEF_CHECK_SUM_IN_FILE() (REG32(ADR_CHECK_SUM_IN_FILE)) = (0x00000000) -+#define DEF_COMMAND_LEN() (REG32(ADR_COMMAND_LEN)) = (0x00000000) -+#define DEF_COMMAND_ADDR() (REG32(ADR_COMMAND_ADDR)) = (0x00000000) -+#define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000) -+#define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000) -+#define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa) -+#define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001) -+#define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000) -+#define DEF_PMU_0() (REG32(ADR_PMU_0)) = (0x0f000040) -+#define DEF_PMU_1() (REG32(ADR_PMU_1)) = (0x015d015d) -+#define DEF_PMU_2() (REG32(ADR_PMU_2)) = (0x00000000) -+#define DEF_PMU_3() (REG32(ADR_PMU_3)) = (0x55550000) -+#define DEF_RTC_1() (REG32(ADR_RTC_1)) = (0x7fff0000) -+#define DEF_RTC_2() (REG32(ADR_RTC_2)) = (0x00000003) -+#define DEF_RTC_3W() (REG32(ADR_RTC_3W)) = (0x00000000) -+#define DEF_RTC_3R() (REG32(ADR_RTC_3R)) = (0x00000000) -+#define DEF_RTC_4() (REG32(ADR_RTC_4)) = (0x00000000) -+#define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000) -+#define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000) -+#define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa) -+#define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001) -+#define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000) -+#define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x02700008) -+#define DEF_SDIO_WAKE_MODE() (REG32(ADR_SDIO_WAKE_MODE)) = (0x00000000) -+#define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000) -+#define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000) -+#define DEF_THREASHOLD() (REG32(ADR_THREASHOLD)) = (0x09000000) -+#define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000) -+#define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000) -+#define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450) -+#define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008) -+#define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000) -+#define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000) -+#define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000) -+#define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000) -+#define DEF_PACKET_COUNTER_INFO_0() (REG32(ADR_PACKET_COUNTER_INFO_0)) = (0x00000000) -+#define DEF_PACKET_COUNTER_INFO_1() (REG32(ADR_PACKET_COUNTER_INFO_1)) = (0x00000000) -+#define DEF_PACKET_COUNTER_INFO_2() (REG32(ADR_PACKET_COUNTER_INFO_2)) = (0x00000000) -+#define DEF_PACKET_COUNTER_INFO_3() (REG32(ADR_PACKET_COUNTER_INFO_3)) = (0x00000000) -+#define DEF_PACKET_COUNTER_INFO_4() (REG32(ADR_PACKET_COUNTER_INFO_4)) = (0x00000000) -+#define DEF_PACKET_COUNTER_INFO_5() (REG32(ADR_PACKET_COUNTER_INFO_5)) = (0x00000000) -+#define DEF_PACKET_COUNTER_INFO_6() (REG32(ADR_PACKET_COUNTER_INFO_6)) = (0x00000000) -+#define DEF_PACKET_COUNTER_INFO_7() (REG32(ADR_PACKET_COUNTER_INFO_7)) = (0x00000000) -+#define DEF_SDIO_TX_RX_FAIL_COUNTER_0() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (0x00000000) -+#define DEF_SDIO_TX_RX_FAIL_COUNTER_1() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_1() (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_8() (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_9() (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (0x00000000) -+#define DEF_HCI_STATE_DEBUG_MODE_10() (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (0x00000000) -+#define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000) -+#define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000) -+#define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000) -+#define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000) -+#define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000) -+#define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000) -+#define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000) -+#define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000) -+#define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000) -+#define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000) -+#define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000) -+#define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000) -+#define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000) -+#define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000) -+#define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000) -+#define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000) -+#define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000) -+#define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000) -+#define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000) -+#define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000) -+#define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002) -+#define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0) -+#define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002) -+#define DEF_EFUSE_AHB_RDATA_0() (REG32(ADR_EFUSE_AHB_RDATA_0)) = (0x00000000) -+#define DEF_EFUSE_WDATA_0() (REG32(ADR_EFUSE_WDATA_0)) = (0x00000000) -+#define DEF_EFUSE_AHB_RDATA_1() (REG32(ADR_EFUSE_AHB_RDATA_1)) = (0x00000000) -+#define DEF_EFUSE_WDATA_1() (REG32(ADR_EFUSE_WDATA_1)) = (0x00000000) -+#define DEF_EFUSE_AHB_RDATA_2() (REG32(ADR_EFUSE_AHB_RDATA_2)) = (0x00000000) -+#define DEF_EFUSE_WDATA_2() (REG32(ADR_EFUSE_WDATA_2)) = (0x00000000) -+#define DEF_EFUSE_AHB_RDATA_3() (REG32(ADR_EFUSE_AHB_RDATA_3)) = (0x00000000) -+#define DEF_EFUSE_WDATA_3() (REG32(ADR_EFUSE_WDATA_3)) = (0x00000000) -+#define DEF_EFUSE_AHB_RDATA_4() (REG32(ADR_EFUSE_AHB_RDATA_4)) = (0x00000000) -+#define DEF_EFUSE_WDATA_4() (REG32(ADR_EFUSE_WDATA_4)) = (0x00000000) -+#define DEF_EFUSE_AHB_RDATA_5() (REG32(ADR_EFUSE_AHB_RDATA_5)) = (0x00000000) -+#define DEF_EFUSE_WDATA_5() (REG32(ADR_EFUSE_WDATA_5)) = (0x00000000) -+#define DEF_EFUSE_AHB_RDATA_6() (REG32(ADR_EFUSE_AHB_RDATA_6)) = (0x00000000) -+#define DEF_EFUSE_WDATA_6() (REG32(ADR_EFUSE_WDATA_6)) = (0x00000000) -+#define DEF_EFUSE_AHB_RDATA_7() (REG32(ADR_EFUSE_AHB_RDATA_7)) = (0x00000000) -+#define DEF_EFUSE_WDATA_7() (REG32(ADR_EFUSE_WDATA_7)) = (0x00000000) -+#define DEF_EFUSE_SPI_RD0_EN() (REG32(ADR_EFUSE_SPI_RD0_EN)) = (0x00000000) -+#define DEF_EFUSE_SPI_RD1_EN() (REG32(ADR_EFUSE_SPI_RD1_EN)) = (0x00000000) -+#define DEF_EFUSE_SPI_RD2_EN() (REG32(ADR_EFUSE_SPI_RD2_EN)) = (0x00000000) -+#define DEF_EFUSE_SPI_RD3_EN() (REG32(ADR_EFUSE_SPI_RD3_EN)) = (0x00000000) -+#define DEF_EFUSE_SPI_RD4_EN() (REG32(ADR_EFUSE_SPI_RD4_EN)) = (0x00000000) -+#define DEF_EFUSE_SPI_RD5_EN() (REG32(ADR_EFUSE_SPI_RD5_EN)) = (0x00000000) -+#define DEF_EFUSE_SPI_RD6_EN() (REG32(ADR_EFUSE_SPI_RD6_EN)) = (0x00000000) -+#define DEF_EFUSE_SPI_RD7_EN() (REG32(ADR_EFUSE_SPI_RD7_EN)) = (0x00000000) -+#define DEF_EFUSE_SPI_BUSY() (REG32(ADR_EFUSE_SPI_BUSY)) = (0x00000000) -+#define DEF_EFUSE_SPI_RDATA_0() (REG32(ADR_EFUSE_SPI_RDATA_0)) = (0x00000000) -+#define DEF_EFUSE_SPI_RDATA_1() (REG32(ADR_EFUSE_SPI_RDATA_1)) = (0x00000000) -+#define DEF_EFUSE_SPI_RDATA_2() (REG32(ADR_EFUSE_SPI_RDATA_2)) = (0x00000000) -+#define DEF_EFUSE_SPI_RDATA_3() (REG32(ADR_EFUSE_SPI_RDATA_3)) = (0x00000000) -+#define DEF_EFUSE_SPI_RDATA_4() (REG32(ADR_EFUSE_SPI_RDATA_4)) = (0x00000000) -+#define DEF_EFUSE_SPI_RDATA_5() (REG32(ADR_EFUSE_SPI_RDATA_5)) = (0x00000000) -+#define DEF_EFUSE_SPI_RDATA_6() (REG32(ADR_EFUSE_SPI_RDATA_6)) = (0x00000000) -+#define DEF_EFUSE_SPI_RDATA_7() (REG32(ADR_EFUSE_SPI_RDATA_7)) = (0x00000000) -+#define DEF_SMS4_CFG1() (REG32(ADR_SMS4_CFG1)) = (0x00000002) -+#define DEF_SMS4_CFG2() (REG32(ADR_SMS4_CFG2)) = (0x00000000) -+#define DEF_SMS4_MODE1() (REG32(ADR_SMS4_MODE1)) = (0x00000000) -+#define DEF_SMS4_TRIG() (REG32(ADR_SMS4_TRIG)) = (0x00000000) -+#define DEF_SMS4_STATUS1() (REG32(ADR_SMS4_STATUS1)) = (0x00000000) -+#define DEF_SMS4_STATUS2() (REG32(ADR_SMS4_STATUS2)) = (0x00000000) -+#define DEF_SMS4_DATA_IN0() (REG32(ADR_SMS4_DATA_IN0)) = (0x00000000) -+#define DEF_SMS4_DATA_IN1() (REG32(ADR_SMS4_DATA_IN1)) = (0x00000000) -+#define DEF_SMS4_DATA_IN2() (REG32(ADR_SMS4_DATA_IN2)) = (0x00000000) -+#define DEF_SMS4_DATA_IN3() (REG32(ADR_SMS4_DATA_IN3)) = (0x00000000) -+#define DEF_SMS4_DATA_OUT0() (REG32(ADR_SMS4_DATA_OUT0)) = (0x00000000) -+#define DEF_SMS4_DATA_OUT1() (REG32(ADR_SMS4_DATA_OUT1)) = (0x00000000) -+#define DEF_SMS4_DATA_OUT2() (REG32(ADR_SMS4_DATA_OUT2)) = (0x00000000) -+#define DEF_SMS4_DATA_OUT3() (REG32(ADR_SMS4_DATA_OUT3)) = (0x00000000) -+#define DEF_SMS4_KEY_0() (REG32(ADR_SMS4_KEY_0)) = (0x00000000) -+#define DEF_SMS4_KEY_1() (REG32(ADR_SMS4_KEY_1)) = (0x00000000) -+#define DEF_SMS4_KEY_2() (REG32(ADR_SMS4_KEY_2)) = (0x00000000) -+#define DEF_SMS4_KEY_3() (REG32(ADR_SMS4_KEY_3)) = (0x00000000) -+#define DEF_SMS4_MODE_IV0() (REG32(ADR_SMS4_MODE_IV0)) = (0x00000000) -+#define DEF_SMS4_MODE_IV1() (REG32(ADR_SMS4_MODE_IV1)) = (0x00000000) -+#define DEF_SMS4_MODE_IV2() (REG32(ADR_SMS4_MODE_IV2)) = (0x00000000) -+#define DEF_SMS4_MODE_IV3() (REG32(ADR_SMS4_MODE_IV3)) = (0x00000000) -+#define DEF_SMS4_OFB_ENC0() (REG32(ADR_SMS4_OFB_ENC0)) = (0x00000000) -+#define DEF_SMS4_OFB_ENC1() (REG32(ADR_SMS4_OFB_ENC1)) = (0x00000000) -+#define DEF_SMS4_OFB_ENC2() (REG32(ADR_SMS4_OFB_ENC2)) = (0x00000000) -+#define DEF_SMS4_OFB_ENC3() (REG32(ADR_SMS4_OFB_ENC3)) = (0x00000000) -+#define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000) -+#define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000) -+#define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000) -+#define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000) -+#define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000) -+#define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000) -+#define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000) -+#define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000) -+#define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000) -+#define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000) -+#define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000) -+#define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000) -+#define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000) -+#define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000) -+#define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000) -+#define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000) -+#define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000) -+#define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000) -+#define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000) -+#define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000) -+#define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000) -+#define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000) -+#define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5) -+#define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6) -+#define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9) -+#define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1) -+#define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9) -+#define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1) -+#define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe) -+#define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe) -+#define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000) -+#define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000) -+#define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000) -+#define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006) -+#define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001) -+#define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003) -+#define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005) -+#define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007) -+#define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008) -+#define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001) -+#define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808) -+#define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000) -+#define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008) -+#define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e) -+#define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838) -+#define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008) -+#define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008) -+#define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000) -+#define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034) -+#define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004) -+#define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004) -+#define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00) -+#define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000) -+#define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000) -+#define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000) -+#define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008) -+#define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000) -+#define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000) -+#define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000) -+#define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000) -+#define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000) -+#define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000) -+#define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff) -+#define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000) -+#define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000) -+#define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000) -+#define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000) -+#define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000) -+#define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000) -+#define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000) -+#define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000) -+#define DEF_WSID0_TID0_RX_SEQ() (REG32(ADR_WSID0_TID0_RX_SEQ)) = (0x00000000) -+#define DEF_WSID0_TID1_RX_SEQ() (REG32(ADR_WSID0_TID1_RX_SEQ)) = (0x00000000) -+#define DEF_WSID0_TID2_RX_SEQ() (REG32(ADR_WSID0_TID2_RX_SEQ)) = (0x00000000) -+#define DEF_WSID0_TID3_RX_SEQ() (REG32(ADR_WSID0_TID3_RX_SEQ)) = (0x00000000) -+#define DEF_WSID0_TID4_RX_SEQ() (REG32(ADR_WSID0_TID4_RX_SEQ)) = (0x00000000) -+#define DEF_WSID0_TID5_RX_SEQ() (REG32(ADR_WSID0_TID5_RX_SEQ)) = (0x00000000) -+#define DEF_WSID0_TID6_RX_SEQ() (REG32(ADR_WSID0_TID6_RX_SEQ)) = (0x00000000) -+#define DEF_WSID0_TID7_RX_SEQ() (REG32(ADR_WSID0_TID7_RX_SEQ)) = (0x00000000) -+#define DEF_WSID1_TID0_RX_SEQ() (REG32(ADR_WSID1_TID0_RX_SEQ)) = (0x00000000) -+#define DEF_WSID1_TID1_RX_SEQ() (REG32(ADR_WSID1_TID1_RX_SEQ)) = (0x00000000) -+#define DEF_WSID1_TID2_RX_SEQ() (REG32(ADR_WSID1_TID2_RX_SEQ)) = (0x00000000) -+#define DEF_WSID1_TID3_RX_SEQ() (REG32(ADR_WSID1_TID3_RX_SEQ)) = (0x00000000) -+#define DEF_WSID1_TID4_RX_SEQ() (REG32(ADR_WSID1_TID4_RX_SEQ)) = (0x00000000) -+#define DEF_WSID1_TID5_RX_SEQ() (REG32(ADR_WSID1_TID5_RX_SEQ)) = (0x00000000) -+#define DEF_WSID1_TID6_RX_SEQ() (REG32(ADR_WSID1_TID6_RX_SEQ)) = (0x00000000) -+#define DEF_WSID1_TID7_RX_SEQ() (REG32(ADR_WSID1_TID7_RX_SEQ)) = (0x00000000) -+#define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79) -+#define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000) -+#define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000) -+#define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e) -+#define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000) -+#define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000) -+#define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000) -+#define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000) -+#define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000) -+#define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00c00c00) -+#define DEF_MTX_EDCCA_TOUT() (REG32(ADR_MTX_EDCCA_TOUT)) = (0x00000200) -+#define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000) -+#define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000) -+#define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x00000042) -+#define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000) -+#define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064) -+#define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000) -+#define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000) -+#define DEF_MTX_BCN_CFG0() (REG32(ADR_MTX_BCN_CFG0)) = (0x00000000) -+#define DEF_MTX_BCN_CFG1() (REG32(ADR_MTX_BCN_CFG1)) = (0x00000000) -+#define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000) -+#define DEF_MTX_DBG_CTRL() (REG32(ADR_MTX_DBG_CTRL)) = (0x00000000) -+#define DEF_MTX_DBG_DAT0() (REG32(ADR_MTX_DBG_DAT0)) = (0x00000000) -+#define DEF_MTX_DBG_DAT1() (REG32(ADR_MTX_DBG_DAT1)) = (0x00000000) -+#define DEF_MTX_DBG_DAT2() (REG32(ADR_MTX_DBG_DAT2)) = (0x00000000) -+#define DEF_MTX_DUR_TOUT() (REG32(ADR_MTX_DUR_TOUT)) = (0x00002c2c) -+#define DEF_MTX_DUR_IFS() (REG32(ADR_MTX_DUR_IFS)) = (0x12d40a05) -+#define DEF_MTX_DUR_SIFS_G() (REG32(ADR_MTX_DUR_SIFS_G)) = (0x12c90100) -+#define DEF_MTX_DBG_DAT3() (REG32(ADR_MTX_DBG_DAT3)) = (0x00000000) -+#define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000) -+#define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000) -+#define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000) -+#define DEF_MTX_DBG_DAT4() (REG32(ADR_MTX_DBG_DAT4)) = (0x00000000) -+#define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000) -+#define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x0000a502) -+#define DEF_TXQ0_MTX_Q_BKF_CNT() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (0x00000000) -+#define DEF_TXQ0_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (0x00000407) -+#define DEF_TXQ0_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (0x00000000) -+#define DEF_TXQ0_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (0x00000000) -+#define DEF_TXQ0_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (0x00000000) -+#define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000) -+#define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x0000a502) -+#define DEF_TXQ1_MTX_Q_BKF_CNT() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (0x00000000) -+#define DEF_TXQ1_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (0x00000407) -+#define DEF_TXQ1_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (0x00000000) -+#define DEF_TXQ1_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (0x00000000) -+#define DEF_TXQ1_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (0x00000000) -+#define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000) -+#define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x0000a502) -+#define DEF_TXQ2_MTX_Q_BKF_CNT() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (0x00000000) -+#define DEF_TXQ2_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (0x00000407) -+#define DEF_TXQ2_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (0x00000000) -+#define DEF_TXQ2_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (0x00000000) -+#define DEF_TXQ2_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (0x00000000) -+#define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000) -+#define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x0000a502) -+#define DEF_TXQ3_MTX_Q_BKF_CNT() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (0x00000000) -+#define DEF_TXQ3_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (0x00000407) -+#define DEF_TXQ3_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (0x00000000) -+#define DEF_TXQ3_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (0x00000000) -+#define DEF_TXQ3_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (0x00000000) -+#define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000) -+#define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x0000a502) -+#define DEF_TXQ4_MTX_Q_BKF_CNT() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (0x00000000) -+#define DEF_TXQ4_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (0x00000407) -+#define DEF_TXQ4_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (0x00000000) -+#define DEF_TXQ4_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (0x00000000) -+#define DEF_TXQ4_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (0x00000000) -+#define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000) -+#define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000) -+#define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000) -+#define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000) -+#define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000) -+#define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000) -+#define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000) -+#define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000) -+#define DEF_INFO0() (REG32(ADR_INFO0)) = (0x00000000) -+#define DEF_INFO1() (REG32(ADR_INFO1)) = (0x00000100) -+#define DEF_INFO2() (REG32(ADR_INFO2)) = (0x00000200) -+#define DEF_INFO3() (REG32(ADR_INFO3)) = (0x00000300) -+#define DEF_INFO4() (REG32(ADR_INFO4)) = (0x00000140) -+#define DEF_INFO5() (REG32(ADR_INFO5)) = (0x00000240) -+#define DEF_INFO6() (REG32(ADR_INFO6)) = (0x00000340) -+#define DEF_INFO7() (REG32(ADR_INFO7)) = (0x00000001) -+#define DEF_INFO8() (REG32(ADR_INFO8)) = (0x00000101) -+#define DEF_INFO9() (REG32(ADR_INFO9)) = (0x00000201) -+#define DEF_INFO10() (REG32(ADR_INFO10)) = (0x00000301) -+#define DEF_INFO11() (REG32(ADR_INFO11)) = (0x00000401) -+#define DEF_INFO12() (REG32(ADR_INFO12)) = (0x00000501) -+#define DEF_INFO13() (REG32(ADR_INFO13)) = (0x00000601) -+#define DEF_INFO14() (REG32(ADR_INFO14)) = (0x00000701) -+#define DEF_INFO15() (REG32(ADR_INFO15)) = (0x00030002) -+#define DEF_INFO16() (REG32(ADR_INFO16)) = (0x00030102) -+#define DEF_INFO17() (REG32(ADR_INFO17)) = (0x00030202) -+#define DEF_INFO18() (REG32(ADR_INFO18)) = (0x00030302) -+#define DEF_INFO19() (REG32(ADR_INFO19)) = (0x00030402) -+#define DEF_INFO20() (REG32(ADR_INFO20)) = (0x00030502) -+#define DEF_INFO21() (REG32(ADR_INFO21)) = (0x00030602) -+#define DEF_INFO22() (REG32(ADR_INFO22)) = (0x00030702) -+#define DEF_INFO23() (REG32(ADR_INFO23)) = (0x00030082) -+#define DEF_INFO24() (REG32(ADR_INFO24)) = (0x00030182) -+#define DEF_INFO25() (REG32(ADR_INFO25)) = (0x00030282) -+#define DEF_INFO26() (REG32(ADR_INFO26)) = (0x00030382) -+#define DEF_INFO27() (REG32(ADR_INFO27)) = (0x00030482) -+#define DEF_INFO28() (REG32(ADR_INFO28)) = (0x00030582) -+#define DEF_INFO29() (REG32(ADR_INFO29)) = (0x00030682) -+#define DEF_INFO30() (REG32(ADR_INFO30)) = (0x00030782) -+#define DEF_INFO31() (REG32(ADR_INFO31)) = (0x00030042) -+#define DEF_INFO32() (REG32(ADR_INFO32)) = (0x00030142) -+#define DEF_INFO33() (REG32(ADR_INFO33)) = (0x00030242) -+#define DEF_INFO34() (REG32(ADR_INFO34)) = (0x00030342) -+#define DEF_INFO35() (REG32(ADR_INFO35)) = (0x00030442) -+#define DEF_INFO36() (REG32(ADR_INFO36)) = (0x00030542) -+#define DEF_INFO37() (REG32(ADR_INFO37)) = (0x00030642) -+#define DEF_INFO38() (REG32(ADR_INFO38)) = (0x00030742) -+#define DEF_INFO_MASK() (REG32(ADR_INFO_MASK)) = (0x00007fc7) -+#define DEF_INFO_RATE_OFFSET() (REG32(ADR_INFO_RATE_OFFSET)) = (0x00040000) -+#define DEF_INFO_IDX_ADDR() (REG32(ADR_INFO_IDX_ADDR)) = (0x00000000) -+#define DEF_INFO_LEN_ADDR() (REG32(ADR_INFO_LEN_ADDR)) = (0x00000000) -+#define DEF_IC_TIME_TAG_0() (REG32(ADR_IC_TIME_TAG_0)) = (0x00000000) -+#define DEF_IC_TIME_TAG_1() (REG32(ADR_IC_TIME_TAG_1)) = (0x00000000) -+#define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000) -+#define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000) -+#define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000) -+#define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000) -+#define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000) -+#define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb) -+#define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b) -+#define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02) -+#define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000) -+#define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000) -+#define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000) -+#define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000) -+#define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000) -+#define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000) -+#define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000) -+#define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000) -+#define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000) -+#define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006) -+#define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000) -+#define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000) -+#define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000) -+#define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000) -+#define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000) -+#define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000) -+#define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000) -+#define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000) -+#define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000) -+#define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000) -+#define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000) -+#define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000) -+#define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000) -+#define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000) -+#define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000) -+#define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000) -+#define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000) -+#define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000) -+#define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000) -+#define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000) -+#define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000) -+#define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000) -+#define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000) -+#define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000) -+#define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000) -+#define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000) -+#define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000) -+#define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000) -+#define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000) -+#define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000) -+#define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000) -+#define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000) -+#define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000) -+#define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000) -+#define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000) -+#define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000) -+#define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000) -+#define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000) -+#define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000) -+#define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000) -+#define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000) -+#define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000) -+#define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000) -+#define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000) -+#define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000) -+#define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000) -+#define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000) -+#define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000) -+#define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000) -+#define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000) -+#define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000) -+#define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000) -+#define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000) -+#define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000) -+#define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000) -+#define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000) -+#define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000) -+#define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000) -+#define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000) -+#define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000) -+#define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000) -+#define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000) -+#define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000) -+#define DEF_CBR_HARD_WIRE_PIN_REGISTER() (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (0x00004000) -+#define DEF_CBR_MANUAL_ENABLE_REGISTER() (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (0x00001fc0) -+#define DEF_CBR_LDO_REGISTER() (REG32(ADR_CBR_LDO_REGISTER)) = (0x2496db1b) -+#define DEF_CBR_ABB_REGISTER_1() (REG32(ADR_CBR_ABB_REGISTER_1)) = (0x151558dd) -+#define DEF_CBR_ABB_REGISTER_2() (REG32(ADR_CBR_ABB_REGISTER_2)) = (0x01011a88) -+#define DEF_CBR_TX_FE_REGISTER() (REG32(ADR_CBR_TX_FE_REGISTER)) = (0x3cbe84fe) -+#define DEF_CBR_RX_FE_REGISTER_1() (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (0x00657579) -+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7) -+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6) -+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001) -+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000) -+#define DEF_CBR_RX_FSM_REGISTER() (REG32(ADR_CBR_RX_FSM_REGISTER)) = (0x00000ca8) -+#define DEF_CBR_RX_ADC_REGISTER() (REG32(ADR_CBR_RX_ADC_REGISTER)) = (0x002a0224) -+#define DEF_CBR_TX_DAC_REGISTER() (REG32(ADR_CBR_TX_DAC_REGISTER)) = (0x00002655) -+#define DEF_CBR_SX_ENABLE_RGISTER() (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (0x0000647c) -+#define DEF_CBR_SYN_RGISTER_1() (REG32(ADR_CBR_SYN_RGISTER_1)) = (0xaa800000) -+#define DEF_CBR_SYN_RGISTER_2() (REG32(ADR_CBR_SYN_RGISTER_2)) = (0x00550800) -+#define DEF_CBR_SYN_PFD_CHP() (REG32(ADR_CBR_SYN_PFD_CHP)) = (0x07c0894a) -+#define DEF_CBR_SYN_VCO_LOBF() (REG32(ADR_CBR_SYN_VCO_LOBF)) = (0xfcccca27) -+#define DEF_CBR_SYN_DIV_SDM_XOSC() (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (0x2773c93c) -+#define DEF_CBR_SYN_LCK1() (REG32(ADR_CBR_SYN_LCK1)) = (0x00000a7c) -+#define DEF_CBR_SYN_LCK2() (REG32(ADR_CBR_SYN_LCK2)) = (0x01c67ff4) -+#define DEF_CBR_DPLL_VCO_REGISTER() (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (0x00103014) -+#define DEF_CBR_DPLL_CP_PFD_REGISTER() (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (0x0001848c) -+#define DEF_CBR_DPLL_DIVIDER_REGISTER() (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (0x034061e0) -+#define DEF_CBR_DCOC_IDAC_REGISTER1() (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (0x00820820) -+#define DEF_CBR_DCOC_IDAC_REGISTER2() (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (0x00820820) -+#define DEF_CBR_DCOC_IDAC_REGISTER3() (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (0x00820820) -+#define DEF_CBR_DCOC_IDAC_REGISTER4() (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (0x00820820) -+#define DEF_CBR_DCOC_IDAC_REGISTER5() (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (0x00820820) -+#define DEF_CBR_DCOC_IDAC_REGISTER6() (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (0x00820820) -+#define DEF_CBR_DCOC_IDAC_REGISTER7() (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (0x00820820) -+#define DEF_CBR_DCOC_IDAC_REGISTER8() (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (0x00820820) -+#define DEF_CBR_RCAL_REGISTER() (REG32(ADR_CBR_RCAL_REGISTER)) = (0x00004080) -+#define DEF_CBR_MANUAL_REGISTER() (REG32(ADR_CBR_MANUAL_REGISTER)) = (0x00003e7e) -+#define DEF_CBR_TRX_DUMMY_REGISTER() (REG32(ADR_CBR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa) -+#define DEF_CBR_SX_DUMMY_REGISTER() (REG32(ADR_CBR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa) -+#define DEF_CBR_RG_PKT_GEN_0() (REG32(ADR_CBR_RG_PKT_GEN_0)) = (0x00000000) -+#define DEF_CBR_RG_PKT_GEN_1() (REG32(ADR_CBR_RG_PKT_GEN_1)) = (0x00000000) -+#define DEF_CBR_RG_PKT_GEN_2() (REG32(ADR_CBR_RG_PKT_GEN_2)) = (0x00000000) -+#define DEF_CBR_RG_INTEGRATION() (REG32(ADR_CBR_RG_INTEGRATION)) = (0x00000000) -+#define DEF_CBR_RG_PKT_GEN_TXCNT() (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (0x00000000) -+#define DEF_CBR_PATTERN_GEN() (REG32(ADR_CBR_PATTERN_GEN)) = (0xff000000) -+#define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000) -+#define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000) -+#define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000) -+#define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000) -+#define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000) -+#define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000) -+#define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000) -+#define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000) -+#define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000) -+#define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000) -+#define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000) -+#define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000) -+#define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000) -+#define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000) -+#define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff) -+#define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002) -+#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000) -+#define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000) -+#define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000) -+#define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000) -+#define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000) -+#define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000) -+#define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000) -+#define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000) -+#define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000) -+#define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000) -+#define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001) -+#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000) -+#define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000) -+#define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000) -+#define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000) -+#define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000) -+#define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000) -+#define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000) -+#define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000) -+#define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000) -+#define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213) -+#define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000) -+#define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000) -+#define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000) -+#define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000) -+#define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000) -+#define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000) -+#define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c) -+#define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000) -+#define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000) -+#define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000) -+#define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000) -+#define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001) -+#define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641) -+#define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000) -+#define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201) -+#define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000) -+#define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100) -+#define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000) -+#define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000) -+#define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000) -+#define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000) -+#define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000) -+#define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000) -+#define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000) -+#define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000) -+#define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000) -+#define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000) -+#define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000) -+#define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100) -+#define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000) -+#define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000) -+#define DEF_PHY_EN_0() (REG32(ADR_PHY_EN_0)) = (0x00000014) -+#define DEF_PHY_EN_1() (REG32(ADR_PHY_EN_1)) = (0x00000000) -+#define DEF_SVN_VERSION_REG() (REG32(ADR_SVN_VERSION_REG)) = (0x00000000) -+#define DEF_PHY_PKT_GEN_0() (REG32(ADR_PHY_PKT_GEN_0)) = (0x00000064) -+#define DEF_PHY_PKT_GEN_1() (REG32(ADR_PHY_PKT_GEN_1)) = (0x00000fff) -+#define DEF_PHY_PKT_GEN_2() (REG32(ADR_PHY_PKT_GEN_2)) = (0x00000003) -+#define DEF_PHY_PKT_GEN_3() (REG32(ADR_PHY_PKT_GEN_3)) = (0x005a0220) -+#define DEF_PHY_PKT_GEN_4() (REG32(ADR_PHY_PKT_GEN_4)) = (0x00000001) -+#define DEF_PHY_REG_00() (REG32(ADR_PHY_REG_00)) = (0x10000000) -+#define DEF_PHY_REG_01() (REG32(ADR_PHY_REG_01)) = (0x00000000) -+#define DEF_PHY_REG_02_AGC() (REG32(ADR_PHY_REG_02_AGC)) = (0x80046771) -+#define DEF_PHY_REG_03_AGC() (REG32(ADR_PHY_REG_03_AGC)) = (0x1f300f6f) -+#define DEF_PHY_REG_04_AGC() (REG32(ADR_PHY_REG_04_AGC)) = (0x663f36d0) -+#define DEF_PHY_REG_05_AGC() (REG32(ADR_PHY_REG_05_AGC)) = (0x106c0000) -+#define DEF_PHY_REG_06_11B_DAGC() (REG32(ADR_PHY_REG_06_11B_DAGC)) = (0x01603fff) -+#define DEF_PHY_REG_07_11B_DAGC() (REG32(ADR_PHY_REG_07_11B_DAGC)) = (0x00600808) -+#define DEF_PHY_REG_08_11GN_DAGC() (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (0xff000160) -+#define DEF_PHY_REG_09_11GN_DAGC() (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (0x00080840) -+#define DEF_PHY_READ_REG_00_DIG_PWR() (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (0x00000000) -+#define DEF_PHY_READ_REG_01_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (0x00000000) -+#define DEF_PHY_READ_REG_02_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (0x00000000) -+#define DEF_PHY_READ_REG_03_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (0x00000000) -+#define DEF_PHY_REG_10_TX_DES() (REG32(ADR_PHY_REG_10_TX_DES)) = (0x00010405) -+#define DEF_PHY_REG_11_TX_DES() (REG32(ADR_PHY_REG_11_TX_DES)) = (0x06090813) -+#define DEF_PHY_REG_12_TX_DES() (REG32(ADR_PHY_REG_12_TX_DES)) = (0x12070000) -+#define DEF_PHY_REG_13_RX_DES() (REG32(ADR_PHY_REG_13_RX_DES)) = (0x01000405) -+#define DEF_PHY_REG_14_RX_DES() (REG32(ADR_PHY_REG_14_RX_DES)) = (0x06090813) -+#define DEF_PHY_REG_15_RX_DES() (REG32(ADR_PHY_REG_15_RX_DES)) = (0x12010000) -+#define DEF_PHY_REG_16_TX_DES_EXCP() (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (0x00000000) -+#define DEF_PHY_REG_17_TX_DES_EXCP() (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (0x10110000) -+#define DEF_PHY_REG_18_RSSI_SNR() (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (0x00fc000f) -+#define DEF_PHY_REG_19_DAC_MANUAL() (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (0x00000000) -+#define DEF_PHY_REG_20_MRX_CNT() (REG32(ADR_PHY_REG_20_MRX_CNT)) = (0x00000000) -+#define DEF_PHY_REG_21_TRX_RAMP() (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (0x3c012801) -+#define DEF_PHY_REG_22_TRX_RAMP() (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (0x24243724) -+#define DEF_PHY_REG_23_ANT() (REG32(ADR_PHY_REG_23_ANT)) = (0x00000011) -+#define DEF_PHY_REG_24_MTX_LEN_CNT() (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (0x1fff0000) -+#define DEF_PHY_REG_25_MTX_LEN_CNT() (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (0x1fff0000) -+#define DEF_PHY_REG_26_MRX_LEN_CNT() (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (0x1fff0000) -+#define DEF_PHY_REG_27_MRX_LEN_CNT() (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (0x1fff0000) -+#define DEF_PHY_READ_REG_04() (REG32(ADR_PHY_READ_REG_04)) = (0x00000000) -+#define DEF_PHY_READ_REG_05() (REG32(ADR_PHY_READ_REG_05)) = (0x00000000) -+#define DEF_PHY_REG_28_BIST() (REG32(ADR_PHY_REG_28_BIST)) = (0x0000fe3e) -+#define DEF_PHY_READ_REG_06_BIST() (REG32(ADR_PHY_READ_REG_06_BIST)) = (0x00000000) -+#define DEF_PHY_READ_REG_07_BIST() (REG32(ADR_PHY_READ_REG_07_BIST)) = (0x00000000) -+#define DEF_PHY_REG_29_MTRX_MAC() (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (0xffffffff) -+#define DEF_PHY_READ_REG_08_MTRX_MAC() (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (0x00000000) -+#define DEF_PHY_READ_REG_09_MTRX_MAC() (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (0x00000000) -+#define DEF_PHY_REG_30_TX_UP_FIL() (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (0x0ead04f5) -+#define DEF_PHY_REG_31_TX_UP_FIL() (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (0x0fd60080) -+#define DEF_PHY_REG_32_TX_UP_FIL() (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (0x00000009) -+#define DEF_PHY_READ_TBUS() (REG32(ADR_PHY_READ_TBUS)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_00() (REG32(ADR_TX_11B_FIL_COEF_00)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_01() (REG32(ADR_TX_11B_FIL_COEF_01)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_02() (REG32(ADR_TX_11B_FIL_COEF_02)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_03() (REG32(ADR_TX_11B_FIL_COEF_03)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_04() (REG32(ADR_TX_11B_FIL_COEF_04)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_05() (REG32(ADR_TX_11B_FIL_COEF_05)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_06() (REG32(ADR_TX_11B_FIL_COEF_06)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_07() (REG32(ADR_TX_11B_FIL_COEF_07)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_08() (REG32(ADR_TX_11B_FIL_COEF_08)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_09() (REG32(ADR_TX_11B_FIL_COEF_09)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_10() (REG32(ADR_TX_11B_FIL_COEF_10)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_11() (REG32(ADR_TX_11B_FIL_COEF_11)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_12() (REG32(ADR_TX_11B_FIL_COEF_12)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_13() (REG32(ADR_TX_11B_FIL_COEF_13)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_14() (REG32(ADR_TX_11B_FIL_COEF_14)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_15() (REG32(ADR_TX_11B_FIL_COEF_15)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_16() (REG32(ADR_TX_11B_FIL_COEF_16)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_17() (REG32(ADR_TX_11B_FIL_COEF_17)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_18() (REG32(ADR_TX_11B_FIL_COEF_18)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_19() (REG32(ADR_TX_11B_FIL_COEF_19)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_20() (REG32(ADR_TX_11B_FIL_COEF_20)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_21() (REG32(ADR_TX_11B_FIL_COEF_21)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_22() (REG32(ADR_TX_11B_FIL_COEF_22)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_23() (REG32(ADR_TX_11B_FIL_COEF_23)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_24() (REG32(ADR_TX_11B_FIL_COEF_24)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_25() (REG32(ADR_TX_11B_FIL_COEF_25)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_26() (REG32(ADR_TX_11B_FIL_COEF_26)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_27() (REG32(ADR_TX_11B_FIL_COEF_27)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_28() (REG32(ADR_TX_11B_FIL_COEF_28)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_29() (REG32(ADR_TX_11B_FIL_COEF_29)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_30() (REG32(ADR_TX_11B_FIL_COEF_30)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_31() (REG32(ADR_TX_11B_FIL_COEF_31)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_32() (REG32(ADR_TX_11B_FIL_COEF_32)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_33() (REG32(ADR_TX_11B_FIL_COEF_33)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_34() (REG32(ADR_TX_11B_FIL_COEF_34)) = (0x00000000) -+#define DEF_TX_11B_FIL_COEF_35() (REG32(ADR_TX_11B_FIL_COEF_35)) = (0x00000005) -+#define DEF_TX_11B_FIL_COEF_36() (REG32(ADR_TX_11B_FIL_COEF_36)) = (0x0000003d) -+#define DEF_TX_11B_FIL_COEF_37() (REG32(ADR_TX_11B_FIL_COEF_37)) = (0x00000162) -+#define DEF_TX_11B_FIL_COEF_38() (REG32(ADR_TX_11B_FIL_COEF_38)) = (0x00000400) -+#define DEF_TX_11B_FIL_COEF_39() (REG32(ADR_TX_11B_FIL_COEF_39)) = (0x00000699) -+#define DEF_TX_11B_FIL_COEF_40() (REG32(ADR_TX_11B_FIL_COEF_40)) = (0x00000787) -+#define DEF_TX_11B_PLCP() (REG32(ADR_TX_11B_PLCP)) = (0x00000000) -+#define DEF_TX_11B_RAMP() (REG32(ADR_TX_11B_RAMP)) = (0x0000403c) -+#define DEF_TX_11B_EN_CNT_RST_N() (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (0x00000001) -+#define DEF_TX_11B_EN_CNT() (REG32(ADR_TX_11B_EN_CNT)) = (0x00000000) -+#define DEF_TX_11B_PKT_GEN_CNT() (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (0x00000000) -+#define DEF_RX_11B_DES_DLY() (REG32(ADR_RX_11B_DES_DLY)) = (0x00000044) -+#define DEF_RX_11B_CCA_0() (REG32(ADR_RX_11B_CCA_0)) = (0x00040000) -+#define DEF_RX_11B_CCA_1() (REG32(ADR_RX_11B_CCA_1)) = (0x00400040) -+#define DEF_RX_11B_TR_KP_KI_0() (REG32(ADR_RX_11B_TR_KP_KI_0)) = (0x00003467) -+#define DEF_RX_11B_TR_KP_KI_1() (REG32(ADR_RX_11B_TR_KP_KI_1)) = (0x00540000) -+#define DEF_RX_11B_CE_CNT_THRESHOLD() (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (0x12243615) -+#define DEF_RX_11B_CE_MU_0() (REG32(ADR_RX_11B_CE_MU_0)) = (0x00390002) -+#define DEF_RX_11B_CE_MU_1() (REG32(ADR_RX_11B_CE_MU_1)) = (0x03456777) -+#define DEF_RX_11B_EQ_MU_0() (REG32(ADR_RX_11B_EQ_MU_0)) = (0x00350046) -+#define DEF_RX_11B_EQ_MU_1() (REG32(ADR_RX_11B_EQ_MU_1)) = (0x00570057) -+#define DEF_RX_11B_EQ_CR_KP_KI() (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (0x00236700) -+#define DEF_RX_11B_LPF_RATE() (REG32(ADR_RX_11B_LPF_RATE)) = (0x000d1746) -+#define DEF_RX_11B_CIT_CNT_THRESHOLD() (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (0x04061787) -+#define DEF_RX_11B_EQ_CH_MAIN_TAP() (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (0x07800000) -+#define DEF_RX_11B_SEARCH_CNT_TH() (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (0x00c0000a) -+#define DEF_RX_11B_CCA_CONTROL() (REG32(ADR_RX_11B_CCA_CONTROL)) = (0x00000000) -+#define DEF_RX_11B_FREQUENCY_OFFSET() (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (0x00000000) -+#define DEF_RX_11B_SNR_RSSI() (REG32(ADR_RX_11B_SNR_RSSI)) = (0x00000000) -+#define DEF_RX_11B_SFD_CRC_CNT() (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (0x00000000) -+#define DEF_RX_11B_PKT_ERR_AND_PKT_ERR_CNT() (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (0x00000000) -+#define DEF_RX_11B_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (0x00000000) -+#define DEF_RX_11B_SFD_FILED_0() (REG32(ADR_RX_11B_SFD_FILED_0)) = (0x00000000) -+#define DEF_RX_11B_SFD_FIELD_1() (REG32(ADR_RX_11B_SFD_FIELD_1)) = (0x00000000) -+#define DEF_RX_11B_PKT_STAT_EN() (REG32(ADR_RX_11B_PKT_STAT_EN)) = (0x00100000) -+#define DEF_RX_11B_SOFT_RST() (REG32(ADR_RX_11B_SOFT_RST)) = (0x00000001) -+#define DEF_TX_11GN_RAMP() (REG32(ADR_TX_11GN_RAMP)) = (0x0000233c) -+#define DEF_TX_11GN_PLCP() (REG32(ADR_TX_11GN_PLCP)) = (0x5d08908e) -+#define DEF_TX_11GN_PKT_GEN_CNT() (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (0x00000000) -+#define DEF_TX_11GN_PLCP_CRC_ERR_CNT() (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (0x00000000) -+#define DEF_RX_11GN_DES_DLY() (REG32(ADR_RX_11GN_DES_DLY)) = (0x00000044) -+#define DEF_RX_11GN_TR_0() (REG32(ADR_RX_11GN_TR_0)) = (0x00750075) -+#define DEF_RX_11GN_TR_1() (REG32(ADR_RX_11GN_TR_1)) = (0x00000075) -+#define DEF_RX_11GN_TR_2() (REG32(ADR_RX_11GN_TR_2)) = (0x10000075) -+#define DEF_RX_11GN_CCA_0() (REG32(ADR_RX_11GN_CCA_0)) = (0x38324705) -+#define DEF_RX_11GN_CCA_1() (REG32(ADR_RX_11GN_CCA_1)) = (0x30182000) -+#define DEF_RX_11GN_CCA_2() (REG32(ADR_RX_11GN_CCA_2)) = (0x20600000) -+#define DEF_RX_11GN_CCA_FFT_SCALE() (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (0x0a010100) -+#define DEF_RX_11GN_SOFT_DEMAP_0() (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (0x50505050) -+#define DEF_RX_11GN_SOFT_DEMAP_1() (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (0x50000000) -+#define DEF_RX_11GN_SOFT_DEMAP_2() (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (0x50505050) -+#define DEF_RX_11GN_SOFT_DEMAP_3() (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (0x50505050) -+#define DEF_RX_11GN_SOFT_DEMAP_4() (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (0x50000000) -+#define DEF_RX_11GN_SOFT_DEMAP_5() (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (0x00000000) -+#define DEF_RX_11GN_SYM_BOUND_0() (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (0x00001420) -+#define DEF_RX_11GN_SYM_BOUND_1() (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (0x0000200a) -+#define DEF_RX_11GN_CCA_PWR() (REG32(ADR_RX_11GN_CCA_PWR)) = (0x30000280) -+#define DEF_RX_11GN_CCA_CNT() (REG32(ADR_RX_11GN_CCA_CNT)) = (0x30023002) -+#define DEF_RX_11GN_CCA_ATCOR_RE_CHECK() (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (0x0000003a) -+#define DEF_RX_11GN_VTB_TB() (REG32(ADR_RX_11GN_VTB_TB)) = (0x40000000) -+#define DEF_RX_11GN_ERR_UPDATE() (REG32(ADR_RX_11GN_ERR_UPDATE)) = (0x009e007e) -+#define DEF_RX_11GN_SHORT_GI() (REG32(ADR_RX_11GN_SHORT_GI)) = (0x00044400) -+#define DEF_RX_11GN_CHANNEL_UPDATE() (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (0x82000000) -+#define DEF_RX_11GN_PKT_FORMAT_0() (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (0x02003030) -+#define DEF_RX_11GN_PKT_FORMAT_1() (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (0x092a092a) -+#define DEF_RX_11GN_TX_TIME() (REG32(ADR_RX_11GN_TX_TIME)) = (0x00700010) -+#define DEF_RX_11GN_STBC_TR_KP_KI() (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (0x00007575) -+#define DEF_RX_11GN_BIST_0() (REG32(ADR_RX_11GN_BIST_0)) = (0x0001fe3e) -+#define DEF_RX_11GN_BIST_1() (REG32(ADR_RX_11GN_BIST_1)) = (0x0000fe3e) -+#define DEF_RX_11GN_BIST_2() (REG32(ADR_RX_11GN_BIST_2)) = (0x00000000) -+#define DEF_RX_11GN_BIST_3() (REG32(ADR_RX_11GN_BIST_3)) = (0x00000000) -+#define DEF_RX_11GN_BIST_4() (REG32(ADR_RX_11GN_BIST_4)) = (0x00000000) -+#define DEF_RX_11GN_BIST_5() (REG32(ADR_RX_11GN_BIST_5)) = (0x00000000) -+#define DEF_RX_11GN_SPECTRUM_ANALYZER() (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (0x00000000) -+#define DEF_RX_11GN_READ_0() (REG32(ADR_RX_11GN_READ_0)) = (0x00000000) -+#define DEF_RX_11GN_FREQ_OFFSET() (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (0x00000000) -+#define DEF_RX_11GN_SIGNAL_FIELD_0() (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (0x00000000) -+#define DEF_RX_11GN_SIGNAL_FIELD_1() (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (0x00000000) -+#define DEF_RX_11GN_PKT_ERR_CNT() (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (0x00000000) -+#define DEF_RX_11GN_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (0x00000000) -+#define DEF_RX_11GN_SERVICE_LENGTH_FIELD() (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (0x00000000) -+#define DEF_RX_11GN_RATE() (REG32(ADR_RX_11GN_RATE)) = (0x00000000) -+#define DEF_RX_11GN_STAT_EN() (REG32(ADR_RX_11GN_STAT_EN)) = (0x00100001) -+#define DEF_RX_11GN_SOFT_RST() (REG32(ADR_RX_11GN_SOFT_RST)) = (0x00000001) -+#define DEF_RF_CONTROL_0() (REG32(ADR_RF_CONTROL_0)) = (0x00000000) -+#define DEF_RF_CONTROL_1() (REG32(ADR_RF_CONTROL_1)) = (0x00008000) -+#define DEF_TX_IQ_CONTROL_0() (REG32(ADR_TX_IQ_CONTROL_0)) = (0x00200020) -+#define DEF_TX_IQ_CONTROL_1() (REG32(ADR_TX_IQ_CONTROL_1)) = (0x00028080) -+#define DEF_TX_IQ_CONTROL_2() (REG32(ADR_TX_IQ_CONTROL_2)) = (0x00000000) -+#define DEF_TX_COMPENSATION_CONTROL() (REG32(ADR_TX_COMPENSATION_CONTROL)) = (0x00000000) -+#define DEF_RX_COMPENSATION_CONTROL() (REG32(ADR_RX_COMPENSATION_CONTROL)) = (0x00000000) -+#define DEF_RX_OBSERVATION_CIRCUIT_0() (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (0x000028ff) -+#define DEF_RX_OBSERVATION_CIRCUIT_1() (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (0x00000000) -+#define DEF_RX_OBSERVATION_CIRCUIT_2() (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (0x00000000) -+#define DEF_RX_OBSERVATION_CIRCUIT_3() (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (0x00000000) -+#define DEF_RF_IQ_CONTROL_0() (REG32(ADR_RF_IQ_CONTROL_0)) = (0x00000202) -+#define DEF_RF_IQ_CONTROL_1() (REG32(ADR_RF_IQ_CONTROL_1)) = (0x00ffc200) -+#define DEF_RF_IQ_CONTROL_2() (REG32(ADR_RF_IQ_CONTROL_2)) = (0x00000000) -+#define DEF_RF_IQ_CONTROL_3() (REG32(ADR_RF_IQ_CONTROL_3)) = (0x00000000) -+#define DEF_DPD_CONTROL() (REG32(ADR_DPD_CONTROL)) = (0x00000000) -+#define DEF_DPD_GAIN_TABLE_0() (REG32(ADR_DPD_GAIN_TABLE_0)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_1() (REG32(ADR_DPD_GAIN_TABLE_1)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_2() (REG32(ADR_DPD_GAIN_TABLE_2)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_3() (REG32(ADR_DPD_GAIN_TABLE_3)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_4() (REG32(ADR_DPD_GAIN_TABLE_4)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_5() (REG32(ADR_DPD_GAIN_TABLE_5)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_6() (REG32(ADR_DPD_GAIN_TABLE_6)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_7() (REG32(ADR_DPD_GAIN_TABLE_7)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_8() (REG32(ADR_DPD_GAIN_TABLE_8)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_9() (REG32(ADR_DPD_GAIN_TABLE_9)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_A() (REG32(ADR_DPD_GAIN_TABLE_A)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_B() (REG32(ADR_DPD_GAIN_TABLE_B)) = (0x02000200) -+#define DEF_DPD_GAIN_TABLE_C() (REG32(ADR_DPD_GAIN_TABLE_C)) = (0x02000200) -+#define DEF_DPD_PH_TABLE_0() (REG32(ADR_DPD_PH_TABLE_0)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_1() (REG32(ADR_DPD_PH_TABLE_1)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_2() (REG32(ADR_DPD_PH_TABLE_2)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_3() (REG32(ADR_DPD_PH_TABLE_3)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_4() (REG32(ADR_DPD_PH_TABLE_4)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_5() (REG32(ADR_DPD_PH_TABLE_5)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_6() (REG32(ADR_DPD_PH_TABLE_6)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_7() (REG32(ADR_DPD_PH_TABLE_7)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_8() (REG32(ADR_DPD_PH_TABLE_8)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_9() (REG32(ADR_DPD_PH_TABLE_9)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_A() (REG32(ADR_DPD_PH_TABLE_A)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_B() (REG32(ADR_DPD_PH_TABLE_B)) = (0x00000000) -+#define DEF_DPD_PH_TABLE_C() (REG32(ADR_DPD_PH_TABLE_C)) = (0x00000000) -+#define DEF_DPD_GAIN_ESTIMATION_0() (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (0x00000000) -+#define DEF_DPD_GAIN_ESTIMATION_1() (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (0x00000100) -+#define DEF_DPD_GAIN_ESTIMATION_2() (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (0x00000000) -+#define DEF_TX_GAIN_FACTOR() (REG32(ADR_TX_GAIN_FACTOR)) = (0x80808080) -+#define DEF_HARD_WIRE_PIN_REGISTER() (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (0x00004000) -+#define DEF_MANUAL_ENABLE_REGISTER() (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (0x00000fc0) -+#define DEF_LDO_REGISTER() (REG32(ADR_LDO_REGISTER)) = (0x000db71b) -+#define DEF_ABB_REGISTER_1() (REG32(ADR_ABB_REGISTER_1)) = (0x151558dd) -+#define DEF_ABB_REGISTER_2() (REG32(ADR_ABB_REGISTER_2)) = (0x01011a88) -+#define DEF_TX_FE_REGISTER() (REG32(ADR_TX_FE_REGISTER)) = (0x3d3e84fe) -+#define DEF_RX_FE_REGISTER_1() (REG32(ADR_RX_FE_REGISTER_1)) = (0x03457579) -+#define DEF_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7) -+#define DEF_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6) -+#define DEF_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001) -+#define DEF_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000) -+#define DEF_RX_TX_FSM_REGISTER() (REG32(ADR_RX_TX_FSM_REGISTER)) = (0x00030ca8) -+#define DEF_RX_ADC_REGISTER() (REG32(ADR_RX_ADC_REGISTER)) = (0x20ea0224) -+#define DEF_TX_DAC_REGISTER() (REG32(ADR_TX_DAC_REGISTER)) = (0x44000655) -+#define DEF_SX_ENABLE_REGISTER() (REG32(ADR_SX_ENABLE_REGISTER)) = (0x0003e07c) -+#define DEF_SYN_REGISTER_1() (REG32(ADR_SYN_REGISTER_1)) = (0xaa800000) -+#define DEF_SYN_REGISTER_2() (REG32(ADR_SYN_REGISTER_2)) = (0x00550800) -+#define DEF_SYN_PFD_CHP() (REG32(ADR_SYN_PFD_CHP)) = (0x07c0894a) -+#define DEF_SYN_VCO_LOBF() (REG32(ADR_SYN_VCO_LOBF)) = (0xfcccca27) -+#define DEF_SYN_DIV_SDM_XOSC() (REG32(ADR_SYN_DIV_SDM_XOSC)) = (0x07700830) -+#define DEF_SYN_KVCO_XO_FINE_TUNE_CBANK() (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (0x00440000) -+#define DEF_SYN_LCK_VT() (REG32(ADR_SYN_LCK_VT)) = (0x00007ff4) -+#define DEF_DPLL_VCO_REGISTER() (REG32(ADR_DPLL_VCO_REGISTER)) = (0x0000000e) -+#define DEF_DPLL_CP_PFD_REGISTER() (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (0x00088008) -+#define DEF_DPLL_DIVIDER_REGISTER() (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (0x00406000) -+#define DEF_DCOC_IDAC_REGISTER1() (REG32(ADR_DCOC_IDAC_REGISTER1)) = (0x08820820) -+#define DEF_DCOC_IDAC_REGISTER2() (REG32(ADR_DCOC_IDAC_REGISTER2)) = (0x00820820) -+#define DEF_DCOC_IDAC_REGISTER3() (REG32(ADR_DCOC_IDAC_REGISTER3)) = (0x00820820) -+#define DEF_DCOC_IDAC_REGISTER4() (REG32(ADR_DCOC_IDAC_REGISTER4)) = (0x00820820) -+#define DEF_DCOC_IDAC_REGISTER5() (REG32(ADR_DCOC_IDAC_REGISTER5)) = (0x00820820) -+#define DEF_DCOC_IDAC_REGISTER6() (REG32(ADR_DCOC_IDAC_REGISTER6)) = (0x00820820) -+#define DEF_DCOC_IDAC_REGISTER7() (REG32(ADR_DCOC_IDAC_REGISTER7)) = (0x00820820) -+#define DEF_DCOC_IDAC_REGISTER8() (REG32(ADR_DCOC_IDAC_REGISTER8)) = (0x00820820) -+#define DEF_RCAL_REGISTER() (REG32(ADR_RCAL_REGISTER)) = (0x00004080) -+#define DEF_SX_LCK_BIN_REGISTERS_I() (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (0x20080080) -+#define DEF_TRX_DUMMY_REGISTER() (REG32(ADR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa) -+#define DEF_SX_DUMMY_REGISTER() (REG32(ADR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa) -+#define DEF_DPLL_FB_DIVIDER_REGISTERS_II() (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (0x00ec2ec5) -+#define DEF_SX_LCK_BIN_REGISTERS_II() (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (0x00000f13) -+#define DEF_RC_OSC_32K_CAL_REGISTERS() (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (0x00098900) -+#define DEF_RF_D_DIGITAL_DEBUG_PORT_REGISTER() (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (0x00000000) -+#define DEF_MMU_CTRL() (REG32(ADR_MMU_CTRL)) = (0x00002042) -+#define DEF_HS_CTRL() (REG32(ADR_HS_CTRL)) = (0x00000000) -+#define DEF_CPU_POR0_7() (REG32(ADR_CPU_POR0_7)) = (0x00000000) -+#define DEF_CPU_POR8_F() (REG32(ADR_CPU_POR8_F)) = (0x00000000) -+#define DEF_REG_LEN_CTRL() (REG32(ADR_REG_LEN_CTRL)) = (0x00000f0f) -+#define DEF_DMN_READ_BYPASS() (REG32(ADR_DMN_READ_BYPASS)) = (0x0000ffff) -+#define DEF_ALC_RLS_ABORT() (REG32(ADR_ALC_RLS_ABORT)) = (0x00000000) -+#define DEF_DEBUG_CTL() (REG32(ADR_DEBUG_CTL)) = (0x00000000) -+#define DEF_DEBUG_OUT() (REG32(ADR_DEBUG_OUT)) = (0x00000000) -+#define DEF_MMU_STATUS() (REG32(ADR_MMU_STATUS)) = (0x00000000) -+#define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00000000) -+#define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000) -+#define DEF_DMN_MCU_STATUS() (REG32(ADR_DMN_MCU_STATUS)) = (0x00000000) -+#define DEF_MB_IDTBL_0_STATUS() (REG32(ADR_MB_IDTBL_0_STATUS)) = (0x00000000) -+#define DEF_MB_IDTBL_1_STATUS() (REG32(ADR_MB_IDTBL_1_STATUS)) = (0x00000000) -+#define DEF_MB_IDTBL_2_STATUS() (REG32(ADR_MB_IDTBL_2_STATUS)) = (0x00000000) -+#define DEF_MB_IDTBL_3_STATUS() (REG32(ADR_MB_IDTBL_3_STATUS)) = (0x00000000) -+#define DEF_PKT_IDTBL_0_STATUS() (REG32(ADR_PKT_IDTBL_0_STATUS)) = (0x00000000) -+#define DEF_PKT_IDTBL_1_STATUS() (REG32(ADR_PKT_IDTBL_1_STATUS)) = (0x00000000) -+#define DEF_PKT_IDTBL_2_STATUS() (REG32(ADR_PKT_IDTBL_2_STATUS)) = (0x00000000) -+#define DEF_PKT_IDTBL_3_STATUS() (REG32(ADR_PKT_IDTBL_3_STATUS)) = (0x00000000) -+#define DEF_DMN_IDTBL_0_STATUS() (REG32(ADR_DMN_IDTBL_0_STATUS)) = (0x00000000) -+#define DEF_DMN_IDTBL_1_STATUS() (REG32(ADR_DMN_IDTBL_1_STATUS)) = (0x00000000) -+#define DEF_DMN_IDTBL_2_STATUS() (REG32(ADR_DMN_IDTBL_2_STATUS)) = (0x00000000) -+#define DEF_DMN_IDTBL_3_STATUS() (REG32(ADR_DMN_IDTBL_3_STATUS)) = (0x00000000) -+#define DEF_MB_NEQID_0_STATUS() (REG32(ADR_MB_NEQID_0_STATUS)) = (0x00000000) -+#define DEF_MB_NEQID_1_STATUS() (REG32(ADR_MB_NEQID_1_STATUS)) = (0x00000000) -+#define DEF_MB_NEQID_2_STATUS() (REG32(ADR_MB_NEQID_2_STATUS)) = (0x00000000) -+#define DEF_MB_NEQID_3_STATUS() (REG32(ADR_MB_NEQID_3_STATUS)) = (0x00000000) -+#define DEF_PKT_NEQID_0_STATUS() (REG32(ADR_PKT_NEQID_0_STATUS)) = (0x00000000) -+#define DEF_PKT_NEQID_1_STATUS() (REG32(ADR_PKT_NEQID_1_STATUS)) = (0x00000000) -+#define DEF_PKT_NEQID_2_STATUS() (REG32(ADR_PKT_NEQID_2_STATUS)) = (0x00000000) -+#define DEF_PKT_NEQID_3_STATUS() (REG32(ADR_PKT_NEQID_3_STATUS)) = (0x00000000) -+#define DEF_ALC_NOCHG_ID_STATUS() (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (0x00000000) -+#define DEF_TAG_SRAM0_F_STATUS_0() (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (0x00000000) -+#define DEF_TAG_SRAM0_F_STATUS_1() (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (0x00000000) -+#define DEF_TAG_SRAM0_F_STATUS_2() (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (0x00000000) -+#define DEF_TAG_SRAM0_F_STATUS_3() (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (0x00000000) -+#define DEF_TAG_SRAM0_F_STATUS_4() (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (0x00000000) -+#define DEF_TAG_SRAM0_F_STATUS_5() (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (0x00000000) -+#define DEF_TAG_SRAM0_F_STATUS_6() (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (0x00000000) -+#define DEF_TAG_SRAM0_F_STATUS_7() (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (0x00000000) -diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h -@@ -0,0 +1,176 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include "ssv6200_reg.h" -+#define BANK_COUNT 49 -+static const u32 BASE_BANK_SSV6200[] = { -+ SYS_REG_BASE, -+ WBOOT_REG_BASE, -+ TU0_US_REG_BASE, -+ TU1_US_REG_BASE, -+ TU2_US_REG_BASE, -+ TU3_US_REG_BASE, -+ TM0_MS_REG_BASE, -+ TM1_MS_REG_BASE, -+ TM2_MS_REG_BASE, -+ TM3_MS_REG_BASE, -+ MCU_WDT_REG_BASE, -+ SYS_WDT_REG_BASE, -+ GPIO_REG_BASE, -+ SD_REG_BASE, -+ SPI_REG_BASE, -+ CSR_I2C_MST_BASE, -+ UART_REG_BASE, -+ DAT_UART_REG_BASE, -+ INT_REG_BASE, -+ DBG_SPI_REG_BASE, -+ FLASH_SPI_REG_BASE, -+ DMA_REG_BASE, -+ CSR_PMU_BASE, -+ CSR_RTC_BASE, -+ RTC_RAM_BASE, -+ D2_DMA_REG_BASE, -+ HCI_REG_BASE, -+ CO_REG_BASE, -+ EFS_REG_BASE, -+ SMS4_REG_BASE, -+ MRX_REG_BASE, -+ AMPDU_REG_BASE, -+ MT_REG_CSR_BASE, -+ TXQ0_MT_Q_REG_CSR_BASE, -+ TXQ1_MT_Q_REG_CSR_BASE, -+ TXQ2_MT_Q_REG_CSR_BASE, -+ TXQ3_MT_Q_REG_CSR_BASE, -+ TXQ4_MT_Q_REG_CSR_BASE, -+ HIF_INFO_BASE, -+ PHY_RATE_INFO_BASE, -+ MAC_GLB_SET_BASE, -+ BTCX_REG_BASE, -+ MIB_REG_BASE, -+ CBR_A_REG_BASE, -+ MB_REG_BASE, -+ ID_MNG_REG_BASE, -+ CSR_PHY_BASE, -+ CSR_RF_BASE, -+ MMU_REG_BASE, -+ 0x00000000 -+}; -+ -+static const char *STR_BANK_SSV6200[] = { -+ "SYS_REG", -+ "WBOOT_REG", -+ "TU0_US_REG", -+ "TU1_US_REG", -+ "TU2_US_REG", -+ "TU3_US_REG", -+ "TM0_MS_REG", -+ "TM1_MS_REG", -+ "TM2_MS_REG", -+ "TM3_MS_REG", -+ "MCU_WDT_REG", -+ "SYS_WDT_REG", -+ "GPIO_REG", -+ "SD_REG", -+ "SPI_REG", -+ "CSR_I2C_MST", -+ "UART_REG", -+ "DAT_UART_REG", -+ "INT_REG", -+ "DBG_SPI_REG", -+ "FLASH_SPI_REG", -+ "DMA_REG", -+ "CSR_PMU", -+ "CSR_RTC", -+ "RTC_RAM", -+ "D2_DMA_REG", -+ "HCI_REG", -+ "CO_REG", -+ "EFS_REG", -+ "SMS4_REG", -+ "MRX_REG", -+ "AMPDU_REG", -+ "MT_REG_CSR", -+ "TXQ0_MT_Q_REG_CSR", -+ "TXQ1_MT_Q_REG_CSR", -+ "TXQ2_MT_Q_REG_CSR", -+ "TXQ3_MT_Q_REG_CSR", -+ "TXQ4_MT_Q_REG_CSR", -+ "HIF_INFO", -+ "PHY_RATE_INFO", -+ "MAC_GLB_SET", -+ "BTCX_REG", -+ "MIB_REG", -+ "CBR_A_REG", -+ "MB_REG", -+ "ID_MNG_REG", -+ "CSR_PHY", -+ "CSR_RF", -+ "MMU_REG", -+ "" -+}; -+ -+static const u32 SIZE_BANK_SSV6200[] = { -+ SYS_REG_BANK_SIZE, -+ WBOOT_REG_BANK_SIZE, -+ TU0_US_REG_BANK_SIZE, -+ TU1_US_REG_BANK_SIZE, -+ TU2_US_REG_BANK_SIZE, -+ TU3_US_REG_BANK_SIZE, -+ TM0_MS_REG_BANK_SIZE, -+ TM1_MS_REG_BANK_SIZE, -+ TM2_MS_REG_BANK_SIZE, -+ TM3_MS_REG_BANK_SIZE, -+ MCU_WDT_REG_BANK_SIZE, -+ SYS_WDT_REG_BANK_SIZE, -+ GPIO_REG_BANK_SIZE, -+ SD_REG_BANK_SIZE, -+ SPI_REG_BANK_SIZE, -+ CSR_I2C_MST_BANK_SIZE, -+ UART_REG_BANK_SIZE, -+ DAT_UART_REG_BANK_SIZE, -+ INT_REG_BANK_SIZE, -+ DBG_SPI_REG_BANK_SIZE, -+ FLASH_SPI_REG_BANK_SIZE, -+ DMA_REG_BANK_SIZE, -+ CSR_PMU_BANK_SIZE, -+ CSR_RTC_BANK_SIZE, -+ RTC_RAM_BANK_SIZE, -+ D2_DMA_REG_BANK_SIZE, -+ HCI_REG_BANK_SIZE, -+ CO_REG_BANK_SIZE, -+ EFS_REG_BANK_SIZE, -+ SMS4_REG_BANK_SIZE, -+ MRX_REG_BANK_SIZE, -+ AMPDU_REG_BANK_SIZE, -+ MT_REG_CSR_BANK_SIZE, -+ TXQ0_MT_Q_REG_CSR_BANK_SIZE, -+ TXQ1_MT_Q_REG_CSR_BANK_SIZE, -+ TXQ2_MT_Q_REG_CSR_BANK_SIZE, -+ TXQ3_MT_Q_REG_CSR_BANK_SIZE, -+ TXQ4_MT_Q_REG_CSR_BANK_SIZE, -+ HIF_INFO_BANK_SIZE, -+ PHY_RATE_INFO_BANK_SIZE, -+ MAC_GLB_SET_BANK_SIZE, -+ BTCX_REG_BANK_SIZE, -+ MIB_REG_BANK_SIZE, -+ CBR_A_REG_BANK_SIZE, -+ MB_REG_BANK_SIZE, -+ ID_MNG_REG_BANK_SIZE, -+ CSR_PHY_BANK_SIZE, -+ CSR_RF_BANK_SIZE, -+ MMU_REG_BANK_SIZE, -+ 0x00000000 -+}; -diff --git a/drivers/net/wireless/ssv6051/include/ssv_cfg.h b/drivers/net/wireless/ssv6051/include/ssv_cfg.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/include/ssv_cfg.h -@@ -0,0 +1,60 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV_CFG_H_ -+#define _SSV_CFG_H_ -+#define SSV6200_HW_CAP_HT 0x00000001 -+#define SSV6200_HW_CAP_GF 0x00000002 -+#define SSV6200_HW_CAP_2GHZ 0x00000004 -+#define SSV6200_HW_CAP_5GHZ 0x00000008 -+#define SSV6200_HW_CAP_SECURITY 0x00000010 -+#define SSV6200_HT_CAP_SGI_20 0x00000020 -+#define SSV6200_HT_CAP_SGI_40 0x00000040 -+#define SSV6200_HW_CAP_AP 0x00000080 -+#define SSV6200_HW_CAP_P2P 0x00000100 -+#define SSV6200_HW_CAP_AMPDU_RX 0x00000200 -+#define SSV6200_HW_CAP_AMPDU_TX 0x00000400 -+#define SSV6200_HW_CAP_TDLS 0x00000800 -+#define EXTERNEL_CONFIG_SUPPORT 64 -+struct ssv6xxx_cfg { -+ u32 hw_caps; -+ u32 def_chan; -+ u32 crystal_type; -+ u32 volt_regulator; -+ u32 force_chip_identity; -+ u8 maddr[2][6]; -+ u32 n_maddr; -+ u32 use_wpa2_only; -+ u32 ignore_reset_in_ap; -+ u32 r_calbration_result; -+ u32 sar_result; -+ u32 crystal_frequency_offset; -+ u32 tx_power_index_1; -+ u32 tx_power_index_2; -+ u32 chip_identity; -+ u32 wifi_tx_gain_level_gn; -+ u32 wifi_tx_gain_level_b; -+ u32 rssi_ctl; -+ u32 sr_bhvr; -+ u32 configuration[EXTERNEL_CONFIG_SUPPORT + 1][2]; -+ u8 firmware_path[128]; -+ u8 flash_bin_path[128]; -+ u8 mac_address_path[128]; -+ u8 mac_output_path[128]; -+ u32 ignore_efuse_mac; -+ u32 mac_address_mode; -+}; -+#endif -diff --git a/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h -@@ -0,0 +1,25 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV_FIRMWARE_VERSION_H_ -+#define _SSV_FIRMWARE_VERSION_H_ -+static u32 ssv_firmware_version = 16380; -+#define SSV_FIRMWARE_URl "http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/6051.Q0.1009.21.000000/ssv6xxx/smac/firmware" -+#define FIRMWARE_COMPILERHOST "ssv-ThinkPad-X230" -+#define FIRMWARE_COMPILERDATE "11-06-2017-09:17:18" -+#define FIRMWARE_COMPILEROS "linux" -+#define FIRMWARE_COMPILEROSARCH "x86_64-linux-gnu-thread-multi" -+#endif -diff --git a/drivers/net/wireless/ssv6051/include/ssv_version.h b/drivers/net/wireless/ssv6051/include/ssv_version.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/include/ssv_version.h -@@ -0,0 +1,12 @@ -+#ifndef _SSV_VERSION_H_ -+#define _SSV_VERSION_H_ -+ -+static u32 ssv_root_version = 16529; -+ -+#define SSV_ROOT_URl "http://192.168.15.30/svn/software/project/release/android/box/rk3x28/6051.Q0.1009.21.400401/ssv6xxx" -+#define COMPILERHOST "icomm-buildserver-T320" -+#define COMPILERDATE "12-08-2017-10:34:54" -+#define COMPILEROS "linux" -+#define COMPILEROSARCH "x86_64-linux-gnu-thread-multi" -+ -+#endif -diff --git a/drivers/net/wireless/ssv6051/platform-config.mak b/drivers/net/wireless/ssv6051/platform-config.mak -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/platform-config.mak -@@ -0,0 +1,97 @@ -+ -+ccflags-y += -DCONFIG_SSV6200_CORE -+ -+########################################################################### -+# Compiler options # -+########################################################################### -+ -+# Enable -g to help debug. Deassembly from .o to .S would help to track to -+# the problomatic line from call stack dump. -+#ccflags-y += -g -+ccflags += -Os -+ -+############################################################ -+# If you change the settings, please change the file synchronization -+# smac\firmware\include\config.h & compiler firmware -+############################################################ -+#ccflags-y += -DCONFIG_SSV_CABRIO_A -+ccflags-y += -DCONFIG_SSV_CABRIO_E -+ -+#CONFIG_SSV_SUPPORT_BTCX=y -+ -+#ccflags-y += -DDEBUG -+ccflags-y += -DCONFIG_SSV6200_CLI_ENABLE -+ -+#PADPD -+#ccflags-y += -DCONFIG_SSV_DPD -+ -+#ccflags-y += -DCONFIG_SSV_CABRIO_MB_DEBUG -+#ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS -+ -+#SDIO -+ccflags-y += -DCONFIG_SSV_TX_LOWTHRESHOLD -+ -+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK -+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3 -+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128 -+#ccflags-y += -DMULTI_THREAD_ENCRYPT -+#ccflags-y += -DKTHREAD_BIND -+#ccflags-y += -DROCKCHIP_WIFI_AUTO_SUPPORT -+ccflags-y += -DCONFIG_SSV_RSSI -+ccflags-y += -DCONFIG_SSV_VENDOR_EXT_SUPPORT -+ -+############################################################ -+# Rate control update for MPDU. -+############################################################ -+ccflags-y += -DRATE_CONTROL_REALTIME_UPDATA -+ -+#workaround -+#ccflags-y += -DCONFIG_SSV_CABRIO_EXT_PA -+ -+############################################################ -+# NOTE: -+# Only one of the following flags could be turned on. -+# It also turned off the following flags. In this case, -+# pure software security or pure hardware security is used. -+# -+############################################################ -+#ccflags-y += -DCONFIG_SSV_SW_ENCRYPT_HW_DECRYPT -+#ccflags-y += -DCONFIG_SSV_HW_ENCRYPT_SW_DECRYPT -+ -+# FOR WFA -+#ccflags-y += -DWIFI_CERTIFIED -+ -+#ccflags-y += -DCONFIG_SSV_SDIO_EXT_INT -+ -+####################################################### -+ccflags-y += -DCONFIG_SSV6200_HAS_RX_WORKQUEUE -+#ccflags-y += -DUSE_THREAD_RX -+ccflags-y += -DUSE_THREAD_TX -+ccflags-y += -DENABLE_AGGREGATE_IN_TIME -+ccflags-y += -DENABLE_INCREMENTAL_AGGREGATION -+ -+# Generic decision table applicable to both AP and STA modes. -+ccflags-y += -DUSE_GENERIC_DECI_TBL -+ -+#ccflags-y += -DCONFIG_SSV_WAPI -+ -+ccflags-y += -DFW_WSID_WATCH_LIST -+#ccflags-y += -DUSE_BATCH_RX -+#ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT -+ -+ccflags-y += -DSSV6200_ECO -+#ccflags-y += -DENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE -+ccflags-y += -DHAS_CRYPTO_LOCK -+ccflags-y += -DENABLE_TX_Q_FLOW_CONTROL -+ -+#ccflags-y += -DCONFIG_DEBUG_SKB_TIMESTAMP -+ -+ -+#enable p2p client to parse GO broadcast noa -+#ccflags-y += -DCONFIG_P2P_NOA -+ -+#enable rx management frame check -+#ccflags-y += -DCONFIG_RX_MGMT_CHECK -+ -+#force SW Broadcast/Multicast decryption -+ccflags-y += -DUSE_MAC80211_DECRYPT_BROADCAST -\ No newline at end of file -diff --git a/drivers/net/wireless/ssv6051/rules.mak b/drivers/net/wireless/ssv6051/rules.mak -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/rules.mak -@@ -0,0 +1,19 @@ -+ -+ -+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o) -+obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o -+ -+ -+.PHONY: all clean install -+ -+all: -+ @$(MAKE) -C /lib/modules/$(KVERSION)/build \ -+ SUBDIRS=$(KBUILD_DIR) CONFIG_DEBUG_SECTION_MISMATCH=y \ -+ modules -+ -+clean: -+ @$(MAKE) -C /lib/modules/$(KVERSION)/build SUBDIRS=$(KBUILD_DIR) clean -+ -+install: -+ @$(MAKE) INSTALL_MOD_DIR=$(DRVPATH) -C /lib/modules/$(KVERSION)/build \ -+ M=$(KBUILD_DIR) modules_install -diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.c b/drivers/net/wireless/ssv6051/smac/ampdu.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ampdu.c -@@ -0,0 +1,2111 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include "dev.h" -+#include "ap.h" -+#include "sec.h" -+#include "ssv_rc_common.h" -+#include "ssv_ht_rc.h" -+extern struct ieee80211_ops ssv6200_ops; -+ -+// Hack: redefine MAX_AMPDU_BUF because buf_size here is a 8-bit char -+// and mainline kernel value is 0x100, which overflows -+#ifdef IEEE80211_MAX_AMPDU_BUF -+#undef IEEE80211_MAX_AMPDU_BUF -+#endif -+#define IEEE80211_MAX_AMPDU_BUF 0x40 -+ -+#define BA_WAIT_TIMEOUT (800) -+#define AMPDU_BA_FRAME_LEN (68) -+#define ampdu_skb_hdr(skb) ((struct ieee80211_hdr*)((u8*)((skb)->data)+AMPDU_DELIMITER_LEN)) -+#define ampdu_skb_ssn(skb) ((ampdu_skb_hdr(skb)->seq_ctrl)>>SSV_SEQ_NUM_SHIFT) -+#define ampdu_hdr_ssn(hdr) ((hdr)->seq_ctrl>>SSV_SEQ_NUM_SHIFT) -+#undef prn_aggr_dbg -+#define prn_aggr_dbg(fmt,...) -+static void void_func(const char *fmt, ...) -+{ -+} -+ -+#define prn_aggr_err(fmt,...) \ -+ do { \ -+ void_func(KERN_ERR fmt, ##__VA_ARGS__);\ -+ } while (0) -+#define get_tid_aggr_len(agg_len,tid_data) \ -+ ({ \ -+ u32 agg_max_num = (tid_data)->agg_num_max; \ -+ u32 to_agg_len = (agg_len); \ -+ (agg_len >= agg_max_num) ? agg_max_num : to_agg_len; \ -+ }) -+#define INDEX_PKT_BY_SSN(tid,ssn) \ -+ ((tid)->aggr_pkts[(ssn) % SSV_AMPDU_BA_WINDOW_SIZE]) -+#define NEXT_PKT_SN(sn) \ -+ ({ (sn + 1) % SSV_AMPDU_MAX_SSN; }) -+#define INC_PKT_SN(sn) \ -+ ({ \ -+ sn = NEXT_PKT_SN(sn); \ -+ sn; \ -+ }) -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+static ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv, -+ char *mib_str, ssize_t length); -+static int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb); -+#endif -+static struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc, -+ struct AMPDU_TID_st *cur_AMPDU_TID, -+ struct sk_buff_head *retry_queue, -+ u32 max_aggr_len); -+static int _dump_BA_notification(char *buf, -+ struct ampdu_ba_notify_data *ba_notification); -+static struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc, -+ struct AMPDU_TID_st *ampdu_tid, -+ u32 len); -+static bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid, -+ struct sk_buff *ampdu_skb, bool retry); -+static void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu); -+static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb); -+static u32 _flush_early_ampdu_q(struct ssv_softc *sc, -+ struct AMPDU_TID_st *ampdu_tid); -+static bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb); -+static void _aggr_ampdu_tx_q(struct ieee80211_hw *hw, -+ struct AMPDU_TID_st *ampdu_tid); -+static void _queue_early_ampdu(struct ssv_softc *sc, -+ struct AMPDU_TID_st *ampdu_tid, -+ struct sk_buff *ampdu_skb); -+static int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb); -+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP -+unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage) -+{ -+ unsigned int timeout; -+ SKB_info *mpdu_skb_info; -+ u16 ssn = 0; -+ struct sk_buff *mpdu = NULL; -+ struct ampdu_hdr_st *ampdu_hdr = NULL; -+ ktime_t current_ktime; -+ ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head; -+ ssn = ampdu_hdr->ssn[0]; -+ mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn); -+ if (mpdu == NULL) -+ return 0; -+ mpdu_skb_info = (SKB_info *) (mpdu->head); -+ current_ktime = ktime_get(); -+ timeout = -+ (unsigned int) -+ ktime_to_ms(ktime_sub(current_ktime, mpdu_skb_info->timestamp)); -+ if (timeout > SKB_DURATION_TIMEOUT_MS) { -+ if (stage == SKB_DURATION_STAGE_TO_SDIO) -+ pr_debug("*a_to_sdio: %ums\n", timeout); -+ else if (stage == SKB_DURATION_STAGE_TX_ENQ) -+ pr_debug("*a_to_txenqueue: %ums\n", timeout); -+ else -+ pr_debug("*a_in_hwq: %ums\n", timeout); -+ } -+ return timeout; -+} -+#endif -+static u8 _cal_ampdu_delm_half_crc(u8 value) -+{ -+ u32 c32 = value, v32 = value; -+ c32 ^= (v32 >> 1) | (v32 << 7); -+ c32 ^= (v32 >> 2); -+ if (v32 & 2) -+ c32 ^= (0xC0); -+ c32 ^= ((v32 << 4) & 0x30); -+ return (u8) c32; -+} -+ -+static u8 _cal_ampdu_delm_crc(u8 * pointer) -+{ -+ u8 crc = 0xCF; -+ crc ^= _cal_ampdu_delm_half_crc(*pointer++); -+ crc = -+ _cal_ampdu_delm_half_crc(crc) ^ _cal_ampdu_delm_half_crc(*pointer); -+ return ~crc; -+} -+ -+static bool ssv6200_ampdu_add_delimiter_and_crc32(struct sk_buff *mpdu) -+{ -+ p_AMPDU_DELIMITER delimiter_p; -+ struct ieee80211_hdr *mpdu_hdr; -+ int ret; -+ u32 orig_mpdu_len = mpdu->len; -+ u32 pad = (4 - (orig_mpdu_len % 4)) % 4; -+ mpdu_hdr = (struct ieee80211_hdr *)(mpdu->data); -+ mpdu_hdr->duration_id = AMPDU_TX_NAV_MCS_567; -+ ret = skb_padto(mpdu, mpdu->len + (AMPDU_FCS_LEN + pad)); -+ if (ret) { -+ pr_err("Failed to extand skb for aggregation\n"); -+ return false; -+ } -+ skb_put(mpdu, AMPDU_FCS_LEN + pad); -+ skb_push(mpdu, AMPDU_DELIMITER_LEN); -+ delimiter_p = (p_AMPDU_DELIMITER) mpdu->data; -+ delimiter_p->reserved = 0; -+ delimiter_p->length = orig_mpdu_len + AMPDU_FCS_LEN; -+ delimiter_p->signature = AMPDU_SIGNATURE; -+ delimiter_p->crc = _cal_ampdu_delm_crc((u8 *) (delimiter_p)); -+ return true; -+} -+ -+static void ssv6200_ampdu_hw_init(struct ieee80211_hw *hw) -+{ -+ struct ssv_softc *sc = hw->priv; -+ u32 temp32; -+ SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32); -+ temp32 |= (0x1 << MTX_AMPDU_CRC_AUTO_SFT); -+ SMAC_REG_WRITE(sc->sh, ADR_MTX_MISC_EN, temp32); -+ SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32); -+} -+ -+bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid, struct sk_buff *ampdu, -+ bool retry) -+{ -+ struct sk_buff **pp_aggr_pkt; -+ struct sk_buff *p_aggr_pkt; -+ unsigned long flags; -+ struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head; -+ struct sk_buff *mpdu; -+ u32 first_ssn = SSV_ILLEGAL_SN; -+ u32 old_aggr_pkt_num; -+ u32 old_baw_head; -+ u32 sync_num = skb_queue_len(&du_hdr->mpdu_q); -+ bool ret = true; -+ spin_lock_irqsave(&du_tid->pkt_array_lock, flags); -+ old_baw_head = ampdu_tid->ssv_baw_head; -+ old_aggr_pkt_num = ampdu_tid->aggr_pkt_num; -+ ampdu_tid->mib.ampdu_mib_ampdu_counter += 1; -+ ampdu_tid->mib.ampdu_mib_dist[sync_num] += 1; -+ do { -+ if (!retry) { -+ ampdu_tid->mib.ampdu_mib_mpdu_counter += sync_num; -+ mpdu = skb_peek_tail(&du_hdr->mpdu_q); -+ if (mpdu == NULL) { -+ ret = false; -+ break; -+ } else { -+ u32 ssn = ampdu_skb_ssn(mpdu); -+ p_aggr_pkt = INDEX_PKT_BY_SSN(ampdu_tid, ssn); -+ if (p_aggr_pkt != NULL) { -+ char msg[256]; -+ u32 sn = ampdu_skb_ssn(mpdu); -+ skb_queue_walk(&du_hdr->mpdu_q, mpdu) { -+ sn = ampdu_skb_ssn(mpdu); -+ sprintf(msg, " %d", sn); -+ } -+ prn_aggr_err("ES %d -> %d (%s)\n", -+ ssn, -+ ampdu_skb_ssn(p_aggr_pkt), -+ msg); -+ ret = false; -+ break; -+ } -+ } -+ } else -+ ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1; -+ skb_queue_walk(&du_hdr->mpdu_q, mpdu) { -+ u32 ssn = ampdu_skb_ssn(mpdu); -+ SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head); -+ if (first_ssn == SSV_ILLEGAL_SN) -+ first_ssn = ssn; -+ pp_aggr_pkt = &INDEX_PKT_BY_SSN(ampdu_tid, ssn); -+ p_aggr_pkt = *pp_aggr_pkt; -+ *pp_aggr_pkt = mpdu; -+ if (!retry) -+ ampdu_tid->aggr_pkt_num++; -+ mpdu_skb_info->ampdu_tx_status = AMPDU_ST_AGGREGATED; -+ if (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN) { -+ ampdu_tid->ssv_baw_head = ssn; -+ } -+ if ((p_aggr_pkt != NULL) && (mpdu != p_aggr_pkt)) -+ prn_aggr_err("%d -> %d (H%d, N%d, Q%d)\n", -+ ssn, ampdu_skb_ssn(p_aggr_pkt), -+ old_baw_head, old_aggr_pkt_num, -+ sync_num); -+ } -+ } while (0); -+ spin_unlock_irqrestore(&du_tid->pkt_array_lock, flags); -+ { -+ u32 page_count = (ampdu->len + SSV6200_ALLOC_RSVD); -+ if (page_count & HW_MMU_PAGE_MASK) -+ page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1; -+ else -+ page_count = page_count >> HW_MMU_PAGE_SHIFT; -+ if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2)) -+ pr_err("AMPDU requires pages %d(%d-%d-%d) exceeds resource limit %d.\n", -+ page_count, ampdu->len, ampdu_hdr->max_size, -+ ampdu_hdr->size, -+ (SSV6200_PAGE_TX_THRESHOLD / 2)); -+ } -+ return ret; -+} -+ -+struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc, -+ struct AMPDU_TID_st *ampdu_tid, -+ struct sk_buff_head *retry_queue, -+ u32 max_aggr_len) -+{ -+ struct sk_buff *retry_mpdu; -+ struct sk_buff *new_ampdu_skb; -+ u32 num_retry_mpdu; -+ u32 temp_i; -+ u32 total_skb_size; -+ unsigned long flags; -+ u16 head_ssn = ampdu_tid->ssv_baw_head; -+ struct ampdu_hdr_st *ampdu_hdr; -+ BUG_ON(head_ssn == SSV_ILLEGAL_SN); -+ num_retry_mpdu = skb_queue_len(retry_queue); -+ if (num_retry_mpdu == 0) -+ return NULL; -+ new_ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, max_aggr_len); -+ if (new_ampdu_skb == 0) -+ return NULL; -+ ampdu_hdr = (struct ampdu_hdr_st *)new_ampdu_skb->head; -+ total_skb_size = 0; -+ spin_lock_irqsave(&retry_queue->lock, flags); -+ for (temp_i = 0; temp_i < ampdu_tid->agg_num_max; temp_i++) { -+ struct ieee80211_hdr *mpdu_hdr; -+ u16 mpdu_sn; -+ u16 diff; -+ u32 new_total_skb_size; -+ retry_mpdu = skb_peek(retry_queue); -+ if (retry_mpdu == NULL) { -+ break; -+ } -+ mpdu_hdr = ampdu_skb_hdr(retry_mpdu); -+ mpdu_sn = ampdu_hdr_ssn(mpdu_hdr); -+ diff = SSV_AMPDU_SN_a_minus_b(head_ssn, mpdu_sn); -+ if ((head_ssn != SSV_ILLEGAL_SN) -+ && (diff > 0) -+ && (diff <= ampdu_tid->ssv_baw_size)) { -+ struct SKB_info_st *skb_info; -+ prn_aggr_err("Z. release skb (s %d, h %d, d %d)\n", -+ mpdu_sn, head_ssn, diff); -+ skb_info = (struct SKB_info_st *)(retry_mpdu->head); -+ skb_info->ampdu_tx_status = AMPDU_ST_DROPPED; -+ ampdu_tid->mib.ampdu_mib_discard_counter++; -+ continue; -+ } -+ new_total_skb_size = total_skb_size + retry_mpdu->len; -+ if (new_total_skb_size > ampdu_hdr->max_size) -+ break; -+ total_skb_size = new_total_skb_size; -+ retry_mpdu = __skb_dequeue(retry_queue); -+ _put_mpdu_to_ampdu(new_ampdu_skb, retry_mpdu); -+ ampdu_tid->mib.ampdu_mib_retry_counter++; -+ } -+ ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1; -+ ampdu_tid->mib.ampdu_mib_dist[temp_i] += 1; -+ spin_unlock_irqrestore(&retry_queue->lock, flags); -+ if (ampdu_hdr->mpdu_num == 0) { -+ dev_kfree_skb_any(new_ampdu_skb); -+ return NULL; -+ } -+ return new_ampdu_skb; -+} -+ -+static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb) -+{ -+ struct ssv6200_tx_desc *tx_desc; -+ ssv6xxx_add_txinfo(sc, ampdu_skb); -+ tx_desc = (struct ssv6200_tx_desc *)ampdu_skb->data; -+ tx_desc->tx_report = 1; -+} -+ -+void _send_hci_skb(struct ssv_softc *sc, struct sk_buff *skb, u32 tx_flag) -+{ -+ struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data; -+ int ret = AMPDU_HCI_SEND(sc->sh, skb, tx_desc->txq_idx, tx_flag); -+ if ((tx_desc->txq_idx > 3) && (ret <= 0)) { -+ prn_aggr_err("BUG!! %d %d\n", tx_desc->txq_idx, ret); -+ } -+} -+ -+static void ssv6200_ampdu_add_txinfo_and_send_HCI(struct ssv_softc *sc, -+ struct sk_buff *ampdu_skb, -+ u32 tx_flag) -+{ -+ _add_ampdu_txinfo(sc, ampdu_skb); -+ _send_hci_skb(sc, ampdu_skb, tx_flag); -+} -+ -+static void ssv6200_ampdu_send_retry(struct ieee80211_hw *hw, -+ AMPDU_TID * cur_ampdu_tid, -+ struct sk_buff_head -+ *ampdu_skb_retry_queue_p, -+ bool send_aggr_tx) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct sk_buff *ampdu_retry_skb; -+ u32 ampdu_skb_retry_queue_len; -+ u32 max_agg_len; -+ u16 lowest_rate; -+ struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES]; -+ ampdu_skb_retry_queue_len = skb_queue_len(ampdu_skb_retry_queue_p); -+ if (ampdu_skb_retry_queue_len == 0) -+ return; -+ ampdu_retry_skb = skb_peek(ampdu_skb_retry_queue_p); -+ lowest_rate = ssv62xx_ht_rate_update(ampdu_retry_skb, sc, rates); -+ max_agg_len = ampdu_max_transmit_length[lowest_rate]; -+ if (max_agg_len > 0) { -+ u32 cur_ampdu_max_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh); -+ if (max_agg_len >= cur_ampdu_max_size) -+ max_agg_len = cur_ampdu_max_size; -+ while (ampdu_skb_retry_queue_len > 0) { -+ struct sk_buff *retry_mpdu = -+ skb_peek(ampdu_skb_retry_queue_p); -+ SKB_info *mpdu_skb_info = -+ (SKB_info *) (retry_mpdu->head); -+ mpdu_skb_info->lowest_rate = lowest_rate; -+ memcpy(mpdu_skb_info->rates, rates, sizeof(rates)); -+ ampdu_retry_skb = -+ _aggr_retry_mpdu(sc, cur_ampdu_tid, -+ ampdu_skb_retry_queue_p, -+ max_agg_len); -+ if (ampdu_retry_skb != NULL) { -+ _sync_ampdu_pkt_arr(cur_ampdu_tid, -+ ampdu_retry_skb, true); -+ ssv6200_ampdu_add_txinfo_and_send_HCI(sc, -+ ampdu_retry_skb, -+ AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL); -+ } else { -+ prn_aggr_err("AMPDU retry failed.\n"); -+ return; -+ } -+ ampdu_skb_retry_queue_len = -+ skb_queue_len(ampdu_skb_retry_queue_p); -+ } -+ } else { -+ struct ieee80211_tx_rate rates[IEEE80211_TX_MAX_RATES]; -+ struct ieee80211_tx_info *info = -+ IEEE80211_SKB_CB(ampdu_retry_skb); -+ memcpy(rates, info->control.rates, sizeof(info->control.rates)); -+ while ((ampdu_retry_skb = -+ __skb_dequeue_tail(ampdu_skb_retry_queue_p)) != NULL) { -+ struct ieee80211_tx_info *info = -+ IEEE80211_SKB_CB(ampdu_retry_skb); -+ info->flags &= ~IEEE80211_TX_CTL_AMPDU; -+ memcpy(info->control.rates, rates, -+ sizeof(info->control.rates)); -+ ssv6xxx_update_txinfo(sc, ampdu_retry_skb); -+ _send_hci_skb(sc, ampdu_retry_skb, -+ AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL); -+ } -+ } -+} -+ -+void ssv6200_ampdu_init(struct ieee80211_hw *hw) -+{ -+ struct ssv_softc *sc = hw->priv; -+ ssv6200_ampdu_hw_init(hw); -+ sc->tx.ampdu_tx_group_id = 0; -+#ifdef USE_ENCRYPT_WORK -+ INIT_WORK(&sc->ampdu_tx_encry_work, encry_work); -+ INIT_WORK(&sc->sync_hwkey_work, sync_hw_key_work); -+#endif -+} -+ -+void ssv6200_ampdu_deinit(struct ieee80211_hw *hw) -+{ -+} -+ -+void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw) -+{ -+ ieee80211_free_txskb(hw, skb); -+} -+ -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+struct mib_dump_data { -+ char *prt_buff; -+ size_t buff_size; -+ size_t prt_len; -+}; -+#define AMPDU_TX_MIB_SUMMARY_BUF_SIZE (4096) -+static ssize_t ampdu_tx_mib_summary_read(struct file *file, -+ char __user * user_buf, size_t count, -+ loff_t * ppos) -+{ -+ struct ssv_sta_priv_data *ssv_sta_priv = -+ (struct ssv_sta_priv_data *)file->private_data; -+ char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL); -+ ssize_t summary_size; -+ ssize_t ret; -+ if (!summary_buf) -+ return -ENOMEM; -+ summary_size = ampdu_tx_mib_dump(ssv_sta_priv, summary_buf, -+ AMPDU_TX_MIB_SUMMARY_BUF_SIZE); -+ ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf, -+ summary_size); -+ kfree(summary_buf); -+ return ret; -+} -+ -+static int ampdu_tx_mib_summary_open(struct inode *inode, struct file *file) -+{ -+ file->private_data = inode->i_private; -+ return 0; -+} -+ -+static const struct file_operations mib_summary_fops = {.read = -+ ampdu_tx_mib_summary_read,.open = ampdu_tx_mib_summary_open, -+}; -+ -+static ssize_t ampdu_tx_tid_window_read(struct file *file, -+ char __user * user_buf, size_t count, -+ loff_t * ppos) -+{ -+ struct AMPDU_TID_st *ampdu_tid = -+ (struct AMPDU_TID_st *)file->private_data; -+ char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL); -+ ssize_t ret; -+ char *prn_ptr = summary_buf; -+ int prt_size; -+ int buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE; -+ int i; -+ struct sk_buff *ba_skb, *tmp_ba_skb; -+ if (!summary_buf) -+ return -ENOMEM; -+ prt_size = snprintf(prn_ptr, buf_size, "\nWMM_TID %d:\n" -+ "\tWindow:", ampdu_tid->tidno); -+ prn_ptr += prt_size; -+ buf_size -= prt_size; -+ for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i++) { -+ struct sk_buff *skb = ampdu_tid->aggr_pkts[i]; -+ if ((i % 8) == 0) { -+ prt_size = snprintf(prn_ptr, buf_size, "\n\t\t"); -+ prn_ptr += prt_size; -+ buf_size -= prt_size; -+ } -+ if (skb == NULL) -+ prt_size = snprintf(prn_ptr, buf_size, " %s", "NULL "); -+ else { -+ struct SKB_info_st *skb_info = -+ (struct SKB_info_st *)(skb->head); -+ const char status_symbol[] = { 'N', -+ 'A', -+ 'S', -+ 'R', -+ 'P', -+ 'D' -+ }; -+ prt_size = -+ snprintf(prn_ptr, buf_size, " %4d%c", -+ ampdu_skb_ssn(skb), -+ ((skb_info->ampdu_tx_status <= -+ AMPDU_ST_DONE) -+ ? status_symbol[skb_info->ampdu_tx_status] -+ : 'X')); -+ } -+ prn_ptr += prt_size; -+ buf_size -= prt_size; -+ } -+ prt_size = -+ snprintf(prn_ptr, buf_size, "\n\tEarly aggregated #: %d\n", -+ ampdu_tid->early_aggr_skb_num); -+ prn_ptr += prt_size; -+ buf_size -= prt_size; -+ prt_size = -+ snprintf(prn_ptr, buf_size, "\tBAW skb #: %d\n", -+ ampdu_tid->aggr_pkt_num); -+ prn_ptr += prt_size; -+ buf_size -= prt_size; -+ prt_size = -+ snprintf(prn_ptr, buf_size, "\tBAW head: %d\n", -+ ampdu_tid->ssv_baw_head); -+ prn_ptr += prt_size; -+ buf_size -= prt_size; -+ prt_size = -+ snprintf(prn_ptr, buf_size, "\tState: %d\n", ampdu_tid->state); -+ prn_ptr += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(prn_ptr, buf_size, "\tBA:\n"); -+ prn_ptr += prt_size; -+ buf_size -= prt_size; -+ skb_queue_walk_safe(&du_tid->ba_q, ba_skb, tmp_ba_skb) { -+ prt_size = _dump_ba_skb(prn_ptr, buf_size, ba_skb); -+ prn_ptr += prt_size; -+ buf_size -= prt_size; -+ } -+ buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE - buf_size; -+ ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf, -+ buf_size); -+ kfree(summary_buf); -+ return ret; -+} -+ -+static int ampdu_tx_tid_window_open(struct inode *inode, struct file *file) -+{ -+ file->private_data = inode->i_private; -+ return 0; -+} -+ -+static const struct file_operations tid_window_fops = {.read = -+ ampdu_tx_tid_window_read,.open = ampdu_tx_tid_window_open, -+}; -+ -+static int ampdu_tx_mib_reset_open(struct inode *inode, struct file *file) -+{ -+ file->private_data = inode->i_private; -+ return 0; -+} -+ -+static ssize_t ampdu_tx_mib_reset_read(struct file *file, -+ char __user * user_buf, size_t count, -+ loff_t * ppos) -+{ -+ char *reset_buf = kzalloc(64, GFP_KERNEL); -+ ssize_t ret; -+ u32 reset_size; -+ if (!reset_buf) -+ return -ENOMEM; -+ reset_size = snprintf(reset_buf, 63, "%d", 0); -+ ret = simple_read_from_buffer(user_buf, count, ppos, reset_buf, -+ reset_size); -+ kfree(reset_buf); -+ return ret; -+} -+ -+static ssize_t ampdu_tx_mib_reset_write(struct file *file, -+ const char __user * buffer, -+ size_t count, loff_t * pos) -+{ -+ struct AMPDU_TID_st *ampdu_tid = -+ (struct AMPDU_TID_st *)file->private_data; -+ memset(&du_tid->mib, 0, sizeof(struct AMPDU_MIB_st)); -+ return count; -+} -+ -+static const struct file_operations mib_reset_fops -+ = {.read = ampdu_tx_mib_reset_read, -+ .open = ampdu_tx_mib_reset_open, -+ .write = ampdu_tx_mib_reset_write -+}; -+ -+static void ssv6200_ampdu_tx_init_debugfs(struct ssv_softc *sc, -+ struct ssv_sta_priv_data -+ *ssv_sta_priv) -+{ -+ struct ssv_sta_info *sta_info = ssv_sta_priv->sta_info; -+ int i; -+ struct dentry *sta_debugfs_dir = sta_info->debugfs_dir; -+ dev_info(sc->dev, "Creating AMPDU TX debugfs.\n"); -+ if (sta_debugfs_dir == NULL) { -+ dev_err(sc->dev, "No STA debugfs.\n"); -+ return; -+ } -+ debugfs_create_file("ampdu_tx_summary", 00444, sta_debugfs_dir, -+ ssv_sta_priv, &mib_summary_fops); -+ debugfs_create_u32("total_BA", 00644, sta_debugfs_dir, -+ &ssv_sta_priv->ampdu_mib_total_BA_counter); -+ for (i = 0; i < WMM_TID_NUM; i++) { -+ char debugfs_name[20]; -+ struct dentry *ampdu_tx_debugfs_dir; -+ int j; -+ struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i]; -+ struct AMPDU_MIB_st *ampdu_mib = &du_tid->mib; -+ snprintf(debugfs_name, sizeof(debugfs_name), "ampdu_tx_%d", i); -+ ampdu_tx_debugfs_dir = debugfs_create_dir(debugfs_name, -+ sta_debugfs_dir); -+ if (ampdu_tx_debugfs_dir == NULL) { -+ dev_err(sc->dev, -+ "Failed to create debugfs for AMPDU TX TID %d: %s\n", -+ i, debugfs_name); -+ continue; -+ } -+ ssv_sta_priv->ampdu_tid[i].debugfs_dir = ampdu_tx_debugfs_dir; -+ debugfs_create_file("baw_status", 00444, ampdu_tx_debugfs_dir, -+ ampdu_tid, &tid_window_fops); -+ debugfs_create_file("reset", 00644, ampdu_tx_debugfs_dir, -+ ampdu_tid, &mib_reset_fops); -+ debugfs_create_u32("total", 00444, ampdu_tx_debugfs_dir, -+ &du_mib->ampdu_mib_ampdu_counter); -+ debugfs_create_u32("retry", 00444, ampdu_tx_debugfs_dir, -+ &du_mib->ampdu_mib_retry_counter); -+ debugfs_create_u32("aggr_retry", 00444, ampdu_tx_debugfs_dir, -+ &du_mib->ampdu_mib_aggr_retry_counter); -+ debugfs_create_u32("BAR", 00444, ampdu_tx_debugfs_dir, -+ &du_mib->ampdu_mib_bar_counter); -+ debugfs_create_u32("Discarded", 00444, ampdu_tx_debugfs_dir, -+ &du_mib->ampdu_mib_discard_counter); -+ debugfs_create_u32("BA", 00444, ampdu_tx_debugfs_dir, -+ &du_mib->ampdu_mib_BA_counter); -+ debugfs_create_u32("Pass", 00444, ampdu_tx_debugfs_dir, -+ &du_mib->ampdu_mib_pass_counter); -+ for (j = 0; j <= SSV_AMPDU_aggr_num_max; j++) { -+ char dist_dbg_name[10]; -+ snprintf(dist_dbg_name, sizeof(dist_dbg_name), -+ "aggr_%d", j); -+ debugfs_create_u32(dist_dbg_name, 00444, -+ ampdu_tx_debugfs_dir, -+ &du_mib->ampdu_mib_dist[j]); -+ } -+ skb_queue_head_init(&ssv_sta_priv->ampdu_tid[i].ba_q); -+ } -+} -+#endif -+void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw, -+ struct ieee80211_sta *sta) -+{ -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ struct ssv_softc *sc; -+ u32 temp_i; -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ sc = (struct ssv_softc *)hw->priv; -+ for (temp_i = 0; temp_i < WMM_TID_NUM; temp_i++) { -+ ssv_sta_priv->ampdu_tid[temp_i].sta = sta; -+ ssv_sta_priv->ampdu_tid[temp_i].state = AMPDU_STATE_STOP; -+ spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i]. -+ ampdu_skb_tx_queue_lock); -+ spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].pkt_array_lock); -+ } -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ ssv6200_ampdu_tx_init_debugfs(sc, ssv_sta_priv); -+#endif -+} -+ -+void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta, -+ struct ieee80211_hw *hw, u16 * ssn) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ struct AMPDU_TID_st *ampdu_tid; -+ int i; -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ ampdu_tid = &ssv_sta_priv->ampdu_tid[tid]; -+ ampdu_tid->ssv_baw_head = SSV_ILLEGAL_SN; -+#ifdef DEBUG_AMPDU_FLUSH -+ pr_debug("Adding %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n", -+ sta->addr[0], sta->addr[1], sta->addr[2], -+ sta->addr[3], sta->addr[4], sta->addr[5], -+ ampdu_tid->tidno, ampdu_tid); -+ { -+ int j; -+ for (j = 0; j <= MAX_TID; j++) { -+ if (sc->tid[j] == 0) -+ break; -+ } -+ if (j == MAX_TID) { -+ dev_err(sc->dev, "No room for new TID.\n"); -+ } else -+ sc->tid[j] = ampdu_tid; -+ } -+#endif -+ list_add_tail_rcu(&du_tid->list, &sc->tx.ampdu_tx_que); -+ skb_queue_head_init(&du_tid->ampdu_skb_tx_queue); -+ skb_queue_head_init(&du_tid->early_aggr_ampdu_q); -+ ampdu_tid->early_aggr_skb_num = 0; -+ skb_queue_head_init(&du_tid->ampdu_skb_wait_encry_queue); -+ skb_queue_head_init(&du_tid->retry_queue); -+ skb_queue_head_init(&du_tid->release_queue); -+ for (i = 0; -+ i < -+ (sizeof(ampdu_tid->aggr_pkts) / sizeof(ampdu_tid->aggr_pkts[0])); -+ i++) -+ ampdu_tid->aggr_pkts[i] = 0; -+ ampdu_tid->aggr_pkt_num = 0; -+ ampdu_tid->cur_ampdu_pkt = _alloc_ampdu_skb(sc, ampdu_tid, 0); -+#ifdef AMPDU_CHECK_SKB_SEQNO -+ ssv_sta_priv->ampdu_tid[tid].last_seqno = (-1); -+#endif -+ ssv_sta_priv->ampdu_mib_total_BA_counter = 0; -+ memset(&ssv_sta_priv->ampdu_tid[tid].mib, 0, -+ sizeof(struct AMPDU_MIB_st)); -+ ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_START; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ skb_queue_head_init(&ssv_sta_priv->ampdu_tid[tid].ba_q); -+#endif -+} -+ -+void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta, -+ struct ieee80211_hw *hw, u8 buffer_size) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ ssv_sta_priv->ampdu_tid[tid].tidno = tid; -+ ssv_sta_priv->ampdu_tid[tid].sta = sta; -+ ssv_sta_priv->ampdu_tid[tid].agg_num_max = MAX_AGGR_NUM; -+ if (buffer_size > IEEE80211_MAX_AMPDU_BUF) { -+ buffer_size = IEEE80211_MAX_AMPDU_BUF; -+ } -+ dev_info(sc->dev, "AMPDU buffer_size=%d\n", buffer_size); -+ ssv_sta_priv->ampdu_tid[tid].ssv_baw_size = SSV_AMPDU_WINDOW_SIZE; -+ ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_OPERATION; -+} -+ -+static void _clear_mpdu_q(struct ieee80211_hw *hw, struct sk_buff_head *q, -+ bool aggregated_mpdu) -+{ -+ struct sk_buff *skb; -+ while (1) { -+ skb = skb_dequeue(q); -+ if (!skb) -+ break; -+ if (aggregated_mpdu) -+ skb_pull(skb, AMPDU_DELIMITER_LEN); -+ ieee80211_tx_status_skb(hw, skb); -+ } -+} -+ -+void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta, -+ struct ieee80211_hw *hw) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ if (ssv_sta_priv->ampdu_tid[tid].state == AMPDU_STATE_STOP) -+ return; -+ ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_STOP; -+ dev_dbg(sc->dev, "ssv6200_ampdu_tx_stop\n"); -+ if (!list_empty(&sc->tx.ampdu_tx_que)) { -+#ifdef DEBUG_AMPDU_FLUSH -+ { -+ int j; -+ struct AMPDU_TID_st *ampdu_tid = -+ &ssv_sta_priv->ampdu_tid[tid]; -+ for (j = 0; j <= MAX_TID; j++) { -+ if (sc->tid[j] == ampdu_tid) -+ break; -+ } -+ if (j == MAX_TID) { -+ dev_dbg(sc->dev, "No TID found when deleting it.\n"); -+ } else -+ sc->tid[j] = NULL; -+ dev_dbg(sc->dev, "Deleting %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n", -+ sta->addr[0], sta->addr[1], sta->addr[2], -+ sta->addr[3], sta->addr[4], sta->addr[5], -+ ampdu_tid->tidno, ampdu_tid); -+ } -+#endif -+ list_del_rcu(&ssv_sta_priv->ampdu_tid[tid].list); -+ } -+ dev_dbg(sc->dev, "clear tx q len=%d\n", -+ skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue)); -+ _clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue, -+ true); -+ dev_dbg(sc->dev, "clear retry q len=%d\n", -+ skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].retry_queue)); -+ _clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].retry_queue, true); -+#ifdef USE_ENCRYPT_WORK -+ dev_dbg(sc->dev, "clear encrypt q len=%d\n", -+ skb_queue_len(&ssv_sta_priv->ampdu_tid[tid]. -+ ampdu_skb_wait_encry_queue)); -+ _clear_mpdu_q(sc->hw, -+ &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_wait_encry_queue, -+ false); -+#endif -+ if (ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt != NULL) { -+ dev_kfree_skb_any(ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt); -+ ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt = NULL; -+ } -+ ssv6200_tx_flow_control((void *)sc, -+ sc->tx.hw_txqid[ssv_sta_priv->ampdu_tid[tid]. -+ ac], false, 1000); -+} -+ -+static void ssv6200_ampdu_tx_state_stop_func(struct ssv_softc *sc, -+ struct ieee80211_sta *sta, -+ struct sk_buff *skb, -+ struct AMPDU_TID_st *cur_AMPDU_TID) -+{ -+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; -+ u8 *skb_qos_ctl = ieee80211_get_qos_ctl(hdr); -+ u8 tid_no = skb_qos_ctl[0] & 0xf; -+ if ((sta->deflink.ht_cap.ht_supported == true) -+ && (!!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) { -+ ieee80211_start_tx_ba_session(sta, tid_no, 0); -+ ampdu_db_log("start ampdu_tx(rc) : tid_no = %d\n", tid_no); -+ } -+} -+ -+static void ssv6200_ampdu_tx_state_operation_func(struct ssv_softc *sc, -+ struct ieee80211_sta *sta, -+ struct sk_buff *skb, -+ struct AMPDU_TID_st -+ *cur_AMPDU_TID) -+{ -+} -+ -+void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta, -+ struct sk_buff *skb) -+{ -+ struct ssv_softc *sc = (struct ssv_softc *)priv; -+ struct ssv_sta_priv_data *ssv_sta_priv = -+ (struct ssv_sta_priv_data *)sta->drv_priv; -+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; -+ u8 *skb_qos_ctl; -+ u8 tid_no; -+ { -+ skb_qos_ctl = ieee80211_get_qos_ctl(hdr); -+ tid_no = skb_qos_ctl[0] & 0xf; -+ switch (ssv_sta_priv->ampdu_tid[tid_no].state) { -+ case AMPDU_STATE_STOP: -+ ssv6200_ampdu_tx_state_stop_func(sc, sta, skb, -+ &(ssv_sta_priv-> -+ ampdu_tid[tid_no])); -+ break; -+ case AMPDU_STATE_START: -+ break; -+ case AMPDU_STATE_OPERATION: -+ ssv6200_ampdu_tx_state_operation_func(sc, sta, skb, -+ &(ssv_sta_priv-> -+ ampdu_tid -+ [tid_no])); -+ break; -+ default: -+ break; -+ } -+ } -+} -+ -+void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu) -+{ -+ bool is_empty_ampdu = (ampdu->len == 0); -+ unsigned char *data_dest; -+ struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head; -+ BUG_ON(skb_tailroom(ampdu) < mpdu->len); -+ data_dest = skb_tail_pointer(ampdu); -+ skb_put(ampdu, mpdu->len); -+ if (is_empty_ampdu) { -+ struct ieee80211_tx_info *ampdu_info = IEEE80211_SKB_CB(ampdu); -+ struct ieee80211_tx_info *mpdu_info = IEEE80211_SKB_CB(mpdu); -+ SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head); -+ u32 max_size_for_rate = -+ ampdu_max_transmit_length[mpdu_skb_info->lowest_rate]; -+ BUG_ON(max_size_for_rate == 0); -+ memcpy(ampdu_info, mpdu_info, sizeof(struct ieee80211_tx_info)); -+ skb_set_queue_mapping(ampdu, skb_get_queue_mapping(mpdu)); -+ ampdu_hdr->first_sn = ampdu_skb_ssn(mpdu); -+ ampdu_hdr->sta = ((struct SKB_info_st *)mpdu->head)->sta; -+ if (ampdu_hdr->max_size > max_size_for_rate) -+ ampdu_hdr->max_size = max_size_for_rate; -+ memcpy(ampdu_hdr->rates, mpdu_skb_info->rates, -+ sizeof(ampdu_hdr->rates)); -+ } -+ memcpy(data_dest, mpdu->data, mpdu->len); -+ __skb_queue_tail(&du_hdr->mpdu_q, mpdu); -+ ampdu_hdr->ssn[ampdu_hdr->mpdu_num++] = ampdu_skb_ssn(mpdu); -+ ampdu_hdr->size += mpdu->len; -+ BUG_ON(ampdu_hdr->size > ampdu_hdr->max_size); -+} -+ -+u32 _flush_early_ampdu_q(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid) -+{ -+ u32 flushed_ampdu = 0; -+ unsigned long flags; -+ struct sk_buff_head *early_aggr_ampdu_q = -+ &du_tid->early_aggr_ampdu_q; -+ spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags); -+ while (skb_queue_len(early_aggr_ampdu_q)) { -+ struct sk_buff *head_ampdu; -+ struct ampdu_hdr_st *head_ampdu_hdr; -+ u32 ampdu_aggr_num; -+ head_ampdu = skb_peek(early_aggr_ampdu_q); -+ head_ampdu_hdr = (struct ampdu_hdr_st *)head_ampdu->head; -+ ampdu_aggr_num = skb_queue_len(&head_ampdu_hdr->mpdu_q); -+ if ((SSV_AMPDU_BA_WINDOW_SIZE - ampdu_tid->aggr_pkt_num) -+ < ampdu_aggr_num) -+ break; -+ if (_sync_ampdu_pkt_arr(ampdu_tid, head_ampdu, false)) { -+ head_ampdu = __skb_dequeue(early_aggr_ampdu_q); -+ ampdu_tid->early_aggr_skb_num -= ampdu_aggr_num; -+#ifdef SSV_AMPDU_FLOW_CONTROL -+ if (ampdu_tid->early_aggr_skb_num -+ <= SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND) { -+ ssv6200_tx_flow_control((void *)sc, -+ sc->tx. -+ hw_txqid[ampdu_tid->ac], -+ false, 1000); -+ } -+#endif -+ if ((skb_queue_len(early_aggr_ampdu_q) == 0) -+ && (ampdu_tid->early_aggr_skb_num > 0)) { -+ dev_warn(sc->dev, "Empty early Q w. %d.\n", -+ ampdu_tid->early_aggr_skb_num); -+ } -+ spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, -+ flags); -+ _send_hci_skb(sc, head_ampdu, -+ AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL); -+ spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags); -+ flushed_ampdu++; -+ } else -+ break; -+ } -+ spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags); -+ return flushed_ampdu; -+} -+ -+volatile int max_aggr_num = 24; -+void _aggr_ampdu_tx_q(struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct sk_buff *ampdu_skb = ampdu_tid->cur_ampdu_pkt; -+ while (skb_queue_len(&du_tid->ampdu_skb_tx_queue)) { -+ u32 aggr_len; -+ struct sk_buff *mpdu_skb; -+ struct ampdu_hdr_st *ampdu_hdr; -+ bool is_aggr_full = false; -+ if (ampdu_skb == NULL) { -+ ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, 0); -+ if (ampdu_skb == NULL) -+ break; -+ ampdu_tid->cur_ampdu_pkt = ampdu_skb; -+ } -+ ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head; -+ aggr_len = skb_queue_len(&du_hdr->mpdu_q); -+ do { -+ struct sk_buff_head *tx_q = -+ &du_tid->ampdu_skb_tx_queue; -+ unsigned long flags; -+ spin_lock_irqsave(&tx_q->lock, flags); -+ mpdu_skb = skb_peek(&du_tid->ampdu_skb_tx_queue); -+ if (mpdu_skb == NULL) { -+ spin_unlock_irqrestore(&tx_q->lock, flags); -+ break; -+ } -+ if ((mpdu_skb->len + ampdu_hdr->size) > -+ ampdu_hdr->max_size) { -+ is_aggr_full = true; -+ spin_unlock_irqrestore(&tx_q->lock, flags); -+ break; -+ } -+ mpdu_skb = -+ __skb_dequeue(&du_tid->ampdu_skb_tx_queue); -+ spin_unlock_irqrestore(&tx_q->lock, flags); -+ _put_mpdu_to_ampdu(ampdu_skb, mpdu_skb); -+ } while (++aggr_len < max_aggr_num); -+ if ((is_aggr_full || (aggr_len >= max_aggr_num)) -+ || ((aggr_len > 0) -+ && (skb_queue_len(&du_tid->early_aggr_ampdu_q) == 0) -+ && (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN) -+ && _is_skb_q_empty(sc, ampdu_skb))) { -+ _add_ampdu_txinfo(sc, ampdu_skb); -+ _queue_early_ampdu(sc, ampdu_tid, ampdu_skb); -+ ampdu_tid->cur_ampdu_pkt = ampdu_skb = NULL; -+ } -+ _flush_early_ampdu_q(sc, ampdu_tid); -+ } -+} -+ -+void _queue_early_ampdu(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid, -+ struct sk_buff *ampdu_skb) -+{ -+ unsigned long flags; -+ struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head; -+ spin_lock_irqsave(&du_tid->early_aggr_ampdu_q.lock, flags); -+ __skb_queue_tail(&du_tid->early_aggr_ampdu_q, ampdu_skb); -+ ampdu_tid->early_aggr_skb_num += skb_queue_len(&du_hdr->mpdu_q); -+#ifdef SSV_AMPDU_FLOW_CONTROL -+ if (ampdu_tid->early_aggr_skb_num >= SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND) { -+ ssv6200_tx_flow_control((void *)sc, -+ sc->tx.hw_txqid[ampdu_tid->ac], true, -+ 1000); -+ } -+#endif -+ spin_unlock_irqrestore(&du_tid->early_aggr_ampdu_q.lock, flags); -+} -+ -+void _flush_mpdu(struct ssv_softc *sc, struct ieee80211_sta *sta) -+{ -+ unsigned long flags; -+ struct ssv_sta_priv_data *ssv_sta_priv = -+ (struct ssv_sta_priv_data *)sta->drv_priv; -+ int i; -+ for (i = 0; -+ i < -+ (sizeof(ssv_sta_priv->ampdu_tid) / -+ sizeof(ssv_sta_priv->ampdu_tid[0])); i++) { -+ struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i]; -+ struct sk_buff_head *early_aggr_ampdu_q; -+ struct sk_buff *ampdu; -+ struct ampdu_hdr_st *ampdu_hdr; -+ struct sk_buff_head *mpdu_q; -+ struct sk_buff *mpdu; -+ if (ampdu_tid->state != AMPDU_STATE_OPERATION) -+ continue; -+ early_aggr_ampdu_q = &du_tid->early_aggr_ampdu_q; -+ spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags); -+ while ((ampdu = __skb_dequeue(early_aggr_ampdu_q)) != NULL) { -+ ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head; -+ mpdu_q = &du_hdr->mpdu_q; -+ spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, -+ flags); -+ while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) { -+ _send_hci_skb(sc, mpdu, -+ AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL); -+ } -+ ssv6200_ampdu_release_skb(ampdu, sc->hw); -+ spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags); -+ } -+ if (ampdu_tid->cur_ampdu_pkt != NULL) { -+ ampdu_hdr = -+ (struct ampdu_hdr_st *)ampdu_tid->cur_ampdu_pkt-> -+ head; -+ mpdu_q = &du_hdr->mpdu_q; -+ spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, -+ flags); -+ while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) { -+ _send_hci_skb(sc, mpdu, -+ AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL); -+ } -+ ssv6200_ampdu_release_skb(ampdu_tid->cur_ampdu_pkt, -+ sc->hw); -+ spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags); -+ ampdu_tid->cur_ampdu_pkt = NULL; -+ } -+ spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags); -+ } -+} -+ -+bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; -+#ifdef REPORT_TX_STATUS_DIRECTLY -+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); -+ struct sk_buff *tx_skb = skb; -+ struct sk_buff *copy_skb = NULL; -+#endif -+ struct SKB_info_st *mpdu_skb_info_p = (SKB_info *) (skb->head); -+ struct ieee80211_sta *sta = mpdu_skb_info_p->sta; -+ struct ssv_sta_priv_data *ssv_sta_priv = -+ (struct ssv_sta_priv_data *)sta->drv_priv; -+ u8 tidno; -+ struct AMPDU_TID_st *ampdu_tid; -+ if (sta == NULL) { -+ WARN_ON(1); -+ return false; -+ } -+ tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; -+ ampdu_db_log("tidno = %d\n", tidno); -+ ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno]; -+ if (ampdu_tid->state != AMPDU_STATE_OPERATION) -+ return false; -+#ifdef AMPDU_CHECK_SKB_SEQNO -+ { -+ u32 skb_seqno = ((struct ieee80211_hdr *)(skb->data))->seq_ctrl -+ >> SSV_SEQ_NUM_SHIFT; -+ u32 tid_seqno = ampdu_tid->last_seqno; -+ if ((tid_seqno != (-1)) -+ && (skb_seqno != NEXT_PKT_SN(tid_seqno))) { -+ prn_aggr_err("Non continueous seq no: %d - %d\n", -+ tid_seqno, skb_seqno); -+ return false; -+ } -+ ampdu_tid->last_seqno = skb_seqno; -+ } -+#endif -+ mpdu_skb_info_p->lowest_rate = -+ ssv62xx_ht_rate_update(skb, sc, mpdu_skb_info_p->rates); -+ if (ampdu_max_transmit_length[mpdu_skb_info_p->lowest_rate] == 0) { -+ _flush_mpdu(sc, sta); -+ return false; -+ } -+ mpdu_skb_info_p = (SKB_info *) (skb->head); -+ mpdu_skb_info_p->mpdu_retry_counter = 0; -+ mpdu_skb_info_p->ampdu_tx_status = AMPDU_ST_NON_AMPDU; -+ mpdu_skb_info_p->ampdu_tx_final_retry_count = 0; -+ ssv_sta_priv->ampdu_tid[tidno].ac = skb_get_queue_mapping(skb); -+#ifdef REPORT_TX_STATUS_DIRECTLY -+ info->flags |= IEEE80211_TX_STAT_ACK; -+ copy_skb = skb_copy(tx_skb, GFP_ATOMIC); -+ if (!copy_skb) { -+ dev_err(sc->dev, "create TX skb copy failed!\n"); -+ return false; -+ } -+ ieee80211_tx_status_skb(sc->hw, tx_skb); -+ skb = copy_skb; -+#endif -+ { -+ bool ret; -+ ret = ssv6200_ampdu_add_delimiter_and_crc32(skb); -+ if (ret == false) { -+ ssv6200_ampdu_release_skb(skb, hw); -+ return false; -+ } -+ skb_queue_tail(&ssv_sta_priv->ampdu_tid[tidno]. -+ ampdu_skb_tx_queue, skb); -+ ssv_sta_priv->ampdu_tid[tidno].timestamp = jiffies; -+ } -+ _aggr_ampdu_tx_q(hw, &ssv_sta_priv->ampdu_tid[tidno]); -+ return true; -+} -+ -+u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct AMPDU_TID_st *cur_AMPDU_TID; -+ u32 flushed_ampdu = 0; -+ u32 tid_idx = 0; -+ if (!list_empty(&sc->tx.ampdu_tx_que)) { -+ list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que, -+ list) { -+ tid_idx++; -+#ifdef DEBUG_AMPDU_FLUSH -+ { -+ int i = 0; -+ for (i = 0; i < MAX_TID; i++) -+ if (sc->tid[i] == cur_AMPDU_TID) -+ break; -+ if (i == MAX_TID) { -+ dev_err(sc->dev, "No matching TID (%d) found! %p\n", -+ tid_idx, cur_AMPDU_TID); -+ continue; -+ } -+ } -+#endif -+ if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION) { -+ struct ieee80211_sta *sta = cur_AMPDU_TID->sta; -+ struct ssv_sta_priv_data *sta_priv = -+ (struct ssv_sta_priv_data *)sta->drv_priv; -+ dev_dbg(sc->dev, "STA %d TID %d is @%d\n", -+ sta_priv->sta_idx, cur_AMPDU_TID->tidno, -+ cur_AMPDU_TID->state); -+ continue; -+ } -+ if ((cur_AMPDU_TID->state == AMPDU_STATE_OPERATION) -+ && -+ (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q) -+ == 0) -+ && (cur_AMPDU_TID->cur_ampdu_pkt != NULL)) { -+ struct ampdu_hdr_st *ampdu_hdr = -+ (struct ampdu_hdr_st *)(cur_AMPDU_TID-> -+ cur_ampdu_pkt-> -+ head); -+ u32 aggr_len = -+ skb_queue_len(&du_hdr->mpdu_q); -+ if (aggr_len) { -+ struct sk_buff *ampdu_skb = -+ cur_AMPDU_TID->cur_ampdu_pkt; -+ cur_AMPDU_TID->cur_ampdu_pkt = NULL; -+ _add_ampdu_txinfo(sc, ampdu_skb); -+ _queue_early_ampdu(sc, cur_AMPDU_TID, -+ ampdu_skb); -+ } -+ } -+ if (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q) > -+ 0) -+ flushed_ampdu += -+ _flush_early_ampdu_q(sc, cur_AMPDU_TID); -+ } -+ } -+ return flushed_ampdu; -+} -+ -+int _dump_BA_notification(char *buf, -+ struct ampdu_ba_notify_data *ba_notification) -+{ -+ int i; -+ char *orig_buf = buf; -+ for (i = 0; i < MAX_AGGR_NUM; i++) { -+ if (ba_notification->seq_no[i] == (u16) (-1)) -+ break; -+ buf += sprintf(buf, " %d", ba_notification->seq_no[i]); -+ } -+ return ((size_t)buf - (size_t)orig_buf); -+} -+ -+int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb) -+{ -+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(ba_skb->data -+ + -+ SSV6XXX_RX_DESC_LEN); -+ AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr; -+ u32 ssn = BA_frame->BA_ssn; -+ struct ampdu_ba_notify_data *ba_notification = -+ (struct ampdu_ba_notify_data *)(ba_skb->data + ba_skb->len -+ - -+ sizeof(struct -+ ampdu_ba_notify_data)); -+ int prt_size; -+ prt_size = snprintf(buf, buf_size, "\n\t\t%04d %08X %08X -", -+ ssn, BA_frame->BA_sn_bit_map[0], -+ BA_frame->BA_sn_bit_map[1]); -+ buf_size -= prt_size; -+ buf += prt_size; -+ prt_size = prt_size + _dump_BA_notification(buf, ba_notification); -+ return prt_size; -+} -+ -+static bool _ssn_to_bit_idx(u32 start_ssn, u32 mpdu_ssn, u32 * word_idx, -+ u32 * bit_idx) -+{ -+ u32 ret_bit_idx, ret_word_idx = 0; -+ s32 diff = mpdu_ssn - start_ssn; -+ if (diff >= 0) { -+ if (diff >= SSV_AMPDU_BA_WINDOW_SIZE) { -+ return false; -+ } -+ ret_bit_idx = diff; -+ } else { -+ diff = -diff; -+ if (diff <= (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) { -+ *word_idx = 0; -+ *bit_idx = 0; -+ return false; -+ } -+ ret_bit_idx = SSV_AMPDU_MAX_SSN - diff; -+ } -+ if (ret_bit_idx >= 32) { -+ ret_bit_idx -= 32; -+ ret_word_idx = 1; -+ } -+ *bit_idx = ret_bit_idx; -+ *word_idx = ret_word_idx; -+ return true; -+} -+ -+static bool _inc_bit_idx(u32 ssn_1st, u32 ssn_next, u32 * word_idx, -+ u32 * bit_idx) -+{ -+ u32 ret_word_idx = *word_idx, ret_bit_idx = *bit_idx; -+ s32 diff = (s32) ssn_1st - (s32) ssn_next; -+ if (diff > 0) { -+ if (diff < (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) { -+ prn_aggr_err -+ ("Irrational SN distance in AMPDU: %d %d.\n", -+ ssn_1st, ssn_next); -+ return false; -+ } -+ diff = SSV_AMPDU_MAX_SSN - diff; -+ } else { -+ diff = -diff; -+ } -+ if (diff > SSV_AMPDU_MAX_SSN) -+ prn_aggr_err("DF %d - %d = %d\n", ssn_1st, ssn_next, diff); -+ ret_bit_idx += diff; -+ if (ret_bit_idx >= 32) { -+ ret_bit_idx -= 32; -+ ret_word_idx++; -+ } -+ *word_idx = ret_word_idx; -+ *bit_idx = ret_bit_idx; -+ return true; -+} -+ -+static void _release_frames(struct AMPDU_TID_st *ampdu_tid) -+{ -+ u32 head_ssn, head_ssn_before, last_ssn; -+ struct sk_buff **skb; -+ struct SKB_info_st *skb_info; -+ spin_lock_bh(&du_tid->pkt_array_lock); -+ head_ssn_before = ampdu_tid->ssv_baw_head; -+ if (head_ssn_before >= SSV_AMPDU_MAX_SSN) { -+ spin_unlock_bh(&du_tid->pkt_array_lock); -+ prn_aggr_err("l x.x %d\n", head_ssn_before); -+ return; -+ } -+ head_ssn = ampdu_tid->ssv_baw_head; -+ last_ssn = head_ssn; -+ do { -+ skb = &INDEX_PKT_BY_SSN(ampdu_tid, head_ssn); -+ if (*skb == NULL) { -+ head_ssn = SSV_ILLEGAL_SN; -+ { -+ int i; -+ char sn_str[66 * 5] = ""; -+ char *str = sn_str; -+ for (i = 0; i < 64; i++) -+ if (ampdu_tid->aggr_pkts[i] != NULL) { -+ str += sprintf(str, "%d ", -+ ampdu_skb_ssn -+ (ampdu_tid-> -+ aggr_pkts[i])); -+ } -+ *str = 0; -+ if (str == sn_str) { -+ } else -+ prn_aggr_err("ILL %d %d - %d (%s)\n", -+ head_ssn_before, last_ssn, -+ ampdu_tid->aggr_pkt_num, -+ sn_str); -+ } -+ break; -+ } -+ skb_info = (struct SKB_info_st *)((*skb)->head); -+ if ((skb_info->ampdu_tx_status == AMPDU_ST_DONE) -+ || (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)) { -+ __skb_queue_tail(&du_tid->release_queue, *skb); -+ *skb = NULL; -+ last_ssn = head_ssn; -+ INC_PKT_SN(head_ssn); -+ ampdu_tid->aggr_pkt_num--; -+ if (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED) -+ ampdu_tid->mib.ampdu_mib_discard_counter++; -+ } else { -+ break; -+ } -+ } while (1); -+ ampdu_tid->ssv_baw_head = head_ssn; -+ spin_unlock_bh(&du_tid->pkt_array_lock); -+} -+ -+static int _collect_retry_frames(struct AMPDU_TID_st *ampdu_tid) -+{ -+ u16 ssn, head_ssn, end_ssn; -+ int num_retry = 0; -+ int timeout_check = 1; -+ unsigned long check_jiffies = jiffies; -+ head_ssn = ampdu_tid->ssv_baw_head; -+ ssn = head_ssn; -+ if (ssn == SSV_ILLEGAL_SN) -+ return 0; -+ end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN; -+ do { -+ struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn); -+ struct SKB_info_st *skb_info; -+ int timeout_retry = 0; -+ if (skb == NULL) -+ break; -+ skb_info = (SKB_info *) (skb->head); -+ if (timeout_check -+ && (skb_info->ampdu_tx_status == AMPDU_ST_SENT)) { -+ unsigned long cur_jiffies = jiffies; -+ unsigned long timeout_jiffies = skb_info->aggr_timestamp -+ + msecs_to_jiffies(BA_WAIT_TIMEOUT); -+ u32 delta_ms; -+ if (time_before(cur_jiffies, timeout_jiffies)) { -+ timeout_check = 0; -+ continue; -+ } -+ _mark_skb_retry(skb_info, skb); -+ delta_ms = -+ jiffies_to_msecs(cur_jiffies - -+ skb_info->aggr_timestamp); -+ prn_aggr_err("t S%d-T%d-%d (%u)\n", -+ ((struct ssv_sta_priv_data *)skb_info-> -+ sta->drv_priv)->sta_idx, ampdu_tid->tidno, -+ ssn, delta_ms); -+ if (delta_ms > 1000) { -+ prn_aggr_err("Last checktime %lu - %lu = %u\n", -+ check_jiffies, -+ ampdu_tid->timestamp, -+ jiffies_to_msecs(check_jiffies - -+ ampdu_tid-> -+ timestamp)); -+ } -+ timeout_retry = 1; -+ } -+ if (skb_info->ampdu_tx_status == AMPDU_ST_RETRY) { -+ skb_queue_tail(&du_tid->retry_queue, skb); -+ ampdu_tid->mib.ampdu_mib_retry_counter++; -+ num_retry++; -+ } -+ INC_PKT_SN(ssn); -+ } while (ssn != end_ssn); -+ ampdu_tid->timestamp = check_jiffies; -+ return num_retry; -+} -+ -+int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb) -+{ -+ if (skb_info->mpdu_retry_counter < SSV_AMPDU_retry_counter_max) { -+ if (skb_info->mpdu_retry_counter == 0) { -+ struct ieee80211_hdr *skb_hdr = ampdu_skb_hdr(skb); -+ skb_hdr->frame_control |= -+ cpu_to_le16(IEEE80211_FCTL_RETRY); -+ } -+ skb_info->ampdu_tx_status = AMPDU_ST_RETRY; -+ skb_info->mpdu_retry_counter++; -+ return 1; -+ } else { -+ skb_info->ampdu_tx_status = AMPDU_ST_DROPPED; -+ prn_aggr_err("p %d\n", ampdu_skb_ssn(skb)); -+ return 0; -+ } -+} -+ -+static u32 _ba_map_walker(struct AMPDU_TID_st *ampdu_tid, u32 start_ssn, -+ u32 sn_bit_map[2], -+ struct ampdu_ba_notify_data *ba_notify_data, -+ u32 * p_acked_num) -+{ -+ int i = 0; -+ u32 ssn = ba_notify_data->seq_no[0]; -+ u32 word_idx = (-1), bit_idx = (-1); -+ bool found = _ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx); -+ bool first_found = found; -+ u32 aggr_num = 0; -+ u32 acked_num = 0; -+ if (found && (word_idx >= 2 || bit_idx >= 32)) -+ prn_aggr_err("idx error 1: %d %d %d %d\n", -+ start_ssn, ssn, word_idx, bit_idx); -+ while ((i < MAX_AGGR_NUM) && (ssn < SSV_AMPDU_MAX_SSN)) { -+ u32 cur_ssn; -+ struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn); -+ u32 skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb); -+ struct SKB_info_st *skb_info; -+ aggr_num++; -+ if (skb_ssn != ssn) { -+ prn_aggr_err("Unmatched SSN packet: %d - %d - %d\n", -+ ssn, skb_ssn, start_ssn); -+ } else { -+ skb_info = (struct SKB_info_st *)(skb->head); -+ if (found && (sn_bit_map[word_idx] & (1 << bit_idx))) { -+ if (skb_info->ampdu_tx_status != AMPDU_ST_SENT) { -+ pr_err("BA marks a MPDU of status %d!\n", -+ skb_info->ampdu_tx_status); -+ } -+ skb_info->ampdu_tx_status = AMPDU_ST_DONE; -+ acked_num++; -+ } else { -+ _mark_skb_retry(skb_info, skb); -+ } -+ } -+ cur_ssn = ssn; -+ if (++i >= MAX_AGGR_NUM) -+ break; -+ ssn = ba_notify_data->seq_no[i]; -+ if (ssn >= SSV_AMPDU_MAX_SSN) -+ break; -+ if (first_found) { -+ u32 old_word_idx = word_idx, old_bit_idx = bit_idx; -+ found = _inc_bit_idx(cur_ssn, ssn, &word_idx, &bit_idx); -+ if (found && (word_idx >= 2 || bit_idx >= 32)) { -+ prn_aggr_err -+ ("idx error 2: %d 0x%08X 0X%08X %d %d (%d %d) (%d %d)\n", -+ start_ssn, sn_bit_map[1], sn_bit_map[0], -+ cur_ssn, ssn, word_idx, bit_idx, -+ old_word_idx, old_bit_idx); -+ found = false; -+ } else if (!found) { -+ char strbuf[256]; -+ _dump_BA_notification(strbuf, ba_notify_data); -+ prn_aggr_err("SN out-of-order: %d\n%s\n", -+ start_ssn, strbuf); -+ } -+ } else { -+ found = -+ _ssn_to_bit_idx(start_ssn, ssn, &word_idx, -+ &bit_idx); -+ first_found = found; -+ if (found && (word_idx >= 2 || bit_idx >= 32)) -+ prn_aggr_err("idx error 3: %d %d %d %d\n", -+ cur_ssn, ssn, word_idx, bit_idx); -+ } -+ } -+ _release_frames(ampdu_tid); -+ if (p_acked_num != NULL) -+ *p_acked_num = acked_num; -+ return aggr_num; -+} -+ -+static void _flush_release_queue(struct ieee80211_hw *hw, -+ struct sk_buff_head *release_queue) -+{ -+ do { -+ struct sk_buff *ampdu_skb = __skb_dequeue(release_queue); -+ struct ieee80211_tx_info *tx_info; -+ struct SKB_info_st *skb_info; -+ if (ampdu_skb == NULL) -+ break; -+ skb_info = (struct SKB_info_st *)(ampdu_skb->head); -+ skb_pull(ampdu_skb, AMPDU_DELIMITER_LEN); -+ tx_info = IEEE80211_SKB_CB(ampdu_skb); -+ ieee80211_tx_info_clear_status(tx_info); -+ tx_info->flags |= IEEE80211_TX_STAT_AMPDU; -+ if (skb_info->ampdu_tx_status == AMPDU_ST_DONE) -+ tx_info->flags |= IEEE80211_TX_STAT_ACK; -+ tx_info->status.ampdu_len = 1; -+ tx_info->status.ampdu_ack_len = 1; -+#ifdef REPORT_TX_STATUS_DIRECTLY -+ dev_kfree_skb_any(ampdu_skb); -+#else -+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_TX_DATA) -+ ieee80211_tx_status_skb(hw, ampdu_skb); -+#else -+ ieee80211_tx_status_irqsafe(hw, ampdu_skb); -+#endif -+#endif -+ } while (1); -+} -+ -+void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb) -+{ -+ struct cfg_host_event *host_event = (struct cfg_host_event *)skb->data; -+ struct ampdu_ba_notify_data *ba_notification = -+ (struct ampdu_ba_notify_data *)&host_event->dat[0]; -+ struct ieee80211_hdr *hdr = -+ (struct ieee80211_hdr *)(ba_notification + 1); -+ struct ssv_softc *sc = hw->priv; -+ struct ieee80211_sta *sta = ssv6xxx_find_sta_by_addr(sc, hdr->addr1); -+ u8 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ char seq_str[256]; -+ struct AMPDU_TID_st *ampdu_tid; -+ int i; -+ u16 aggr_num = 0; -+ struct firmware_rate_control_report_data *report_data; -+ if (sta == NULL) { -+ prn_aggr_err -+ ("NO BA for %d to unmatched STA %02X-%02X-%02X-%02X-%02X-%02X: %s\n", -+ tidno, hdr->addr1[0], hdr->addr1[1], hdr->addr1[2], -+ hdr->addr1[3], hdr->addr1[4], hdr->addr1[5], seq_str); -+ dev_kfree_skb_any(skb); -+ return; -+ } -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ _dump_BA_notification(seq_str, ba_notification); -+ prn_aggr_err("NO BA for %d to %02X-%02X-%02X-%02X-%02X-%02X: %s\n", -+ tidno, sta->addr[0], sta->addr[1], sta->addr[2], -+ sta->addr[3], sta->addr[4], sta->addr[5], seq_str); -+ ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno]; -+ if (ampdu_tid->state != AMPDU_STATE_OPERATION) { -+ dev_kfree_skb_any(skb); -+ return; -+ } -+ for (i = 0; i < MAX_AGGR_NUM; i++) { -+ u32 ssn = ba_notification->seq_no[i]; -+ struct sk_buff *skb; -+ u32 skb_ssn; -+ struct SKB_info_st *skb_info; -+ if (ssn >= (4096)) -+ break; -+ aggr_num++; -+ skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn); -+ skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb); -+ if (skb_ssn != ssn) { -+ prn_aggr_err("Unmatched SSN packet: %d - %d\n", ssn, -+ skb_ssn); -+ continue; -+ } -+ skb_info = (struct SKB_info_st *)(skb->head); -+ if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) { -+ if (skb_info->mpdu_retry_counter < -+ SSV_AMPDU_retry_counter_max) { -+ if (skb_info->mpdu_retry_counter == 0) { -+ struct ieee80211_hdr *skb_hdr = -+ ampdu_skb_hdr(skb); -+ skb_hdr->frame_control |= -+ cpu_to_le16(IEEE80211_FCTL_RETRY); -+ } -+ skb_info->ampdu_tx_status = AMPDU_ST_RETRY; -+ skb_info->mpdu_retry_counter++; -+ } else { -+ skb_info->ampdu_tx_status = AMPDU_ST_DROPPED; -+ prn_aggr_err("p %d\n", skb_ssn); -+ } -+ } else { -+ prn_aggr_err("S %d %d\n", skb_ssn, -+ skb_info->ampdu_tx_status); -+ } -+ } -+ _release_frames(ampdu_tid); -+ host_event->h_event = SOC_EVT_RC_AMPDU_REPORT; -+ report_data = -+ (struct firmware_rate_control_report_data *)&host_event->dat[0]; -+ report_data->ampdu_len = aggr_num; -+ report_data->ampdu_ack_len = 0; -+ report_data->wsid = ssv_sta_priv->sta_info->hw_wsid; -+ skb_queue_tail(&sc->rc_report_queue, skb); -+ if (sc->rc_sample_sechedule == 0) -+ queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work); -+} -+ -+void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data -+ + -+ SSV6XXX_RX_DESC_LEN); -+ AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr; -+ struct ieee80211_sta *sta; -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ struct ampdu_ba_notify_data *ba_notification; -+ u32 ssn, aggr_num = 0, acked_num = 0; -+ u8 tid_no; -+ u32 sn_bit_map[2]; -+ struct firmware_rate_control_report_data *report_data; -+ HDR_HostEvent *host_evt; -+ sta = ssv6xxx_find_sta_by_rx_skb(sc, skb); -+ if (sta == NULL) { -+ if (skb->len > AMPDU_BA_FRAME_LEN) { -+ char strbuf[256]; -+ struct ampdu_ba_notify_data *ba_notification = -+ (struct ampdu_ba_notify_data *)(skb->data + skb->len -+ - -+ sizeof(struct -+ ampdu_ba_notify_data)); -+ _dump_BA_notification(strbuf, ba_notification); -+ prn_aggr_err -+ ("BA from not connected STA (%02X-%02X-%02X-%02X-%02X-%02X) (%s)\n", -+ BA_frame->ta_addr[0], BA_frame->ta_addr[1], -+ BA_frame->ta_addr[2], BA_frame->ta_addr[3], -+ BA_frame->ta_addr[4], BA_frame->ta_addr[5], -+ strbuf); -+ } -+ dev_kfree_skb_any(skb); -+ return; -+ } -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ ssn = BA_frame->BA_ssn; -+ sn_bit_map[0] = BA_frame->BA_sn_bit_map[0]; -+ sn_bit_map[1] = BA_frame->BA_sn_bit_map[1]; -+ tid_no = BA_frame->tid_info; -+ ssv_sta_priv->ampdu_mib_total_BA_counter++; -+ if (ssv_sta_priv->ampdu_tid[tid_no].state == AMPDU_STATE_STOP) { -+ prn_aggr_err -+ ("ssv6200_ampdu_BA_handler state == AMPDU_STATE_STOP.\n"); -+ dev_kfree_skb_any(skb); -+ return; -+ } -+ ssv_sta_priv->ampdu_tid[tid_no].mib.ampdu_mib_BA_counter++; -+ if (skb->len <= AMPDU_BA_FRAME_LEN) { -+ prn_aggr_err("b %d\n", ssn); -+ dev_kfree_skb_any(skb); -+ return; -+ } -+ ba_notification = -+ (struct ampdu_ba_notify_data *)(skb->data + skb->len -+ - -+ sizeof(struct -+ ampdu_ba_notify_data)); -+ aggr_num = -+ _ba_map_walker(&(ssv_sta_priv->ampdu_tid[tid_no]), ssn, sn_bit_map, -+ ba_notification, &acked_num); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (ssv_sta_priv->ampdu_tid[tid_no].debugfs_dir) { -+ struct sk_buff *dup_skb; -+ if (skb_queue_len(&ssv_sta_priv->ampdu_tid[tid_no].ba_q) > 24) { -+ struct sk_buff *ba_skb = -+ skb_dequeue(&ssv_sta_priv->ampdu_tid[tid_no].ba_q); -+ if (ba_skb) -+ dev_kfree_skb_any(ba_skb); -+ } -+ dup_skb = skb_clone(skb, GFP_ATOMIC); -+ if (dup_skb) -+ skb_queue_tail(&ssv_sta_priv->ampdu_tid[tid_no].ba_q, -+ dup_skb); -+ } -+#endif -+ skb_trim(skb, skb->len - sizeof(struct ampdu_ba_notify_data)); -+ host_evt = (HDR_HostEvent *) skb->data; -+ host_evt->h_event = SOC_EVT_RC_AMPDU_REPORT; -+ report_data = -+ (struct firmware_rate_control_report_data *)&host_evt->dat[0]; -+ memcpy(report_data, ba_notification, -+ sizeof(struct firmware_rate_control_report_data)); -+ report_data->ampdu_len = aggr_num; -+ report_data->ampdu_ack_len = acked_num; -+#ifdef RATE_CONTROL_HT_PERCENTAGE_TRACE -+ if ((acked_num) && (acked_num != aggr_num)) { -+ int i; -+ for (i = 0; i < SSV62XX_TX_MAX_RATES; i++) { -+ if (report_data->rates[i].data_rate == -1) -+ break; -+ if (report_data->rates[i].count == 0) -+ dev_err(sc->dev, "illegal HT report\n"); -+ -+ dev_dbg(sc->dev, "i=[%d] rate[%d] count[%d]\n", i, -+ report_data->rates[i].data_rate, -+ report_data->rates[i].count); -+ } -+ dev_dbg(sc->dev, "AMPDU percentage = %d%% \n", -+ acked_num * 100 / aggr_num); -+ } else if (acked_num == 0) { -+ dev_dbg(sc->dev, "AMPDU percentage = 0%% aggr_num=%d acked_num=%d\n", -+ aggr_num, acked_num); -+ } -+#endif -+ skb_queue_tail(&sc->rc_report_queue, skb); -+ if (sc->rc_sample_sechedule == 0) -+ queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work); -+} -+ -+static void _postprocess_BA(struct ssv_softc *sc, struct ssv_sta_info *sta_info, -+ void *param) -+{ -+ int j; -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ if ((sta_info->sta == NULL) -+ || ((sta_info->s_flags & STA_FLAG_VALID) == 0)) -+ return; -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv; -+ for (j = 0; j < WMM_TID_NUM; j++) { -+ AMPDU_TID *ampdu_tid = &ssv_sta_priv->ampdu_tid[j]; -+ if (ampdu_tid->state != AMPDU_STATE_OPERATION) -+ continue; -+ _collect_retry_frames(ampdu_tid); -+ ssv6200_ampdu_send_retry(sc->hw, ampdu_tid, -+ &du_tid->retry_queue, true); -+ _flush_early_ampdu_q(sc, ampdu_tid); -+ _flush_release_queue(sc->hw, &du_tid->release_queue); -+ } -+} -+ -+void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw) -+{ -+ struct ssv_softc *sc = hw->priv; -+ ssv6xxx_foreach_sta(sc, _postprocess_BA, NULL); -+} -+ -+static void ssv6200_hw_set_rx_ba_session(struct ssv_hw *sh, bool on, u8 * ta, -+ u16 tid, u16 ssn, u8 buf_size) -+{ -+ if (on) { -+ u32 u32ta; -+ u32ta = 0; -+ u32ta |= (ta[0] & 0xff) << (8 * 0); -+ u32ta |= (ta[1] & 0xff) << (8 * 1); -+ u32ta |= (ta[2] & 0xff) << (8 * 2); -+ u32ta |= (ta[3] & 0xff) << (8 * 3); -+ SMAC_REG_WRITE(sh, ADR_BA_TA_0, u32ta); -+ u32ta = 0; -+ u32ta |= (ta[4] & 0xff) << (8 * 0); -+ u32ta |= (ta[5] & 0xff) << (8 * 1); -+ SMAC_REG_WRITE(sh, ADR_BA_TA_1, u32ta); -+ SMAC_REG_WRITE(sh, ADR_BA_TID, tid); -+ SMAC_REG_WRITE(sh, ADR_BA_ST_SEQ, ssn); -+ SMAC_REG_WRITE(sh, ADR_BA_SB0, 0); -+ SMAC_REG_WRITE(sh, ADR_BA_SB1, 0); -+ SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0xb); -+ } else { -+ SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0x0); -+ } -+} -+ -+void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work) -+{ -+ struct ssv_softc -+ *sc = container_of(work, struct ssv_softc, set_ampdu_rx_add_work); -+ ssv6200_hw_set_rx_ba_session(sc->sh, true, sc->ba_ra_addr, sc->ba_tid, -+ sc->ba_ssn, 64); -+} -+ -+void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work) -+{ -+ struct ssv_softc *sc = container_of(work, struct ssv_softc, -+ set_ampdu_rx_del_work); -+ u8 addr[6] = { 0 }; -+ ssv6200_hw_set_rx_ba_session(sc->sh, false, addr, 0, 0, 0); -+} -+ -+static void _reset_ampdu_mib(struct ssv_softc *sc, -+ struct ssv_sta_info *sta_info, void *param) -+{ -+ struct ieee80211_sta *sta = sta_info->sta; -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ int i; -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ for (i = 0; i < WMM_TID_NUM; i++) { -+ ssv_sta_priv->ampdu_tid[i].ampdu_mib_reset = 1; -+ } -+} -+ -+void ssv6xxx_ampdu_mib_reset(struct ieee80211_hw *hw) -+{ -+ struct ssv_softc *sc = hw->priv; -+ if (sc == NULL) -+ return; -+ ssv6xxx_foreach_sta(sc, _reset_ampdu_mib, NULL); -+} -+ -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv, -+ char *mib_str, ssize_t length) -+{ -+ ssize_t buf_size = length; -+ ssize_t prt_size; -+ int j; -+ struct ssv_sta_info *ssv_sta = ssv_sta_priv->sta_info; -+ if (ssv_sta->sta == NULL) { -+ prt_size = snprintf(mib_str, buf_size, "\n NULL STA.\n"); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ goto mib_dump_exit; -+ } -+ for (j = 0; j < WMM_TID_NUM; j++) { -+ int k; -+ struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[j]; -+ struct AMPDU_MIB_st *ampdu_mib = &du_tid->mib; -+ prt_size = -+ snprintf(mib_str, buf_size, "\n WMM_TID %d@%d\n", j, -+ ampdu_tid->state); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ if (ampdu_tid->state != AMPDU_STATE_OPERATION) -+ continue; -+ prt_size = -+ snprintf(mib_str, buf_size, " BA window size: %d\n", -+ ampdu_tid->ssv_baw_size); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = -+ snprintf(mib_str, buf_size, " BA window head: %d\n", -+ ampdu_tid->ssv_baw_head); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(mib_str, buf_size, -+ " Sending aggregated #: %d\n", -+ ampdu_tid->aggr_pkt_num); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = -+ snprintf(mib_str, buf_size, " Waiting #: %d\n", -+ skb_queue_len(&du_tid->ampdu_skb_tx_queue)); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = -+ snprintf(mib_str, buf_size, " Early aggregated %d\n", -+ ampdu_tid->early_aggr_skb_num); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(mib_str, buf_size, -+ " MPDU: %d\n", -+ ampdu_mib->ampdu_mib_mpdu_counter); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(mib_str, buf_size, -+ " Passed: %d\n", -+ ampdu_mib->ampdu_mib_pass_counter); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(mib_str, buf_size, -+ " Retry: %d\n", -+ ampdu_mib->ampdu_mib_retry_counter); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(mib_str, buf_size, -+ " AMPDU: %d\n", -+ ampdu_mib->ampdu_mib_ampdu_counter); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(mib_str, buf_size, -+ " Retry AMPDU: %d\n", -+ ampdu_mib->ampdu_mib_aggr_retry_counter); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(mib_str, buf_size, -+ " BAR count: %d\n", -+ ampdu_mib->ampdu_mib_bar_counter); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(mib_str, buf_size, -+ " Discard count: %d\n", -+ ampdu_mib->ampdu_mib_discard_counter); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(mib_str, buf_size, -+ " BA count: %d\n", -+ ampdu_mib->ampdu_mib_BA_counter); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = -+ snprintf(mib_str, buf_size, " Total BA count: %d\n", -+ ssv_sta_priv->ampdu_mib_total_BA_counter); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ prt_size = -+ snprintf(mib_str, buf_size, " Aggr # count:\n"); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ for (k = 0; k <= SSV_AMPDU_aggr_num_max; k++) { -+ prt_size = -+ snprintf(mib_str, buf_size, " %d: %d\n", -+ k, ampdu_mib->ampdu_mib_dist[k]); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ } -+ } -+ mib_dump_exit: -+ return (length - buf_size); -+} -+ -+static void _dump_ampdu_mib(struct ssv_softc *sc, struct ssv_sta_info *sta_info, -+ void *param) -+{ -+ struct mib_dump_data *dump_data = (struct mib_dump_data *)param; -+ struct ieee80211_sta *sta; -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ ssize_t buf_size; -+ ssize_t prt_size; -+ char *mib_str = dump_data->prt_buff; -+ if (param == NULL) -+ return; -+ buf_size = dump_data->buff_size - 1; -+ sta = sta_info->sta; -+ if ((sta == NULL) || ((sta_info->s_flags & STA_FLAG_VALID) == 0)) -+ return; -+ prt_size = snprintf(mib_str, buf_size, -+ "STA: %02X-%02X-%02X-%02X-%02X-%02X:\n", -+ sta->addr[0], sta->addr[1], sta->addr[2], -+ sta->addr[3], sta->addr[4], sta->addr[5]); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ prt_size = ampdu_tx_mib_dump(ssv_sta_priv, mib_str, buf_size); -+ mib_str += prt_size; -+ buf_size -= prt_size; -+ dump_data->prt_len = (dump_data->buff_size - 1 - buf_size); -+ dump_data->prt_buff = mib_str; -+ dump_data->buff_size = buf_size; -+} -+ -+ssize_t ssv6xxx_ampdu_mib_dump(struct ieee80211_hw *hw, char *mib_str, -+ ssize_t length) -+{ -+ struct ssv_softc *sc = hw->priv; -+ ssize_t buf_size = length - 1; -+ struct mib_dump_data dump_data = { mib_str, buf_size, 0 }; -+ if (sc == NULL) -+ return 0; -+ ssv6xxx_foreach_sta(sc, _dump_ampdu_mib, &dump_data); -+ return dump_data.prt_len; -+} -+#endif -+struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc, -+ struct AMPDU_TID_st *ampdu_tid, u32 len) -+{ -+ unsigned char *payload_addr; -+ u32 headroom = sc->hw->extra_tx_headroom; -+ u32 offset; -+ u32 cur_max_ampdu_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh); -+ u32 extra_room = sc->sh->tx_desc_len * 2 + 48; -+ u32 max_physical_len = (len -+ && ((len + extra_room) < cur_max_ampdu_size)) -+ ? (len + extra_room) -+ : cur_max_ampdu_size; -+ u32 skb_len = max_physical_len + headroom + 3; -+ struct sk_buff *ampdu_skb = __dev_alloc_skb(skb_len, GFP_KERNEL); -+ struct ampdu_hdr_st *ampdu_hdr; -+ if (ampdu_skb == NULL) { -+ dev_err(sc->dev, "AMPDU allocation of size %d(%d) failed\n", -+ len, skb_len); -+ return NULL; -+ } -+ payload_addr = ampdu_skb->data + headroom - sc->sh->tx_desc_len; -+ offset = ((size_t)payload_addr) % 4U; -+ if (offset) { -+ dev_dbg(sc->dev, "Align AMPDU data %d\n", offset); -+ skb_reserve(ampdu_skb, headroom + 4 - offset); -+ } else -+ skb_reserve(ampdu_skb, headroom); -+ ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head; -+ skb_queue_head_init(&du_hdr->mpdu_q); -+ ampdu_hdr->max_size = max_physical_len - extra_room; -+ ampdu_hdr->size = 0; -+ ampdu_hdr->ampdu_tid = ampdu_tid; -+ memset(ampdu_hdr->ssn, 0xFF, sizeof(ampdu_hdr->ssn)); -+ ampdu_hdr->mpdu_num = 0; -+ return ampdu_skb; -+} -+ -+bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb) -+{ -+ u32 ac = skb_get_queue_mapping(skb); -+ u32 hw_txqid = sc->tx.hw_txqid[ac]; -+ return AMPDU_HCI_Q_EMPTY(sc->sh, hw_txqid); -+} -+ -+static u32 _check_timeout(struct AMPDU_TID_st *ampdu_tid) -+{ -+ u16 ssn, head_ssn, end_ssn; -+ unsigned long check_jiffies = jiffies; -+ u32 has_retry = 0; -+ head_ssn = ampdu_tid->ssv_baw_head; -+ ssn = head_ssn; -+ if (ssn == SSV_ILLEGAL_SN) -+ return 0; -+ end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN; -+ do { -+ struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn); -+ struct SKB_info_st *skb_info; -+ unsigned long cur_jiffies; -+ unsigned long timeout_jiffies; -+ u32 delta_ms; -+ if (skb == NULL) -+ break; -+ skb_info = (SKB_info *) (skb->head); -+ cur_jiffies = jiffies; -+ timeout_jiffies = -+ skb_info->aggr_timestamp + -+ msecs_to_jiffies(BA_WAIT_TIMEOUT); -+ if ((skb_info->ampdu_tx_status != AMPDU_ST_SENT) -+ || time_before(cur_jiffies, timeout_jiffies)) -+ break; -+ delta_ms = -+ jiffies_to_msecs(cur_jiffies - skb_info->aggr_timestamp); -+ prn_aggr_err("rt S%d-T%d-%d (%u)\n", -+ ((struct ssv_sta_priv_data *)skb_info->sta-> -+ drv_priv)->sta_idx, ampdu_tid->tidno, ssn, -+ delta_ms); -+ if (delta_ms > 1000) { -+ prn_aggr_err("Last checktime %lu - %lu = %u\n", -+ check_jiffies, ampdu_tid->timestamp, -+ jiffies_to_msecs(check_jiffies - -+ ampdu_tid->timestamp)); -+ } -+ has_retry += _mark_skb_retry(skb_info, skb); -+ INC_PKT_SN(ssn); -+ } while (ssn != end_ssn); -+ ampdu_tid->timestamp = check_jiffies; -+ return has_retry; -+} -+ -+void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct AMPDU_TID_st *cur_AMPDU_TID; -+ if (!list_empty(&sc->tx.ampdu_tx_que)) { -+ list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que, -+ list) { -+ u32 has_retry; -+ if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION) -+ continue; -+ has_retry = _check_timeout(cur_AMPDU_TID); -+ if (has_retry) { -+ _collect_retry_frames(cur_AMPDU_TID); -+ ssv6200_ampdu_send_retry(sc->hw, cur_AMPDU_TID, -+ &cur_AMPDU_TID-> -+ retry_queue, true); -+ } -+ } -+ } -+} -+ -+void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head; -+ struct sk_buff *mpdu; -+ unsigned long cur_jiffies = jiffies; -+ int i; -+ SKB_info *mpdu_skb_info; -+ u16 ssn; -+ if (ampdu_hdr->ampdu_tid->state != AMPDU_STATE_OPERATION) -+ return; -+ spin_lock_bh(&du_hdr->ampdu_tid->pkt_array_lock); -+ for (i = 0; i < ampdu_hdr->mpdu_num; i++) { -+ ssn = ampdu_hdr->ssn[i]; -+ mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn); -+ if (mpdu == NULL) { -+ dev_err(sc->dev, "T%d-%d is a NULL MPDU.\n", -+ ampdu_hdr->ampdu_tid->tidno, ssn); -+ continue; -+ } -+ if (ampdu_skb_ssn(mpdu) != ssn) { -+ dev_err(sc->dev, "T%d-%d does not match %d MPDU.\n", -+ ampdu_hdr->ampdu_tid->tidno, ssn, -+ ampdu_skb_ssn(mpdu)); -+ continue; -+ } -+ mpdu_skb_info = (SKB_info *) (mpdu->head); -+ mpdu_skb_info->aggr_timestamp = cur_jiffies; -+ mpdu_skb_info->ampdu_tx_status = AMPDU_ST_SENT; -+ } -+ spin_unlock_bh(&du_hdr->ampdu_tid->pkt_array_lock); -+} -diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.h b/drivers/net/wireless/ssv6051/smac/ampdu.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ampdu.h -@@ -0,0 +1,215 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _AMPDU_H_ -+#define _AMPDU_H_ -+#include -+#include -+#define Enable_ampdu_debug_log (0) -+#define Enable_AMPDU_Live_Time (0) -+#define Enable_HW_AUTO_CRC_32 (1) -+#define Enable_AMPDU_Rx (1) -+#define Enable_AMPDU_Tx (1) -+#define Enable_AMPDU_FW_Retry (1) -+#define Enable_AMPDU_delay_work (1) -+#define USE_FLUSH_RETRY -+#define USE_AMPDU_TX_STATUS_ARRAY -+#define SSV_AMPDU_FLOW_CONTROL -+#define AMPDU_CHECK_SKB_SEQNO -+#define REPORT_TX_STATUS_DIRECTLY -+#define SSV_AMPDU_aggr_num_max MAX_AGGR_NUM -+#define SSV_AMPDU_seq_num_max (4096) -+#define SSV_AMPDU_retry_counter_max (3) -+#define SSV_AMPDU_tx_group_id_max (64) -+#define SSV_AMPDU_MAX_SSN (4096) -+#define SSV_AMPDU_BA_WINDOW_SIZE (64) -+#define SSV_AMPDU_WINDOW_SIZE (64) -+#define SSV_GET_MAX_AMPDU_SIZE(sh) (((sh)->tx_page_available/(sh)->ampdu_divider) << HW_MMU_PAGE_SHIFT) -+#define SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND (64) -+#define SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND (48) -+#define SSV_AMPDU_timer_period (50) -+#define SSV_AMPDU_TX_TIME_THRESHOLD (50) -+#define SSV_AMPDU_MPDU_LIVE_TIME (SSV_AMPDU_retry_counter_max*8) -+#define SSV_AMPDU_BA_TIME (50) -+#define SSV_ILLEGAL_SN (0xffff) -+#define AMPDU_BUFFER_SIZE (32*1024) -+#define AMPDU_SIGNATURE (0x4E) -+#define AMPDU_DELIMITER_LEN (4) -+#define AMPDU_FCS_LEN (4) -+#define AMPDU_RESERVED_LEN (3) -+#define AMPDU_TX_NAV_MCS_567 (48) -+#define SSV_SEQ_NUM_SHIFT (4) -+#define SSV_RETRY_BIT_SHIFT (11) -+#define IEEE80211_SEQ_SEQ_SHIFT (4) -+#define IEEE80211_AMPDU_BA_LEN (34) -+#define SSV6200_AMPDU_TRIGGER_INDEX 0 -+#define SSV_SN_STATUS_Release (0xaa) -+#define SSV_SN_STATUS_Retry (0xbb) -+#define SSV_SN_STATUS_Wait_BA (0xcc) -+#define SSV_SN_STATUS_Discard (0xdd) -+#define AMPDU_HCI_SEND_TAIL_WITH_FLOWCTRL (0) -+#define AMPDU_HCI_SEND_HEAD_WITH_FLOWCTRL (1) -+#define AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL (2) -+#define AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL (3) -+#define SSV_BAR_CTRL_ACK_POLICY_NORMAL (0x0000) -+#define SSV_BAR_CTRL_CBMTID_COMPRESSED_BA (0x0004) -+#define SSV_BAR_CTRL_TID_INFO_SHIFT (12) -+#define AMPDU_STATE_START BIT(0) -+#define AMPDU_STATE_OPERATION BIT(1) -+#define AMPDU_STATE_STOP BIT(2) -+typedef enum { -+ AMPDU_REKEY_PAUSE_STOP = 0, -+ AMPDU_REKEY_PAUSE_START, -+ AMPDU_REKEY_PAUSE_ONGOING, -+ AMPDU_REKEY_PAUSE_DEFER, -+ AMPDU_REKEY_PAUSE_HWKEY_SYNC, -+} AMPDU_REKEY_PAUSE_STATE; -+#define SSV_a_minus_b_in_c(a,b,c) (((a)>=(b))?((a)-(b)):((c)-(b)+(a))) -+#define SSV_AMPDU_SN_a_minus_b(a,b) (SSV_a_minus_b_in_c((a), (b), SSV_AMPDU_seq_num_max)) -+#define AMPDU_HCI_SEND(_sh,_sk,_q,_flag) (_sh)->hci.hci_ops->hci_tx((_sk), (_q), (_flag)) -+#define AMPDU_HCI_Q_EMPTY(_sh,_q) (_sh)->hci.hci_ops->hci_txq_empty((_q)) -+struct ampdu_hdr_st { -+ u32 first_sn; -+ struct sk_buff_head mpdu_q; -+ u32 max_size; -+ u32 size; -+ struct AMPDU_TID_st *ampdu_tid; -+ u16 ssn[MAX_AGGR_NUM]; -+ u16 mpdu_num; -+ struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES]; -+ struct ieee80211_sta *sta; -+}; -+enum AMPDU_TX_STATUS_E { -+ AMPDU_ST_NON_AMPDU, -+ AMPDU_ST_AGGREGATED, -+ AMPDU_ST_SENT, -+ AMPDU_ST_RETRY, -+ AMPDU_ST_DROPPED, -+ AMPDU_ST_DONE, -+}; -+typedef struct AMPDU_MIB_st { -+ u32 ampdu_mib_mpdu_counter; -+ u32 ampdu_mib_retry_counter; -+ u32 ampdu_mib_ampdu_counter; -+ u32 ampdu_mib_aggr_retry_counter; -+ u32 ampdu_mib_bar_counter; -+ u32 ampdu_mib_discard_counter; -+ u32 ampdu_mib_total_BA_counter; -+ u32 ampdu_mib_BA_counter; -+ u32 ampdu_mib_pass_counter; -+ u32 ampdu_mib_dist[SSV_AMPDU_aggr_num_max + 1]; -+} AMPDU_MIB; -+typedef struct AMPDU_TID_st { -+ struct list_head list; -+ volatile unsigned long timestamp; -+ u32 tidno; -+ u16 ac; -+ struct ieee80211_sta *sta; -+ u16 ssv_baw_size; -+ u8 agg_num_max; -+ u8 state; -+#ifdef AMPDU_CHECK_SKB_SEQNO -+ u32 last_seqno; -+#endif -+ struct sk_buff_head ampdu_skb_tx_queue; -+ spinlock_t ampdu_skb_tx_queue_lock; -+ struct sk_buff_head retry_queue; -+ struct sk_buff_head release_queue; -+ struct sk_buff *aggr_pkts[SSV_AMPDU_BA_WINDOW_SIZE]; -+ volatile u32 aggr_pkt_num; -+ volatile u16 ssv_baw_head; -+ spinlock_t pkt_array_lock; -+ struct sk_buff *cur_ampdu_pkt; -+ struct sk_buff_head early_aggr_ampdu_q; -+ u32 early_aggr_skb_num; -+ struct sk_buff_head ampdu_skb_wait_encry_queue; -+ u32 ampdu_mib_reset; -+ struct AMPDU_MIB_st mib; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct dentry *debugfs_dir; -+ struct sk_buff_head ba_q; -+#endif -+} AMPDU_TID, *p_AMPDU_TID; -+typedef struct AMPDU_DELIMITER_st { -+ u16 reserved:4; -+ u16 length:12; -+ u8 crc; -+ u8 signature; -+} AMPDU_DELIMITER, *p_AMPDU_DELIMITER; -+typedef struct AMPDU_BLOCKACK_st { -+ u16 frame_control; -+ u16 duration; -+ u8 ra_addr[ETH_ALEN]; -+ u8 ta_addr[ETH_ALEN]; -+ u16 BA_ack_ploicy:1; -+ u16 multi_tid:1; -+ u16 compress_bitmap:1; -+ u16 reserved:9; -+ u16 tid_info:4; -+ u16 BA_fragment_sn:4; -+ u16 BA_ssn:12; -+ u32 BA_sn_bit_map[2]; -+} AMPDU_BLOCKACK, *p_AMPDU_BLOCKACK; -+struct ssv_bar { -+ unsigned short frame_control; -+ unsigned short duration; -+ unsigned char ra[6]; -+ unsigned char ta[6]; -+ unsigned short control; -+ unsigned short start_seq_num; -+} __packed; -+#if Enable_ampdu_debug_log -+#define ampdu_db_log(format, args...) printk("~~~ampdu [%s:%d] "format, __FUNCTION__, __LINE__, ##args) -+#define ampdu_db_log_simple(format, args...) printk(format, ##args) -+#else -+#define ampdu_db_log(...) do {} while (0) -+#define ampdu_db_log_simple(...) do {} while (0) -+#endif -+#if Enable_AMPDU_delay_work -+void ssv6200_ampdu_delayed_work_callback_func(struct work_struct *work); -+#else -+void ssv6200_ampdu_timer_callback_func(unsigned long data); -+#endif -+void ssv6200_ampdu_init(struct ieee80211_hw *hw); -+void ssv6200_ampdu_deinit(struct ieee80211_hw *hw); -+void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw); -+void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta, -+ struct ieee80211_hw *hw, u16 * ssn); -+void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta, -+ struct ieee80211_hw *hw, u8 buffer_size); -+void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta, -+ struct ieee80211_hw *hw); -+bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb); -+u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw); -+void ssv6200_ampdu_timeout_tx(struct ieee80211_hw *hw); -+struct cfg_host_event; -+void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb); -+void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb); -+void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta, -+ struct sk_buff *skb); -+void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw, -+ struct ieee80211_sta *sta); -+void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw); -+void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw); -+void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu); -+extern void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work); -+extern void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work); -+void ssv6xxx_mib_reset(struct ieee80211_hw *hw); -+ssize_t ssv6xxx_mib_dump(struct ieee80211_hw *hw, char *mib_str, -+ ssize_t length); -+void encry_work(struct work_struct *work); -+void sync_hw_key_work(struct work_struct *work); -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/ap.c b/drivers/net/wireless/ssv6051/smac/ap.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ap.c -@@ -0,0 +1,598 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "lib.h" -+#include "dev.h" -+#include "ap.h" -+#include "ssv_rc_common.h" -+#include "ssv_rc.h" -+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq); -+#define IS_EQUAL(a,b) ( (a) == (b) ) -+#define SET_BIT(v,b) ( (v) |= (0x01<>PBUF_ADDR_SHIFT) -+#define PBUF_MapIDtoPkt(_ID) (PBUF_BASE_ADDR|((_ID)<sh, ADR_MTX_BCN_MISC, val); -+} -+ -+void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval, -+ u8 dtim_cnt) -+{ -+ u32 val; -+ if (beacon_interval == 0) -+ beacon_interval = 100; -+#ifdef BEACON_DEBUG -+ printk("[A] BSS_CHANGED_BEACON_INT beacon_int[%d] dtim_cnt[%d]\n", -+ beacon_interval, (dtim_cnt)); -+#endif -+ val = -+ (beacon_interval << MTX_BCN_PERIOD_SHIFT) | (dtim_cnt << -+ MTX_DTIM_NUM_SHIFT); -+ SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_PRD, val); -+} -+ -+bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable) -+{ -+ u32 regval = 0; -+ int ret = 0; -+ if (bEnable && !sc->beacon_usage) { -+ printk -+ ("[A] Reject to set beacon!!!. ssv6xxx_beacon_enable bEnable[%d] sc->beacon_usage[%d]\n", -+ bEnable, sc->beacon_usage); -+ sc->enable_beacon = BEACON_WAITING_ENABLED; -+ return 0; -+ } -+ if ((bEnable && (BEACON_ENABLED & sc->enable_beacon)) || -+ (!bEnable && !sc->enable_beacon)) { -+ printk -+ ("[A] ssv6xxx_beacon_enable bEnable[%d] and sc->enable_beacon[%d] are the same. no need to execute.\n", -+ bEnable, sc->enable_beacon); -+ if (bEnable) { -+ printk(" Ignore enable beacon cmd!!!!\n"); -+ return 0; -+ } -+ } -+ SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, ®val); -+#ifdef BEACON_DEBUG -+ printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval); -+#endif -+ regval &= MTX_BCN_ENABLE_MASK; -+#ifdef BEACON_DEBUG -+ printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval); -+#endif -+ regval |= (bEnable << MTX_BCN_TIMER_EN_SHIFT); -+ ret = SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval); -+#ifdef BEACON_DEBUG -+ printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval); -+#endif -+ sc->enable_beacon = (bEnable == true) ? BEACON_ENABLED : 0; -+ return ret; -+} -+ -+int ssv6xxx_beacon_fill_content(struct ssv_softc *sc, u32 regaddr, u8 * beacon, -+ int size) -+{ -+ u32 i, val; -+ u32 *ptr = (u32 *) beacon; -+ size = size / 4; -+ for (i = 0; i < size; i++) { -+ val = (u32) (*(ptr + i)); -+#ifdef BEACON_DEBUG -+ printk("[%08x] ", val); -+#endif -+ SMAC_REG_WRITE(sc->sh, regaddr + i * 4, val); -+ } -+#ifdef BEACON_DEBUG -+ printk("\n"); -+#endif -+ return 0; -+} -+ -+void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc, -+ struct sk_buff *beacon_skb) -+{ -+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(beacon_skb); -+ struct ssv6200_tx_desc *tx_desc; -+ u16 pb_offset = TXPB_OFFSET; -+ struct ssv_rate_info ssv_rate; -+ skb_push(beacon_skb, pb_offset); -+ tx_desc = (struct ssv6200_tx_desc *)beacon_skb->data; -+ memset(tx_desc, 0, pb_offset); -+ ssv6xxx_rc_hw_rate_idx(sc, tx_info, &ssv_rate); -+ tx_desc->len = beacon_skb->len - pb_offset; -+ tx_desc->c_type = M2_TXREQ; -+ tx_desc->f80211 = 1; -+ tx_desc->ack_policy = 1; -+ tx_desc->hdr_offset = pb_offset; -+ tx_desc->hdr_len = 24; -+ tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len; -+ tx_desc->crate_idx = ssv_rate.crate_hw_idx; -+ tx_desc->drate_idx = ssv_rate.drate_hw_idx; -+ skb_put(beacon_skb, 4); -+} -+ -+inline enum ssv6xxx_beacon_type ssv6xxx_beacon_get_valid_reg(struct ssv_softc -+ *sc) -+{ -+ u32 regval = 0; -+ SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, ®val); -+ regval &= MTX_BCN_CFG_VLD_MASK; -+ regval = regval >> MTX_BCN_CFG_VLD_SHIFT; -+ if (regval == 0x2 || regval == 0x0) -+ return SSV6xxx_BEACON_0; -+ else if (regval == 0x1) -+ return SSV6xxx_BEACON_1; -+ else -+ printk("=============>ERROR!!drv_bcn_reg_available\n"); -+ return SSV6xxx_BEACON_0; -+} -+ -+bool ssv6xxx_beacon_set(struct ssv_softc *sc, struct sk_buff *beacon_skb, -+ int dtim_offset) -+{ -+ u32 reg_tx_beacon_adr = ADR_MTX_BCN_CFG0; -+ enum ssv6xxx_beacon_type avl_bcn_type = SSV6xxx_BEACON_0; -+ bool ret = true; -+ int val; -+ ssv6xxx_beacon_reg_lock(sc, 1); -+ avl_bcn_type = ssv6xxx_beacon_get_valid_reg(sc); -+ if (avl_bcn_type == SSV6xxx_BEACON_1) -+ reg_tx_beacon_adr = ADR_MTX_BCN_CFG1; -+#ifdef BEACON_DEBUG -+ printk("[A] ssv6xxx_beacon_set avl_bcn_type[%d]\n", avl_bcn_type); -+#endif -+ do { -+ if (IS_BIT_SET(sc->beacon_usage, avl_bcn_type)) { -+#ifdef BEACON_DEBUG -+ printk -+ ("[A] beacon has already been set old len[%d] new len[%d]\n", -+ sc->beacon_info[avl_bcn_type].len, -+ beacon_skb->len); -+#endif -+ if (sc->beacon_info[avl_bcn_type].len >= -+ beacon_skb->len) { -+ break; -+ } else { -+ if (false == -+ ssv6xxx_pbuf_free(sc, -+ sc-> -+ beacon_info[avl_bcn_type]. -+ pubf_addr)) { -+#ifdef BEACON_DEBUG -+ printk -+ ("=============>ERROR!!Intend to allcoate beacon from ASIC fail.\n"); -+#endif -+ ret = false; -+ goto out; -+ } -+ CLEAR_BIT(sc->beacon_usage, avl_bcn_type); -+ } -+ } -+ sc->beacon_info[avl_bcn_type].pubf_addr = -+ ssv6xxx_pbuf_alloc(sc, beacon_skb->len, TX_BUF); -+ sc->beacon_info[avl_bcn_type].len = beacon_skb->len; -+ if (sc->beacon_info[avl_bcn_type].pubf_addr == 0) { -+ ret = false; -+ goto out; -+ } -+ SET_BIT(sc->beacon_usage, avl_bcn_type); -+#ifdef BEACON_DEBUG -+ printk -+ ("[A] beacon type[%d] usage[%d] allocate new beacon addr[%08x] \n", -+ avl_bcn_type, sc->beacon_usage, -+ sc->beacon_info[avl_bcn_type].pubf_addr); -+#endif -+ } while (0); -+ ssv6xxx_beacon_fill_content(sc, sc->beacon_info[avl_bcn_type].pubf_addr, -+ beacon_skb->data, beacon_skb->len); -+ val = -+ (PBUF_MapPkttoID(sc->beacon_info[avl_bcn_type].pubf_addr)) | -+ (dtim_offset << MTX_DTIM_OFST0); -+ SMAC_REG_WRITE(sc->sh, reg_tx_beacon_adr, val); -+#ifdef BEACON_DEBUG -+ printk("[A] update to register reg_tx_beacon_adr[%08x] val[%08x]\n", -+ reg_tx_beacon_adr, val); -+#endif -+ out: -+ ssv6xxx_beacon_reg_lock(sc, 0); -+ if (sc->beacon_usage && (sc->enable_beacon & BEACON_WAITING_ENABLED)) { -+ printk("[A] enable beacon for BEACON_WAITING_ENABLED flags\n"); -+ ssv6xxx_beacon_enable(sc, true); -+ } -+ return ret; -+} -+ -+inline bool ssv6xxx_auto_bcn_ongoing(struct ssv_softc *sc) -+{ -+ u32 regval; -+ SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, ®val); -+ return ((AUTO_BCN_ONGOING_MASK & regval) >> AUTO_BCN_ONGOING_SHIFT); -+} -+ -+void ssv6xxx_beacon_release(struct ssv_softc *sc) -+{ -+ int cnt = 10; -+ printk("[A] ssv6xxx_beacon_release Enter\n"); -+ cancel_work_sync(&sc->set_tim_work); -+ do { -+ if (ssv6xxx_auto_bcn_ongoing(sc)) -+ ssv6xxx_beacon_enable(sc, false); -+ else -+ break; -+ cnt--; -+ if (cnt <= 0) -+ break; -+ } while (1); -+ if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_0)) { -+ ssv6xxx_pbuf_free(sc, -+ sc->beacon_info[SSV6xxx_BEACON_0].pubf_addr); -+ CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_0); -+ } -+ if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_1)) { -+ ssv6xxx_pbuf_free(sc, -+ sc->beacon_info[SSV6xxx_BEACON_1].pubf_addr); -+ CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_1); -+ } -+ sc->enable_beacon = 0; -+ if (sc->beacon_buf) { -+ dev_kfree_skb_any(sc->beacon_buf); -+ sc->beacon_buf = NULL; -+ } -+#ifdef BEACON_DEBUG -+ printk("[A] ssv6xxx_beacon_release leave\n"); -+#endif -+} -+ -+void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif, bool aid0_bit_set) -+{ -+ struct sk_buff *skb; -+ struct sk_buff *old_skb = NULL; -+ u16 tim_offset, tim_length; -+ if (sc == NULL || hw == NULL || vif == NULL) { -+ printk("[Error]........ssv6xxx_beacon_change input error\n"); -+ return; -+ } -+ do { -+ skb = ieee80211_beacon_get_tim(hw, vif, -+ &tim_offset, &tim_length, 0); -+ if (skb == NULL) { -+ printk("[Error]........skb is NULL\n"); -+ break; -+ } -+ if (tim_offset && tim_length >= 6) { -+ skb->data[tim_offset + 2] = 0; -+ if (aid0_bit_set) -+ skb->data[tim_offset + 4] |= 1; -+ else -+ skb->data[tim_offset + 4] &= ~1; -+ } -+#ifdef BEACON_DEBUG -+ printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len, -+ tim_offset); -+#endif -+ ssv6xxx_beacon_fill_tx_desc(sc, skb); -+#ifdef BEACON_DEBUG -+ printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len, -+ tim_offset); -+#endif -+ if (sc->beacon_buf) { -+ if (memcmp -+ (sc->beacon_buf->data, skb->data, -+ (skb->len - FCS_LEN)) == 0) { -+ old_skb = skb; -+ break; -+ } else { -+ old_skb = sc->beacon_buf; -+ sc->beacon_buf = skb; -+ } -+ } else { -+ sc->beacon_buf = skb; -+ } -+ tim_offset += 2; -+ if (ssv6xxx_beacon_set(sc, skb, tim_offset)) { -+ u8 dtim_cnt = vif->bss_conf.dtim_period - 1; -+ if (sc->beacon_dtim_cnt != dtim_cnt) { -+ sc->beacon_dtim_cnt = dtim_cnt; -+#ifdef BEACON_DEBUG -+ printk("[A] beacon_dtim_cnt [%d]\n", -+ sc->beacon_dtim_cnt); -+#endif -+ ssv6xxx_beacon_set_info(sc, sc->beacon_interval, -+ sc->beacon_dtim_cnt); -+ } -+ } -+ } while (0); -+ if (old_skb) -+ dev_kfree_skb_any(old_skb); -+} -+ -+void ssv6200_set_tim_work(struct work_struct *work) -+{ -+ struct ssv_softc *sc = -+ container_of(work, struct ssv_softc, set_tim_work); -+#ifdef BROADCAST_DEBUG -+ printk("%s() enter\n", __FUNCTION__); -+#endif -+ ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set); -+#ifdef BROADCAST_DEBUG -+ printk("%s() leave\n", __FUNCTION__); -+#endif -+} -+ -+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq) -+{ -+ u32 len; -+ unsigned long flags; -+ spin_lock_irqsave(&bcast_txq->txq_lock, flags); -+ len = bcast_txq->cur_qsize; -+ spin_unlock_irqrestore(&bcast_txq->txq_lock, flags); -+ return len; -+} -+ -+struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq, -+ u8 * remain_len) -+{ -+ struct sk_buff *skb = NULL; -+ unsigned long flags; -+ spin_lock_irqsave(&bcast_txq->txq_lock, flags); -+ if (bcast_txq->cur_qsize) { -+ bcast_txq->cur_qsize--; -+ if (remain_len) -+ *remain_len = bcast_txq->cur_qsize; -+ skb = __skb_dequeue(&bcast_txq->qhead); -+ } -+ spin_unlock_irqrestore(&bcast_txq->txq_lock, flags); -+ return skb; -+} -+ -+int ssv6200_bcast_enqueue(struct ssv_softc *sc, -+ struct ssv6xxx_bcast_txq *bcast_txq, -+ struct sk_buff *skb) -+{ -+ unsigned long flags; -+ spin_lock_irqsave(&bcast_txq->txq_lock, flags); -+ if (bcast_txq->cur_qsize >= SSV6200_MAX_BCAST_QUEUE_LEN) { -+ struct sk_buff *old_skb; -+ old_skb = __skb_dequeue(&bcast_txq->qhead); -+ bcast_txq->cur_qsize--; -+ ssv6xxx_txbuf_free_skb(old_skb, (void *)sc); -+ printk("[B] ssv6200_bcast_enqueue - remove oldest queue\n"); -+ } -+ __skb_queue_tail(&bcast_txq->qhead, skb); -+ bcast_txq->cur_qsize++; -+ spin_unlock_irqrestore(&bcast_txq->txq_lock, flags); -+ return bcast_txq->cur_qsize; -+} -+ -+void ssv6200_bcast_flush(struct ssv_softc *sc, -+ struct ssv6xxx_bcast_txq *bcast_txq) -+{ -+ struct sk_buff *skb; -+ unsigned long flags; -+#ifdef BCAST_DEBUG -+ printk("ssv6200_bcast_flush\n"); -+#endif -+ spin_lock_irqsave(&bcast_txq->txq_lock, flags); -+ while (bcast_txq->cur_qsize > 0) { -+ skb = __skb_dequeue(&bcast_txq->qhead); -+ bcast_txq->cur_qsize--; -+ ssv6xxx_txbuf_free_skb(skb, (void *)sc); -+ } -+ spin_unlock_irqrestore(&bcast_txq->txq_lock, flags); -+} -+ -+static int queue_block_cnt = 0; -+void ssv6200_bcast_tx_work(struct work_struct *work) -+{ -+ struct ssv_softc *sc = -+ container_of(work, struct ssv_softc, bcast_tx_work.work); -+ struct sk_buff *skb; -+ int i; -+ u8 remain_size; -+ unsigned long flags; -+ bool needtimer = true; -+ long tmo = sc->bcast_interval; -+ spin_lock_irqsave(&sc->ps_state_lock, flags); -+ do { -+#ifdef BCAST_DEBUG -+ printk -+ ("[B] bcast_timer: hw_mng_used[%d] HCI_TXQ_EMPTY[%d] bcast_queue_len[%d].....................\n", -+ sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4), -+ ssv6200_bcast_queue_len(&sc->bcast_txq)); -+#endif -+ if (sc->hw_mng_used != 0 || false == HCI_TXQ_EMPTY(sc->sh, 4)) { -+#ifdef BCAST_DEBUG -+ printk -+ ("HW queue still have frames insdide. skip this one hw_mng_used[%d] bEmptyTXQ4[%d]\n", -+ sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4)); -+#endif -+ queue_block_cnt++; -+ if (queue_block_cnt > 5) { -+ queue_block_cnt = 0; -+ ssv6200_bcast_flush(sc, &sc->bcast_txq); -+ needtimer = false; -+ } -+ break; -+ } -+ queue_block_cnt = 0; -+ for (i = 0; i < SSV6200_ID_MANAGER_QUEUE; i++) { -+ skb = -+ ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size); -+ if (!skb) { -+ needtimer = false; -+ break; -+ } -+ if ((0 != remain_size) && -+ (SSV6200_ID_MANAGER_QUEUE - 1) != i) { -+ struct ieee80211_hdr *hdr; -+ struct ssv6200_tx_desc *tx_desc = -+ (struct ssv6200_tx_desc *)skb->data; -+ hdr = -+ (struct ieee80211_hdr *)((u8 *) tx_desc + -+ tx_desc-> -+ hdr_offset); -+ hdr->frame_control |= -+ cpu_to_le16(IEEE80211_FCTL_MOREDATA); -+ } -+#ifdef BCAST_DEBUG -+ printk("[B] bcast_timer:tx remain_size[%d] i[%d]\n", -+ remain_size, i); -+#endif -+ spin_unlock_irqrestore(&sc->ps_state_lock, flags); -+ if (HCI_SEND(sc->sh, skb, 4) < 0) { -+ printk("bcast_timer send fail!!!!!!! \n"); -+ ssv6xxx_txbuf_free_skb(skb, (void *)sc); -+ BUG_ON(1); -+ } -+ spin_lock_irqsave(&sc->ps_state_lock, flags); -+ } -+ } while (0); -+ if (needtimer) { -+#ifdef BCAST_DEBUG -+ printk -+ ("[B] bcast_timer:need more timer to tx bcast frame time[%d]\n", -+ sc->bcast_interval); -+#endif -+ queue_delayed_work(sc->config_wq, &sc->bcast_tx_work, tmo); -+ } else { -+#ifdef BCAST_DEBUG -+ printk("[B] bcast_timer: ssv6200_bcast_stop\n"); -+#endif -+ ssv6200_bcast_stop(sc); -+ } -+ spin_unlock_irqrestore(&sc->ps_state_lock, flags); -+#ifdef BCAST_DEBUG -+ printk("[B] bcast_timer: leave.....................\n"); -+#endif -+} -+ -+void ssv6200_bcast_start_work(struct work_struct *work) -+{ -+ struct ssv_softc *sc = -+ container_of(work, struct ssv_softc, bcast_start_work); -+#ifdef BCAST_DEBUG -+ printk("[B] ssv6200_bcast_start_work==\n"); -+#endif -+ sc->bcast_interval = (sc->beacon_dtim_cnt + 1) * -+ (sc->beacon_interval + 20) * HZ / 1000; -+ if (!sc->aid0_bit_set) { -+ sc->aid0_bit_set = true; -+ ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set); -+ queue_delayed_work(sc->config_wq, -+ &sc->bcast_tx_work, sc->bcast_interval); -+#ifdef BCAST_DEBUG -+ printk("[B] bcast_start_work: Modify timer to DTIM[%d]ms==\n", -+ (sc->beacon_dtim_cnt + 1) * (sc->beacon_interval + 20)); -+#endif -+ } -+} -+ -+void ssv6200_bcast_stop_work(struct work_struct *work) -+{ -+ struct ssv_softc *sc = -+ container_of(work, struct ssv_softc, bcast_stop_work.work); -+ long tmo = HZ / 100; -+#ifdef BCAST_DEBUG -+ printk("[B] ssv6200_bcast_stop_work\n"); -+#endif -+ if (sc->aid0_bit_set) { -+ if (0 == ssv6200_bcast_queue_len(&sc->bcast_txq)) { -+ cancel_delayed_work_sync(&sc->bcast_tx_work); -+ sc->aid0_bit_set = false; -+ ssv6xxx_beacon_change(sc, sc->hw, -+ sc->ap_vif, sc->aid0_bit_set); -+#ifdef BCAST_DEBUG -+ printk("remove group bit in DTIM\n"); -+#endif -+ } else { -+#ifdef BCAST_DEBUG -+ printk -+ ("bcast_stop_work: bcast queue still have data. just modify timer to 10ms\n"); -+#endif -+ queue_delayed_work(sc->config_wq, -+ &sc->bcast_tx_work, tmo); -+ } -+ } -+} -+ -+void ssv6200_bcast_stop(struct ssv_softc *sc) -+{ -+ queue_delayed_work(sc->config_wq, -+ &sc->bcast_stop_work, -+ sc->beacon_interval * HZ / 1024); -+} -+ -+void ssv6200_bcast_start(struct ssv_softc *sc) -+{ -+ queue_work(sc->config_wq, &sc->bcast_start_work); -+} -+ -+void ssv6200_release_bcast_frame_res(struct ssv_softc *sc, -+ struct ieee80211_vif *vif) -+{ -+ unsigned long flags; -+ struct ssv_vif_priv_data *priv_vif = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ spin_lock_irqsave(&sc->ps_state_lock, flags); -+ priv_vif->sta_asleep_mask = 0; -+ spin_unlock_irqrestore(&sc->ps_state_lock, flags); -+ cancel_work_sync(&sc->bcast_start_work); -+ cancel_delayed_work_sync(&sc->bcast_stop_work); -+ ssv6200_bcast_flush(sc, &sc->bcast_txq); -+ cancel_delayed_work_sync(&sc->bcast_tx_work); -+} -diff --git a/drivers/net/wireless/ssv6051/smac/ap.h b/drivers/net/wireless/ssv6051/smac/ap.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ap.h -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _AP_H_ -+#define _AP_H_ -+#define BEACON_WAITING_ENABLED 1<<0 -+#define BEACON_ENABLED 1<<1 -+void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif, bool aid0_bit_set); -+void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval, -+ u8 dtim_cnt); -+bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable); -+void ssv6xxx_beacon_release(struct ssv_softc *sc); -+void ssv6200_set_tim_work(struct work_struct *work); -+void ssv6200_bcast_start_work(struct work_struct *work); -+void ssv6200_bcast_stop_work(struct work_struct *work); -+void ssv6200_bcast_tx_work(struct work_struct *work); -+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq); -+struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq, -+ u8 * remain_len); -+int ssv6200_bcast_enqueue(struct ssv_softc *sc, -+ struct ssv6xxx_bcast_txq *bcast_txq, -+ struct sk_buff *skb); -+void ssv6200_bcast_start(struct ssv_softc *sc); -+void ssv6200_bcast_stop(struct ssv_softc *sc); -+void ssv6200_release_bcast_frame_res(struct ssv_softc *sc, -+ struct ieee80211_vif *vif); -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/dev.c b/drivers/net/wireless/ssv6051/smac/dev.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/dev.c -@@ -0,0 +1,3881 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include "linux_80211.h" -+#include "lib.h" -+#include "ssv_rc.h" -+#include "ssv_ht_rc.h" -+#include "dev.h" -+#include "ap.h" -+#include "init.h" -+#include "p2p.h" -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+#include "ssv6xxx_debugfs.h" -+#endif -+struct rssi_res_st rssi_res, *p_rssi_res; -+#define NO_USE_RXQ_LOCK -+#ifndef WLAN_CIPHER_SUITE_SMS4 -+#define WLAN_CIPHER_SUITE_SMS4 0x00147201 -+#endif -+#define MAX_TX_Q_LEN (64) -+#define LOW_TX_Q_LEN (MAX_TX_Q_LEN/2) -+static u16 bits_per_symbol[][2] = { -+ {26, 54}, -+ {52, 108}, -+ {78, 162}, -+ {104, 216}, -+ {156, 324}, -+ {208, 432}, -+ {234, 486}, -+ {260, 540}, -+}; -+ -+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP -+extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci; -+extern unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage); -+#endif -+struct ssv6xxx_calib_table { -+ u16 channel_id; -+ u32 rf_ctrl_N; -+ u32 rf_ctrl_F; -+ u16 rf_precision_default; -+}; -+static void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q, -+ spinlock_t * rx_q_lock); -+static u32 _process_tx_done(struct ssv_softc *sc); -+ -+void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args) -+{ -+ struct ssv_softc *sc = (struct ssv_softc *)args; -+ if (!skb) -+ return; -+ ieee80211_free_txskb(sc->hw, skb); -+} -+ -+#define ADDRESS_OFFSET 16 -+#define HW_ID_OFFSET 7 -+#define CH0_FULL_MASK CH0_FULL_MSK -+#define MAX_FAIL_COUNT 100 -+#define MAX_RETRY_COUNT 20 -+inline bool ssv6xxx_mcu_input_full(struct ssv_softc *sc) -+{ -+ u32 regval = 0; -+ SMAC_REG_READ(sc->sh, ADR_MCU_STATUS, ®val); -+ return CH0_FULL_MASK & regval; -+} -+ -+u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type) -+{ -+ u32 regval, pad; -+ int cnt = MAX_RETRY_COUNT; -+ int page_cnt = -+ (size + ((1 << HW_MMU_PAGE_SHIFT) - 1)) >> HW_MMU_PAGE_SHIFT; -+ regval = 0; -+ mutex_lock(&sc->mem_mutex); -+ pad = size % 4; -+ size += pad; -+ do { -+ SMAC_REG_WRITE(sc->sh, ADR_WR_ALC, (size | (type << 16))); -+ SMAC_REG_READ(sc->sh, ADR_WR_ALC, ®val); -+ if (regval == 0) { -+ cnt--; -+ msleep(1); -+ } else -+ break; -+ } while (cnt); -+ if (type == TX_BUF) { -+ sc->sh->tx_page_available -= page_cnt; -+ sc->sh->page_count[PACKET_ADDR_2_ID(regval)] = page_cnt; -+ } -+ mutex_unlock(&sc->mem_mutex); -+ if (regval == 0) -+ dev_err(sc->dev, -+ "Failed to allocate packet buffer of %d bytes in %d type.", -+ size, type); -+ else { -+ dev_dbg(sc->dev, -+ "Allocated %d type packet buffer of size %d (%d) at address %x.\n", -+ type, size, page_cnt, regval); -+ } -+ return regval; -+} -+ -+bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr) -+{ -+ u32 regval = 0; -+ u16 failCount = 0; -+ u8 *p_tx_page_cnt = &sc->sh->page_count[PACKET_ADDR_2_ID(pbuf_addr)]; -+ while (ssv6xxx_mcu_input_full(sc)) { -+ if (failCount++ < 1000) -+ continue; -+ dev_err(sc->dev, "Error in mailbox block after %d iterations\n", failCount); -+ return false; -+ } -+ mutex_lock(&sc->mem_mutex); -+ regval = -+ ((M_ENG_TRASH_CAN << HW_ID_OFFSET) | (pbuf_addr >> ADDRESS_OFFSET)); -+ SMAC_REG_WRITE(sc->sh, ADR_CH0_TRIG_1, regval); -+ if (*p_tx_page_cnt) { -+ sc->sh->tx_page_available += *p_tx_page_cnt; -+ *p_tx_page_cnt = 0; -+ } -+ mutex_unlock(&sc->mem_mutex); -+ return true; -+} -+ -+static const struct ssv6xxx_calib_table vt_tbl[SSV6XXX_IQK_CFG_XTAL_MAX][14] = { -+ { -+ {1, 0xB9, 0x89D89E, 3859}, -+ {2, 0xB9, 0xEC4EC5, 3867}, -+ {3, 0xBA, 0x4EC4EC, 3875}, -+ {4, 0xBA, 0xB13B14, 3883}, -+ {5, 0xBB, 0x13B13B, 3891}, -+ {6, 0xBB, 0x762762, 3899}, -+ {7, 0xBB, 0xD89D8A, 3907}, -+ {8, 0xBC, 0x3B13B1, 3915}, -+ {9, 0xBC, 0x9D89D9, 3923}, -+ {10, 0xBD, 0x000000, 3931}, -+ {11, 0xBD, 0x627627, 3939}, -+ {12, 0xBD, 0xC4EC4F, 3947}, -+ {13, 0xBE, 0x276276, 3955}, -+ {14, 0xBF, 0x13B13B, 3974}, -+ }, -+ { -+ {1, 0xf1, 0x333333, 3859}, -+ {2, 0xf1, 0xB33333, 3867}, -+ {3, 0xf2, 0x333333, 3875}, -+ {4, 0xf2, 0xB33333, 3883}, -+ {5, 0xf3, 0x333333, 3891}, -+ {6, 0xf3, 0xB33333, 3899}, -+ {7, 0xf4, 0x333333, 3907}, -+ {8, 0xf4, 0xB33333, 3915}, -+ {9, 0xf5, 0x333333, 3923}, -+ {10, 0xf5, 0xB33333, 3931}, -+ {11, 0xf6, 0x333333, 3939}, -+ {12, 0xf6, 0xB33333, 3947}, -+ {13, 0xf7, 0x333333, 3955}, -+ {14, 0xf8, 0x666666, 3974}, -+ }, -+ { -+ {1, 0xC9, 0x000000, 3859}, -+ {2, 0xC9, 0x6AAAAB, 3867}, -+ {3, 0xC9, 0xD55555, 3875}, -+ {4, 0xCA, 0x400000, 3883}, -+ {5, 0xCA, 0xAAAAAB, 3891}, -+ {6, 0xCB, 0x155555, 3899}, -+ {7, 0xCB, 0x800000, 3907}, -+ {8, 0xCB, 0xEAAAAB, 3915}, -+ {9, 0xCC, 0x555555, 3923}, -+ {10, 0xCC, 0xC00000, 3931}, -+ {11, 0xCD, 0x2AAAAB, 3939}, -+ {12, 0xCD, 0x955555, 3947}, -+ {13, 0xCE, 0x000000, 3955}, -+ {14, 0xCF, 0x000000, 3974}, -+ } -+}; -+ -+#define FAIL_MAX 100 -+#define RETRY_MAX 20 -+int ssv6xxx_set_channel(struct ssv_softc *sc, int ch) -+{ -+ struct ssv_hw *sh = sc->sh; -+ int retry_cnt, fail_cnt = 0; -+ u32 regval; -+ int ret = -1; -+ int chidx; -+ bool chidx_vld = 0; -+ dev_dbg(sc->dev, "Setting channel to %d\n", ch); -+ if ((sh->cfg.chip_identity == SSV6051Z) -+ || (sc->sh->cfg.chip_identity == SSV6051P)) { -+ if ((ch == 13) || (ch == 14)) { -+ if (sh->ipd_channel_touch == 0) { -+ for (chidx = 0; chidx < sh->ch_cfg_size; -+ chidx++) { -+ SMAC_REG_WRITE(sh, -+ sh->p_ch_cfg[chidx]. -+ reg_addr, -+ sh->p_ch_cfg[chidx]. -+ ch13_14_value); -+ } -+ sh->ipd_channel_touch = 1; -+ } -+ } else { -+ if (sh->ipd_channel_touch) { -+ for (chidx = 0; chidx < sh->ch_cfg_size; -+ chidx++) { -+ SMAC_REG_WRITE(sh, -+ sh->p_ch_cfg[chidx]. -+ reg_addr, -+ sh->p_ch_cfg[chidx]. -+ ch1_12_value); -+ } -+ sh->ipd_channel_touch = 0; -+ } -+ } -+ } -+ for (chidx = 0; chidx < 14; chidx++) { -+ if (vt_tbl[sh->cfg.crystal_type][chidx].channel_id == ch) { -+ chidx_vld = 1; -+ break; -+ } -+ } -+ if (chidx_vld == 0) { -+ dev_dbg(sc->dev, "%s(): fail! channel_id not found in vt_tbl\n", -+ __FUNCTION__); -+ goto exit; -+ } -+ if ((ret = ssv6xxx_rf_disable(sc->sh)) != 0) -+ goto exit; -+ do { -+ if ((sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M) -+ || (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M)) { -+ if ((ret = -+ SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC, -+ (0x00 << 13), -+ (0x01 << 13))) != 0) -+ break; -+ } else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) { -+ if ((ret = -+ SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC, -+ (0x01 << 13), -+ (0x01 << 13))) != 0) -+ break; -+ } else { -+ dev_warn(sc->dev, "Illegal crystal setting in ssv6xxx_set_channel\n"); -+ BUG_ON(1); -+ } -+ if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I, -+ (0x01 << 19), (0x01 << 19))) != 0) -+ break; -+ regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_F; -+ if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_1, -+ (regval << 0), -+ (0x00ffffff << 0))) != 0) -+ break; -+ regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_N; -+ if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_2, -+ (regval << 0), -+ (0x07ff << 0))) != 0) -+ break; -+ if ((ret = -+ SMAC_REG_READ(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I, -+ ®val)) != 0) -+ break; -+ regval = -+ vt_tbl[sh->cfg.crystal_type][chidx].rf_precision_default; -+ if ((ret = -+ SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_II, -+ (regval << 0), (0x1fff << 0))) != 0) -+ break; -+ if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER, -+ (0x00 << 14), (0x01 << 14))) != 0) -+ break; -+ if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER, -+ (0x01 << 14), (0x01 << 14))) != 0) -+ break; -+ retry_cnt = 0; -+ do { -+ mdelay(1); -+ if ((ret = -+ SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1, -+ ®val)) != 0) -+ break; -+ if (regval & 0x00000002) { -+ if ((ret = -+ SMAC_REG_READ(sc->sh, -+ ADR_READ_ONLY_FLAGS_2, -+ ®val)) != 0) -+ break; -+ ret = ssv6xxx_rf_enable(sc->sh); -+ //dev_info(sc->dev, "Lock to channel %d ([0xce010098]=%x)!!\n", vt_tbl[sh->cfg.crystal_type][chidx].channel_id, regval); -+ sc->hw_chan = ch; -+ goto exit; -+ } -+ retry_cnt++; -+ } -+ while (retry_cnt < RETRY_MAX); -+ fail_cnt++; -+ dev_warn(sc->dev, "calibation fail after %d iterations\n", fail_cnt); -+ } -+ while ((fail_cnt < FAIL_MAX) && (ret == 0)); -+ exit: -+ if (ch == 14 && regval == 0xff0) { -+ SMAC_IFC_RESET(sc->sh); -+ ssv6xxx_restart_hw(sc); -+ } -+ if (ch <= 7) { -+ if (sh->cfg.tx_power_index_1) { -+ SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, ®val); -+ regval &= RG_TX_GAIN_OFFSET_I_MSK; -+ regval |= -+ (sh->cfg.tx_power_index_1 << RG_TX_GAIN_OFFSET_SFT); -+ SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval); -+ } else if (sh->cfg.tx_power_index_2) { -+ SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, ®val); -+ regval &= RG_TX_GAIN_OFFSET_I_MSK; -+ SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval); -+ } -+ } else { -+ if (sh->cfg.tx_power_index_2) { -+ SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, ®val); -+ regval &= RG_TX_GAIN_OFFSET_I_MSK; -+ regval |= -+ (sh->cfg.tx_power_index_2 << RG_TX_GAIN_OFFSET_SFT); -+ SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval); -+ } else if (sh->cfg.tx_power_index_1) { -+ SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, ®val); -+ regval &= RG_TX_GAIN_OFFSET_I_MSK; -+ SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval); -+ } -+ } -+ return ret; -+} -+ -+#ifdef CONFIG_SSV_SMARTLINK -+int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch) -+{ -+ *pch = sc->hw_chan; -+ return 0; -+} -+ -+int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept) -+{ -+ u32 val = 0; -+ if (accept) { -+ val = 0x2; -+ } else { -+ val = 0x3; -+ } -+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB13, val); -+ return 0; -+} -+ -+int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept) -+{ -+ u32 val = 0; -+ SMAC_REG_READ(sc->sh, ADR_MRX_FLT_TB13, &val); -+ if (val == 0x2) { -+ *paccept = 1; -+ } else { -+ *paccept = 0; -+ } -+ return 0; -+} -+#endif -+int ssv6xxx_rf_enable(struct ssv_hw *sh) -+{ -+ return SMAC_REG_SET_BITS(sh, 0xce010000, (0x02 << 12), (0x03 << 12) -+ ); -+} -+ -+int ssv6xxx_rf_disable(struct ssv_hw *sh) -+{ -+ return SMAC_REG_SET_BITS(sh, 0xce010000, (0x01 << 12), (0x03 << 12) -+ ); -+} -+ -+int ssv6xxx_update_decision_table(struct ssv_softc *sc) -+{ -+ int i; -+ for (i = 0; i < MAC_DECITBL1_SIZE; i++) { -+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + i * 4, -+ sc->mac_deci_tbl[i]); -+ SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_TB0 + i * 4, -+ sc->mac_deci_tbl[i]); -+ } -+ for (i = 0; i < MAC_DECITBL2_SIZE; i++) { -+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN0 + i * 4, -+ sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]); -+ SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN0 + i * 4, -+ sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]); -+ } -+ return 0; -+} -+ -+static int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht) -+{ -+#define CTRL_FRAME_INDEX(fc) ((hdr->frame_control-IEEE80211_STYPE_BACK_REQ)>>4) -+ u16 fc, CTRL_FLEN[] = { 16, 16, 16, 16, 10, 10, 16, 16 }; -+ int hdr_len = 24; -+ fc = hdr->frame_control; -+ if (ieee80211_is_ctl(fc)) -+ hdr_len = CTRL_FLEN[CTRL_FRAME_INDEX(fc)]; -+ else if (ieee80211_is_mgmt(fc)) { -+ if (ieee80211_has_order(fc)) -+ hdr_len += ((is_ht == 1) ? 4 : 0); -+ } else { -+ if (ieee80211_has_a4(fc)) -+ hdr_len += 6; -+ if (ieee80211_is_data_qos(fc)) { -+ hdr_len += 2; -+ if (ieee80211_has_order(hdr->frame_control) && -+ is_ht == true) -+ hdr_len += 4; -+ } -+ } -+ return hdr_len; -+} -+ -+static u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width, -+ int half_gi, bool is_gf) -+{ -+ u32 nbits, nsymbits, duration, nsymbols; -+ int streams; -+ streams = 1; -+ nbits = (pktlen << 3) + OFDM_PLCP_BITS; -+ nsymbits = bits_per_symbol[rix % 8][width] * streams; -+ nsymbols = (nbits + nsymbits - 1) / nsymbits; -+ if (!half_gi) -+ duration = SYMBOL_TIME(nsymbols); -+ else { -+ if (!is_gf) -+ duration = -+ DIV_ROUND_UP(SYMBOL_TIME_HALFGI(nsymbols), 4) << 2; -+ else -+ duration = SYMBOL_TIME_HALFGI(nsymbols); -+ } -+ duration += -+ L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams) + -+ HT_SIGNAL_EXT; -+ if (is_gf) -+ duration -= 12; -+ duration += HT_SIFS_TIME; -+ return duration; -+} -+ -+static u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps, -+ u32 frameLen, bool shortPreamble) -+{ -+ u32 bits_per_symbol, num_bits, num_symbols; -+ u32 phy_time, tx_time; -+ if (kbps == 0) -+ return 0; -+ switch (phy) { -+ case WLAN_RC_PHY_CCK: -+ phy_time = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; -+ if (shortPreamble) -+ phy_time >>= 1; -+ num_bits = frameLen << 3; -+ tx_time = CCK_SIFS_TIME + phy_time + ((num_bits * 1000) / kbps); -+ break; -+ case WLAN_RC_PHY_OFDM: -+ bits_per_symbol = (kbps * OFDM_SYMBOL_TIME) / 1000; -+ num_bits = OFDM_PLCP_BITS + (frameLen << 3); -+ num_symbols = DIV_ROUND_UP(num_bits, bits_per_symbol); -+ tx_time = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME -+ + (num_symbols * OFDM_SYMBOL_TIME); -+ break; -+ default: -+ pr_err("ssv6051: unknown phy %u\n", phy); -+ BUG_ON(1); -+ tx_time = 0; -+ break; -+ } -+ return tx_time; -+} -+ -+static u32 ssv6xxx_set_frame_duration(struct ieee80211_tx_info *info, -+ struct ssv_rate_info *ssv_rate, u16 len, -+ struct ssv6200_tx_desc *tx_desc, -+ struct fw_rc_retry_params *rc_params, -+ struct ssv_softc *sc) -+{ -+ struct ieee80211_tx_rate *tx_drate; -+ u32 frame_time = 0, ack_time = 0, rts_cts_nav = 0, frame_consume_time = -+ 0; -+ u32 l_length = 0, drate_kbps = 0, crate_kbps = 0; -+ bool ctrl_short_preamble = false, is_sgi, is_ht40; -+ bool is_ht, is_gf; -+ int d_phy, c_phy, nRCParams, mcsidx; -+ struct ssv_rate_ctrl *ssv_rc = NULL; -+ tx_drate = &info->control.rates[0]; -+ is_sgi = !!(tx_drate->flags & IEEE80211_TX_RC_SHORT_GI); -+ is_ht40 = !!(tx_drate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH); -+ is_ht = !!(tx_drate->flags & IEEE80211_TX_RC_MCS); -+ is_gf = !!(tx_drate->flags & IEEE80211_TX_RC_GREEN_FIELD); -+ if ((info->control.short_preamble) || -+ (tx_drate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)) -+ ctrl_short_preamble = true; -+ pr_debug("mcs = %d, data rate idx=%d\n", tx_drate->idx, tx_drate[3].count); -+ for (nRCParams = 0; (nRCParams < SSV62XX_TX_MAX_RATES); nRCParams++) { -+ if ((rc_params == NULL) || (sc == NULL)) { -+ mcsidx = tx_drate->idx; -+ drate_kbps = ssv_rate->drate_kbps; -+ crate_kbps = ssv_rate->crate_kbps; -+ } else { -+ if (rc_params[nRCParams].count == 0) { -+ break; -+ } -+ ssv_rc = sc->rc; -+ mcsidx = -+ (rc_params[nRCParams].drate - -+ SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES; -+ drate_kbps = -+ ssv_rc->rc_table[rc_params[nRCParams].drate]. -+ rate_kbps; -+ crate_kbps = -+ ssv_rc->rc_table[rc_params[nRCParams].crate]. -+ rate_kbps; -+ } -+ if (tx_drate->flags & IEEE80211_TX_RC_MCS) { -+ frame_time = ssv6xxx_ht_txtime(mcsidx, -+ len, is_ht40, is_sgi, -+ is_gf); -+ d_phy = 0; -+ } else { -+ if ((info->band == INDEX_80211_BAND_2GHZ) && -+ !(ssv_rate->d_flags & IEEE80211_RATE_ERP_G)) -+ d_phy = WLAN_RC_PHY_CCK; -+ else -+ d_phy = WLAN_RC_PHY_OFDM; -+ frame_time = ssv6xxx_non_ht_txtime(d_phy, drate_kbps, -+ len, -+ ctrl_short_preamble); -+ } -+ if ((info->band == INDEX_80211_BAND_2GHZ) && -+ !(ssv_rate->c_flags & IEEE80211_RATE_ERP_G)) -+ c_phy = WLAN_RC_PHY_CCK; -+ else -+ c_phy = WLAN_RC_PHY_OFDM; -+ if (tx_desc->unicast) { -+ if (info->flags & IEEE80211_TX_CTL_AMPDU) { -+ ack_time = ssv6xxx_non_ht_txtime(c_phy, -+ crate_kbps, -+ BA_LEN, -+ ctrl_short_preamble); -+ } else { -+ ack_time = ssv6xxx_non_ht_txtime(c_phy, -+ crate_kbps, -+ ACK_LEN, -+ ctrl_short_preamble); -+ } -+ } -+ if (tx_desc->do_rts_cts & IEEE80211_TX_RC_USE_RTS_CTS) { -+ rts_cts_nav = frame_time; -+ rts_cts_nav += ack_time; -+ rts_cts_nav += ssv6xxx_non_ht_txtime(c_phy, -+ crate_kbps, -+ CTS_LEN, -+ ctrl_short_preamble); -+ frame_consume_time = rts_cts_nav; -+ frame_consume_time += ssv6xxx_non_ht_txtime(c_phy, -+ crate_kbps, -+ RTS_LEN, -+ ctrl_short_preamble); -+ } else if (tx_desc-> -+ do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) { -+ rts_cts_nav = frame_time; -+ rts_cts_nav += ack_time; -+ frame_consume_time = rts_cts_nav; -+ frame_consume_time += ssv6xxx_non_ht_txtime(c_phy, -+ crate_kbps, -+ CTS_LEN, -+ ctrl_short_preamble); -+ } else {; -+ } -+ if (tx_drate->flags & IEEE80211_TX_RC_MCS) { -+ l_length = frame_time - HT_SIFS_TIME; -+ l_length = ((l_length - (HT_SIGNAL_EXT + 20)) + 3) >> 2; -+ l_length += ((l_length << 1) - 3); -+ } -+ if ((rc_params == NULL) || (sc == NULL)) { -+ tx_desc->rts_cts_nav = rts_cts_nav; -+ tx_desc->frame_consume_time = -+ (frame_consume_time >> 5) + 1;; -+ tx_desc->dl_length = l_length; -+ break; -+ } else { -+ rc_params[nRCParams].rts_cts_nav = rts_cts_nav; -+ rc_params[nRCParams].frame_consume_time = -+ (frame_consume_time >> 5) + 1; -+ rc_params[nRCParams].dl_length = l_length; -+ if (nRCParams == 0) { -+ tx_desc->drate_idx = rc_params[nRCParams].drate; -+ tx_desc->crate_idx = rc_params[nRCParams].crate; -+ tx_desc->rts_cts_nav = -+ rc_params[nRCParams].rts_cts_nav; -+ tx_desc->frame_consume_time = -+ rc_params[nRCParams].frame_consume_time; -+ tx_desc->dl_length = -+ rc_params[nRCParams].dl_length; -+ } -+ } -+ } -+ return ack_time; -+} -+ -+static void ssv6200_hw_set_pair_type(struct ssv_hw *sh, u8 type) -+{ -+ u32 temp; -+ SMAC_REG_READ(sh, ADR_SCRT_SET, &temp); -+ temp = (temp & PAIR_SCRT_I_MSK); -+ temp |= (type << PAIR_SCRT_SFT); -+ SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp); -+ dev_dbg(sh->sc->dev, "==>%s: write cipher type %d into hw\n", __func__, type); -+} -+ -+static u32 ssv6200_hw_get_pair_type(struct ssv_hw *sh) -+{ -+ u32 temp; -+ SMAC_REG_READ(sh, ADR_SCRT_SET, &temp); -+ temp &= PAIR_SCRT_MSK; -+ temp = (temp >> PAIR_SCRT_SFT); -+ SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp); -+ dev_dbg(sh->sc->dev, "==>%s: read cipher type %d from hw\n", __func__, temp); -+ return temp; -+} -+ -+static void ssv6200_hw_set_group_type(struct ssv_hw *sh, u8 type) -+{ -+ u32 temp; -+ SMAC_REG_READ(sh, ADR_SCRT_SET, &temp); -+ temp = temp & GRP_SCRT_I_MSK; -+ temp |= (type << GRP_SCRT_SFT); -+ SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp); -+ dev_dbg(sh->sc->dev, "Set group key type %d\n", type); -+} -+ -+void ssv6xxx_reset_sec_module(struct ssv_softc *sc) -+{ -+ ssv6200_hw_set_group_type(sc->sh, ME_NONE); -+ ssv6200_hw_set_pair_type(sc->sh, ME_NONE); -+} -+ -+static int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta, -+ struct ssv_sta_info *sta_info, int sta_idx, -+ int rx_hw_sec, int ops) -+{ -+ int ret = 0; -+ int retry_cnt = 20; -+ struct sk_buff *skb = NULL; -+ struct cfg_host_cmd *host_cmd; -+ struct ssv6xxx_wsid_params *ptr; -+ dev_dbg(sc->dev, "cmd=%d for fw wsid list, wsid %d \n", ops, sta_idx); -+ skb = -+ ssv_skb_alloc(HOST_CMD_HDR_LEN + -+ sizeof(struct ssv6xxx_wsid_params)); -+ if (skb == NULL || sta_info == NULL || sc == NULL) -+ return -1; -+ skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_wsid_params); -+ skb->len = skb->data_len; -+ host_cmd = (struct cfg_host_cmd *)skb->data; -+ host_cmd->c_type = HOST_CMD; -+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_WSID_OP; -+ host_cmd->len = skb->data_len; -+ ptr = (struct ssv6xxx_wsid_params *)host_cmd->dat8; -+ ptr->cmd = ops; -+ ptr->hw_security = rx_hw_sec; -+ if ((ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE) -+ && (ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE)) { -+ ptr->wsid_idx = (u8) (sta_idx - SSV_NUM_HW_STA); -+ } else { -+ ptr->wsid_idx = (u8) (sta_idx); -+ }; -+ memcpy(&ptr->target_wsid, &sta->addr[0], 6); -+ while (((sc->sh->hci.hci_ops->hci_send_cmd(skb)) != 0) && (retry_cnt)) { -+ dev_dbg(sc->dev, "WSID cmd=%d retry=%d!!\n", ops, retry_cnt); -+ retry_cnt--; -+ } -+ dev_dbg(sc->dev, "%s: wsid_idx = %u\n", __FUNCTION__, ptr->wsid_idx); -+ ssv_skb_free(skb); -+ if (ops == SSV6XXX_WSID_OPS_ADD) -+ sta_info->hw_wsid = sta_idx; -+ return ret; -+} -+ -+static void hw_crypto_key_clear(struct ieee80211_hw *hw, int index, -+ struct ieee80211_key_conf *key, -+ struct ssv_vif_priv_data *vif_priv, -+ struct ssv_sta_priv_data *sta_priv) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_sta_info *sta_info = NULL; -+ if ((index == 0) && (sta_priv == NULL)) -+ return; -+ if ((index < 0) || (index >= 4)) -+ return; -+ if (index > 0) { -+ if (vif_priv) -+ vif_priv->group_key_idx = 0; -+ if (sta_priv) -+ sta_priv->group_key_idx = 0; -+ } -+ if (sta_priv) { -+ sta_info = &sc->sta_info[sta_priv->sta_idx]; -+ if ((index == 0) && (sta_priv->has_hw_decrypt == true) -+ && (sta_info->hw_wsid >= SSV_NUM_HW_STA)) { -+ hw_update_watch_wsid(sc, sta_info->sta, sta_info, -+ sta_priv->sta_idx, -+ SSV6XXX_WSID_SEC_PAIRWISE, -+ SSV6XXX_WSID_OPS_DISABLE_CAPS); -+ } -+ } -+ if (vif_priv) { -+ if ((index != 0) && !list_empty(&vif_priv->sta_list)) { -+ struct ssv_sta_priv_data *sta_priv_iter; -+ list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, -+ list) { -+ if (((sta_priv_iter->sta_info-> -+ s_flags & STA_FLAG_VALID) == 0) -+ || (sta_priv_iter->sta_info->hw_wsid < -+ SSV_NUM_HW_STA)) -+ continue; -+ hw_update_watch_wsid(sc, -+ sta_priv_iter->sta_info-> -+ sta, -+ sta_priv_iter->sta_info, -+ sta_priv_iter->sta_idx, -+ SSV6XXX_WSID_SEC_GROUP, -+ SSV6XXX_WSID_OPS_DISABLE_CAPS); -+ } -+ } -+ } -+} -+ -+static void _set_wep_sw_crypto_key(struct ssv_softc *sc, -+ struct ssv_vif_info *vif_info, -+ struct ssv_sta_info *sta_info, void *param) -+{ -+ struct ssv_sta_priv_data *sta_priv = -+ (struct ssv_sta_priv_data *)sta_info->sta->drv_priv; -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)vif_info->vif->drv_priv; -+ sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt; -+ sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt; -+ sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt; -+ sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt; -+} -+ -+static void _set_wep_hw_crypto_pair_key(struct ssv_softc *sc, -+ struct ssv_vif_info *vif_info, -+ struct ssv_sta_info *sta_info, -+ void *param) -+{ -+ int wsid = sta_info->hw_wsid; -+ struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param; -+ int address = 0; -+ int *pointer = NULL; -+ u32 sec_key_tbl_base = sc->sh->hw_sec_key[0]; -+ u32 sec_key_tbl = sec_key_tbl_base; -+ int i; -+ u8 *key = sram_key->sta_key[0].pair.key; -+ u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0]; -+ struct ssv_sta_priv_data *sta_priv = -+ (struct ssv_sta_priv_data *)sta_info->sta->drv_priv; -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)vif_info->vif->drv_priv; -+ if (wsid == (-1)) -+ return; -+ sram_key->sta_key[wsid].pair_key_idx = 0; -+ sram_key->sta_key[wsid].group_key_idx = 0; -+ sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt; -+ sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt; -+ sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt; -+ sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt; -+ if (wsid != 0) -+ memcpy(sram_key->sta_key[wsid].pair.key, key, key_len); -+ address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key)) -+ + wsid * sizeof(struct ssv6xxx_hw_sta_key); -+ address += (0x10000 * wsid); -+ pointer = (int *)&sram_key->sta_key[wsid]; -+ for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++) -+ SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++)); -+} -+ -+static void _set_wep_hw_crypto_group_key(struct ssv_softc *sc, -+ struct ssv_vif_info *vif_info, -+ struct ssv_sta_info *sta_info, -+ void *param) -+{ -+ int wsid = sta_info->hw_wsid; -+ struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param; -+ int address = 0; -+ int *pointer = NULL; -+ u32 key_idx = sram_key->sta_key[0].pair_key_idx; -+ u32 sec_key_tbl_base = sc->sh->hw_sec_key[0]; -+ u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0]; -+ u8 *key = sram_key->group_key[key_idx - 1].key; -+ u32 sec_key_tbl = sec_key_tbl_base; -+ struct ssv_sta_priv_data *sta_priv = -+ (struct ssv_sta_priv_data *)sta_info->sta->drv_priv; -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)vif_info->vif->drv_priv; -+ if (wsid == (-1)) -+ return; -+ if (wsid != 0) { -+ sram_key->sta_key[wsid].pair_key_idx = key_idx; -+ sram_key->sta_key[wsid].group_key_idx = key_idx; -+ sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt; -+ sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt; -+ sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt; -+ sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt; -+ } -+ if (wsid != 0) -+ memcpy(sram_key->group_key[key_idx - 1].key, key, key_len); -+ sec_key_tbl += (0x10000 * wsid); -+ address = sec_key_tbl + ((key_idx - 1) * sizeof(struct ssv6xxx_hw_key)); -+ pointer = (int *)&sram_key->group_key[key_idx - 1]; -+ { -+ int i; -+ for (i = 0; i < (sizeof(struct ssv6xxx_hw_key) / 4); i++) -+ SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++)); -+ } -+ address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key)) -+ + (wsid * sizeof(struct ssv6xxx_hw_sta_key)); -+ pointer = (int *)&sram_key->sta_key[wsid]; -+ SMAC_REG_WRITE(sc->sh, address, *(pointer)); -+} -+ -+static int hw_crypto_key_write_wep(struct ieee80211_hw *hw, -+ struct ieee80211_key_conf *key, -+ u8 algorithm, struct ssv_vif_info *vif_info) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey; -+ if (key->keyidx == 0) { -+ ssv6xxx_foreach_vif_sta(sc, vif_info, -+ _set_wep_hw_crypto_pair_key, sramKey); -+ } else { -+ ssv6xxx_foreach_vif_sta(sc, vif_info, -+ _set_wep_hw_crypto_group_key, sramKey); -+ } -+ return 0; -+} -+ -+static void _set_aes_tkip_hw_crypto_group_key(struct ssv_softc *sc, -+ struct ssv_vif_info *vif_info, -+ struct ssv_sta_info *sta_info, -+ void *param) -+{ -+ int wsid = sta_info->hw_wsid; -+ int j; -+ u32 sec_key_tbl_base = sc->sh->hw_sec_key[0]; -+ u32 sec_key_tbl = sec_key_tbl_base; -+ int address = 0; -+ int *pointer = 0; -+ struct ssv6xxx_hw_sec *sramKey = &(vif_info->sramKey); -+ int index = *(u8 *) param; -+ if (wsid == (-1)) -+ return; -+ BUG_ON(index == 0); -+ sramKey->sta_key[wsid].group_key_idx = index; -+ sec_key_tbl += (0x10000 * wsid); -+ address = sec_key_tbl + ((index - 1) * sizeof(struct ssv6xxx_hw_key)); -+ if (vif_info->vif_priv != NULL) -+ dev_dbg(sc->dev, "Write group key %d to VIF %d to %08X\n", -+ index, vif_info->vif_priv->vif_idx, address); -+ else -+ dev_err(sc->dev, "NULL VIF.\n"); -+ pointer = (int *)&sramKey->group_key[index - 1]; -+ for (j = 0; j < (sizeof(struct ssv6xxx_hw_key) / 4); j++) -+ SMAC_REG_WRITE(sc->sh, address + (j * 4), *(pointer++)); -+ address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key)) -+ + (wsid * sizeof(struct ssv6xxx_hw_sta_key)); -+ pointer = (int *)&sramKey->sta_key[wsid]; -+ SMAC_REG_WRITE(sc->sh, address, *(pointer)); -+ if (wsid >= SSV_NUM_HW_STA) { -+ hw_update_watch_wsid(sc, sta_info->sta, sta_info, -+ wsid, SSV6XXX_WSID_SEC_GROUP, -+ SSV6XXX_WSID_OPS_ENABLE_CAPS); -+ } -+} -+ -+static int _write_pairwise_key_to_hw(struct ssv_softc *sc, -+ int index, u8 algorithm, -+ const u8 * key, int key_len, -+ struct ieee80211_key_conf *keyconf, -+ struct ssv_vif_priv_data *vif_priv, -+ struct ssv_sta_priv_data *sta_priv) -+{ -+ int i; -+ struct ssv6xxx_hw_sec *sramKey; -+ int address = 0; -+ int *pointer = NULL; -+ u32 sec_key_tbl_base = sc->sh->hw_sec_key[0]; -+ u32 sec_key_tbl; -+ int wsid = (-1); -+ if (sta_priv == NULL) { -+ dev_err(sc->dev, "Set pair-wise key with NULL STA.\n"); -+ return -EOPNOTSUPP; -+ } -+ wsid = sta_priv->sta_info->hw_wsid; -+ if ((wsid < 0) || (wsid >= SSV_NUM_STA)) { -+ dev_err(sc->dev, "Set pair-wise key to invalid WSID %d.\n", -+ wsid); -+ return -EOPNOTSUPP; -+ } -+ dev_dbg(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid, -+ key_len); -+ sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey); -+ sramKey->sta_key[wsid].pair_key_idx = 0; -+ sramKey->sta_key[wsid].group_key_idx = vif_priv->group_key_idx; -+ memcpy(sramKey->sta_key[wsid].pair.key, key, key_len); -+ sec_key_tbl = sec_key_tbl_base; -+ sec_key_tbl += (0x10000 * wsid); -+ address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key)) -+ + wsid * sizeof(struct ssv6xxx_hw_sta_key); -+ pointer = (int *)&sramKey->sta_key[wsid]; -+ for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++) -+ SMAC_REG_WRITE(sc->sh, (address + (i * 4)), *(pointer++)); -+ if (wsid >= SSV_NUM_HW_STA) { -+ hw_update_watch_wsid(sc, sta_priv->sta_info->sta, -+ sta_priv->sta_info, sta_priv->sta_idx, -+ SSV6XXX_WSID_SEC_PAIRWISE, -+ SSV6XXX_WSID_OPS_ENABLE_CAPS); -+ } -+ return 0; -+} -+ -+static int _write_group_key_to_hw(struct ssv_softc *sc, -+ int index, u8 algorithm, -+ const u8 * key, int key_len, -+ struct ieee80211_key_conf *keyconf, -+ struct ssv_vif_priv_data *vif_priv, -+ struct ssv_sta_priv_data *sta_priv) -+{ -+ struct ssv6xxx_hw_sec *sramKey; -+ int wsid = sta_priv ? sta_priv->sta_info->hw_wsid : (-1); -+ int ret = 0; -+ if (vif_priv == NULL) { -+ dev_err(sc->dev, "Setting group key to NULL VIF\n"); -+ return -EOPNOTSUPP; -+ } -+ dev_dbg(sc->dev, -+ "Setting VIF %d group key %d of length %d to WSID %d.\n", -+ vif_priv->vif_idx, index, key_len, wsid); -+ sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey); -+ vif_priv->group_key_idx = index; -+ if (sta_priv) -+ sta_priv->group_key_idx = index; -+ memcpy(sramKey->group_key[index - 1].key, key, key_len); -+ WARN_ON(sc->vif_info[vif_priv->vif_idx].vif_priv == NULL); -+ ssv6xxx_foreach_vif_sta(sc, &sc->vif_info[vif_priv->vif_idx], -+ _set_aes_tkip_hw_crypto_group_key, &index); -+ ret = 0; -+ return ret; -+} -+ -+static enum SSV_CIPHER_E _prepare_key(struct ieee80211_key_conf *key) -+{ -+ enum SSV_CIPHER_E cipher; -+ switch (key->cipher) { -+ case WLAN_CIPHER_SUITE_WEP40: -+ cipher = SSV_CIPHER_WEP40; -+ break; -+ case WLAN_CIPHER_SUITE_WEP104: -+ cipher = SSV_CIPHER_WEP104; -+ break; -+ case WLAN_CIPHER_SUITE_TKIP: -+ key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; -+ cipher = SSV_CIPHER_TKIP; -+ break; -+ case WLAN_CIPHER_SUITE_CCMP: -+ key->flags |= -+ (IEEE80211_KEY_FLAG_SW_MGMT_TX | -+ IEEE80211_KEY_FLAG_RX_MGMT); -+ cipher = SSV_CIPHER_CCMP; -+ break; -+ default: -+ cipher = SSV_CIPHER_INVALID; -+ break; -+ } -+ return cipher; -+} -+int _set_key_wep(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, -+ struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, -+ struct ieee80211_key_conf *key) -+{ -+ int ret = 0; -+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx]; -+ struct ssv6xxx_hw_sec *sram_key = &vif_info->sramKey; -+ sram_key->sta_key[0].pair_key_idx = key->keyidx; -+ sram_key->sta_key[0].group_key_idx = key->keyidx; -+ *(u16 *) & sram_key->sta_key[0].reserve[0] = key->keylen; -+ dev_dbg(sc->dev, "Set WEP %02X %02X %02X %02X %02X %02X %02X %02X... (%d %d)\n", -+ key->key[0], key->key[1], key->key[2], key->key[3], key->key[4], -+ key->key[5], key->key[6], key->key[7], key->keyidx, key->keylen); -+ if (key->keyidx == 0) { -+ memcpy(sram_key->sta_key[0].pair.key, key->key, key->keylen); -+ } else { -+ memcpy(sram_key->group_key[key->keyidx - 1].key, key->key, -+ key->keylen); -+ } -+ if (sc->sh->cfg.use_wpa2_only) { -+ dev_warn(sc->dev, "WEP: use WPA2 HW security mode only.\n"); -+ } -+ if ((sc->sh->cfg.use_wpa2_only == 0) -+ && vif_priv->vif_idx == 0) { -+ vif_priv->has_hw_decrypt = true; -+ vif_priv->has_hw_encrypt = true; -+ vif_priv->need_sw_decrypt = false; -+ vif_priv->need_sw_encrypt = false; -+ vif_priv->use_mac80211_decrypt = false; -+ ssv6200_hw_set_pair_type(sc->sh, cipher); -+ ssv6200_hw_set_group_type(sc->sh, cipher); -+ hw_crypto_key_write_wep(sc->hw, key, cipher, -+ &sc->vif_info[vif_priv->vif_idx]); -+ } else { -+ vif_priv->has_hw_decrypt = false; -+ vif_priv->has_hw_encrypt = false; -+ vif_priv->need_sw_decrypt = false; -+ vif_priv->need_sw_encrypt = false; -+ vif_priv->use_mac80211_decrypt = true; -+ ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_sw_crypto_key, -+ NULL); -+ ret = -EOPNOTSUPP; -+ } -+ vif_priv->pair_cipher = vif_priv->group_cipher = cipher; -+ vif_priv->is_security_valid = true; -+ return ret; -+} -+ -+static int _set_pairwise_key_tkip_ccmp(struct ssv_softc *sc, -+ struct ssv_vif_priv_data *vif_priv, -+ struct ssv_sta_priv_data *sta_priv, -+ enum SSV_CIPHER_E cipher, -+ struct ieee80211_key_conf *key) -+{ -+ int ret = 0; -+ const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP"; -+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx]; -+ bool tdls_link = false, tdls_use_sw_cipher = false, tkip_use_sw_cipher = -+ false; -+ bool use_non_ccmp = false; -+ int another_vif_idx = ((vif_priv->vif_idx + 1) % 2); -+ struct ssv_vif_priv_data *another_vif_priv = -+ (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv; -+ if (sta_priv == NULL) { -+ dev_err(sc->dev, -+ "Setting pairwise TKIP/CCMP key to NULL STA.\n"); -+ return -EOPNOTSUPP; -+ } -+ if (sc->sh->cfg.use_wpa2_only) { -+ dev_warn(sc->dev, "Pairwise TKIP/CCMP: use WPA2 HW security mode only.\n"); -+ } -+ if (vif_info->if_type == NL80211_IFTYPE_STATION) { -+ struct ssv_sta_priv_data *first_sta_priv = -+ list_first_entry(&vif_priv->sta_list, -+ struct ssv_sta_priv_data, list); -+ if (first_sta_priv->sta_idx != sta_priv->sta_idx) { -+ tdls_link = true; -+ } -+ dev_dbg(sc->dev, "first sta idx %d, current sta idx %d\n", -+ first_sta_priv->sta_idx, sta_priv->sta_idx); -+ } -+ if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP) -+ && (sc->sh->cfg.use_wpa2_only == false)) { -+ tdls_use_sw_cipher = true; -+ } -+ if (another_vif_priv != NULL) { -+ if ((another_vif_priv->pair_cipher != SSV_CIPHER_CCMP) -+ && (another_vif_priv->pair_cipher != SSV_CIPHER_NONE)) { -+ use_non_ccmp = true; -+ dev_dbg(sc->dev, "another vif use none ccmp\n"); -+ } -+ } -+ if ((((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)) -+ || (use_non_ccmp)) -+ && (sc->sh->cfg.use_wpa2_only == 1) && (cipher == SSV_CIPHER_CCMP)) { -+ u32 val; -+ SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val); -+ if (((val >> 4) & 0xF) != M_ENG_CPU) { -+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, -+ ((val & 0xf) | (M_ENG_CPU << 4) -+ | (val & 0xfffffff0) << 4)); -+ dev_dbg(sc->dev, -+ "orginal Rx_Flow %x , modified flow %x \n", val, -+ ((val & 0xf) | (M_ENG_CPU << 4) | -+ (val & 0xfffffff0) << 4)); -+ } -+ } -+ if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) { -+ tkip_use_sw_cipher = true; -+ } -+ if (tkip_use_sw_cipher == true) -+ dev_info(sc->dev, "Using software TKIP cipher\n"); -+ if ((((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false) -+ && (tkip_use_sw_cipher == false))) -+ || ((cipher == SSV_CIPHER_CCMP) -+ && (sc->sh->cfg.use_wpa2_only == 1))) { -+ sta_priv->has_hw_decrypt = true; -+ sta_priv->need_sw_decrypt = false; -+ if ((cipher == SSV_CIPHER_TKIP) -+ || ((!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX) || -+ (sta_priv->sta_info->sta->deflink.ht_cap.ht_supported == -+ false)) -+ && (vif_priv->force_sw_encrypt == false))) { -+ dev_dbg(sc->dev, -+ "STA %d uses HW encrypter for pairwise.\n", -+ sta_priv->sta_idx); -+ sta_priv->has_hw_encrypt = true; -+ sta_priv->need_sw_encrypt = false; -+ sta_priv->use_mac80211_decrypt = false; -+ ret = 0; -+ } else { -+ sta_priv->has_hw_encrypt = false; -+ sta_priv->need_sw_encrypt = false; -+ sta_priv->use_mac80211_decrypt = true; -+ ret = -EOPNOTSUPP; -+ } -+ } else { -+ sta_priv->has_hw_encrypt = false; -+ sta_priv->has_hw_decrypt = false; -+ dev_err(sc->dev, "STA %d MAC80211's %s cipher.\n", -+ sta_priv->sta_idx, cipher_name); -+ sta_priv->need_sw_encrypt = false; -+ sta_priv->need_sw_decrypt = false; -+ sta_priv->use_mac80211_decrypt = true; -+ ret = -EOPNOTSUPP; -+ } -+ if (sta_priv->has_hw_encrypt || sta_priv->has_hw_decrypt) { -+ ssv6200_hw_set_pair_type(sc->sh, cipher); -+ _write_pairwise_key_to_hw(sc, key->keyidx, cipher, -+ key->key, key->keylen, key, -+ vif_priv, sta_priv); -+ } -+ if ((vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt) -+ && (vif_priv->group_key_idx > 0)) { -+ _set_aes_tkip_hw_crypto_group_key(sc, -+ &sc->vif_info[vif_priv-> -+ vif_idx], -+ sta_priv->sta_info, -+ &vif_priv->group_key_idx); -+ } -+ return ret; -+} -+ -+static int _set_group_key_tkip_ccmp(struct ssv_softc *sc, -+ struct ssv_vif_priv_data *vif_priv, -+ struct ssv_sta_priv_data *sta_priv, -+ enum SSV_CIPHER_E cipher, -+ struct ieee80211_key_conf *key) -+{ -+ int ret = 0; -+ const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP"; -+ bool tkip_use_sw_cipher = false; -+ vif_priv->group_cipher = cipher; -+ if (sc->sh->cfg.use_wpa2_only) { -+ dev_warn(sc->dev, "Group TKIP/CCMP: use WPA2 HW security mode only.\n"); -+ } -+ if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) { -+ tkip_use_sw_cipher = true; -+ } -+ if (((vif_priv->vif_idx == 0) && (tkip_use_sw_cipher == false)) -+ || ((cipher == SSV_CIPHER_CCMP) -+ && (sc->sh->cfg.use_wpa2_only == 1))) { -+ dev_dbg(sc->dev, "VIF %d uses HW %s cipher for group.\n", -+ vif_priv->vif_idx, cipher_name); -+#ifdef USE_MAC80211_DECRYPT_BROADCAST -+ vif_priv->has_hw_decrypt = false; -+ ret = -EOPNOTSUPP; -+#else -+ vif_priv->has_hw_decrypt = true; -+#endif -+ vif_priv->has_hw_encrypt = true; -+ vif_priv->need_sw_decrypt = false; -+ vif_priv->need_sw_encrypt = false; -+ vif_priv->use_mac80211_decrypt = false; -+ } else { -+ vif_priv->has_hw_decrypt = false; -+ vif_priv->has_hw_encrypt = false; -+ dev_err(sc->dev, "VIF %d uses MAC80211's %s cipher.\n", -+ vif_priv->vif_idx, cipher_name); -+ vif_priv->need_sw_encrypt = false; -+ vif_priv->need_sw_encrypt = false; -+ vif_priv->use_mac80211_decrypt = true; -+ ret = -EOPNOTSUPP; -+ } -+ if (vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt) { -+#ifdef USE_MAC80211_DECRYPT_BROADCAST -+ ssv6200_hw_set_group_type(sc->sh, ME_NONE); -+#else -+ ssv6200_hw_set_group_type(sc->sh, cipher); -+#endif -+ key->hw_key_idx = key->keyidx; -+ _write_group_key_to_hw(sc, key->keyidx, cipher, -+ key->key, key->keylen, key, -+ vif_priv, sta_priv); -+ } -+ vif_priv->is_security_valid = true; -+ { -+ int another_vif_idx = ((vif_priv->vif_idx + 1) % 2); -+ struct ssv_vif_priv_data *another_vif_priv = -+ (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx]. -+ vif_priv; -+ if (another_vif_priv != NULL) { -+ if (((SSV6XXX_USE_SW_DECRYPT(vif_priv) -+ && SSV6XXX_USE_HW_DECRYPT(another_vif_priv))) -+ || ((SSV6XXX_USE_HW_DECRYPT(vif_priv) -+ && -+ (SSV6XXX_USE_SW_DECRYPT(another_vif_priv))))) { -+ u32 val; -+ SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val); -+ if (((val >> 4) & 0xF) != M_ENG_CPU) { -+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, -+ ((val & 0xf) | -+ (M_ENG_CPU << 4) -+ | (val & 0xfffffff0) << -+ 4)); -+ dev_dbg(sc->dev, -+ "orginal Rx_Flow %x , modified flow %x \n", -+ val, -+ ((val & 0xf) | (M_ENG_CPU << 4) -+ | (val & 0xfffffff0) << 4)); -+ } else { -+ dev_dbg(sc->dev, " doesn't need to change rx flow\n"); -+ } -+ } -+ } -+ } -+ return ret; -+} -+ -+static int _set_key_tkip_ccmp(struct ssv_softc *sc, -+ struct ssv_vif_priv_data *vif_priv, -+ struct ssv_sta_priv_data *sta_priv, -+ enum SSV_CIPHER_E cipher, -+ struct ieee80211_key_conf *key) -+{ -+ if (key->keyidx == 0) -+ return _set_pairwise_key_tkip_ccmp(sc, vif_priv, sta_priv, -+ cipher, key); -+ else -+ return _set_group_key_tkip_ccmp(sc, vif_priv, sta_priv, cipher, -+ key); -+} -+ -+static int ssv6200_set_key(struct ieee80211_hw *hw, -+ enum set_key_cmd cmd, -+ struct ieee80211_vif *vif, -+ struct ieee80211_sta *sta, -+ struct ieee80211_key_conf *key) -+{ -+ struct ssv_softc *sc = hw->priv; -+ int ret = 0; -+ enum SSV_CIPHER_E cipher = SSV_CIPHER_NONE; -+ int sta_idx = (-1); -+ struct ssv_sta_info *sta_info = NULL; -+ struct ssv_sta_priv_data *sta_priv = NULL; -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx]; -+ if (sta) { -+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ sta_idx = sta_priv->sta_idx; -+ sta_info = sta_priv->sta_info; -+ } -+ BUG_ON((cmd != SET_KEY) && (cmd != DISABLE_KEY)); -+ if (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_SECURITY)) { -+ dev_warn(sc->dev, "HW does not support security.\n"); -+ return -EOPNOTSUPP; -+ } -+ if (sta_info && (sta_info->hw_wsid == (-1))) { -+ dev_warn(sc->dev, -+ "Add STA without HW resource. Use MAC80211's solution.\n"); -+ return -EOPNOTSUPP; -+ } -+ cipher = _prepare_key(key); -+ dev_dbg(sc->dev, -+ "Set key VIF %d VIF type %d STA %d algorithm = %d, key->keyidx = %d, cmd = %d\n", -+ vif_priv->vif_idx, vif->type, sta_idx, cipher, key->keyidx, -+ cmd); -+ if (cipher == SSV_CIPHER_INVALID) { -+ dev_warn(sc->dev, "Unsupported cipher type.\n"); -+ return -EOPNOTSUPP; -+ } -+ mutex_lock(&sc->mutex); -+ switch (cmd) { -+ case SET_KEY: -+ { -+ switch (cipher) { -+ case SSV_CIPHER_WEP40: -+ case SSV_CIPHER_WEP104: -+ ret = -+ _set_key_wep(sc, vif_priv, sta_priv, cipher, -+ key); -+ break; -+ case SSV_CIPHER_TKIP: -+ case SSV_CIPHER_CCMP: -+ ret = -+ _set_key_tkip_ccmp(sc, vif_priv, sta_priv, -+ cipher, key); -+ break; -+ default: -+ break; -+ } -+ if (sta) { -+ struct ssv_sta_priv_data *first_sta_priv = -+ list_first_entry(&vif_priv->sta_list, -+ struct ssv_sta_priv_data, -+ list); -+ if (first_sta_priv->sta_idx == -+ sta_priv->sta_idx) { -+ vif_priv->pair_cipher = cipher; -+ } -+ if (SSV6200_USE_HW_WSID(sta_idx)) { -+ if (SSV6XXX_USE_SW_DECRYPT(sta_priv)) { -+ u32 cipher_setting; -+ cipher_setting = -+ ssv6200_hw_get_pair_type -+ (sc->sh); -+ if (cipher_setting != ME_NONE) { -+ u32 val; -+ SMAC_REG_READ(sc->sh, -+ ADR_RX_FLOW_DATA, -+ &val); -+ if (((val >> 4) & 0xF) -+ != M_ENG_CPU) { -+ SMAC_REG_WRITE -+ (sc->sh, -+ ADR_RX_FLOW_DATA, -+ ((val & -+ 0xf) | -+ (M_ENG_CPU -+ << 4) -+ | (val & -+ 0xfffffff0) -+ << 4)); -+ dev_dbg(sc->dev, -+ "orginal Rx_Flow %x , modified flow %x \n", -+ val, -+ ((val & -+ 0xf) | -+ (M_ENG_CPU -+ << 4) -+ | (val -+ & -+ 0xfffffff0) -+ << 4)); -+ } else { -+ dev_dbg(sc->dev, " doesn't need to change rx flow\n"); -+ } -+ } -+ } -+ if (sta_priv->has_hw_decrypt) { -+ hw_update_watch_wsid(sc, sta, -+ sta_info, -+ sta_idx, -+ SSV6XXX_WSID_SEC_HW, -+ SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE); -+ dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for pairwise key\n", sta_idx); -+ } -+ } -+ } else { -+ if (vif_info->if_type == NL80211_IFTYPE_STATION) { -+ struct ssv_sta_priv_data *first_sta_priv -+ = -+ list_first_entry(&vif_priv-> -+ sta_list, -+ struct -+ ssv_sta_priv_data, -+ list); -+ if (SSV6200_USE_HW_WSID -+ (first_sta_priv->sta_idx)) { -+ if (vif_priv->has_hw_decrypt) { -+ hw_update_watch_wsid(sc, -+ sta, -+ sta_info, -+ first_sta_priv-> -+ sta_idx, -+ SSV6XXX_WSID_SEC_HW, -+ SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE); -+ dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for group key\n", first_sta_priv->sta_idx); -+ } -+ } -+ } -+ } -+ } -+ break; -+ case DISABLE_KEY: -+ { -+ int another_vif_idx = ((vif_priv->vif_idx + 1) % 2); -+ struct ssv_vif_priv_data *another_vif_priv = -+ (struct ssv_vif_priv_data *)sc-> -+ vif_info[another_vif_idx].vif_priv; -+ if (another_vif_priv != NULL) { -+ struct ssv_vif_info *vif_info = -+ &sc->vif_info[vif_priv->vif_idx]; -+ if (vif_info->if_type != NL80211_IFTYPE_AP) { -+ if ((SSV6XXX_USE_SW_DECRYPT(vif_priv) -+ && -+ SSV6XXX_USE_HW_DECRYPT -+ (another_vif_priv)) -+ || -+ (SSV6XXX_USE_SW_DECRYPT -+ (another_vif_priv) -+ && -+ SSV6XXX_USE_HW_DECRYPT(vif_priv))) -+ { -+ SMAC_REG_WRITE(sc->sh, -+ ADR_RX_FLOW_DATA, -+ M_ENG_MACRX | -+ (M_ENG_ENCRYPT_SEC -+ << 4) | -+ (M_ENG_HWHCI << -+ 8)); -+ dev_dbg(sc->dev, "redirect Rx flow for disconnect\n"); -+ } -+ } else { -+ if (sta == NULL) { -+ if (SSV6XXX_USE_SW_DECRYPT -+ (another_vif_priv) -+ && -+ SSV6XXX_USE_HW_DECRYPT -+ (vif_priv)) { -+ SMAC_REG_WRITE(sc->sh, -+ ADR_RX_FLOW_DATA, -+ M_ENG_MACRX -+ | -+ (M_ENG_ENCRYPT_SEC -+ << 4) | -+ (M_ENG_HWHCI -+ << 8)); -+ dev_dbg(sc->dev, "redirect Rx flow for disconnect\n"); -+ } -+ } -+ } -+ } -+ if (sta == NULL) { -+ vif_priv->group_cipher = ME_NONE; -+ if ((another_vif_priv == NULL) -+ || ((another_vif_priv != NULL) -+ && -+ (!SSV6XXX_USE_HW_DECRYPT -+ (another_vif_priv)))) { -+ ssv6200_hw_set_group_type(sc->sh, -+ ME_NONE); -+ } -+ } else { -+ struct ssv_vif_info *vif_info = -+ &sc->vif_info[vif_priv->vif_idx]; -+ if ((vif_info->if_type != NL80211_IFTYPE_AP) -+ && (another_vif_priv == NULL)) { -+ struct ssv_sta_priv_data *first_sta_priv -+ = -+ list_first_entry(&vif_priv-> -+ sta_list, -+ struct -+ ssv_sta_priv_data, -+ list); -+ if (sta_priv == first_sta_priv) { -+ ssv6200_hw_set_pair_type(sc->sh, -+ ME_NONE); -+ } -+ } -+ vif_priv->pair_cipher = ME_NONE; -+ } -+ if ((cipher == ME_TKIP) || (cipher == ME_CCMP)) { -+ dev_dbg(sc->dev, "Clear key %d VIF %d, STA %d\n", -+ key->keyidx, (vif != NULL), -+ (sta != NULL)); -+ hw_crypto_key_clear(hw, key->keyidx, key, -+ vif_priv, sta_priv); -+ } -+ { -+ if ((key->keyidx == 0) && (sta_priv != NULL)) { -+ sta_priv->has_hw_decrypt = false; -+ sta_priv->has_hw_encrypt = false; -+ sta_priv->need_sw_encrypt = false; -+ sta_priv->use_mac80211_decrypt = false; -+ } -+ if ((vif_priv->is_security_valid) -+ && (key->keyidx != 0)) { -+ vif_priv->is_security_valid = false; -+ } -+ } -+ ret = 0; -+ } -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ mutex_unlock(&sc->mutex); -+ if (sta_priv != NULL) { -+ dev_info(sc->dev, "station mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d\n", -+ (sta_priv->has_hw_encrypt == true), -+ (sta_priv->has_hw_decrypt == true), -+ (sta_priv->need_sw_encrypt == true), -+ (sta_priv->need_sw_decrypt == true)); -+ } -+ if (vif_priv) { -+ dev_info -+ (sc->dev, "vif mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d, mac80211 decrypt: %d, valid:%d\n", -+ (vif_priv->has_hw_encrypt == true), -+ (vif_priv->has_hw_decrypt == true), -+ (vif_priv->need_sw_encrypt == true), -+ (vif_priv->need_sw_decrypt == true), -+ (vif_priv->use_mac80211_decrypt == true), -+ (vif_priv->is_security_valid == true)); -+ } -+ if (vif_priv->force_sw_encrypt -+ || (sta_info && (sta_info->hw_wsid != 1) -+ && (sta_info->hw_wsid != 0))) { -+ if (vif_priv->force_sw_encrypt == false) -+ vif_priv->force_sw_encrypt = true; -+ ret = -EOPNOTSUPP; -+ } -+ dev_dbg(sc->dev, "SET KEY %d\n", ret); -+ return ret; -+} -+ -+u32 _process_tx_done(struct ssv_softc *sc) -+{ -+ struct ieee80211_tx_info *tx_info; -+ struct sk_buff *skb; -+ while ((skb = skb_dequeue(&sc->tx_done_q))) { -+ struct ssv6200_tx_desc *tx_desc; -+ tx_info = IEEE80211_SKB_CB(skb); -+ tx_desc = (struct ssv6200_tx_desc *)skb->data; -+ if (tx_desc->c_type > M2_TXREQ) { -+ ssv_skb_free(skb); -+ dev_dbg(sc->dev, "free cmd skb!\n"); -+ continue; -+ } -+ if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { -+ ssv6200_ampdu_release_skb(skb, sc->hw); -+ continue; -+ } -+ skb_pull(skb, SSV6XXX_TX_DESC_LEN); -+ ieee80211_tx_info_clear_status(tx_info); -+ tx_info->flags |= IEEE80211_TX_STAT_ACK; -+ tx_info->status.ack_signal = 100; -+#ifdef REPORT_TX_DONE_IN_IRQ -+ ieee80211_tx_status_irqsafe(sc->hw, skb); -+#else -+ ieee80211_tx_status_skb(sc->hw, skb); -+ if (skb_queue_len(&sc->rx_skb_q)) -+ break; -+#endif -+ } -+ return skb_queue_len(&sc->tx_done_q); -+} -+ -+#ifdef REPORT_TX_DONE_IN_IRQ -+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args) -+{ -+ struct ssv_softc *sc = (struct ssv_softc *)args; -+ _process_tx_done *(sc); -+} -+#else -+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args) -+{ -+ struct ssv_softc *sc = (struct ssv_softc *)args; -+ struct sk_buff *skb; -+ while ((skb = skb_dequeue(skb_head))) { -+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); -+ struct ssv6200_tx_desc *tx_desc; -+ tx_desc = (struct ssv6200_tx_desc *)skb->data; -+ if (tx_desc->c_type > M2_TXREQ) { -+ ssv_skb_free(skb); -+ dev_dbg(sc->dev, "free cmd skb!\n"); -+ continue; -+ } -+ if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) -+ ssv6xxx_ampdu_sent(sc->hw, skb); -+ skb_queue_tail(&sc->tx_done_q, skb); -+ } -+ wake_up_interruptible(&sc->rx_wait_q); -+} -+#endif -+void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args) -+{ -+ struct ieee80211_hdr *hdr; -+ struct ssv_softc *sc = args; -+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); -+ struct ssv6200_tx_desc *tx_desc; -+ struct ssv_rate_info ssv_rate; -+ u32 nav = 0; -+ int ret = 0; -+ tx_desc = (struct ssv6200_tx_desc *)skb->data; -+ if (tx_desc->c_type > M2_TXREQ) -+ return; -+ if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) { -+ hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_TX_DESC_LEN); -+ if ((ieee80211_is_data_qos(hdr->frame_control) -+ || ieee80211_is_data(hdr->frame_control)) -+ && (tx_desc->wsid < SSV_RC_MAX_HARDWARE_SUPPORT)) { -+ ret = -+ ssv6xxx_rc_hw_rate_update_check(skb, sc, -+ tx_desc-> -+ do_rts_cts); -+ if (ret & RC_FIRMWARE_REPORT_FLAG) { -+ { -+ tx_desc->RSVD_0 = SSV6XXX_RC_REPORT; -+ tx_desc->tx_report = 1; -+ } -+ ret &= 0xf; -+ } -+ if (ret) { -+ ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate); -+ tx_desc->crate_idx = ssv_rate.crate_hw_idx; -+ tx_desc->drate_idx = ssv_rate.drate_hw_idx; -+ nav = -+ ssv6xxx_set_frame_duration(info, &ssv_rate, -+ skb->len + -+ FCS_LEN, tx_desc, -+ NULL, NULL); -+ if (tx_desc->tx_burst == 0) { -+ if (tx_desc->ack_policy != 0x01) -+ hdr->duration_id = nav; -+ } -+ } -+ } -+ } else { -+ } -+ return; -+} -+ -+void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb) -+{ -+ struct ieee80211_hdr *hdr; -+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); -+ struct ieee80211_sta *sta; -+ struct ssv_sta_info *sta_info = NULL; -+ struct ssv_sta_priv_data *ssv_sta_priv = NULL; -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)info->control.vif->drv_priv; -+ struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data; -+ struct ieee80211_tx_rate *tx_drate; -+ struct ssv_rate_info ssv_rate; -+ int ac, hw_txqid; -+ u32 nav = 0; -+ if (info->flags & IEEE80211_TX_CTL_AMPDU) { -+ struct ampdu_hdr_st *ampdu_hdr = -+ (struct ampdu_hdr_st *)skb->head; -+ sta = ampdu_hdr->ampdu_tid->sta; -+ hdr = -+ (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET + -+ AMPDU_DELIMITER_LEN); -+ } else { -+ struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head; -+ sta = skb_info->sta; -+ hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET); -+ } -+ if (sta) { -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ sta_info = ssv_sta_priv->sta_info; -+ } -+ if ((!sc->bq4_dtim) && -+ (ieee80211_is_mgmt(hdr->frame_control) || -+ ieee80211_is_nullfunc(hdr->frame_control) || -+ ieee80211_is_qos_nullfunc(hdr->frame_control))) { -+ ac = 4; -+ hw_txqid = 4; -+ } else if ((sc->bq4_dtim) && -+ info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { -+ hw_txqid = 4; -+ ac = 4; -+ } else { -+ ac = skb_get_queue_mapping(skb); -+ hw_txqid = sc->tx.hw_txqid[ac]; -+ } -+ tx_drate = &info->control.rates[0]; -+ ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate); -+ tx_desc->len = skb->len; -+ tx_desc->c_type = M2_TXREQ; -+ tx_desc->f80211 = 1; -+ tx_desc->qos = (ieee80211_is_data_qos(hdr->frame_control)) ? 1 : 0; -+ if (tx_drate->flags & IEEE80211_TX_RC_MCS) { -+ if (ieee80211_is_mgmt(hdr->frame_control) && -+ ieee80211_has_order(hdr->frame_control)) -+ tx_desc->ht = 1; -+ } -+ tx_desc->use_4addr = (ieee80211_has_a4(hdr->frame_control)) ? 1 : 0; -+ tx_desc->more_data = -+ (ieee80211_has_morefrags(hdr->frame_control)) ? 1 : 0; -+ tx_desc->stype_b5b4 = (cpu_to_le16(hdr->frame_control) >> 4) & 0x3; -+ tx_desc->frag = (tx_desc->more_data || (hdr->seq_ctrl & 0xf)) ? 1 : 0; -+ tx_desc->unicast = (is_multicast_ether_addr(hdr->addr1)) ? 0 : 1; -+ tx_desc->tx_burst = (tx_desc->frag) ? 1 : 0; -+ tx_desc->wsid = (!sta_info -+ || (sta_info->hw_wsid < 0)) ? 0x0F : sta_info->hw_wsid; -+ tx_desc->txq_idx = hw_txqid; -+ tx_desc->hdr_offset = TXPB_OFFSET; -+ tx_desc->hdr_len = ssv6xxx_frame_hdrlen(hdr, tx_desc->ht); -+ tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len; -+ if (info->control.use_rts) -+ tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS; -+ else if (info->control.use_cts_prot) -+ tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_CTS_PROTECT; -+ if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT) -+ tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS; -+ if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT) { -+ tx_desc->crate_idx = 0; -+ } else -+ tx_desc->crate_idx = ssv_rate.crate_hw_idx; -+ tx_desc->drate_idx = ssv_rate.drate_hw_idx; -+ if (tx_desc->unicast == 0) -+ tx_desc->ack_policy = 1; -+ else if (tx_desc->qos == 1) -+ tx_desc->ack_policy = (*ieee80211_get_qos_ctl(hdr) & 0x60) >> 5; -+ else if (ieee80211_is_ctl(hdr->frame_control)) -+ tx_desc->ack_policy = 1; -+ tx_desc->security = 0; -+ tx_desc->fCmdIdx = 0; -+ tx_desc->fCmd = (hw_txqid + M_ENG_TX_EDCA0); -+ if (info->flags & IEEE80211_TX_CTL_AMPDU) { -+#ifdef AMPDU_HAS_LEADING_FRAME -+ tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_CPU; -+#else -+ tx_desc->RSVD_1 = 1; -+#endif -+ tx_desc->aggregation = 1; -+ tx_desc->ack_policy = 0x01; -+ if ((tx_desc->do_rts_cts == 0) -+ && ((sc->hw->wiphy->rts_threshold == (-1)) -+ || ((skb->len - sc->sh->tx_desc_len) > -+ sc->hw->wiphy->rts_threshold))) { -+ tx_drate->flags |= IEEE80211_TX_RC_USE_RTS_CTS; -+ tx_desc->do_rts_cts = 1; -+ } -+ } -+ if (ieee80211_has_protected(hdr->frame_control) -+ && (ieee80211_is_data_qos(hdr->frame_control) -+ || ieee80211_is_data(hdr->frame_control))) { -+ if ((tx_desc->unicast && ssv_sta_priv -+ && ssv_sta_priv->has_hw_encrypt) -+ || (!tx_desc->unicast && vif_priv -+ && vif_priv->has_hw_encrypt)) { -+ if (!tx_desc->unicast -+ && !list_empty(&vif_priv->sta_list)) { -+ struct ssv_sta_priv_data *one_sta_priv; -+ int hw_wsid; -+ one_sta_priv = -+ list_first_entry(&vif_priv->sta_list, -+ struct ssv_sta_priv_data, -+ list); -+ hw_wsid = one_sta_priv->sta_info->hw_wsid; -+ if (hw_wsid != (-1)) { -+ tx_desc->wsid = hw_wsid; -+ } -+ } -+ tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_ENCRYPT; -+ } else if (ssv_sta_priv->need_sw_encrypt) { -+ } else { -+ } -+ } else { -+ } -+ tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_HWHCI; -+ if (tx_desc->aggregation == 1) { -+ struct ampdu_hdr_st *ampdu_hdr = -+ (struct ampdu_hdr_st *)skb->head; -+ memcpy(&tx_desc->rc_params[0], ampdu_hdr->rates, -+ sizeof(tx_desc->rc_params)); -+ nav = -+ ssv6xxx_set_frame_duration(info, &ssv_rate, -+ (skb->len + FCS_LEN), tx_desc, -+ &tx_desc->rc_params[0], sc); -+#ifdef FW_RC_RETRY_DEBUG -+ { -+ dev_dbg -+ (sc->dev, "[FW_RC]:param[0]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n", -+ tx_desc->rc_params[0].drate, -+ tx_desc->rc_params[0].count, -+ tx_desc->rc_params[0].crate, -+ tx_desc->rc_params[0].dl_length, -+ tx_desc->rc_params[0].frame_consume_time, -+ tx_desc->rc_params[0].rts_cts_nav); -+ dev_dbg -+ (sc->dev, "[FW_RC]:param[1]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n", -+ tx_desc->rc_params[1].drate, -+ tx_desc->rc_params[1].count, -+ tx_desc->rc_params[1].crate, -+ tx_desc->rc_params[1].dl_length, -+ tx_desc->rc_params[1].frame_consume_time, -+ tx_desc->rc_params[1].rts_cts_nav); -+ dev_dbg -+ (sc->dev, "[FW_RC]:param[2]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n", -+ tx_desc->rc_params[2].drate, -+ tx_desc->rc_params[2].count, -+ tx_desc->rc_params[2].crate, -+ tx_desc->rc_params[2].dl_length, -+ tx_desc->rc_params[2].frame_consume_time, -+ tx_desc->rc_params[2].rts_cts_nav); -+ } -+#endif -+ } else { -+ nav = -+ ssv6xxx_set_frame_duration(info, &ssv_rate, -+ (skb->len + FCS_LEN), tx_desc, -+ NULL, NULL); -+ } -+ if ((tx_desc->aggregation == 0)) { -+ if (tx_desc->tx_burst == 0) { -+ if (tx_desc->ack_policy != 0x01) -+ hdr->duration_id = nav; -+ } else { -+ } -+ } -+} -+ -+void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb) -+{ -+ struct ssv6200_tx_desc *tx_desc; -+ skb_push(skb, sc->sh->tx_desc_len); -+ tx_desc = (struct ssv6200_tx_desc *)skb->data; -+ memset((void *)tx_desc, 0, sc->sh->tx_desc_len); -+ ssv6xxx_update_txinfo(sc, skb); -+} -+ -+int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb) -+{ -+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); -+ struct ieee80211_tx_rate *tx_drate; -+ struct ssv_rate_info ssv_rate; -+ tx_drate = &info->control.rates[0]; -+ ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate); -+ return ssv_rate.drate_hw_idx; -+} -+ -+static void _ssv6xxx_tx(struct ieee80211_hw *hw, struct sk_buff *skb) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); -+ struct ieee80211_vif *vif = info->control.vif; -+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; -+ struct ssv6200_tx_desc *tx_desc; -+ int ret; -+ unsigned long flags; -+ bool send_hci = false; -+ do { -+ if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { -+ if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) -+ sc->tx.seq_no += 0x10; -+ hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); -+ hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); -+ } -+ if (info->flags & IEEE80211_TX_CTL_AMPDU) { -+ if (ssv6xxx_get_real_index(sc, skb) < -+ SSV62XX_RATE_MCS_INDEX) { -+ info->flags &= (~IEEE80211_TX_CTL_AMPDU); -+ goto tx_mpdu; -+ } -+ if (ssv6200_ampdu_tx_handler(hw, skb)) { -+ break; -+ } else { -+ info->flags &= (~IEEE80211_TX_CTL_AMPDU); -+ } -+ } -+ tx_mpdu: -+ ssv6xxx_add_txinfo(sc, skb); -+ if (vif && -+ vif->type == NL80211_IFTYPE_AP && -+ (sc->bq4_dtim) && -+ info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { -+ struct ssv_vif_priv_data *priv_vif = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ u8 buffered = 0; -+ spin_lock_irqsave(&sc->ps_state_lock, flags); -+ if (priv_vif->sta_asleep_mask) { -+ buffered = -+ ssv6200_bcast_enqueue(sc, &sc->bcast_txq, -+ skb); -+ if (1 == buffered) { -+ dev_dbg(sc->dev, "ssv6200_tx:ssv6200_bcast_start\n"); -+ ssv6200_bcast_start(sc); -+ } -+ } -+ spin_unlock_irqrestore(&sc->ps_state_lock, flags); -+ if (buffered) -+ break; -+ } -+ if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ dev_dbg(sc->dev, "vif[%d] sc->bq4_dtim[%d]\n", -+ vif_priv->vif_idx, sc->bq4_dtim); -+ } -+ tx_desc = (struct ssv6200_tx_desc *)skb->data; -+ ret = HCI_SEND(sc->sh, skb, tx_desc->txq_idx); -+ send_hci = true; -+ } while (0); -+ if ((skb_queue_len(&sc->tx_skb_q) < LOW_TX_Q_LEN) -+ ) { -+ if (sc->tx.flow_ctrl_status != 0) { -+ int ac; -+ for (ac = 0; ac < sc->hw->queues; ac++) { -+ if ((sc->tx.flow_ctrl_status & BIT(ac)) == 0) -+ ieee80211_wake_queue(sc->hw, ac); -+ } -+ } else { -+ ieee80211_wake_queues(sc->hw); -+ } -+ } -+} -+ -+static void ssv6200_tx(struct ieee80211_hw *hw, -+ struct ieee80211_tx_control *control, -+ struct sk_buff *skb) -+{ -+ struct ssv_softc *sc = (struct ssv_softc *)hw->priv; -+ struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head; -+ skb_info->sta = control ? control->sta : NULL; -+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP -+ skb_info->timestamp = ktime_get(); -+#endif -+ skb_queue_tail(&sc->tx_skb_q, skb); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (sc->max_tx_skb_q_len < skb_queue_len(&sc->tx_skb_q)) -+ sc->max_tx_skb_q_len = skb_queue_len(&sc->tx_skb_q); -+#endif -+ wake_up_interruptible(&sc->tx_wait_q); -+ do { -+ if (skb_queue_len(&sc->tx_skb_q) >= MAX_TX_Q_LEN) -+ ieee80211_stop_queues(sc->hw); -+ } while (0); -+} -+ -+int ssv6xxx_tx_task(void *data) -+{ -+ struct ssv_softc *sc = (struct ssv_softc *)data; -+ u32 wait_period = SSV_AMPDU_timer_period / 2; -+ dev_info(sc->dev, "TX Task started\n"); -+ while (!kthread_should_stop()) { -+ u32 before_timeout = (-1); -+ set_current_state(TASK_INTERRUPTIBLE); -+ before_timeout = wait_event_interruptible_timeout(sc->tx_wait_q, -+ (skb_queue_len -+ (&sc-> -+ tx_skb_q) -+ || -+ kthread_should_stop -+ () -+ || sc-> -+ tx_q_empty), -+ msecs_to_jiffies -+ (wait_period)); -+ if (kthread_should_stop()) { -+ dev_dbg(sc->dev, "Quit TX task loop...\n"); -+ break; -+ } -+ set_current_state(TASK_RUNNING); -+ do { -+ struct sk_buff *tx_skb = skb_dequeue(&sc->tx_skb_q); -+ if (tx_skb == NULL) -+ break; -+ _ssv6xxx_tx(sc->hw, tx_skb); -+ } while (1); -+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP -+ { -+ struct ssv_hw_txq *hw_txq = NULL; -+ struct ieee80211_tx_info *tx_info = NULL; -+ struct sk_buff *skb = NULL; -+ int txqid; -+ unsigned int timeout; -+ u32 status; -+ for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) { -+ hw_txq = &ssv_dbg_ctrl_hci->hw_txq[txqid]; -+ skb = skb_peek(&hw_txq->qhead); -+ if (skb != NULL) { -+ tx_info = IEEE80211_SKB_CB(skb); -+ if (tx_info-> -+ flags & IEEE80211_TX_CTL_AMPDU) -+ timeout = -+ cal_duration_of_ampdu(skb, -+ SKB_DURATION_STAGE_IN_HWQ); -+ else -+ timeout = -+ cal_duration_of_mpdu(skb); -+ if (timeout > SKB_DURATION_TIMEOUT_MS) { -+ HCI_IRQ_STATUS(ssv_dbg_ctrl_hci, -+ &status); -+ dev_dbg(sc->dev, "hci int_mask: %08x\n", -+ ssv_dbg_ctrl_hci-> -+ int_mask); -+ dev_dbg(sc->dev, "sdio status: %08x\n", -+ status); -+ dev_dbg(sc->dev, "hwq%d len: %d\n", txqid, -+ skb_queue_len(&hw_txq-> -+ qhead)); -+ } -+ } -+ } -+ } -+#endif -+ if (sc->tx_q_empty || (before_timeout == 0)) { -+ u32 flused_ampdu = ssv6xxx_ampdu_flush(sc->hw); -+ sc->tx_q_empty = false; -+ if (flused_ampdu == 0 && before_timeout == 0) { -+ wait_period *= 2; -+ if (wait_period > 1000) -+ wait_period = 1000; -+ } -+ } else -+ wait_period = SSV_AMPDU_timer_period / 2; -+ } -+ return 0; -+} -+ -+int ssv6xxx_rx_task(void *data) -+{ -+ struct ssv_softc *sc = (struct ssv_softc *)data; -+ unsigned long wait_period = msecs_to_jiffies(200); -+ unsigned long last_timeout_check_jiffies = jiffies; -+ unsigned long cur_jiffies; -+ dev_info(sc->dev, "RX Task started\n"); -+ while (!kthread_should_stop()) { -+ u32 before_timeout = (-1); -+ set_current_state(TASK_INTERRUPTIBLE); -+ before_timeout = wait_event_interruptible_timeout(sc->rx_wait_q, -+ (skb_queue_len -+ (&sc-> -+ rx_skb_q) -+ || -+ skb_queue_len -+ (&sc-> -+ tx_done_q) -+ || -+ kthread_should_stop -+ ()), -+ wait_period); -+ if (kthread_should_stop()) { -+ dev_dbg(sc->dev, "Quit RX task loop...\n"); -+ break; -+ } -+ set_current_state(TASK_RUNNING); -+ cur_jiffies = jiffies; -+ if ((before_timeout == 0) -+ || time_before((last_timeout_check_jiffies + wait_period), -+ cur_jiffies)) { -+ ssv6xxx_ampdu_check_timeout(sc->hw); -+ last_timeout_check_jiffies = cur_jiffies; -+ } -+ if (skb_queue_len(&sc->rx_skb_q)) -+ _process_rx_q(sc, &sc->rx_skb_q, NULL); -+ if (skb_queue_len(&sc->tx_done_q)) -+ _process_tx_done(sc); -+ } -+ return 0; -+} -+ -+struct ssv6xxx_iqk_cfg init_iqk_cfg = { -+ SSV6XXX_IQK_CFG_XTAL_26M, -+#ifdef CONFIG_SSV_DPD -+ SSV6XXX_IQK_CFG_PA_LI_MPB, -+#else -+ SSV6XXX_IQK_CFG_PA_DEF, -+#endif -+ 0, -+ 0, -+ 26, -+ 3, -+ 0x75, -+ 0x75, -+ 0x80, -+ 0x80, -+ SSV6XXX_IQK_CMD_INIT_CALI, -+ {SSV6XXX_IQK_TEMPERATURE -+ + SSV6XXX_IQK_RXDC -+ + SSV6XXX_IQK_RXRC -+ + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ -+#ifdef CONFIG_SSV_DPD -+ + SSV6XXX_IQK_PAPD -+#endif -+ }, -+}; -+ -+static int ssv6200_start(struct ieee80211_hw *hw) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_hw *sh = sc->sh; -+ struct ieee80211_channel *chan; -+ int ret; -+ -+ mutex_lock(&sc->mutex); -+ ret = ssv6xxx_init_mac(sc->sh); -+ if (ret != 0) { -+ dev_err(sc->dev, "Failed to initialize mac, ret=%d\n", ret); -+ ssv6xxx_deinit_mac(sc); -+ mutex_unlock(&sc->mutex); -+ return -1; -+ } -+#ifdef CONFIG_P2P_NOA -+ ssv6xxx_noa_reset(sc); -+#endif -+ HCI_START(sh); -+ ieee80211_wake_queues(hw); -+ ssv6200_ampdu_init(hw); -+ sc->watchdog_flag = WD_KICKED; -+ mutex_unlock(&sc->mutex); -+ mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT); -+#ifdef CONFIG_SSV_SMARTLINK -+ { -+ extern int ksmartlink_init(void); -+ (void)ksmartlink_init(); -+ } -+#endif -+ ret = ssv6xxx_do_iq_calib(sc->sh, &init_iqk_cfg); -+ if (ret != 0) { -+ dev_err(sc->dev, "IQ Calibration failed, ret=%d\n", ret); -+ return ret; -+ } -+ -+ dev_info(sc->dev, "Calibration successful\n"); -+ -+ SMAC_REG_WRITE(sc->sh, ADR_PHY_EN_1, 0x217f); -+ if ((sh->cfg.chip_identity == SSV6051Z) -+ || (sc->sh->cfg.chip_identity == SSV6051P)) { -+ int i; -+ for (i = 0; i < sh->ch_cfg_size; i++) { -+ SMAC_REG_READ(sh, sh->p_ch_cfg[i].reg_addr, -+ &sh->p_ch_cfg[i].ch1_12_value); -+ } -+ } -+ chan = hw->conf.chandef.chan; -+ sc->cur_channel = chan; -+ dev_dbg(sc->dev, "%s(): current channel: %d,sc->ps_status=%d\n", __FUNCTION__, -+ sc->cur_channel->hw_value, sc->ps_status); -+ ssv6xxx_set_channel(sc, chan->hw_value); -+ ssv6xxx_rf_enable(sh); -+ return 0; -+} -+ -+static void ssv6200_stop(struct ieee80211_hw *hw, bool flag) -+{ -+ struct ssv_softc *sc = hw->priv; -+ u32 count = 0; -+ struct rssi_res_st *rssi_tmp0, *rssi_tmp1; -+ dev_dbg(sc->dev, "%s(): sc->ps_status=%d\n", __FUNCTION__, -+ sc->ps_status); -+ mutex_lock(&sc->mutex); -+ list_for_each_entry_safe(rssi_tmp0, rssi_tmp1, &rssi_res.rssi_list, -+ rssi_list) { -+ list_del(&rssi_tmp0->rssi_list); -+ kfree(rssi_tmp0); -+ } -+ ssv6200_ampdu_deinit(hw); -+ ssv6xxx_rf_disable(sc->sh); -+ HCI_STOP(sc->sh); -+#ifndef NO_USE_RXQ_LOCK -+ while (0) { -+#else -+ while (skb_queue_len(&sc->rx.rxq_head)) { -+#endif -+ dev_dbg(sc->dev, "sc->rx.rxq_count=%d\n", sc->rx.rxq_count); -+ count++; -+ if (count > 90000000) { -+ dev_err(sc->dev, "Could not empty RX queue during shutdown\n"); -+ break; -+ } -+ } -+ HCI_TXQ_FLUSH(sc->sh, (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2 | -+ TXQ_EDCA_3 | TXQ_MGMT)); -+ if ((sc->ps_status == PWRSV_PREPARE) || (sc->ps_status == PWRSV_ENABLE)) { -+ ssv6xxx_enable_ps(sc); -+ ssv6xxx_rf_enable(sc->sh); -+ } -+ sc->watchdog_flag = WD_SLEEP; -+ mutex_unlock(&sc->mutex); -+ del_timer_sync(&sc->watchdog_timeout); -+#ifdef CONFIG_SSV_SMARTLINK -+ { -+ extern void ksmartlink_exit(void); -+ ksmartlink_exit(); -+ } -+#endif -+ dev_dbg(sc->dev, "%s(): leave\n", __FUNCTION__); -+} -+ -+void inline ssv62xxx_set_bssid(struct ssv_softc *sc, u8 * bssid) -+{ -+ memcpy(sc->bssid, bssid, 6); -+ SMAC_REG_WRITE(sc->sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0])); -+ SMAC_REG_WRITE(sc->sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4])); -+} -+ -+struct ssv_vif_priv_data *ssv6xxx_config_vif_res(struct ssv_softc *sc, -+ struct ieee80211_vif *vif) -+{ -+ int i; -+ struct ssv_vif_priv_data *priv_vif; -+ struct ssv_vif_info *vif_info; -+ lockdep_assert_held(&sc->mutex); -+ for (i = 0; i < SSV6200_MAX_VIF; i++) { -+ if (sc->vif_info[i].vif == NULL) -+ break; -+ } -+ BUG_ON(i >= SSV6200_MAX_VIF); -+ dev_dbg(sc->dev, "ssv6xxx_config_vif_res id[%d].\n", i); -+ priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv; -+ memset(priv_vif, 0, sizeof(struct ssv_vif_priv_data)); -+ priv_vif->vif_idx = i; -+ memset(&sc->vif_info[i], 0, sizeof(sc->vif_info[0])); -+ sc->vif_info[i].vif = vif; -+ sc->vif_info[i].vif_priv = priv_vif; -+ INIT_LIST_HEAD(&priv_vif->sta_list); -+ priv_vif->pair_cipher = SSV_CIPHER_NONE; -+ priv_vif->group_cipher = SSV_CIPHER_NONE; -+ priv_vif->has_hw_decrypt = false; -+ priv_vif->has_hw_encrypt = false; -+ priv_vif->need_sw_encrypt = false; -+ priv_vif->need_sw_decrypt = false; -+ priv_vif->use_mac80211_decrypt = false; -+ priv_vif->is_security_valid = false; -+ priv_vif->force_sw_encrypt = (vif->type == NL80211_IFTYPE_AP); -+ vif_info = &sc->vif_info[priv_vif->vif_idx]; -+ vif_info->if_type = vif->type; -+ vif_info->vif = vif; -+ return priv_vif; -+} -+ -+static int ssv6200_add_interface(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif) -+{ -+ struct ssv_softc *sc = hw->priv; -+ int ret = 0; -+ struct ssv_vif_priv_data *vif_priv = NULL; -+ dev_dbg(sc->dev, "[I] %s(): vif->type = %d, NL80211_IFTYPE_AP=%d\n", __FUNCTION__, -+ vif->type, NL80211_IFTYPE_AP); -+ if ((sc->nvif >= SSV6200_MAX_VIF) -+ || (((vif->type == NL80211_IFTYPE_AP) -+ || (vif->p2p)) -+ && (sc->ap_vif != NULL))) { -+ dev_err(sc->dev, "Add interface of type %d (p2p: %d) failed.\n", -+ vif->type, vif->p2p); -+ return -EOPNOTSUPP; -+ } -+ mutex_lock(&sc->mutex); -+ vif_priv = ssv6xxx_config_vif_res(sc, vif); -+ if ((vif_priv->vif_idx == 0) && (vif->p2p == 0) -+ && (vif->type == NL80211_IFTYPE_AP)) { -+ dev_dbg(sc->dev, "VIF[0] set bssid and config opmode to ap\n"); -+ ssv62xxx_set_bssid(sc, sc->sh->cfg.maddr[0]); -+ SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_AP, -+ OP_MODE_MSK); -+ } -+ if (vif->type == NL80211_IFTYPE_AP) { -+ BUG_ON(sc->ap_vif != NULL); -+ sc->ap_vif = vif; -+ if (!vif->p2p && (vif_priv->vif_idx == 0)) { -+ dev_dbg(sc->dev, "Normal AP mode. Config Q4 to DTIM Q.\n"); -+ SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC, -+ MTX_HALT_MNG_UNTIL_DTIM_MSK, -+ MTX_HALT_MNG_UNTIL_DTIM_MSK); -+ sc->bq4_dtim = true; -+ } -+ } -+ sc->nvif++; -+ dev_dbg(sc->dev, -+ "VIF %02x:%02x:%02x:%02x:%02x:%02x of type %d is added.\n", -+ vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3], -+ vif->addr[4], vif->addr[5], vif->type); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ ssv6xxx_debugfs_add_interface(sc, vif); -+#endif -+ mutex_unlock(&sc->mutex); -+ return ret; -+} -+ -+static void ssv6200_remove_interface(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ dev_err(sc->dev, -+ "Removing interface %02x:%02x:%02x:%02x:%02x:%02x. PS=%d\n", -+ vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3], -+ vif->addr[4], vif->addr[5], sc->ps_status); -+ mutex_lock(&sc->mutex); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ ssv6xxx_debugfs_remove_interface(sc, vif); -+#endif -+ if (vif->type == NL80211_IFTYPE_AP) { -+ if (sc->bq4_dtim) { -+ sc->bq4_dtim = false; -+ ssv6200_release_bcast_frame_res(sc, vif); -+ SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC, -+ 0, MTX_HALT_MNG_UNTIL_DTIM_MSK); -+ dev_dbg(sc->dev, "Config Q4 to normal Q \n"); -+ } -+ ssv6xxx_beacon_release(sc); -+ sc->ap_vif = NULL; -+ } -+ memset(&sc->vif_info[vif_priv->vif_idx], 0, -+ sizeof(struct ssv_vif_info)); -+ sc->nvif--; -+ mutex_unlock(&sc->mutex); -+} -+ -+static int ssv6200_change_interface(struct ieee80211_hw *dev, -+ struct ieee80211_vif *vif, -+ enum nl80211_iftype new_type, bool p2p) -+{ -+ struct ssv_softc *sc = dev->priv; -+ int ret = 0; -+ -+ dev_dbg(sc->dev, "change_interface new: %d (%d), old: %d (%d)\n", new_type, -+ p2p, vif->type, vif->p2p); -+ -+ if (new_type != vif->type || vif->p2p != p2p) { -+ ssv6200_remove_interface(dev, vif); -+ vif->type = new_type; -+ vif->p2p = p2p; -+ ret = ssv6200_add_interface(dev, vif); -+ } -+ -+ return ret; -+} -+ -+void ssv6xxx_ps_callback_func(unsigned long data) -+{ -+ struct ssv_softc *sc = (struct ssv_softc *)data; -+ struct sk_buff *skb; -+ struct cfg_host_cmd *host_cmd; -+ int retry_cnt = 20; -+#ifdef SSV_WAKEUP_HOST -+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG, -+ M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8)); -+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, -+ M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8)); -+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4, -+ (sc->mac_deci_tbl[6] | 1)); -+#else -+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG, -+ M_ENG_MACRX | (M_ENG_TRASH_CAN << 4)); -+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, -+ M_ENG_MACRX | (M_ENG_TRASH_CAN << 4)); -+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG, -+ M_ENG_MACRX | (M_ENG_TRASH_CAN << 4)); -+#endif -+ skb = ssv_skb_alloc(sizeof(struct cfg_host_cmd)); -+ skb->data_len = sizeof(struct cfg_host_cmd); -+ skb->len = skb->data_len; -+ host_cmd = (struct cfg_host_cmd *)skb->data; -+ host_cmd->c_type = HOST_CMD; -+ host_cmd->RSVD0 = 0; -+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS; -+ host_cmd->len = skb->data_len; -+#ifdef SSV_WAKEUP_HOST -+ host_cmd->dummy = sc->ps_aid; -+#else -+ host_cmd->dummy = 0; -+#endif -+ sc->ps_aid = 0; -+ while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) { -+ dev_warn(sc->dev, "PS cmd retry=%d!!\n", retry_cnt); -+ retry_cnt--; -+ } -+ ssv_skb_free(skb); -+ dev_dbg(sc->dev, "SSV6XXX_HOST_CMD_PS,ps_aid = %d,len=%d,tabl=0x%x\n", -+ host_cmd->dummy, skb->len, (sc->mac_deci_tbl[6] | 1)); -+} -+ -+void ssv6xxx_enable_ps(struct ssv_softc *sc) -+{ -+ sc->ps_status = PWRSV_ENABLE; -+} -+ -+void ssv6xxx_disable_ps(struct ssv_softc *sc) -+{ -+ sc->ps_status = PWRSV_DISABLE; -+ dev_info(sc->dev, "Power saving disabled\n"); -+} -+ -+int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag) -+{ -+ struct sk_buff *skb; -+ struct cfg_host_cmd *host_cmd; -+ int ret = 0; -+ dev_dbg(sh->sc->dev, "ssv6xxx_watchdog_controller %d\n", flag); -+ skb = ssv_skb_alloc(HOST_CMD_HDR_LEN); -+ if (skb == NULL) { -+ dev_warn(sh->sc->dev, "init ssv6xxx_watchdog_controller fail!!!\n"); -+ return (-1); -+ } -+ skb->data_len = HOST_CMD_HDR_LEN; -+ skb->len = skb->data_len; -+ host_cmd = (struct cfg_host_cmd *)skb->data; -+ host_cmd->c_type = HOST_CMD; -+ host_cmd->h_cmd = (u8) flag; -+ host_cmd->len = skb->data_len; -+ sh->hci.hci_ops->hci_send_cmd(skb); -+ ssv_skb_free(skb); -+ return ret; -+} -+ -+static int ssv6200_config(struct ieee80211_hw *hw, u32 changed) -+{ -+ struct ssv_softc *sc = hw->priv; -+ int ret = 0; -+ mutex_lock(&sc->mutex); -+ if (changed & IEEE80211_CONF_CHANGE_PS) { -+ struct ieee80211_conf *conf = &hw->conf; -+ if (conf->flags & IEEE80211_CONF_PS) { -+ dev_dbg(sc->dev, "Enable IEEE80211_CONF_PS ps_aid=%d\n", -+ sc->ps_aid); -+ } else { -+ dev_dbg(sc->dev, "Disable IEEE80211_CONF_PS ps_aid=%d\n", -+ sc->ps_aid); -+ } -+ } -+ if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { -+ struct ieee80211_channel *chan; -+ chan = hw->conf.chandef.chan; -+#ifdef CONFIG_P2P_NOA -+ if (sc->p2p_noa.active_noa_vif) { -+ dev_dbg(sc->dev, "NOA operating-active vif[%02x] skip scan\n", -+ sc->p2p_noa.active_noa_vif); -+ goto out; -+ } -+#endif -+ if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) { -+ if ((sc->ap_vif == NULL) -+ || -+ list_empty(& -+ ((struct ssv_vif_priv_data *)sc->ap_vif-> -+ drv_priv)->sta_list)) { -+ HCI_PAUSE(sc->sh, -+ (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2 -+ | TXQ_EDCA_3 | TXQ_MGMT)); -+ sc->sc_flags |= SC_OP_OFFCHAN; -+ ssv6xxx_set_channel(sc, chan->hw_value); -+ sc->hw_chan = chan->hw_value; -+ HCI_RESUME(sc->sh, TXQ_MGMT); -+ } else { -+ dev_dbg(sc->dev, -+ "Off-channel to %d is ignored when AP mode enabled.\n", -+ chan->hw_value); -+ } -+ } else { -+ if ((sc->cur_channel == NULL) -+ || (sc->sc_flags & SC_OP_OFFCHAN) -+ || (sc->hw_chan != chan->hw_value)) { -+ HCI_PAUSE(sc->sh, -+ (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2 -+ | TXQ_EDCA_3 | TXQ_MGMT)); -+ ssv6xxx_set_channel(sc, chan->hw_value); -+ sc->cur_channel = chan; -+ HCI_RESUME(sc->sh, -+ (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2 -+ | TXQ_EDCA_3 | TXQ_MGMT)); -+ sc->sc_flags &= ~SC_OP_OFFCHAN; -+ } else { -+ dev_dbg(sc->dev, -+ "Change to the same channel %d\n", -+ chan->hw_value); -+ } -+ } -+ } -+#ifdef CONFIG_P2P_NOA -+ out: -+#endif -+ mutex_unlock(&sc->mutex); -+ return ret; -+} -+ -+#define SUPPORTED_FILTERS \ -+ (FIF_ALLMULTI | \ -+ FIF_CONTROL | \ -+ FIF_PSPOLL | \ -+ FIF_OTHER_BSS | \ -+ FIF_BCN_PRBRESP_PROMISC | \ -+ FIF_PROBE_REQ | \ -+ FIF_FCSFAIL) -+static void ssv6200_config_filter(struct ieee80211_hw *hw, -+ unsigned int changed_flags, -+ unsigned int *total_flags, u64 multicast) -+{ -+ changed_flags &= SUPPORTED_FILTERS; -+ *total_flags &= SUPPORTED_FILTERS; -+} -+ -+static void ssv6200_bss_info_changed(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif, -+ struct ieee80211_bss_conf *info, -+ u64 changed) -+{ -+ struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv; -+ struct ssv_softc *sc = hw->priv; -+#ifdef CONFIG_P2P_NOA -+ u8 null_address[6] = { 0 }; -+#endif -+ mutex_lock(&sc->mutex); -+ if (changed & BSS_CHANGED_ERP_PREAMBLE) { -+ dev_dbg(sc->dev, "BSS Changed use_short_preamble[%d]\n", -+ info->use_short_preamble); -+ if (info->use_short_preamble) -+ sc->sc_flags |= SC_OP_SHORT_PREAMBLE; -+ else -+ sc->sc_flags &= ~SC_OP_SHORT_PREAMBLE; -+ } -+ if (!priv_vif->vif_idx) { -+ if (changed & BSS_CHANGED_BSSID) { -+#ifdef CONFIG_P2P_NOA -+ struct ssv_vif_priv_data *vif_priv; -+ vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv; -+#endif -+ ssv62xxx_set_bssid(sc, (u8 *) info->bssid); -+ dev_dbg(sc->dev, "BSS_CHANGED_BSSID: %02x:%02x:%02x:%02x:%02x:%02x\n", -+ info->bssid[0], info->bssid[1], info->bssid[2], -+ info->bssid[3], info->bssid[4], info->bssid[5]); -+#ifdef CONFIG_P2P_NOA -+ if (memcmp(info->bssid, null_address, 6)) -+ ssv6xxx_noa_hdl_bss_change(sc, -+ MONITOR_NOA_CONF_ADD, -+ vif_priv->vif_idx); -+ else -+ ssv6xxx_noa_hdl_bss_change(sc, -+ MONITOR_NOA_CONF_REMOVE, -+ vif_priv->vif_idx); -+#endif -+ } -+ if (changed & BSS_CHANGED_ERP_SLOT) { -+ u32 regval = 0; -+ dev_dbg(sc->dev, "BSS_CHANGED_ERP_SLOT: use_short_slot[%d]\n", -+ info->use_short_slot); -+ if (info->use_short_slot) { -+ SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, ®val); -+ regval = regval & MTX_DUR_SLOT_I_MSK; -+ regval |= 9 << MTX_DUR_SLOT_SFT; -+ SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval); -+ SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G, -+ ®val); -+ regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK; -+ regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT; -+ regval = regval & MTX_DUR_SLOT_G_I_MSK; -+ regval |= 9 << MTX_DUR_SLOT_G_SFT; -+ SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G, -+ regval); -+ } else { -+ SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, ®val); -+ regval = regval & MTX_DUR_SLOT_I_MSK; -+ regval |= 20 << MTX_DUR_SLOT_SFT; -+ SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval); -+ SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G, -+ ®val); -+ regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK; -+ regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT; -+ regval = regval & MTX_DUR_SLOT_G_I_MSK; -+ regval |= 20 << MTX_DUR_SLOT_G_SFT; -+ SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G, -+ regval); -+ } -+ } -+ } -+ if (changed & BSS_CHANGED_HT) { -+ dev_dbg(sc->dev, "BSS_CHANGED_HT: Untreated!!\n"); -+ } -+ if (changed & BSS_CHANGED_BASIC_RATES) { -+ dev_dbg(sc->dev, "ssv6xxx_rc_update_basic_rate!!\n"); -+ ssv6xxx_rc_update_basic_rate(sc, info->basic_rates); -+ } -+ if (vif->type == NL80211_IFTYPE_STATION) { -+ dev_dbg(sc->dev, "NL80211_IFTYPE_STATION!!\n"); -+ if ((changed & BSS_CHANGED_ASSOC) && (vif->p2p == 0)) { -+ sc->isAssoc = vif->cfg.assoc; -+ if (!sc->isAssoc) { -+ sc->channel_center_freq = 0; -+ sc->ps_aid = 0; -+#ifdef CONFIG_SSV_MRX_EN3_CTRL -+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400); -+#endif -+ SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL, -+ 0x0); -+ } else { -+ struct ieee80211_channel *curchan; -+ curchan = hw->conf.chandef.chan; -+ sc->channel_center_freq = curchan->center_freq; -+ dev_dbg(sc->dev, "info->aid = %d\n", vif->cfg.aid); -+ sc->ps_aid = vif->cfg.aid; -+#ifdef CONFIG_SSV_MRX_EN3_CTRL -+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000); -+#endif -+ } -+ } -+#ifdef CONFIG_SSV_MRX_EN3_CTRL -+ else if ((changed & BSS_CHANGED_ASSOC) && vif->p2p == 1) { -+ if (info->assoc) -+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400); -+ else if (sc->ps_aid != 0) -+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000); -+ } -+#endif -+ } -+ if (vif->type == NL80211_IFTYPE_AP) { -+ if (changed & (BSS_CHANGED_BEACON -+ | BSS_CHANGED_SSID -+ | BSS_CHANGED_BSSID | BSS_CHANGED_BASIC_RATES)) { -+#ifdef BROADCAST_DEBUG -+ dev_dbg(sc->dev, "[A] ssv6200_bss_info_changed:beacon changed\n"); -+#endif -+ queue_work(sc->config_wq, &sc->set_tim_work); -+ } -+ if (changed & BSS_CHANGED_BEACON_INT) { -+ dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_INT beacon_interval(%d)\n", -+ info->beacon_int); -+ if (sc->beacon_interval != info->beacon_int) { -+ sc->beacon_interval = info->beacon_int; -+ ssv6xxx_beacon_set_info(sc, sc->beacon_interval, -+ sc->beacon_dtim_cnt); -+ } -+ } -+ if (changed & BSS_CHANGED_BEACON_ENABLED) { -+#ifdef BEACON_DEBUG -+ dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_ENABLED (0x%x)\n", -+ info->enable_beacon); -+#endif -+ if (0 != ssv6xxx_beacon_enable(sc, info->enable_beacon)) { -+ dev_err(sc->dev, "Beacon enable %d error.\n", -+ info->enable_beacon); -+ } -+ } -+ } -+ mutex_unlock(&sc->mutex); -+ dev_dbg(sc->dev, "[I] %s(): leave\n", __FUNCTION__); -+} -+ -+static int ssv6200_sta_add(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif, struct ieee80211_sta *sta) -+{ -+ struct ssv_sta_priv_data *sta_priv_dat = NULL; -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_sta_info *sta_info; -+ u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 }; -+ int s, i; -+ u32 reg_wsid_tid0[] = { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ }; -+ u32 reg_wsid_tid7[] = { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ }; -+ unsigned long flags; -+ int ret = 0; -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ int fw_sec_caps = SSV6XXX_WSID_SEC_NONE; -+ bool tdls_use_sw_cipher = false, tdls_link = false; -+ dev_dbg(sc->dev, "[I] %s(): vif[%d] ", __FUNCTION__, vif_priv->vif_idx); -+ if (sc->force_triger_reset == true) { -+ vif_priv->sta_asleep_mask = 0; -+ do { -+ spin_lock_irqsave(&sc->ps_state_lock, flags); -+ for (s = 0; s < SSV_NUM_STA; s++, sta_info++) { -+ sta_info = &sc->sta_info[s]; -+ if ((sta_info->s_flags & STA_FLAG_VALID)) { -+ if (sta_info->sta == sta) { -+ dev_dbg -+ (sc->dev, "search stat %02x:%02x:%02x:%02x:%02x:%02x to wsid=%d\n", -+ sta->addr[0], sta->addr[1], -+ sta->addr[2], sta->addr[3], -+ sta->addr[4], sta->addr[5], -+ sta_info->hw_wsid); -+ spin_unlock_irqrestore(&sc-> -+ ps_state_lock, -+ flags); -+ return ret; -+ } -+ } -+ } -+ spin_unlock_irqrestore(&sc->ps_state_lock, flags); -+ if (s >= SSV_NUM_STA) { -+ break; -+ } -+ } while (0); -+ } -+ do { -+ spin_lock_irqsave(&sc->ps_state_lock, flags); -+ if (!list_empty(&vif_priv->sta_list) -+ && vif->type == NL80211_IFTYPE_STATION) { -+ tdls_link = true; -+ } -+ if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_NONE) -+ && (vif_priv->pair_cipher != SSV_CIPHER_CCMP) -+ && (sc->sh->cfg.use_wpa2_only == false)) { -+ tdls_use_sw_cipher = true; -+ } -+ if (((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false)) -+ || sc->sh->cfg.use_wpa2_only) -+ s = 0; -+ else -+ s = 2; -+ for (; s < SSV_NUM_STA; s++) { -+ sta_info = &sc->sta_info[s]; -+ if ((sta_info->s_flags & STA_FLAG_VALID) == 0) { -+ sta_info->aid = sta->aid; -+ sta_info->sta = sta; -+ sta_info->vif = vif; -+ sta_info->s_flags = STA_FLAG_VALID; -+ sta_priv_dat = -+ (struct ssv_sta_priv_data *)sta->drv_priv; -+ sta_priv_dat->sta_idx = s; -+ sta_priv_dat->sta_info = sta_info; -+ sta_priv_dat->has_hw_encrypt = false; -+ sta_priv_dat->has_hw_decrypt = false; -+ sta_priv_dat->need_sw_decrypt = false; -+ sta_priv_dat->need_sw_encrypt = false; -+ sta_priv_dat->use_mac80211_decrypt = false; -+ if ((vif_priv->pair_cipher == SSV_CIPHER_WEP40) -+ || (vif_priv->pair_cipher == -+ SSV_CIPHER_WEP104)) { -+ sta_priv_dat->has_hw_encrypt = -+ vif_priv->has_hw_encrypt; -+ sta_priv_dat->has_hw_decrypt = -+ vif_priv->has_hw_decrypt; -+ sta_priv_dat->need_sw_encrypt = -+ vif_priv->need_sw_encrypt; -+ sta_priv_dat->need_sw_decrypt = -+ vif_priv->need_sw_decrypt; -+ } -+ list_add_tail(&sta_priv_dat->list, -+ &vif_priv->sta_list); -+ break; -+ } -+ } -+ spin_unlock_irqrestore(&sc->ps_state_lock, flags); -+ if (s >= SSV_NUM_STA) { -+ dev_err(sc->dev, -+ "Number of STA exceeds driver limitation %d\n.", -+ SSV_NUM_STA); -+ ret = -1; -+ break; -+ } -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ ssv6xxx_debugfs_add_sta(sc, sta_info); -+#endif -+ sta_info->hw_wsid = -1; -+ if (sta_priv_dat->sta_idx < SSV_NUM_HW_STA) { -+ SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 4, -+ *((u32 *) & sta->addr[0])); -+ SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 8, -+ *((u32 *) & sta->addr[4])); -+ SMAC_REG_WRITE(sc->sh, reg_wsid[s], 1); -+ for (i = reg_wsid_tid0[s]; i <= reg_wsid_tid7[s]; -+ i += 4) -+ SMAC_REG_WRITE(sc->sh, i, 0); -+ ssv6xxx_rc_hw_reset(sc, sta_priv_dat->rc_idx, s); -+ sta_info->hw_wsid = sta_priv_dat->sta_idx; -+ } else if ((vif_priv->vif_idx == 0) -+ || sc->sh->cfg.use_wpa2_only) { -+ sta_info->hw_wsid = sta_priv_dat->sta_idx; -+ } -+ if ((sta_priv_dat->has_hw_encrypt -+ || sta_priv_dat->has_hw_decrypt) -+ && ((vif_priv->pair_cipher == SSV_CIPHER_WEP40) -+ || (vif_priv->pair_cipher == SSV_CIPHER_WEP104))) { -+ struct ssv_vif_info *vif_info = -+ &sc->vif_info[vif_priv->vif_idx]; -+ struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey; -+ _set_wep_hw_crypto_pair_key(sc, vif_info, sta_info, -+ (void *)sramKey); -+ if (sramKey->sta_key[0].pair_key_idx != 0) { -+ _set_wep_hw_crypto_group_key(sc, vif_info, -+ sta_info, -+ (void *)sramKey); -+ } -+ } -+ ssv6200_ampdu_tx_add_sta(hw, sta); -+ if (sta_info->hw_wsid >= SSV_NUM_HW_STA) { -+ if (sta_priv_dat->has_hw_decrypt) -+ fw_sec_caps = SSV6XXX_WSID_SEC_PAIRWISE; -+ if (vif_priv->has_hw_decrypt) -+ fw_sec_caps |= SSV6XXX_WSID_SEC_GROUP; -+ hw_update_watch_wsid(sc, sta, sta_info, -+ sta_priv_dat->sta_idx, fw_sec_caps, -+ SSV6XXX_WSID_OPS_ADD); -+ } else if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)) { -+ hw_update_watch_wsid(sc, sta, sta_info, -+ sta_priv_dat->sta_idx, -+ SSV6XXX_WSID_SEC_SW, -+ SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE); -+ hw_update_watch_wsid(sc, sta, sta_info, -+ sta_priv_dat->sta_idx, -+ SSV6XXX_WSID_SEC_SW, -+ SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE); -+ } -+ dev_dbg -+ (sc->dev, "Add %02x:%02x:%02x:%02x:%02x:%02x to VIF %d sw_idx=%d, wsid=%d\n", -+ sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3], -+ sta->addr[4], sta->addr[5], vif_priv->vif_idx, -+ sta_priv_dat->sta_idx, sta_info->hw_wsid); -+ } while (0); -+ return ret; -+} -+ -+void ssv6200_rx_flow_check(struct ssv_sta_priv_data *sta_priv_dat, -+ struct ssv_softc *sc) -+{ -+ if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx) -+ && (sta_priv_dat->need_sw_decrypt)) { -+ int other_hw_wsid = (sta_priv_dat->sta_idx + 1) & 1; -+ struct ssv_sta_info *sta_info = &sc->sta_info[other_hw_wsid]; -+ struct ieee80211_sta *sta = sta_info->sta; -+ struct ssv_sta_priv_data *sta_priv = -+ (struct ssv_sta_priv_data *)sta->drv_priv; -+ mutex_lock(&sc->mutex); -+ if ((sta_info->s_flags == 0) -+ || ((sta_info->s_flags && STA_FLAG_VALID) -+ && (sta_priv->has_hw_decrypt))) { -+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, -+ M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) | -+ (M_ENG_HWHCI << 8)); -+ dev_dbg(sc->dev, "redirect Rx flow for sta %d disconnect\n", -+ sta_priv_dat->sta_idx); -+ } -+ mutex_unlock(&sc->mutex); -+ } -+} -+ -+static int ssv6200_sta_remove(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif, -+ struct ieee80211_sta *sta) -+{ -+ u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 }; -+ struct ssv_sta_priv_data *sta_priv_dat = -+ (struct ssv_sta_priv_data *)sta->drv_priv; -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_sta_info *sta_info = sta_priv_dat->sta_info; -+ unsigned long flags; -+ u32 bit; -+ struct ssv_vif_priv_data *priv_vif = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ u8 hw_wsid = -1; -+ BUG_ON(sta_priv_dat->sta_idx >= SSV_NUM_STA); -+ dev_notice(sc->dev, -+ "Removing STA %d (%02X:%02X:%02X:%02X:%02X:%02X) from VIF %d\n.", -+ sta_priv_dat->sta_idx, sta->addr[0], sta->addr[1], -+ sta->addr[2], sta->addr[3], sta->addr[4], sta->addr[5], -+ priv_vif->vif_idx); -+ ssv6200_rx_flow_check(sta_priv_dat, sc); -+ spin_lock_irqsave(&sc->ps_state_lock, flags); -+ bit = BIT(sta_priv_dat->sta_idx); -+ priv_vif->sta_asleep_mask &= ~bit; -+ if (sta_info->hw_wsid != -1) { -+ hw_wsid = sta_info->hw_wsid; -+ } -+ if (sta_info->hw_wsid >= SSV_NUM_HW_STA) { -+ spin_unlock_irqrestore(&sc->ps_state_lock, flags); -+ hw_update_watch_wsid(sc, sta, sta_info, sta_info->hw_wsid, 0, -+ SSV6XXX_WSID_OPS_DEL); -+ spin_lock_irqsave(&sc->ps_state_lock, flags); -+ } -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ { -+ ssv6xxx_debugfs_remove_sta(sc, sta_info); -+ } -+#endif -+ memset(sta_info, 0, sizeof(*sta_info)); -+ sta_priv_dat->sta_idx = -1; -+ list_del(&sta_priv_dat->list); -+ if (list_empty(&priv_vif->sta_list) -+ && vif->type == NL80211_IFTYPE_STATION) { -+ priv_vif->pair_cipher = 0; -+ priv_vif->group_cipher = 0; -+ } -+ spin_unlock_irqrestore(&sc->ps_state_lock, flags); -+ if ((hw_wsid != -1) && (hw_wsid < SSV_NUM_HW_STA)) -+ SMAC_REG_WRITE(sc->sh, reg_wsid[hw_wsid], 0x00); -+ return 0; -+} -+ -+static void ssv6200_sta_notify(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif, -+ enum sta_notify_cmd cmd, -+ struct ieee80211_sta *sta) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_vif_priv_data *priv_vif = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ struct ssv_sta_priv_data *sta_priv_dat = -+ sta != NULL ? (struct ssv_sta_priv_data *)sta->drv_priv : NULL; -+ struct ssv_sta_info *sta_info; -+ u32 bit, prev; -+ unsigned long flags; -+ spin_lock_irqsave(&sc->ps_state_lock, flags); -+ if (sta_priv_dat != NULL) { -+ bit = BIT(sta_priv_dat->sta_idx); -+ prev = priv_vif->sta_asleep_mask & bit; -+ sta_info = sta_priv_dat->sta_info; -+ switch (cmd) { -+ case STA_NOTIFY_SLEEP: -+ if (!prev) { -+ sta_info->sleeping = true; -+ if ((vif->type == NL80211_IFTYPE_AP) -+ && sc->bq4_dtim -+ && !priv_vif->sta_asleep_mask -+ && ssv6200_bcast_queue_len(&sc-> -+ bcast_txq)) { -+ dev_dbg(sc->dev, "%s(): ssv6200_bcast_start\n", __FUNCTION__); -+ ssv6200_bcast_start(sc); -+ } -+ priv_vif->sta_asleep_mask |= bit; -+ } -+ break; -+ case STA_NOTIFY_AWAKE: -+ if (prev) { -+ sta_info->sleeping = false; -+ priv_vif->sta_asleep_mask &= ~bit; -+ } -+ break; -+ default: -+ break; -+ } -+ } -+ spin_unlock_irqrestore(&sc->ps_state_lock, flags); -+} -+ -+static u64 ssv6200_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) -+{ -+ return jiffies * 1000 * 1000 / HZ; -+} -+ -+static u64 ssv6200_get_systime_us(void) -+{ -+#if LINUX_VERSION_CODE > KERNEL_VERSION(4,19,0) -+ struct timespec64 ts; -+ ktime_get_boottime_ts64(&ts); -+#else -+ struct timespec ts; -+ get_monotonic_boottime(&ts); -+#endif -+ return ((u64) ts.tv_sec * 1000000) + ts.tv_nsec / 1000; -+} -+ -+static u32 pre_11b_cca_control; -+static u32 pre_11b_cca_1; -+static void ssv6200_sw_scan_start(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif, -+ const u8 * mac_addr) -+{ -+ ((struct ssv_softc *)(hw->priv))->bScanning = true; -+ SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh, -+ ADR_RX_11B_CCA_CONTROL, &pre_11b_cca_control); -+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, -+ ADR_RX_11B_CCA_CONTROL, 0x0); -+ SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1, -+ &pre_11b_cca_1); -+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1, -+ RX_11B_CCA_IN_SCAN); -+#ifdef CONFIG_SSV_MRX_EN3_CTRL -+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_MRX_FLT_EN3, -+ 0x0400); -+#endif -+} -+ -+static void ssv6200_sw_scan_complete(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif) -+{ -+ -+#ifdef CONFIG_SSV_MRX_EN3_CTRL -+ bool is_p2p_assoc; -+#endif -+ ((struct ssv_softc *)(hw->priv))->bScanning = false; -+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, -+ ADR_RX_11B_CCA_CONTROL, pre_11b_cca_control); -+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1, -+ pre_11b_cca_1); -+#ifdef CONFIG_SSV_MRX_EN3_CTRL -+ is_p2p_assoc = -+ ((struct ssv_softc *)(hw->priv))->vif_info[1].vif->bss_conf.assoc; -+ if (((struct ssv_softc *)(hw->priv))->ps_aid != 0 && (!is_p2p_assoc)) -+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, -+ ADR_MRX_FLT_EN3, 0x1000); -+#endif -+} -+ -+static int ssv6200_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, -+ bool set) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_sta_info *sta_info = sta -+ ? ((struct ssv_sta_priv_data *)sta->drv_priv)->sta_info : NULL; -+ if (sta_info && (sta_info->tim_set ^ set)) { -+ dev_dbg(sc->dev, "[I] [A] ssvcabrio_set_tim"); -+ sta_info->tim_set = set; -+ queue_work(sc->config_wq, &sc->set_tim_work); -+ } -+ return 0; -+} -+ -+static int ssv6200_conf_tx(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif, u32 link_id, u16 queue, -+ const struct ieee80211_tx_queue_params *params) -+{ -+ struct ssv_softc *sc = hw->priv; -+ u32 cw; -+ u8 hw_txqid = sc->tx.hw_txqid[queue]; -+ struct ssv_vif_priv_data *priv_vif = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ dev_dbg -+ (sc->dev, "[I] sv6200_conf_tx vif[%d] qos[%d] queue[%d] aifsn[%d] cwmin[%d] cwmax[%d] txop[%d] \n", -+ priv_vif->vif_idx, vif->bss_conf.qos, queue, params->aifs, -+ params->cw_min, params->cw_max, params->txop); -+ if (queue > NL80211_TXQ_Q_BK) -+ return 1; -+ if (priv_vif->vif_idx != 0) { -+ dev_warn(sc->dev, -+ "WMM setting applicable to primary interface only.\n"); -+ return 1; -+ } -+ mutex_lock(&sc->mutex); -+ SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, -+ (vif->bss_conf.qos << QOS_EN_SFT), QOS_EN_MSK); -+ cw = (params->aifs - 1) & 0xf; -+ cw |= ((ilog2(params->cw_min + 1)) & 0xf) << TXQ1_MTX_Q_ECWMIN_SFT; -+ cw |= ((ilog2(params->cw_max + 1)) & 0xf) << TXQ1_MTX_Q_ECWMAX_SFT; -+ cw |= ((params->txop) & 0xff) << TXQ1_MTX_Q_TXOP_LIMIT_SFT; -+ SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_AIFSN + 0x100 * hw_txqid, cw); -+ mutex_unlock(&sc->mutex); -+ return 0; -+} -+ -+static int ssv6200_ampdu_action(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif, -+ struct ieee80211_ampdu_params *params) -+{ -+ struct ssv_softc *sc = hw->priv; -+ int ret = 0; -+ struct ieee80211_sta *sta = params->sta; -+ enum ieee80211_ampdu_mlme_action action = params->action; -+ u16 tid = params->tid; -+ u16 *ssn = &(params->ssn); -+ u8 buf_size = params->buf_size; -+ if (sta == NULL) -+ return ret; -+#if (!Enable_AMPDU_Rx) -+ if (action == IEEE80211_AMPDU_RX_START -+ || action == IEEE80211_AMPDU_RX_STOP) { -+ ampdu_db_log("Disable AMPDU_RX for test(1).\n"); -+ return -EOPNOTSUPP; -+ } -+#endif -+#if (!Enable_AMPDU_Tx) -+ if (action == IEEE80211_AMPDU_TX_START -+ || action == IEEE80211_AMPDU_TX_STOP -+ || action == IEEE80211_AMPDU_TX_OPERATIONAL) { -+ ampdu_db_log("Disable AMPDU_TX for test(1).\n"); -+ return -EOPNOTSUPP; -+ } -+#endif -+ if ((action == IEEE80211_AMPDU_RX_START -+ || action == IEEE80211_AMPDU_RX_STOP) -+ && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX))) { -+ ampdu_db_log("Disable AMPDU_RX(2).\n"); -+ return -EOPNOTSUPP; -+ } -+ if ((action == IEEE80211_AMPDU_TX_START -+ || action == IEEE80211_AMPDU_TX_STOP_CONT -+ || action == IEEE80211_AMPDU_TX_STOP_FLUSH -+ || action == IEEE80211_AMPDU_TX_STOP_FLUSH_CONT -+ || action == IEEE80211_AMPDU_TX_OPERATIONAL) -+ && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) { -+ ampdu_db_log("Disable AMPDU_TX(2).\n"); -+ return -EOPNOTSUPP; -+ } -+ switch (action) { -+ case IEEE80211_AMPDU_RX_START: -+#ifdef WIFI_CERTIFIED -+ if (sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS) { -+ ieee80211_stop_rx_ba_session(vif, -+ (1 << (sc->ba_tid)), -+ sc->ba_ra_addr); -+ sc->rx_ba_session_count--; -+ } -+#else -+ if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS) -+ && (sc->rx_ba_sta != sta)) { -+ ret = -EBUSY; -+ break; -+ } else -+ if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS) -+ && (sc->rx_ba_sta == sta)) { -+ ieee80211_stop_rx_ba_session(vif, (1 << (sc->ba_tid)), -+ sc->ba_ra_addr); -+ sc->rx_ba_session_count--; -+ } -+#endif -+ dev_dbg(sc->dev, "IEEE80211_AMPDU_RX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n", -+ sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3], -+ sta->addr[4], sta->addr[5], tid); -+ sc->rx_ba_session_count++; -+ sc->rx_ba_sta = sta; -+ sc->ba_tid = tid; -+ sc->ba_ssn = *ssn; -+ memcpy(sc->ba_ra_addr, sta->addr, ETH_ALEN); -+ queue_work(sc->config_wq, &sc->set_ampdu_rx_add_work); -+ break; -+ case IEEE80211_AMPDU_RX_STOP: -+ sc->rx_ba_session_count--; -+ if (sc->rx_ba_session_count == 0) -+ sc->rx_ba_sta = NULL; -+ queue_work(sc->config_wq, &sc->set_ampdu_rx_del_work); -+ break; -+ case IEEE80211_AMPDU_TX_START: -+ dev_dbg(sc->dev, "AMPDU_TX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n", -+ sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3], -+ sta->addr[4], sta->addr[5], tid); -+ ssv6200_ampdu_tx_start(tid, sta, hw, ssn); -+ ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); -+ break; -+ case IEEE80211_AMPDU_TX_STOP_CONT: -+ case IEEE80211_AMPDU_TX_STOP_FLUSH: -+ case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: -+ dev_dbg(sc->dev, "AMPDU_TX_STOP %02X:%02X:%02X:%02X:%02X:%02X %d.\n", -+ sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3], -+ sta->addr[4], sta->addr[5], tid); -+ ssv6200_ampdu_tx_stop(tid, sta, hw); -+ ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); -+ break; -+ case IEEE80211_AMPDU_TX_OPERATIONAL: -+ dev_dbg(sc->dev, "AMPDU_TX_OPERATIONAL %02X:%02X:%02X:%02X:%02X:%02X %d.\n", -+ sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3], -+ sta->addr[4], sta->addr[5], tid); -+ ssv6200_ampdu_tx_operation(tid, sta, hw, buf_size); -+ break; -+ default: -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ return ret; -+} -+ -+#ifdef CONFIG_PM -+int ssv6xxx_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan) -+{ -+ return 0; -+} -+ -+int ssv6xxx_resume(struct ieee80211_hw *hw) -+{ -+ return 0; -+} -+#endif -+struct ieee80211_ops ssv6200_ops = { -+ .tx = ssv6200_tx, -+ .start = ssv6200_start, -+ .stop = ssv6200_stop, -+ .add_interface = ssv6200_add_interface, -+ .remove_interface = ssv6200_remove_interface, -+ .change_interface = ssv6200_change_interface, -+ .config = ssv6200_config, -+ .configure_filter = ssv6200_config_filter, -+ .bss_info_changed = ssv6200_bss_info_changed, -+ .sta_add = ssv6200_sta_add, -+ .sta_remove = ssv6200_sta_remove, -+ .sta_notify = ssv6200_sta_notify, -+ .set_key = ssv6200_set_key, -+ .sw_scan_start = ssv6200_sw_scan_start, -+ .sw_scan_complete = ssv6200_sw_scan_complete, -+ .get_tsf = ssv6200_get_tsf, -+ .set_tim = ssv6200_set_tim, -+ .conf_tx = ssv6200_conf_tx, -+ .ampdu_action = ssv6200_ampdu_action, -+ .wake_tx_queue = ieee80211_handle_wake_tx_queue, -+#ifdef CONFIG_PM -+ .suspend = ssv6xxx_suspend, -+ .resume = ssv6xxx_resume, -+#endif -+}; -+ -+int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug) -+{ -+ struct ssv_softc *sc = dev; -+ int ac; -+ BUG_ON(hw_txqid > 4); -+ if (hw_txqid == 4) -+ return 0; -+ ac = sc->tx.ac_txqid[hw_txqid]; -+ if (fc_en == false) { -+ if (sc->tx.flow_ctrl_status & (1 << ac)) { -+ ieee80211_wake_queue(sc->hw, ac); -+ sc->tx.flow_ctrl_status &= ~(1 << ac); -+ } else { -+ } -+ } else { -+ if ((sc->tx.flow_ctrl_status & (1 << ac)) == 0) { -+ ieee80211_stop_queue(sc->hw, ac); -+ sc->tx.flow_ctrl_status |= (1 << ac); -+ } else { -+ } -+ } -+ return 0; -+} -+ -+void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *cb_data) -+{ -+ struct ssv_softc *sc = cb_data; -+ BUG_ON(sc == NULL); -+ sc->tx_q_empty = true; -+ smp_mb(); -+ wake_up_interruptible(&sc->tx_wait_q); -+} -+ -+struct ssv6xxx_b_cca_control { -+ u32 down_level; -+ u32 upper_level; -+ u32 adjust_cca_control; -+ u32 adjust_cca_1; -+}; -+struct ssv6xxx_b_cca_control adjust_cci[] = { -+ {0, 43, 0x00162000, 0x20380050}, -+ {40, 48, 0x00161000, 0x20380050}, -+ {45, 53, 0x00160800, 0x20380050}, -+ {50, 63, 0x00160400, 0x20380050}, -+ {60, 68, 0x00160200, 0x20380050}, -+ {65, 73, 0x00160100, 0x20380050}, -+ {70, 128, 0x00000000, 0x20300050}, -+}; -+ -+#define MAX_CCI_LEVEL 128 -+static unsigned long last_jiffies = INITIAL_JIFFIES; -+static s32 size = sizeof(adjust_cci) / sizeof(adjust_cci[0]); -+static u32 current_level = MAX_CCI_LEVEL; -+static u32 current_gate = (sizeof(adjust_cci) / sizeof(adjust_cci[0])) - 1; -+void mitigate_cci(struct ssv_softc *sc, u32 input_level) -+{ -+ s32 i; -+ if (input_level > MAX_CCI_LEVEL) { -+ dev_dbg(sc->dev, "mitigate_cci input error[%d]!!\n", input_level); -+ return; -+ } -+ if (time_after(jiffies, last_jiffies + msecs_to_jiffies(3000))) { -+ dev_dbg(sc->dev, "jiffies=%lu, input_level=%d\n", jiffies, input_level); -+ last_jiffies = jiffies; -+ if ((input_level >= adjust_cci[current_gate].down_level) -+ && (input_level <= adjust_cci[current_gate].upper_level)) { -+ current_level = input_level; -+#ifdef DEBUG_MITIGATE_CCI -+ dev_dbg(sc->dev, "Keep the 0xce0020a0[%x] 0xce002008[%x]!!\n", -+ adjust_cci[current_gate].adjust_cca_control, -+ adjust_cci[current_gate].adjust_cca_1); -+#endif -+ } else { -+ if (current_level < input_level) { -+ for (i = 0; i < size; i++) { -+ if (input_level <= -+ adjust_cci[i].upper_level) { -+#ifdef DEBUG_MITIGATE_CCI -+ dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].upper_level=%d, value=%08x\n", -+ current_gate, input_level, -+ i, -+ adjust_cci[i].upper_level, -+ adjust_cci[i]. -+ adjust_cca_control); -+#endif -+ current_level = input_level; -+ current_gate = i; -+ SMAC_REG_WRITE(sc->sh, -+ ADR_RX_11B_CCA_CONTROL, -+ adjust_cci[i]. -+ adjust_cca_control); -+ SMAC_REG_WRITE(sc->sh, -+ ADR_RX_11B_CCA_1, -+ adjust_cci[i]. -+ adjust_cca_1); -+#ifdef DEBUG_MITIGATE_CCI -+ dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n", -+ adjust_cci[current_gate]. -+ adjust_cca_control, -+ adjust_cci[current_gate]. -+ adjust_cca_1); -+#endif -+ return; -+ } -+ } -+ } else { -+ for (i = (size - 1); i >= 0; i--) { -+ if (input_level >= -+ adjust_cci[i].down_level) { -+#ifdef DEBUG_MITIGATE_CCI -+ dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].down_level=%d, value=%08x\n", -+ current_gate, input_level, -+ i, -+ adjust_cci[i].down_level, -+ adjust_cci[i]. -+ adjust_cca_control); -+#endif -+ current_level = input_level; -+ current_gate = i; -+ SMAC_REG_WRITE(sc->sh, -+ ADR_RX_11B_CCA_CONTROL, -+ adjust_cci[i]. -+ adjust_cca_control); -+ SMAC_REG_WRITE(sc->sh, -+ ADR_RX_11B_CCA_1, -+ adjust_cci[i]. -+ adjust_cca_1); -+#ifdef DEBUG_MITIGATE_CCI -+ dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n", -+ adjust_cci[current_gate]. -+ adjust_cca_control, -+ adjust_cci[current_gate]. -+ adjust_cca_1); -+#endif -+ return; -+ } -+ } -+ } -+ } -+ } -+} -+ -+#define RSSI_SMOOTHING_SHIFT 5 -+#define RSSI_DECIMAL_POINT_SHIFT 6 -+static void _proc_data_rx_skb(struct ssv_softc *sc, struct sk_buff *rx_skb) -+{ -+ struct ieee80211_rx_status *rxs; -+ struct ieee80211_hdr *hdr; -+ __le16 fc; -+ struct ssv6200_rx_desc *rxdesc; -+ struct ssv6200_rxphy_info_padding *rxphypad; -+ struct ssv6200_rxphy_info *rxphy; -+ struct ieee80211_channel *chan; -+ struct ieee80211_vif *vif = NULL; -+ struct ieee80211_sta *sta = NULL; -+ bool rx_hw_dec = false; -+ bool do_sw_dec = false; -+ struct ssv_sta_priv_data *sta_priv = NULL; -+ struct ssv_vif_priv_data *vif_priv = NULL; -+ SKB_info *skb_info = NULL; -+ u8 is_beacon; -+ u8 is_probe_resp; -+ s32 found = 0; -+#ifdef CONFIG_SSV_SMARTLINK -+ { -+ extern int ksmartlink_smartlink_started(void); -+ void smartlink_nl_send_msg(struct sk_buff *skb); -+ if (unlikely(ksmartlink_smartlink_started())) { -+ skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN); -+ skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad); -+ smartlink_nl_send_msg(rx_skb); -+ return; -+ } -+ } -+#endif -+ rxdesc = (struct ssv6200_rx_desc *)rx_skb->data; -+ rxphy = (struct ssv6200_rxphy_info *)(rx_skb->data + sizeof(*rxdesc)); -+ rxphypad = -+ (struct ssv6200_rxphy_info_padding *)(rx_skb->data + rx_skb->len - -+ sizeof(struct -+ ssv6200_rxphy_info_padding)); -+ hdr = (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN); -+ fc = hdr->frame_control; -+ skb_info = (SKB_info *) rx_skb->head; -+ if (rxdesc->wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) { -+ if ((ieee80211_is_data(hdr->frame_control)) -+ && (!(ieee80211_is_nullfunc(hdr->frame_control)))) { -+ ssv6xxx_rc_rx_data_handler(sc->hw, rx_skb, -+ rxdesc->rate_idx); -+ } -+ } -+ rxs = IEEE80211_SKB_RXCB(rx_skb); -+ memset(rxs, 0, sizeof(struct ieee80211_rx_status)); -+ ssv6xxx_rc_mac8011_rate_idx(sc, rxdesc->rate_idx, rxs); -+ -+ rxs->mactime = *((u32 *) & rx_skb->data[28]); -+ chan = sc->hw->conf.chandef.chan; -+ rxs->band = chan->band; -+ rxs->freq = chan->center_freq; -+ rxs->antenna = 1; -+ is_beacon = ieee80211_is_beacon(hdr->frame_control); -+ is_probe_resp = ieee80211_is_probe_resp(hdr->frame_control); -+ if (is_beacon) //+++ -+ { -+ struct ieee80211_mgmt *mgmt_tmp = NULL; -+ mgmt_tmp = -+ (struct ieee80211_mgmt *)(rx_skb->data + -+ SSV6XXX_RX_DESC_LEN); -+ mgmt_tmp->u.beacon.timestamp = -+ cpu_to_le64(ssv6200_get_systime_us()); -+ } -+ if (is_probe_resp) { -+ struct ieee80211_mgmt *mgmt_tmp = NULL; -+ mgmt_tmp = -+ (struct ieee80211_mgmt *)(rx_skb->data + -+ SSV6XXX_RX_DESC_LEN); -+ mgmt_tmp->u.probe_resp.timestamp = -+ cpu_to_le64(ssv6200_get_systime_us()); -+ } -+ -+ if (rxdesc->rate_idx < SSV62XX_G_RATE_INDEX && rxphypad->RSVD == 0) { -+ if (is_beacon || is_probe_resp) { -+ sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb); -+ if (sta) { -+ sta_priv = -+ (struct ssv_sta_priv_data *)sta->drv_priv; -+#ifdef SSV_RSSI_DEBUG -+ dev_dbg(sc->dev, "b_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n", -+ hdr->addr2[0], hdr->addr2[1], -+ hdr->addr2[2], hdr->addr2[3], -+ hdr->addr2[4], hdr->addr2[5], -+ rxphypad->rpci, rxphypad->snr); -+#endif -+ if (sta_priv->beacon_rssi) { -+ sta_priv->beacon_rssi = -+ ((rxphypad-> -+ rpci << RSSI_DECIMAL_POINT_SHIFT) -+ + -+ ((sta_priv-> -+ beacon_rssi << -+ RSSI_SMOOTHING_SHIFT) - -+ sta_priv-> -+ beacon_rssi)) >> -+ RSSI_SMOOTHING_SHIFT; -+ rxphypad->rpci = -+ (sta_priv-> -+ beacon_rssi >> -+ RSSI_DECIMAL_POINT_SHIFT); -+ } else -+ sta_priv->beacon_rssi = -+ (rxphypad-> -+ rpci << RSSI_DECIMAL_POINT_SHIFT); -+#ifdef SSV_RSSI_DEBUG -+ dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphypad->rpci); -+#endif -+ mitigate_cci(sc, rxphypad->rpci); -+ } else { -+ mutex_lock(&sc->mutex); -+ list_for_each_entry(p_rssi_res, -+ &rssi_res.rssi_list, -+ rssi_list) { -+ if (!memcmp -+ (p_rssi_res->bssid, hdr->addr2, -+ ETH_ALEN)) { -+ { -+ p_rssi_res->rssi = -+ ((rxphypad-> -+ rpci << -+ RSSI_DECIMAL_POINT_SHIFT) -+ + -+ ((p_rssi_res-> -+ rssi << -+ RSSI_SMOOTHING_SHIFT) -+ - -+ p_rssi_res-> -+ rssi)) >> -+ RSSI_SMOOTHING_SHIFT; -+ rxphypad->rpci = -+ (p_rssi_res-> -+ rssi >> -+ RSSI_DECIMAL_POINT_SHIFT); -+ } -+ p_rssi_res->cache_jiffies = -+ jiffies; -+ found = 1; -+ break; -+ } else { -+ if (p_rssi_res->rssi) { -+ if (time_after -+ (jiffies, -+ p_rssi_res-> -+ cache_jiffies + -+ msecs_to_jiffies -+ (40000))) { -+ p_rssi_res-> -+ timeout = 1; -+ } -+ } -+ } -+ } -+ if (!found) { -+ p_rssi_res = -+ kmalloc(sizeof(struct rssi_res_st), -+ GFP_KERNEL); -+ memcpy(p_rssi_res->bssid, hdr->addr2, -+ ETH_ALEN); -+ p_rssi_res->cache_jiffies = jiffies; -+ p_rssi_res->rssi = -+ (rxphypad-> -+ rpci << RSSI_DECIMAL_POINT_SHIFT); -+ p_rssi_res->timeout = 0; -+ INIT_LIST_HEAD(&p_rssi_res->rssi_list); -+ list_add_tail_rcu(& -+ (p_rssi_res-> -+ rssi_list), -+ &(rssi_res. -+ rssi_list)); -+ } -+ mutex_unlock(&sc->mutex); -+ } -+ if (rxphypad->rpci > 88) -+ rxphypad->rpci = 88; -+ } -+ if (sc->sh->cfg.rssi_ctl) { -+ rxs->signal = (-rxphypad->rpci) + sc->sh->cfg.rssi_ctl; -+ } else { -+ rxs->signal = (-rxphypad->rpci); -+ } -+ } else if (rxdesc->rate_idx >= SSV62XX_G_RATE_INDEX -+ && rxphy->service == 0) { -+ if (is_beacon || is_probe_resp) { -+ sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb); -+ if (sta) { -+ sta_priv = -+ (struct ssv_sta_priv_data *)sta->drv_priv; -+#ifdef SSV_RSSI_DEBUG -+ dev_dbg(sc->dev, "gn_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n", -+ hdr->addr2[0], hdr->addr2[1], -+ hdr->addr2[2], hdr->addr2[3], -+ hdr->addr2[4], hdr->addr2[5], rxphy->rpci, -+ rxphy->snr); -+#endif -+ if (sta_priv->beacon_rssi) { -+ sta_priv->beacon_rssi = -+ ((rxphy-> -+ rpci << RSSI_DECIMAL_POINT_SHIFT) -+ + -+ ((sta_priv-> -+ beacon_rssi << -+ RSSI_SMOOTHING_SHIFT) - -+ sta_priv-> -+ beacon_rssi)) >> -+ RSSI_SMOOTHING_SHIFT; -+ rxphy->rpci = -+ (sta_priv-> -+ beacon_rssi >> -+ RSSI_DECIMAL_POINT_SHIFT); -+ } else -+ sta_priv->beacon_rssi = -+ (rxphy-> -+ rpci << RSSI_DECIMAL_POINT_SHIFT); -+#ifdef SSV_RSSI_DEBUG -+ dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphy->rpci); -+#endif -+ } -+ if (rxphy->rpci > 88) -+ rxphy->rpci = 88; -+ } -+ if (sc->sh->cfg.rssi_ctl) { -+ rxs->signal = (-rxphy->rpci) + sc->sh->cfg.rssi_ctl; -+ } else { -+ rxs->signal = (-rxphy->rpci); -+ } -+ } else { -+#ifdef SSV_RSSI_DEBUG -+ dev_dbg(sc->dev, "########unicast: %d, b_rssi/snr: %d/%d, gn_rssi/snr: %d/%d, rate:%d###############\n", -+ rxdesc->unicast, (-rxphy->rpci), rxphy->snr, -+ (-rxphypad->rpci), rxphypad->snr, rxdesc->rate_idx); -+ dev_dbg(sc->dev, "RSSI, %d, rate_idx, %d\n", rxs->signal, -+ rxdesc->rate_idx); -+ dev_dbg(sc->dev, "rxdesc->RxResult = %x,rxdesc->wsid = %d\n", -+ rxdesc->RxResult, rxdesc->wsid); -+#endif -+ sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb); -+ if (sta) { -+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ rxs->signal = -+ -(sta_priv-> -+ beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT); -+ } -+#ifdef SSV_RSSI_DEBUG -+ dev_dbg(sc->dev, "Others signal %d\n", rxs->signal); -+#endif -+ } -+// rxs->flag = RX_FLAG_MACTIME_START; //+++ -+ rxs->rx_flags = 0; -+ if (rxphy->aggregate) -+ rxs->flag |= RX_FLAG_NO_SIGNAL_VAL; -+ sc->hw_mng_used = rxdesc->mng_used; -+ if ((ieee80211_is_data(fc) || ieee80211_is_data_qos(fc)) -+ && ieee80211_has_protected(fc)) { -+ sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb); -+ if (sta == NULL) -+ goto drop_rx; -+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ vif = sta_priv->sta_info->vif; -+ if (vif == NULL) -+ goto drop_rx; -+ if (is_broadcast_ether_addr(hdr->addr1) || is_multicast_ether_addr(hdr->addr1)) { -+ vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv; -+ rx_hw_dec = vif_priv->has_hw_decrypt; -+ do_sw_dec = vif_priv->need_sw_decrypt; -+ } else { -+ rx_hw_dec = sta_priv->has_hw_decrypt; -+ do_sw_dec = sta_priv->need_sw_decrypt; -+ } -+ } -+ skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN); -+ skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad); -+#ifdef CONFIG_P2P_NOA -+ if (is_beacon) -+ ssv6xxx_noa_detect(sc, hdr, rx_skb->len); -+#endif -+ if (rx_hw_dec || do_sw_dec) { -+ hdr = (struct ieee80211_hdr *)rx_skb->data; -+ rxs = IEEE80211_SKB_RXCB(rx_skb); -+ hdr->frame_control = -+ hdr-> -+ frame_control & ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED)); -+ rxs->flag |= (RX_FLAG_DECRYPTED | RX_FLAG_IV_STRIPPED); -+ } -+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_RX_DATA) -+ local_bh_disable(); -+ ieee80211_rx(sc->hw, rx_skb); -+ local_bh_enable(); -+#else -+ ieee80211_rx_irqsafe(sc->hw, rx_skb); -+#endif -+ return; -+ drop_rx: -+ dev_kfree_skb_any(rx_skb); -+} -+ -+#ifdef IRQ_PROC_RX_DATA -+static struct sk_buff *_proc_rx_skb(struct ssv_softc *sc, -+ struct sk_buff *rx_skb) -+{ -+ struct ieee80211_hdr *hdr = -+ (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN); -+ struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)rx_skb->data; -+ if (ieee80211_is_back(hdr->frame_control) -+ || (rxdesc->c_type == HOST_EVENT)) -+ return rx_skb; -+ _proc_data_rx_skb(sc, rx_skb); -+ return NULL; -+} -+#endif -+void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q, -+ spinlock_t * rx_q_lock) -+{ -+ struct sk_buff *skb; -+ struct ieee80211_hdr *hdr; -+ struct ssv6200_rx_desc *rxdesc; -+ unsigned long flags = 0; -+#ifdef USE_FLUSH_RETRY -+ bool has_ba_processed = false; -+#endif -+ while (1) { -+ if (rx_q_lock != NULL) { -+ spin_lock_irqsave(rx_q_lock, flags); -+ skb = __skb_dequeue(rx_q); -+ } else -+ skb = skb_dequeue(rx_q); -+ if (!skb) { -+ if (rx_q_lock != NULL) -+ spin_unlock_irqrestore(rx_q_lock, flags); -+ break; -+ } -+ sc->rx.rxq_count--; -+ if (rx_q_lock != NULL) -+ spin_unlock_irqrestore(rx_q_lock, flags); -+ rxdesc = (struct ssv6200_rx_desc *)skb->data; -+ if (rxdesc->c_type == HOST_EVENT) { -+ struct cfg_host_event *h_evt = -+ (struct cfg_host_event *)rxdesc; -+ if (h_evt->h_event == SOC_EVT_NO_BA) { -+ ssv6200_ampdu_no_BA_handler(sc->hw, skb); -+#ifdef USE_FLUSH_RETRY -+ has_ba_processed = true; -+#endif -+ } else if (h_evt->h_event == SOC_EVT_RC_MPDU_REPORT) { -+ skb_queue_tail(&sc->rc_report_queue, skb); -+ if (sc->rc_sample_sechedule == 0) -+ queue_work(sc->rc_sample_workqueue, -+ &sc->rc_sample_work); -+ } else if (h_evt->h_event == SOC_EVT_SDIO_TEST_COMMAND) { -+ if (h_evt->evt_seq_no == 0) { -+ dev_dbg(sc->dev, "SOC_EVT_SDIO_TEST_COMMAND\n"); -+ sc->sdio_rx_evt_size = h_evt->len; -+ sc->sdio_throughput_timestamp = jiffies; -+ } else { -+ sc->sdio_rx_evt_size += h_evt->len; -+ if (time_after -+ (jiffies, -+ sc->sdio_throughput_timestamp + -+ msecs_to_jiffies(1000))) { -+ dev_dbg(sc->dev, "data[%ld] SDIO RX throughput %ld Kbps\n", -+ sc->sdio_rx_evt_size, -+ (sc-> -+ sdio_rx_evt_size << 3) / -+ jiffies_to_msecs(jiffies - -+ sc-> -+ sdio_throughput_timestamp)); -+ sc->sdio_throughput_timestamp = -+ jiffies; -+ sc->sdio_rx_evt_size = 0; -+ } -+ } -+ dev_kfree_skb_any(skb); -+ } else if (h_evt->h_event == SOC_EVT_WATCHDOG_TRIGGER) { -+ dev_kfree_skb_any(skb); -+// if(sc->watchdog_flag != WD_SLEEP) //+++ -+ sc->watchdog_flag = WD_KICKED; -+ } else if (h_evt->h_event == SOC_EVT_RESET_HOST) { -+ dev_kfree_skb_any(skb); -+ if ((sc->ap_vif == NULL) -+ || !(sc->sh->cfg.ignore_reset_in_ap)) { -+ ssv6xxx_restart_hw(sc); -+ } else { -+ dev_warn(sc->dev, -+ "Reset event ignored.\n"); -+ } -+ } -+#ifdef CONFIG_P2P_NOA -+ else if (h_evt->h_event == SOC_EVT_NOA) { -+ ssv6xxx_process_noa_event(sc, skb); -+ dev_kfree_skb_any(skb); -+ } -+#endif -+ else if (h_evt->h_event == SOC_EVT_SDIO_TXTPUT_RESULT) { -+ dev_dbg(sc->dev, "data SDIO TX throughput %d Kbps\n", -+ h_evt->evt_seq_no); -+ dev_kfree_skb_any(skb); -+ } else if (h_evt->h_event == SOC_EVT_TXLOOPBK_RESULT) { -+ if (h_evt->evt_seq_no == SSV6XXX_STATE_OK) { -+ dev_dbg(sc->dev, "FW TX LOOPBACK OK\n"); -+ sc->iq_cali_done = IQ_CALI_OK; -+ } else { -+ dev_dbg(sc->dev, "FW TX LOOPBACK FAILED\n"); -+ sc->iq_cali_done = IQ_CALI_FAILED; -+ } -+ dev_kfree_skb_any(skb); -+ wake_up_interruptible(&sc->fw_wait_q); -+ } else { -+ dev_warn(sc->dev, "Unkown event %d received\n", -+ h_evt->h_event); -+ dev_kfree_skb_any(skb); -+ } -+ continue; -+ } -+ hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN); -+ if (ieee80211_is_back(hdr->frame_control)) { -+ ssv6200_ampdu_BA_handler(sc->hw, skb); -+#ifdef USE_FLUSH_RETRY -+ has_ba_processed = true; -+#endif -+ continue; -+ } -+ _proc_data_rx_skb(sc, skb); -+ } -+#ifdef USE_FLUSH_RETRY -+ if (has_ba_processed) { -+ ssv6xxx_ampdu_postprocess_BA(sc->hw); -+ } -+#endif -+} -+ -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args) -+#else -+int ssv6200_rx(struct sk_buff *rx_skb, void *args) -+#endif -+{ -+ struct ssv_softc *sc = args; -+#ifdef IRQ_PROC_RX_DATA -+ struct sk_buff *skb; -+ skb = _proc_rx_skb(sc, rx_skb); -+ if (skb == NULL) -+ return 0; -+#endif -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+ { -+ unsigned long flags; -+ spin_lock_irqsave(&sc->rx_skb_q.lock, flags); -+ while (skb_queue_len(rx_skb_q)) -+ __skb_queue_tail(&sc->rx_skb_q, -+ __skb_dequeue(rx_skb_q)); -+ spin_unlock_irqrestore(&sc->rx_skb_q.lock, flags); -+ } -+#else -+ skb_queue_tail(&sc->rx_skb_q, rx_skb); -+#endif -+ wake_up_interruptible(&sc->rx_wait_q); -+ return 0; -+} -+ -+struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc, -+ struct sk_buff *skb) -+{ -+ struct ieee80211_hdr *hdr = -+ (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN); -+ struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)skb->data;; -+ if ((rxdesc->wsid >= 0) && (rxdesc->wsid < SSV_NUM_STA)) -+ return sc->sta_info[rxdesc->wsid].sta; -+ else -+ return ssv6xxx_find_sta_by_addr(sc, hdr->addr2); -+} -+ -+struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc, u8 addr[6]) -+{ -+ struct ieee80211_sta *sta; -+ int i; -+ for (i = 0; i < SSV6200_MAX_VIF; i++) { -+ if (sc->vif_info[i].vif == NULL) -+ continue; -+ sta = ieee80211_find_sta(sc->vif_info[i].vif, addr); -+ if (sta != NULL) -+ return sta; -+ } -+ return NULL; -+} -+ -+void ssv6xxx_foreach_sta(struct ssv_softc *sc, -+ void (*sta_func)(struct ssv_softc *, -+ struct ssv_sta_info *, void *), -+ void *param) -+{ -+ int i; -+ BUG_ON(sta_func == NULL); -+ for (i = 0; i < SSV_NUM_STA; i++) { -+ if ((sc->sta_info[i].s_flags & STA_FLAG_VALID) == 0) -+ continue; -+ (*sta_func) (sc, &sc->sta_info[i], param); -+ } -+} -+ -+void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc, -+ struct ssv_vif_info *vif_info, -+ void (*sta_func)(struct ssv_softc *, -+ struct ssv_vif_info *, -+ struct ssv_sta_info *, -+ void *), void *param) -+{ -+ struct ssv_vif_priv_data *vif_priv; -+ struct ssv_sta_priv_data *sta_priv_iter; -+ BUG_ON(vif_info == NULL); -+ BUG_ON((size_t)vif_info < 0x30000); -+ vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv; -+ BUG_ON((size_t)vif_info->vif < 0x30000); -+ BUG_ON((size_t)vif_priv < 0x30000); -+ list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) { -+ BUG_ON(sta_priv_iter == NULL); -+ BUG_ON((size_t)sta_priv_iter < 0x30000); -+ BUG_ON(sta_priv_iter->sta_info == NULL); -+ BUG_ON((size_t)sta_priv_iter->sta_info < 0x30000); -+ if ((sta_priv_iter->sta_info->s_flags & STA_FLAG_VALID) == 0) -+ continue; -+ (*sta_func) (sc, vif_info, sta_priv_iter->sta_info, param); -+ } -+} -+ -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf, -+ ssize_t length) -+{ -+ ssize_t buf_size = length; -+ ssize_t prt_size; -+ prt_size = -+ snprintf(status_buf, buf_size, "\nSMAC driver queue status:.\n"); -+ status_buf += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(status_buf, buf_size, "\tTX queue: %d\n", -+ skb_queue_len(&sc->tx_skb_q)); -+ status_buf += prt_size; -+ buf_size -= prt_size; -+ prt_size = snprintf(status_buf, buf_size, "\tMax TX queue: %d\n", -+ sc->max_tx_skb_q_len); -+ status_buf += prt_size; -+ buf_size -= prt_size; -+ return (length - buf_size); -+} -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/dev.h b/drivers/net/wireless/ssv6051/smac/dev.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/dev.h -@@ -0,0 +1,445 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _DEV_H_ -+#define _DEV_H_ -+#include -+#include -+#include -+#include -+#include "ampdu.h" -+#include "ssv_rc_common.h" -+#include "drv_comm.h" -+#include "sec.h" -+#include "p2p.h" -+#include -+#define SSV6200_MAX_HW_MAC_ADDR 2 -+#define SSV6200_MAX_VIF 2 -+#define SSV6200_RX_BA_MAX_SESSIONS 1 -+#define SSV6200_OPMODE_STA 0 -+#define SSV6200_OPMODE_AP 1 -+#define SSV6200_OPMODE_IBSS 2 -+#define SSV6200_OPMODE_WDS 3 -+#define SSV6200_USE_HW_WSID(_sta_idx) ((_sta_idx == 0) || (_sta_idx == 1)) -+#define HW_MAX_RATE_TRIES 7 -+#define MAC_DECITBL1_SIZE 16 -+#define MAC_DECITBL2_SIZE 9 -+#define RX_11B_CCA_IN_SCAN 0x20230050 -+//#define WATCHDOG_TIMEOUT (10*HZ) -+#define WATCHDOG_TIMEOUT (99999*HZ) -+extern u16 generic_deci_tbl[]; -+#define ap_deci_tbl generic_deci_tbl -+#define sta_deci_tbl generic_deci_tbl -+#define HT_SIGNAL_EXT 6 -+#define HT_SIFS_TIME 10 -+#define BITS_PER_BYTE 8 -+#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) -+#define ACK_LEN (14) -+#define BA_LEN (32) -+#define RTS_LEN (20) -+#define CTS_LEN (14) -+#define L_STF 8 -+#define L_LTF 8 -+#define L_SIG 4 -+#define HT_SIG 8 -+#define HT_STF 4 -+#define HT_LTF(_ns) (4 * (_ns)) -+#define SYMBOL_TIME(_ns) ((_ns) << 2) -+#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) -+#define CCK_SIFS_TIME 10 -+#define CCK_PREAMBLE_BITS 144 -+#define CCK_PLCP_BITS 48 -+#define OFDM_SIFS_TIME 16 -+#define OFDM_PREAMBLE_TIME 20 -+#define OFDM_PLCP_BITS 22 -+#define OFDM_SYMBOL_TIME 4 -+#define WMM_AC_VO 0 -+#define WMM_AC_VI 1 -+#define WMM_AC_BE 2 -+#define WMM_AC_BK 3 -+#define WMM_NUM_AC 4 -+#define WMM_TID_NUM 8 -+#define TXQ_EDCA_0 0x01 -+#define TXQ_EDCA_1 0x02 -+#define TXQ_EDCA_2 0x04 -+#define TXQ_EDCA_3 0x08 -+#define TXQ_MGMT 0x10 -+#define IS_SSV_HT(dsc) ((dsc)->rate_idx >= 15) -+#define IS_SSV_SHORT_GI(dsc) ((dsc)->rate_idx>=23 && (dsc)->rate_idx<=30) -+#define IS_SSV_HT_GF(dsc) ((dsc)->rate_idx >= 31) -+#define IS_SSV_SHORT_PRE(dsc) ((dsc)->rate_idx>=4 && (dsc)->rate_idx<=14) -+#define SMAC_REG_WRITE(_s,_r,_v) \ -+ (_s)->hci.hci_ops->hci_write_word(_r,_v) -+#define SMAC_REG_READ(_s,_r,_v) \ -+ (_s)->hci.hci_ops->hci_read_word(_r, _v) -+#define SMAC_LOAD_FW(_s,_r,_v) \ -+ (_s)->hci.hci_ops->hci_load_fw(_r, _v) -+#define SMAC_IFC_RESET(_s) (_s)->hci.hci_ops->hci_interface_reset() -+#define SMAC_REG_CONFIRM(_s,_r,_v) \ -+{ \ -+ u32 _regval; \ -+ SMAC_REG_READ(_s, _r, &_regval); \ -+ if (_regval != (_v)) { \ -+ printk("ERROR!!Please check interface!\n"); \ -+ printk("[0x%08x]: 0x%08x!=0x%08x\n", \ -+ (_r), (_v), _regval); \ -+ printk("SOS!SOS!\n"); \ -+ return -1; \ -+ } \ -+} -+#define SMAC_REG_SET_BITS(_sh,_reg,_set,_clr) \ -+({ \ -+ int ret; \ -+ u32 _regval; \ -+ ret = SMAC_REG_READ(_sh, _reg, &_regval); \ -+ _regval &= ~(_clr); \ -+ _regval |= (_set); \ -+ if (ret == 0) \ -+ ret = SMAC_REG_WRITE(_sh, _reg, _regval); \ -+ ret; \ -+}) -+#define HCI_START(_sh) \ -+ (_sh)->hci.hci_ops->hci_start() -+#define HCI_STOP(_sh) \ -+ (_sh)->hci.hci_ops->hci_stop() -+#define HCI_SEND(_sh,_sk,_q) \ -+ (_sh)->hci.hci_ops->hci_tx(_sk, _q, 0) -+#define HCI_PAUSE(_sh,_mk) \ -+ (_sh)->hci.hci_ops->hci_tx_pause(_mk) -+#define HCI_RESUME(_sh,_mk) \ -+ (_sh)->hci.hci_ops->hci_tx_resume(_mk) -+#define HCI_TXQ_FLUSH(_sh,_mk) \ -+ (_sh)->hci.hci_ops->hci_txq_flush(_mk) -+#define HCI_TXQ_FLUSH_BY_STA(_sh,_aid) \ -+ (_sh)->hci.hci_ops->hci_txq_flush_by_sta(_aid) -+#define HCI_TXQ_EMPTY(_sh,_txqid) \ -+ (_sh)->hci.hci_ops->hci_txq_empty(_txqid) -+#define HCI_WAKEUP_PMU(_sh) \ -+ (_sh)->hci.hci_ops->hci_pmu_wakeup() -+#define HCI_SEND_CMD(_sh,_sk) \ -+ (_sh)->hci.hci_ops->hci_send_cmd(_sk) -+#define SSV6XXX_SET_HW_TABLE(sh_,tbl_) \ -+({ \ -+ int ret = 0; \ -+ u32 i=0; \ -+ for(; ihas_hw_decrypt) -+#define SSV6XXX_USE_SW_DECRYPT(_priv) (SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) || SSV6XXX_USE_MAC80211_DECRYPT(_priv)) -+#define SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) (_priv->need_sw_decrypt) -+#define SSV6XXX_USE_MAC80211_DECRYPT(_priv) (_priv->use_mac80211_decrypt) -+struct ssv_softc; -+#ifdef CONFIG_P2P_NOA -+struct ssv_p2p_noa; -+#endif -+#define SSV6200_HT_TX_STREAMS 1 -+#define SSV6200_HT_RX_STREAMS 1 -+#define SSV6200_RX_HIGHEST_RATE 72 -+enum PWRSV_STATUS { -+ PWRSV_DISABLE, -+ PWRSV_ENABLE, -+ PWRSV_PREPARE, -+}; -+struct rssi_res_st { -+ struct list_head rssi_list; -+ unsigned long cache_jiffies; -+ s32 rssi; -+ s32 timeout; -+ u8 bssid[ETH_ALEN]; -+}; -+struct ssv_hw { -+ struct ssv_softc *sc; -+ struct ssv6xxx_platform_data *priv; -+ struct ssv6xxx_hci_info hci; -+ char chip_id[24]; -+ u64 chip_tag; -+ u32 tx_desc_len; -+ u32 rx_desc_len; -+ u32 rx_pinfo_pad; -+ u32 tx_page_available; -+ u32 ampdu_divider; -+ u8 page_count[SSV6200_ID_NUMBER]; -+ u32 hw_buf_ptr[SSV_RC_MAX_STA]; -+ u32 hw_sec_key[SSV_RC_MAX_STA]; -+ u32 hw_pinfo; -+ struct ssv6xxx_cfg cfg; -+ u32 n_addresses; -+ struct mac_address maddr[SSV6200_MAX_HW_MAC_ADDR]; -+ u8 ipd_channel_touch; -+ struct ssv6xxx_ch_cfg *p_ch_cfg; -+ u32 ch_cfg_size; -+}; -+struct ssv_tx { -+ u16 seq_no; -+ int hw_txqid[WMM_NUM_AC]; -+ int ac_txqid[WMM_NUM_AC]; -+ u32 flow_ctrl_status; -+ u32 tx_pkt[SSV_HW_TXQ_NUM]; -+ u32 tx_frag[SSV_HW_TXQ_NUM]; -+ struct list_head ampdu_tx_que; -+ spinlock_t ampdu_tx_que_lock; -+ u16 ampdu_tx_group_id; -+}; -+struct ssv_rx { -+ struct sk_buff *rx_buf; -+ spinlock_t rxq_lock; -+ struct sk_buff_head rxq_head; -+ u32 rxq_count; -+}; -+#define SSV6XXX_GET_STA_INFO(_sc,_s) \ -+ &(_sc)->sta_info[((struct ssv_sta_priv_data *)((_s)->drv_priv))->sta_idx] -+#define STA_FLAG_VALID 0x00001 -+#define STA_FLAG_QOS 0x00002 -+#define STA_FLAG_AMPDU 0x00004 -+#define STA_FLAG_ENCRYPT 0x00008 -+struct ssv_sta_info { -+ u16 aid; -+ u16 s_flags; -+ int hw_wsid; -+ struct ieee80211_sta *sta; -+ struct ieee80211_vif *vif; -+ bool sleeping; -+ bool tim_set; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct dentry *debugfs_dir; -+#endif -+}; -+struct ssv_vif_info { -+ struct ieee80211_vif *vif; -+ struct ssv_vif_priv_data *vif_priv; -+ enum nl80211_iftype if_type; -+ struct ssv6xxx_hw_sec sramKey; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct dentry *debugfs_dir; -+#endif -+}; -+struct ssv_sta_priv_data { -+ int sta_idx; -+ int rc_idx; -+ int rx_data_rate; -+ struct ssv_sta_info *sta_info; -+ struct list_head list; -+ u32 ampdu_mib_total_BA_counter; -+ AMPDU_TID ampdu_tid[WMM_TID_NUM]; -+ bool has_hw_encrypt; -+ bool need_sw_encrypt; -+ bool has_hw_decrypt; -+ bool need_sw_decrypt; -+ bool use_mac80211_decrypt; -+ u8 group_key_idx; -+ u32 beacon_rssi; -+}; -+struct ssv_vif_priv_data { -+ int vif_idx; -+ struct list_head sta_list; -+ u32 sta_asleep_mask; -+ u32 pair_cipher; -+ u32 group_cipher; -+ bool is_security_valid; -+ bool has_hw_encrypt; -+ bool need_sw_encrypt; -+ bool has_hw_decrypt; -+ bool need_sw_decrypt; -+ bool use_mac80211_decrypt; -+ bool force_sw_encrypt; -+ u8 group_key_idx; -+}; -+#define SC_OP_INVALID 0x00000001 -+#define SC_OP_HW_RESET 0x00000002 -+#define SC_OP_OFFCHAN 0x00000004 -+#define SC_OP_FIXED_RATE 0x00000008 -+#define SC_OP_SHORT_PREAMBLE 0x00000010 -+struct ssv6xxx_beacon_info { -+ u32 pubf_addr; -+ u16 len; -+ u8 tim_offset; -+ u8 tim_cnt; -+}; -+#define SSV6200_MAX_BCAST_QUEUE_LEN 16 -+struct ssv6xxx_bcast_txq { -+ spinlock_t txq_lock; -+ struct sk_buff_head qhead; -+ int cur_qsize; -+}; -+#ifdef DEBUG_AMPDU_FLUSH -+typedef struct AMPDU_TID_st AMPDU_TID; -+#define MAX_TID (24) -+#endif -+struct ssv_softc { -+ struct ieee80211_hw *hw; -+ struct device *dev; -+ u32 restart_counter; -+ bool force_triger_reset; -+ unsigned long sdio_throughput_timestamp; -+ unsigned long sdio_rx_evt_size; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) -+ struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; -+#else -+ struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; -+#endif -+ struct ieee80211_channel *cur_channel; -+ u16 hw_chan; -+ struct mutex mutex; -+ struct ssv_hw *sh; -+ struct ssv_tx tx; -+ struct ssv_rx rx; -+ struct ssv_vif_info vif_info[SSV_NUM_VIF]; -+ struct ssv_sta_info sta_info[SSV_NUM_STA]; -+ struct ieee80211_vif *ap_vif; -+ u8 nvif; -+ u32 sc_flags; -+ void *rc; -+ int max_rate_idx; -+ struct workqueue_struct *rc_sample_workqueue; -+ struct sk_buff_head rc_report_queue; -+ struct work_struct rc_sample_work; -+#ifdef DEBUG_AMPDU_FLUSH -+ struct AMPDU_TID_st *tid[MAX_TID]; -+#endif -+ u16 rc_sample_sechedule; -+ u16 *mac_deci_tbl; -+ struct workqueue_struct *config_wq; -+ bool bq4_dtim; -+ struct work_struct set_tim_work; -+ u8 enable_beacon; -+ u8 beacon_interval; -+ u8 beacon_dtim_cnt; -+ u8 beacon_usage; -+ struct ssv6xxx_beacon_info beacon_info[2]; -+ struct sk_buff *beacon_buf; -+ struct work_struct bcast_start_work; -+ struct delayed_work bcast_stop_work; -+ struct delayed_work bcast_tx_work; -+ struct delayed_work thermal_monitor_work; -+ struct workqueue_struct *thermal_wq; -+ int is_sar_enabled; -+ bool aid0_bit_set; -+ u8 hw_mng_used; -+ struct ssv6xxx_bcast_txq bcast_txq; -+ int bcast_interval; -+ u8 bssid[6]; -+ struct mutex mem_mutex; -+ spinlock_t ps_state_lock; -+ u8 hw_wsid_bit; -+ int rx_ba_session_count; -+ struct ieee80211_sta *rx_ba_sta; -+ u8 rx_ba_bitmap; -+ u8 ba_ra_addr[ETH_ALEN]; -+ u16 ba_tid; -+ u16 ba_ssn; -+ struct work_struct set_ampdu_rx_add_work; -+ struct work_struct set_ampdu_rx_del_work; -+ bool isAssoc; -+ u16 channel_center_freq; -+ bool bScanning; -+ int ps_status; -+ u16 ps_aid; -+ u16 tx_wait_q_woken; -+ wait_queue_head_t tx_wait_q; -+ struct sk_buff_head tx_skb_q; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ u32 max_tx_skb_q_len; -+#endif -+ struct task_struct *tx_task; -+ bool tx_q_empty; -+ struct sk_buff_head tx_done_q; -+ u16 rx_wait_q_woken; -+ wait_queue_head_t rx_wait_q; -+ struct sk_buff_head rx_skb_q; -+ struct task_struct *rx_task; -+ bool dbg_rx_frame; -+ bool dbg_tx_frame; -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct dentry *debugfs_dir; -+#endif -+#ifdef CONFIG_P2P_NOA -+ struct ssv_p2p_noa p2p_noa; -+#endif -+ struct timer_list watchdog_timeout; -+ u32 watchdog_flag; -+ wait_queue_head_t fw_wait_q; -+ u32 iq_cali_done; -+ u32 sr_bhvr; -+}; -+enum { -+ IQ_CALI_RUNNING, -+ IQ_CALI_OK, -+ IQ_CALI_FAILED -+}; -+enum { -+ WD_SLEEP, -+ WD_BARKING, -+ WD_KICKED, -+ WD_MAX -+}; -+void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args); -+void ssv6200_rx_process(struct work_struct *work); -+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX) -+int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args); -+#else -+int ssv6200_rx(struct sk_buff *rx_skb, void *args); -+#endif -+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args); -+void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args); -+int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug); -+void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *); -+int ssv6xxx_rf_disable(struct ssv_hw *sh); -+int ssv6xxx_rf_enable(struct ssv_hw *sh); -+int ssv6xxx_set_channel(struct ssv_softc *sc, int ch); -+#ifdef CONFIG_SSV_SMARTLINK -+int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch); -+int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept); -+int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept); -+#endif -+int ssv6xxx_tx_task(void *data); -+int ssv6xxx_rx_task(void *data); -+u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type); -+bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr); -+void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb); -+void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb); -+int ssv6xxx_update_decision_table(struct ssv_softc *sc); -+void ssv6xxx_ps_callback_func(unsigned long data); -+void ssv6xxx_enable_ps(struct ssv_softc *sc); -+void ssv6xxx_disable_ps(struct ssv_softc *sc); -+int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag); -+int ssv6xxx_skb_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc); -+int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta, -+ struct ssv_softc *sc); -+void ssv6200_sync_hw_key_sequence(struct ssv_softc *sc, -+ struct ssv_sta_info *sta_info, bool bWrite); -+struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc, -+ struct sk_buff *skb); -+struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc, -+ u8 addr[6]); -+void ssv6xxx_foreach_sta(struct ssv_softc *sc, -+ void (*sta_func)(struct ssv_softc *, -+ struct ssv_sta_info *, void *), -+ void *param); -+void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc, -+ struct ssv_vif_info *vif_info, -+ void (*sta_func)(struct ssv_softc *, -+ struct ssv_vif_info *, -+ struct ssv_sta_info *, void *), -+ void *param); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf, -+ ssize_t buf_size); -+#endif -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/dev_tbl.h b/drivers/net/wireless/ssv6051/smac/dev_tbl.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/dev_tbl.h -@@ -0,0 +1,141 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _DEV_TBL_H_ -+#define _DEV_TBL_H_ -+#include "ssv6200_configuration.h" -+#include "drv_comm.h" -+struct ssv6xxx_dev_table { -+ u32 address; -+ u32 data; -+}; -+#define ssv6200_phy_tbl phy_setting -+#define ssv6200_rf_tbl asic_rf_setting -+#define ACTION_DO_NOTHING 0 -+#define ACTION_UPDATE_NAV 1 -+#define ACTION_RESET_NAV 2 -+#define ACTION_SIGNAL_ACK 3 -+#define FRAME_ACCEPT 0 -+#define FRAME_DROP 1 -+#define SET_DEC_TBL(_type,_mask,_action,_drop) \ -+ (_type<<9| \ -+ _mask <<3| \ -+ _action<<1| \ -+ _drop) -+u16 generic_deci_tbl[] = { -+ SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP), -+ SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT), -+ SET_DEC_TBL(0x1a, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT), -+ SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP), -+ 0, -+ 0, -+ 0, -+ SET_DEC_TBL(0x05, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT), -+ SET_DEC_TBL(0x0b, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT), -+ SET_DEC_TBL(0x01, 0x3d, ACTION_SIGNAL_ACK, FRAME_ACCEPT), -+ SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT), -+ SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT), -+ SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP), -+ SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP), -+ SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP), -+ SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP), -+ 0x2008, -+ 0x1001, -+ 0x0400, -+ 0x0400, -+ 0x2000, -+ 0x800E, -+ 0x0800, -+ 0x0B88, -+ 0x0800, -+}; -+ -+#define SET_PHY_INFO(_ctsdur,_ba_rate_idx,_ack_rate_idx,_llength_idx,_llength_enable) \ -+ (_ctsdur<<16| \ -+ _ba_rate_idx <<10| \ -+ _ack_rate_idx<<4| \ -+ _llength_idx<<1| \ -+ _llength_enable) -+#define SET_PHY_L_LENGTH(_l_ba,_l_rts,_l_cts_ack) (_l_ba<<12|_l_rts<<6 |_l_cts_ack) -+static u32 phy_info_6051z[] = { -+ 0x18000000, 0x18000100, 0x18000200, 0x18000300, 0x18000140, -+ 0x18000240, 0x18000340, 0x0C000001, 0x0C000101, 0x0C000201, -+ 0x0C000301, 0x18000401, 0x18000501, 0x18000601, 0x18000701, -+ 0x0C030002, 0x0C030102, 0x0C030202, 0x18030302, 0x18030402, -+ 0x18030502, 0x18030602, 0x1C030702, 0x0C030082, 0x0C030182, -+ 0x0C030282, 0x18030382, 0x18030482, 0x18030582, 0x18030682, -+ 0x1C030782, 0x0C030042, 0x0C030142, 0x0C030242, 0x18030342, -+ 0x18030442, 0x18030542, 0x18030642, 0x1C030742 -+}; -+ -+static u32 phy_info_tbl[] = { -+ 0x0C000000, 0x0C000100, 0x0C000200, 0x0C000300, 0x0C000140, -+ 0x0C000240, 0x0C000340, 0x00000001, 0x00000101, 0x00000201, -+ 0x00000301, 0x0C000401, 0x0C000501, 0x0C000601, 0x0C000701, -+ 0x00030002, 0x00030102, 0x00030202, 0x0C030302, 0x0C030402, -+ 0x0C030502, 0x0C030602, 0x10030702, 0x00030082, 0x00030182, -+ 0x00030282, 0x0C030382, 0x0C030482, 0x0C030582, 0x0C030682, -+ 0x10030782, 0x00030042, 0x00030142, 0x00030242, 0x0C030342, -+ 0x0C030442, 0x0C030542, 0x0C030642, 0x10030742, -+ SET_PHY_INFO(314, 0, 0, 0, 0), -+ SET_PHY_INFO(258, 0, 1, 0, 0), -+ SET_PHY_INFO(223, 0, 1, 0, 0), -+ SET_PHY_INFO(213, 0, 1, 0, 0), -+ SET_PHY_INFO(162, 0, 4, 0, 0), -+ SET_PHY_INFO(127, 0, 4, 0, 0), -+ SET_PHY_INFO(117, 0, 4, 0, 0), -+ SET_PHY_INFO(60, 7, 7, 0, 0), -+ SET_PHY_INFO(52, 7, 7, 0, 0), -+ SET_PHY_INFO(48, 9, 9, 0, 0), -+ SET_PHY_INFO(44, 9, 9, 0, 0), -+ SET_PHY_INFO(44, 11, 11, 0, 0), -+ SET_PHY_INFO(40, 11, 11, 0, 0), -+ SET_PHY_INFO(40, 11, 11, 0, 0), -+ SET_PHY_INFO(40, 11, 11, 0, 0), -+ SET_PHY_INFO(76, 7, 7, 0, 1), -+ SET_PHY_INFO(64, 9, 9, 1, 1), -+ SET_PHY_INFO(60, 9, 9, 2, 1), -+ SET_PHY_INFO(60, 11, 11, 3, 1), -+ SET_PHY_INFO(56, 11, 11, 4, 1), -+ SET_PHY_INFO(56, 11, 11, 5, 1), -+ SET_PHY_INFO(56, 11, 11, 5, 1), -+ SET_PHY_INFO(56, 11, 11, 5, 1), -+ SET_PHY_INFO(76, 7, 7, 6, 1), -+ SET_PHY_INFO(64, 9, 9, 1, 1), -+ SET_PHY_INFO(60, 9, 9, 2, 1), -+ SET_PHY_INFO(60, 11, 11, 3, 1), -+ SET_PHY_INFO(56, 11, 11, 4, 1), -+ SET_PHY_INFO(56, 11, 11, 5, 1), -+ SET_PHY_INFO(56, 11, 11, 5, 1), -+ SET_PHY_INFO(56, 11, 11, 5, 1), -+ SET_PHY_INFO(64, 7, 7, 0, 0), -+ SET_PHY_INFO(52, 9, 9, 0, 0), -+ SET_PHY_INFO(48, 9, 9, 0, 0), -+ SET_PHY_INFO(48, 11, 11, 0, 0), -+ SET_PHY_INFO(44, 11, 11, 0, 0), -+ SET_PHY_INFO(44, 11, 11, 0, 0), -+ SET_PHY_INFO(44, 11, 11, 0, 0), -+ SET_PHY_INFO(44, 11, 11, 0, 0), -+ SET_PHY_L_LENGTH(50, 38, 35), -+ SET_PHY_L_LENGTH(35, 29, 26), -+ SET_PHY_L_LENGTH(29, 26, 23), -+ SET_PHY_L_LENGTH(26, 23, 23), -+ SET_PHY_L_LENGTH(23, 23, 20), -+ SET_PHY_L_LENGTH(23, 20, 20), -+ SET_PHY_L_LENGTH(47, 38, 35), -+ SET_PHY_L_LENGTH(0, 0, 0), -+}; -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/drv_comm.h b/drivers/net/wireless/ssv6051/smac/drv_comm.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/drv_comm.h -@@ -0,0 +1,61 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _DRV_COMM_H_ -+#define _DRV_COMM_H_ -+#define PHY_INFO_TBL1_SIZE 39 -+#define PHY_INFO_TBL2_SIZE 39 -+#define PHY_INFO_TBL3_SIZE 8 -+#define ampdu_fw_rate_info_status_no_use BIT(0) -+#define ampdu_fw_rate_info_status_in_use BIT(1) -+#define ampdu_fw_rate_info_status_reset BIT(2) -+#define SSV_NUM_STA 8 -+#define SSV_NUM_VIF 2 -+#define SECURITY_KEY_LEN (32) -+enum SSV_CIPHER_E { -+ SSV_CIPHER_NONE, -+ SSV_CIPHER_WEP40, -+ SSV_CIPHER_WEP104, -+ SSV_CIPHER_TKIP, -+ SSV_CIPHER_CCMP, -+ SSV_CIPHER_SMS4, -+ SSV_CIPHER_INVALID = (-1) -+}; -+#define ME_NONE 0 -+#define ME_WEP40 1 -+#define ME_WEP104 2 -+#define ME_TKIP 3 -+#define ME_CCMP 4 -+#define ME_SMS4 5 -+struct ssv6xxx_hw_key { -+ u8 key[SECURITY_KEY_LEN]; -+ u32 tx_pn_l; -+ u32 tx_pn_h; -+ u32 rx_pn_l; -+ u32 rx_pn_h; -+} __attribute__((packed)); -+struct ssv6xxx_hw_sta_key { -+ u8 pair_key_idx:4; -+ u8 group_key_idx:4; -+ u8 valid; -+ u8 reserve[2]; -+ struct ssv6xxx_hw_key pair; -+} __attribute__((packed)); -+struct ssv6xxx_hw_sec { -+ struct ssv6xxx_hw_key group_key[3]; -+ struct ssv6xxx_hw_sta_key sta_key[8]; -+} __attribute__((packed)); -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/efuse.c b/drivers/net/wireless/ssv6051/smac/efuse.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/efuse.c -@@ -0,0 +1,334 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include "efuse.h" -+ -+struct file *openFile(char *path, int flag, int mode) -+{ -+ struct file *fp = NULL; -+ fp = filp_open(path, flag, 0); -+ if (IS_ERR(fp)) -+ return NULL; -+ else -+ return fp; -+} -+ -+int readFile(struct file *fp, char *buf, int readlen) -+{ -+ if (fp->f_op && fp->f_op->read) -+ return fp->f_op->read(fp, buf, readlen, &fp->f_pos); -+ else -+ return -1; -+} -+ -+int closeFile(struct file *fp) -+{ -+ filp_close(fp, NULL); -+ return 0; -+} -+ -+void initKernelEnv(void) -+{ -+} -+ -+void parseMac(char *mac, u_int8_t addr[]) -+{ -+ long b; -+ int i; -+ for (i = 0; i < 6; i++) { -+ b = simple_strtol(mac + (3 * i), (char **)NULL, 16); -+ addr[i] = (char)b; -+ } -+} -+ -+static int readfile_mac(u8 * path, u8 * mac_addr) -+{ -+ char buf[128]; -+ struct file *fp = NULL; -+ int ret = 0; -+ fp = openFile(path, O_RDONLY, 0); -+ if (fp != NULL) { -+ initKernelEnv(); -+ memset(buf, 0, 128); -+ if ((ret = readFile(fp, buf, 128)) > 0) { -+ parseMac(buf, (uint8_t *) mac_addr); -+ } else -+ pr_err("read file error %d=[%s]\n", ret, path); -+ closeFile(fp); -+ } else -+ pr_err("Read open File fail[%s]!!!! \n", path); -+ return ret; -+} -+ -+static int write_mac_to_file(u8 * mac_path, u8 * mac_addr) -+{ -+ char buf[128]; -+ struct file *fp = NULL; -+ int ret = 0, len; -+ fp = openFile(mac_path, O_WRONLY | O_CREAT, 0640); -+ if (fp != NULL) { -+ initKernelEnv(); -+ memset(buf, 0, 128); -+ sprintf(buf, "%x:%x:%x:%x:%x:%x", mac_addr[0], mac_addr[1], -+ mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]); -+ len = strlen(buf) + 1; -+ fp->f_op->write(fp, (char *)buf, len, &fp->f_pos); -+ closeFile(fp); -+ } else -+ pr_err("Write open File fail!!!![%s] \n", mac_path); -+ return ret; -+} -+ -+static struct efuse_map SSV_EFUSE_ITEM_TABLE[] = { -+ {4, 0, 0}, -+ {4, 8, 0}, -+ {4, 8, 0}, -+ {4, 48, 0}, -+ {4, 8, 0}, -+ {4, 8, 0}, -+ {4, 8, 0}, -+}; -+ -+static u8 read_efuse(struct ssv_hw *sh, u8 * pbuf) -+{ -+ extern struct ssv6xxx_cfg ssv_cfg; -+ u32 val, i; -+ u32 *temp = (u32 *) pbuf; -+ SMAC_REG_WRITE(sh, 0xC0000328, 0x11); -+ SMAC_REG_WRITE(sh, SSV_EFUSE_ID_READ_SWITCH, 0x1); -+ SMAC_REG_READ(sh, SSV_EFUSE_ID_RAW_DATA_BASE, &val); -+ ssv_cfg.chip_identity = val; -+ SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH, 0x1); -+ SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE, &val); -+ if (val == 0x00) { -+ return 0; -+ } -+ for (i = 0; i < (EFUSE_MAX_SECTION_MAP); i++) { -+ SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH + i * 4, 0x1); -+ SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE + i * 4, &val); -+ *temp++ = val; -+ } -+ SMAC_REG_WRITE(sh, 0xC0000328, 0x1800000a); -+ return 1; -+} -+ -+static u16 parser_efuse(u8 * pbuf, u8 * mac_addr) -+{ -+ u8 *rtemp8, idx = 0; -+ u16 shift = 0, i; -+ u16 efuse_real_content_len = 0; -+ rtemp8 = pbuf; -+ if (*rtemp8 == 0x00) { -+ return efuse_real_content_len; -+ } -+ do { -+ idx = (*(rtemp8) >> shift) & 0xf; -+ switch (idx) { -+ case EFUSE_R_CALIBRATION_RESULT: -+ case EFUSE_CRYSTAL_FREQUENCY_OFFSET: -+ case EFUSE_TX_POWER_INDEX_1: -+ case EFUSE_TX_POWER_INDEX_2: -+ case EFUSE_SAR_RESULT: -+ if (shift) { -+ rtemp8++; -+ SSV_EFUSE_ITEM_TABLE[idx].value = -+ (u16) ((u8) (*((u16 *) rtemp8)) & -+ ((1 << -+ SSV_EFUSE_ITEM_TABLE -+ [idx].byte_cnts) - 1)); -+ } else { -+ SSV_EFUSE_ITEM_TABLE[idx].value = -+ (u16) ((u8) (*((u16 *) rtemp8) >> 4) & -+ ((1 << -+ SSV_EFUSE_ITEM_TABLE -+ [idx].byte_cnts) - 1)); -+ } -+ efuse_real_content_len += -+ (SSV_EFUSE_ITEM_TABLE[idx].offset + -+ SSV_EFUSE_ITEM_TABLE[idx].byte_cnts); -+ break; -+ case EFUSE_MAC: -+ if (shift) { -+ rtemp8++; -+ memcpy(mac_addr, rtemp8, 6); -+ } else { -+ for (i = 0; i < 6; i++) { -+ mac_addr[i] = -+ (u16) (*((u16 *) rtemp8) >> 4) & -+ 0xff; -+ rtemp8++; -+ } -+ } -+ efuse_real_content_len += -+ (SSV_EFUSE_ITEM_TABLE[idx].offset + -+ SSV_EFUSE_ITEM_TABLE[idx].byte_cnts); -+ break; -+ default: -+ idx = 0; -+ break; -+ } -+ shift = efuse_real_content_len % 8; -+ rtemp8 = &pbuf[efuse_real_content_len / 8]; -+ } while (idx != 0); -+ return efuse_real_content_len; -+} -+ -+void addr_increase_copy(u8 * dst, u8 * src) -+{ -+ u8 *a = (u8 *) dst; -+ const u8 *b = (const u8 *)src; -+ a[0] = b[0]; -+ a[1] = b[1]; -+ a[2] = b[2]; -+ a[3] = b[3]; -+ a[4] = b[4]; -+ if (b[5] & 0x1) -+ a[5] = b[5] - 1; -+ else -+ a[5] = b[5] + 1; -+} -+ -+static u8 key_char2num(u8 ch) -+{ -+ if ((ch >= '0') && (ch <= '9')) -+ return ch - '0'; -+ else if ((ch >= 'a') && (ch <= 'f')) -+ return ch - 'a' + 10; -+ else if ((ch >= 'A') && (ch <= 'F')) -+ return ch - 'A' + 10; -+ else -+ return 0xff; -+} -+ -+u8 key_2char2num(u8 hch, u8 lch) -+{ -+ return ((key_char2num(hch) << 4) | key_char2num(lch)); -+} -+ -+extern struct ssv6xxx_cfg ssv_cfg; -+extern char *ssv_initmac; -+void efuse_read_all_map(struct ssv_hw *sh) -+{ -+ u8 mac[ETH_ALEN] = { 0 }; -+ int jj, kk; -+ u8 efuse_mapping_table[EFUSE_HWSET_MAX_SIZE / 8]; -+#ifndef CONFIG_SSV_RANDOM_MAC -+ u8 pseudo_mac0[ETH_ALEN] = { 0x00, 0x33, 0x33, 0x33, 0x33, 0x33 }; -+#endif -+ u8 rom_mac0[ETH_ALEN]; -+ memset(rom_mac0, 0x00, ETH_ALEN); -+ memset(efuse_mapping_table, 0x00, EFUSE_HWSET_MAX_SIZE / 8); -+ read_efuse(sh, efuse_mapping_table); -+ parser_efuse(efuse_mapping_table, rom_mac0); -+ ssv_cfg.r_calbration_result = -+ (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_R_CALIBRATION_RESULT].value; -+ ssv_cfg.sar_result = (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_SAR_RESULT].value; -+ ssv_cfg.crystal_frequency_offset = -+ (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_CRYSTAL_FREQUENCY_OFFSET].value; -+ ssv_cfg.tx_power_index_1 = -+ (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_1].value; -+ ssv_cfg.tx_power_index_2 = -+ (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_2].value; -+ if (!is_valid_ether_addr(&sh->cfg.maddr[0][0])) { -+ if (!sh->cfg.ignore_efuse_mac) { -+ if (is_valid_ether_addr(rom_mac0)) { -+ dev_info(sh->sc->dev, "Using MAC address from e-fuse\n"); -+ memcpy(&sh->cfg.maddr[0][0], rom_mac0, -+ ETH_ALEN); -+ addr_increase_copy(&sh->cfg.maddr[1][0], -+ rom_mac0); -+ goto Done; -+ } -+ } -+ if (ssv_initmac != NULL) { -+ for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) { -+ mac[jj] = -+ key_2char2num(ssv_initmac[kk], -+ ssv_initmac[kk + 1]); -+ } -+ if (is_valid_ether_addr(mac)) { -+ dev_info(sh->sc->dev, "Using MAC address from module option\n"); -+ memcpy(&sh->cfg.maddr[0][0], mac, ETH_ALEN); -+ addr_increase_copy(&sh->cfg.maddr[1][0], mac); -+ goto Done; -+ } -+ } -+ if (sh->cfg.mac_address_path[0] != 0x00) { -+ if ((readfile_mac -+ (sh->cfg.mac_address_path, &sh->cfg.maddr[0][0])) -+ && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) { -+ dev_info -+ (sh->sc->dev, "Using MAC address from configuration file\n"); -+ addr_increase_copy(&sh->cfg.maddr[1][0], -+ &sh->cfg.maddr[0][0]); -+ goto Done; -+ } -+ } -+ switch (sh->cfg.mac_address_mode) { -+ case 1: -+ get_random_bytes(&sh->cfg.maddr[0][0], ETH_ALEN); -+ sh->cfg.maddr[0][0] = sh->cfg.maddr[0][0] & 0xF0; -+ addr_increase_copy(&sh->cfg.maddr[1][0], -+ &sh->cfg.maddr[0][0]); -+ break; -+ case 2: -+ if ((readfile_mac -+ (sh->cfg.mac_output_path, &sh->cfg.maddr[0][0])) -+ && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) { -+ addr_increase_copy(&sh->cfg.maddr[1][0], -+ &sh->cfg.maddr[0][0]); -+ } else { -+ { -+ get_random_bytes(&sh->cfg.maddr[0][0], -+ ETH_ALEN); -+ sh->cfg.maddr[0][0] = -+ sh->cfg.maddr[0][0] & 0xF0; -+ addr_increase_copy(&sh->cfg.maddr[1][0], -+ &sh-> -+ cfg.maddr[0][0]); -+ if (sh->cfg.mac_output_path[0] != 0x00) -+ write_mac_to_file(sh-> -+ cfg.mac_output_path, -+ &sh-> -+ cfg.maddr[0] -+ [0]); -+ } -+ } -+ break; -+ default: -+ memcpy(&sh->cfg.maddr[0][0], pseudo_mac0, ETH_ALEN); -+ addr_increase_copy(&sh->cfg.maddr[1][0], pseudo_mac0); -+ break; -+ } -+ dev_info(sh->sc->dev, "MAC address from Software MAC mode[%d]\n", -+ sh->cfg.mac_address_mode); -+ } -+ Done: -+ dev_info(sh->sc->dev, "Chip identity from efuse: %08x\n", ssv_cfg.chip_identity); -+ dev_dbg(sh->sc->dev, "r_calbration_result- %x\n", ssv_cfg.r_calbration_result); -+ dev_dbg(sh->sc->dev, "sar_result- %x\n", ssv_cfg.sar_result); -+ dev_dbg(sh->sc->dev, "crystal_frequency_offset- %x\n", -+ ssv_cfg.crystal_frequency_offset); -+ dev_dbg(sh->sc->dev, "tx_power_index_1- %x\n", ssv_cfg.tx_power_index_1); -+ dev_dbg(sh->sc->dev, "tx_power_index_2- %x\n", ssv_cfg.tx_power_index_2); -+ dev_dbg(sh->sc->dev, "MAC address - %pM\n", rom_mac0); -+ sh->cfg.crystal_frequency_offset = ssv_cfg.crystal_frequency_offset; -+ sh->cfg.tx_power_index_1 = ssv_cfg.tx_power_index_1; -+ sh->cfg.tx_power_index_2 = ssv_cfg.tx_power_index_2; -+ sh->cfg.chip_identity = ssv_cfg.chip_identity; -+} -diff --git a/drivers/net/wireless/ssv6051/smac/efuse.h b/drivers/net/wireless/ssv6051/smac/efuse.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/efuse.h -@@ -0,0 +1,40 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV_EFUSE_H_ -+#define _SSV_EFUSE_H_ -+#include "dev.h" -+struct efuse_map { -+ u8 offset; -+ u8 byte_cnts; -+ u16 value; -+}; -+enum efuse_data_item { -+ EFUSE_R_CALIBRATION_RESULT = 1, -+ EFUSE_SAR_RESULT, -+ EFUSE_MAC, -+ EFUSE_CRYSTAL_FREQUENCY_OFFSET, -+ EFUSE_TX_POWER_INDEX_1, -+ EFUSE_TX_POWER_INDEX_2 -+}; -+#define EFUSE_HWSET_MAX_SIZE (256-32) -+#define EFUSE_MAX_SECTION_MAP (EFUSE_HWSET_MAX_SIZE>>5) -+#define SSV_EFUSE_ID_READ_SWITCH 0xC2000128 -+#define SSV_EFUSE_ID_RAW_DATA_BASE 0xC200014C -+#define SSV_EFUSE_READ_SWITCH 0xC200012C -+#define SSV_EFUSE_RAW_DATA_BASE 0xC2000150 -+void efuse_read_all_map(struct ssv_hw *sh); -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/init.c b/drivers/net/wireless/ssv6051/smac/init.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/init.c -@@ -0,0 +1,1347 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0) -+#include -+#else -+#include -+#endif -+#include -+#include -+#include -+#include "dev_tbl.h" -+#include "dev.h" -+#include "lib.h" -+#include "ssv_rc.h" -+#include "ap.h" -+#include "efuse.h" -+#include "sar.h" -+#include "ssv_cfgvendor.h" -+ -+#include "linux_80211.h" -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+#include "ssv6xxx_debugfs.h" -+#endif -+ -+#define WIFI_FIRMWARE_NAME "ssv6051-sw.bin" -+static const struct ieee80211_iface_limit ssv6xxx_p2p_limits[] = { -+ { -+ .max = 2, -+ .types = BIT(NL80211_IFTYPE_STATION), -+ }, -+ { -+ .max = 1, -+ .types = BIT(NL80211_IFTYPE_P2P_GO) | -+ BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_AP), -+ }, -+}; -+ -+static const struct ieee80211_iface_combination -+ ssv6xxx_iface_combinations_p2p[] = { -+ {.num_different_channels = 1, -+ .max_interfaces = SSV6200_MAX_VIF, -+ .beacon_int_infra_match = true, -+ .limits = ssv6xxx_p2p_limits, -+ .n_limits = ARRAY_SIZE(ssv6xxx_p2p_limits), -+ }, -+}; -+ -+#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ -+ (((a) & 0xff00ff00) >> 8)) -+#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) -+#define CHAN2G(_freq,_idx) { \ -+ .band = INDEX_80211_BAND_2GHZ, \ -+ .center_freq = (_freq), \ -+ .hw_value = (_idx), \ -+ .max_power = 20, \ -+} -+#ifndef WLAN_CIPHER_SUITE_SMS4 -+#define WLAN_CIPHER_SUITE_SMS4 0x00147201 -+#endif -+#define SHPCHECK(__hw_rate,__flags) \ -+ ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate +3 ) : 0) -+#define RATE(_bitrate,_hw_rate,_flags) { \ -+ .bitrate = (_bitrate), \ -+ .flags = (_flags), \ -+ .hw_value = (_hw_rate), \ -+ .hw_value_short = SHPCHECK(_hw_rate,_flags) \ -+} -+extern struct ssv6xxx_cfg ssv_cfg; -+static const struct ieee80211_channel ssv6200_2ghz_chantable[] = { -+ CHAN2G(2412, 1), -+ CHAN2G(2417, 2), -+ CHAN2G(2422, 3), -+ CHAN2G(2427, 4), -+ CHAN2G(2432, 5), -+ CHAN2G(2437, 6), -+ CHAN2G(2442, 7), -+ CHAN2G(2447, 8), -+ CHAN2G(2452, 9), -+ CHAN2G(2457, 10), -+ CHAN2G(2462, 11), -+ CHAN2G(2467, 12), -+ CHAN2G(2472, 13), -+ CHAN2G(2484, 14), -+}; -+ -+static struct ieee80211_rate ssv6200_legacy_rates[] = { -+ RATE(10, 0x00, 0), -+ RATE(20, 0x01, IEEE80211_RATE_SHORT_PREAMBLE), -+ RATE(55, 0x02, IEEE80211_RATE_SHORT_PREAMBLE), -+ RATE(110, 0x03, IEEE80211_RATE_SHORT_PREAMBLE), -+ RATE(60, 0x07, 0), -+ RATE(90, 0x08, 0), -+ RATE(120, 0x09, 0), -+ RATE(180, 0x0a, 0), -+ RATE(240, 0x0b, 0), -+ RATE(360, 0x0c, 0), -+ RATE(480, 0x0d, 0), -+ RATE(540, 0x0e, 0), -+}; -+ -+struct ssv6xxx_ch_cfg ch_cfg_z[] = { -+ {ADR_ABB_REGISTER_1, 0, 0x151559fc}, -+ {ADR_LDO_REGISTER, 0, 0x00eb7c1c}, -+ {ADR_RX_ADC_REGISTER, 0, 0x20d000d2} -+}; -+ -+struct ssv6xxx_ch_cfg ch_cfg_p[] = { -+ {ADR_ABB_REGISTER_1, 0, 0x151559fc}, -+ {ADR_RX_ADC_REGISTER, 0, 0x20d000d2} -+}; -+ -+int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg) -+{ -+ struct sk_buff *skb; -+ struct cfg_host_cmd *host_cmd; -+ int ret = 0; -+ dev_dbg(sh->sc->dev, "# Do init_cali (iq)\n"); -+ skb = -+ ssv_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + -+ RF_SETTING_SIZE); -+ if (skb == NULL) { -+ dev_err(sh->sc->dev, "init ssv6xxx_do_iq_calib failure\n"); -+ return (-1); -+ } -+ if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) || -+ (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) { -+ dev_warn(sh->sc->dev, "wrong RF or PHY table size\n"); -+ WARN_ON(1); -+ return (-1); -+ } -+ skb->data_len = -+ HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE; -+ skb->len = skb->data_len; -+ host_cmd = (struct cfg_host_cmd *)skb->data; -+ host_cmd->c_type = HOST_CMD; -+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI; -+ host_cmd->len = skb->data_len; -+ p_cfg->phy_tbl_size = PHY_SETTING_SIZE; -+ p_cfg->rf_tbl_size = RF_SETTING_SIZE; -+ memcpy(host_cmd->dat32, p_cfg, IQK_CFG_LEN); -+ memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE); -+ memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, ssv6200_rf_tbl, -+ RF_SETTING_SIZE); -+ sh->hci.hci_ops->hci_send_cmd(skb); -+ ssv_skb_free(skb); -+ { -+ u32 timeout; -+ sh->sc->iq_cali_done = IQ_CALI_RUNNING; -+ set_current_state(TASK_INTERRUPTIBLE); -+ timeout = wait_event_interruptible_timeout(sh->sc->fw_wait_q, -+ sh->sc->iq_cali_done, -+ msecs_to_jiffies -+ (500)); -+ set_current_state(TASK_RUNNING); -+ if (timeout == 0) -+ return -ETIME; -+ if (sh->sc->iq_cali_done != IQ_CALI_OK) -+ return (-1); -+ } -+ return ret; -+} -+ -+#define HT_CAP_RX_STBC_ONE_STREAM 0x1 -+#if defined(CONFIG_PM) -+static const struct wiphy_wowlan_support wowlan_support = { -+#ifdef SSV_WAKEUP_HOST -+ .flags = WIPHY_WOWLAN_ANY, -+#else -+ .flags = WIPHY_WOWLAN_DISCONNECT, -+#endif -+ .n_patterns = 0, -+ .pattern_max_len = 0, -+ .pattern_min_len = 0, -+ .max_pkt_offset = 0, -+}; -+#endif -+static void ssv6xxx_set_80211_hw_capab(struct ssv_softc *sc) -+{ -+ struct ieee80211_hw *hw = sc->hw; -+ struct ssv_hw *sh = sc->sh; -+ struct ieee80211_sta_ht_cap *ht_info; -+ ieee80211_hw_set(hw, SIGNAL_DBM); -+ hw->rate_control_algorithm = "ssv6xxx_rate_control"; -+ //hw->rate_control_algorithm = NULL; // NULL selects default -+ ht_info = &sc->sbands[INDEX_80211_BAND_2GHZ].ht_cap; -+ ampdu_db_log("sh->cfg.hw_caps = 0x%x\n", sh->cfg.hw_caps); -+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_HT) { -+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX) { -+ ieee80211_hw_set(hw, AMPDU_AGGREGATION); -+ ampdu_db_log("set IEEE80211_HW_AMPDU_AGGREGATION(%d)\n", -+ ieee80211_hw_check(hw, AMPDU_AGGREGATION)); -+ } -+ ht_info->cap = IEEE80211_HT_CAP_SM_PS; -+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_GF) { -+ ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; -+ ht_info->cap |= -+ HT_CAP_RX_STBC_ONE_STREAM << -+ IEEE80211_HT_CAP_RX_STBC_SHIFT; -+ } -+ if (sh->cfg.hw_caps & SSV6200_HT_CAP_SGI_20) -+ ht_info->cap |= IEEE80211_HT_CAP_SGI_20; -+ ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_32K; -+ ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; -+ memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); -+ ht_info->mcs.rx_mask[0] = 0xff; -+ ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; -+ ht_info->mcs.rx_highest = cpu_to_le16(SSV6200_RX_HIGHEST_RATE); -+ ht_info->ht_supported = true; -+ } -+ hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); -+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) { -+ hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_CLIENT); -+ hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_GO); -+ hw->wiphy->iface_combinations = ssv6xxx_iface_combinations_p2p; -+ hw->wiphy->n_iface_combinations = -+ ARRAY_SIZE(ssv6xxx_iface_combinations_p2p); -+ } -+ hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; -+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_AP) { -+ hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP); -+ hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; -+ } -+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_TDLS) { -+ hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; -+ hw->wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP; -+ dev_info(sc->dev, "TDLS function enabled in sta.cfg\n"); -+ } -+ hw->queues = 4; -+ hw->max_rates = 4; -+ hw->max_listen_interval = 1; -+ hw->max_rate_tries = HW_MAX_RATE_TRIES; -+ hw->extra_tx_headroom = TXPB_OFFSET + AMPDU_DELIMITER_LEN; -+ if (sizeof(struct ampdu_hdr_st) > SSV_SKB_info_size) -+ hw->extra_tx_headroom += sizeof(struct ampdu_hdr_st); -+ else -+ hw->extra_tx_headroom += SSV_SKB_info_size; -+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) { -+ hw->wiphy->bands[INDEX_80211_BAND_2GHZ] = -+ &sc->sbands[INDEX_80211_BAND_2GHZ]; -+ } -+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX) -+#ifdef PREFER_RX -+ hw->max_rx_aggregation_subframes = 64; -+#else -+ hw->max_rx_aggregation_subframes = 16; -+#endif -+ else -+ hw->max_rx_aggregation_subframes = 12; -+ hw->max_tx_aggregation_subframes = 64; -+ hw->sta_data_size = sizeof(struct ssv_sta_priv_data); -+ hw->vif_data_size = sizeof(struct ssv_vif_priv_data); -+ memcpy(sh->maddr[0].addr, &sh->cfg.maddr[0][0], ETH_ALEN); -+ hw->wiphy->addresses = sh->maddr; -+ hw->wiphy->n_addresses = 1; -+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) { -+ int i; -+ for (i = 1; i < SSV6200_MAX_HW_MAC_ADDR; i++) { -+ memcpy(sh->maddr[i].addr, sh->maddr[i - 1].addr, -+ ETH_ALEN); -+ sh->maddr[i].addr[5]++; -+ hw->wiphy->n_addresses++; -+ } -+ } -+ if (!is_zero_ether_addr(sh->cfg.maddr[1])) { -+ memcpy(sh->maddr[1].addr, sh->cfg.maddr[1], ETH_ALEN); -+ if (hw->wiphy->n_addresses < 2) -+ hw->wiphy->n_addresses = 2; -+ } -+#if defined(CONFIG_PM) -+ hw->wiphy->wowlan = &wowlan_support; -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) && defined(CONFIG_SSV_VENDOR_EXT_SUPPORT) -+ { -+ int err = 0; -+ struct ssv_softc *softc = (struct ssv_softc *)hw->priv; -+ if (softc) -+ { -+ set_wiphy_dev(hw->wiphy, softc->dev); -+ *((struct ssv_softc **)wiphy_priv(hw->wiphy)) = softc; -+ } -+ dev_dbg(sc->dev, "Registering Vendor80211\n"); -+ err = ssv_cfgvendor_attach(hw->wiphy); -+ if (unlikely(err < 0)) { -+ dev_err(sc->dev, "Couldn not attach vendor commands (%d)\n", err); -+ } -+ } -+#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */ -+} -+ -+void ssv6xxx_watchdog_restart_hw(struct ssv_softc *sc) -+{ -+ dev_dbg(sc->dev, "%s()\n", __FUNCTION__); -+ sc->restart_counter++; -+ sc->force_triger_reset = true; -+ sc->beacon_info[0].pubf_addr = 0x00; -+ sc->beacon_info[1].pubf_addr = 0x00; -+ ieee80211_restart_hw(sc->hw); -+} -+ -+extern struct rssi_res_st rssi_res; -+void ssv6200_watchdog_timeout(struct timer_list *t) -+{ -+ static u32 count = 0; -+ struct rssi_res_st *rssi_tmp0 = NULL, *rssi_tmp1 = NULL; -+ struct ssv_softc *sc = from_timer(sc, t, watchdog_timeout); -+ if (sc->watchdog_flag == WD_BARKING) { -+ ssv6xxx_watchdog_restart_hw(sc); -+ mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT); -+ return; -+ } -+ if (sc->watchdog_flag != WD_SLEEP) -+ sc->watchdog_flag = WD_BARKING; -+ count++; -+ if (count == 6) { -+ count = 0; -+ if (list_empty(&rssi_res.rssi_list)) { -+ return; -+ } -+ list_for_each_entry_safe(rssi_tmp0, rssi_tmp1, -+ &rssi_res.rssi_list, rssi_list) { -+ if (rssi_tmp0->timeout) { -+ list_del_rcu(&rssi_tmp0->rssi_list); -+ kfree(rssi_tmp0); -+ } -+ } -+ } -+ mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT); -+ return; -+} -+ -+static void ssv6xxx_preload_sw_cipher(void) -+{ -+} -+ -+static int ssv6xxx_init_softc(struct ssv_softc *sc) -+{ -+ void *channels; -+ int ret = 0; -+ sc->sc_flags = SC_OP_INVALID; -+ mutex_init(&sc->mutex); -+ mutex_init(&sc->mem_mutex); -+ sc->config_wq = create_singlethread_workqueue("ssv6xxx_cong_wq"); -+ sc->thermal_wq = create_singlethread_workqueue("ssv6xxx_thermal_wq"); -+ INIT_DELAYED_WORK(&sc->thermal_monitor_work, thermal_monitor); -+ INIT_WORK(&sc->set_tim_work, ssv6200_set_tim_work); -+ INIT_WORK(&sc->bcast_start_work, ssv6200_bcast_start_work); -+ INIT_DELAYED_WORK(&sc->bcast_stop_work, ssv6200_bcast_stop_work); -+ INIT_DELAYED_WORK(&sc->bcast_tx_work, ssv6200_bcast_tx_work); -+ INIT_WORK(&sc->set_ampdu_rx_add_work, ssv6xxx_set_ampdu_rx_add_work); -+ INIT_WORK(&sc->set_ampdu_rx_del_work, ssv6xxx_set_ampdu_rx_del_work); -+ sc->mac_deci_tbl = sta_deci_tbl; -+ memset((void *)&sc->tx, 0, sizeof(struct ssv_tx)); -+ sc->tx.hw_txqid[WMM_AC_VO] = 3; -+ sc->tx.ac_txqid[3] = WMM_AC_VO; -+ sc->tx.hw_txqid[WMM_AC_VI] = 2; -+ sc->tx.ac_txqid[2] = WMM_AC_VI; -+ sc->tx.hw_txqid[WMM_AC_BE] = 1; -+ sc->tx.ac_txqid[1] = WMM_AC_BE; -+ sc->tx.hw_txqid[WMM_AC_BK] = 0; -+ sc->tx.ac_txqid[0] = WMM_AC_BK; -+ INIT_LIST_HEAD(&sc->tx.ampdu_tx_que); -+ spin_lock_init(&sc->tx.ampdu_tx_que_lock); -+ memset((void *)&sc->rx, 0, sizeof(struct ssv_rx)); -+ spin_lock_init(&sc->rx.rxq_lock); -+ skb_queue_head_init(&sc->rx.rxq_head); -+ sc->rx.rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE); -+ if (sc->rx.rx_buf == NULL) -+ return -ENOMEM; -+ memset(&sc->bcast_txq, 0, sizeof(struct ssv6xxx_bcast_txq)); -+ spin_lock_init(&sc->bcast_txq.txq_lock); -+ skb_queue_head_init(&sc->bcast_txq.qhead); -+ spin_lock_init(&sc->ps_state_lock); -+#ifdef CONFIG_P2P_NOA -+ spin_lock_init(&sc->p2p_noa.p2p_config_lock); -+#endif -+ if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) { -+ channels = kmemdup(ssv6200_2ghz_chantable, -+ sizeof(ssv6200_2ghz_chantable), GFP_KERNEL); -+ if (!channels) { -+ kfree(sc->rx.rx_buf); -+ return -ENOMEM; -+ } -+ sc->sbands[INDEX_80211_BAND_2GHZ].channels = channels; -+ sc->sbands[INDEX_80211_BAND_2GHZ].band = INDEX_80211_BAND_2GHZ; -+ sc->sbands[INDEX_80211_BAND_2GHZ].n_channels = -+ ARRAY_SIZE(ssv6200_2ghz_chantable); -+ sc->sbands[INDEX_80211_BAND_2GHZ].bitrates = -+ ssv6200_legacy_rates; -+ sc->sbands[INDEX_80211_BAND_2GHZ].n_bitrates = -+ ARRAY_SIZE(ssv6200_legacy_rates); -+ } -+ sc->cur_channel = NULL; -+ sc->hw_chan = (-1); -+ ssv6xxx_set_80211_hw_capab(sc); -+ ret = ssv6xxx_rate_control_register(); -+ if (ret != 0) { -+ dev_warn(sc->dev, "%s(): Failed to register rc algorithm.\n",__FUNCTION__); -+ } -+ init_waitqueue_head(&sc->tx_wait_q); -+ sc->tx_wait_q_woken = 0; -+ skb_queue_head_init(&sc->tx_skb_q); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ sc->max_tx_skb_q_len = 0; -+#endif -+ sc->tx_task = kthread_run(ssv6xxx_tx_task, sc, "ssv6xxx_tx_task"); -+ sc->tx_q_empty = false; -+ skb_queue_head_init(&sc->tx_done_q); -+ init_waitqueue_head(&sc->rx_wait_q); -+ sc->rx_wait_q_woken = 0; -+ skb_queue_head_init(&sc->rx_skb_q); -+ sc->rx_task = kthread_run(ssv6xxx_rx_task, sc, "ssv6xxx_rx_task"); -+ ssv6xxx_preload_sw_cipher(); -+ timer_setup(&sc->watchdog_timeout, ssv6200_watchdog_timeout, 0); -+ init_waitqueue_head(&sc->fw_wait_q); -+ INIT_LIST_HEAD(&rssi_res.rssi_list); -+ rssi_res.rssi = 0; -+ mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT); -+ //add_timer(&sc->watchdog_timeout); -+ //if(get_flash_info(sc) == 1) -+ sc->is_sar_enabled = get_flash_info(sc); -+ if (sc->is_sar_enabled) -+ queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work, -+ THERMAL_MONITOR_TIME); -+ //schedule_delayed_work(&sc->thermal_monitor_work, THERMAL_MONITOR_TIME); -+ return ret; -+} -+ -+static int ssv6xxx_deinit_softc(struct ssv_softc *sc) -+{ -+ void *channels; -+ struct sk_buff *skb; -+ u8 remain_size; -+ dev_dbg(sc->dev, "%s():\n", __FUNCTION__); -+ if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) { -+ channels = sc->sbands[INDEX_80211_BAND_2GHZ].channels; -+ kfree(channels); -+ } -+ ssv_skb_free(sc->rx.rx_buf); -+ sc->rx.rx_buf = NULL; -+ ssv6xxx_rate_control_unregister(); -+ cancel_delayed_work_sync(&sc->bcast_tx_work); -+ //ssv6xxx_watchdog_controller(sc->sh ,(u8)SSV6XXX_HOST_CMD_WATCHDOG_STOP); -+ del_timer_sync(&sc->watchdog_timeout); -+ cancel_delayed_work(&sc->thermal_monitor_work); -+ sc->ps_status = PWRSV_PREPARE; -+ flush_workqueue(sc->thermal_wq); -+ destroy_workqueue(sc->thermal_wq); -+ do { -+ skb = ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size); -+ if (skb) -+ ssv6xxx_txbuf_free_skb(skb, (void *)sc); -+ else -+ break; -+ } while (remain_size); -+ if (sc->tx_task != NULL) { -+ dev_dbg(sc->dev, "Stopping TX task...\n"); -+ kthread_stop(sc->tx_task); -+ sc->tx_task = NULL; -+ dev_dbg(sc->dev, "Stopped TX task.\n"); -+ } -+ if (sc->rx_task != NULL) { -+ dev_dbg(sc->dev, "Stopping RX task...\n"); -+ kthread_stop(sc->rx_task); -+ sc->rx_task = NULL; -+ dev_dbg(sc->dev, "Stopped RX task.\n"); -+ } -+ destroy_workqueue(sc->config_wq); -+ return 0; -+} -+ -+static void ssv6xxx_hw_set_replay_ignore(struct ssv_hw *sh, u8 ignore) -+{ -+ u32 temp; -+ SMAC_REG_READ(sh, ADR_SCRT_SET, &temp); -+ temp = temp & SCRT_RPLY_IGNORE_I_MSK; -+ temp |= (ignore << SCRT_RPLY_IGNORE_SFT); -+ SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp); -+} -+ -+int ssv6xxx_init_mac(struct ssv_hw *sh) -+{ -+ struct ssv_softc *sc = sh->sc; -+ int i = 0, ret = 0; -+ -+ u32 *ptr, id_len, regval, temp[0x8]; -+ char *chip_id = sh->chip_id; -+ SMAC_REG_READ(sh, ADR_IC_TIME_TAG_1, ®val); -+ sh->chip_tag = ((u64) regval << 32); -+ SMAC_REG_READ(sh, ADR_IC_TIME_TAG_0, ®val); -+ sh->chip_tag |= (regval); -+ SMAC_REG_READ(sh, ADR_CHIP_ID_3, ®val); -+ *((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval); -+ SMAC_REG_READ(sh, ADR_CHIP_ID_2, ®val); -+ *((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval); -+ SMAC_REG_READ(sh, ADR_CHIP_ID_1, ®val); -+ *((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval); -+ SMAC_REG_READ(sh, ADR_CHIP_ID_0, ®val); -+ *((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval); -+ chip_id[12 + sizeof(u32)] = 0; -+ dev_info(sh->sc->dev, "chip id: %s, tag: %llx\n", chip_id, sh->chip_tag); -+ if (sc->ps_status == PWRSV_ENABLE) { -+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA, -+ M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) | -+ (M_ENG_HWHCI << 8)); -+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG, -+ M_ENG_MACRX | (M_ENG_HWHCI << 4)); -+#if Enable_AMPDU_FW_Retry -+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, -+ M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << -+ 8)); -+#else -+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, -+ M_ENG_MACRX | (M_ENG_HWHCI << 4)); -+#endif -+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4, -+ (sc->mac_deci_tbl[6])); -+ return ret; -+ } -+ SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (0 << RG_PHY_MD_EN_SFT), -+ RG_PHY_MD_EN_MSK); -+ SMAC_REG_WRITE(sh, ADR_BRG_SW_RST, 1 << MAC_SW_RST_SFT); -+ do { -+ SMAC_REG_READ(sh, ADR_BRG_SW_RST, ®val); -+ i++; -+ if (i > 10000) { -+ dev_err(sh->sc->dev, "MAC reset fail !!!!\n"); -+ WARN_ON(1); -+ ret = 1; -+ goto exit; -+ } -+ } while (regval != 0); -+ SMAC_REG_WRITE(sc->sh, ADR_TXQ4_MTX_Q_AIFSN, 0xffff2101); -+ SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC, 0, -+ MTX_HALT_MNG_UNTIL_DTIM_MSK); -+ SMAC_REG_WRITE(sh, ADR_CONTROL, 0x12000006); -+ SMAC_REG_WRITE(sh, ADR_RX_TIME_STAMP_CFG, -+ ((28 << MRX_STP_OFST_SFT) | 0x01)); -+ SMAC_REG_WRITE(sh, ADR_HCI_TX_RX_INFO_SIZE, -+ ((u32) (TXPB_OFFSET) << TX_PBOFFSET_SFT) | -+ ((u32) (sh->tx_desc_len) << TX_INFO_SIZE_SFT) | -+ ((u32) (sh->rx_desc_len) << RX_INFO_SIZE_SFT) | -+ ((u32) (sh->rx_pinfo_pad) << RX_LAST_PHY_SIZE_SFT) -+ ); -+ SMAC_REG_READ(sh, ADR_MMU_CTRL, ®val); -+ regval |= (0xff << MMU_SHARE_MCU_SFT); -+ SMAC_REG_WRITE(sh, ADR_MMU_CTRL, regval); -+ SMAC_REG_READ(sh, ADR_MRX_WATCH_DOG, ®val); -+ regval &= 0xfffffff0; -+ SMAC_REG_WRITE(sh, ADR_MRX_WATCH_DOG, regval); -+ SMAC_REG_READ(sh, ADR_TRX_ID_THRESHOLD, &id_len); -+ id_len = (id_len & 0xffff0000) | -+ (SSV6200_ID_TX_THRESHOLD << TX_ID_THOLD_SFT) | -+ (SSV6200_ID_RX_THRESHOLD << RX_ID_THOLD_SFT); -+ SMAC_REG_WRITE(sh, ADR_TRX_ID_THRESHOLD, id_len); -+ SMAC_REG_READ(sh, ADR_ID_LEN_THREADSHOLD1, &id_len); -+ id_len = (id_len & 0x0f) | -+ (SSV6200_PAGE_TX_THRESHOLD << ID_TX_LEN_THOLD_SFT) | -+ (SSV6200_PAGE_RX_THRESHOLD << ID_RX_LEN_THOLD_SFT); -+ SMAC_REG_WRITE(sh, ADR_ID_LEN_THREADSHOLD1, id_len); -+#ifdef CONFIG_SSV_CABRIO_MB_DEBUG -+ SMAC_REG_READ(sh, ADR_MB_DBG_CFG3, ®val); -+ regval |= (debug_buffer << 0); -+ SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG3, regval); -+ SMAC_REG_READ(sh, ADR_MB_DBG_CFG2, ®val); -+ regval |= (DEBUG_SIZE << 16); -+ SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG2, regval); -+ SMAC_REG_READ(sh, ADR_MB_DBG_CFG1, ®val); -+ regval |= (1 << MB_DBG_EN_SFT); -+ SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG1, regval); -+ SMAC_REG_READ(sh, ADR_MBOX_HALT_CFG, ®val); -+ regval |= (1 << MB_ERR_AUTO_HALT_EN_SFT); -+ SMAC_REG_WRITE(sh, ADR_MBOX_HALT_CFG, regval); -+#endif -+ SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, ®val); -+ regval |= (1 << MTX_TSF_TIMER_EN_SFT); -+ SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval); -+ SMAC_REG_WRITE(sh, 0xcd010004, 0x1213); -+ for (i = 0; i < SSV_RC_MAX_STA; i++) { -+ if (i == 0) { -+ sh->hw_buf_ptr[i] = -+ ssv6xxx_pbuf_alloc(sc, -+ sizeof(phy_info_tbl) + -+ sizeof(struct ssv6xxx_hw_sec), -+ NOTYPE_BUF); -+ if ((sh->hw_buf_ptr[i] >> 28) != 8) { -+ dev_err(sh->sc->dev, "opps allocate pbuf error\n"); -+ WARN_ON(1); -+ ret = 1; -+ goto exit; -+ } -+ } else { -+ sh->hw_buf_ptr[i] = -+ ssv6xxx_pbuf_alloc(sc, -+ sizeof(struct ssv6xxx_hw_sec), -+ NOTYPE_BUF); -+ if ((sh->hw_buf_ptr[i] >> 28) != 8) { -+ dev_err(sh->sc->dev, "opps allocate pbuf error\n"); -+ WARN_ON(1); -+ ret = 1; -+ goto exit; -+ } -+ } -+ } -+ for (i = 0; i < 0x8; i++) { -+ temp[i] = 0; -+ temp[i] = ssv6xxx_pbuf_alloc(sc, 256, NOTYPE_BUF); -+ } -+ for (i = 0; i < 0x8; i++) { -+ if (temp[i] == 0x800e0000) -+ dev_dbg(sh->sc->dev, "Found 0x800e0000 at position %d\n", i); -+ else -+ ssv6xxx_pbuf_free(sc, temp[i]); -+ } -+ for (i = 0; i < SSV_RC_MAX_STA; i++) -+ sh->hw_sec_key[i] = sh->hw_buf_ptr[i]; -+ for (i = 0; i < SSV_RC_MAX_STA; i++) { -+ int x; -+ for (x = 0; x < sizeof(struct ssv6xxx_hw_sec); x += 4) { -+ SMAC_REG_WRITE(sh, sh->hw_sec_key[i] + x, 0); -+ } -+ } -+ SMAC_REG_READ(sh, ADR_SCRT_SET, ®val); -+ regval &= SCRT_PKT_ID_I_MSK; -+ regval |= ((sh->hw_sec_key[0] >> 16) << SCRT_PKT_ID_SFT); -+ SMAC_REG_WRITE(sh, ADR_SCRT_SET, regval); -+ sh->hw_pinfo = sh->hw_sec_key[0] + sizeof(struct ssv6xxx_hw_sec); -+ for (i = 0, ptr = phy_info_tbl; i < PHY_INFO_TBL1_SIZE; i++, ptr++) { -+ SMAC_REG_WRITE(sh, ADR_INFO0 + i * 4, *ptr); -+ SMAC_REG_CONFIRM(sh, ADR_INFO0 + i * 4, *ptr); -+ } -+ for (i = 0; i < PHY_INFO_TBL2_SIZE; i++, ptr++) { -+ SMAC_REG_WRITE(sh, sh->hw_pinfo + i * 4, *ptr); -+ SMAC_REG_CONFIRM(sh, sh->hw_pinfo + i * 4, *ptr); -+ } -+ for (i = 0; i < PHY_INFO_TBL3_SIZE; i++, ptr++) { -+ SMAC_REG_WRITE(sh, sh->hw_pinfo + -+ (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr); -+ SMAC_REG_CONFIRM(sh, sh->hw_pinfo + -+ (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr); -+ } -+ SMAC_REG_WRITE(sh, ADR_INFO_RATE_OFFSET, 0x00040000); -+ SMAC_REG_WRITE(sh, ADR_INFO_IDX_ADDR, sh->hw_pinfo); -+ SMAC_REG_WRITE(sh, ADR_INFO_LEN_ADDR, -+ sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4); -+ dev_dbg(sh->sc->dev, "ADR_INFO_IDX_ADDR[%08x] ADR_INFO_LEN_ADDR[%08x]\n", -+ sh->hw_pinfo, sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4); -+ SMAC_REG_WRITE(sh, ADR_GLBLE_SET, -+ (0 << OP_MODE_SFT) | (0 << SNIFFER_MODE_SFT) | (1 << -+ DUP_FLT_SFT) -+ | (SSV6200_TX_PKT_RSVD_SETTING << TX_PKT_RSVD_SFT) | -+ ((u32) (RXPB_OFFSET) << PB_OFFSET_SFT) -+ ); -+ SMAC_REG_WRITE(sh, ADR_STA_MAC_0, *((u32 *) & sh->cfg.maddr[0][0])); -+ SMAC_REG_WRITE(sh, ADR_STA_MAC_1, *((u32 *) & sh->cfg.maddr[0][4])); -+ SMAC_REG_WRITE(sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0])); -+ SMAC_REG_WRITE(sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4])); -+ SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_0, 0x00000000); -+ SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_1, 0x00000000); -+ SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_0, 0x00000000); -+ SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_1, 0x00000000); -+ SMAC_REG_WRITE(sh, ADR_REASON_TRAP0, 0x7FBC7F87); -+ SMAC_REG_WRITE(sh, ADR_REASON_TRAP1, 0x0000003F); -+ SMAC_REG_WRITE(sh, ADR_TRAP_HW_ID, M_ENG_CPU); -+ SMAC_REG_WRITE(sh, ADR_WSID0, 0x00000000); -+ SMAC_REG_WRITE(sh, ADR_WSID1, 0x00000000); -+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA, -+ M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) | (M_ENG_HWHCI << -+ 8)); -+#if defined(CONFIG_P2P_NOA) || defined(CONFIG_RX_MGMT_CHECK) -+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG, -+ M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8)); -+#else -+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_HWHCI << 4)); -+#endif -+#if Enable_AMPDU_FW_Retry -+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, -+ M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8)); -+#else -+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_HWHCI << 4)); -+#endif -+ ssv6xxx_hw_set_replay_ignore(sh, 1); -+ ssv6xxx_update_decision_table(sc); -+ SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_STA, -+ OP_MODE_MSK); -+ SMAC_REG_WRITE(sh, ADR_SDIO_MASK, 0xfffe1fff); -+ SMAC_REG_WRITE(sh, ADR_TX_LIMIT_INTR, 0x80000000 | -+ SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER << 16 | -+ SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER); -+#ifdef CONFIG_SSV_SUPPORT_BTCX -+ SMAC_REG_WRITE(sh, ADR_BTCX0, -+ COEXIST_EN_MSK | (WIRE_MODE_SZ << WIRE_MODE_SFT) -+ | WIFI_TX_SW_POL_MSK | BT_SW_POL_MSK); -+ SMAC_REG_WRITE(sh, ADR_BTCX1, -+ SSV6200_BT_PRI_SMP_TIME | (SSV6200_BT_STA_SMP_TIME << -+ BT_STA_SMP_TIME_SFT) -+ | (SSV6200_WLAN_REMAIN_TIME << WLAN_REMAIN_TIME_SFT)); -+ SMAC_REG_WRITE(sh, ADR_SWITCH_CTL, BT_2WIRE_EN_MSK); -+ SMAC_REG_WRITE(sh, ADR_PAD7, 1); -+ SMAC_REG_WRITE(sh, ADR_PAD8, 0); -+ SMAC_REG_WRITE(sh, ADR_PAD9, 1); -+ SMAC_REG_WRITE(sh, ADR_PAD25, 1); -+ SMAC_REG_WRITE(sh, ADR_PAD27, 8); -+ SMAC_REG_WRITE(sh, ADR_PAD28, 8); -+#endif -+ dev_info(sh->sc->dev, "attempt to load firmware %s\n", WIFI_FIRMWARE_NAME); -+ ret = SMAC_LOAD_FW(sh, WIFI_FIRMWARE_NAME, 0); -+ -+ SMAC_REG_READ(sh, FW_VERSION_REG, ®val); -+ if (regval == ssv_firmware_version) { -+ SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (1 << RG_PHY_MD_EN_SFT), -+ RG_PHY_MD_EN_MSK); -+ dev_info(sh->sc->dev, "Firmware version %d\n", regval); -+ } else { -+ dev_err(sh->sc->dev, "Firmware version not mapping %d\n", regval); -+ ret = -1; -+ } -+ ssv6xxx_watchdog_controller(sh, (u8) SSV6XXX_HOST_CMD_WATCHDOG_START); -+ exit: -+ return ret; -+} -+ -+void ssv6xxx_deinit_mac(struct ssv_softc *sc) -+{ -+ int i; -+ for (i = 0; i < SSV_RC_MAX_STA; i++) { -+ if (sc->sh->hw_buf_ptr[i]) -+ ssv6xxx_pbuf_free(sc, sc->sh->hw_buf_ptr[i]); -+ } -+} -+ -+void inline ssv6xxx_deinit_hw(struct ssv_softc *sc) -+{ -+ dev_dbg(sc->dev, "%s(): \n", __FUNCTION__); -+ ssv6xxx_deinit_mac(sc); -+} -+ -+void ssv6xxx_restart_hw(struct ssv_softc *sc) -+{ -+ dev_info(sc->dev, "Software MAC reset\n"); -+ sc->restart_counter++; -+ sc->force_triger_reset = true; -+ HCI_STOP(sc->sh); -+ SMAC_REG_WRITE(sc->sh, 0xce000004, 0x0); -+ sc->beacon_info[0].pubf_addr = 0x00; -+ sc->beacon_info[1].pubf_addr = 0x00; -+ ieee80211_restart_hw(sc->hw); -+} -+ -+extern struct ssv6xxx_iqk_cfg init_iqk_cfg; -+static int ssv6xxx_init_hw(struct ssv_hw *sh) -+{ -+ int ret = 0, i = 0, x = 0; -+ u32 regval; -+ sh->tx_desc_len = SSV6XXX_TX_DESC_LEN; -+ sh->rx_desc_len = SSV6XXX_RX_DESC_LEN; -+ sh->rx_pinfo_pad = 0x04; -+ sh->tx_page_available = SSV6200_PAGE_TX_THRESHOLD; -+ sh->ampdu_divider = SSV6XXX_AMPDU_DIVIDER; -+ memset(sh->page_count, 0, sizeof(sh->page_count)); -+ if (sh->cfg.force_chip_identity) { -+ dev_info(sh->sc->dev, "Force use external RF setting [%08x]\n", -+ sh->cfg.force_chip_identity); -+ sh->cfg.chip_identity = sh->cfg.force_chip_identity; -+ } -+ if (sh->cfg.chip_identity == SSV6051Z) { -+ sh->p_ch_cfg = &ch_cfg_z[0]; -+ sh->ch_cfg_size = -+ sizeof(ch_cfg_z) / sizeof(struct ssv6xxx_ch_cfg); -+ memcpy(phy_info_tbl, phy_info_6051z, sizeof(phy_info_6051z)); -+ } else if (sh->cfg.chip_identity == SSV6051P) { -+ sh->p_ch_cfg = &ch_cfg_p[0]; -+ sh->ch_cfg_size = -+ sizeof(ch_cfg_p) / sizeof(struct ssv6xxx_ch_cfg); -+ } -+ switch (sh->cfg.chip_identity) { -+ case SSV6051Q_P1: -+ case SSV6051Q_P2: -+ case SSV6051Q: -+ dev_info(sh->sc->dev, "Using SSV6051Q setting\n"); -+ for (i = 0; -+ i < -+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table); -+ i++) { -+ if (ssv6200_rf_tbl[i].address == 0xCE010008) -+ ssv6200_rf_tbl[i].data = 0x008DF61B; -+ if (ssv6200_rf_tbl[i].address == 0xCE010014) -+ ssv6200_rf_tbl[i].data = 0x3D3E84FE; -+ if (ssv6200_rf_tbl[i].address == 0xCE010018) -+ ssv6200_rf_tbl[i].data = 0x01457D79; -+ if (ssv6200_rf_tbl[i].address == 0xCE01001C) -+ ssv6200_rf_tbl[i].data = 0x000103A7; -+ if (ssv6200_rf_tbl[i].address == 0xCE010020) -+ ssv6200_rf_tbl[i].data = 0x000103A6; -+ if (ssv6200_rf_tbl[i].address == 0xCE01002C) -+ ssv6200_rf_tbl[i].data = 0x00032CA8; -+ if (ssv6200_rf_tbl[i].address == 0xCE010048) -+ ssv6200_rf_tbl[i].data = 0xFCCCCF27; -+ if (ssv6200_rf_tbl[i].address == 0xCE010050) -+ ssv6200_rf_tbl[i].data = 0x0047C000; -+ } -+ break; -+ case SSV6051Z: -+ dev_info(sh->sc->dev, "Using SSV6051Z setting\n"); -+ for (i = 0; -+ i < -+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table); -+ i++) { -+ if (ssv6200_rf_tbl[i].address == 0xCE010008) -+ ssv6200_rf_tbl[i].data = 0x004D561C; -+ if (ssv6200_rf_tbl[i].address == 0xCE010014) -+ ssv6200_rf_tbl[i].data = 0x3D9E84FE; -+ if (ssv6200_rf_tbl[i].address == 0xCE010018) -+ ssv6200_rf_tbl[i].data = 0x00457D79; -+ if (ssv6200_rf_tbl[i].address == 0xCE01001C) -+ ssv6200_rf_tbl[i].data = 0x000103EB; -+ if (ssv6200_rf_tbl[i].address == 0xCE010020) -+ ssv6200_rf_tbl[i].data = 0x000103EA; -+ if (ssv6200_rf_tbl[i].address == 0xCE01002C) -+ ssv6200_rf_tbl[i].data = 0x00062CA8; -+ if (ssv6200_rf_tbl[i].address == 0xCE010048) -+ ssv6200_rf_tbl[i].data = 0xFCCCCF27; -+ if (ssv6200_rf_tbl[i].address == 0xCE010050) -+ ssv6200_rf_tbl[i].data = 0x0047C000; -+ } -+ break; -+ case SSV6051P: -+ dev_info(sh->sc->dev, "Using SSV6051P setting\n"); -+ for (i = 0; -+ i < -+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table); -+ i++) { -+ if (ssv6200_rf_tbl[i].address == 0xCE010008) -+ ssv6200_rf_tbl[i].data = 0x008B7C1C; -+ if (ssv6200_rf_tbl[i].address == 0xCE010014) -+ ssv6200_rf_tbl[i].data = 0x3D7E84FE; -+ if (ssv6200_rf_tbl[i].address == 0xCE010018) -+ ssv6200_rf_tbl[i].data = 0x01457D79; -+ if (ssv6200_rf_tbl[i].address == 0xCE01001C) -+ ssv6200_rf_tbl[i].data = 0x000103EB; -+ if (ssv6200_rf_tbl[i].address == 0xCE010020) -+ ssv6200_rf_tbl[i].data = 0x000103EA; -+ if (ssv6200_rf_tbl[i].address == 0xCE01002C) -+ ssv6200_rf_tbl[i].data = 0x00032CA8; -+ if (ssv6200_rf_tbl[i].address == 0xCE010048) -+ ssv6200_rf_tbl[i].data = 0xFCCCCC27; -+ if (ssv6200_rf_tbl[i].address == 0xCE010050) -+ ssv6200_rf_tbl[i].data = 0x0047C000; -+ if (ssv6200_rf_tbl[i].address == 0xC0001D00) -+ ssv6200_rf_tbl[i].data = 0x5E000040; -+ } -+ break; -+ default: -+ dev_err(sh->sc->dev, "No RF setting\n"); -+ break; -+ } -+ if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M) { -+ init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_26M; -+ dev_info(sh->sc->dev, "Crystal frequency: 26 Mhz\n"); -+ } else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) { -+ init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_40M; -+ dev_info(sh->sc->dev, "Crystal frequency: 40 Mhz\n"); -+ } else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M) { -+ init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_24M; -+ dev_info(sh->sc->dev, "Crystal frequency: 24 Mhz\n"); -+ for (i = 0; -+ i < -+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table); -+ i++) { -+ if (ssv6200_rf_tbl[i].address == ADR_SX_ENABLE_REGISTER) -+ ssv6200_rf_tbl[i].data = 0x0003E07C; -+ if (ssv6200_rf_tbl[i].address == -+ ADR_DPLL_DIVIDER_REGISTER) -+ ssv6200_rf_tbl[i].data = 0x00406000; -+ if (ssv6200_rf_tbl[i].address == -+ ADR_DPLL_FB_DIVIDER_REGISTERS_I) -+ ssv6200_rf_tbl[i].data = 0x00000028; -+ if (ssv6200_rf_tbl[i].address == -+ ADR_DPLL_FB_DIVIDER_REGISTERS_II) -+ ssv6200_rf_tbl[i].data = 0x00000000; -+ } -+ } else { -+ dev_warn(sh->sc->dev, "Illegal crystal setting, using default value of 26 Mhz\n"); -+ } -+ for (i = 0; -+ i < sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table); -+ i++) { -+ if (ssv6200_rf_tbl[i].address == -+ ADR_SYN_KVCO_XO_FINE_TUNE_CBANK) { -+ if (sh->cfg.crystal_frequency_offset) { -+ ssv6200_rf_tbl[i].data &= -+ RG_XOSC_CBANK_XO_I_MSK; -+ ssv6200_rf_tbl[i].data |= -+ (sh->cfg. -+ crystal_frequency_offset << -+ RG_XOSC_CBANK_XO_SFT); -+ } -+ } -+ } -+ for (i = 0; i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table); -+ i++) { -+ if (phy_setting[i].address == ADR_TX_GAIN_FACTOR) { -+ switch (sh->cfg.chip_identity) { -+ case SSV6051Q_P1: -+ case SSV6051Q_P2: -+ case SSV6051Q: -+ dev_dbg(sh->sc->dev, "SSV6051Q setting [0x5B606C72]\n"); -+ phy_setting[i].data = 0x5B606C72; -+ break; -+ case SSV6051Z: -+ dev_dbg(sh->sc->dev, "SSV6051Z setting [0x60606060]\n"); -+ phy_setting[i].data = 0x60606060; -+ break; -+ case SSV6051P: -+ dev_dbg(sh->sc->dev, "SSV6051P setting [0x6C726C72]\n"); -+ phy_setting[i].data = 0x6C726C72; -+ break; -+ default: -+ dev_dbg(sh->sc->dev, "Use default power setting\n"); -+ break; -+ } -+ if (sh->cfg.wifi_tx_gain_level_b) { -+ phy_setting[i].data &= 0xffff0000; -+ phy_setting[i].data |= -+ wifi_tx_gain[sh->cfg. -+ wifi_tx_gain_level_b] & -+ 0x0000ffff; -+ } -+ if (sh->cfg.wifi_tx_gain_level_gn) { -+ phy_setting[i].data &= 0x0000ffff; -+ phy_setting[i].data |= -+ wifi_tx_gain[sh->cfg. -+ wifi_tx_gain_level_gn] & -+ 0xffff0000; -+ } -+ dev_dbg(sh->sc->dev, "TX power setting 0x%x\n", phy_setting[i].data); -+ init_iqk_cfg.cfg_def_tx_scale_11b = -+ (phy_setting[i].data >> 0) & 0xff; -+ init_iqk_cfg.cfg_def_tx_scale_11b_p0d5 = -+ (phy_setting[i].data >> 8) & 0xff; -+ init_iqk_cfg.cfg_def_tx_scale_11g = -+ (phy_setting[i].data >> 16) & 0xff; -+ init_iqk_cfg.cfg_def_tx_scale_11g_p0d5 = -+ (phy_setting[i].data >> 24) & 0xff; -+ break; -+ } -+ } -+ if (sh->cfg.volt_regulator == SSV6XXX_VOLT_LDO_CONVERT) { -+ dev_info(sh->sc->dev, "Using LDO voltage regulator\n"); -+ for (i = 0; -+ i < -+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table); -+ i++) { -+ if (ssv6200_rf_tbl[i].address == ADR_PMU_2) { -+ ssv6200_rf_tbl[i].data &= 0xFFFFFFFE; -+ ssv6200_rf_tbl[i].data |= 0x00000000; -+ } -+ } -+ } else if (sh->cfg.volt_regulator == SSV6XXX_VOLT_DCDC_CONVERT) { -+ dev_info(sh->sc->dev, "Using DCDC buck regulator\n"); -+ for (i = 0; -+ i < -+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table); -+ i++) { -+ if (ssv6200_rf_tbl[i].address == ADR_PMU_2) { -+ ssv6200_rf_tbl[i].data &= 0xFFFFFFFE; -+ ssv6200_rf_tbl[i].data |= 0x00000001; -+ } -+ } -+ } else { -+ dev_warn(sh->sc->dev, "Illegal regulator setting, using DCDC buck as default\n"); -+ } -+ while (ssv_cfg.configuration[x][0]) { -+ for (i = 0; -+ i < -+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table); -+ i++) { -+ if (ssv6200_rf_tbl[i].address == -+ ssv_cfg.configuration[x][0]) { -+ ssv6200_rf_tbl[i].data = -+ ssv_cfg.configuration[x][1]; -+ break; -+ } -+ } -+ for (i = 0; -+ i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table); -+ i++) { -+ if (phy_setting[i].address == -+ ssv_cfg.configuration[x][0]) { -+ phy_setting[i].data = -+ ssv_cfg.configuration[x][1]; -+ break; -+ } -+ } -+ x++; -+ }; -+ if (ret == 0) -+ ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_rf_tbl); -+ if (ret == 0) -+ ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1, 0x00000000); -+ SMAC_REG_READ(sh, ADR_PHY_EN_0, ®val); -+ if (regval & (1 << RG_RF_BB_CLK_SEL_SFT)) { -+ dev_dbg(sh->sc->dev, "already do clock switch\n"); -+ } else { -+ dev_dbg(sh->sc->dev, "reset PLL\n"); -+ SMAC_REG_READ(sh, ADR_DPLL_CP_PFD_REGISTER, ®val); -+ regval |= -+ ((1 << RG_DP_BBPLL_PD_SFT) | -+ (1 << RG_DP_BBPLL_SDM_EDGE_SFT)); -+ SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval); -+ regval &= -+ ~((1 << RG_DP_BBPLL_PD_SFT) | -+ (1 << RG_DP_BBPLL_SDM_EDGE_SFT)); -+ SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval); -+ mdelay(10); -+ } -+ if (ret == 0) -+ ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_phy_tbl); -+ if (ret == 0) -+ ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xEAAAAAAA); -+ SMAC_REG_READ(sh, ADR_TRX_DUMMY_REGISTER, ®val); -+ if (regval != 0xEAAAAAAA) { -+ dev_warn(sh->sc->dev, "Unexpected register value\n"); -+ WARN_ON(1); -+ } -+ if (ret == 0) -+ ret = SMAC_REG_WRITE(sh, ADR_PAD53, 0x21); -+ if (ret == 0) -+ ret = SMAC_REG_WRITE(sh, ADR_PAD54, 0x3000); -+ if (ret == 0) -+ ret = SMAC_REG_WRITE(sh, ADR_PIN_SEL_0, 0x4000); -+ if (ret == 0) -+ ret = SMAC_REG_WRITE(sh, 0xc0000304, 0x01); -+ if (ret == 0) -+ ret = SMAC_REG_WRITE(sh, 0xc0000308, 0x01); -+ if (ret == 0) -+ ret = SMAC_REG_WRITE(sh, ADR_CLOCK_SELECTION, 0x3); -+ if (ret == 0) -+ ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xAAAAAAAA); -+ if ((ret = ssv6xxx_set_channel(sh->sc, sh->cfg.def_chan))) -+ return ret; -+ if (ret == 0) -+ ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1, -+ (RG_PHYRX_MD_EN_MSK | RG_PHYTX_MD_EN_MSK | -+ RG_PHY11GN_MD_EN_MSK | RG_PHY11B_MD_EN_MSK -+ | RG_PHYRXFIFO_MD_EN_MSK | -+ RG_PHYTXFIFO_MD_EN_MSK | -+ RG_PHY11BGN_MD_EN_MSK)); -+ return ret; -+} -+ -+static void ssv6xxx_check_mac2(struct ssv_hw *sh) -+{ -+ const u8 addr_mask[6] = { 0xfd, 0xff, 0xff, 0xff, 0xff, 0xfc }; -+ u8 i; -+ bool invalid = false; -+ for (i = 0; i < 6; i++) { -+ if ((ssv_cfg.maddr[0][i] & addr_mask[i]) != -+ (ssv_cfg.maddr[1][i] & addr_mask[i])) { -+ invalid = true; -+ dev_dbg(sh->sc->dev, " i %d , mac1[i] %x, mac2[i] %x, mask %x \n", i, -+ ssv_cfg.maddr[0][i], ssv_cfg.maddr[1][i], -+ addr_mask[i]); -+ break; -+ } -+ } -+ if (invalid) { -+ memcpy(&ssv_cfg.maddr[1][0], &ssv_cfg.maddr[0][0], 6); -+ ssv_cfg.maddr[1][5] ^= 0x01; -+ if (ssv_cfg.maddr[1][5] < ssv_cfg.maddr[0][5]) { -+ u8 temp; -+ temp = ssv_cfg.maddr[0][5]; -+ ssv_cfg.maddr[0][5] = ssv_cfg.maddr[1][5]; -+ ssv_cfg.maddr[1][5] = temp; -+ sh->cfg.maddr[0][5] = ssv_cfg.maddr[0][5]; -+ } -+ dev_warn(sh->sc->dev, "MAC 2 address invalid!!\n"); -+ dev_warn(sh->sc->dev, "After modification, MAC1 %pM, MAC2 %pM\n", -+ ssv_cfg.maddr[0], ssv_cfg.maddr[1]); -+ } -+} -+ -+static int ssv6xxx_read_configuration(struct ssv_hw *sh) -+{ -+ extern u32 sdio_sr_bhvr; -+ if (is_valid_ether_addr(&ssv_cfg.maddr[0][0])) -+ memcpy(&sh->cfg.maddr[0][0], &ssv_cfg.maddr[0][0], ETH_ALEN); -+ if (is_valid_ether_addr(&ssv_cfg.maddr[1][0])) { -+ ssv6xxx_check_mac2(sh); -+ memcpy(&sh->cfg.maddr[1][0], &ssv_cfg.maddr[1][0], ETH_ALEN); -+ } -+ if (ssv_cfg.hw_caps) -+ sh->cfg.hw_caps = ssv_cfg.hw_caps; -+ else -+ sh->cfg.hw_caps = SSV6200_HW_CAP_HT | -+ SSV6200_HW_CAP_2GHZ | -+ SSV6200_HW_CAP_SECURITY | -+ SSV6200_HW_CAP_P2P | -+ SSV6200_HT_CAP_SGI_20 | -+ SSV6200_HW_CAP_AMPDU_RX | -+ SSV6200_HW_CAP_AMPDU_TX | SSV6200_HW_CAP_AP; -+ if (ssv_cfg.def_chan) -+ sh->cfg.def_chan = ssv_cfg.def_chan; -+ else -+ sh->cfg.def_chan = 6; -+ sh->cfg.use_wpa2_only = ssv_cfg.use_wpa2_only; -+ if (ssv_cfg.crystal_type == 26) -+ sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_26M; -+ else if (ssv_cfg.crystal_type == 40) -+ sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_40M; -+ else if (ssv_cfg.crystal_type == 24) -+ sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_24M; -+ else { -+ dev_warn(sh->sc->dev, "Please redefine xtal_clock(wifi.cfg)!!\n"); -+ WARN_ON(1); -+ return 1; -+ } -+ if (ssv_cfg.volt_regulator < 2) -+ sh->cfg.volt_regulator = ssv_cfg.volt_regulator; -+ else { -+ dev_warn(sh->sc->dev, "Please redefine volt_regulator(wifi.cfg)!!\n"); -+ WARN_ON(1); -+ return 1; -+ } -+ sh->cfg.wifi_tx_gain_level_gn = ssv_cfg.wifi_tx_gain_level_gn; -+ sh->cfg.wifi_tx_gain_level_b = ssv_cfg.wifi_tx_gain_level_b; -+ sh->cfg.rssi_ctl = ssv_cfg.rssi_ctl; -+ sh->cfg.sr_bhvr = ssv_cfg.sr_bhvr; -+ sdio_sr_bhvr = ssv_cfg.sr_bhvr; -+ sh->cfg.force_chip_identity = ssv_cfg.force_chip_identity; -+ strncpy(sh->cfg.firmware_path, ssv_cfg.firmware_path, -+ sizeof(sh->cfg.firmware_path) - 1); -+ strncpy(sh->cfg.flash_bin_path, ssv_cfg.flash_bin_path, -+ sizeof(sh->cfg.flash_bin_path) - 1); -+ strncpy(sh->cfg.mac_address_path, ssv_cfg.mac_address_path, -+ sizeof(sh->cfg.mac_address_path) - 1); -+ strncpy(sh->cfg.mac_output_path, ssv_cfg.mac_output_path, -+ sizeof(sh->cfg.mac_output_path) - 1); -+ sh->cfg.ignore_efuse_mac = ssv_cfg.ignore_efuse_mac; -+ sh->cfg.mac_address_mode = ssv_cfg.mac_address_mode; -+ return 0; -+} -+ -+static int ssv6xxx_read_hw_info(struct ssv_softc *sc) -+{ -+ struct ssv_hw *sh; -+ sh = kzalloc(sizeof(struct ssv_hw), GFP_KERNEL); -+ if (sh == NULL) -+ return -ENOMEM; -+ memset((void *)sh, 0, sizeof(struct ssv_hw)); -+ sc->sh = sh; -+ sh->sc = sc; -+ sh->priv = sc->dev->platform_data; -+ if (ssv6xxx_read_configuration(sh)) -+ return -ENOMEM; -+ sh->hci.dev = sc->dev; -+ sh->hci.hci_ops = NULL; -+ sh->hci.hci_rx_cb = ssv6200_rx; -+ sh->hci.rx_cb_args = (void *)sc; -+ sh->hci.hci_tx_cb = ssv6xxx_tx_cb; -+ sh->hci.tx_cb_args = (void *)sc; -+ sh->hci.hci_skb_update_cb = ssv6xxx_tx_rate_update; -+ sh->hci.skb_update_args = (void *)sc; -+ sh->hci.hci_tx_flow_ctrl_cb = ssv6200_tx_flow_control; -+ sh->hci.tx_fctrl_cb_args = (void *)sc; -+ sh->hci.hci_tx_q_empty_cb = ssv6xxx_tx_q_empty_cb; -+ sh->hci.tx_q_empty_args = (void *)sc; -+ sh->hci.if_ops = sh->priv->ops; -+ sh->hci.hci_tx_buf_free_cb = ssv6xxx_txbuf_free_skb; -+ sh->hci.tx_buf_free_args = (void *)sc; -+ return 0; -+} -+ -+static int ssv6xxx_init_device(struct ssv_softc *sc, const char *name) -+{ -+ struct ieee80211_hw *hw = sc->hw; -+ struct ssv_hw *sh; -+ int error = 0; -+ BUG_ON(!sc->dev->platform_data); -+ if ((error = ssv6xxx_read_hw_info(sc)) != 0) { -+ return error; -+ } -+ sh = sc->sh; -+ if (sh->cfg.hw_caps == 0) -+ return -1; -+ ssv6xxx_hci_register(&sh->hci); -+ efuse_read_all_map(sh); -+ if ((error = ssv6xxx_init_softc(sc)) != 0) { -+ ssv6xxx_deinit_softc(sc); -+ ssv6xxx_hci_deregister(); -+ kfree(sh); -+ return error; -+ } -+ if ((error = ssv6xxx_init_hw(sc->sh)) != 0) { -+ ssv6xxx_deinit_hw(sc); -+ ssv6xxx_deinit_softc(sc); -+ ssv6xxx_hci_deregister(); -+ kfree(sh); -+ return error; -+ } -+ if ((error = ieee80211_register_hw(hw)) != 0) { -+ dev_err(sc->dev, "Failed to register ieee80211 wireless device. ret=%d.\n", error); -+ ssv6xxx_deinit_hw(sc); -+ ssv6xxx_deinit_softc(sc); -+ ssv6xxx_hci_deregister(); -+ kfree(sh); -+ return error; -+ } -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ ssv6xxx_init_debugfs(sc, name); -+#endif -+ return 0; -+} -+ -+static void ssv6xxx_deinit_device(struct ssv_softc *sc) -+{ -+ dev_dbg(sc->dev, "%s(): \n", __FUNCTION__); -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ ssv6xxx_deinit_debugfs(sc); -+#endif -+ ssv6xxx_rf_disable(sc->sh); -+ ieee80211_unregister_hw(sc->hw); -+ ssv6xxx_deinit_hw(sc); -+ ssv6xxx_deinit_softc(sc); -+ ssv6xxx_hci_deregister(); -+ kfree(sc->sh); -+} -+ -+extern struct ieee80211_ops ssv6200_ops; -+int ssv6xxx_dev_probe(struct platform_device *pdev) -+{ -+#ifdef CONFIG_SSV6200_CLI_ENABLE -+ extern struct ssv_softc *ssv_dbg_sc; -+#endif -+#ifdef CONFIG_SSV_SMARTLINK -+ extern struct ssv_softc *ssv_smartlink_sc; -+#endif -+ struct ssv_softc *softc; -+ struct ieee80211_hw *hw; -+ int ret; -+ if (!pdev->dev.platform_data) { -+ dev_err(&pdev->dev, "no platform data specified!\n"); -+ return -EINVAL; -+ } -+ hw = ieee80211_alloc_hw(sizeof(struct ssv_softc), &ssv6200_ops); -+ if (hw == NULL) { -+ dev_err(&pdev->dev, "Could not allocate memory for ieee80211 wireless device\n"); -+ return -ENOMEM; -+ } -+ SET_IEEE80211_DEV(hw, &pdev->dev); -+ dev_set_drvdata(&pdev->dev, hw); -+ memset((void *)hw->priv, 0, sizeof(struct ssv_softc)); -+ softc = hw->priv; -+ softc->hw = hw; -+ softc->dev = &pdev->dev; -+ //SET_IEEE80211_PERM_ADDR(hw, (const u8 *)&softc->sh->maddr[0]); -+ ret = ssv6xxx_init_device(softc, pdev->name); -+ if (ret) { -+ dev_err(&pdev->dev, "Failed to initialize device\n"); -+ ieee80211_free_hw(hw); -+ return ret; -+ } -+#ifdef CONFIG_SSV6200_CLI_ENABLE -+ ssv_dbg_sc = softc; -+#endif -+#ifdef CONFIG_SSV_SMARTLINK -+ ssv_smartlink_sc = softc; -+#endif -+ wiphy_info(hw->wiphy, "%s\n", "SSV6200 of South Silicon Valley"); -+ return 0; -+} -+ -+EXPORT_SYMBOL(ssv6xxx_dev_probe); -+void ssv6xxx_dev_remove(struct platform_device *pdev) -+{ -+ struct ieee80211_hw *hw = dev_get_drvdata(&pdev->dev); -+ struct ssv_softc *softc = hw->priv; -+ dev_dbg(&pdev->dev, "ssv6xxx_dev_remove(): pdev=%p, hw=%p\n", pdev, hw); -+ ssv6xxx_deinit_device(softc); -+ dev_dbg(&pdev->dev, "ieee80211_free_hw(): \n"); -+ ieee80211_free_hw(hw); -+ dev_info(&pdev->dev, "driver unloaded\n"); -+ return; -+} -+ -+EXPORT_SYMBOL(ssv6xxx_dev_remove); -+static const struct platform_device_id ssv6xxx_id_table[] = { -+ { -+ .name = "ssv6200", -+ .driver_data = 0x00, -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(platform, ssv6xxx_id_table); -+static struct platform_driver ssv6xxx_driver = { -+ .probe = ssv6xxx_dev_probe, -+ .remove = ssv6xxx_dev_remove, -+ .id_table = ssv6xxx_id_table, -+ .driver = { -+ .name = "SSV WLAN driver", -+ .owner = THIS_MODULE, -+ } -+}; -+ -+int ssv6xxx_init(void) -+{ -+ extern void *ssv_dbg_phy_table; -+ extern u32 ssv_dbg_phy_len; -+ extern void *ssv_dbg_rf_table; -+ extern u32 ssv_dbg_rf_len; -+ ssv_dbg_phy_table = (void *)ssv6200_phy_tbl; -+ ssv_dbg_phy_len = -+ sizeof(ssv6200_phy_tbl) / sizeof(struct ssv6xxx_dev_table); -+ ssv_dbg_rf_table = (void *)ssv6200_rf_tbl; -+ ssv_dbg_rf_len = -+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table); -+ return platform_driver_register(&ssv6xxx_driver); -+} -+ -+void ssv6xxx_exit(void) -+{ -+ platform_driver_unregister(&ssv6xxx_driver); -+} -+ -+EXPORT_SYMBOL(ssv6xxx_init); -+EXPORT_SYMBOL(ssv6xxx_exit); -diff --git a/drivers/net/wireless/ssv6051/smac/init.h b/drivers/net/wireless/ssv6051/smac/init.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/init.h -@@ -0,0 +1,23 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _INIT_H_ -+#define _INIT_H_ -+int ssv6xxx_init_mac(struct ssv_hw *sh); -+int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg); -+void ssv6xxx_deinit_mac(struct ssv_softc *sc); -+void ssv6xxx_restart_hw(struct ssv_softc *sc); -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/lib.c b/drivers/net/wireless/ssv6051/smac/lib.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/lib.c -@@ -0,0 +1,33 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include "lib.h" -+struct sk_buff *ssv_skb_alloc(s32 len) -+{ -+ struct sk_buff *skb; -+ skb = __dev_alloc_skb(len + 128, GFP_KERNEL); -+ if (skb != NULL) { -+ skb_put(skb, 0x20); -+ skb_pull(skb, 0x20); -+ } -+ return skb; -+} -+ -+void ssv_skb_free(struct sk_buff *skb) -+{ -+ dev_kfree_skb_any(skb); -+} -diff --git a/drivers/net/wireless/ssv6051/smac/lib.h b/drivers/net/wireless/ssv6051/smac/lib.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/lib.h -@@ -0,0 +1,23 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _LIB_H_ -+#define _LIB_H_ -+#include -+#include -+struct sk_buff *ssv_skb_alloc(s32 len); -+void ssv_skb_free(struct sk_buff *skb); -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/linux_80211.h b/drivers/net/wireless/ssv6051/smac/linux_80211.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/linux_80211.h -@@ -0,0 +1,24 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _LINUX_80211_H_ -+#define _LINUX_80211_H_ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) -+#define INDEX_80211_BAND_2GHZ IEEE80211_BAND_2GHZ -+#else -+#define INDEX_80211_BAND_2GHZ NL80211_BAND_2GHZ -+#endif -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/p2p.c b/drivers/net/wireless/ssv6051/smac/p2p.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/p2p.c -@@ -0,0 +1,305 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "p2p.h" -+#include "dev.h" -+#include "lib.h" -+#ifdef CONFIG_P2P_NOA -+#define P2P_IE_VENDOR_TYPE 0x506f9a09 -+#define P2P_NOA_DETECT_INTERVAL (5 * HZ) -+#ifndef MAC2STR -+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] -+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" -+#define COMPACT_MACSTR "%02x%02x%02x%02x%02x%02x" -+#endif -+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc, -+ struct ssv6xxx_p2p_noa_param *p2p_noa_param); -+static inline u32 WPA_GET_BE32(const u8 * a) -+{ -+ return (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]; -+} -+ -+static inline u16 WPA_GET_LE16(const u8 * a) -+{ -+ return (a[1] << 8) | a[0]; -+} -+ -+static inline u32 WPA_GET_LE32(const u8 * a) -+{ -+ return (a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]; -+} -+ -+#define IEEE80211_HDRLEN 24 -+enum p2p_attr_id { -+ P2P_ATTR_STATUS = 0, -+ P2P_ATTR_MINOR_REASON_CODE = 1, -+ P2P_ATTR_CAPABILITY = 2, -+ P2P_ATTR_DEVICE_ID = 3, -+ P2P_ATTR_GROUP_OWNER_INTENT = 4, -+ P2P_ATTR_CONFIGURATION_TIMEOUT = 5, -+ P2P_ATTR_LISTEN_CHANNEL = 6, -+ P2P_ATTR_GROUP_BSSID = 7, -+ P2P_ATTR_EXT_LISTEN_TIMING = 8, -+ P2P_ATTR_INTENDED_INTERFACE_ADDR = 9, -+ P2P_ATTR_MANAGEABILITY = 10, -+ P2P_ATTR_CHANNEL_LIST = 11, -+ P2P_ATTR_NOTICE_OF_ABSENCE = 12, -+ P2P_ATTR_DEVICE_INFO = 13, -+ P2P_ATTR_GROUP_INFO = 14, -+ P2P_ATTR_GROUP_ID = 15, -+ P2P_ATTR_INTERFACE = 16, -+ P2P_ATTR_OPERATING_CHANNEL = 17, -+ P2P_ATTR_INVITATION_FLAGS = 18, -+ P2P_ATTR_OOB_GO_NEG_CHANNEL = 19, -+ P2P_ATTR_VENDOR_SPECIFIC = 221 -+}; -+struct ssv6xxx_p2p_noa_attribute { -+ u8 index; -+ u16 ctwindows_oppps; -+ struct ssv6xxx_p2p_noa_param noa_param; -+}; -+extern void _ssv6xxx_hexdump(const char *title, const u8 * buf, size_t len); -+bool p2p_find_noa(const u8 * ies, struct ssv6xxx_p2p_noa_attribute *noa_attr) -+{ -+ const u8 *end, *pos, *ie; -+ u32 len; -+ len = ie[1] - 4; -+ pos = ie + 6; -+ end = pos + len; -+ while (pos < end) { -+ u16 attr_len; -+ if (pos + 2 >= end) { -+ return false; -+ } -+ attr_len = WPA_GET_LE16(pos + 1); -+ if (pos + 3 + attr_len > end) { -+ return false; -+ } -+ if (pos[0] != P2P_ATTR_NOTICE_OF_ABSENCE) { -+ pos += 3 + attr_len; -+ continue; -+ } -+ if (attr_len < 15) { -+ printk -+ ("*********************NOA descriptor does not exist len[%d]\n", -+ attr_len); -+ break; -+ } -+ if (attr_len > 15) -+ printk("More than one NOA descriptor\n"); -+ noa_attr->index = pos[3]; -+ noa_attr->ctwindows_oppps = pos[4]; -+ noa_attr->noa_param.count = pos[5]; -+ noa_attr->noa_param.duration = WPA_GET_LE32(&pos[6]); -+ noa_attr->noa_param.interval = WPA_GET_LE32(&pos[10]); -+ noa_attr->noa_param.start_time = WPA_GET_LE32(&pos[14]); -+ return true; -+ } -+ return false; -+} -+ -+bool p2p_get_attribute_noa(const u8 * ies, u32 oui_type, -+ struct ssv6xxx_p2p_noa_attribute *noa_attr) -+{ -+ const u8 *end, *pos, *ie; -+ u32 len; -+ pos = ies; -+ end = ies + ies_len; -+ ie = NULL; -+ while (pos + 1 < end) { -+ if (pos + 2 + pos[1] > end) -+ return false; -+ if (pos[0] == WLAN_EID_VENDOR_SPECIFIC && pos[1] >= 4 && -+ WPA_GET_BE32(&pos[2]) == oui_type) { -+ ie = pos; -+ if (p2p_find_noa(ie, 0, noa_attr) == true) -+ return true; -+ } -+ pos += 2 + pos[1]; -+ } -+ return false; -+} -+ -+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb) -+{ -+ struct cfg_host_event *host_event; -+ struct ssv62xx_noa_evt *noa_evt; -+ host_event = (struct cfg_host_event *)skb->data; -+ noa_evt = (struct ssv62xx_noa_evt *)&host_event->dat[0]; -+ switch (noa_evt->evt_id) { -+ case SSV6XXX_NOA_START: -+ sc->p2p_noa.active_noa_vif |= (1 << noa_evt->vif); -+ printk("SSV6XXX_NOA_START===>[%08x]\n", -+ sc->p2p_noa.active_noa_vif); -+ break; -+ case SSV6XXX_NOA_STOP: -+ sc->p2p_noa.active_noa_vif &= ~(1 << noa_evt->vif); -+ printk("SSV6XXX_NOA_STOP===>[%08x]\n", -+ sc->p2p_noa.active_noa_vif); -+ break; -+ default: -+ printk("--------->NOA wrong command<---------\n"); -+ break; -+ } -+} -+ -+void ssv6xxx_noa_reset(struct ssv_softc *sc) -+{ -+ unsigned long flags; -+ printk("Reset NOA param...\n"); -+ spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags); -+ memset(&sc->p2p_noa.noa_detect, 0, -+ sizeof(struct ssv_p2p_noa_detect) * SSV_NUM_VIF); -+ sc->p2p_noa.active_noa_vif = 0; -+ sc->p2p_noa.monitor_noa_vif = 0; -+ spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags); -+} -+ -+void ssv6xxx_noa_host_stop_noa(struct ssv_softc *sc, u8 vif_id) -+{ -+ struct ssv6xxx_p2p_noa_attribute noa_attr; -+ if (sc->p2p_noa.noa_detect[vif_id].p2p_noa_index >= 0) { -+ sc->p2p_noa.noa_detect[vif_id].p2p_noa_index = -1; -+ sc->p2p_noa.active_noa_vif &= ~(1 << vif_id); -+ memset(&sc->p2p_noa.noa_detect[vif_id].noa_param_cmd, 0, -+ sizeof(struct ssv6xxx_p2p_noa_param)); -+ printk("->remove NOA operating vif[%d]\n", vif_id); -+ noa_attr.noa_param.enable = 0; -+ noa_attr.noa_param.vif_id = vif_id; -+ ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param); -+ } -+} -+ -+void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr, -+ u32 len) -+{ -+ int i; -+ unsigned long flags; -+ struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; -+ struct ssv6xxx_p2p_noa_attribute noa_attr; -+ spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags); -+ if (sc->p2p_noa.monitor_noa_vif == 0) -+ goto out; -+ for (i = 0; i < SSV_NUM_VIF; i++) { -+ if (sc->p2p_noa.noa_detect[i].noa_addr == NULL) -+ continue; -+ if (memcmp(mgmt->bssid, sc->p2p_noa.noa_detect[i].noa_addr, 6) -+ != 0) -+ continue; -+ if (sc->p2p_noa.active_noa_vif && -+ ((sc->p2p_noa.active_noa_vif & 1 << i) == 0)) -+ continue; -+ sc->p2p_noa.noa_detect[i].last_rx = jiffies; -+ if (p2p_get_attribute_noa((const u8 *)mgmt->u.beacon.variable, -+ len - (IEEE80211_HDRLEN + -+ sizeof(mgmt->u.beacon)), -+ P2P_IE_VENDOR_TYPE, -+ &noa_attr) == false) { -+ continue; -+ } -+ if (sc->p2p_noa.noa_detect[i].p2p_noa_index == noa_attr.index) { -+ goto out; -+ } -+ printk(MACSTR "->set NOA element\n", MAC2STR(mgmt->bssid)); -+ sc->p2p_noa.active_noa_vif |= (1 << i); -+ sc->p2p_noa.noa_detect[i].p2p_noa_index = noa_attr.index; -+ memcpy(&sc->p2p_noa.noa_detect[i].noa_param_cmd, -+ &noa_attr.noa_param, -+ sizeof(struct ssv6xxx_p2p_noa_param)); -+ noa_attr.noa_param.enable = 1; -+ noa_attr.noa_param.vif_id = i; -+ memcpy(noa_attr.noa_param.addr, hdr->addr2, 6); -+ ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param); -+ } -+ out: -+ spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags); -+} -+ -+void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc, -+ enum ssv6xxx_noa_conf conf, u8 vif_idx) -+{ -+ unsigned long flags; -+ if (sc->vif_info[vif_idx].vif->type != NL80211_IFTYPE_STATION || -+ sc->vif_info[vif_idx].vif->p2p != true) -+ return; -+ spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags); -+ printk("====>[NOA]ssv6xxx_noa_hdl_bss_change conf[%d] vif_idx[%d]\n", -+ conf, vif_idx); -+ switch (conf) { -+ case MONITOR_NOA_CONF_ADD: -+ memset(&sc->p2p_noa.noa_detect[vif_idx], 0, -+ sizeof(struct ssv_p2p_noa_detect)); -+ sc->p2p_noa.noa_detect[vif_idx].noa_addr = -+ sc->vif_info[vif_idx].vif->bss_conf.bssid; -+ sc->p2p_noa.noa_detect[vif_idx].p2p_noa_index = -1; -+ sc->p2p_noa.noa_detect[vif_idx].last_rx = jiffies; -+ sc->p2p_noa.monitor_noa_vif |= 1 << vif_idx; -+ break; -+ case MONITOR_NOA_CONF_REMOVE: -+ sc->p2p_noa.monitor_noa_vif &= ~(1 << vif_idx); -+ sc->p2p_noa.noa_detect[vif_idx].noa_addr = NULL; -+ ssv6xxx_noa_host_stop_noa(sc, vif_idx); -+ break; -+ default: -+ break; -+ } -+ spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags); -+} -+ -+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc, -+ struct ssv6xxx_p2p_noa_param *p2p_noa_param) -+{ -+ struct sk_buff *skb; -+ struct cfg_host_cmd *host_cmd; -+ int retry_cnt = 5; -+ skb = -+ ssv_skb_alloc(HOST_CMD_HDR_LEN + -+ sizeof(struct ssv6xxx_p2p_noa_param)); -+ skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param); -+ skb->len = skb->data_len; -+ host_cmd = (struct cfg_host_cmd *)skb->data; -+ host_cmd->c_type = HOST_CMD; -+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA; -+ host_cmd->len = skb->data_len; -+ memcpy(host_cmd->dat32, p2p_noa_param, -+ sizeof(struct ssv6xxx_p2p_noa_param)); -+ printk -+ ("Noa cmd NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]vif[%d]\n\n", -+ p2p_noa_param->enable, p2p_noa_param->interval, -+ p2p_noa_param->duration, p2p_noa_param->start_time, -+ p2p_noa_param->count, p2p_noa_param->addr[0], -+ p2p_noa_param->addr[1], p2p_noa_param->addr[2], -+ p2p_noa_param->addr[3], p2p_noa_param->addr[4], -+ p2p_noa_param->addr[5], p2p_noa_param->vif_id); -+ while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) { -+ printk(KERN_INFO "NOA cmd retry=%d!!\n", retry_cnt); -+ retry_cnt--; -+ } -+ ssv_skb_free(skb); -+} -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/p2p.h b/drivers/net/wireless/ssv6051/smac/p2p.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/p2p.h -@@ -0,0 +1,58 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _P2P_H_ -+#define _P2P_H_ -+#include -+#include -+#include "drv_comm.h" -+#ifdef CONFIG_P2P_NOA -+#define P2P_MAX_NOA_INTERFACE 1 -+struct ssv_p2p_noa_detect { -+ const u8 *noa_addr; -+ s16 p2p_noa_index; -+ unsigned long last_rx; -+ struct ssv6xxx_p2p_noa_param noa_param_cmd; -+}; -+struct ssv_p2p_noa { -+ spinlock_t p2p_config_lock; -+ struct ssv_p2p_noa_detect noa_detect[SSV_NUM_VIF]; -+ u8 active_noa_vif; -+ u8 monitor_noa_vif; -+}; -+enum ssv_cmd_state { -+ SSC_CMD_STATE_IDLE, -+ SSC_CMD_STATE_WAIT_RSP, -+}; -+struct ssv_cmd_Info { -+ struct sk_buff_head cmd_que; -+ struct sk_buff_head evt_que; -+ enum ssv_cmd_state state; -+}; -+enum ssv6xxx_noa_conf { -+ MONITOR_NOA_CONF_ADD, -+ MONITOR_NOA_CONF_REMOVE, -+}; -+struct ssv_softc; -+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb); -+void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc, -+ enum ssv6xxx_noa_conf conf, u8 vif_idx); -+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb); -+void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr, -+ u32 len); -+void ssv6xxx_noa_reset(struct ssv_softc *sc); -+#endif -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/sar.c b/drivers/net/wireless/ssv6051/smac/sar.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/sar.c -@@ -0,0 +1,208 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include "dev.h" -+#include "sar.h" -+ -+WIFI_FLASH_CCFG flash_cfg = { -+ //16bytes -+ 0x6051, 0x3009, 0x20170519, 0x1, 0x0, 0x0, -+ { //16bytes -+ {0x47c000, 0x47c000, 0x47c000, 0x9, 0x1d, 0x0}, -+ //16bytes -+ {0x79807980, 0x79807980, 0x79807980, 0x9, 0x1d, 0x0} -+ } -+}; -+ -+WIFI_FLASH_CCFG *pflash_cfg; -+ -+struct t_sar_info sar_info[] = { -+ {SAR_LVL_INVALID, 0x0047c000, NULL}, -+ {SAR_LVL_INVALID, 0x79807980, NULL} -+}; -+ -+int sar_info_size = sizeof(sar_info) / sizeof(sar_info[0]); -+ -+static u8 get_sar_lvl(u32 sar) -+{ -+ static u32 prev_sar = 0; -+ int i; -+ u8 changed = 0x0; -+ -+ if (sar == prev_sar) -+ return changed; -+ -+ pr_debug("[thermal_sar] %d\n", (int)sar); -+ -+ for (i = 0; i < sar_info_size; i++) { -+ if (sar_info[i].lvl == SAR_LVL_INVALID) { //if driver loaded under LT/HT env, it would cause wrong settings at this time. -+ sar_info[i].lvl = SAR_LVL_RT; -+ sar_info[i].value = sar_info[i].p->rt; -+ changed |= BIT(i); -+ } else if (sar_info[i].lvl == SAR_LVL_RT) { -+ if (sar < prev_sar) { -+ if (sar <= (u32) (sar_info[i].p->lt_ts - 2)) { //we need check if (g_tt_lt - 1) < SAR_MIN -+ sar_info[i].lvl = SAR_LVL_LT; -+ sar_info[i].value = sar_info[i].p->lt; -+ changed |= BIT(i); -+ } -+ } else if (sar > prev_sar) { -+ if (sar >= (u32) (sar_info[i].p->ht_ts + 2)) { //we need check if (g_tt_lt + 1) > SAR_MAX -+ sar_info[i].lvl = SAR_LVL_HT; -+ sar_info[i].value = sar_info[i].p->ht; -+ changed |= BIT(i); -+ } -+ } -+ } else if (sar_info[i].lvl == SAR_LVL_LT) { -+ if (sar >= (u32) (sar_info[i].p->lt_ts + 2)) { -+ sar_info[i].lvl = SAR_LVL_RT; -+ sar_info[i].value = sar_info[i].p->rt; -+ changed |= BIT(i); -+ } -+ } else if (sar_info[i].lvl == SAR_LVL_HT) { -+ if (sar <= (u32) (sar_info[i].p->ht_ts - 2)) { -+ sar_info[i].lvl = SAR_LVL_RT; -+ sar_info[i].value = sar_info[i].p->rt; -+ changed |= BIT(i); -+ } -+ } -+ } -+ if (changed) { -+ pr_debug("changed: 0x%x\n", changed); -+ } -+ prev_sar = sar; -+ return changed; -+} -+ -+void sar_monitor(u32 curr_sar, struct ssv_softc *sc) -+{ -+ //static u32 prev_sar_lvl = SAR_LVL_INVALID; //sar = 0, temparature < -25C -+ u8 changed; -+ changed = get_sar_lvl(curr_sar); -+ -+ if (changed & BIT(SAR_TXGAIN_INDEX)) { -+ dev_dbg(sc->dev, "TXGAIN: 0x%08x\n", sar_info[SAR_TXGAIN_INDEX].value); -+ SMAC_REG_WRITE(sc->sh, ADR_TX_GAIN_FACTOR, -+ sar_info[SAR_TXGAIN_INDEX].value); -+ } -+ if (changed & BIT(SAR_XTAL_INDEX)) { -+ dev_dbg(sc->dev, "XTAL: 0x%08x\n", sar_info[SAR_XTAL_INDEX].value); -+ SMAC_REG_WRITE(sc->sh, ADR_SYN_KVCO_XO_FINE_TUNE_CBANK, -+ sar_info[SAR_XTAL_INDEX].value); -+ } -+} -+ -+/* -+ SET_RG_SARADC_THERMAL(1); //ce010030[26] -+ SET_RG_EN_SARADC(1); //ce010030[30] -+ while(!GET_SAR_ADC_FSM_RDY); //ce010094[23] -+ sar_code = GET_RG_SARADC_BIT; //ce010094[21:16] -+ SET_RG_SARADC_THERMAL(0); -+ SET_RG_EN_SARADC(0); -+*/ -+void thermal_monitor(struct work_struct *work) -+{ -+ struct ssv_softc *sc = -+ container_of(work, struct ssv_softc, thermal_monitor_work.work); -+ u32 curr_sar; -+ -+ u32 temp; -+ if (sc->ps_status == PWRSV_PREPARE) { -+ dev_dbg(sc->dev, "sar PWRSV_PREPARE\n"); -+ return; -+ } -+ -+ mutex_lock(&sc->mutex); -+ SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_1, &temp); -+ if (temp == RX_11B_CCA_IN_SCAN) { -+ dev_dbg(sc->dev, "in scan\n"); -+ mutex_unlock(&sc->mutex); -+ queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work, -+ THERMAL_MONITOR_TIME); -+ return; -+ } -+ SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp); -+ //printk("ori %08x:%08x\n", ADR_RX_ADC_REGISTER, temp); -+ SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, -+ (1 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK); -+ SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (1 << RG_EN_SARADC_SFT), -+ RG_EN_SARADC_MSK); -+ -+ do { -+ msleep(1); -+ SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1, &temp); -+ } while (((temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT) != 1); -+ //printk("SAR_ADC_FSM_RDY_STAT %d\n", (temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT); -+ curr_sar = (temp & RG_SARADC_BIT_MSK) >> RG_SARADC_BIT_SFT; -+ SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp); -+ -+ //printk("new %08x:%08x\n", ADR_RX_ADC_REGISTER, temp); -+ -+ SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, -+ (0 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK); -+ SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (0 << RG_EN_SARADC_SFT), -+ RG_EN_SARADC_MSK); -+ sar_monitor(curr_sar, sc); -+ -+ mutex_unlock(&sc->mutex); -+ -+ queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work, -+ THERMAL_MONITOR_TIME); -+} -+ -+int get_flash_info(struct ssv_softc *sc) -+{ -+ struct file *fp = (struct file *)NULL; -+ int i, ret; -+ -+ pflash_cfg = &flash_cfg; -+ -+ if (sc->sh->cfg.flash_bin_path[0] != 0x00) { -+ fp = filp_open(sc->sh->cfg.flash_bin_path, O_RDONLY, 0); -+ if (IS_ERR(fp) || fp == NULL) { -+ fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0); -+ } -+ } else { -+ fp = filp_open(DEFAULT_CFG_BIN_NAME, O_RDONLY, 0); -+ if (IS_ERR(fp) || fp == NULL) { -+ fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0); -+ } -+ } -+ if (IS_ERR(fp) || fp == NULL) { -+ dev_info(sc->dev, "flash_file %s not found, disable sar\n", -+ DEFAULT_CFG_BIN_NAME); -+ //WARN_ON(1); -+ ret = 0; -+ return ret; -+ } -+ -+ fp->f_op->read(fp, (char *)pflash_cfg, sizeof(flash_cfg), &fp->f_pos); -+ -+ filp_close(fp, NULL); -+ ret = 1; -+ -+ for (i = 0; i < sar_info_size; i++) { -+ sar_info[i].p = &flash_cfg.sar_rlh[i]; -+ dev_dbg(sc->dev, "rt = %x, lt = %x, ht = %x\n", sar_info[i].p->rt, -+ sar_info[i].p->lt, sar_info[i].p->ht); -+ dev_dbg(sc->dev, "lt_ts = %x, ht_ts = %x\n", sar_info[i].p->lt_ts, -+ sar_info[i].p->ht_ts); -+ } -+ return ret; -+} -diff --git a/drivers/net/wireless/ssv6051/smac/sar.h b/drivers/net/wireless/ssv6051/smac/sar.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/sar.h -@@ -0,0 +1,63 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _CFG_H_ -+#define _CFG_H_ -+#include -+ -+#define SAR_XTAL_INDEX (0) -+#define SAR_TXGAIN_INDEX (1) -+#define THERMAL_MONITOR_TIME (10 * HZ) -+#define DEFAULT_CFG_BIN_NAME "/lib/firmware/ssv6051_sar.bin" -+#define SEC_CFG_BIN_NAME "/lib/firmware/ssv6xxx_sar.bin" -+enum { -+ SAR_LVL_LT, -+ SAR_LVL_RT, -+ SAR_LVL_HT, -+ SAR_LVL_INVALID -+}; -+ -+struct flash_thermal_info { -+ u32 rt; -+ u32 lt; -+ u32 ht; -+ u8 lt_ts; -+ u8 ht_ts; -+ u16 reserve; -+}; -+typedef struct t_WIFI_FLASH_CCFG { -+ //16bytes -+ u16 chip_id; -+ u16 sid; -+ u32 date; -+ u16 version; -+ u16 reserve_1; -+ u32 reserve_2; -+ //16bytes -+ struct flash_thermal_info sar_rlh[2]; -+} WIFI_FLASH_CCFG; -+ -+struct t_sar_info { -+ u32 lvl; -+ u32 value; -+ struct flash_thermal_info *p; -+}; -+ -+void thermal_monitor(struct work_struct *work); -+int get_flash_info(struct ssv_softc *sc); -+void flash_hexdump(void); -+ -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/sec.h b/drivers/net/wireless/ssv6051/smac/sec.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/sec.h -@@ -0,0 +1,52 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef SEC_H -+#define SEC_H -+#include -+#include -+#include -+#define CCMP_TK_LEN 16 -+#define TKIP_KEY_LEN 32 -+#define WEP_KEY_LEN 13 -+struct ssv_crypto_ops { -+ const char *name; -+ struct list_head list; -+ void *(*init)(int keyidx); -+ void (*deinit)(void *priv); -+ int (*encrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv); -+ int (*decrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv); -+ int (*encrypt_msdu)(struct sk_buff * skb, int hdr_len, void *priv); -+ int (*decrypt_msdu)(struct sk_buff * skb, int keyidx, int hdr_len, -+ void *priv); -+ int (*set_tx_pn)(u8 * seq, void *priv); -+ int (*set_key)(void *key, int len, u8 * seq, void *priv); -+ int (*get_key)(void *key, int len, u8 * seq, void *priv); -+ char *(*print_stats)(char *p, void *priv); -+ unsigned long (*get_flags)(void *priv); -+ unsigned long (*set_flags)(unsigned long flags, void *priv); -+ int extra_mpdu_prefix_len, extra_mpdu_postfix_len; -+ int extra_msdu_prefix_len, extra_msdu_postfix_len; -+}; -+struct ssv_crypto_data { -+ struct ssv_crypto_ops *ops; -+ void *priv; -+ rwlock_t lock; -+}; -+struct ssv_crypto_ops *get_crypto_ccmp_ops(void); -+struct ssv_crypto_ops *get_crypto_tkip_ops(void); -+struct ssv_crypto_ops *get_crypto_wep_ops(void); -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/smartlink.c b/drivers/net/wireless/ssv6051/smac/smartlink.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/smartlink.c -@@ -0,0 +1,340 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "lib.h" -+#include "dev.h" -+#define NETLINK_SMARTLINK (31) -+#define MAX_PAYLOAD (2048) -+static struct sock *nl_sk = NULL; -+struct ssv_softc *ssv_smartlink_sc = NULL; -+EXPORT_SYMBOL(ssv_smartlink_sc); -+u32 ssv_smartlink_status = 0; -+static int _ksmartlink_start_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf, -+ u32 * pOutBufLen) -+{ -+#ifdef KSMARTLINK_DEBUG -+ printk(KERN_INFO "%s\n", __FUNCTION__); -+#endif -+ ssv_smartlink_status = 1; -+ *pOutBufLen = 0; -+ return 0; -+} -+ -+int ksmartlink_smartlink_started(void) -+{ -+ return ssv_smartlink_status; -+} -+ -+EXPORT_SYMBOL(ksmartlink_smartlink_started); -+static int _ksmartlink_stop_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf, -+ u32 * pOutBufLen) -+{ -+#ifdef KSMARTLINK_DEBUG -+ printk(KERN_INFO "%s\n", __FUNCTION__); -+#endif -+ ssv_smartlink_status = 0; -+ *pOutBufLen = 0; -+ return 0; -+} -+ -+static int _ksmartlink_set_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf, -+ u32 * pOutBufLen) -+{ -+ int ret = -10; -+ int ch = (int)(*pInBuf); -+ struct ssv_softc *sc = ssv_smartlink_sc; -+#ifdef KSMARTLINK_DEBUG -+ printk(KERN_INFO "%s %d\n", __FUNCTION__, ch); -+#endif -+ if (!sc) { -+ goto out; -+ } -+ mutex_lock(&sc->mutex); -+ ret = ssv6xxx_set_channel(sc, ch); -+ mutex_unlock(&sc->mutex); -+ *pOutBufLen = 0; -+ out: -+ return ret; -+} -+ -+static int _ksmartlink_get_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf, -+ u32 * pOutBufLen) -+{ -+ int ret = -10; -+ int ch = 0; -+ struct ssv_softc *sc = ssv_smartlink_sc; -+#ifdef KSMARTLINK_DEBUG -+ printk(KERN_INFO "%s\n", __FUNCTION__); -+#endif -+ if (!sc) { -+ goto out; -+ } -+ mutex_lock(&sc->mutex); -+ ret = ssv6xxx_get_channel(sc, &ch); -+ mutex_unlock(&sc->mutex); -+ *pOutBuf = ch; -+ *pOutBufLen = 1; -+#ifdef KSMARTLINK_DEBUG -+ printk(KERN_INFO "%s %d\n", __FUNCTION__, ch); -+#endif -+ out: -+ return ret; -+} -+ -+static int _ksmartlink_set_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf, -+ u32 * pOutBufLen) -+{ -+ int ret = -10; -+ int accept = (int)(*pInBuf); -+ struct ssv_softc *sc = ssv_smartlink_sc; -+#ifdef KSMARTLINK_DEBUG -+ printk(KERN_INFO "%s %d\n", __FUNCTION__, accept); -+#endif -+ if (!sc) { -+ goto out; -+ } -+ mutex_lock(&sc->mutex); -+ ret = ssv6xxx_set_promisc(sc, accept); -+ mutex_unlock(&sc->mutex); -+ *pOutBufLen = 0; -+ out: -+ return ret; -+} -+ -+static int _ksmartlink_get_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf, -+ u32 * pOutBufLen) -+{ -+ int ret = -10; -+ int accept = (int)(*pInBuf); -+ struct ssv_softc *sc = ssv_smartlink_sc; -+#ifdef KSMARTLINK_DEBUG -+ printk(KERN_INFO "%s\n", __FUNCTION__); -+#endif -+ if (!sc) { -+ goto out; -+ } -+ mutex_lock(&sc->mutex); -+ ret = ssv6xxx_get_promisc(sc, &accept); -+ mutex_unlock(&sc->mutex); -+ *pOutBuf = accept; -+ *pOutBufLen = 1; -+#ifdef KSMARTLINK_DEBUG -+ printk(KERN_INFO "%s %d\n", __FUNCTION__, accept); -+#endif -+ out: -+ return ret; -+} -+ -+#define SMARTLINK_CMD_FIXED_LEN (10) -+#define SMARTLINK_CMD_FIXED_TOT_LEN (SMARTLINK_CMD_FIXED_LEN+1) -+#define SMARTLINK_RES_FIXED_LEN (SMARTLINK_CMD_FIXED_LEN) -+#define SMARTLINK_RES_FIXED_TOT_LEN (SMARTLINK_RES_FIXED_LEN+2) -+struct ksmartlink_cmd { -+ char *cmd; -+ int (*process_func)(u8 *, u32, u8 *, u32 *); -+}; -+static struct ksmartlink_cmd _ksmartlink_cmd_table[] = { -+ {"startairki", _ksmartlink_start_smartlink}, -+ {"stopairkis", _ksmartlink_stop_smartlink}, -+ {"setchannel", _ksmartlink_set_channel}, -+ {"getchannel", _ksmartlink_get_channel}, -+ {"setpromisc", _ksmartlink_set_promisc}, -+ {"getpromisc", _ksmartlink_get_promisc}, -+}; -+ -+static u32 _ksmartlink_cmd_table_size = -+ sizeof(_ksmartlink_cmd_table) / sizeof(struct ksmartlink_cmd); -+#ifdef KSMARTLINK_DEBUG -+static void _ksmartlink_hex_dump(u8 * pInBuf, u32 inBufLen) -+{ -+ u32 i = 0; -+ printk(KERN_INFO "\nKernel Hex Dump(len=%d):\n", inBufLen); -+ printk(KERN_INFO ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); -+ for (i = 0; i < inBufLen; i++) { -+ if ((i) && ((i & 0xf) == 0)) { -+ printk("\n"); -+ } -+ printk("%02x ", pInBuf[i]); -+ } -+ printk(KERN_INFO "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); -+} -+#endif -+static int _ksmartlink_process_msg(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf, -+ u32 * pOutBufLen) -+{ -+ int ret = 0; -+ u32 i = 0; -+ struct ksmartlink_cmd *pCmd; -+ if (!pInBuf || !pOutBuf || !pOutBufLen) { -+ printk(KERN_ERR "NULL pointer\n"); -+ return -1; -+ } -+ for (i = 0; i < _ksmartlink_cmd_table_size; i++) { -+ if (!strncmp -+ (_ksmartlink_cmd_table[i].cmd, pInBuf, -+ SMARTLINK_CMD_FIXED_LEN)) { -+ break; -+ } -+ } -+ if (i < _ksmartlink_cmd_table_size) { -+ pCmd = &_ksmartlink_cmd_table[i]; -+ if (!pCmd->process_func) { -+ printk(KERN_ERR "CMD %s has NULL process_func\n", -+ pCmd->cmd); -+ return -3; -+ } -+ ret = -+ pCmd->process_func(pInBuf + SMARTLINK_CMD_FIXED_LEN, -+ inBufLen, pOutBuf, pOutBufLen); -+#ifdef CONFIG_SSV_NETLINK_RESPONSE -+ if (ret < 0) { -+ *pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN; -+ } else { -+ if (*pOutBufLen > 0) { -+ pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret; -+ pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = *pOutBuf; -+ } else { -+ pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret; -+ pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = 0; -+ } -+ *pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN; -+ } -+ memcpy(pOutBuf, pCmd->cmd, SMARTLINK_RES_FIXED_LEN); -+#else -+ (void)pOutBuf; -+ (void)pOutBufLen; -+#endif -+ return 0; -+ } else { -+ printk(KERN_INFO "Unknow CMD or Packet?\n"); -+ } -+ return 0; -+} -+static u8 gkBuf[MAX_PAYLOAD] = { 0 }; -+ -+static int ssv_usr_pid = 0; -+void smartlink_nl_recv_msg(struct sk_buff *skb) -+{ -+ struct nlmsghdr *nlh; -+#ifdef CONFIG_SSV_NETLINK_RESPONSE -+ struct sk_buff *skb_out; -+#endif -+ int ret = 0; -+ u8 *pInBuf = NULL; -+ u32 inBufLen = 0; -+ u32 outBufLen = 0; -+ nlh = (struct nlmsghdr *)skb->data; -+ ssv_usr_pid = nlh->nlmsg_pid; -+ pInBuf = (u8 *) nlmsg_data(nlh); -+ inBufLen = nlmsg_len(nlh); -+#ifdef KSMARTLINK_DEBUG -+ _ksmartlink_hex_dump(pInBuf, inBufLen); -+#endif -+ outBufLen = 0; -+ memset(gkBuf, 0, MAX_PAYLOAD); -+ ret = _ksmartlink_process_msg(pInBuf, inBufLen, gkBuf, &outBufLen); -+#ifdef CONFIG_SSV_NETLINK_RESPONSE -+ if (outBufLen == 0) { -+ memcpy(gkBuf, "Nothing", 8); -+ outBufLen = strlen(gkBuf); -+ } -+ skb_out = nlmsg_new(outBufLen, 0); -+ if (!skb_out) { -+ printk(KERN_ERR "Failed to allocate new skb\n"); -+ return; -+ } -+ nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0); -+ NETLINK_CB(skb_out).dst_group = 0; -+ memcpy(nlmsg_data(nlh), gkBuf, outBufLen); -+ ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid); -+ if (ret < 0) { -+ printk(KERN_ERR "Error while sending bak to user\n"); -+ } -+#endif -+ return; -+} -+ -+void smartlink_nl_send_msg(struct sk_buff *skb) -+{ -+ struct nlmsghdr *nlh; -+ struct sk_buff *skb_out; -+ int ret = 0; -+ u8 *pOutBuf = skb->data; -+ u32 outBufLen = skb->len; -+#ifdef KSMARTLINK_DEBUG -+#endif -+ skb_out = nlmsg_new(outBufLen, 0); -+ if (!skb_out) { -+ printk(KERN_ERR "Allocate new skb failed!\n"); -+ return; -+ } -+ nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0); -+ NETLINK_CB(skb_out).dst_group = 0; -+ memcpy(nlmsg_data(nlh), pOutBuf, outBufLen); -+ ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid); -+ if (ret < 0) { -+ printk(KERN_ERR "nlmsg_unicast failed!\n"); -+ } -+ kfree_skb(skb); -+ return; -+} -+ -+EXPORT_SYMBOL(smartlink_nl_send_msg); -+int ksmartlink_init(void) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0) -+ nl_sk = netlink_kernel_create(&init_net, -+ NETLINK_SMARTLINK, -+ 0, -+ smartlink_nl_recv_msg, NULL, THIS_MODULE); -+#else -+ struct netlink_kernel_cfg cfg = { -+ .groups = 0, -+ .input = smartlink_nl_recv_msg, -+ }; -+ nl_sk = netlink_kernel_create(&init_net, NETLINK_SMARTLINK, &cfg); -+#endif -+ printk(KERN_INFO "***************SmartLink Init-S**************\n"); -+ if (!nl_sk) { -+ printk(KERN_ERR "Error creating socket.\n"); -+ return -10; -+ } -+ printk(KERN_INFO "***************SmartLink Init-E**************\n"); -+ return 0; -+} -+ -+void ksmartlink_exit(void) -+{ -+ printk(KERN_INFO "%s\n", __FUNCTION__); -+ if (nl_sk) { -+ netlink_kernel_release(nl_sk); -+ nl_sk = NULL; -+ } -+} -+ -+EXPORT_SYMBOL(ksmartlink_init); -+EXPORT_SYMBOL(ksmartlink_exit); -diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c -@@ -0,0 +1,223 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "dev.h" -+#include "ssv6xxx_debugfs.h" -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+#define QUEUE_STATUS_BUF_SIZE (4096) -+static ssize_t queue_status_read(struct file *file, -+ char __user * user_buf, size_t count, -+ loff_t * ppos) -+{ -+ struct ssv_softc *sc = (struct ssv_softc *)file->private_data; -+ char *status_buf = kzalloc(QUEUE_STATUS_BUF_SIZE, GFP_KERNEL); -+ ssize_t status_size; -+ ssize_t ret; -+ if (!status_buf) -+ return -ENOMEM; -+ status_size = ssv6xxx_tx_queue_status_dump(sc, status_buf, -+ QUEUE_STATUS_BUF_SIZE); -+ ret = simple_read_from_buffer(user_buf, count, ppos, status_buf, -+ status_size); -+ kfree(status_buf); -+ return ret; -+} -+ -+static int queue_status_open(struct inode *inode, struct file *file) -+{ -+ file->private_data = inode->i_private; -+ return 0; -+} -+ -+static const struct file_operations queue_status_fops -+ = {.read = queue_status_read, -+ .open = queue_status_open -+}; -+#endif -+int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name) -+{ -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct ieee80211_hw *hw = sc->hw; -+ struct dentry *phy_debugfs_dir = hw->wiphy->debugfsdir; -+ struct dentry *drv_debugfs_dir; -+ drv_debugfs_dir = debugfs_create_dir(name, phy_debugfs_dir); -+ if (!drv_debugfs_dir) { -+ dev_err(sc->dev, "Failed to create debugfs.\n"); -+ return -ENOMEM; -+ } -+ sc->debugfs_dir = drv_debugfs_dir; -+ sc->sh->hci.hci_ops->hci_init_debugfs(sc->debugfs_dir); -+ debugfs_create_file("queue_status", 00444, drv_debugfs_dir, -+ sc, &queue_status_fops); -+#endif -+ return 0; -+} -+ -+void ssv6xxx_deinit_debugfs(struct ssv_softc *sc) -+{ -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ if (!sc->debugfs_dir) -+ return; -+ sc->sh->hci.hci_ops->hci_deinit_debugfs(); -+ debugfs_remove_recursive(sc->debugfs_dir); -+ sc->debugfs_dir = NULL; -+#endif -+} -+ -+int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc, -+ struct ieee80211_vif *vif) -+{ -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct dentry *drv_debugfs_dir = sc->debugfs_dir; -+ struct dentry *vif_debugfs_dir; -+ char vif_addr[18]; -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx]; -+ snprintf(vif_addr, sizeof(vif_addr), "%02X-%02X-%02X-%02X-%02X-%02X", -+ vif->addr[0], vif->addr[1], vif->addr[2], -+ vif->addr[3], vif->addr[4], vif->addr[5]); -+ vif_debugfs_dir = debugfs_create_dir(vif_addr, drv_debugfs_dir); -+ if (!vif_debugfs_dir) { -+ dev_err(sc->dev, "Failed to create interface debugfs for %s.\n", -+ vif_addr); -+ return -ENOMEM; -+ } -+ sc->debugfs_dir = drv_debugfs_dir; -+ vif_info->debugfs_dir = vif_debugfs_dir; -+#endif -+ return 0; -+} -+ -+int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc, -+ struct ieee80211_vif *vif) -+{ -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)vif->drv_priv; -+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx]; -+ if ((vif_info->debugfs_dir == NULL) || (sc->debugfs_dir == NULL)) -+ return 0; -+ debugfs_remove_recursive(vif_info->debugfs_dir); -+ vif_info->debugfs_dir = NULL; -+#endif -+ return 0; -+} -+ -+int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta) -+{ -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)sta->vif->drv_priv; -+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx]; -+ if ((sc->debugfs_dir == NULL) || (vif_info->debugfs_dir == NULL) -+ || (sta->debugfs_dir == NULL)) -+ return 0; -+ debugfs_remove_recursive(sta->debugfs_dir); -+ sta->debugfs_dir = NULL; -+#endif -+ return 0; -+} -+ -+int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta) -+{ -+#ifdef CONFIG_SSV6XXX_DEBUGFS -+ struct ssv_vif_priv_data *vif_priv = -+ (struct ssv_vif_priv_data *)sta->vif->drv_priv; -+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx]; -+ struct dentry *vif_debugfs_dir = vif_info->debugfs_dir; -+ struct dentry *sta_debugfs_dir; -+ char sta_addr[18]; -+ if (vif_debugfs_dir == NULL) -+ return 0; -+ snprintf(sta_addr, sizeof(sta_addr), "%02X-%02X-%02X-%02X-%02X-%02X", -+ sta->sta->addr[0], sta->sta->addr[1], sta->sta->addr[2], -+ sta->sta->addr[3], sta->sta->addr[4], sta->sta->addr[5]); -+ sta_debugfs_dir = debugfs_create_dir(sta_addr, vif_debugfs_dir); -+ if (!sta_debugfs_dir) { -+ dev_err(sc->dev, "Failed to create interface debugfs for %s.\n", -+ sta_addr); -+ return -ENOMEM; -+ } -+ sta->debugfs_dir = sta_debugfs_dir; -+#endif -+ return 0; -+} -+ -+#define DEBUGFS_ADD_FILE(name,parent,mode) do { \ -+ if (!debugfs_create_file(#name, mode, parent, priv, \ -+ &ssv_dbgfs_##name##_ops)) \ -+ goto err; \ -+} while (0) -+#define DEBUGFS_ADD_BOOL(name,parent,ptr) do { \ -+ struct dentry *__tmp; \ -+ __tmp = debugfs_create_bool(#name, S_IWUSR | S_IRUSR, \ -+ parent, ptr); \ -+ if (IS_ERR(__tmp) || !__tmp) \ -+ goto err; \ -+} while (0) -+#define DEBUGFS_ADD_X32(name,parent,ptr) do { \ -+ struct dentry *__tmp; \ -+ __tmp = debugfs_create_x32(#name, S_IWUSR | S_IRUSR, \ -+ parent, ptr); \ -+ if (IS_ERR(__tmp) || !__tmp) \ -+ goto err; \ -+} while (0) -+#define DEBUGFS_ADD_U32(name,parent,ptr,mode) do { \ -+ struct dentry *__tmp; \ -+ __tmp = debugfs_create_u32(#name, mode, \ -+ parent, ptr); \ -+ if (IS_ERR(__tmp) || !__tmp) \ -+ goto err; \ -+} while (0) -+#define DEBUGFS_READ_FUNC(name) \ -+static ssize_t ssv_dbgfs_##name##_read(struct file *file, \ -+ char __user *user_buf, \ -+ size_t count, loff_t *ppos); -+#define DEBUGFS_WRITE_FUNC(name) \ -+static ssize_t ssv_dbgfs_##name##_write(struct file *file, \ -+ const char __user *user_buf, \ -+ size_t count, loff_t *ppos); -+#define DEBUGFS_READ_FILE_OPS(name) \ -+ DEBUGFS_READ_FUNC(name); \ -+static const struct file_operations ssv_dbgfs_##name##_ops = { \ -+ .read = ssv_dbgfs_##name##_read, \ -+ .open = ssv_dbgfs_open_file_generic, \ -+ .llseek = generic_file_llseek, \ -+}; -+#define DEBUGFS_WRITE_FILE_OPS(name) \ -+ DEBUGFS_WRITE_FUNC(name); \ -+static const struct file_operations ssv_dbgfs_##name##_ops = { \ -+ .write = ssv_dbgfs_##name##_write, \ -+ .open = ssv_dbgfs_open_file_generic, \ -+ .llseek = generic_file_llseek, \ -+}; -+#define DEBUGFS_READ_WRITE_FILE_OPS(name) \ -+ DEBUGFS_READ_FUNC(name); \ -+ DEBUGFS_WRITE_FUNC(name); \ -+static const struct file_operations ssv_dbgfs_##name##_ops = { \ -+ .write = ssv_dbgfs_##name##_write, \ -+ .read = ssv_dbgfs_##name##_read, \ -+ .open = ssv_dbgfs_open_file_generic, \ -+ .llseek = generic_file_llseek, \ -+}; -diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h -@@ -0,0 +1,27 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef __SSV6XXX_DBGFS_H__ -+#define __SSV6XXX_DBGFS_H__ -+int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name); -+void ssv6xxx_deinit_debugfs(struct ssv_softc *sc); -+int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc, -+ struct ieee80211_vif *vif); -+int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc, -+ struct ieee80211_vif *vif); -+int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta); -+int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta); -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c -@@ -0,0 +1,1384 @@ -+/****************************************************************************** -+ * -+ * Copyright(c) 2012 - 2018 icomm Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -+ * -+ * -+ ******************************************************************************/ -+ -+#include "dev.h" -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(CONFIG_SSV_VENDOR_EXT_SUPPORT) -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "ssv_cfgvendor.h" -+ -+#define wiphy_to_softc(x) (*((struct ssv_softc**)wiphy_priv(x))) -+#define FUNC_NDEV_FMT "%s" -+#define FUNC_NDEV_ARG(ndev) __func__ -+ -+#define _drv_always_ 1 -+#define _drv_emerg_ 2 -+#define _drv_alert_ 3 -+#define _drv_crit_ 4 -+#define _drv_err_ 5 -+#define _drv_warning_ 6 -+#define _drv_notice_ 7 -+#define _drv_info_ 8 -+#define _drv_dump_ 9 -+#define _drv_debug_ 10 -+ -+struct sk_buff *ssv_cfg80211_vendor_event_alloc(struct wiphy *wiphy, int len, -+ int event_id, gfp_t gfp) -+{ -+ struct sk_buff *skb; -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0)) -+ skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp); -+#else -+ skb = cfg80211_vendor_event_alloc(wiphy, NULL, len, event_id, gfp); -+#endif -+ return skb; -+} -+ -+#define ssv_cfg80211_vendor_event(skb, gfp) \ -+ cfg80211_vendor_event(skb, gfp) -+ -+#define ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \ -+ cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) -+ -+#define ssv_cfg80211_vendor_cmd_reply(skb) \ -+ cfg80211_vendor_cmd_reply(skb) -+ -+/* -+ * This API is to be used for asynchronous vendor events. This -+ * shouldn't be used in response to a vendor command from its -+ * do_it handler context (instead ssv_cfgvendor_send_cmd_reply should -+ * be used). -+ */ -+int ssv_cfgvendor_send_async_event(struct wiphy *wiphy, -+ struct net_device *dev, int event_id, -+ const void *data, int len) -+{ -+ u16 kflags; -+ struct sk_buff *skb; -+ -+ kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL; -+ -+ /* Alloc the SKB for vendor_event */ -+ skb = ssv_cfg80211_vendor_event_alloc(wiphy, len, event_id, kflags); -+ if (!skb) { -+ dev_err(&wiphy->dev, "skb alloc failed\n"); -+ return -ENOMEM; -+ } -+ -+ /* Push the data to the skb */ -+ nla_put_nohdr(skb, len, data); -+ -+ ssv_cfg80211_vendor_event(skb, kflags); -+ -+ return 0; -+} -+ -+static int ssv_cfgvendor_send_cmd_reply(struct wiphy *wiphy, -+ struct net_device *dev, -+ const void *data, int len) -+{ -+ struct sk_buff *skb; -+ -+ /* Alloc the SKB for vendor_event */ -+ skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len); -+ if (unlikely(!skb)) { -+ dev_err(&wiphy->dev, "skb alloc failed"); -+ return -ENOMEM; -+ } -+ -+ /* Push the data to the skb */ -+ nla_put_nohdr(skb, len, data); -+ -+ return ssv_cfg80211_vendor_cmd_reply(skb); -+} -+ -+#define WIFI_FEATURE_INFRA 0x0001 /* Basic infrastructure mode */ -+#define WIFI_FEATURE_INFRA_5G 0x0002 /* Support for 5 GHz Band */ -+#define WIFI_FEATURE_HOTSPOT 0x0004 /* Support for GAS/ANQP */ -+#define WIFI_FEATURE_P2P 0x0008 /* Wifi-Direct */ -+#define WIFI_FEATURE_SOFT_AP 0x0010 /* Soft AP */ -+#define WIFI_FEATURE_GSCAN 0x0020 /* Google-Scan APIs */ -+#define WIFI_FEATURE_NAN 0x0040 /* Neighbor Awareness Networking */ -+#define WIFI_FEATURE_D2D_RTT 0x0080 /* Device-to-device RTT */ -+#define WIFI_FEATURE_D2AP_RTT 0x0100 /* Device-to-AP RTT */ -+#define WIFI_FEATURE_BATCH_SCAN 0x0200 /* Batched Scan (legacy) */ -+#define WIFI_FEATURE_PNO 0x0400 /* Preferred network offload */ -+#define WIFI_FEATURE_ADDITIONAL_STA 0x0800 /* Support for two STAs */ -+#define WIFI_FEATURE_TDLS 0x1000 /* Tunnel directed link setup */ -+#define WIFI_FEATURE_TDLS_OFFCHANNEL 0x2000 /* Support for TDLS off channel */ -+#define WIFI_FEATURE_EPR 0x4000 /* Enhanced power reporting */ -+#define WIFI_FEATURE_AP_STA 0x8000 /* Support for AP STA Concurrency */ -+ -+#define MAX_FEATURE_SET_CONCURRRENT_GROUPS 3 -+ -+int ssv_dev_get_feature_set(struct net_device *dev) -+{ -+ int feature_set = 0; -+ -+ feature_set |= WIFI_FEATURE_INFRA; -+ -+ feature_set |= WIFI_FEATURE_P2P; -+ feature_set |= WIFI_FEATURE_SOFT_AP; -+ -+#if defined(GSCAN_SUPPORT) -+ feature_set |= WIFI_FEATURE_GSCAN; -+#endif -+ -+#if defined(RTT_SUPPORT) -+ feature_set |= WIFI_FEATURE_NAN; -+ feature_set |= WIFI_FEATURE_D2D_RTT; -+ feature_set |= WIFI_FEATURE_D2AP_RTT; -+#endif -+ -+ return feature_set; -+} -+ -+int *ssv_dev_get_feature_set_matrix(struct net_device *dev, int *num) -+{ -+ int feature_set_full, mem_needed; -+ int *ret; -+ -+ *num = 0; -+ mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS; -+ ret = -+ (int *)kmalloc(mem_needed, in_interrupt()? GFP_ATOMIC : GFP_KERNEL); -+ -+ if (!ret) { -+ dev_err(&dev->dev, "failed to allocate %d bytes\n", mem_needed); -+ return ret; -+ } -+ -+ feature_set_full = ssv_dev_get_feature_set(dev); -+ -+ ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) | -+ (feature_set_full & WIFI_FEATURE_INFRA_5G) | -+ (feature_set_full & WIFI_FEATURE_NAN) | -+ (feature_set_full & WIFI_FEATURE_D2D_RTT) | -+ (feature_set_full & WIFI_FEATURE_D2AP_RTT) | -+ (feature_set_full & WIFI_FEATURE_PNO) | -+ (feature_set_full & WIFI_FEATURE_BATCH_SCAN) | -+ (feature_set_full & WIFI_FEATURE_GSCAN) | -+ (feature_set_full & WIFI_FEATURE_HOTSPOT) | -+ (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) | -+ (feature_set_full & WIFI_FEATURE_EPR); -+ -+ ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) | -+ (feature_set_full & WIFI_FEATURE_INFRA_5G) | -+ /* Not yet verified NAN with P2P */ -+ /* (feature_set_full & WIFI_FEATURE_NAN) | */ -+ (feature_set_full & WIFI_FEATURE_P2P) | -+ (feature_set_full & WIFI_FEATURE_D2AP_RTT) | -+ (feature_set_full & WIFI_FEATURE_D2D_RTT) | -+ (feature_set_full & WIFI_FEATURE_EPR); -+ -+ ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) | -+ (feature_set_full & WIFI_FEATURE_INFRA_5G) | -+ (feature_set_full & WIFI_FEATURE_NAN) | -+ (feature_set_full & WIFI_FEATURE_D2D_RTT) | -+ (feature_set_full & WIFI_FEATURE_D2AP_RTT) | -+ (feature_set_full & WIFI_FEATURE_TDLS) | -+ (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) | -+ (feature_set_full & WIFI_FEATURE_EPR); -+ *num = MAX_FEATURE_SET_CONCURRRENT_GROUPS; -+ -+ return ret; -+} -+ -+#define wdev_to_ndev(wdev) NULL -+ -+static int ssv_cfgvendor_get_feature_set(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0; -+ int reply; -+ -+ reply = ssv_dev_get_feature_set(wdev_to_ndev(wdev)); -+ -+ err = -+ ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply, -+ sizeof(int)); -+ -+ if (unlikely(err)) -+ dev_err(&wiphy->dev, "vendor Command reply failed, ret:%d\n", err); -+ -+ return err; -+} -+ -+static int ssv_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0; -+ struct sk_buff *skb; -+ int *reply; -+ int num, mem_needed, i; -+ -+ reply = ssv_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num); -+ -+ if (!reply) { -+ dev_err(&wiphy->dev, "could not get feature list matrix\n"); -+ err = -EINVAL; -+ return err; -+ } -+ -+ mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) + -+ ATTRIBUTE_U32_LEN; -+ -+ /* Alloc the SKB for vendor_event */ -+ skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed); -+ if (unlikely(!skb)) { -+ dev_err(&wiphy->dev, "skb alloc failed\n"); -+ err = -ENOMEM; -+ goto exit; -+ } -+ -+ nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num); -+ for (i = 0; i < num; i++) { -+ nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]); -+ } -+ -+ err = ssv_cfg80211_vendor_cmd_reply(skb); -+ -+ if (unlikely(err)) -+ dev_err(&wiphy->dev, "vendor Command reply failed, ret=%d\n", err); -+ exit: -+ kfree((void *)reply); -+ return err; -+} -+ -+#if defined(GSCAN_SUPPORT) && 0 -+int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, -+ struct net_device *dev, void *data, int len, -+ wl_vendor_event_t event) -+{ -+ u16 kflags; -+ const void *ptr; -+ struct sk_buff *skb; -+ int malloc_len, total, iter_cnt_to_send, cnt; -+ gscan_results_cache_t *cache = (gscan_results_cache_t *) data; -+ -+ total = len / sizeof(wifi_gscan_result_t); -+ while (total > 0) { -+ malloc_len = -+ (total * sizeof(wifi_gscan_result_t)) + -+ VENDOR_DATA_OVERHEAD; -+ if (malloc_len > NLMSG_DEFAULT_SIZE) { -+ malloc_len = NLMSG_DEFAULT_SIZE; -+ } -+ iter_cnt_to_send = -+ (malloc_len - -+ VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t); -+ total = total - iter_cnt_to_send; -+ -+ kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL; -+ -+ /* Alloc the SKB for vendor_event */ -+ skb = -+ ssv_cfg80211_vendor_event_alloc(wiphy, malloc_len, event, -+ kflags); -+ if (!skb) { -+ WL_ERR(("skb alloc failed")); -+ return -ENOMEM; -+ } -+ -+ while (cache && iter_cnt_to_send) { -+ ptr = -+ (const void *)&cache->results[cache->tot_consumed]; -+ -+ if (iter_cnt_to_send < -+ (cache->tot_count - cache->tot_consumed)) -+ cnt = iter_cnt_to_send; -+ else -+ cnt = (cache->tot_count - cache->tot_consumed); -+ -+ iter_cnt_to_send -= cnt; -+ cache->tot_consumed += cnt; -+ /* Push the data to the skb */ -+ nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr); -+ if (cache->tot_consumed == cache->tot_count) -+ cache = cache->next; -+ -+ } -+ -+ ssv_cfg80211_vendor_event(skb, kflags); -+ } -+ -+ return 0; -+} -+ -+static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ dhd_pno_gscan_capabilities_t *reply = NULL; -+ uint32 reply_len = 0; -+ -+ reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg), -+ DHD_PNO_GET_CAPABILITIES, NULL, -+ &reply_len); -+ if (!reply) { -+ WL_ERR(("Could not get capabilities\n")); -+ err = -EINVAL; -+ return err; -+ } -+ -+ err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg), -+ reply, reply_len); -+ -+ if (unlikely(err)) -+ WL_ERR(("Vendor Command reply failed ret:%d \n", err)); -+ -+ kfree(reply); -+ return err; -+} -+ -+static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0, type, band; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ uint16 *reply = NULL; -+ uint32 reply_len = 0, num_channels, mem_needed; -+ struct sk_buff *skb; -+ -+ type = nla_type(data); -+ -+ if (type == GSCAN_ATTRIBUTE_BAND) { -+ band = nla_get_u32(data); -+ } else { -+ return -1; -+ } -+ -+ reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg), -+ DHD_PNO_GET_CHANNEL_LIST, &band, -+ &reply_len); -+ -+ if (!reply) { -+ WL_ERR(("Could not get channel list\n")); -+ err = -EINVAL; -+ return err; -+ } -+ num_channels = reply_len / sizeof(uint32); -+ mem_needed = -+ reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2); -+ -+ /* Alloc the SKB for vendor_event */ -+ skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed); -+ if (unlikely(!skb)) { -+ WL_ERR(("skb alloc failed")); -+ err = -ENOMEM; -+ goto exit; -+ } -+ -+ nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels); -+ nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply); -+ -+ err = ssv_cfg80211_vendor_cmd_reply(skb); -+ -+ if (unlikely(err)) -+ WL_ERR(("Vendor Command reply failed ret:%d \n", err)); -+ exit: -+ kfree(reply); -+ return err; -+} -+ -+static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ gscan_results_cache_t *results, *iter; -+ uint32 reply_len, complete = 0, num_results_iter; -+ int32 mem_needed; -+ wifi_gscan_result_t *ptr; -+ uint16 num_scan_ids, num_results; -+ struct sk_buff *skb; -+ struct nlattr *scan_hdr; -+ -+ dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg)); -+ dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg)); -+ results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg), -+ DHD_PNO_GET_BATCH_RESULTS, NULL, -+ &reply_len); -+ -+ if (!results) { -+ WL_ERR(("No results to send %d\n", err)); -+ err = -+ ssv_cfgvendor_send_cmd_reply(wiphy, -+ bcmcfg_to_prmry_ndev(cfg), -+ results, 0); -+ -+ if (unlikely(err)) -+ WL_ERR(("Vendor Command reply failed ret:%d \n", err)); -+ dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev -+ (cfg)); -+ return err; -+ } -+ num_scan_ids = reply_len & 0xFFFF; -+ num_results = (reply_len & 0xFFFF0000) >> 16; -+ mem_needed = (num_results * sizeof(wifi_gscan_result_t)) + -+ (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) + -+ VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN; -+ -+ if (mem_needed > (int32) NLMSG_DEFAULT_SIZE) { -+ mem_needed = (int32) NLMSG_DEFAULT_SIZE; -+ complete = 0; -+ } else { -+ complete = 1; -+ } -+ -+ WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete, -+ mem_needed, (int)NLMSG_DEFAULT_SIZE)); -+ /* Alloc the SKB for vendor_event */ -+ skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed); -+ if (unlikely(!skb)) { -+ WL_ERR(("skb alloc failed")); -+ dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev -+ (cfg)); -+ return -ENOMEM; -+ } -+ iter = results; -+ -+ nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete); -+ -+ mem_needed = -+ mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN + -+ VENDOR_REPLY_OVERHEAD); -+ -+ while (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) > 0)) { -+ scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS); -+ nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id); -+ nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag); -+ num_results_iter = -+ (mem_needed - -+ GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t); -+ -+ if ((iter->tot_count - iter->tot_consumed) < num_results_iter) -+ num_results_iter = iter->tot_count - iter->tot_consumed; -+ -+ nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS, -+ num_results_iter); -+ if (num_results_iter) { -+ ptr = &iter->results[iter->tot_consumed]; -+ iter->tot_consumed += num_results_iter; -+ nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS, -+ num_results_iter * sizeof(wifi_gscan_result_t), -+ ptr); -+ } -+ nla_nest_end(skb, scan_hdr); -+ mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN + -+ (num_results_iter * sizeof(wifi_gscan_result_t)); -+ iter = iter->next; -+ } -+ -+ dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg)); -+ dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg)); -+ -+ return ssv_cfg80211_vendor_cmd_reply(skb); -+} -+ -+static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ int type, tmp = len; -+ int run = 0xFF; -+ int flush = 0; -+ const struct nlattr *iter; -+ -+ nla_for_each_attr(iter, data, len, tmp) { -+ type = nla_type(iter); -+ if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE) -+ run = nla_get_u32(iter); -+ else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE) -+ flush = nla_get_u32(iter); -+ } -+ -+ if (run != 0xFF) { -+ err = -+ dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run, -+ flush); -+ -+ if (unlikely(err)) -+ WL_ERR(("Could not run gscan:%d \n", err)); -+ return err; -+ } else { -+ return -1; -+ } -+ -+} -+ -+static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ int type; -+ bool real_time = FALSE; -+ -+ type = nla_type(data); -+ -+ if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) { -+ real_time = nla_get_u32(data); -+ -+ err = -+ dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev -+ (cfg), real_time); -+ -+ if (unlikely(err)) -+ WL_ERR(("Could not run gscan:%d \n", err)); -+ -+ } else { -+ err = -1; -+ } -+ -+ return err; -+} -+ -+static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ gscan_scan_params_t *scan_param; -+ int j = 0; -+ int type, tmp, tmp1, tmp2, k = 0; -+ const struct nlattr *iter, *iter1, *iter2; -+ struct dhd_pno_gscan_channel_bucket *ch_bucket; -+ -+ scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL); -+ if (!scan_param) { -+ WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n")); -+ err = -EINVAL; -+ return err; -+ -+ } -+ -+ scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC; -+ nla_for_each_attr(iter, data, len, tmp) { -+ type = nla_type(iter); -+ -+ if (j >= GSCAN_MAX_CH_BUCKETS) -+ break; -+ -+ switch (type) { -+ case GSCAN_ATTRIBUTE_BASE_PERIOD: -+ scan_param->scan_fr = nla_get_u32(iter) / 1000; -+ break; -+ case GSCAN_ATTRIBUTE_NUM_BUCKETS: -+ scan_param->nchannel_buckets = nla_get_u32(iter); -+ break; -+ case GSCAN_ATTRIBUTE_CH_BUCKET_1: -+ case GSCAN_ATTRIBUTE_CH_BUCKET_2: -+ case GSCAN_ATTRIBUTE_CH_BUCKET_3: -+ case GSCAN_ATTRIBUTE_CH_BUCKET_4: -+ case GSCAN_ATTRIBUTE_CH_BUCKET_5: -+ case GSCAN_ATTRIBUTE_CH_BUCKET_6: -+ case GSCAN_ATTRIBUTE_CH_BUCKET_7: -+ nla_for_each_nested(iter1, iter, tmp1) { -+ type = nla_type(iter1); -+ ch_bucket = scan_param->channel_bucket; -+ -+ switch (type) { -+ case GSCAN_ATTRIBUTE_BUCKET_ID: -+ break; -+ case GSCAN_ATTRIBUTE_BUCKET_PERIOD: -+ ch_bucket[j].bucket_freq_multiple = -+ nla_get_u32(iter1) / 1000; -+ break; -+ case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS: -+ ch_bucket[j].num_channels = -+ nla_get_u32(iter1); -+ break; -+ case GSCAN_ATTRIBUTE_BUCKET_CHANNELS: -+ nla_for_each_nested(iter2, iter1, tmp2) { -+ if (k >= -+ PFN_SWC_RSSI_WINDOW_MAX) -+ break; -+ ch_bucket[j].chan_list[k] = -+ nla_get_u32(iter2); -+ k++; -+ } -+ k = 0; -+ break; -+ case GSCAN_ATTRIBUTE_BUCKETS_BAND: -+ ch_bucket[j].band = (uint16) -+ nla_get_u32(iter1); -+ break; -+ case GSCAN_ATTRIBUTE_REPORT_EVENTS: -+ ch_bucket[j].report_flag = (uint8) -+ nla_get_u32(iter1); -+ break; -+ } -+ } -+ j++; -+ break; -+ } -+ } -+ -+ if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg), -+ DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) { -+ WL_ERR(("Could not set GSCAN scan cfg\n")); -+ err = -EINVAL; -+ } -+ -+ kfree(scan_param); -+ return err; -+ -+} -+ -+static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy, -+ struct wireless_dev *wdev, const void *data, -+ int len) -+{ -+ int err = 0; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ gscan_hotlist_scan_params_t *hotlist_params; -+ int tmp, tmp1, tmp2, type, j = 0, dummy; -+ const struct nlattr *outer, *inner, *iter; -+ uint8 flush = 0; -+ struct bssid_t *pbssid; -+ -+ hotlist_params = -+ (gscan_hotlist_scan_params_t *) kzalloc(len, GFP_KERNEL); -+ if (!hotlist_params) { -+ WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len)); -+ return -1; -+ } -+ -+ hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT; -+ -+ nla_for_each_attr(iter, data, len, tmp2) { -+ type = nla_type(iter); -+ switch (type) { -+ case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS: -+ pbssid = hotlist_params->bssid; -+ nla_for_each_nested(outer, iter, tmp) { -+ nla_for_each_nested(inner, outer, tmp1) { -+ type = nla_type(inner); -+ -+ switch (type) { -+ case GSCAN_ATTRIBUTE_BSSID: -+ memcpy(&(pbssid[j].macaddr), -+ nla_data(inner), -+ ETHER_ADDR_LEN); -+ break; -+ case GSCAN_ATTRIBUTE_RSSI_LOW: -+ pbssid[j]. -+ rssi_reporting_threshold = -+ (int8) nla_get_u8(inner); -+ break; -+ case GSCAN_ATTRIBUTE_RSSI_HIGH: -+ dummy = -+ (int8) nla_get_u8(inner); -+ break; -+ } -+ } -+ j++; -+ } -+ hotlist_params->nbssid = j; -+ break; -+ case GSCAN_ATTRIBUTE_HOTLIST_FLUSH: -+ flush = nla_get_u8(iter); -+ break; -+ case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE: -+ hotlist_params->lost_ap_window = nla_get_u32(iter); -+ break; -+ } -+ -+ } -+ -+ if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg), -+ DHD_PNO_GEOFENCE_SCAN_CFG_ID, -+ hotlist_params, flush) < 0) { -+ WL_ERR(("Could not set GSCAN HOTLIST cfg\n")); -+ err = -EINVAL; -+ goto exit; -+ } -+ exit: -+ kfree(hotlist_params); -+ return err; -+} -+ -+static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0, tmp, type; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ gscan_batch_params_t batch_param; -+ const struct nlattr *iter; -+ -+ batch_param.mscan = batch_param.bestn = 0; -+ batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET; -+ -+ nla_for_each_attr(iter, data, len, tmp) { -+ type = nla_type(iter); -+ -+ switch (type) { -+ case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN: -+ batch_param.bestn = nla_get_u32(iter); -+ break; -+ case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE: -+ batch_param.mscan = nla_get_u32(iter); -+ break; -+ case GSCAN_ATTRIBUTE_REPORT_THRESHOLD: -+ batch_param.buffer_threshold = nla_get_u32(iter); -+ break; -+ } -+ } -+ -+ if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg), -+ DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param, -+ 0) < 0) { -+ WL_ERR(("Could not set batch cfg\n")); -+ err = -EINVAL; -+ return err; -+ } -+ -+ return err; -+} -+ -+static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ gscan_swc_params_t *significant_params; -+ int tmp, tmp1, tmp2, type, j = 0; -+ const struct nlattr *outer, *inner, *iter; -+ uint8 flush = 0; -+ wl_pfn_significant_bssid_t *pbssid; -+ -+ significant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL); -+ if (!significant_params) { -+ WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len)); -+ return -1; -+ } -+ -+ nla_for_each_attr(iter, data, len, tmp2) { -+ type = nla_type(iter); -+ -+ switch (type) { -+ case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH: -+ flush = nla_get_u8(iter); -+ break; -+ case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE: -+ significant_params->rssi_window = nla_get_u16(iter); -+ break; -+ case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE: -+ significant_params->lost_ap_window = nla_get_u16(iter); -+ break; -+ case GSCAN_ATTRIBUTE_MIN_BREACHING: -+ significant_params->swc_threshold = nla_get_u16(iter); -+ break; -+ case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS: -+ pbssid = significant_params->bssid_elem_list; -+ nla_for_each_nested(outer, iter, tmp) { -+ nla_for_each_nested(inner, outer, tmp1) { -+ switch (nla_type(inner)) { -+ case GSCAN_ATTRIBUTE_BSSID: -+ memcpy(&(pbssid[j].macaddr), -+ nla_data(inner), -+ ETHER_ADDR_LEN); -+ break; -+ case GSCAN_ATTRIBUTE_RSSI_HIGH: -+ pbssid[j].rssi_high_threshold = -+ (int8) nla_get_u8(inner); -+ break; -+ case GSCAN_ATTRIBUTE_RSSI_LOW: -+ pbssid[j].rssi_low_threshold = -+ (int8) nla_get_u8(inner); -+ break; -+ } -+ } -+ j++; -+ } -+ break; -+ } -+ } -+ significant_params->nbssid = j; -+ -+ if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg), -+ DHD_PNO_SIGNIFICANT_SCAN_CFG_ID, -+ significant_params, flush) < 0) { -+ WL_ERR(("Could not set GSCAN significant cfg\n")); -+ err = -EINVAL; -+ goto exit; -+ } -+ exit: -+ kfree(significant_params); -+ return err; -+} -+#endif /* GSCAN_SUPPORT */ -+ -+#if defined(RTT_SUPPORT) && 0 -+void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data) -+{ -+ struct wireless_dev *wdev = (struct wireless_dev *)ctx; -+ struct wiphy *wiphy; -+ struct sk_buff *skb; -+ uint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0; -+ gfp_t kflags; -+ rtt_report_t *rtt_report = NULL; -+ rtt_result_t *rtt_result = NULL; -+ struct list_head *rtt_list; -+ wiphy = wdev->wiphy; -+ -+ WL_DBG(("In\n")); -+ /* Push the data to the skb */ -+ if (!rtt_data) { -+ WL_ERR(("rtt_data is NULL\n")); -+ goto exit; -+ } -+ rtt_list = (struct list_head *)rtt_data; -+ kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL; -+ /* Alloc the SKB for vendor_event */ -+ skb = -+ ssv_cfg80211_vendor_event_alloc(wiphy, tot_len, -+ GOOGLE_RTT_COMPLETE_EVENT, kflags); -+ if (!skb) { -+ WL_ERR(("skb alloc failed")); -+ goto exit; -+ } -+ /* fill in the rtt results on each entry */ -+ list_for_each_entry(rtt_result, rtt_list, list) { -+ entry_len = 0; -+ if (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) { -+ entry_len = sizeof(rtt_report_t); -+ rtt_report = kzalloc(entry_len, kflags); -+ if (!rtt_report) { -+ WL_ERR(("rtt_report alloc failed")); -+ goto exit; -+ } -+ rtt_report->addr = rtt_result->peer_mac; -+ rtt_report->num_measurement = 1; /* ONE SHOT */ -+ rtt_report->status = rtt_result->err_code; -+ rtt_report->type = -+ (rtt_result->TOF_type == -+ TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY; -+ rtt_report->peer = rtt_result->target_info->peer; -+ rtt_report->channel = rtt_result->target_info->channel; -+ rtt_report->rssi = rtt_result->avg_rssi; -+ /* tx_rate */ -+ rtt_report->tx_rate = rtt_result->tx_rate; -+ /* RTT */ -+ rtt_report->rtt = rtt_result->meanrtt; -+ rtt_report->rtt_sd = rtt_result->sdrtt; -+ /* convert to centi meter */ -+ if (rtt_result->distance != 0xffffffff) -+ rtt_report->distance = -+ (rtt_result->distance >> 2) * 25; -+ else /* invalid distance */ -+ rtt_report->distance = -1; -+ -+ rtt_report->ts = rtt_result->ts; -+ nla_append(skb, entry_len, rtt_report); -+ kfree(rtt_report); -+ } -+ } -+ ssv_cfg80211_vendor_event(skb, kflags); -+ exit: -+ return; -+} -+ -+static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0, rem, rem1, rem2, type; -+ rtt_config_params_t rtt_param; -+ rtt_target_info_t *rtt_target = NULL; -+ const struct nlattr *iter, *iter1, *iter2; -+ int8 eabuf[ETHER_ADDR_STR_LEN]; -+ int8 chanbuf[CHANSPEC_STR_LEN]; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ -+ WL_DBG(("In\n")); -+ err = -+ dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev, -+ wl_cfgvendor_rtt_evt); -+ if (err < 0) { -+ WL_ERR(("failed to register rtt_noti_callback\n")); -+ goto exit; -+ } -+ memset(&rtt_param, 0, sizeof(rtt_param)); -+ nla_for_each_attr(iter, data, len, rem) { -+ type = nla_type(iter); -+ switch (type) { -+ case RTT_ATTRIBUTE_TARGET_CNT: -+ rtt_param.rtt_target_cnt = nla_get_u8(iter); -+ if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) { -+ WL_ERR(("exceed max target count : %d\n", -+ rtt_param.rtt_target_cnt)); -+ err = BCME_RANGE; -+ } -+ break; -+ case RTT_ATTRIBUTE_TARGET_INFO: -+ rtt_target = rtt_param.target_info; -+ nla_for_each_nested(iter1, iter, rem1) { -+ nla_for_each_nested(iter2, iter1, rem2) { -+ type = nla_type(iter2); -+ switch (type) { -+ case RTT_ATTRIBUTE_TARGET_MAC: -+ memcpy(&rtt_target->addr, -+ nla_data(iter2), -+ ETHER_ADDR_LEN); -+ break; -+ case RTT_ATTRIBUTE_TARGET_TYPE: -+ rtt_target->type = -+ nla_get_u8(iter2); -+ break; -+ case RTT_ATTRIBUTE_TARGET_PEER: -+ rtt_target->peer = -+ nla_get_u8(iter2); -+ break; -+ case RTT_ATTRIBUTE_TARGET_CHAN: -+ memcpy(&rtt_target->channel, -+ nla_data(iter2), -+ sizeof(rtt_target-> -+ channel)); -+ break; -+ case RTT_ATTRIBUTE_TARGET_MODE: -+ rtt_target->continuous = -+ nla_get_u8(iter2); -+ break; -+ case RTT_ATTRIBUTE_TARGET_INTERVAL: -+ rtt_target->interval = -+ nla_get_u32(iter2); -+ break; -+ case RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT: -+ rtt_target->measure_cnt = -+ nla_get_u32(iter2); -+ break; -+ case RTT_ATTRIBUTE_TARGET_NUM_PKT: -+ rtt_target->ftm_cnt = -+ nla_get_u32(iter2); -+ break; -+ case RTT_ATTRIBUTE_TARGET_NUM_RETRY: -+ rtt_target->retry_cnt = -+ nla_get_u32(iter2); -+ } -+ } -+ /* convert to chanspec value */ -+ rtt_target->chanspec = -+ dhd_rtt_convert_to_chspec(rtt_target-> -+ channel); -+ if (rtt_target->chanspec == 0) { -+ WL_ERR(("Channel is not valid \n")); -+ goto exit; -+ } -+ WL_INFORM(("Target addr %s, Channel : %s for RTT \n", bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf), wf_chspec_ntoa(rtt_target->chanspec, chanbuf))); -+ rtt_target++; -+ } -+ break; -+ } -+ } -+ WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt)); -+ if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) { -+ WL_ERR(("Could not set RTT configuration\n")); -+ err = -EINVAL; -+ } -+ exit: -+ return err; -+} -+ -+static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0, rem, type, target_cnt = 0; -+ const struct nlattr *iter; -+ struct ether_addr *mac_list = NULL, *mac_addr = NULL; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ -+ nla_for_each_attr(iter, data, len, rem) { -+ type = nla_type(iter); -+ switch (type) { -+ case RTT_ATTRIBUTE_TARGET_CNT: -+ target_cnt = nla_get_u8(iter); -+ mac_list = -+ (struct ether_addr *)kzalloc(target_cnt * -+ ETHER_ADDR_LEN, -+ GFP_KERNEL); -+ if (mac_list == NULL) { -+ WL_ERR(("failed to allocate mem for mac list\n")); -+ goto exit; -+ } -+ mac_addr = &mac_list[0]; -+ break; -+ case RTT_ATTRIBUTE_TARGET_MAC: -+ if (mac_addr) -+ memcpy(mac_addr++, nla_data(iter), -+ ETHER_ADDR_LEN); -+ else { -+ WL_ERR(("mac_list is NULL\n")); -+ goto exit; -+ } -+ break; -+ } -+ if (dhd_dev_rtt_cancel_cfg -+ (bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) { -+ WL_ERR(("Could not cancel RTT configuration\n")); -+ err = -EINVAL; -+ goto exit; -+ } -+ } -+ exit: -+ if (mac_list) -+ kfree(mac_list); -+ return err; -+} -+ -+static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0; -+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); -+ rtt_capabilities_t capability; -+ -+ err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability); -+ if (unlikely(err)) { -+ WL_ERR(("Vendor Command reply failed ret:%d \n", err)); -+ goto exit; -+ } -+ err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg), -+ &capability, sizeof(capability)); -+ -+ if (unlikely(err)) { -+ WL_ERR(("Vendor Command reply failed ret:%d \n", err)); -+ } -+ exit: -+ return err; -+} -+ -+#endif /* RTT_SUPPORT */ -+static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy, -+ struct wireless_dev *wdev, -+ const void *data, int len) -+{ -+ int err = 0; -+ u8 resp[1] = { '\0' }; -+ -+ dev_dbg(&wiphy->dev, "%s\n", (char *)data); -+ err = ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), resp, 1); -+ if (unlikely(err)) -+ dev_err(&wiphy->dev, "vendor Command reply failed, ret=:%d\n", err); -+ -+ return err; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0) -+static const struct wiphy_vendor_command ssv_vendor_cmds[] = { -+ { -+ { -+ .vendor_id = OUI_SSV, -+ .subcmd = RTK_VENDOR_SCMD_PRIV_STR}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_priv_string_handler, -+ .policy = VENDOR_CMD_RAW_DATA}, -+#if defined(GSCAN_SUPPORT) && 0 -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_gscan_get_capabilities, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_SET_CONFIG}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_set_scan_cfg, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_set_batch_scan_cfg, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_initiate_gscan, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_enable_full_scan_result, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_SET_HOTLIST}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_hotlist_cfg, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_significant_change_cfg, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_gscan_get_batch_results, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_gscan_get_channel_list, -+ .policy = VENDOR_CMD_RAW_DATA}, -+#endif /* GSCAN_SUPPORT */ -+#if defined(RTT_SUPPORT) && 0 -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = RTT_SUBCMD_SET_CONFIG}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_rtt_set_config, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = RTT_SUBCMD_CANCEL_CONFIG}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_rtt_cancel_config, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = RTT_SUBCMD_GETCAPABILITY}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_rtt_get_capability, -+ .policy = VENDOR_CMD_RAW_DATA}, -+#endif /* RTT_SUPPORT */ -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = ssv_cfgvendor_get_feature_set, -+ .policy = VENDOR_CMD_RAW_DATA}, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = ssv_cfgvendor_get_feature_set_matrix, -+ .policy = VENDOR_CMD_RAW_DATA} -+}; -+#else -+static const struct wiphy_vendor_command ssv_vendor_cmds[] = { -+ { -+ { -+ .vendor_id = OUI_SSV, -+ .subcmd = RTK_VENDOR_SCMD_PRIV_STR}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_priv_string_handler -+ }, -+#if defined(GSCAN_SUPPORT) && 0 -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_gscan_get_capabilities -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_SET_CONFIG}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_set_scan_cfg -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_set_batch_scan_cfg -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_initiate_gscan -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_enable_full_scan_result -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_SET_HOTLIST}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_hotlist_cfg -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_significant_change_cfg -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_gscan_get_batch_results -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_gscan_get_channel_list -+ }, -+#endif /* GSCAN_SUPPORT */ -+#if defined(RTT_SUPPORT) && 0 -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = RTT_SUBCMD_SET_CONFIG}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_rtt_set_config -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = RTT_SUBCMD_CANCEL_CONFIG}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_rtt_cancel_config -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = RTT_SUBCMD_GETCAPABILITY}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = wl_cfgvendor_rtt_get_capability -+ }, -+#endif /* RTT_SUPPORT */ -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = ssv_cfgvendor_get_feature_set -+ }, -+ { -+ { -+ .vendor_id = OUI_GOOGLE, -+ .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX}, -+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, -+ .doit = ssv_cfgvendor_get_feature_set_matrix -+ } -+}; -+#endif -+ -+static const struct nl80211_vendor_cmd_info ssv_vendor_events[] = { -+ {OUI_SSV, RTK_VENDOR_EVENT_UNSPEC}, -+ {OUI_SSV, RTK_VENDOR_EVENT_PRIV_STR}, -+#if defined(GSCAN_SUPPORT) && 0 -+ {OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT}, -+ {OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT}, -+ {OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT}, -+ {OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT}, -+#endif /* GSCAN_SUPPORT */ -+#if defined(RTT_SUPPORT) && 0 -+ {OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT}, -+#endif /* RTT_SUPPORT */ -+#if defined(GSCAN_SUPPORT) && 0 -+ {OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT}, -+ {OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT} -+#endif /* GSCAN_SUPPORT */ -+}; -+ -+int ssv_cfgvendor_attach(struct wiphy *wiphy) -+{ -+ -+ dev_info(&wiphy->dev, "register SSV cfg80211 vendor cmd(0x%x) interface\n", -+ NL80211_CMD_VENDOR); -+ -+ wiphy->vendor_commands = ssv_vendor_cmds; -+ wiphy->n_vendor_commands = ARRAY_SIZE(ssv_vendor_cmds); -+ wiphy->vendor_events = ssv_vendor_events; -+ wiphy->n_vendor_events = ARRAY_SIZE(ssv_vendor_events); -+ -+ return 0; -+} -+ -+int ssv_cfgvendor_detach(struct wiphy *wiphy) -+{ -+ dev_info(&wiphy->dev, "unregister SSV cfg80211 vendor interface\n"); -+ -+ wiphy->vendor_commands = NULL; -+ wiphy->vendor_events = NULL; -+ wiphy->n_vendor_commands = 0; -+ wiphy->n_vendor_events = 0; -+ -+ return 0; -+} -+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT) */ -diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h -@@ -0,0 +1,247 @@ -+/****************************************************************************** -+ * -+ * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -+ * -+ * -+ ******************************************************************************/ -+ -+#ifndef _RTW_CFGVENDOR_H_ -+#define _RTW_CFGVENDOR_H_ -+ -+#define OUI_SSV 0x00E04C -+#define OUI_GOOGLE 0x001A11 -+#define ATTRIBUTE_U32_LEN (NLA_HDRLEN + 4) -+#define VENDOR_ID_OVERHEAD ATTRIBUTE_U32_LEN -+#define VENDOR_SUBCMD_OVERHEAD ATTRIBUTE_U32_LEN -+#define VENDOR_DATA_OVERHEAD (NLA_HDRLEN) -+ -+#define SCAN_RESULTS_COMPLETE_FLAG_LEN ATTRIBUTE_U32_LEN -+#define SCAN_INDEX_HDR_LEN (NLA_HDRLEN) -+#define SCAN_ID_HDR_LEN ATTRIBUTE_U32_LEN -+#define SCAN_FLAGS_HDR_LEN ATTRIBUTE_U32_LEN -+#define GSCAN_NUM_RESULTS_HDR_LEN ATTRIBUTE_U32_LEN -+#define GSCAN_RESULTS_HDR_LEN (NLA_HDRLEN) -+#define GSCAN_BATCH_RESULT_HDR_LEN (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \ -+ SCAN_FLAGS_HDR_LEN + \ -+ GSCAN_NUM_RESULTS_HDR_LEN + \ -+ GSCAN_RESULTS_HDR_LEN) -+ -+#define VENDOR_REPLY_OVERHEAD (VENDOR_ID_OVERHEAD + \ -+ VENDOR_SUBCMD_OVERHEAD + \ -+ VENDOR_DATA_OVERHEAD) -+typedef enum { -+ /* don't use 0 as a valid subcommand */ -+ VENDOR_NL80211_SUBCMD_UNSPECIFIED, -+ -+ /* define all vendor startup commands between 0x0 and 0x0FFF */ -+ VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001, -+ VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF, -+ -+ /* define all GScan related commands between 0x1000 and 0x10FF */ -+ ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000, -+ ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF, -+ -+ /* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */ -+ ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100, -+ ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF, -+ -+ /* define all RTT related commands between 0x1100 and 0x11FF */ -+ ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100, -+ ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF, -+ -+ ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200, -+ ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF, -+ -+ ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300, -+ ANDROID_NL80211_SUBCMD_TDLS_RANGE_END = 0x13FF, -+ /* This is reserved for future usage */ -+ -+} ANDROID_VENDOR_SUB_COMMAND; -+ -+enum wl_vendor_subcmd { -+ RTK_VENDOR_SCMD_UNSPEC, -+ RTK_VENDOR_SCMD_PRIV_STR, -+ GSCAN_SUBCMD_GET_CAPABILITIES = -+ ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START, -+ GSCAN_SUBCMD_SET_CONFIG, -+ GSCAN_SUBCMD_SET_SCAN_CONFIG, -+ GSCAN_SUBCMD_ENABLE_GSCAN, -+ GSCAN_SUBCMD_GET_SCAN_RESULTS, -+ GSCAN_SUBCMD_SCAN_RESULTS, -+ GSCAN_SUBCMD_SET_HOTLIST, -+ GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG, -+ GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS, -+ GSCAN_SUBCMD_GET_CHANNEL_LIST, -+ ANDR_WIFI_SUBCMD_GET_FEATURE_SET, -+ ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX, -+ RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START, -+ RTT_SUBCMD_CANCEL_CONFIG, -+ RTT_SUBCMD_GETCAPABILITY, -+ /* Add more sub commands here */ -+ VENDOR_SUBCMD_MAX -+}; -+ -+enum gscan_attributes { -+ GSCAN_ATTRIBUTE_NUM_BUCKETS = 10, -+ GSCAN_ATTRIBUTE_BASE_PERIOD, -+ GSCAN_ATTRIBUTE_BUCKETS_BAND, -+ GSCAN_ATTRIBUTE_BUCKET_ID, -+ GSCAN_ATTRIBUTE_BUCKET_PERIOD, -+ GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS, -+ GSCAN_ATTRIBUTE_BUCKET_CHANNELS, -+ GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN, -+ GSCAN_ATTRIBUTE_REPORT_THRESHOLD, -+ GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE, -+ GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND, -+ -+ GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20, -+ GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, -+ GSCAN_ATTRIBUTE_FLUSH_FEATURE, -+ GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS, -+ GSCAN_ATTRIBUTE_REPORT_EVENTS, -+ /* remaining reserved for additional attributes */ -+ GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30, -+ GSCAN_ATTRIBUTE_FLUSH_RESULTS, -+ GSCAN_ATTRIBUTE_SCAN_RESULTS, /* flat array of wifi_scan_result */ -+ GSCAN_ATTRIBUTE_SCAN_ID, /* indicates scan number */ -+ GSCAN_ATTRIBUTE_SCAN_FLAGS, /* indicates if scan was aborted */ -+ GSCAN_ATTRIBUTE_AP_FLAGS, /* flags on significant change event */ -+ GSCAN_ATTRIBUTE_NUM_CHANNELS, -+ GSCAN_ATTRIBUTE_CHANNEL_LIST, -+ -+ /* remaining reserved for additional attributes */ -+ -+ GSCAN_ATTRIBUTE_SSID = 40, -+ GSCAN_ATTRIBUTE_BSSID, -+ GSCAN_ATTRIBUTE_CHANNEL, -+ GSCAN_ATTRIBUTE_RSSI, -+ GSCAN_ATTRIBUTE_TIMESTAMP, -+ GSCAN_ATTRIBUTE_RTT, -+ GSCAN_ATTRIBUTE_RTTSD, -+ -+ /* remaining reserved for additional attributes */ -+ -+ GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50, -+ GSCAN_ATTRIBUTE_RSSI_LOW, -+ GSCAN_ATTRIBUTE_RSSI_HIGH, -+ GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM, -+ GSCAN_ATTRIBUTE_HOTLIST_FLUSH, -+ -+ /* remaining reserved for additional attributes */ -+ GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60, -+ GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE, -+ GSCAN_ATTRIBUTE_MIN_BREACHING, -+ GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS, -+ GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH, -+ GSCAN_ATTRIBUTE_MAX -+}; -+ -+enum gscan_bucket_attributes { -+ GSCAN_ATTRIBUTE_CH_BUCKET_1, -+ GSCAN_ATTRIBUTE_CH_BUCKET_2, -+ GSCAN_ATTRIBUTE_CH_BUCKET_3, -+ GSCAN_ATTRIBUTE_CH_BUCKET_4, -+ GSCAN_ATTRIBUTE_CH_BUCKET_5, -+ GSCAN_ATTRIBUTE_CH_BUCKET_6, -+ GSCAN_ATTRIBUTE_CH_BUCKET_7 -+}; -+ -+enum gscan_ch_attributes { -+ GSCAN_ATTRIBUTE_CH_ID_1, -+ GSCAN_ATTRIBUTE_CH_ID_2, -+ GSCAN_ATTRIBUTE_CH_ID_3, -+ GSCAN_ATTRIBUTE_CH_ID_4, -+ GSCAN_ATTRIBUTE_CH_ID_5, -+ GSCAN_ATTRIBUTE_CH_ID_6, -+ GSCAN_ATTRIBUTE_CH_ID_7 -+}; -+ -+enum rtt_attributes { -+ RTT_ATTRIBUTE_TARGET_CNT, -+ RTT_ATTRIBUTE_TARGET_INFO, -+ RTT_ATTRIBUTE_TARGET_MAC, -+ RTT_ATTRIBUTE_TARGET_TYPE, -+ RTT_ATTRIBUTE_TARGET_PEER, -+ RTT_ATTRIBUTE_TARGET_CHAN, -+ RTT_ATTRIBUTE_TARGET_MODE, -+ RTT_ATTRIBUTE_TARGET_INTERVAL, -+ RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT, -+ RTT_ATTRIBUTE_TARGET_NUM_PKT, -+ RTT_ATTRIBUTE_TARGET_NUM_RETRY -+}; -+ -+typedef enum wl_vendor_event { -+ RTK_VENDOR_EVENT_UNSPEC, -+ RTK_VENDOR_EVENT_PRIV_STR, -+ GOOGLE_GSCAN_SIGNIFICANT_EVENT, -+ GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT, -+ GOOGLE_GSCAN_BATCH_SCAN_EVENT, -+ GOOGLE_SCAN_FULL_RESULTS_EVENT, -+ GOOGLE_RTT_COMPLETE_EVENT, -+ GOOGLE_SCAN_COMPLETE_EVENT, -+ GOOGLE_GSCAN_GEOFENCE_LOST_EVENT -+} wl_vendor_event_t; -+ -+enum andr_wifi_feature_set_attr { -+ ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, -+ ANDR_WIFI_ATTRIBUTE_FEATURE_SET -+}; -+ -+typedef enum wl_vendor_gscan_attribute { -+ ATTR_START_GSCAN, -+ ATTR_STOP_GSCAN, -+ ATTR_SET_SCAN_BATCH_CFG_ID, /* set batch scan params */ -+ ATTR_SET_SCAN_GEOFENCE_CFG_ID, /* set list of bssids to track */ -+ ATTR_SET_SCAN_SIGNIFICANT_CFG_ID, /* set list of bssids, rssi threshold etc.. */ -+ ATTR_SET_SCAN_CFG_ID, /* set common scan config params here */ -+ ATTR_GET_GSCAN_CAPABILITIES_ID, -+ /* Add more sub commands here */ -+ ATTR_GSCAN_MAX -+} wl_vendor_gscan_attribute_t; -+ -+typedef enum gscan_batch_attribute { -+ ATTR_GSCAN_BATCH_BESTN, -+ ATTR_GSCAN_BATCH_MSCAN, -+ ATTR_GSCAN_BATCH_BUFFER_THRESHOLD -+} gscan_batch_attribute_t; -+ -+typedef enum gscan_geofence_attribute { -+ ATTR_GSCAN_NUM_HOTLIST_BSSID, -+ ATTR_GSCAN_HOTLIST_BSSID -+} gscan_geofence_attribute_t; -+ -+typedef enum gscan_complete_event { -+ WIFI_SCAN_BUFFER_FULL, -+ WIFI_SCAN_COMPLETE -+} gscan_complete_event_t; -+ -+/* Capture the RTK_VENDOR_SUBCMD_PRIV_STRINGS* here */ -+#define RTK_VENDOR_SCMD_CAPA "cap" -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT) -+extern int ssv_cfgvendor_attach(struct wiphy *wiphy); -+extern int ssv_cfgvendor_detach(struct wiphy *wiphy); -+extern int ssv_cfgvendor_send_async_event(struct wiphy *wiphy, -+ struct net_device *dev, int event_id, -+ const void *data, int len); -+#if defined(GSCAN_SUPPORT) && 0 -+extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, -+ struct net_device *dev, void *data, -+ int len, wl_vendor_event_t event); -+#endif -+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */ -+ -+#endif /* _RTW_CFGVENDOR_H_ */ -diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c -@@ -0,0 +1,546 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include "dev.h" -+#include "ssv_ht_rc.h" -+#include "ssv_rc.h" -+#define SAMPLE_COUNT 4 -+#define HT_CW_MIN 15 -+#define HT_SEGMENT_SIZE 6000 -+#define AVG_PKT_SIZE 12000 -+#define SAMPLE_COLUMNS 10 -+#define EWMA_LEVEL 75 -+#define MCS_NBITS (AVG_PKT_SIZE << 3) -+#define MCS_NSYMS(bps) ((MCS_NBITS + (bps) - 1) / (bps)) -+#define MCS_SYMBOL_TIME(sgi,syms) \ -+ (sgi ? \ -+ ((syms) * 18 + 4) / 5 : \ -+ (syms) << 2 \ -+ ) -+#define MCS_DURATION(streams,sgi,bps) MCS_SYMBOL_TIME(sgi, MCS_NSYMS((streams) * (bps))) -+#define MCS_GROUP(_streams,_sgi,_ht40) { \ -+ .duration = { \ -+ MCS_DURATION(_streams, _sgi, _ht40 ? 54 : 26), \ -+ MCS_DURATION(_streams, _sgi, _ht40 ? 108 : 52), \ -+ MCS_DURATION(_streams, _sgi, _ht40 ? 162 : 78), \ -+ MCS_DURATION(_streams, _sgi, _ht40 ? 216 : 104), \ -+ MCS_DURATION(_streams, _sgi, _ht40 ? 324 : 156), \ -+ MCS_DURATION(_streams, _sgi, _ht40 ? 432 : 208), \ -+ MCS_DURATION(_streams, _sgi, _ht40 ? 486 : 234), \ -+ MCS_DURATION(_streams, _sgi, _ht40 ? 540 : 260) \ -+ } \ -+} -+const struct mcs_group minstrel_mcs_groups_ssv[] = { -+ MCS_GROUP(1, 0, 0), -+ MCS_GROUP(1, 1, 0), -+}; -+ -+const u16 ampdu_max_transmit_length[RATE_TABLE_SIZE] = { -+ 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200, -+ 5100, 10200, 15400, 20500, 30800, 41100, 46200, 51300, -+ 4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200 -+}; -+ -+static u8 sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES]; -+static int minstrel_ewma(int old, int new, int weight) -+{ -+ return (new * (100 - weight) + old * weight) / 100; -+} -+ -+static inline struct minstrel_rate_stats *minstrel_get_ratestats(struct -+ ssv62xx_ht *mi, -+ int index) -+{ -+ return &mi->groups.rates[index % MCS_GROUP_RATES]; -+} -+ -+static void minstrel_calc_rate_ewma(struct minstrel_rate_stats *mr) -+{ -+ if (unlikely(mr->attempts > 0)) { -+ mr->sample_skipped = 0; -+ mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts); -+ if (!mr->att_hist) -+ mr->probability = mr->cur_prob; -+ else -+ mr->probability = minstrel_ewma(mr->probability, -+ mr->cur_prob, -+ EWMA_LEVEL); -+ mr->att_hist += mr->attempts; -+ mr->succ_hist += mr->success; -+ } else { -+ mr->sample_skipped++; -+ } -+ mr->last_success = mr->success; -+ mr->last_attempts = mr->attempts; -+ mr->success = 0; -+ mr->attempts = 0; -+} -+ -+static void minstrel_ht_calc_tp(struct ssv62xx_ht *mi, -+ struct ssv_sta_rc_info *rc_sta, int rate) -+{ -+ struct minstrel_rate_stats *mr; -+ unsigned int usecs, group_id; -+ if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20) -+ group_id = 0; -+ else -+ group_id = 1; -+ mr = &mi->groups.rates[rate]; -+ if (mr->probability < MINSTREL_FRAC(1, 10)) { -+ mr->cur_tp = 0; -+ return; -+ } -+ usecs = mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len); -+ usecs += minstrel_mcs_groups_ssv[group_id].duration[rate]; -+ mr->cur_tp = MINSTREL_TRUNC((1000000 / usecs) * mr->probability); -+} -+ -+static void rate_control_ht_sample(struct ssv62xx_ht *mi, -+ struct ssv_sta_rc_info *rc_sta) -+{ -+ struct minstrel_mcs_group_data *mg; -+ struct minstrel_rate_stats *mr; -+ int cur_prob, cur_prob_tp, cur_tp, cur_tp2; -+ int i, index; -+ if (mi->ampdu_packets > 0) { -+ mi->avg_ampdu_len = minstrel_ewma(mi->avg_ampdu_len, -+ MINSTREL_FRAC(mi->ampdu_len, -+ mi-> -+ ampdu_packets), -+ EWMA_LEVEL); -+ mi->ampdu_len = 0; -+ mi->ampdu_packets = 0; -+ } else -+ return; -+ mi->sample_slow = 0; -+ mi->sample_count = 0; -+ { -+ cur_prob = 0; -+ cur_prob_tp = 0; -+ cur_tp = 0; -+ cur_tp2 = 0; -+ mg = &mi->groups; -+ mg->max_tp_rate = 0; -+ mg->max_tp_rate2 = 0; -+ mg->max_prob_rate = 0; -+ for (i = 0; i < MCS_GROUP_RATES; i++) { -+ if (!(rc_sta->ht_supp_rates & BIT(i))) -+ continue; -+ mr = &mg->rates[i]; -+ index = i; -+ minstrel_calc_rate_ewma(mr); -+ minstrel_ht_calc_tp(mi, rc_sta, i); -+#ifdef RATE_CONTROL_HT_PARAMETER_DEBUG -+ if (mr->cur_prob) -+ pr_debug -+ ("rate[%d]probability[%08d]cur_prob[%08d]TP[%04d]\n", -+ i, mr->probability, mr->cur_prob, -+ mr->cur_tp); -+#endif -+#ifdef RATE_CONTROL_HT_STUPID_DEBUG -+ pr_debug -+ ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n", -+ mg->max_tp_rate, mg->max_tp_rate2, -+ mg->max_prob_rate); -+ pr_debug("rate[%d]probability[%08d]TP[%d]\n", i, -+ mr->probability, mr->cur_tp); -+#endif -+ if (!mr->cur_tp) -+ continue; -+#ifdef RATE_CONTROL_HT_STUPID_DEBUG -+ pr_debug("HT--1 mr->cur_tp[%d]cur_prob_tp[%d]\n", -+ mr->cur_tp, cur_prob_tp); -+#endif -+ if ((mr->cur_tp > cur_prob_tp && mr->probability > -+ MINSTREL_FRAC(3, 4)) -+ || mr->probability > cur_prob) { -+ mg->max_prob_rate = index; -+ cur_prob = mr->probability; -+ cur_prob_tp = mr->cur_tp; -+ } -+#ifdef RATE_CONTROL_HT_STUPID_DEBUG -+ pr_debug("HT--2 mr->cur_tp[%d]cur_tp[%d]\n", mr->cur_tp, -+ cur_tp); -+#endif -+ if (mr->cur_tp > cur_tp) { -+ swap(index, mg->max_tp_rate); -+ cur_tp = mr->cur_tp; -+ mr = minstrel_get_ratestats(mi, index); -+ } -+#ifdef RATE_CONTROL_HT_STUPID_DEBUG -+ if (index != i) -+ pr_debug -+ ("HT--3 index[%d]i[%d]mg->max_tp_rate[%d]\n", -+ index, i, mg->max_tp_rate); -+#endif -+ if (index >= mg->max_tp_rate) -+ continue; -+#ifdef RATE_CONTROL_HT_STUPID_DEBUG -+ if (index != i) -+ pr_debug("HT--4 mr->cur_tp[%d]cur_tp2[%d]\n", -+ mr->cur_tp, cur_tp2); -+#endif -+ if (mr->cur_tp > cur_tp2) { -+ mg->max_tp_rate2 = index; -+ cur_tp2 = mr->cur_tp; -+ } -+ } -+ } -+ mi->sample_count = SAMPLE_COUNT; -+ mi->max_tp_rate = mg->max_tp_rate; -+ mi->max_tp_rate2 = mg->max_tp_rate2; -+ mi->max_prob_rate = mg->max_prob_rate; -+#ifdef RATE_CONTROL_HT_STUPID_DEBUG -+ pr_debug -+ ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n", -+ mi->max_tp_rate, mi->max_tp_rate2, mi->max_prob_rate); -+#endif -+ mi->stats_update = jiffies; -+} -+ -+static void minstrel_ht_set_rate(struct ssv62xx_ht *mi, -+ struct fw_rc_retry_params *rate, int index, -+ bool sample, bool rtscts, -+ struct ssv_sta_rc_info *rc_sta, -+ struct ssv_rate_ctrl *ssv_rc) -+{ -+ struct minstrel_rate_stats *mr; -+ mr = minstrel_get_ratestats(mi, index); -+ rate->drate = ssv_rc->rc_table[mr->rc_index].hw_rate_idx; -+ rate->crate = ssv_rc->rc_table[mr->rc_index].ctrl_rate_idx; -+} -+ -+static inline int minstrel_get_duration(int index, -+ struct ssv_sta_rc_info *rc_sta) -+{ -+ unsigned int group_id; -+ const struct mcs_group *group; -+ if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20) -+ group_id = 0; -+ else -+ group_id = 1; -+ group = &minstrel_mcs_groups_ssv[group_id]; -+ return group->duration[index % MCS_GROUP_RATES]; -+} -+ -+static void minstrel_next_sample_idx(struct ssv62xx_ht *mi) -+{ -+ struct minstrel_mcs_group_data *mg; -+ for (;;) { -+ mg = &mi->groups; -+ if (++mg->index >= MCS_GROUP_RATES) { -+ mg->index = 0; -+ if (++mg->column >= ARRAY_SIZE(sample_table)) -+ mg->column = 0; -+ } -+ break; -+ } -+} -+ -+static int minstrel_get_sample_rate(struct ssv62xx_ht *mi, -+ struct ssv_sta_rc_info *rc_sta) -+{ -+ struct minstrel_rate_stats *mr; -+ struct minstrel_mcs_group_data *mg; -+ int sample_idx = 0; -+ if (mi->sample_wait > 0) { -+ mi->sample_wait--; -+ return -1; -+ } -+ if (!mi->sample_tries) -+ return -1; -+ mi->sample_tries--; -+ mg = &mi->groups; -+ sample_idx = sample_table[mg->column][mg->index]; -+ mr = &mg->rates[sample_idx]; -+ minstrel_next_sample_idx(mi); -+ if (minstrel_get_duration(sample_idx, rc_sta) > -+ minstrel_get_duration(mi->max_tp_rate, rc_sta)) { -+ if (mr->sample_skipped < 20) { -+ return -1; -+ } -+ if (mi->sample_slow++ > 2) { -+ return -1; -+ } -+ } -+ return sample_idx; -+} -+ -+static void _fill_txinfo_rates(struct ssv_rate_ctrl *ssv_rc, -+ struct sk_buff *skb, -+ struct fw_rc_retry_params *ar) -+{ -+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); -+ info->control.rates[0].idx = -+ ssv_rc->rc_table[ar[0].drate].dot11_rate_idx; -+ info->control.rates[0].count = 1; -+ info->control.rates[SSV_DRATE_IDX].count = ar[0].drate; -+ info->control.rates[SSV_CRATE_IDX].count = ar[0].crate; -+} -+ -+extern const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13]; -+s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc, -+ struct fw_rc_retry_params *ar) -+{ -+ struct ssv_rate_ctrl *ssv_rc = sc->rc; -+ struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head; -+ struct ieee80211_sta *sta = skb_info->sta; -+ struct ssv62xx_ht *mi = NULL; -+ int sample_idx; -+ bool sample = false; -+ struct ssv_sta_rc_info *rc_sta; -+ struct ssv_sta_priv_data *sta_priv; -+ struct rc_pid_sta_info *spinfo; -+ int ret = 0; -+ if (sc->sc_flags & SC_OP_FIXED_RATE) { -+ ar[0].count = 3; -+ ar[0].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx; -+ ar[0].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx; -+ ar[1].count = 2; -+ ar[1].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx; -+ ar[1].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx; -+ ar[2].count = 2; -+ ar[2].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx; -+ ar[2].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx; -+ _fill_txinfo_rates(ssv_rc, skb, ar); -+ return ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx; -+ } -+ if (sta == NULL) { -+ dev_err(sc->dev, "Station NULL\n"); -+ BUG_ON(1); -+ } -+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx]; -+ spinfo = &rc_sta->spinfo; -+ if ((rc_sta->rc_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) -+ || (rc_sta->rc_wsid < 0)) { -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ int rateidx = 99; -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ { -+ if ((rc_sta->ht_rc_type >= RC_TYPE_HT_SGI_20) && -+ (ssv_sta_priv->rx_data_rate < -+ SSV62XX_RATE_MCS_INDEX)) { -+ if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0] -+ == 12) -+ rateidx = -+ (int)rc_sta->pinfo.rinfo[4]. -+ rc_index; -+ else -+ rateidx = -+ (int)rc_sta->pinfo.rinfo[0]. -+ rc_index; -+ } else { -+ rateidx = (int)ssv_sta_priv->rx_data_rate; -+ rateidx -= SSV62XX_RATE_MCS_INDEX; -+ rateidx %= 8; -+ if (rc_sta->ht_rc_type == RC_TYPE_HT_SGI_20) -+ rateidx += SSV62XX_RATE_MCS_SGI_INDEX; -+ else if (rc_sta->ht_rc_type == -+ RC_TYPE_HT_LGI_20) -+ rateidx += SSV62XX_RATE_MCS_LGI_INDEX; -+ else -+ rateidx += -+ SSV62XX_RATE_MCS_GREENFIELD_INDEX; -+ } -+ } -+ ar[0].count = 3; -+ ar[2].drate = ar[1].drate = ar[0].drate = -+ ssv_rc->rc_table[rateidx].hw_rate_idx; -+ ar[2].crate = ar[1].crate = ar[0].crate = -+ ssv_rc->rc_table[rateidx].ctrl_rate_idx; -+ ar[1].count = 2; -+ ar[2].count = 2; -+ _fill_txinfo_rates(ssv_rc, skb, ar); -+ return rateidx; -+ } -+ mi = &rc_sta->ht; -+ sample_idx = minstrel_get_sample_rate(mi, rc_sta); -+ if (sample_idx >= 0) { -+ sample = true; -+ minstrel_ht_set_rate(mi, &ar[0], sample_idx, -+ true, false, rc_sta, ssv_rc); -+ } else { -+ minstrel_ht_set_rate(mi, &ar[0], mi->max_tp_rate, -+ false, false, rc_sta, ssv_rc); -+ } -+ ar[0].count = mi->first_try_count; -+ ret = ar[0].drate; -+ { -+ if (sample_idx >= 0) -+ minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate, -+ false, false, rc_sta, ssv_rc); -+ else -+ minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate2, -+ false, true, rc_sta, ssv_rc); -+ ar[1].count = mi->second_try_count; -+ if (ret > ar[1].drate) -+ ret = ar[1].drate; -+ minstrel_ht_set_rate(mi, &ar[2], mi->max_prob_rate, -+ false, !sample, rc_sta, ssv_rc); -+ ar[2].count = mi->other_try_count; -+ if (ret > ar[2].drate) -+ ret = ar[2].drate; -+ } -+ mi->total_packets++; -+ if (mi->total_packets == ~0) { -+ mi->total_packets = 0; -+ mi->sample_packets = 0; -+ } -+ if (spinfo->real_hw_index < SSV62XX_RATE_MCS_INDEX) -+ return spinfo->real_hw_index; -+ _fill_txinfo_rates(ssv_rc, skb, ar); -+ return ret; -+} -+ -+static void init_sample_table(void) -+{ -+ int col, i, new_idx; -+ u8 rnd[MCS_GROUP_RATES]; -+ memset(sample_table, 0xff, sizeof(sample_table)); -+ for (col = 0; col < SAMPLE_COLUMNS; col++) { -+ for (i = 0; i < MCS_GROUP_RATES; i++) { -+ get_random_bytes(rnd, sizeof(rnd)); -+ new_idx = (i + rnd[i]) % MCS_GROUP_RATES; -+ while (sample_table[col][new_idx] != 0xff) -+ new_idx = (new_idx + 1) % MCS_GROUP_RATES; -+ sample_table[col][new_idx] = i; -+ } -+ } -+} -+ -+void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13], -+ struct ssv_sta_rc_info *rc_sta) -+{ -+ struct ssv62xx_ht *mi = &rc_sta->ht; -+ int ack_dur; -+ int i; -+ unsigned int group_id; -+ if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20) -+ group_id = 0; -+ else -+ group_id = 1; -+ for (i = 0; i < MCS_GROUP_RATES; i++) { -+ pr_debug("[RC]HT duration[%d][%d]\n", i, -+ minstrel_mcs_groups_ssv[group_id].duration[i]); -+ } -+ init_sample_table(); -+ memset(mi, 0, sizeof(*mi)); -+ mi->stats_update = jiffies; -+ ack_dur = pide_frame_duration(10, 60, 0, 0); -+ mi->overhead = pide_frame_duration(0, 60, 0, 0) + ack_dur; -+ mi->overhead_rtscts = mi->overhead + 2 * ack_dur; -+ mi->avg_ampdu_len = MINSTREL_FRAC(1, 1); -+ mi->sample_count = 16; -+ mi->sample_wait = 0; -+ mi->sample_tries = 4; -+#ifdef DISABLE_RATE_CONTROL_SAMPLE -+ mi->max_tp_rate = MCS_GROUP_RATES - 1; -+ mi->max_tp_rate2 = MCS_GROUP_RATES - 1; -+ mi->max_prob_rate = MCS_GROUP_RATES - 1; -+#endif -+#if (HW_MAX_RATE_TRIES == 7) -+ { -+ mi->first_try_count = 3; -+ mi->second_try_count = 2; -+ mi->other_try_count = 2; -+ } -+#else -+ { -+ mi->first_try_count = 2; -+ mi->second_try_count = 1; -+ mi->other_try_count = 1; -+ } -+#endif -+ for (i = 0; i < MCS_GROUP_RATES; i++) { -+ mi->groups.rates[i].rc_index = -+ ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][i + 1]; -+ } -+} -+ -+static bool minstrel_ht_txstat_valid(struct ssv62xx_tx_rate *rate) -+{ -+ if (!rate->count) -+ return false; -+ if (rate->data_rate < 0) -+ return false; -+ return true; -+} -+ -+void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb, -+ struct ssv_sta_rc_info *rc_sta) -+{ -+ struct cfg_host_event *host_event; -+ struct firmware_rate_control_report_data *report_data; -+ struct ssv62xx_ht *mi; -+ struct minstrel_rate_stats *rate; -+ bool last = false; -+ int i = 0; -+ u16 report_ampdu_packets = 0; -+ unsigned long period; -+ host_event = (struct cfg_host_event *)skb->data; -+ report_data = -+ (struct firmware_rate_control_report_data *)&host_event->dat[0]; -+ if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) { -+ report_ampdu_packets = 1; -+ } else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) { -+ report_data->ampdu_len = 1; -+ report_ampdu_packets = report_data->ampdu_len; -+ } else { -+ dev_warn(sc->dev, "rate control report handler got garbage\n"); -+ return; -+ } -+ mi = &rc_sta->ht; -+ mi->ampdu_packets += report_ampdu_packets; -+ mi->ampdu_len += report_data->ampdu_len; -+ if (!mi->sample_wait && !mi->sample_tries && mi->sample_count > 0) { -+ mi->sample_wait = 16 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len); -+ mi->sample_tries = 2; -+ mi->sample_count--; -+ } -+ for (i = 0; !last; i++) { -+ last = (i == SSV62XX_TX_MAX_RATES - 1) || -+ !minstrel_ht_txstat_valid(&report_data->rates[i + 1]); -+ if (!minstrel_ht_txstat_valid(&report_data->rates[i])) -+ break; -+#ifdef RATE_CONTROL_DEBUG -+ if ((report_data->rates[i].data_rate < SSV62XX_RATE_MCS_INDEX) -+ || (report_data->rates[i].data_rate >= -+ SSV62XX_RATE_MCS_GREENFIELD_INDEX)) { -+ dev_dbg -+ (sc->dev, "[RC]ssv6xxx_ht_report_handler get error report rate[%d]\n", -+ report_data->rates[i].data_rate); -+ break; -+ } -+#endif -+ rate = -+ &mi->groups. -+ rates[(report_data->rates[i].data_rate - -+ SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES]; -+ if (last) -+ rate->success += report_data->ampdu_ack_len; -+ rate->attempts += -+ report_data->rates[i].count * report_data->ampdu_len; -+ } -+ period = msecs_to_jiffies(SSV_RC_HT_INTERVAL / 2); -+ if (time_after(jiffies, mi->stats_update + period)) { -+ rate_control_ht_sample(mi, rc_sta); -+ } -+} -diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h -@@ -0,0 +1,31 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV_RC_HT_H_ -+#define _SSV_RC_HT_H_ -+#include "ssv_rc_common.h" -+#define MINSTREL_SCALE 16 -+#define MINSTREL_FRAC(val,div) (((val) << MINSTREL_SCALE) / div) -+#define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE) -+#define SSV_RC_HT_INTERVAL 100 -+extern const u16 ampdu_max_transmit_length[]; -+s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc, -+ struct fw_rc_retry_params *ar); -+void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13], -+ struct ssv_sta_rc_info *rc_sta); -+void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb, -+ struct ssv_sta_rc_info *rc_sta); -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.c b/drivers/net/wireless/ssv6051/smac/ssv_pm.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.c -@@ -0,0 +1,19 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include "dev.h" -+#include "sar.h" -diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.h b/drivers/net/wireless/ssv6051/smac/ssv_pm.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.h -@@ -0,0 +1,20 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV_PM_H_ -+#define _SSV_PM_H_ -+#include -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_rc.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.c -@@ -0,0 +1,1716 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include "dev.h" -+#include "ssv_ht_rc.h" -+#include "ssv_rc.h" -+#include "ssv_rc_common.h" -+static struct ssv_rc_rate ssv_11bgn_rate_table[] = { -+ [0] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_CCK, -+ .rate_kbps = 1000, -+ .dot11_rate_idx = 0, -+ .ctrl_rate_idx = 0, -+ .hw_rate_idx = 0, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [1] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_CCK, -+ .rate_kbps = 2000, -+ .dot11_rate_idx = 1, -+ .ctrl_rate_idx = 1, -+ .hw_rate_idx = 1, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [2] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_CCK, -+ .rate_kbps = 5500, -+ .dot11_rate_idx = 2, -+ .ctrl_rate_idx = 1, -+ .hw_rate_idx = 2, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [3] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_CCK, -+ .rate_kbps = 11000, -+ .dot11_rate_idx = 3, -+ .ctrl_rate_idx = 1, -+ .hw_rate_idx = 3, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [4] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE, -+ .phy_type = WLAN_RC_PHY_CCK, -+ .rate_kbps = 2000, -+ .dot11_rate_idx = 1, -+ .ctrl_rate_idx = 4, -+ .hw_rate_idx = 4, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [5] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE, -+ .phy_type = WLAN_RC_PHY_CCK, -+ .rate_kbps = 5500, -+ .dot11_rate_idx = 2, -+ .ctrl_rate_idx = 4, -+ .hw_rate_idx = 5, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [6] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE, -+ .phy_type = WLAN_RC_PHY_CCK, -+ .rate_kbps = 11000, -+ .dot11_rate_idx = 3, -+ .ctrl_rate_idx = 4, -+ .hw_rate_idx = 6, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [7] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_OFDM, -+ .rate_kbps = 6000, -+ .dot11_rate_idx = 4, -+ .ctrl_rate_idx = 7, -+ .hw_rate_idx = 7, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [8] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_OFDM, -+ .rate_kbps = 9000, -+ .dot11_rate_idx = 5, -+ .ctrl_rate_idx = 7, -+ .hw_rate_idx = 8, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [9] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_OFDM, -+ .rate_kbps = 12000, -+ .dot11_rate_idx = 6, -+ .ctrl_rate_idx = 9, -+ .hw_rate_idx = 9, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [10] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_OFDM, -+ .rate_kbps = 18000, -+ .dot11_rate_idx = 7, -+ .ctrl_rate_idx = 9, -+ .hw_rate_idx = 10, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [11] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_OFDM, -+ .rate_kbps = 24000, -+ .dot11_rate_idx = 8, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 11, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [12] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_OFDM, -+ .rate_kbps = 36000, -+ .dot11_rate_idx = 9, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 12, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [13] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_OFDM, -+ .rate_kbps = 48000, -+ .dot11_rate_idx = 10, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 13, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [14] = {.rc_flags = RC_FLAG_LEGACY, -+ .phy_type = WLAN_RC_PHY_OFDM, -+ .rate_kbps = 54000, -+ .dot11_rate_idx = 11, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 14, -+ .arith_shift = 8, -+ .target_pf = 8}, -+ [15] = {.rc_flags = RC_FLAG_HT, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI, -+ .rate_kbps = 6500, -+ .dot11_rate_idx = 0, -+ .ctrl_rate_idx = 7, -+ .hw_rate_idx = 15, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [16] = {.rc_flags = RC_FLAG_HT, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI, -+ .rate_kbps = 13000, -+ .dot11_rate_idx = 1, -+ .ctrl_rate_idx = 9, -+ .hw_rate_idx = 16, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [17] = {.rc_flags = RC_FLAG_HT, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI, -+ .rate_kbps = 19500, -+ .dot11_rate_idx = 2, -+ .ctrl_rate_idx = 9, -+ .hw_rate_idx = 17, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [18] = {.rc_flags = RC_FLAG_HT, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI, -+ .rate_kbps = 26000, -+ .dot11_rate_idx = 3, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 18, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [19] = {.rc_flags = RC_FLAG_HT, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI, -+ .rate_kbps = 39000, -+ .dot11_rate_idx = 4, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 19, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [20] = {.rc_flags = RC_FLAG_HT, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI, -+ .rate_kbps = 52000, -+ .dot11_rate_idx = 5, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 20, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [21] = {.rc_flags = RC_FLAG_HT, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI, -+ .rate_kbps = 58500, -+ .dot11_rate_idx = 6, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 21, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [22] = {.rc_flags = RC_FLAG_HT, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI, -+ .rate_kbps = 65000, -+ .dot11_rate_idx = 7, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 22, -+ .arith_shift = 8, -+ .target_pf = 8}, -+ [23] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI, -+ .rate_kbps = 7200, -+ .dot11_rate_idx = 0, -+ .ctrl_rate_idx = 7, -+ .hw_rate_idx = 23, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [24] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI, -+ .rate_kbps = 14400, -+ .dot11_rate_idx = 1, -+ .ctrl_rate_idx = 9, -+ .hw_rate_idx = 24, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [25] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI, -+ .rate_kbps = 21700, -+ .dot11_rate_idx = 2, -+ .ctrl_rate_idx = 9, -+ .hw_rate_idx = 25, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [26] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI, -+ .rate_kbps = 28900, -+ .dot11_rate_idx = 3, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 26, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [27] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI, -+ .rate_kbps = 43300, -+ .dot11_rate_idx = 4, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 27, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [28] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI, -+ .rate_kbps = 57800, -+ .dot11_rate_idx = 5, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 28, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [29] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI, -+ .rate_kbps = 65000, -+ .dot11_rate_idx = 6, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 29, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [30] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI, -+ .rate_kbps = 72200, -+ .dot11_rate_idx = 7, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 30, -+ .arith_shift = 8, -+ .target_pf = 8}, -+ [31] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF, -+ .rate_kbps = 6500, -+ .dot11_rate_idx = 0, -+ .ctrl_rate_idx = 7, -+ .hw_rate_idx = 31, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [32] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF, -+ .rate_kbps = 13000, -+ .dot11_rate_idx = 1, -+ .ctrl_rate_idx = 9, -+ .hw_rate_idx = 32, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [33] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF, -+ .rate_kbps = 19500, -+ .dot11_rate_idx = 2, -+ .ctrl_rate_idx = 9, -+ .hw_rate_idx = 33, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [34] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF, -+ .rate_kbps = 26000, -+ .dot11_rate_idx = 3, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 34, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [35] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF, -+ .rate_kbps = 39000, -+ .dot11_rate_idx = 4, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 35, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [36] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF, -+ .rate_kbps = 52000, -+ .dot11_rate_idx = 5, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 36, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [37] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF, -+ .rate_kbps = 58500, -+ .dot11_rate_idx = 6, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 37, -+ .arith_shift = 8, -+ .target_pf = 26, -+ }, -+ [38] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF, -+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF, -+ .rate_kbps = 65000, -+ .dot11_rate_idx = 7, -+ .ctrl_rate_idx = 11, -+ .hw_rate_idx = 38, -+ .arith_shift = 8, -+ .target_pf = 8}, -+}; -+ -+const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13] = { -+ [RC_TYPE_B_ONLY] = {4, 0, 1, 2, 3}, -+ [RC_TYPE_LEGACY_GB] = {12, 0, 1, 2, 7, 8, 3, 9, 10, 11, 12, 13, 14}, -+ [RC_TYPE_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30}, -+ [RC_TYPE_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22}, -+ [RC_TYPE_HT_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30}, -+ [RC_TYPE_HT_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22}, -+ [RC_TYPE_HT_GF] = {8, 31, 32, 33, 34, 35, 36, 37, 38}, -+}; -+ -+static u32 ssv6xxx_rate_supported(struct ssv_sta_rc_info *rc_sta, u32 index) -+{ -+ return (rc_sta->rc_supp_rates & BIT(index)); -+} -+ -+static u8 ssv6xxx_rate_lowest_index(struct ssv_sta_rc_info *rc_sta) -+{ -+ int i; -+ for (i = 0; i < rc_sta->rc_num_rate; i++) -+ if (ssv6xxx_rate_supported(rc_sta, i)) -+ return i; -+ return 0; -+} -+ -+#ifdef DISABLE_RATE_CONTROL_SAMPLE -+static u8 ssv6xxx_rate_highest_index(struct ssv_sta_rc_info *rc_sta) -+{ -+ int i; -+ for (i = rc_sta->rc_num_rate - 1; i >= 0; i--) -+ if (ssv6xxx_rate_supported(rc_sta, i)) -+ return i; -+ return 0; -+} -+#endif -+static void rate_control_pid_adjust_rate(struct ssv_sta_rc_info *rc_sta, -+ struct rc_pid_sta_info *spinfo, -+ int adj, struct rc_pid_rateinfo *rinfo) -+{ -+ int cur_sorted, new_sorted, probe, tmp, n_bitrates; -+ int cur = spinfo->txrate_idx; -+ n_bitrates = rc_sta->rc_num_rate; -+ cur_sorted = rinfo[cur].index; -+ new_sorted = cur_sorted + adj; -+ if (new_sorted < 0) -+ new_sorted = rinfo[0].index; -+ else if (new_sorted >= n_bitrates) -+ new_sorted = rinfo[n_bitrates - 1].index; -+ tmp = new_sorted; -+ if (adj < 0) { -+ for (probe = cur_sorted; probe >= new_sorted; probe--) -+ if (rinfo[probe].diff <= rinfo[cur_sorted].diff && -+ ssv6xxx_rate_supported(rc_sta, rinfo[probe].index)) -+ tmp = probe; -+ } else { -+ for (probe = new_sorted + 1; probe < n_bitrates; probe++) -+ if (rinfo[probe].diff <= rinfo[new_sorted].diff && -+ ssv6xxx_rate_supported(rc_sta, rinfo[probe].index)) -+ tmp = probe; -+ } -+ BUG_ON(tmp < 0 || tmp >= n_bitrates); -+ do { -+ if (ssv6xxx_rate_supported(rc_sta, rinfo[tmp].index)) { -+ spinfo->tmp_rate_idx = rinfo[tmp].index; -+ break; -+ } -+ if (adj < 0) -+ tmp--; -+ else -+ tmp++; -+ } while (tmp < n_bitrates && tmp >= 0); -+ spinfo->oldrate = spinfo->txrate_idx; -+ if (spinfo->tmp_rate_idx != spinfo->txrate_idx) { -+ spinfo->monitoring = 1; -+#ifdef RATE_CONTROL_PARAMETER_DEBUG -+ pr_debug("Trigger monitor tmp_rate_idx=[%d]\n", -+ spinfo->tmp_rate_idx); -+#endif -+ spinfo->probe_cnt = MAXPROBES; -+ } -+} -+ -+static void rate_control_pid_normalize(struct rc_pid_info *pinfo, int l) -+{ -+ int i, norm_offset = RC_PID_NORM_OFFSET; -+ struct rc_pid_rateinfo *r = pinfo->rinfo; -+ if (r[0].diff > norm_offset) -+ r[0].diff -= norm_offset; -+ else if (r[0].diff < -norm_offset) -+ r[0].diff += norm_offset; -+ for (i = 0; i < l - 1; i++) -+ if (r[i + 1].diff > r[i].diff + norm_offset) -+ r[i + 1].diff -= norm_offset; -+ else if (r[i + 1].diff <= r[i].diff) -+ r[i + 1].diff += norm_offset; -+} -+ -+#ifdef RATE_CONTROL_DEBUG -+unsigned int txrate_dlr = 0; -+#endif -+static void rate_control_pid_sample(struct ssv_rate_ctrl *ssv_rc, -+ struct rc_pid_info *pinfo, -+ struct ssv_sta_rc_info *rc_sta, -+ struct rc_pid_sta_info *spinfo) -+{ -+ struct rc_pid_rateinfo *rinfo = pinfo->rinfo; -+ u8 pf; -+ s32 err_avg; -+ s32 err_prop; -+ s32 err_int; -+ s32 err_der; -+ int adj, i, j, tmp; -+ struct ssv_rc_rate *rc_table; -+ unsigned int dlr; -+ unsigned int perfect_time = 0; -+ unsigned int this_thp, ewma_thp; -+ struct rc_pid_rateinfo *rate; -+ if (!spinfo->monitoring) { -+ if (spinfo->tx_num_xmit == 0) -+ return; -+ spinfo->last_sample = jiffies; -+ pf = spinfo->tx_num_failed * 100 / spinfo->tx_num_xmit; -+ if (pinfo->rinfo[spinfo->txrate_idx].this_attempt > 0) { -+ rate = &pinfo->rinfo[spinfo->txrate_idx]; -+ rc_table = &ssv_rc->rc_table[spinfo->txrate_idx]; -+ dlr = 100 - rate->this_fail * 100 / rate->this_attempt; -+ perfect_time = rate->perfect_tx_time; -+ if (!perfect_time) -+ perfect_time = 1000000; -+ this_thp = dlr * (1000000 / perfect_time); -+ ewma_thp = rate->throughput; -+ if (ewma_thp == 0) -+ rate->throughput = this_thp; -+ else -+ rate->throughput = (ewma_thp + this_thp) >> 1; -+ rate->attempt += rate->this_attempt; -+ rate->success += rate->this_success; -+ rate->fail += rate->this_fail; -+ spinfo->tx_num_xmit = 0; -+ spinfo->tx_num_failed = 0; -+ rate->this_fail = 0; -+ rate->this_success = 0; -+ rate->this_attempt = 0; -+ if (pinfo->oldrate < 0 -+ || pinfo->oldrate >= rc_sta->rc_num_rate) { -+ WARN_ON(1); -+ } -+ if (spinfo->txrate_idx < 0 -+ || spinfo->txrate_idx >= rc_sta->rc_num_rate) { -+ WARN_ON(1); -+ } -+ if (pinfo->oldrate != spinfo->txrate_idx) { -+ i = rinfo[pinfo->oldrate].index; -+ j = rinfo[spinfo->txrate_idx].index; -+ tmp = (pf - spinfo->last_pf); -+ tmp = -+ RC_PID_DO_ARITH_RIGHT_SHIFT(tmp, -+ rc_table->arith_shift); -+ rinfo[j].diff = rinfo[i].diff + tmp; -+ pinfo->oldrate = spinfo->txrate_idx; -+ } -+ rate_control_pid_normalize(pinfo, rc_sta->rc_num_rate); -+ err_prop = -+ (rc_table->target_pf - pf) << rc_table->arith_shift; -+ err_avg = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT; -+ spinfo->err_avg_sc = -+ spinfo->err_avg_sc - err_avg + err_prop; -+ err_int = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT; -+ err_der = pf - spinfo->last_pf; -+ spinfo->last_pf = pf; -+ spinfo->last_dlr = dlr; -+ spinfo->oldrate = spinfo->txrate_idx; -+ adj = -+ (err_prop * RC_PID_COEFF_P + -+ err_int * RC_PID_COEFF_I + -+ err_der * RC_PID_COEFF_D); -+ adj = -+ RC_PID_DO_ARITH_RIGHT_SHIFT(adj, -+ rc_table->arith_shift << -+ 1); -+ if (adj) { -+#ifdef RATE_CONTROL_PARAMETER_DEBUG -+ if ((spinfo->txrate_idx != 11) -+ || ((spinfo->txrate_idx == 11) -+ && (adj < 0))) -+ pr_debug -+ ("[RC]Probe adjust[%d] dlr[%d%%] this_thp[%d] ewma_thp[%d] index[%d]\n", -+ adj, dlr, this_thp, ewma_thp, -+ spinfo->txrate_idx); -+#endif -+ rate_control_pid_adjust_rate(rc_sta, spinfo, -+ adj, rinfo); -+ } -+ } -+ } else { -+ if ((spinfo->feedback_probes >= MAXPROBES) -+ || (spinfo->feedback_probes && spinfo->probe_cnt)) { -+ rate = &pinfo->rinfo[spinfo->txrate_idx]; -+ spinfo->last_sample = jiffies; -+ if (rate->this_attempt > 0) { -+ dlr = -+ 100 - -+ rate->this_fail * 100 / rate->this_attempt; -+#ifdef RATE_CONTROL_DEBUG -+#ifdef PROBE -+ txrate_dlr = dlr; -+#endif -+#endif -+ spinfo->last_dlr = dlr; -+ perfect_time = rate->perfect_tx_time; -+ if (!perfect_time) -+ perfect_time = 1000000; -+ this_thp = dlr * (1000000 / perfect_time); -+ ewma_thp = rate->throughput; -+ if (ewma_thp == 0) -+ rate->throughput = this_thp; -+ else -+ rate->throughput = -+ (ewma_thp + this_thp) >> 1; -+ rate->attempt += rate->this_attempt; -+ rate->success += rate->this_success; -+ rinfo[spinfo->txrate_idx].fail += -+ rate->this_fail; -+ rate->this_fail = 0; -+ rate->this_success = 0; -+ rate->this_attempt = 0; -+ } else { -+#ifdef RATE_CONTROL_DEBUG -+#ifdef PROBE -+ txrate_dlr = 0; -+#endif -+#endif -+ } -+ rate = &pinfo->rinfo[spinfo->tmp_rate_idx]; -+ if (rate->this_attempt > 0) { -+ dlr = -+ 100 - -+ ((rate->this_fail * 100) / -+ rate->this_attempt); -+ { -+ perfect_time = rate->perfect_tx_time; -+ if (!perfect_time) -+ perfect_time = 1000000; -+ if (dlr) -+ this_thp = -+ dlr * (1000000 / -+ perfect_time); -+ else -+ this_thp = 0; -+ ewma_thp = rate->throughput; -+ if (ewma_thp == 0) -+ rate->throughput = this_thp; -+ else -+ rate->throughput = -+ (ewma_thp + this_thp) >> 1; -+ if (rate->throughput > -+ pinfo->rinfo[spinfo-> -+ txrate_idx].throughput) -+ { -+#ifdef RATE_CONTROL_PARAMETER_DEBUG -+ pr_debug -+ ("[RC]UPDATE probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n", -+ spinfo->tmp_rate_idx, -+ rate->throughput, dlr, -+ spinfo->txrate_idx, -+ pinfo-> -+ rinfo -+ [spinfo->txrate_idx].throughput, -+ txrate_dlr, -+ spinfo->feedback_probes); -+#endif -+ spinfo->txrate_idx = -+ spinfo->tmp_rate_idx; -+ } else { -+#ifdef RATE_CONTROL_PARAMETER_DEBUG -+ pr_debug -+ ("[RC]Fail probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n", -+ spinfo->tmp_rate_idx, -+ rate->throughput, dlr, -+ spinfo->txrate_idx, -+ pinfo-> -+ rinfo -+ [spinfo->txrate_idx].throughput, -+ txrate_dlr, -+ spinfo->feedback_probes); -+#endif -+ ; -+ } -+ rate->attempt += rate->this_attempt; -+ rate->success += rate->this_success; -+ rate->fail += rate->this_fail; -+ rate->this_fail = 0; -+ rate->this_success = 0; -+ rate->this_attempt = 0; -+ spinfo->oldrate = spinfo->txrate_idx; -+ } -+ } -+#ifdef RATE_CONTROL_DEBUG -+ else -+ pr_err("Unexpected error\n"); -+#endif -+ spinfo->feedback_probes = 0; -+ spinfo->tx_num_xmit = 0; -+ spinfo->tx_num_failed = 0; -+ spinfo->monitoring = 0; -+#ifdef RATE_CONTROL_PARAMETER_DEBUG -+ pr_debug("Disable monitor\n"); -+#endif -+ spinfo->probe_report_flag = 0; -+ spinfo->probe_wating_times = 0; -+ } else { -+ spinfo->probe_wating_times++; -+#ifdef RATE_CONTROL_DEBUG -+ if (spinfo->probe_wating_times > 3) { -+ pr_debug -+ ("[RC]@@@@@ PROBE LOSE @@@@@ feedback=[%d] need=[%d] probe_cnt=[%d] wating times[%d]\n", -+ spinfo->feedback_probes, MAXPROBES, -+ spinfo->probe_cnt, -+ spinfo->probe_wating_times); -+ spinfo->feedback_probes = 0; -+ spinfo->tx_num_xmit = 0; -+ spinfo->tx_num_failed = 0; -+ spinfo->monitoring = 0; -+ spinfo->probe_report_flag = 0; -+ spinfo->probe_wating_times = 0; -+ } -+#else -+ if (spinfo->probe_wating_times > 3) { -+ spinfo->feedback_probes = 0; -+ spinfo->tx_num_xmit = 0; -+ spinfo->tx_num_failed = 0; -+ spinfo->monitoring = 0; -+ spinfo->probe_report_flag = 0; -+ spinfo->probe_wating_times = 0; -+ } -+#endif -+ } -+ } -+} -+ -+#ifdef RATE_CONTROL_PERCENTAGE_TRACE -+int percentage = 0; -+int percentageCounter = 0; -+#endif -+void ssv6xxx_legacy_report_handler(struct ssv_softc *sc, struct sk_buff *skb, -+ struct ssv_sta_rc_info *rc_sta) -+{ -+ struct ssv_rate_ctrl *ssv_rc = sc->rc; -+ struct cfg_host_event *host_event; -+ struct firmware_rate_control_report_data *report_data; -+ struct rc_pid_info *pinfo; -+ struct rc_pid_sta_info *spinfo; -+ struct rc_pid_rateinfo *pidrate; -+ struct rc_pid_rateinfo *rate; -+ s32 report_data_index = 0; -+ unsigned long period; -+ host_event = (struct cfg_host_event *)skb->data; -+ report_data = -+ (struct firmware_rate_control_report_data *)&host_event->dat[0]; -+ if ((report_data->wsid != (-1)) -+ && sc->sta_info[report_data->wsid].sta == NULL) { -+ dev_warn(sc->dev, "RC report has no valid STA.(%d)\n", -+ report_data->wsid); -+ return; -+ } -+ pinfo = &rc_sta->pinfo; -+ spinfo = &rc_sta->spinfo; -+ pidrate = rc_sta->pinfo.rinfo; -+ if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) { -+ period = msecs_to_jiffies(HT_RC_UPDATE_INTERVAL); -+ if (time_after(jiffies, spinfo->last_sample + period)) { -+ if (rc_sta->rc_num_rate == 12) -+ spinfo->txrate_idx = rc_sta->ht.max_tp_rate + 4; -+ else -+ spinfo->txrate_idx = rc_sta->ht.max_tp_rate; -+#ifdef RATE_CONTROL_DEBUG -+ pr_debug("MPDU rate update time txrate_idx[%d]!!\n", -+ spinfo->txrate_idx); -+#endif -+ spinfo->last_sample = jiffies; -+ } -+ return; -+ } else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) { -+ ; -+ } else { -+ dev_warn(sc->dev, "RC report handler got garbage\n"); -+ return; -+ } -+ if (report_data->rates[0].data_rate < 7) { -+ if (report_data->rates[0].data_rate > 3) { -+ report_data->rates[0].data_rate -= 3; -+ } -+ } -+ if (ssv_rc-> -+ rc_table[rc_sta->pinfo.rinfo[spinfo->txrate_idx]. -+ rc_index].hw_rate_idx == report_data->rates[0].data_rate) { -+ report_data_index = -+ rc_sta->pinfo.rinfo[spinfo->txrate_idx].index; -+ } else -+ if (ssv_rc->rc_table -+ [rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx]. -+ rc_index].hw_rate_idx == report_data->rates[0].data_rate) { -+ report_data_index = -+ rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].index; -+ } -+ if ((report_data_index != spinfo->tmp_rate_idx) -+ && (report_data_index != spinfo->txrate_idx)) { -+#ifdef RATE_CONTROL_DEBUG -+ dev_dbg -+ (sc->dev, "Rate control report mismatch report_rate_idx[%d] tmp_rate_idx[%d]rate[%d] txrate_idx[%d]rate[%d]!!\n", -+ report_data->rates[0].data_rate, spinfo->tmp_rate_idx, -+ ssv_rc->rc_table[rc_sta->pinfo. -+ rinfo[spinfo->tmp_rate_idx].rc_index]. -+ hw_rate_idx, spinfo->txrate_idx, -+ ssv_rc->rc_table[rc_sta->pinfo. -+ rinfo[spinfo->txrate_idx].rc_index]. -+ hw_rate_idx); -+#endif -+ return; -+ } -+ if (report_data_index == spinfo->txrate_idx) { -+ spinfo->tx_num_xmit += report_data->rates[0].count; -+ spinfo->tx_num_failed += -+ (report_data->rates[0].count - report_data->ampdu_ack_len); -+ rate = &pidrate[spinfo->txrate_idx]; -+ rate->this_fail += -+ (report_data->rates[0].count - report_data->ampdu_ack_len); -+ rate->this_attempt += report_data->rates[0].count; -+ rate->this_success += report_data->ampdu_ack_len; -+ } -+ if (report_data_index != spinfo->txrate_idx -+ && report_data_index == spinfo->tmp_rate_idx) { -+ spinfo->feedback_probes += report_data->ampdu_len; -+ rate = &pidrate[spinfo->tmp_rate_idx]; -+ rate->this_fail += -+ (report_data->rates[0].count - report_data->ampdu_ack_len); -+ rate->this_attempt += report_data->rates[0].count; -+ rate->this_success += report_data->ampdu_ack_len; -+ } -+ period = msecs_to_jiffies(RC_PID_INTERVAL); -+ if (time_after(jiffies, spinfo->last_sample + period)) { -+#ifdef RATE_CONTROL_PERCENTAGE_TRACE -+ rate = &pidrate[spinfo->txrate_idx]; -+ if (rate->this_success > rate->this_attempt) { -+ dev_dbg(sc->dev, "this_success[%ld] this_attempt[%ld]\n", -+ rate->this_success, rate->this_attempt); -+ } else { -+ if (percentage == 0) -+ percentage = -+ (int)((rate->this_success * 100) / -+ rate->this_attempt); -+ else -+ percentage = -+ (percentage + -+ (int)((rate->this_success * 100) / -+ rate->this_attempt)) / 2; -+ deb_dbg(sc->dev, "Percentage[%d]\n", percentage); -+ if ((percentageCounter % 16) == 1) -+ percentage = 0; -+ } -+#endif -+#ifdef RATE_CONTROL_STUPID_DEBUG -+ if (spinfo->txrate_idx != spinfo->tmp_rate_idx) { -+ rate = &pidrate[spinfo->tmp_rate_idx]; -+ if (spinfo->monitoring && ((rate->this_attempt == 0) -+ || (rate->this_attempt != -+ MAXPROBES))) { -+ dev_dbg(sc->dev, "Probe result a[%ld]s[%ld]f[%ld]", -+ rate->this_attempt, rate->this_success, -+ rate->this_fail); -+ } -+ rate = &pidrate[spinfo->txrate_idx]; -+ dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt, -+ rate->this_success, rate->this_fail); -+ } else { -+ rate = &pidrate[spinfo->txrate_idx]; -+ dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt, -+ rate->this_success, rate->this_fail); -+ } -+ dev_dbg(sc->dev, "w[%d]x%03d-f%03d\n", rc_sta->rc_wsid, -+ spinfo->tx_num_xmit, spinfo->tx_num_failed); -+#endif -+ rate_control_pid_sample(sc->rc, pinfo, rc_sta, spinfo); -+ } -+} -+ -+void ssv6xxx_sample_work(struct work_struct *work) -+{ -+ struct ssv_softc *sc = -+ container_of(work, struct ssv_softc, rc_sample_work); -+ struct ssv_rate_ctrl *ssv_rc = sc->rc; -+ struct sk_buff *skb; -+ struct cfg_host_event *host_event; -+ struct ssv_sta_rc_info *rc_sta = NULL; -+ struct firmware_rate_control_report_data *report_data; -+ struct ssv_sta_info *ssv_sta; -+ u8 hw_wsid = 0; -+ sc->rc_sample_sechedule = 1; -+ while (1) { -+ skb = skb_dequeue(&sc->rc_report_queue); -+ if (skb == NULL) -+ break; -+#ifdef DISABLE_RATE_CONTROL_SAMPLE -+ { -+ dev_kfree_skb_any(skb); -+ continue; -+ } -+#endif -+ host_event = (struct cfg_host_event *)skb->data; -+ if ((host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) -+ || (host_event->h_event == SOC_EVT_RC_MPDU_REPORT)) { -+ report_data = -+ (struct firmware_rate_control_report_data *) -+ &host_event->dat[0]; -+ hw_wsid = report_data->wsid; -+ } else { -+ dev_warn(sc->dev, "rate control sampling got garbage\n"); -+ dev_kfree_skb_any(skb); -+ continue; -+ } -+ if (hw_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) { -+#ifdef RATE_CONTROL_DEBUG -+ dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-0!!\n"); -+#endif -+ dev_kfree_skb_any(skb); -+ continue; -+ } -+ ssv_sta = &sc->sta_info[hw_wsid]; -+ if (ssv_sta->sta == NULL) { -+ dev_err(sc->dev, "Null STA %d for RC report.\n", -+ hw_wsid); -+ rc_sta = NULL; -+ } else { -+ struct ssv_sta_priv_data *ssv_sta_priv = -+ (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv; -+ rc_sta = &ssv_rc->sta_rc_info[ssv_sta_priv->rc_idx]; -+ if (rc_sta->rc_wsid != hw_wsid) { -+ rc_sta = NULL; -+ } -+ } -+ if (rc_sta == NULL) { -+ dev_err(sc->dev, -+ "[RC]rc_sta is NULL pointer Check-1!!\n"); -+ dev_kfree_skb_any(skb); -+ continue; -+ } -+ if (rc_sta == NULL) { -+#ifdef RATE_CONTROL_DEBUG -+ dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-2!!\n"); -+#endif -+ dev_kfree_skb_any(skb); -+ continue; -+ } -+ if (rc_sta->is_ht) { -+ ssv6xxx_legacy_report_handler(sc, skb, rc_sta); -+ ssv6xxx_ht_report_handler(sc, skb, rc_sta); -+ } else -+ ssv6xxx_legacy_report_handler(sc, skb, rc_sta); -+ dev_kfree_skb_any(skb); -+ } -+ sc->rc_sample_sechedule = 0; -+} -+ -+static void ssv6xxx_tx_status(void *priv, -+ struct ieee80211_supported_band *sband, -+ struct ieee80211_sta *sta, void *priv_sta, -+ struct sk_buff *skb) -+{ -+ struct ssv_softc *sc; -+ struct ieee80211_hdr *hdr; -+ __le16 fc; -+ hdr = (struct ieee80211_hdr *)skb->data; -+ fc = hdr->frame_control; -+ if (!priv_sta || !ieee80211_is_data_qos(fc)) -+ return; -+ sc = (struct ssv_softc *)priv; -+ if (conf_is_ht(&sc->hw->conf) -+ && (!(skb->protocol == cpu_to_be16(ETH_P_PAE)))) { -+ if (skb_get_queue_mapping(skb) != IEEE80211_AC_VO) -+ ssv6200_ampdu_tx_update_state(priv, sta, skb); -+ } -+ return; -+} -+ -+static void rateControlGetRate(u8 rateIndex, char *pointer) -+{ -+ switch (rateIndex) { -+ case 0: -+ sprintf(pointer, "1Mbps"); -+ return; -+ case 1: -+ case 4: -+ sprintf(pointer, "2Mbps"); -+ return; -+ case 2: -+ case 5: -+ sprintf(pointer, "5.5Mbps"); -+ return; -+ case 3: -+ case 6: -+ sprintf(pointer, "11Mbps"); -+ return; -+ case 7: -+ sprintf(pointer, "6Mbps"); -+ return; -+ case 8: -+ sprintf(pointer, "9Mbps"); -+ return; -+ case 9: -+ sprintf(pointer, "12Mbps"); -+ return; -+ case 10: -+ sprintf(pointer, "18Mbps"); -+ return; -+ case 11: -+ sprintf(pointer, "24Mbps"); -+ return; -+ case 12: -+ sprintf(pointer, "36Mbps"); -+ return; -+ case 13: -+ sprintf(pointer, "48Mbps"); -+ return; -+ case 14: -+ sprintf(pointer, "54Mbps"); -+ return; -+ case 15: -+ case 31: -+ sprintf(pointer, "MCS0-l"); -+ return; -+ case 16: -+ case 32: -+ sprintf(pointer, "MCS1-l"); -+ return; -+ case 17: -+ case 33: -+ sprintf(pointer, "MCS2-l"); -+ return; -+ case 18: -+ case 34: -+ sprintf(pointer, "MCS3-l"); -+ return; -+ case 19: -+ case 35: -+ sprintf(pointer, "MCS4-l"); -+ return; -+ case 20: -+ case 36: -+ sprintf(pointer, "MCS5-l"); -+ return; -+ case 21: -+ case 37: -+ sprintf(pointer, "MCS6-l"); -+ return; -+ case 22: -+ case 38: -+ sprintf(pointer, "MCS7-l"); -+ return; -+ case 23: -+ sprintf(pointer, "MCS0-s"); -+ return; -+ case 24: -+ sprintf(pointer, "MCS1-s"); -+ return; -+ case 25: -+ sprintf(pointer, "MCS2-s"); -+ return; -+ case 26: -+ sprintf(pointer, "MCS3-s"); -+ return; -+ case 27: -+ sprintf(pointer, "MCS4-s"); -+ return; -+ case 28: -+ sprintf(pointer, "MCS5-s"); -+ return; -+ case 29: -+ sprintf(pointer, "MCS6-s"); -+ return; -+ case 30: -+ sprintf(pointer, "MCS7-s"); -+ return; -+ default: -+ sprintf(pointer, "Unknow"); -+ return; -+ }; -+} -+ -+static void ssv6xxx_get_rate(void *priv, struct ieee80211_sta *sta, -+ void *priv_sta, -+ struct ieee80211_tx_rate_control *txrc) -+{ -+ struct ssv_softc *sc = priv; -+ struct ssv_rate_ctrl *ssv_rc = sc->rc; -+ struct ssv_sta_rc_info *rc_sta = priv_sta; -+ struct sk_buff *skb = txrc->skb; -+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); -+ struct ieee80211_tx_rate *rates = tx_info->control.rates; -+ struct rc_pid_sta_info *spinfo = &rc_sta->spinfo; -+ struct ssv_rc_rate *rc_rate = NULL; -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ int rateidx = 99; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0) -+ if (rate_control_send_low(sta, priv_sta, txrc)) { -+ int i = 0; -+ int total_rates = -+ (sizeof(ssv_11bgn_rate_table) / -+ sizeof(ssv_11bgn_rate_table[0])); -+#if 1 -+ if ((txrc->rate_idx_mask & (1 << rates[0].idx)) == 0) { -+ u32 rate_idx = rates[0].idx + 1; -+ u32 rate_idx_mask = txrc->rate_idx_mask >> rate_idx; -+ while (rate_idx_mask && (rate_idx_mask & 1) == 0) { -+ rate_idx_mask >>= 1; -+ rate_idx++; -+ } -+ if (rate_idx_mask) -+ rates[0].idx = rate_idx; -+ else { -+ WARN_ON(rate_idx_mask == 0); -+ } -+ } -+#endif -+ for (i = 0; i < total_rates; i++) { -+ if (rates[0].idx == -+ ssv_11bgn_rate_table[i].dot11_rate_idx) { -+ break; -+ } -+ } -+ if (i < total_rates) -+ rc_rate = &ssv_rc->rc_table[i]; -+ else { -+ WARN_ON("Failed to find matching low rate."); -+ } -+ } -+#endif -+ if (rc_rate == NULL) { -+ if (conf_is_ht(&sc->hw->conf) && -+ (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)) -+ tx_info->flags |= IEEE80211_TX_CTL_LDPC; -+ if (conf_is_ht(&sc->hw->conf) && -+ (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_TX_STBC)) -+ tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT); -+ if (sc->sc_flags & SC_OP_FIXED_RATE) { -+ rateidx = sc->max_rate_idx; -+ } else { -+ if (rc_sta->rc_valid == false) { -+ rateidx = 0; -+ } else { -+ if ((rc_sta->rc_wsid >= -+ SSV_RC_MAX_HARDWARE_SUPPORT) -+ || (rc_sta->rc_wsid < 0)) { -+ ssv_sta_priv = -+ (struct ssv_sta_priv_data *) -+ sta->drv_priv; -+ { -+ if ((rc_sta->ht_rc_type >= -+ RC_TYPE_HT_SGI_20) -+ && -+ (ssv_sta_priv->rx_data_rate -+ < -+ SSV62XX_RATE_MCS_INDEX)) { -+ rateidx = -+ rc_sta-> -+ pinfo.rinfo -+ [spinfo->txrate_idx].rc_index; -+ } else { -+ rateidx = -+ ssv_sta_priv->rx_data_rate; -+ } -+ } -+ } else { -+ if (rc_sta->is_ht) { -+#ifdef DISABLE_RATE_CONTROL_SAMPLE -+ rateidx = -+ rc_sta->ht. -+ groups.rates[MCS_GROUP_RATES -+ - 1].rc_index; -+#else -+ rateidx = -+ rc_sta->pinfo. -+ rinfo -+ [spinfo->txrate_idx].rc_index; -+#endif -+ } else { -+ { -+ BUG_ON -+ (spinfo->txrate_idx -+ >= -+ rc_sta->rc_num_rate); -+ rateidx = -+ rc_sta-> -+ pinfo.rinfo -+ [spinfo->txrate_idx].rc_index; -+ } -+ if (rateidx < 4) { -+ if (rateidx) { -+ if ((sc->sc_flags & SC_OP_SHORT_PREAMBLE) -+ || -+ (txrc->short_preamble)) -+ { -+ rateidx -+ += -+ 3; -+ } -+ } -+ } -+ } -+ } -+ } -+ } -+ rc_rate = &ssv_rc->rc_table[rateidx]; -+ if (spinfo->real_hw_index != rc_rate->hw_rate_idx) { -+ char string[24]; -+ rateControlGetRate(rc_rate->hw_rate_idx, string); -+ } -+ spinfo->real_hw_index = rc_rate->hw_rate_idx; -+ rates[0].count = 4; -+ rates[0].idx = rc_rate->dot11_rate_idx; -+ tx_info->control.rts_cts_rate_idx = -+ ssv_rc->rc_table[rc_rate->ctrl_rate_idx].dot11_rate_idx; -+ if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE) -+ rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE; -+ if (rc_rate->rc_flags & RC_FLAG_HT) { -+ rates[0].flags |= IEEE80211_TX_RC_MCS; -+ if (rc_rate->rc_flags & RC_FLAG_HT_SGI) -+ rates[0].flags |= IEEE80211_TX_RC_SHORT_GI; -+ if (rc_rate->rc_flags & RC_FLAG_HT_GF) -+ rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD; -+ } -+ } -+ rates[1].count = 0; -+ rates[1].idx = -1; -+ rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx; -+ rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx]; -+ rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx; -+} -+ -+int pide_frame_duration(size_t len, int rate, int short_preamble, int flags) -+{ -+ int dur = 0; -+ if (flags == WLAN_RC_PHY_CCK) { -+ dur = 10; -+ dur += short_preamble ? (72 + 24) : (144 + 48); -+ dur += DIV_ROUND_UP(8 * (len + 4) * 10, rate); -+ } else { -+ dur = 16; -+ dur += 16; -+ dur += 4; -+ dur += 4 * DIV_ROUND_UP((16 + 8 * (len + 4) + 6) * 10, -+ 4 * rate); -+ } -+ return dur; -+} -+ -+static void ssv62xx_rc_caps(struct ssv_sta_rc_info *rc_sta) -+{ -+ struct rc_pid_sta_info *spinfo; -+ struct rc_pid_info *pinfo; -+ struct rc_pid_rateinfo *rinfo; -+ int i; -+ spinfo = &rc_sta->spinfo; -+ pinfo = &rc_sta->pinfo; -+ memset(spinfo, 0, sizeof(struct rc_pid_sta_info)); -+ memset(pinfo, 0, sizeof(struct rc_pid_info)); -+ rinfo = rc_sta->pinfo.rinfo; -+ for (i = 0; i < rc_sta->rc_num_rate; i++) { -+ rinfo[i].rc_index = ssv6xxx_rc_rate_set[rc_sta->rc_type][i + 1]; -+ rinfo[i].diff = i * RC_PID_NORM_OFFSET; -+ rinfo[i].index = (u16) i; -+ rinfo[i].perfect_tx_time = -+ TDIFS + (TSLOT * 15 >> 1) + pide_frame_duration(1530, -+ ssv_11bgn_rate_table -+ [rinfo -+ [i].rc_index].rate_kbps -+ / 100, 1, -+ ssv_11bgn_rate_table -+ [rinfo -+ [i].rc_index].phy_type) -+ + pide_frame_duration(10, -+ ssv_11bgn_rate_table[rinfo[i]. -+ rc_index].rate_kbps -+ / 100, 1, -+ ssv_11bgn_rate_table[rinfo[i]. -+ rc_index].phy_type); -+ pr_debug("[RC]Init perfect_tx_time[%d][%d]\n", i, -+ rinfo[i].perfect_tx_time); -+ rinfo[i].throughput = 0; -+ } -+ if (rc_sta->is_ht) { -+ if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0] == 12) -+ spinfo->txrate_idx = 4; -+ else -+ spinfo->txrate_idx = 0; -+ } else { -+ spinfo->txrate_idx = ssv6xxx_rate_lowest_index(rc_sta); -+#ifdef DISABLE_RATE_CONTROL_SAMPLE -+ spinfo->txrate_idx = ssv6xxx_rate_highest_index(rc_sta); -+#endif -+ } -+ spinfo->real_hw_index = 0; -+ spinfo->probe_cnt = MAXPROBES; -+ spinfo->tmp_rate_idx = spinfo->txrate_idx; -+ spinfo->oldrate = spinfo->txrate_idx; -+ spinfo->last_sample = jiffies; -+ spinfo->last_report = jiffies; -+} -+ -+static void ssv6xxx_rate_update_rc_type(void *priv, -+ struct ieee80211_supported_band *sband, -+ struct ieee80211_sta *sta, -+ void *priv_sta) -+{ -+ struct ssv_softc *sc = priv; -+ struct ssv_hw *sh = sc->sh; -+ struct ssv_sta_rc_info *rc_sta = priv_sta; -+ int i; -+ u32 ht_supp_rates = 0; -+ BUG_ON(rc_sta->rc_valid == false); -+ dev_dbg(sc->dev, "[I] %s(): \n", __FUNCTION__); -+ rc_sta->ht_supp_rates = 0; -+ rc_sta->rc_supp_rates = 0; -+ rc_sta->is_ht = 0; -+#ifndef CONFIG_CH14_SUPPORT_GN_MODE -+ if (sc->cur_channel->hw_value == 14) { -+ dev_dbg(sc->dev, "[RC init ]Channel 14 support\n"); -+ if ((sta->deflink.supp_rates[sband->band] & (~0xfL)) == 0x0) { -+ dev_dbg(sc->dev, "[RC init ]B only mode\n"); -+ rc_sta->rc_type = RC_TYPE_B_ONLY; -+ } else { -+ dev_dbg(sc->dev, "[RC init ]GB mode\n"); -+ rc_sta->rc_type = RC_TYPE_LEGACY_GB; -+ } -+ } else -+#endif -+ if (sta->deflink.ht_cap.ht_supported == true) { -+ dev_dbg(sc->dev, "[RC init ]HT support wsid\n"); -+ for (i = 0; i < SSV_HT_RATE_MAX; i++) { -+ if (sta->deflink.ht_cap.mcs.rx_mask[i / -+ MCS_GROUP_RATES] & (1 << (i -+ % -+ MCS_GROUP_RATES))) -+ ht_supp_rates |= BIT(i); -+ } -+ rc_sta->ht_supp_rates = ht_supp_rates; -+ if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD) { -+ rc_sta->rc_type = RC_TYPE_HT_GF; -+ rc_sta->ht_rc_type = RC_TYPE_HT_GF; -+ } else if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) { -+ rc_sta->rc_type = RC_TYPE_SGI_20; -+ rc_sta->ht_rc_type = RC_TYPE_HT_SGI_20; -+ } else { -+ rc_sta->rc_type = RC_TYPE_LGI_20; -+ rc_sta->ht_rc_type = RC_TYPE_HT_LGI_20; -+ } -+ } else { -+ if ((sta->deflink.supp_rates[sband->band] & (~0xfL)) == 0x0) { -+ rc_sta->rc_type = RC_TYPE_B_ONLY; -+ dev_dbg(sc->dev, "[RC init ]B only mode\n"); -+ } else { -+ rc_sta->rc_type = RC_TYPE_LEGACY_GB; -+ dev_dbg(sc->dev, "[RC init ]legacy G mode\n"); -+ } -+ } -+#ifdef CONFIG_SSV_DPD -+ if (rc_sta->rc_type == RC_TYPE_B_ONLY) { -+ SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3D3E84FE); -+ SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x1457D79); -+ SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x0); -+ } else { -+ SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3CBE84FE); -+ SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x4507F9); -+ SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x3); -+ } -+#endif -+ if ((rc_sta->rc_type != RC_TYPE_B_ONLY) -+ && (rc_sta->rc_type != RC_TYPE_LEGACY_GB)) { -+ if ((sta->deflink.ht_cap.ht_supported) -+ && (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)) { -+ rc_sta->is_ht = 1; -+ ssv62xx_ht_rc_caps(ssv6xxx_rc_rate_set, rc_sta); -+ } -+ } -+ { -+ rc_sta->rc_num_rate = -+ (u8) ssv6xxx_rc_rate_set[rc_sta->rc_type][0]; -+ if ((rc_sta->rc_type == RC_TYPE_HT_GF) -+ || (rc_sta->rc_type == RC_TYPE_LGI_20) -+ || (rc_sta->rc_type == RC_TYPE_SGI_20)) { -+ if (rc_sta->rc_num_rate == 12) { -+ rc_sta->rc_supp_rates = -+ sta->deflink.supp_rates[sband->band] & 0xfL; -+ rc_sta->rc_supp_rates |= (ht_supp_rates << 4); -+ } else -+ rc_sta->rc_supp_rates = ht_supp_rates; -+ } else if (rc_sta->rc_type == RC_TYPE_LEGACY_GB) -+ rc_sta->rc_supp_rates = sta->deflink.supp_rates[sband->band]; -+ else if (rc_sta->rc_type == RC_TYPE_B_ONLY) -+ rc_sta->rc_supp_rates = -+ sta->deflink.supp_rates[sband->band] & 0xfL; -+ ssv62xx_rc_caps(rc_sta); -+ } -+} -+ -+static void ssv6xxx_rate_update(void *priv, -+ struct ieee80211_supported_band *sband, -+ struct cfg80211_chan_def *chandef, -+ struct ieee80211_sta *sta, void *priv_sta, -+ u32 changed) -+{ -+ pr_debug("%s: changed=%d\n", __FUNCTION__, changed); -+ return; -+} -+ -+static void ssv6xxx_rate_init(void *priv, -+ struct ieee80211_supported_band *sband, -+ struct cfg80211_chan_def *chandef, -+ struct ieee80211_sta *sta, void *priv_sta) -+{ -+ ssv6xxx_rate_update_rc_type(priv, sband, sta, priv_sta); -+} -+ -+static void *ssv6xxx_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, -+ gfp_t gfp) -+{ -+ struct ssv_sta_priv_data *sta_priv = -+ (struct ssv_sta_priv_data *)sta->drv_priv; -+#ifndef RC_STA_DIRECT_MAP -+ struct ssv_softc *sc = priv; -+ struct ssv_rate_ctrl *ssv_rc = sc->rc; -+ int s; -+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ for (s = 0; s < SSV_RC_MAX_STA; s++) { -+ if (ssv_rc->sta_rc_info[s].rc_valid == false) { -+ dev_dbg(sc->dev, "%s(): use index %d\n", __FUNCTION__, s); -+ memset(&ssv_rc->sta_rc_info[s], 0, -+ sizeof(struct ssv_sta_rc_info)); -+ ssv_rc->sta_rc_info[s].rc_valid = true; -+ ssv_rc->sta_rc_info[s].rc_wsid = -1; -+ sta_priv->rc_idx = s; -+ return &ssv_rc->sta_rc_info[s]; -+ } -+ } -+ return NULL; -+#else -+ sta_priv->rc_idx = (-1); -+ return sta_priv; -+#endif -+} -+ -+static void ssv6xxx_rate_free_sta(void *priv, struct ieee80211_sta *sta, -+ void *priv_sta) -+{ -+ struct ssv_sta_rc_info *rc_sta = priv_sta; -+ rc_sta->rc_valid = false; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0) -+static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw) -+#else -+static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw, -+ struct dentry *debugfsdir) -+#endif -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ssv_rate_ctrl *ssv_rc; -+ sc->rc = kzalloc(sizeof(struct ssv_rate_ctrl), GFP_KERNEL); -+ if (!sc->rc) { -+ pr_err("%s(): Unable to allocate RC structure !\n", -+ __FUNCTION__); -+ return NULL; -+ } -+ memset(sc->rc, 0, sizeof(struct ssv_rate_ctrl)); -+ ssv_rc = (struct ssv_rate_ctrl *)sc->rc; -+ ssv_rc->rc_table = ssv_11bgn_rate_table; -+ skb_queue_head_init(&sc->rc_report_queue); -+ INIT_WORK(&sc->rc_sample_work, ssv6xxx_sample_work); -+ sc->rc_sample_workqueue = create_workqueue("ssv6xxx_rc_sample"); -+ sc->rc_sample_sechedule = 0; -+ return hw->priv; -+} -+ -+static void ssv6xxx_rate_free(void *priv) -+{ -+ struct ssv_softc *sc = priv; -+ if (sc->rc) { -+ kfree(sc->rc); -+ sc->rc = NULL; -+ } -+ sc->rc_sample_sechedule = 0; -+ cancel_work_sync(&sc->rc_sample_work); -+ flush_workqueue(sc->rc_sample_workqueue); -+ destroy_workqueue(sc->rc_sample_workqueue); -+} -+ -+static struct rate_control_ops ssv_rate_ops = { -+ .name = "ssv6xxx_rate_control", -+ .tx_status = ssv6xxx_tx_status, -+ .get_rate = ssv6xxx_get_rate, -+ .rate_init = ssv6xxx_rate_init, -+ .rate_update = ssv6xxx_rate_update, -+ .alloc = ssv6xxx_rate_alloc, -+ .free = ssv6xxx_rate_free, -+ .alloc_sta = ssv6xxx_rate_alloc_sta, -+ .free_sta = ssv6xxx_rate_free_sta, -+}; -+ -+void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc, -+ int hw_rate_idx, -+ struct ieee80211_rx_status *rxs) -+{ -+ struct ssv_rate_ctrl *ssv_rc = sc->rc; -+ struct ssv_rc_rate *rc_rate; -+ BUG_ON(hw_rate_idx >= RATE_TABLE_SIZE && hw_rate_idx < 0); -+ rc_rate = &ssv_rc->rc_table[hw_rate_idx]; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0) -+ if (rc_rate->rc_flags & RC_FLAG_HT) { -+ // rxs->flag |= RC_FLAG_HT; -+ if (rc_rate->rc_flags & RC_FLAG_HT_SGI) -+ rxs->enc_flags |= RX_ENC_FLAG_SHORT_GI; -+ } else { -+ if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE) -+ rxs->enc_flags |= RX_ENC_FLAG_SHORTPRE; -+ } -+#else -+ if (rc_rate->rc_flags & RC_FLAG_HT) { -+ rxs->flag |= RC_FLAG_HT; -+ if (rc_rate->rc_flags & RC_FLAG_HT_SGI) -+ rxs->flag |= RX_FLAG_SHORT_GI; -+ } else { -+ if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE) -+ rxs->flag |= RX_FLAG_SHORTPRE; -+ } -+#endif -+ rxs->rate_idx = rc_rate->dot11_rate_idx; -+} -+ -+void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc, -+ struct ieee80211_tx_info *info, -+ struct ssv_rate_info *sr) -+{ -+ struct ieee80211_tx_rate *tx_rate; -+ struct ssv_rate_ctrl *ssv_rc = sc->rc; -+ tx_rate = &info->control.rates[0]; -+ sr->d_flags = -+ (ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].phy_type == -+ WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0; -+ sr->d_flags |= -+ (ssv_rc-> -+ rc_table[tx_rate[SSV_DRATE_IDX]. -+ count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ? -+ IEEE80211_RATE_SHORT_PREAMBLE : 0; -+ sr->c_flags = -+ (ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].phy_type == -+ WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0; -+ sr->c_flags |= -+ (ssv_rc-> -+ rc_table[tx_rate[SSV_CRATE_IDX]. -+ count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ? -+ IEEE80211_RATE_SHORT_PREAMBLE : 0; -+ sr->drate_kbps = -+ ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].rate_kbps; -+ sr->drate_hw_idx = tx_rate[SSV_DRATE_IDX].count; -+ sr->crate_kbps = -+ ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].rate_kbps; -+ sr->crate_hw_idx = tx_rate[SSV_CRATE_IDX].count; -+} -+ -+u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc, -+ u32 do_rts_cts) -+{ -+ int ret = 0; -+ struct ssv_rate_ctrl *ssv_rc = sc->rc; -+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); -+ struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head; -+ struct ieee80211_sta *sta = skb_info->sta; -+ struct ieee80211_tx_rate *rates = &tx_info->control.rates[0]; -+ struct ssv_rc_rate *rc_rate = NULL; -+ u8 rateidx = 0; -+ struct ssv_sta_rc_info *rc_sta = NULL; -+ struct rc_pid_sta_info *spinfo; -+ struct ssv_sta_priv_data *sta_priv = NULL; -+ unsigned long period = 0; -+ if (sc->sc_flags & SC_OP_FIXED_RATE) -+ return ret; -+ if (sta == NULL) -+ return ret; -+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ if (sta_priv == NULL) { -+#ifdef RATE_CONTROL_DEBUG -+ dev_dbg(rc->dev, "%s sta_priv == NULL \n\r", __FUNCTION__); -+#endif -+ return ret; -+ } -+ if ((sta_priv->rc_idx < 0) || (sta_priv->rc_idx >= SSV_RC_MAX_STA)) { -+#ifdef RATE_CONTROL_DEBUG -+ dev_dbg(sc->dev, "%s rc_idx %x illegal \n\r", __FUNCTION__, -+ sta_priv->rc_idx); -+#endif -+ return ret; -+ } -+ rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx]; -+ if (rc_sta->rc_valid == false) { -+#ifdef RATE_CONTROL_DEBUG -+ dev_dbg(sc->dev, "%s rc_valid false \n\r", __FUNCTION__); -+#endif -+ return ret; -+ } -+ spinfo = &rc_sta->spinfo; -+ period = msecs_to_jiffies(RC_PID_REPORT_INTERVAL); -+ if (time_after(jiffies, spinfo->last_report + period)) { -+ ret |= RC_FIRMWARE_REPORT_FLAG; -+ spinfo->last_report = jiffies; -+ } -+ { -+ if (spinfo->monitoring) { -+ if (spinfo->probe_report_flag == 0) { -+ ret |= RC_FIRMWARE_REPORT_FLAG; -+ spinfo->last_report = jiffies; -+ spinfo->probe_report_flag = 1; -+ rateidx = spinfo->real_hw_index; -+ } else if (spinfo->probe_cnt > 0 -+ && spinfo->probe_report_flag) { -+ rateidx = -+ rc_sta->pinfo.rinfo[spinfo-> -+ tmp_rate_idx].rc_index; -+ spinfo->probe_cnt--; -+ if (spinfo->probe_cnt == 0) { -+ ret |= RC_FIRMWARE_REPORT_FLAG; -+ spinfo->last_report = jiffies; -+ } -+ } else -+ rateidx = spinfo->real_hw_index; -+ } else -+ rateidx = spinfo->real_hw_index; -+ } -+ if (rateidx >= RATE_TABLE_SIZE) { -+ dev_err(sc->dev, "rateidx over range\n"); -+ return 0; -+ } -+ rc_rate = &ssv_rc->rc_table[rateidx]; -+#ifdef RATE_CONTROL_STUPID_DEBUG -+ if (spinfo->monitoring && (spinfo->probe_cnt)) { -+ char string[24]; -+ rateControlGetRate(rc_rate->hw_rate_idx, string); -+ dev_dbg(sc->dev, "[RC]Probe rate[%s]\n", string); -+ } -+#endif -+ if (rc_rate == NULL) -+ return ret; -+ if (rc_rate->hw_rate_idx != rates[SSV_DRATE_IDX].count) { -+ rates[0].flags = 0; -+ if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE) -+ rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE; -+ if (rc_rate->rc_flags & RC_FLAG_HT) { -+ rates[0].flags |= IEEE80211_TX_RC_MCS; -+ if (rc_rate->rc_flags & RC_FLAG_HT_SGI) -+ rates[0].flags |= IEEE80211_TX_RC_SHORT_GI; -+ if (rc_rate->rc_flags & RC_FLAG_HT_GF) -+ rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD; -+ } -+ rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx; -+ if (do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) { -+ rates[SSV_CRATE_IDX].count = 0; -+ } else { -+ rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx]; -+ rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx; -+ } -+ ret |= 0x1; -+ } -+ return ret; -+} -+ -+void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx) -+{ -+ struct ssv_rate_ctrl *ssv_rc = sc->rc; -+ struct ssv_sta_rc_info *rc_sta; -+ u32 rc_hw_reg[] = { ADR_MTX_MIB_WSID0, ADR_MTX_MIB_WSID1 }; -+ BUG_ON(rc_idx >= SSV_RC_MAX_STA); -+ rc_sta = &ssv_rc->sta_rc_info[rc_idx]; -+ if (hwidx >= 0 && hwidx < SSV_NUM_HW_STA) { -+ rc_sta->rc_wsid = hwidx; -+ dev_dbg(sc->dev, "rc_wsid[%d] rc_idx[%d]\n", rc_sta[rc_idx].rc_wsid, -+ rc_idx); -+ SMAC_REG_WRITE(sc->sh, rc_hw_reg[hwidx], 0x40000000); -+ } else { -+ rc_sta->rc_wsid = -1; -+ } -+} -+ -+#define UPDATE_PHY_INFO_ACK_RATE(_phy_info,_ack_rate_idx) ( _phy_info = (_phy_info&0xfffffc0f)|(_ack_rate_idx<<4)) -+int ssv6xxx_rc_update_bmode_ctrl_rate(struct ssv_softc *sc, int rate_tbl_idx, -+ int ctrl_rate_idx) -+{ -+ u32 temp32; -+ struct ssv_hw *sh = sc->sh; -+ u32 addr; -+ addr = sh->hw_pinfo + rate_tbl_idx * 4; -+ ssv_11bgn_rate_table[rate_tbl_idx].ctrl_rate_idx = ctrl_rate_idx; -+ SMAC_REG_READ(sh, addr, &temp32); -+ UPDATE_PHY_INFO_ACK_RATE(temp32, ctrl_rate_idx); -+ SMAC_REG_WRITE(sh, addr, temp32); -+ SMAC_REG_CONFIRM(sh, addr, temp32); -+ return 0; -+} -+ -+void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates) -+{ -+ int i; -+ int rate_idx, pre_rate_idx = 0; -+ for (i = 0; i < 4; i++) { -+ if (((basic_rates >> i) & 0x01)) { -+ rate_idx = i; -+ pre_rate_idx = i; -+ } else -+ rate_idx = pre_rate_idx; -+ ssv6xxx_rc_update_bmode_ctrl_rate(sc, i, rate_idx); -+ if (i) -+ ssv6xxx_rc_update_bmode_ctrl_rate(sc, i + 3, rate_idx); -+ } -+} -+ -+int ssv6xxx_rate_control_register(void) -+{ -+ return ieee80211_rate_control_register(&ssv_rate_ops); -+} -+ -+void ssv6xxx_rate_control_unregister(void) -+{ -+ ieee80211_rate_control_unregister(&ssv_rate_ops); -+} -+ -+void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb, -+ u32 rate_index) -+{ -+ struct ssv_softc *sc = hw->priv; -+ struct ieee80211_sta *sta; -+ struct ssv_sta_priv_data *ssv_sta_priv; -+ sta = ssv6xxx_find_sta_by_rx_skb(sc, skb); -+ if (sta == NULL) { -+ return; -+ } -+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv; -+ ssv_sta_priv->rx_data_rate = rate_index; -+} -diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_rc.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.h -@@ -0,0 +1,50 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV_RC_H_ -+#define _SSV_RC_H_ -+#include "ssv_rc_common.h" -+#define RC_PID_REPORT_INTERVAL 40 -+#define RC_PID_INTERVAL 125 -+#define RC_PID_DO_ARITH_RIGHT_SHIFT(x,y) \ -+ ((x) < 0 ? -((-(x)) >> (y)) : (x) >> (y)) -+#define RC_PID_NORM_OFFSET 3 -+#define RC_PID_SMOOTHING_SHIFT 1 -+#define RC_PID_SMOOTHING (1 << RC_PID_SMOOTHING_SHIFT) -+#define RC_PID_COEFF_P 15 -+#define RC_PID_COEFF_I 15 -+#define RC_PID_COEFF_D 5 -+#define MAXPROBES 3 -+#define SSV_DRATE_IDX (2) -+#define SSV_CRATE_IDX (3) -+ -+struct ssv_softc; -+struct ssv_rc_rate *ssv6xxx_rc_get_rate(int rc_index); -+void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc, -+ struct ieee80211_tx_info *info, -+ struct ssv_rate_info *sr); -+u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc, -+ u32 do_rts_cts); -+void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc, int hw_rate_idx, -+ struct ieee80211_rx_status *rxs); -+void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx); -+void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates); -+int ssv6xxx_rate_control_register(void); -+void ssv6xxx_rate_control_unregister(void); -+void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb, -+ u32 rate_index); -+int pide_frame_duration(size_t len, int rate, int short_preamble, int flags); -+#endif -diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h -@@ -0,0 +1,175 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV_RC_COM_H_ -+#define _SSV_RC_COM_H_ -+#define SSV_RC_MAX_STA 8 -+#define MCS_GROUP_RATES 8 -+#define SSV_HT_RATE_MAX 8 -+#define TDIFS 34 -+#define TSLOT 9 -+#define SSV_RC_MAX_HARDWARE_SUPPORT 2 -+#define RC_FIRMWARE_REPORT_FLAG 0x80 -+#define RC_FLAG_INVALID 0x00000001 -+#define RC_FLAG_LEGACY 0x00000002 -+#define RC_FLAG_HT 0x00000004 -+#define RC_FLAG_HT_SGI 0x00000008 -+#define RC_FLAG_HT_GF 0x00000010 -+#define RC_FLAG_SHORT_PREAMBLE 0x00000020 -+enum ssv6xxx_rc_phy_type { -+ WLAN_RC_PHY_CCK, -+ WLAN_RC_PHY_OFDM, -+ WLAN_RC_PHY_HT_20_SS_LGI, -+ WLAN_RC_PHY_HT_20_SS_SGI, -+ WLAN_RC_PHY_HT_20_SS_GF, -+}; -+#define RATE_TABLE_SIZE 39 -+#define RC_STA_VALID 0x00000001 -+#define RC_STA_CAP_HT 0x00000002 -+#define RC_STA_CAP_GF 0x00000004 -+#define RC_STA_CAP_SGI_20 0x00000008 -+#define RC_STA_CAP_SHORT_PREAMBLE 0x00000010 -+#define SSV62XX_G_RATE_INDEX 7 -+#define SSV62XX_RATE_MCS_INDEX 15 -+#define SSV62XX_RATE_MCS_LGI_INDEX 15 -+#define SSV62XX_RATE_MCS_SGI_INDEX 23 -+#define SSV62XX_RATE_MCS_GREENFIELD_INDEX 31 -+enum ssv_rc_rate_type { -+ RC_TYPE_B_ONLY = 0, -+ RC_TYPE_LEGACY_GB, -+ RC_TYPE_SGI_20, -+ RC_TYPE_LGI_20, -+ RC_TYPE_HT_SGI_20, -+ RC_TYPE_HT_LGI_20, -+ RC_TYPE_HT_GF, -+ RC_TYPE_MAX, -+}; -+struct ssv_rate_info { -+ int crate_kbps; -+ int crate_hw_idx; -+ int drate_kbps; -+ int drate_hw_idx; -+ u32 d_flags; -+ u32 c_flags; -+}; -+struct ssv_rc_rate { -+ u32 rc_flags; -+ u16 phy_type; -+ u32 rate_kbps; -+ u8 dot11_rate_idx; -+ u8 ctrl_rate_idx; -+ u8 hw_rate_idx; -+ u8 arith_shift; -+ u8 target_pf; -+}; -+struct rc_pid_sta_info { -+ unsigned long last_sample; -+ unsigned long last_report; -+ u16 tx_num_failed; -+ u16 tx_num_xmit; -+ u8 probe_report_flag; -+ u8 probe_wating_times; -+ u8 real_hw_index; -+ int txrate_idx; -+ u8 last_pf; -+ s32 err_avg_sc; -+ int last_dlr; -+ u8 feedback_probes; -+ u8 monitoring; -+ u8 oldrate; -+ u8 tmp_rate_idx; -+ u8 probe_cnt; -+}; -+struct rc_pid_rateinfo { -+ u16 rc_index; -+ u16 index; -+ s32 diff; -+ u16 perfect_tx_time; -+ u32 throughput; -+ unsigned long this_attempt; -+ unsigned long this_success; -+ unsigned long this_fail; -+ u64 attempt; -+ u64 success; -+ u64 fail; -+}; -+struct rc_pid_info { -+ unsigned int target; -+ int oldrate; -+ struct rc_pid_rateinfo rinfo[12]; -+}; -+struct mcs_group { -+ unsigned int duration[MCS_GROUP_RATES]; -+}; -+struct minstrel_rate_stats { -+ u16 rc_index; -+ unsigned int attempts, last_attempts; -+ unsigned int success, last_success; -+ u64 att_hist, succ_hist; -+ unsigned int cur_tp; -+ unsigned int cur_prob, probability; -+ unsigned int retry_count; -+ unsigned int retry_count_rtscts; -+ u8 sample_skipped; -+}; -+struct minstrel_mcs_group_data { -+ u8 index; -+ u8 column; -+ unsigned int max_tp_rate; -+ unsigned int max_tp_rate2; -+ unsigned int max_prob_rate; -+ struct minstrel_rate_stats rates[MCS_GROUP_RATES]; -+}; -+struct ssv62xx_ht { -+ unsigned int ampdu_len; -+ unsigned int ampdu_packets; -+ unsigned int avg_ampdu_len; -+ unsigned int max_tp_rate; -+ unsigned int max_tp_rate2; -+ unsigned int max_prob_rate; -+ int first_try_count; -+ int second_try_count; -+ int other_try_count; -+ unsigned long stats_update; -+ unsigned int overhead; -+ unsigned int overhead_rtscts; -+ unsigned int total_packets; -+ unsigned int sample_packets; -+ u8 sample_wait; -+ u8 sample_tries; -+ u8 sample_count; -+ u8 sample_slow; -+ struct minstrel_mcs_group_data groups; -+}; -+struct ssv_sta_rc_info { -+ u8 rc_valid; -+ u8 rc_type; -+ u8 rc_num_rate; -+ s8 rc_wsid; -+ u8 ht_rc_type; -+ u8 is_ht; -+ u32 rc_supp_rates; -+ u32 ht_supp_rates; -+ struct rc_pid_info pinfo; -+ struct rc_pid_sta_info spinfo; -+ struct ssv62xx_ht ht; -+}; -+struct ssv_rate_ctrl { -+ struct ssv_rc_rate *rc_table; -+ struct ssv_sta_rc_info sta_rc_info[SSV_RC_MAX_STA]; -+}; -+#define HT_RC_UPDATE_INTERVAL 1000 -+#endif -diff --git a/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c -@@ -0,0 +1,76 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static int g_wifidev_registered = 0; -+extern int ssvdevice_init(void); -+extern void ssvdevice_exit(void); -+extern int ssv6xxx_get_dev_status(void); -+ -+static __init int ssv_init_module(void) -+{ -+ int ret = 0; -+ int time = 5; -+ -+ msleep(120); -+ -+ g_wifidev_registered = 1; -+ ret = ssvdevice_init(); -+ -+ while(time-- > 0){ -+ msleep(500); -+ if(ssv6xxx_get_dev_status() == 1) -+ break; -+ pr_info("%s : Retry to carddetect\n",__func__); -+ } -+ -+ return ret; -+ -+} -+static __exit void ssv_exit_module(void) -+{ -+ -+ if (g_wifidev_registered) -+ { -+ ssvdevice_exit(); -+ msleep(50); -+ g_wifidev_registered = 0; -+ } -+ -+ return; -+ -+} -+ -+module_init(ssv_init_module); -+module_exit(ssv_exit_module); -+ -+MODULE_AUTHOR("iComm Semiconductor Co., Ltd"); -+MODULE_FIRMWARE("ssv*-sw.bin"); -+MODULE_FIRMWARE("ssv*-wifi.cfg"); -+MODULE_DESCRIPTION("Shared library for SSV wireless LAN cards."); -+MODULE_LICENSE("Dual BSD/GPL"); -+ -diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c -@@ -0,0 +1,1765 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ssv_cmd.h" -+#include -+#include -+#define SSV_CMD_PRINTF() -+struct ssv6xxx_dev_table { -+ u32 address; -+ u32 val; -+}; -+struct ssv6xxx_debug { -+ struct device *dev; -+ struct platform_device *pdev; -+ struct ssv6xxx_hwif_ops *ifops; -+}; -+static struct ssv6xxx_debug *ssv6xxx_debug_ifops; -+static char sg_cmd_buffer[CLI_BUFFER_SIZE + 1]; -+static char *sg_argv[CLI_ARG_SIZE]; -+static u32 sg_argc; -+extern char *ssv6xxx_result_buf; -+#if defined (CONFIG_ARM64) || defined (__x86_64__) -+u64 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 }; -+#else -+u32 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 }; -+#endif -+EXPORT_SYMBOL(ssv6xxx_ifdebug_info); -+struct sk_buff *ssvdevice_skb_alloc(s32 len) -+{ -+ struct sk_buff *skb; -+ skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL); -+ if (skb != NULL) { -+ skb_put(skb, 0x20); -+ skb_pull(skb, 0x20); -+ } -+ return skb; -+} -+ -+void ssvdevice_skb_free(struct sk_buff *skb) -+{ -+ dev_kfree_skb_any(skb); -+} -+ -+static int ssv_cmd_help(int argc, char *argv[]) -+{ -+ extern struct ssv_cmd_table cmd_table[]; -+ struct ssv_cmd_table *sc_tbl; -+ char tmpbf[161]; -+ int total_cmd = 0; -+ { -+ sprintf(ssv6xxx_result_buf, "Usage:\n"); -+ for (sc_tbl = &cmd_table[3]; sc_tbl->cmd; sc_tbl++) { -+ sprintf(tmpbf, "%-20s\t\t%s\n", sc_tbl->cmd, -+ sc_tbl->usage); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ total_cmd++; -+ } -+ sprintf(tmpbf, -+ "Total CMDs: %d\n\nType cli help [CMD] for more detail command.\n\n", -+ total_cmd); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ } -+ return 0; -+} -+ -+static int ssv_cmd_reg(int argc, char *argv[]) -+{ -+ u32 addr, value, count; -+ char tmpbf[64], *endp; -+ int s; -+ if (argc == 4 && strcmp(argv[1], "w") == 0) { -+ addr = simple_strtoul(argv[2], &endp, 16); -+ value = simple_strtoul(argv[3], &endp, 16); -+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ; -+ sprintf(ssv6xxx_result_buf, " => write [0x%08x]: 0x%08x\n", -+ addr, value); -+ return 0; -+ } else if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) { -+ count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10); -+ addr = simple_strtoul(argv[2], &endp, 16); -+ sprintf(ssv6xxx_result_buf, "ADDRESS: 0x%08x\n", addr); -+ for (s = 0; s < count; s++, addr += 4) { -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ; -+ sprintf(tmpbf, "%08x ", value); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ if (((s + 1) & 0x07) == 0) -+ strcat(ssv6xxx_result_buf, "\n"); -+ } -+ strcat(ssv6xxx_result_buf, "\n"); -+ return 0; -+ } else { -+ sprintf(tmpbf, "reg [r|w] [address] [value|word-count]\n\n"); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ return 0; -+ } -+ return -1; -+} -+ -+struct ssv6xxx_cfg ssv_cfg; -+EXPORT_SYMBOL(ssv_cfg); -+static int __string2u32(u8 * u8str, void *val, u32 arg) -+{ -+ char *endp; -+ int base = 10; -+ if (u8str[0] == '0' && ((u8str[1] == 'x') || (u8str[1] == 'X'))) -+ base = 16; -+ *(u32 *) val = simple_strtoul(u8str, &endp, base); -+ return 0; -+} -+ -+static int __string2flag32(u8 * flag_str, void *flag, u32 arg) -+{ -+ u32 *val = (u32 *) flag; -+ if (arg >= (sizeof(u32) << 3)) -+ return -1; -+ if (strcmp(flag_str, "on") == 0) { -+ *val |= (1 << arg); -+ return 0; -+ } -+ if (strcmp(flag_str, "off") == 0) { -+ *val &= ~(1 << arg); -+ return 0; -+ } -+ return -1; -+} -+ -+static int __string2mac(u8 * mac_str, void *val, u32 arg) -+{ -+ int s, macaddr[6]; -+ u8 *mac = (u8 *) val; -+ s = sscanf(mac_str, "%02x:%02x:%02x:%02x:%02x:%02x", -+ &macaddr[0], &macaddr[1], &macaddr[2], -+ &macaddr[3], &macaddr[4], &macaddr[5]); -+ if (s != 6) -+ return -1; -+ mac[0] = (u8) macaddr[0], mac[1] = (u8) macaddr[1]; -+ mac[2] = (u8) macaddr[2], mac[3] = (u8) macaddr[3]; -+ mac[4] = (u8) macaddr[4], mac[5] = (u8) macaddr[5]; -+ return 0; -+} -+ -+static int __string2str(u8 * path, void *val, u32 arg) -+{ -+ u8 *temp = (u8 *) val; -+ sprintf(temp, "%s", path); -+ return 0; -+} -+ -+static int __string2configuration(u8 * mac_str, void *val, u32 arg) -+{ -+ unsigned int address, value; -+ int i; -+ i = sscanf(mac_str, "%08x:%08x", &address, &value); -+ if (i != 2) -+ return -1; -+ for (i = 0; i < EXTERNEL_CONFIG_SUPPORT; i++) { -+ if (ssv_cfg.configuration[i][0] == 0x0) { -+ ssv_cfg.configuration[i][0] = address; -+ ssv_cfg.configuration[i][1] = value; -+ return 0; -+ } -+ } -+ return 0; -+} -+ -+struct ssv6xxx_cfg_cmd_table cfg_cmds[] = { -+ {"hw_mac", (void *)&ssv_cfg.maddr[0][0], 0, __string2mac}, -+ {"hw_mac_2", (void *)&ssv_cfg.maddr[1][0], 0, __string2mac}, -+ {"def_chan", (void *)&ssv_cfg.def_chan, 0, __string2u32}, -+ {"hw_cap_ht", (void *)&ssv_cfg.hw_caps, 0, __string2flag32}, -+ {"hw_cap_gf", (void *)&ssv_cfg.hw_caps, 1, __string2flag32}, -+ {"hw_cap_2ghz", (void *)&ssv_cfg.hw_caps, 2, __string2flag32}, -+ {"hw_cap_5ghz", (void *)&ssv_cfg.hw_caps, 3, __string2flag32}, -+ {"hw_cap_security", (void *)&ssv_cfg.hw_caps, 4, __string2flag32}, -+ {"hw_cap_sgi_20", (void *)&ssv_cfg.hw_caps, 5, __string2flag32}, -+ {"hw_cap_sgi_40", (void *)&ssv_cfg.hw_caps, 6, __string2flag32}, -+ {"hw_cap_ap", (void *)&ssv_cfg.hw_caps, 7, __string2flag32}, -+ {"hw_cap_p2p", (void *)&ssv_cfg.hw_caps, 8, __string2flag32}, -+ {"hw_cap_ampdu_rx", (void *)&ssv_cfg.hw_caps, 9, __string2flag32}, -+ {"hw_cap_ampdu_tx", (void *)&ssv_cfg.hw_caps, 10, __string2flag32}, -+ {"hw_cap_tdls", (void *)&ssv_cfg.hw_caps, 11, __string2flag32}, -+ {"use_wpa2_only", (void *)&ssv_cfg.use_wpa2_only, 0, __string2u32}, -+ {"wifi_tx_gain_level_gn", (void *)&ssv_cfg.wifi_tx_gain_level_gn, 0, -+ __string2u32}, -+ {"wifi_tx_gain_level_b", (void *)&ssv_cfg.wifi_tx_gain_level_b, 0, -+ __string2u32}, -+ {"rssi_ctl", (void *)&ssv_cfg.rssi_ctl, 0, __string2u32}, -+ {"xtal_clock", (void *)&ssv_cfg.crystal_type, 0, __string2u32}, -+ {"volt_regulator", (void *)&ssv_cfg.volt_regulator, 0, __string2u32}, -+ {"force_chip_identity", (void *)&ssv_cfg.force_chip_identity, 0, -+ __string2u32}, -+ {"firmware_path", (void *)&ssv_cfg.firmware_path[0], 0, __string2str}, -+ {"flash_bin_path", (void *)&ssv_cfg.flash_bin_path[0], 0, __string2str}, -+ {"mac_address_path", (void *)&ssv_cfg.mac_address_path[0], 0, -+ __string2str}, -+ {"mac_output_path", (void *)&ssv_cfg.mac_output_path[0], 0, -+ __string2str}, -+ {"ignore_efuse_mac", (void *)&ssv_cfg.ignore_efuse_mac, 0, -+ __string2u32}, -+ {"mac_address_mode", (void *)&ssv_cfg.mac_address_mode, 0, -+ __string2u32}, -+ {"sr_bhvr", (void *)&ssv_cfg.sr_bhvr, 0, __string2u32}, -+ {"register", NULL, 0, __string2configuration}, -+ {NULL, NULL, 0, NULL}, -+}; -+ -+EXPORT_SYMBOL(cfg_cmds); -+static int ssv_cmd_cfg(int argc, char *argv[]) -+{ -+ char temp_buf[64]; -+ int s; -+ if (argc == 2 && strcmp(argv[1], "reset") == 0) { -+ memset(&ssv_cfg, 0, sizeof(ssv_cfg)); -+ return 0; -+ } else if (argc == 2 && strcmp(argv[1], "show") == 0) { -+ strcpy(ssv6xxx_result_buf, ">> ssv6xxx config:\n"); -+ sprintf(temp_buf, " hw_caps = 0x%08x\n", ssv_cfg.hw_caps); -+ strcat(ssv6xxx_result_buf, temp_buf); -+ sprintf(temp_buf, " def_chan = %d\n", ssv_cfg.def_chan); -+ strcat(ssv6xxx_result_buf, temp_buf); -+ sprintf(temp_buf, " wifi_tx_gain_level_gn = %d\n", -+ ssv_cfg.wifi_tx_gain_level_gn); -+ strcat(ssv6xxx_result_buf, temp_buf); -+ sprintf(temp_buf, " wifi_tx_gain_level_b = %d\n", -+ ssv_cfg.wifi_tx_gain_level_b); -+ strcat(ssv6xxx_result_buf, temp_buf); -+ sprintf(temp_buf, " rssi_ctl = %d\n", ssv_cfg.rssi_ctl); -+ strcat(ssv6xxx_result_buf, temp_buf); -+ sprintf(temp_buf, " sr_bhvr = %d\n", ssv_cfg.sr_bhvr); -+ strcat(ssv6xxx_result_buf, temp_buf); -+ sprintf(temp_buf, " sta-mac = %02x:%02x:%02x:%02x:%02x:%02x", -+ ssv_cfg.maddr[0][0], ssv_cfg.maddr[0][1], -+ ssv_cfg.maddr[0][2], ssv_cfg.maddr[0][3], -+ ssv_cfg.maddr[0][4], ssv_cfg.maddr[0][5]); -+ strcat(ssv6xxx_result_buf, temp_buf); -+ strcat(ssv6xxx_result_buf, "\n"); -+ return 0; -+ } -+ if (argc != 4) -+ return -1; -+ for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) { -+ if (strcmp(cfg_cmds[s].cfg_cmd, argv[1]) == 0) { -+ cfg_cmds[s].translate_func(argv[3], -+ cfg_cmds[s].var, -+ cfg_cmds[s].arg); -+ strcpy(ssv6xxx_result_buf, ""); -+ return 0; -+ } -+ } -+ return -1; -+} -+ -+void *ssv_dbg_phy_table = NULL; -+EXPORT_SYMBOL(ssv_dbg_phy_table); -+u32 ssv_dbg_phy_len = 0; -+EXPORT_SYMBOL(ssv_dbg_phy_len); -+void *ssv_dbg_rf_table = NULL; -+EXPORT_SYMBOL(ssv_dbg_rf_table); -+u32 ssv_dbg_rf_len = 0; -+EXPORT_SYMBOL(ssv_dbg_rf_len); -+struct ssv_softc *ssv_dbg_sc = NULL; -+EXPORT_SYMBOL(ssv_dbg_sc); -+struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci = NULL; -+EXPORT_SYMBOL(ssv_dbg_ctrl_hci); -+struct Dump_Sta_Info { -+ char *dump_buf; -+ int sta_idx; -+}; -+static void _dump_sta_info(struct ssv_softc *sc, -+ struct ssv_vif_info *vif_info, -+ struct ssv_sta_info *sta_info, void *param) -+{ -+ char tmpbf[128]; -+ struct Dump_Sta_Info *dump_sta_info = (struct Dump_Sta_Info *)param; -+ struct ssv_sta_priv_data *priv_sta = -+ (struct ssv_sta_priv_data *)sta_info->sta->drv_priv; -+ if ((sta_info->s_flags & STA_FLAG_VALID) == 0) -+ sprintf(tmpbf, -+ " Station %d: %d is not valid\n", -+ dump_sta_info->sta_idx, priv_sta->sta_idx); -+ else -+ sprintf(tmpbf, -+ " Station %d: %d\n" -+ " Address: %02X:%02X:%02X:%02X:%02X:%02X\n" -+ " WISD: %d\n" -+ " AID: %d\n" -+ " Sleep: %d\n", -+ dump_sta_info->sta_idx, priv_sta->sta_idx, -+ sta_info->sta->addr[0], sta_info->sta->addr[1], -+ sta_info->sta->addr[2], sta_info->sta->addr[3], -+ sta_info->sta->addr[4], sta_info->sta->addr[5], -+ sta_info->hw_wsid, sta_info->aid, sta_info->sleeping); -+ dump_sta_info->sta_idx++; -+ strcat(dump_sta_info->dump_buf, tmpbf); -+} -+ -+void ssv6xxx_dump_sta_info(struct ssv_softc *sc, char *target_buf) -+{ -+ int j; -+ char tmpbf[128]; -+ struct Dump_Sta_Info dump_sta_info = { target_buf, 0 }; -+ sprintf(tmpbf, " >>>> bcast queue len[%d]\n", sc->bcast_txq.cur_qsize); -+ strcat(target_buf, tmpbf); -+ for (j = 0; j < SSV6200_MAX_VIF; j++) { -+ struct ieee80211_vif *vif = sc->vif_info[j].vif; -+ struct ssv_vif_priv_data *priv_vif; -+ struct ssv_sta_priv_data *sta_priv_iter; -+ if (vif == NULL) { -+ sprintf(tmpbf, " VIF: %d is not used.\n", j); -+ strcat(target_buf, tmpbf); -+ continue; -+ } -+ sprintf(tmpbf, -+ " VIF: %d - [%02X:%02X:%02X:%02X:%02X:%02X] type[%d] p2p[%d]\n", -+ j, vif->addr[0], vif->addr[1], vif->addr[2], -+ vif->addr[3], vif->addr[4], vif->addr[5], vif->type, -+ vif->p2p); -+ strcat(target_buf, tmpbf); -+ priv_vif = (struct ssv_vif_priv_data *)(vif->drv_priv); -+ list_for_each_entry(sta_priv_iter, &priv_vif->sta_list, list) { -+ if ((sta_priv_iter->sta_info-> -+ s_flags & STA_FLAG_VALID) == 0) { -+ sprintf(tmpbf, " VIF: %d is not valid.\n", -+ j); -+ strcat(target_buf, tmpbf); -+ continue; -+ } -+ _dump_sta_info(sc, &sc->vif_info[priv_vif->vif_idx], -+ sta_priv_iter->sta_info, &dump_sta_info); -+ } -+ } -+} -+ -+static int ssv_cmd_sta(int argc, char *argv[]) -+{ -+ if (argc >= 2 && strcmp(argv[1], "show") == 0) -+ ssv6xxx_dump_sta_info(ssv_dbg_sc, ssv6xxx_result_buf); -+ else -+ strcat(ssv6xxx_result_buf, "sta show\n\n"); -+ return 0; -+} -+ -+static int ssv_cmd_dump(int argc, char *argv[]) -+{ -+ u32 addr, regval; -+ char tmpbf[64]; -+ int s; -+ if (!ssv6xxx_result_buf) { -+ pr_warn("ssv6xxx_result_buf = NULL!!\n"); -+ return -1; -+ } -+ if (argc != 2) { -+ sprintf(tmpbf, -+ "dump [wsid|decision|phy-info|phy-reg|rf-reg]\n"); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ return 0; -+ } -+ if (strcmp(argv[1], "wsid") == 0) { -+ const u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 }; -+ const u32 reg_wsid_tid0[] = -+ { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ }; -+ const u32 reg_wsid_tid7[] = -+ { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ }; -+ const u8 *op_mode_str[] = { "STA", "AP", "AD-HOC", "WDS" }; -+ const u8 *ht_mode_str[] = -+ { "Non-HT", "HT-MF", "HT-GF", "RSVD" }; -+ for (s = 0; s < SSV_NUM_HW_STA; s++) { -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, reg_wsid[s], ®val)) ; -+ sprintf(tmpbf, -+ "==>WSID[%d]\n\tvalid[%d] qos[%d] op_mode[%s] ht_mode[%s]\n", -+ s, regval & 0x1, (regval >> 1) & 0x1, -+ op_mode_str[((regval >> 2) & 3)], -+ ht_mode_str[((regval >> 4) & 3)]); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, reg_wsid[s] + 4, ®val)) ; -+ sprintf(tmpbf, "\tMAC[%02x:%02x:%02x:%02x:", -+ (regval & 0xff), ((regval >> 8) & 0xff), -+ ((regval >> 16) & 0xff), -+ ((regval >> 24) & 0xff)); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, reg_wsid[s] + 8, ®val)) ; -+ sprintf(tmpbf, "%02x:%02x]\n", (regval & 0xff), -+ ((regval >> 8) & 0xff)); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ for (addr = reg_wsid_tid0[s]; addr <= reg_wsid_tid7[s]; -+ addr += 4) { -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, addr, ®val)) ; -+ sprintf(tmpbf, "\trx_seq%d[%d]\n", -+ ((addr - reg_wsid_tid0[s]) >> 2), -+ ((regval) & 0xffff)); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ } -+ } -+ return 0; -+ } -+ if (strcmp(argv[1], "decision") == 0) { -+ strcpy(ssv6xxx_result_buf, ">> Decision Table:\n"); -+ for (s = 0, addr = ADR_MRX_FLT_TB0; s < 16; s++, addr += 4) { -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, ®val)) ; -+ sprintf(tmpbf, " [%d]: ADDR[0x%08x] = 0x%08x\n", -+ s, addr, regval); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ } -+ strcat(ssv6xxx_result_buf, "\n\n>> Decision Mask:\n"); -+ for (s = 0, addr = ADR_MRX_FLT_EN0; s < 9; s++, addr += 4) { -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, ®val)) ; -+ sprintf(tmpbf, " [%d]: ADDR[0x%08x] = 0x%08x\n", -+ s, addr, regval); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ } -+ strcat(ssv6xxx_result_buf, "\n\n"); -+ return 0; -+ } -+ if (strcmp(argv[1], "phy-info") == 0) { -+ return 0; -+ } -+ if (strcmp(argv[1], "phy-reg") == 0) { -+ struct ssv6xxx_dev_table *raw; -+ raw = (struct ssv6xxx_dev_table *)ssv_dbg_phy_table; -+ strcpy(ssv6xxx_result_buf, ">> PHY Register Table:\n"); -+ for (s = 0; s < ssv_dbg_phy_len; s++, raw++) { -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, raw->address, ®val)) ; -+ sprintf(tmpbf, " ADDR[0x%08x] = 0x%08x\n", -+ raw->address, regval); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ } -+ strcat(ssv6xxx_result_buf, "\n\n"); -+ return 0; -+ } -+ if (strcmp(argv[1], "rf-reg") == 0) { -+ struct ssv6xxx_dev_table *raw; -+ raw = (struct ssv6xxx_dev_table *)ssv_dbg_rf_table; -+ strcpy(ssv6xxx_result_buf, ">> RF Register Table:\n"); -+ for (s = 0; s < ssv_dbg_rf_len; s++, raw++) { -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, raw->address, ®val)) ; -+ sprintf(tmpbf, " ADDR[0x%08x] = 0x%08x\n", -+ raw->address, regval); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ } -+ strcat(ssv6xxx_result_buf, "\n\n"); -+ return 0; -+ } -+ return -1; -+} -+ -+static int ssv_cmd_irq(int argc, char *argv[]) -+{ -+ char *endp; -+ u32 irq_sts; -+ if (argc >= 3 && strcmp(argv[1], "set") == 0) { -+ if (strcmp(argv[2], "mask") == 0 && argc == 4) { -+ irq_sts = simple_strtoul(argv[3], &endp, 16); -+ if (!ssv6xxx_debug_ifops->ifops->irq_setmask) { -+ sprintf(ssv6xxx_result_buf, -+ "The interface doesn't provide irq_setmask operation.\n"); -+ return 0; -+ } -+ ssv6xxx_debug_ifops->ifops-> -+ irq_setmask(ssv6xxx_debug_ifops->dev, irq_sts); -+ sprintf(ssv6xxx_result_buf, -+ "set sdio irq mask to 0x%08x\n", irq_sts); -+ return 0; -+ } -+ if (strcmp(argv[2], "enable") == 0) { -+ if (!ssv6xxx_debug_ifops->ifops->irq_enable) { -+ sprintf(ssv6xxx_result_buf, -+ "The interface doesn't provide irq_enable operation.\n"); -+ return 0; -+ } -+ ssv6xxx_debug_ifops->ifops-> -+ irq_enable(ssv6xxx_debug_ifops->dev); -+ strcpy(ssv6xxx_result_buf, "enable sdio irq.\n"); -+ return 0; -+ } -+ if (strcmp(argv[2], "disable") == 0) { -+ if (!ssv6xxx_debug_ifops->ifops->irq_disable) { -+ sprintf(ssv6xxx_result_buf, -+ "The interface doesn't provide irq_disable operation.\n"); -+ return 0; -+ } -+ ssv6xxx_debug_ifops->ifops-> -+ irq_disable(ssv6xxx_debug_ifops->dev, false); -+ strcpy(ssv6xxx_result_buf, "disable sdio irq.\n"); -+ return 0; -+ } -+ return -1; -+ } else if (argc == 3 && strcmp(argv[1], "get") == 0) { -+ if (strcmp(argv[2], "mask") == 0) { -+ if (!ssv6xxx_debug_ifops->ifops->irq_getmask) { -+ sprintf(ssv6xxx_result_buf, -+ "The interface doesn't provide irq_getmask operation.\n"); -+ return 0; -+ } -+ ssv6xxx_debug_ifops->ifops-> -+ irq_getmask(ssv6xxx_debug_ifops->dev, &irq_sts); -+ sprintf(ssv6xxx_result_buf, -+ "sdio irq mask: 0x%08x, int_mask=0x%08x\n", -+ irq_sts, ssv_dbg_ctrl_hci->int_mask); -+ return 0; -+ } -+ if (strcmp(argv[2], "status") == 0) { -+ if (!ssv6xxx_debug_ifops->ifops->irq_getstatus) { -+ sprintf(ssv6xxx_result_buf, -+ "The interface doesn't provide irq_getstatus operation.\n"); -+ return 0; -+ } -+ ssv6xxx_debug_ifops->ifops-> -+ irq_getstatus(ssv6xxx_debug_ifops->dev, &irq_sts); -+ sprintf(ssv6xxx_result_buf, "sdio irq status: 0x%08x\n", -+ irq_sts); -+ return 0; -+ } -+ return -1; -+ } else { -+ sprintf(ssv6xxx_result_buf, -+ "irq [set|get] [mask|enable|disable|status]\n"); -+ } -+ return 0; -+} -+ -+static int ssv_cmd_mac(int argc, char *argv[]) -+{ -+ char temp_str[128], *endp; -+ u32 s; -+ int i; -+ if (argc == 3 && !strcmp(argv[1], "wsid") && !strcmp(argv[2], "show")) { -+ for (s = 0; s < SSV_NUM_HW_STA; s++) { -+ } -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "rx")) { -+ if (!strcmp(argv[2], "enable")) { -+ ssv_dbg_sc->dbg_rx_frame = 1; -+ } else { -+ ssv_dbg_sc->dbg_rx_frame = 0; -+ } -+ sprintf(temp_str, " dbg_rx_frame %d\n", -+ ssv_dbg_sc->dbg_rx_frame); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "tx")) { -+ if (!strcmp(argv[2], "enable")) { -+ ssv_dbg_sc->dbg_tx_frame = 1; -+ } else { -+ ssv_dbg_sc->dbg_tx_frame = 0; -+ } -+ sprintf(temp_str, " dbg_tx_frame %d\n", -+ ssv_dbg_sc->dbg_tx_frame); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "rxq") -+ && !strcmp(argv[2], "show")) { -+ sprintf(temp_str, ">> MAC RXQ: (%s)\n cur_qsize=%d\n", -+ ((ssv_dbg_sc-> -+ sc_flags & SC_OP_OFFCHAN) ? "off channel" : -+ "on channel"), ssv_dbg_sc->rx.rxq_count); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } else if (argc == 4 && !strcmp(argv[1], "set") -+ && !strcmp(argv[2], "rate")) { -+ if (strcmp(argv[3], "auto") == 0) { -+ ssv_dbg_sc->sc_flags &= ~SC_OP_FIXED_RATE; -+ return 0; -+ } -+ i = simple_strtoul(argv[3], &endp, 10); -+ if (i < 0 || i > 38) { -+ strcpy(ssv6xxx_result_buf, " Invalid rat index !!\n"); -+ return -1; -+ } -+ ssv_dbg_sc->max_rate_idx = i; -+ ssv_dbg_sc->sc_flags |= SC_OP_FIXED_RATE; -+ sprintf(temp_str, " Set rate to index %d\n", i); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "get") -+ && !strcmp(argv[2], "rate")) { -+ if (ssv_dbg_sc->sc_flags & SC_OP_FIXED_RATE) -+ sprintf(temp_str, " Current Rate Index: %d\n", -+ ssv_dbg_sc->max_rate_idx); -+ else -+ sprintf(temp_str, " Current Rate Index: auto\n"); -+ strcpy(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } else { -+ sprintf(temp_str, "mac [security|wsid|rxq] [show]\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "mac [set|get] [rate] [auto|idx]\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "mac [rx|tx] [eable|disable]\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ return 0; -+} -+ -+#ifdef CONFIG_IRQ_DEBUG_COUNT -+void print_irq_count(void) -+{ -+ char temp_str[512]; -+ sprintf(temp_str, "irq debug (%s)\n", -+ ssv_dbg_ctrl_hci->irq_enable ? "enable" : "disable"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "total irq (%d)\n", ssv_dbg_ctrl_hci->irq_count); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "invalid irq (%d)\n", -+ ssv_dbg_ctrl_hci->invalid_irq_count); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "rx irq (%d)\n", ssv_dbg_ctrl_hci->rx_irq_count); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "tx irq (%d)\n", ssv_dbg_ctrl_hci->tx_irq_count); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "real tx count irq (%d)\n", -+ ssv_dbg_ctrl_hci->real_tx_irq_count); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "tx packet count (%d)\n", -+ ssv_dbg_ctrl_hci->irq_tx_pkt_count); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "rx packet (%d)\n", -+ ssv_dbg_ctrl_hci->irq_rx_pkt_count); -+ strcat(ssv6xxx_result_buf, temp_str); -+} -+#endif -+void print_isr_info(void) -+{ -+ char temp_str[512]; -+ sprintf(temp_str, ">>>> HCI Calculate ISR TIME(%s) unit:us\n", -+ ((ssv_dbg_ctrl_hci->isr_summary_eable) ? "enable" : "disable")); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "isr_routine_time(%d)\n", -+ jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_routine_time)); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "isr_tx_time(%d)\n", -+ jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_tx_time)); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "isr_rx_time(%d)\n", -+ jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_time)); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "isr_idle_time(%d)\n", -+ jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_idle_time)); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "isr_rx_idle_time(%d)\n", -+ jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_idle_time)); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "isr_miss_cnt(%d)\n", ssv_dbg_ctrl_hci->isr_miss_cnt); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "prev_isr_jiffes(%lu)\n", -+ ssv_dbg_ctrl_hci->prev_isr_jiffes); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "prev_rx_isr_jiffes(%lu)\n", -+ ssv_dbg_ctrl_hci->prev_rx_isr_jiffes); -+ strcat(ssv6xxx_result_buf, temp_str); -+} -+ -+static int ssv_cmd_hci(int argc, char *argv[]) -+{ -+ struct ssv_hw_txq *txq; -+ char temp_str[512]; -+ int s, ac = 0; -+ if (argc == 3 && !strcmp(argv[1], "txq") && !strcmp(argv[2], "show")) { -+ for (s = 0; s < WMM_NUM_AC; s++) { -+ if (ssv_dbg_sc != NULL) -+ ac = ssv_dbg_sc->tx.ac_txqid[s]; -+ txq = &ssv_dbg_ctrl_hci->hw_txq[s]; -+ sprintf(temp_str, ">> txq[%d]", txq->txq_no); -+ if (ssv_dbg_sc != NULL) -+ sprintf(temp_str, "(%s): ", -+ ((ssv_dbg_sc-> -+ sc_flags & SC_OP_OFFCHAN) ? -+ "off channel" : "on channel")); -+ sprintf(temp_str, "cur_qsize=%d\n", -+ skb_queue_len(&txq->qhead)); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, -+ " max_qsize=%d, pause=%d, resume_thres=%d", -+ txq->max_qsize, txq->paused, txq->resum_thres); -+ if (ssv_dbg_sc != NULL) -+ sprintf(temp_str, " flow_control[%d]\n", -+ !!(ssv_dbg_sc->tx. -+ flow_ctrl_status & (1 << ac))); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, " Total %d frame sent\n", -+ txq->tx_pkt); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ sprintf(temp_str, -+ ">> HCI Debug Counters:\n read_rs0_info_fail=%d, read_rs1_info_fail=%d\n", -+ ssv_dbg_ctrl_hci->read_rs0_info_fail, -+ ssv_dbg_ctrl_hci->read_rs1_info_fail); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, -+ " rx_work_running=%d, isr_running=%d, xmit_running=%d\n", -+ ssv_dbg_ctrl_hci->rx_work_running, -+ ssv_dbg_ctrl_hci->isr_running, -+ ssv_dbg_ctrl_hci->xmit_running); -+ strcat(ssv6xxx_result_buf, temp_str); -+ if (ssv_dbg_sc != NULL) -+ sprintf(temp_str, " flow_ctrl_status=%08x\n", -+ ssv_dbg_sc->tx.flow_ctrl_status); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "rxq") -+ && !strcmp(argv[2], "show")) { -+ sprintf(temp_str, ">> HCI RX Queue (%s): cur_qsize=%d\n", -+ ((ssv_dbg_sc-> -+ sc_flags & SC_OP_OFFCHAN) ? "off channel" : -+ "on channel"), ssv_dbg_ctrl_hci->rx_pkt); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "isr_time") -+ && !strcmp(argv[2], "start")) { -+ ssv_dbg_ctrl_hci->isr_summary_eable = 1; -+ ssv_dbg_ctrl_hci->isr_routine_time = 0; -+ ssv_dbg_ctrl_hci->isr_tx_time = 0; -+ ssv_dbg_ctrl_hci->isr_rx_time = 0; -+ ssv_dbg_ctrl_hci->isr_idle_time = 0; -+ ssv_dbg_ctrl_hci->isr_rx_idle_time = 0; -+ ssv_dbg_ctrl_hci->isr_miss_cnt = 0; -+ ssv_dbg_ctrl_hci->prev_isr_jiffes = 0; -+ ssv_dbg_ctrl_hci->prev_rx_isr_jiffes = 0; -+ print_isr_info(); -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "isr_time") -+ && !strcmp(argv[2], "stop")) { -+ ssv_dbg_ctrl_hci->isr_summary_eable = 0; -+ print_isr_info(); -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "isr_time") -+ && !strcmp(argv[2], "show")) { -+ print_isr_info(); -+ return 0; -+ } -+#ifdef CONFIG_IRQ_DEBUG_COUNT -+ else if (argc == 3 && !strcmp(argv[1], "isr_debug") -+ && !strcmp(argv[2], "reset")) { -+ ssv_dbg_ctrl_hci->irq_enable = 0; -+ ssv_dbg_ctrl_hci->irq_count = 0; -+ ssv_dbg_ctrl_hci->invalid_irq_count = 0; -+ ssv_dbg_ctrl_hci->tx_irq_count = 0; -+ ssv_dbg_ctrl_hci->real_tx_irq_count = 0; -+ ssv_dbg_ctrl_hci->rx_irq_count = 0; -+ ssv_dbg_ctrl_hci->isr_rx_idle_time = 0; -+ ssv_dbg_ctrl_hci->irq_rx_pkt_count = 0; -+ ssv_dbg_ctrl_hci->irq_tx_pkt_count = 0; -+ strcat(ssv6xxx_result_buf, "irq debug reset count\n"); -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "isr_debug") -+ && !strcmp(argv[2], "show")) { -+ print_irq_count(); -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "isr_debug") -+ && !strcmp(argv[2], "stop")) { -+ ssv_dbg_ctrl_hci->irq_enable = 0; -+ strcat(ssv6xxx_result_buf, "irq debug stop\n"); -+ return 0; -+ } else if (argc == 3 && !strcmp(argv[1], "isr_debug") -+ && !strcmp(argv[2], "start")) { -+ ssv_dbg_ctrl_hci->irq_enable = 1; -+ strcat(ssv6xxx_result_buf, "irq debug start\n"); -+ return 0; -+ } -+#endif -+ else { -+ strcat(ssv6xxx_result_buf, -+ "hci [txq|rxq] [show]\nhci [isr_time] [start|stop|show]\n\n"); -+ return 0; -+ } -+ return -1; -+} -+ -+static int ssv_cmd_hwq(int argc, char *argv[]) -+{ -+#undef GET_FFO0_CNT -+#undef GET_FFO1_CNT -+#undef GET_FFO2_CNT -+#undef GET_FFO3_CNT -+#undef GET_FFO4_CNT -+#undef GET_FFO5_CNT -+#undef GET_FFO6_CNT -+#undef GET_FFO7_CNT -+#undef GET_FFO8_CNT -+#undef GET_FFO9_CNT -+#undef GET_FFO10_CNT -+#undef GET_FFO11_CNT -+#undef GET_FFO12_CNT -+#undef GET_FFO13_CNT -+#undef GET_FFO14_CNT -+#undef GET_FFO15_CNT -+#undef GET_FF0_CNT -+#undef GET_FF1_CNT -+#undef GET_FF3_CNT -+#undef GET_FF5_CNT -+#undef GET_FF6_CNT -+#undef GET_FF7_CNT -+#undef GET_FF8_CNT -+#undef GET_FF9_CNT -+#undef GET_FF10_CNT -+#undef GET_FF11_CNT -+#undef GET_FF12_CNT -+#undef GET_FF13_CNT -+#undef GET_FF14_CNT -+#undef GET_FF15_CNT -+#undef GET_FF4_CNT -+#undef GET_FF2_CNT -+#undef GET_TX_ID_ALC_LEN -+#undef GET_RX_ID_ALC_LEN -+#undef GET_AVA_TAG -+#define GET_FFO0_CNT ((value & 0x0000001f ) >> 0) -+#define GET_FFO1_CNT ((value & 0x000003e0 ) >> 5) -+#define GET_FFO2_CNT ((value & 0x00000c00 ) >> 10) -+#define GET_FFO3_CNT ((value & 0x000f8000 ) >> 15) -+#define GET_FFO4_CNT ((value & 0x00300000 ) >> 20) -+#define GET_FFO5_CNT ((value & 0x0e000000 ) >> 25) -+#define GET_FFO6_CNT ((value1 & 0x0000000f ) >> 0) -+#define GET_FFO7_CNT ((value1 & 0x000003e0 ) >> 5) -+#define GET_FFO8_CNT ((value1 & 0x00007c00 ) >> 10) -+#define GET_FFO9_CNT ((value1 & 0x000f8000 ) >> 15) -+#define GET_FFO10_CNT ((value1 & 0x00f00000 ) >> 20) -+#define GET_FFO11_CNT ((value1 & 0x3e000000 ) >> 25) -+#define GET_FFO12_CNT ((value2 & 0x00000007 ) >> 0) -+#define GET_FFO13_CNT ((value2 & 0x00000060 ) >> 5) -+#define GET_FFO14_CNT ((value2 & 0x00000c00 ) >> 10) -+#define GET_FFO15_CNT ((value2 & 0x001f8000 ) >> 15) -+#define GET_FF0_CNT ((value & 0x0000001f ) >> 0) -+#define GET_FF1_CNT ((value & 0x000001e0 ) >> 5) -+#define GET_FF3_CNT ((value & 0x00003800 ) >> 11) -+#define GET_FF5_CNT ((value & 0x000e0000 ) >> 17) -+#define GET_FF6_CNT ((value & 0x00700000 ) >> 20) -+#define GET_FF7_CNT ((value & 0x03800000 ) >> 23) -+#define GET_FF8_CNT ((value & 0x1c000000 ) >> 26) -+#define GET_FF9_CNT ((value & 0xe0000000 ) >> 29) -+#define GET_FF10_CNT ((value1 & 0x00000007 ) >> 0) -+#define GET_FF11_CNT ((value1 & 0x00000038 ) >> 3) -+#define GET_FF12_CNT ((value1 & 0x000001c0 ) >> 6) -+#define GET_FF13_CNT ((value1 & 0x00000600 ) >> 9) -+#define GET_FF14_CNT ((value1 & 0x00001800 ) >> 11) -+#define GET_FF15_CNT ((value1 & 0x00006000 ) >> 13) -+#define GET_FF4_CNT ((value1 & 0x000f8000 ) >> 15) -+#define GET_FF2_CNT ((value1 & 0x00700000 ) >> 20) -+#define GET_TX_ID_ALC_LEN ((value & 0x0003fe00 ) >> 9) -+#define GET_RX_ID_ALC_LEN ((value & 0x07fc0000 ) >> 18) -+#define GET_AVA_TAG ((value1 & 0x01ff0000 ) >> 16) -+ u32 addr, value, value1, value2; -+ char temp_str[512]; -+ addr = ADR_RD_FFOUT_CNT1; -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ; -+ addr = ADR_RD_FFOUT_CNT2; -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ; -+ addr = ADR_RD_FFOUT_CNT3; -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value2)) ; -+ sprintf(temp_str, -+ "\n[TAG] MCU - HCI - SEC - RX - MIC - TX0 - TX1 - TX2 - TX3 - TX4 - SEC - MIC - TSH\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, -+ "OUTPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n", -+ GET_FFO0_CNT, GET_FFO1_CNT, GET_FFO3_CNT, GET_FFO4_CNT, -+ GET_FFO5_CNT, GET_FFO6_CNT, GET_FFO7_CNT, GET_FFO8_CNT, -+ GET_FFO9_CNT, GET_FFO10_CNT, GET_FFO11_CNT, GET_FFO12_CNT, -+ GET_FFO15_CNT); -+ strcat(ssv6xxx_result_buf, temp_str); -+ addr = ADR_RD_IN_FFCNT1; -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ; -+ addr = ADR_RD_IN_FFCNT2; -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ; -+ sprintf(temp_str, -+ "INPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n", -+ GET_FF0_CNT, GET_FF1_CNT, GET_FF3_CNT, GET_FF4_CNT, GET_FF5_CNT, -+ GET_FF6_CNT, GET_FF7_CNT, GET_FF8_CNT, GET_FF9_CNT, -+ GET_FF10_CNT, GET_FF11_CNT, GET_FF12_CNT, GET_FF15_CNT); -+ strcat(ssv6xxx_result_buf, temp_str); -+ addr = ADR_ID_LEN_THREADSHOLD2; -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ; -+ addr = ADR_TAG_STATUS; -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ; -+ sprintf(temp_str, "TX[%d]RX[%d]AVA[%d]\n", GET_TX_ID_ALC_LEN, -+ GET_RX_ID_ALC_LEN, GET_AVA_TAG); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+} -+ -+#ifdef CONFIG_P2P_NOA -+static struct ssv6xxx_p2p_noa_param cmd_noa_param = { -+ 50, -+ 100, -+ 0x12345678, -+ 1, -+ 255, -+ {0x4c, 0xe6, 0x76, 0xa2, 0x4e, 0x7c} -+}; -+ -+void noa_dump(char *temp_str) -+{ -+ sprintf(temp_str, -+ "NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]\n", -+ cmd_noa_param.enable, cmd_noa_param.interval, -+ cmd_noa_param.duration, cmd_noa_param.start_time, -+ cmd_noa_param.count, cmd_noa_param.addr[0], -+ cmd_noa_param.addr[1], cmd_noa_param.addr[2], -+ cmd_noa_param.addr[3], cmd_noa_param.addr[4], -+ cmd_noa_param.addr[5]); -+ strcat(ssv6xxx_result_buf, temp_str); -+} -+ -+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc, -+ struct ssv6xxx_p2p_noa_param *p2p_noa_param) -+{ -+ struct sk_buff *skb; -+ struct cfg_host_cmd *host_cmd; -+ int retry_cnt = 5; -+ skb = -+ ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + -+ sizeof(struct ssv6xxx_p2p_noa_param)); -+ skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param); -+ skb->len = skb->data_len; -+ host_cmd = (struct cfg_host_cmd *)skb->data; -+ host_cmd->c_type = HOST_CMD; -+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA; -+ host_cmd->len = skb->data_len; -+ memcpy(host_cmd->dat32, p2p_noa_param, -+ sizeof(struct ssv6xxx_p2p_noa_param)); -+ while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) { -+ pr_debug("NOA cmd retry=%d\n", retry_cnt); -+ retry_cnt--; -+ } -+ ssvdevice_skb_free(skb); -+} -+ -+static int ssv_cmd_noa(int argc, char *argv[]) -+{ -+ char temp_str[512]; -+ char *endp; -+ if (argc == 2 && !strcmp(argv[1], "show")) { -+ ; -+ } else if (argc == 3 && !strcmp(argv[1], "duration")) { -+ cmd_noa_param.duration = simple_strtoul(argv[2], &endp, 0); -+ } else if (argc == 3 && !strcmp(argv[1], "interval")) { -+ cmd_noa_param.interval = simple_strtoul(argv[2], &endp, 0); -+ } else if (argc == 3 && !strcmp(argv[1], "start")) { -+ cmd_noa_param.start_time = simple_strtoul(argv[2], &endp, 0); -+ } else if (argc == 3 && !strcmp(argv[1], "enable")) { -+ cmd_noa_param.enable = simple_strtoul(argv[2], &endp, 0); -+ } else if (argc == 3 && !strcmp(argv[1], "count")) { -+ cmd_noa_param.count = simple_strtoul(argv[2], &endp, 0); -+ } else if (argc == 8 && !strcmp(argv[1], "addr")) { -+ cmd_noa_param.addr[0] = simple_strtoul(argv[2], &endp, 16); -+ cmd_noa_param.addr[1] = simple_strtoul(argv[3], &endp, 16); -+ cmd_noa_param.addr[2] = simple_strtoul(argv[4], &endp, 16); -+ cmd_noa_param.addr[3] = simple_strtoul(argv[5], &endp, 16); -+ cmd_noa_param.addr[4] = simple_strtoul(argv[6], &endp, 16); -+ cmd_noa_param.addr[5] = simple_strtoul(argv[7], &endp, 16); -+ } else if (argc == 2 && !strcmp(argv[1], "send")) { -+ ssv6xxx_send_noa_cmd(ssv_dbg_sc, &cmd_noa_param); -+ } else { -+ sprintf(temp_str, "## wrong command\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } -+ noa_dump(temp_str); -+ return 0; -+} -+#endif -+static int ssv_cmd_mib(int argc, char *argv[]) -+{ -+ u32 addr, value; -+ char temp_str[512]; -+ int i; -+ if (argc == 2 && !strcmp(argv[1], "reset")) { -+ addr = MIB_REG_BASE; -+ value = 0x0; -+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ; -+ value = 0xffffffff; -+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ; -+ value = 0x0; -+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ; -+ value = 0x100000; -+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ; -+ value = 0x0; -+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ; -+ value = 0x100000; -+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ; -+ value = 0x0; -+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ; -+ value = 0x80000000; -+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ; -+ sprintf(temp_str, " => MIB reseted\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else if (argc == 2 && !strcmp(argv[1], "list")) { -+ addr = MIB_REG_BASE; -+ for (i = 0; i < 120; i++, addr += 4) { -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ; -+ sprintf(temp_str, "%08x ", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ if (((i + 1) & 0x07) == 0) -+ strcat(ssv6xxx_result_buf, "\n"); -+ } -+ strcat(ssv6xxx_result_buf, "\n"); -+ } else if (argc == 2 && strcmp(argv[1], "rx") == 0) { -+ sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t\t%-10s\n", -+ "MRX_FCS_SUCC", "MRX_FCS_ERR", "MRX_ALC_FAIL", -+ "MRX_MISS"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, ADR_MRX_FCS_SUCC, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_FCS_ERR, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, ADR_MRX_ALC_FAIL, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MISS, &value)) { -+ sprintf(temp_str, "[%08x]\n", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t%-10s\n", -+ "MRX_MB_MISS", "MRX_NIDLE_MISS", -+ "DBG_LEN_ALC_FAIL", "DBG_LEN_CRC_FAIL"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MB_MISS, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, ADR_MRX_NIDLE_MISS, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, ADR_DBG_LEN_ALC_FAIL, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, ADR_DBG_LEN_CRC_FAIL, &value)) { -+ sprintf(temp_str, "[%08x]\n\n", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_PASS, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_FAIL, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL1, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL2, &value)) { -+ sprintf(temp_str, "[%08x]\n\n", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "PHY B mode:\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n", -+ "CRC error", "CCA", "counter"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023E8, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value & 0xffff); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023EC, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "PHY G/N mode:\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n", -+ "CRC error", "CCA", "counter"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043E8, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", value & 0xffff); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043EC, &value)) { -+ sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ } else { -+ sprintf(temp_str, "mib [reset|list|rx]\n\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ return 0; -+} -+ -+static int ssv_cmd_sdio(int argc, char *argv[]) -+{ -+ u32 addr, value; -+ char temp_str[512], *endp; -+ int ret = 0; -+ if (argc == 4 && !strcmp(argv[1], "reg") && !strcmp(argv[2], "r")) { -+ addr = simple_strtoul(argv[3], &endp, 16); -+ if (!ssv6xxx_debug_ifops->ifops->cmd52_read) { -+ sprintf(temp_str, -+ "The interface doesn't provide cmd52 read\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } -+ ret = -+ ssv6xxx_debug_ifops->ifops->cmd52_read(ssv6xxx_debug_ifops-> -+ dev, addr, &value); -+ if (ret >= 0) { -+ sprintf(temp_str, " ==> %x\n", value); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } -+ } else if (argc == 5 && !strcmp(argv[1], "reg") -+ && !strcmp(argv[2], "w")) { -+ addr = simple_strtoul(argv[3], &endp, 16); -+ value = simple_strtoul(argv[4], &endp, 16); -+ if (!ssv6xxx_debug_ifops->ifops->cmd52_write) { -+ sprintf(temp_str, -+ "The interface doesn't provide cmd52 write\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } -+ ret = -+ ssv6xxx_debug_ifops->ifops-> -+ cmd52_write(ssv6xxx_debug_ifops->dev, addr, value); -+ if (ret >= 0) { -+ sprintf(temp_str, " ==> write odne.\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } -+ } -+ sprintf(temp_str, "sdio cmd52 fail: %d\n", ret); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+} -+ -+static struct ssv6xxx_iqk_cfg cmd_iqk_cfg = { -+ SSV6XXX_IQK_CFG_XTAL_26M, -+ SSV6XXX_IQK_CFG_PA_DEF, -+ 0, -+ 0, -+ 26, -+ 3, -+ 0x75, -+ 0x75, -+ 0x80, -+ 0x80, -+ SSV6XXX_IQK_CMD_INIT_CALI, -+ {SSV6XXX_IQK_TEMPERATURE -+ + SSV6XXX_IQK_RXDC -+ + SSV6XXX_IQK_RXRC -+ + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ}, -+}; -+ -+static int ssv_cmd_iqk(int argc, char *argv[]) -+{ -+ char temp_str[512], *endp; -+ struct sk_buff *skb; -+ struct cfg_host_cmd *host_cmd; -+ u32 rxcnt_total, rxcnt_error; -+ sprintf(temp_str, "# got iqk command\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ if ((argc == 3) && (strcmp(argv[1], "cfg-pa") == 0)) { -+ cmd_iqk_cfg.cfg_pa = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## set cfg_pa as %d\n", cmd_iqk_cfg.cfg_pa); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } else if ((argc == 3) && (strcmp(argv[1], "cfg-tssi-trgt") == 0)) { -+ cmd_iqk_cfg.cfg_tssi_trgt = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## set cfg_tssi_trgt as %d\n", -+ cmd_iqk_cfg.cfg_tssi_trgt); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } else if ((argc == 3) && (strcmp(argv[1], "init-cali") == 0)) { -+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_INIT_CALI; -+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## do init-cali\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else if ((argc == 3) && (strcmp(argv[1], "rtbl-load") == 0)) { -+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD; -+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## do rtbl-load\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else if ((argc == 3) && (strcmp(argv[1], "rtbl-load-def") == 0)) { -+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD_DEF; -+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## do rtbl-load\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else if ((argc == 3) && (strcmp(argv[1], "rtbl-reset") == 0)) { -+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_RESET; -+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## do rtbl-reset\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else if ((argc == 3) && (strcmp(argv[1], "rtbl-set") == 0)) { -+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_SET; -+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## do rtbl-set\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else if ((argc == 3) && (strcmp(argv[1], "rtbl-export") == 0)) { -+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_EXPORT; -+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## do rtbl-export\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else if ((argc == 3) && (strcmp(argv[1], "tk-evm") == 0)) { -+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_EVM; -+ cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## do tk-evm\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else if ((argc == 3) && (strcmp(argv[1], "tk-tone") == 0)) { -+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_TONE; -+ cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## do tk-tone\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else if ((argc == 3) && (strcmp(argv[1], "channel") == 0)) { -+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_CHCH; -+ cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0); -+ sprintf(temp_str, "## do change channel\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else if ((argc == 2) && (strcmp(argv[1], "tk-rxcnt-report") == 0)) { -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, 0xCE0043E8, &rxcnt_error)) ; -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, 0xCE0043EC, &rxcnt_total)) ; -+ sprintf(temp_str, "## GN Rx error rate = (%06d/%06d)\n", -+ rxcnt_error, rxcnt_total); -+ strcat(ssv6xxx_result_buf, temp_str); -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, 0xCE0023E8, &rxcnt_error)) ; -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, 0xCE0023EC, &rxcnt_total)) ; -+ sprintf(temp_str, "## B Rx error rate = (%06d/%06d)\n", -+ rxcnt_error, rxcnt_total); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } else { -+ sprintf(temp_str, "## invalid iqk command\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "## cmd: cfg-pa/cfg-tssi-trgt\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, -+ "## cmd: init-cali/rtbl-load/rtbl-load-def/rtbl-reset/rtbl-set/rtbl-export/tk-evm/tk-tone/tk-channel\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "## fx_sel: 0x0008: RXDC\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, " 0x0010: RXRC\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, " 0x0020: TXDC\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, " 0x0040: TXIQ\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, " 0x0080: RXIQ\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, " 0x0100: TSSI\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, " 0x0200: PAPD\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+ } -+ skb = -+ ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN + -+ PHY_SETTING_SIZE + RF_SETTING_SIZE); -+ if (skb == NULL) { -+ pr_err("ssv command ssvdevice_skb_alloc failure\n"); -+ return 0; -+ } -+ if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) || -+ (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) { -+ pr_err("Please check RF or PHY table size\n"); -+ BUG_ON(1); -+ return 0; -+ } -+ skb->data_len = -+ HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE; -+ skb->len = skb->data_len; -+ host_cmd = (struct cfg_host_cmd *)skb->data; -+ host_cmd->c_type = HOST_CMD; -+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI; -+ host_cmd->len = skb->data_len; -+ cmd_iqk_cfg.phy_tbl_size = PHY_SETTING_SIZE; -+ cmd_iqk_cfg.rf_tbl_size = RF_SETTING_SIZE; -+ memcpy(host_cmd->dat32, &cmd_iqk_cfg, IQK_CFG_LEN); -+ memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE); -+ memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, asic_rf_setting, -+ RF_SETTING_SIZE); -+ if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) { -+ sprintf(temp_str, "## hci send cmd success\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } else { -+ sprintf(temp_str, "## hci send cmd fail\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ } -+ ssvdevice_skb_free(skb); -+ return 0; -+} -+ -+#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ -+ (((a) & 0xff00ff00) >> 8)) -+#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) -+static int ssv_cmd_version(int argc, char *argv[]) -+{ -+ char temp_str[256]; -+ u32 regval; -+ u64 chip_tag = 0; -+ char chip_id[24] = ""; -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_1, ®val)) ; -+ chip_tag = ((u64) regval << 32); -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_0, ®val)) ; -+ chip_tag |= (regval); -+ sprintf(temp_str, "CHIP TAG: %llx \n", chip_tag); -+ strcat(ssv6xxx_result_buf, temp_str); -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_3, ®val)) ; -+ *((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval); -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_2, ®val)) ; -+ *((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval); -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_1, ®val)) ; -+ *((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval); -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_0, ®val)) ; -+ *((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval); -+ sprintf(temp_str, "CHIP ID: %s \n", chip_id); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "# current Software mac version: %d\n", -+ ssv_root_version); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "SVN ROOT URL %s \n", SSV_ROOT_URl); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "COMPILER HOST %s \n", COMPILERHOST); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "COMPILER DATE %s \n", COMPILERDATE); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "COMPILER OS %s \n", COMPILEROS); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "COMPILER OS ARCH %s \n", COMPILEROSARCH); -+ strcat(ssv6xxx_result_buf, temp_str); -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, FW_VERSION_REG, ®val)) ; -+ sprintf(temp_str, "Firmware image version: %d\n", regval); -+ strcat(ssv6xxx_result_buf, temp_str); -+ sprintf(temp_str, "\n[Compiler Option!!]\n"); -+ strcat(ssv6xxx_result_buf, temp_str); -+ return 0; -+} -+ -+static int ssv_cmd_tool(int argc, char *argv[]) -+{ -+ u32 addr, value, count; -+ char tmpbf[12], *endp; -+ int s; -+ if (argc == 4 && strcmp(argv[1], "w") == 0) { -+ addr = simple_strtoul(argv[2], &endp, 16); -+ value = simple_strtoul(argv[3], &endp, 16); -+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ; -+ sprintf(ssv6xxx_result_buf, "ok"); -+ return 0; -+ } -+ if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) { -+ count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10); -+ addr = simple_strtoul(argv[2], &endp, 16); -+ for (s = 0; s < count; s++, addr += 4) { -+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ; -+ sprintf(tmpbf, "%08x\n", value); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ } -+ return 0; -+ } -+ return -1; -+} -+ -+struct _ssv6xxx_txtput { -+ struct task_struct *txtput_tsk; -+ struct sk_buff *skb; -+ u32 size_per_frame; -+ u32 loop_times; -+ u32 occupied_tx_pages; -+}; -+struct _ssv6xxx_txtput *ssv6xxx_txtput; -+struct _ssv6xxx_txtput ssv_txtput = { NULL, NULL, 0, 0, 0 }; -+ -+static int txtput_thread_m2(void *data) -+{ -+#define Q_DELAY_MS 20 -+ struct sk_buff *skb = NULL; -+ struct ssv6200_tx_desc *tx_desc; -+ int qlen = 0, max_qlen, q_delay_urange[2]; -+ max_qlen = -+ (200 * 1000 / 8 * Q_DELAY_MS) / ssv6xxx_txtput->size_per_frame; -+ q_delay_urange[0] = Q_DELAY_MS * 1000; -+ q_delay_urange[1] = q_delay_urange[0] + 1000; -+ pr_debug("max_qlen: %d\n", max_qlen); -+ while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) { -+ ssv6xxx_txtput->loop_times--; -+ skb = ssvdevice_skb_alloc(ssv6xxx_txtput->size_per_frame); -+ if (skb == NULL) { -+ pr_debug("ssv command txtput_generate_m2 " -+ "ssvdevice_skb_alloc fail!!!\n"); -+ goto end; -+ } -+ skb->data_len = ssv6xxx_txtput->size_per_frame; -+ skb->len = ssv6xxx_txtput->size_per_frame; -+ tx_desc = (struct ssv6200_tx_desc *)skb->data; -+ memset((void *)tx_desc, 0xff, SSV6XXX_TX_DESC_LEN); -+ tx_desc->len = skb->len; -+ tx_desc->c_type = M2_TXREQ; -+ tx_desc->fCmd = (M_ENG_CPU << 4) | M_ENG_HWHCI; -+ tx_desc->reason = ID_TRAP_SW_TXTPUT; -+ qlen = ssv_dbg_ctrl_hci->shi->hci_ops->hci_tx(skb, 0, 0); -+ if (qlen >= max_qlen) { -+ usleep_range(q_delay_urange[0], q_delay_urange[1]); -+ } -+ } -+ end: -+ ssv6xxx_txtput->txtput_tsk = NULL; -+ return 0; -+} -+ -+static int txtput_thread(void *data) -+{ -+ struct sk_buff *skb = ssv6xxx_txtput->skb; -+ struct ssv6xxx_hci_txq_info2 txq_info2; -+ u32 ret = 0, free_tx_page; -+ int send_cnt; -+ unsigned long start_time, end_time, throughput, time_elapse; -+ throughput = -+ ssv6xxx_txtput->loop_times * ssv6xxx_txtput->size_per_frame * 8; -+ start_time = jiffies; -+ while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) { -+ ret = -+ SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_TX_ID_ALL_INFO2, -+ (u32 *) & txq_info2); -+ if (ret < 0) { -+ pr_debug("%s, read ADR_TX_ID_ALL_INFO2 failed\n", -+ __func__); -+ goto end; -+ } -+ free_tx_page = -+ SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page; -+ send_cnt = free_tx_page / ssv6xxx_txtput->occupied_tx_pages; -+ while (send_cnt > 0 && ssv6xxx_txtput->loop_times > 0) { -+ send_cnt--; -+ ssv6xxx_txtput->loop_times--; -+ ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb); -+ } -+ } -+ end_time = jiffies; -+ ssvdevice_skb_free(skb); -+ time_elapse = ((end_time - start_time) * 1000) / HZ; -+ if (time_elapse > 0) { -+ throughput = throughput / time_elapse; -+ pr_debug("duration %ldms, avg. throughput %d Kbps\n", time_elapse, -+ (int)throughput); -+ } -+ end: -+ ssv6xxx_txtput->txtput_tsk = NULL; -+ return 0; -+} -+ -+int txtput_generate_m2(u32 size_per_frame, u32 loop_times) -+{ -+ ssv6xxx_txtput->size_per_frame = size_per_frame; -+ ssv6xxx_txtput->loop_times = loop_times; -+ ssv6xxx_txtput->txtput_tsk = -+ kthread_run(txtput_thread_m2, NULL, "txtput_thread_m2"); -+ return 0; -+} -+ -+int txtput_generate_host_cmd(u32 size_per_frame, u32 loop_times) -+{ -+#define PAGESIZE 256 -+ struct cfg_host_cmd *host_cmd; -+ struct sk_buff *skb; -+ skb = ssvdevice_skb_alloc(size_per_frame); -+ if (skb == NULL) { -+ pr_debug -+ ("ssv command txtput_generate_host_cmd ssvdevice_skb_alloc fail!!!\n"); -+ return 0; -+ } -+ skb->data_len = size_per_frame; -+ skb->len = skb->data_len; -+ host_cmd = (struct cfg_host_cmd *)skb->data; -+ host_cmd->c_type = TEST_CMD; -+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_TX_TPUT; -+ host_cmd->len = skb->data_len; -+ memcpy(host_cmd->dat32, skb->data, size_per_frame); -+ ssv6xxx_txtput->occupied_tx_pages = -+ (size_per_frame / PAGESIZE) + ((size_per_frame % PAGESIZE) != 0); -+ ssv6xxx_txtput->size_per_frame = size_per_frame; -+ ssv6xxx_txtput->loop_times = loop_times; -+ ssv6xxx_txtput->skb = skb; -+ ssv6xxx_txtput->txtput_tsk = -+ kthread_run(txtput_thread, NULL, "txtput_thread"); -+ return 0; -+} -+ -+int txtput_tsk_cleanup(void) -+{ -+ int ret = 0; -+ if (ssv6xxx_txtput->txtput_tsk) { -+ ret = kthread_stop(ssv6xxx_txtput->txtput_tsk); -+ ssv6xxx_txtput->txtput_tsk = NULL; -+ } -+ return ret; -+} -+ -+int watchdog_controller(struct ssv_hw *sh, u8 flag) -+{ -+ struct sk_buff *skb; -+ struct cfg_host_cmd *host_cmd; -+ int ret = 0; -+ pr_debug("watchdog_controller %d\n", flag); -+ skb = ssvdevice_skb_alloc(HOST_CMD_HDR_LEN); -+ if (skb == NULL) { -+ pr_err("init watchdog_controller failure\n"); -+ return (-1); -+ } -+ skb->data_len = HOST_CMD_HDR_LEN; -+ skb->len = skb->data_len; -+ host_cmd = (struct cfg_host_cmd *)skb->data; -+ host_cmd->c_type = HOST_CMD; -+ host_cmd->h_cmd = (u8) flag; -+ host_cmd->len = skb->data_len; -+ sh->hci.hci_ops->hci_send_cmd(skb); -+ ssvdevice_skb_free(skb); -+ return ret; -+} -+ -+static int ssv_cmd_txtput(int argc, char *argv[]) -+{ -+ char tmpbf[64], *endp; -+ u32 size_per_frame, loop_times, pkt_type; -+ ssv6xxx_txtput = &ssv_txtput; -+ if (argc == 2 && !strcmp(argv[1], "stop")) { -+ txtput_tsk_cleanup(); -+ return 0; -+ } -+ if (argc != 4) { -+ sprintf(tmpbf, "* txtput stop\n"); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ sprintf(tmpbf, "* txtput [type] [size] [frames]\n"); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ sprintf(tmpbf, " type(packet type):\n"); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ sprintf(tmpbf, " 0 = host_cmd\n"); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ sprintf(tmpbf, " 1 = m2_type \n"); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ sprintf(tmpbf, " EX: txtput 1 14000 9999 \n"); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ return 0; -+ } -+ pkt_type = simple_strtoul(argv[1], &endp, 10); -+ size_per_frame = simple_strtoul(argv[2], &endp, 10); -+ loop_times = simple_strtoul(argv[3], &endp, 10); -+ sprintf(tmpbf, "type&size&frames:%d&%d&%d\n", pkt_type, size_per_frame, -+ loop_times); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ if (ssv6xxx_txtput->txtput_tsk) { -+ sprintf(tmpbf, "txtput already in progress\n"); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ return 0; -+ } -+ watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh, -+ (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP); -+ ((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP; -+ if (pkt_type) -+ txtput_generate_m2(size_per_frame + SSV6XXX_TX_DESC_LEN, -+ loop_times); -+ else -+ txtput_generate_host_cmd(size_per_frame + HOST_CMD_HDR_LEN, -+ loop_times); -+ return 0; -+} -+ -+static int ssv_cmd_rxtput(int argc, char *argv[]) -+{ -+ struct sk_buff *skb; -+ struct cfg_host_cmd *host_cmd; -+ struct sdio_rxtput_cfg cmd_rxtput_cfg; -+ char tmpbf[32], *endp; -+ if (argc != 3) { -+ sprintf(ssv6xxx_result_buf, "rxtput [size] [frames]\n"); -+ return 0; -+ } -+ skb = -+ ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + -+ sizeof(struct sdio_rxtput_cfg)); -+ if (skb == NULL) { -+ pr_err("ssv command ssvdevice_skb_alloc fail\n"); -+ return 0; -+ } -+ watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh, -+ (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP); -+ ((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP; -+ cmd_rxtput_cfg.size_per_frame = simple_strtoul(argv[1], &endp, 10); -+ cmd_rxtput_cfg.total_frames = simple_strtoul(argv[2], &endp, 10); -+ sprintf(tmpbf, "size&frames:%d&%d\n", cmd_rxtput_cfg.size_per_frame, -+ cmd_rxtput_cfg.total_frames); -+ strcat(ssv6xxx_result_buf, tmpbf); -+ skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct sdio_rxtput_cfg); -+ skb->len = skb->data_len; -+ host_cmd = (struct cfg_host_cmd *)skb->data; -+ host_cmd->c_type = HOST_CMD; -+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_RX_TPUT; -+ host_cmd->len = skb->data_len; -+ memcpy(host_cmd->dat32, &cmd_rxtput_cfg, -+ sizeof(struct sdio_rxtput_cfg)); -+ if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) { -+ strcat(ssv6xxx_result_buf, -+ "## hci cmd was sent successfully\n"); -+ } else { -+ strcat(ssv6xxx_result_buf, "## hci cmd was sent failed\n"); -+ } -+ ssvdevice_skb_free(skb); -+ return 0; -+} -+ -+static int ssv_cmd_check(int argc, char *argv[]) -+{ -+ u32 size, i, j, x, y, id, value, address, id_value; -+ char *endp; -+ u32 id_base_address[4]; -+ id_base_address[0] = 0xcd010008; -+ id_base_address[1] = 0xcd01000c; -+ id_base_address[2] = 0xcd010054; -+ id_base_address[3] = 0xcd010058; -+ if (argc != 2) { -+ sprintf(ssv6xxx_result_buf, "check [packet size]\n"); -+ return 0; -+ } -+ size = simple_strtoul(argv[1], &endp, 10); -+ size = size >> 2; -+ for (x = 0; x < 4; x++) { -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, id_base_address[x], &id_value)) ; -+ for (y = 0; y < 32 && id_value; y++, id_value >>= 1) { -+ if (id_value & 0x1) { -+ id = 32 * x + y; -+ address = 0x80000000 + (id << 16); -+ { -+ for (i = 0; i < size; i += 8) { -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, -+ address, &value)) ; -+ address += 4; -+ for (j = 1; j < 8; j++) { -+ if (SSV_REG_READ1 -+ (ssv6xxx_debug_ifops, -+ address, &value)) ; -+ address += 4; -+ } -+ } -+ } -+ } -+ } -+ } -+ return 0; -+} -+ -+struct ssv_cmd_table cmd_table[] = { -+ {"help", ssv_cmd_help, "ssv6200 command usage."}, -+ {"-h", ssv_cmd_help, "ssv6200 command usage."}, -+ {"--help", ssv_cmd_help, "ssv6200 command usage."}, -+ {"reg", ssv_cmd_reg, "ssv6200 register read/write."}, -+ {"cfg", ssv_cmd_cfg, "ssv6200 configuration."}, -+ {"sta", ssv_cmd_sta, "svv6200 station info."}, -+ {"dump", ssv_cmd_dump, "dump ssv6200 tables."}, -+ {"hwq", ssv_cmd_hwq, "hardware queue staus"}, -+#ifdef CONFIG_P2P_NOA -+ {"noa", ssv_cmd_noa, "config noa param"}, -+#endif -+ {"irq", ssv_cmd_irq, "get sdio irq status."}, -+ {"mac", ssv_cmd_mac, "ieee80211 swmac."}, -+ {"hci", ssv_cmd_hci, "HCI command."}, -+ {"sdio", ssv_cmd_sdio, "SDIO command."}, -+ {"iqk", ssv_cmd_iqk, "iqk command"}, -+ {"version", ssv_cmd_version, "version information"}, -+ {"mib", ssv_cmd_mib, "mib counter related"}, -+ {"tool", ssv_cmd_tool, "ssv6200 tool register read/write."}, -+ {"rxtput", ssv_cmd_rxtput, "test rx sdio throughput"}, -+ {"txtput", ssv_cmd_txtput, "test tx sdio throughput"}, -+ {"check", ssv_cmd_check, "dump all allocate packet buffer"}, -+ {NULL, NULL, NULL}, -+}; -+ -+int ssv_cmd_submit(char *cmd) -+{ -+ struct ssv_cmd_table *sc_tbl; -+ char *pch, ch; -+ int ret; -+ ssv6xxx_debug_ifops = (void *)ssv6xxx_ifdebug_info; -+ strcpy(sg_cmd_buffer, cmd); -+ for (sg_argc = 0, ch = 0, pch = sg_cmd_buffer; -+ (*pch != 0x00) && (sg_argc < CLI_ARG_SIZE); pch++) { -+ if ((ch == 0) && (*pch != ' ')) { -+ ch = 1; -+ sg_argv[sg_argc] = pch; -+ } -+ if ((ch == 1) && (*pch == ' ')) { -+ *pch = 0x00; -+ ch = 0; -+ sg_argc++; -+ } -+ } -+ if (ch == 1) { -+ sg_argc++; -+ } else if (sg_argc > 0) { -+ *(pch - 1) = ' '; -+ } -+ if (sg_argc > 0) { -+ for (sc_tbl = cmd_table; sc_tbl->cmd; sc_tbl++) { -+ if (!strcmp(sg_argv[0], sc_tbl->cmd)) { -+ if ((sc_tbl->cmd_func_ptr != ssv_cmd_cfg) && -+ (!ssv6xxx_debug_ifops->dev || -+ !ssv6xxx_debug_ifops->ifops || -+ !ssv6xxx_debug_ifops->pdev)) { -+ strcpy(ssv6xxx_result_buf, -+ "Member of ssv6xxx_ifdebug_info is NULL !\n"); -+ return -1; -+ } -+ ssv6xxx_result_buf[0] = 0x00; -+ ret = sc_tbl->cmd_func_ptr(sg_argc, sg_argv); -+ if (ret < 0) { -+ strcpy(ssv6xxx_result_buf, -+ "Invalid command !\n"); -+ } -+ return 0; -+ } -+ } -+ strcpy(ssv6xxx_result_buf, "Command not found !\n"); -+ } else { -+ strcpy(ssv6xxx_result_buf, "./cli -h\n"); -+ } -+ return 0; -+} -diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h -@@ -0,0 +1,50 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _SSV_CMD_H_ -+#define _SSV_CMD_H_ -+#define CLI_BUFFER_SIZE 256 -+#define CLI_ARG_SIZE 10 -+#define CLI_RESULT_BUF_SIZE (4096) -+#define DEBUG_DIR_ENTRY "ssv" -+#define DEBUG_DEVICETYPE_ENTRY "ssv_devicetype" -+#define DEBUG_CMD_ENTRY "ssv_cmd" -+#define MAX_CHARS_PER_LINE 256 -+struct ssv_cmd_table { -+ const char *cmd; -+ int (*cmd_func_ptr)(int, char **); -+ const char *usage; -+}; -+struct ssv6xxx_cfg_cmd_table { -+ u8 *cfg_cmd; -+ void *var; -+ u32 arg; -+ int (*translate_func)(u8 *, void *, u32); -+}; -+#define SSV_REG_READ1(ops,reg,val) \ -+ (ops)->ifops->readreg((ops)->dev, reg, val) -+#define SSV_REG_WRITE1(ops,reg,val) \ -+ (ops)->ifops->writereg((ops)->dev, reg, val) -+#define SSV_REG_SET_BITS1(ops,reg,set,clr) \ -+ { \ -+ u32 reg_val; \ -+ SSV_REG_READ(ops, reg, ®_val); \ -+ reg_val &= ~(clr); \ -+ reg_val |= (set); \ -+ SSV_REG_WRITE(ops, reg, reg_val); \ -+ } -+int ssv_cmd_submit(char *cmd); -+#endif -diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c -@@ -0,0 +1,256 @@ -+/* -+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. -+ * Copyright (c) 2015 iComm Corporation -+ * -+ * This program is free software: you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation, either version 3 of the License, or -+ * (at your option) any later version. -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the GNU General Public License for more details. -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ssv_cmd.h" -+#include "ssv_cfg.h" -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_DEBUG_FS -+#include -+#endif -+ -+char *ssv_initmac = NULL; -+EXPORT_SYMBOL(ssv_initmac); -+module_param(ssv_initmac, charp, 0644); -+MODULE_PARM_DESC(ssv_initmac, "Wi-Fi MAC address"); -+ -+u32 ssv_devicetype = 0; -+EXPORT_SYMBOL(ssv_devicetype); -+ -+#ifdef CONFIG_DEBUG_FS -+static struct dentry *debugfs; -+#endif -+ -+struct proc_dir_entry *procfs; -+static char *ssv6xxx_cmd_buf; -+char *ssv6xxx_result_buf; -+extern struct ssv6xxx_cfg_cmd_table cfg_cmds[]; -+extern struct ssv6xxx_cfg ssv_cfg; -+char DEFAULT_CFG_PATH[] = "/lib/firmware/ssv6051-wifi.cfg"; -+static int ssv6xxx_dbg_open(struct inode *inode, struct file *filp) -+{ -+ filp->private_data = inode->i_private; -+ return 0; -+} -+ -+static ssize_t ssv6xxx_dbg_read(struct file *filp, char __user * buffer, -+ size_t count, loff_t * ppos) -+{ -+ int len; -+ if (*ppos != 0) -+ return 0; -+ len = strlen(ssv6xxx_result_buf) + 1; -+ if (len == 1) -+ return 0; -+ if (copy_to_user(buffer, ssv6xxx_result_buf, len)) -+ return -EFAULT; -+ ssv6xxx_result_buf[0] = 0x00; -+ return len; -+} -+ -+static ssize_t ssv6xxx_dbg_write(struct file *filp, const char __user * buffer, -+ size_t count, loff_t * ppos) -+{ -+ if (*ppos != 0 || count > 255) -+ return 0; -+ if (copy_from_user(ssv6xxx_cmd_buf, buffer, count)) -+ return -EFAULT; -+ ssv6xxx_cmd_buf[count - 1] = 0x00; -+ ssv_cmd_submit(ssv6xxx_cmd_buf); -+ return count; -+} -+ -+size_t read_line(struct file * fp, char *buf, size_t size) -+{ -+ size_t num_read = 0; -+ size_t total_read = 0; -+ char *buffer; -+ char ch; -+ size_t start_ignore = 0; -+ if (size <= 0 || buf == NULL) { -+ total_read = -EINVAL; -+ return -EINVAL; -+ } -+ buffer = buf; -+ for (;;) { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0) -+ num_read = kernel_read(fp, &ch, 1, &fp->f_pos); -+#else -+ mm_segment_t fs; -+ fs = get_fs(); -+ set_fs(KERNEL_DS); -+ num_read = vfs_read(fp, &ch, 1, &fp->f_pos); -+ set_fs(fs); -+#endif -+ if (num_read < 0) { -+ if (num_read == EINTR) -+ continue; -+ else -+ return -1; -+ } else if (num_read == 0) { -+ if (total_read == 0) -+ return 0; -+ else -+ break; -+ } else { -+ if (ch == '#') -+ start_ignore = 1; -+ if (total_read < size - 1) { -+ total_read++; -+ if (start_ignore) -+ *buffer++ = '\0'; -+ else -+ *buffer++ = ch; -+ } -+ if (ch == '\n') -+ break; -+ } -+ } -+ *buffer = '\0'; -+ return total_read; -+} -+ -+int ischar(char *c) -+{ -+ int is_char = 1; -+ while (*c) { -+ if (isalpha(*c) || isdigit(*c) || *c == '_' || *c == ':' -+ || *c == '/' || *c == '.' || *c == '-') -+ c++; -+ else { -+ is_char = 0; -+ break; -+ } -+ } -+ return is_char; -+} -+ -+void sta_cfg_set(void) -+{ -+ struct file *fp = (struct file *)NULL; -+ char buf[MAX_CHARS_PER_LINE], cfg_cmd[32], cfg_value[32]; -+ size_t s, read_len = 0, is_cmd_support = 0; -+ -+ memset(&ssv_cfg, 0, sizeof(ssv_cfg)); -+ memset(buf, 0, sizeof(buf)); -+ fp = filp_open(DEFAULT_CFG_PATH, O_RDONLY, 0); -+ if (IS_ERR(fp) || fp == NULL) { -+ WARN_ON(1); -+ return; -+ } -+ if (fp->f_path.dentry == NULL) { -+ WARN_ON(1); -+ return; -+ } -+ do { -+ memset(cfg_cmd, '\0', sizeof(cfg_cmd)); -+ memset(cfg_value, '\0', sizeof(cfg_value)); -+ read_len = read_line(fp, buf, MAX_CHARS_PER_LINE); -+ sscanf(buf, "%s = %s", cfg_cmd, cfg_value); -+ if (!ischar(cfg_cmd) || !ischar(cfg_value)) { -+ pr_warn("Invalid configuration parameter: %s\n", buf); -+ continue; -+ } -+ is_cmd_support = 0; -+ for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) { -+ if (strcmp(cfg_cmds[s].cfg_cmd, cfg_cmd) == 0) { -+ cfg_cmds[s].translate_func(cfg_value, -+ cfg_cmds[s].var, -+ cfg_cmds[s].arg); -+ is_cmd_support = 1; -+ break; -+ } -+ } -+ if (!is_cmd_support && strlen(cfg_cmd) > 0) { -+ pr_warn("Unsupported configuration command: %s", cfg_cmd); -+ } -+ } while (read_len > 0); -+ filp_close(fp, NULL); -+} -+ -+static const struct file_operations ssv6xxx_dbg_fops = { -+ .owner = THIS_MODULE, -+ .open = ssv6xxx_dbg_open, -+ .read = ssv6xxx_dbg_read, -+ .write = ssv6xxx_dbg_write, -+}; -+ -+extern int ssv6xxx_hci_init(void); -+extern void ssv6xxx_hci_exit(void); -+extern int ssv6xxx_init(void); -+extern void ssv6xxx_exit(void); -+extern int ssv6xxx_sdio_init(void); -+extern void ssv6xxx_sdio_exit(void); -+ -+int ssvdevice_init(void) -+{ -+ ssv6xxx_cmd_buf = -+ (char *)kzalloc(CLI_BUFFER_SIZE + CLI_RESULT_BUF_SIZE, GFP_KERNEL); -+ if (!ssv6xxx_cmd_buf) -+ return -ENOMEM; -+ ssv6xxx_result_buf = ssv6xxx_cmd_buf + CLI_BUFFER_SIZE; -+ ssv6xxx_cmd_buf[0] = 0x00; -+ ssv6xxx_result_buf[0] = 0x00; -+#ifdef CONFIG_DEBUG_FS -+ debugfs = debugfs_create_dir(DEBUG_DIR_ENTRY, NULL); -+ if (!debugfs) -+ return -ENOMEM; -+ debugfs_create_u32(DEBUG_DEVICETYPE_ENTRY, S_IRUGO | S_IWUSR, debugfs, -+ &ssv_devicetype); -+ debugfs_create_file(DEBUG_CMD_ENTRY, S_IRUGO | S_IWUSR, debugfs, NULL, -+ &ssv6xxx_dbg_fops); -+#endif -+ sta_cfg_set(); -+ { -+ int ret; -+ ret = ssv6xxx_hci_init(); -+ if (!ret) { -+ ret = ssv6xxx_init(); -+ } -+ if (!ret) { -+ ret = ssv6xxx_sdio_init(); -+ } -+ return ret; -+ } -+ -+ return 0; -+} -+ -+void ssvdevice_exit(void) -+{ -+ -+ ssv6xxx_exit(); -+ ssv6xxx_hci_exit(); -+ ssv6xxx_sdio_exit(); -+ -+#ifdef CONFIG_DEBUG_FS -+ debugfs_remove_recursive(debugfs); -+#endif -+ kfree(ssv6xxx_cmd_buf); -+} -+ -+EXPORT_SYMBOL(ssvdevice_init); -+EXPORT_SYMBOL(ssvdevice_exit); --- -Armbian - diff --git a/patch/kernel/rockchip64-6.14/general-add-hdmi-mks-ips50-resolutions.patch b/patch/kernel/rockchip64-6.16/general-add-hdmi-mks-ips50-resolutions.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-add-hdmi-mks-ips50-resolutions.patch rename to patch/kernel/rockchip64-6.16/general-add-hdmi-mks-ips50-resolutions.patch diff --git a/patch/kernel/rockchip64-6.14/general-add-miniDP-dt-doc.patch b/patch/kernel/rockchip64-6.16/general-add-miniDP-dt-doc.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-add-miniDP-dt-doc.patch rename to patch/kernel/rockchip64-6.16/general-add-miniDP-dt-doc.patch diff --git a/patch/kernel/rockchip64-6.14/general-add-miniDP-virtual-extcon.patch b/patch/kernel/rockchip64-6.16/general-add-miniDP-virtual-extcon.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-add-miniDP-virtual-extcon.patch rename to patch/kernel/rockchip64-6.16/general-add-miniDP-virtual-extcon.patch diff --git a/patch/kernel/rockchip64-6.16/general-add-overlay-compilation-support.patch b/patch/kernel/rockchip64-6.16/general-add-overlay-compilation-support.patch new file mode 100644 index 0000000..267fd37 --- /dev/null +++ b/patch/kernel/rockchip64-6.16/general-add-overlay-compilation-support.patch @@ -0,0 +1,66 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Wed, 2 Oct 2024 19:30:34 +0300 +Subject: compile .scr and install overlays in right path + +--- + scripts/Makefile.dtbinst | 13 +++++++++- + scripts/Makefile.dtbs | 8 +++++- + 2 files changed, 19 insertions(+), 2 deletions(-) + +diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst +index 111111111111..222222222222 100644 +--- a/scripts/Makefile.dtbinst ++++ b/scripts/Makefile.dtbinst +@@ -33,7 +33,18 @@ endef + + $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d)))) + +-dtbs := $(notdir $(dtbs)) ++# Very convoluted way to flatten all the device tree ++# directories, but keep the "/overlay/" directory ++ ++# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip) ++topmost_dir = $(firstword $(subst /, ,$(dtbs))) ++# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir" ++dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs))) ++# collect the non-overlay dtbs ++dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs)) ++# compose the dtbs variable flattening all the non-overlays entries ++# and appending the overlays entries ++dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays) + + endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL + +diff --git a/scripts/Makefile.dtbs b/scripts/Makefile.dtbs +index 111111111111..222222222222 100644 +--- a/scripts/Makefile.dtbs ++++ b/scripts/Makefile.dtbs +@@ -122,17 +122,23 @@ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + quiet_cmd_dtc = DTC $(quiet_dtb_check_tag) $@ + cmd_dtc = \ + $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ +- $(DTC) -o $@ -b 0 $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) \ ++ $(DTC) -@ -o $@ -b 0 $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) \ + $(DTC_FLAGS) -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) \ + $(cmd_dtb_check) + ++quiet_cmd_scr = MKIMAGE $@ ++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ ++ + $(obj)/%.dtb: $(obj)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(call if_changed_dep,dtc) + + $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE + $(call if_changed_dep,dtc) + ++$(obj)/%.scr: $(src)/%.scr-cmd FORCE ++ $(call if_changed,scr) ++ + # targets + # --------------------------------------------------------------------------- + +-- +Armbian + diff --git a/patch/kernel/rockchip64-6.16/general-add-overlay-configfs._patch b/patch/kernel/rockchip64-6.16/general-add-overlay-configfs._patch new file mode 100644 index 0000000..3f75a5c --- /dev/null +++ b/patch/kernel/rockchip64-6.16/general-add-overlay-configfs._patch @@ -0,0 +1,419 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Pantelis Antoniou +Date: Wed, 3 Dec 2014 13:23:28 +0200 +Subject: OF: DT-Overlay configfs interface + +This is a port of Pantelis Antoniou's v3 port that makes use of the +new upstreamed configfs support for binary attributes. + +Original commit message: + +Add a runtime interface to using configfs for generic device tree overlay +usage. With it its possible to use device tree overlays without having +to use a per-platform overlay manager. + +Please see Documentation/devicetree/configfs-overlays.txt for more info. + +Changes since v2: +- Removed ifdef CONFIG_OF_OVERLAY (since for now it's required) +- Created a documentation entry +- Slight rewording in Kconfig + +Changes since v1: +- of_resolve() -> of_resolve_phandles(). + +Originally-signed-off-by: Pantelis Antoniou +Signed-off-by: Phil Elwell + +DT configfs: Fix build errors on other platforms + +Signed-off-by: Phil Elwell + +DT configfs: fix build error + +There is an error when compiling rpi-4.6.y branch: + CC drivers/of/configfs.o +drivers/of/configfs.c:291:21: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types] + .default_groups = of_cfs_def_groups, + ^ +drivers/of/configfs.c:291:21: note: (near initialization for 'of_cfs_subsys.su_group.default_groups.next') + +The .default_groups is linked list since commit +1ae1602de028acaa42a0f6ff18d19756f8e825c6. +This commit uses configfs_add_default_group to fix this problem. + +Signed-off-by: Slawomir Stepien + +configfs: New of_overlay API + +of: configfs: Use of_overlay_fdt_apply API call + +The published API to the dynamic overlay application mechanism now +takes a Flattened Device Tree blob as input so that it can manage the +lifetime of the unflattened tree. Conveniently, the new API call - +of_overlay_fdt_apply - is virtually a drop-in replacement for +create_overlay, which can now be deleted. + +Signed-off-by: Phil Elwell +--- + Documentation/devicetree/configfs-overlays.txt | 31 ++ + drivers/of/Kconfig | 11 + + drivers/of/Makefile | 1 + + drivers/of/configfs.c | 277 ++++++++++ + 4 files changed, 320 insertions(+) + +diff --git a/Documentation/devicetree/configfs-overlays.txt b/Documentation/devicetree/configfs-overlays.txt +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/Documentation/devicetree/configfs-overlays.txt +@@ -0,0 +1,31 @@ ++Howto use the configfs overlay interface. ++ ++A device-tree configfs entry is created in /config/device-tree/overlays ++and and it is manipulated using standard file system I/O. ++Note that this is a debug level interface, for use by developers and ++not necessarily something accessed by normal users due to the ++security implications of having direct access to the kernel's device tree. ++ ++* To create an overlay you mkdir the directory: ++ ++ # mkdir /config/device-tree/overlays/foo ++ ++* Either you echo the overlay firmware file to the path property file. ++ ++ # echo foo.dtbo >/config/device-tree/overlays/foo/path ++ ++* Or you cat the contents of the overlay to the dtbo file ++ ++ # cat foo.dtbo >/config/device-tree/overlays/foo/dtbo ++ ++The overlay file will be applied, and devices will be created/destroyed ++as required. ++ ++To remove it simply rmdir the directory. ++ ++ # rmdir /config/device-tree/overlays/foo ++ ++The rationalle of the dual interface (firmware & direct copy) is that each is ++better suited to different use patterns. The firmware interface is what's ++intended to be used by hardware managers in the kernel, while the copy interface ++make sense for developers (since it avoids problems with namespaces). +diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig +index 111111111111..222222222222 100644 +--- a/drivers/of/Kconfig ++++ b/drivers/of/Kconfig +@@ -126,4 +126,15 @@ config OF_OVERLAY_KUNIT_TEST + config OF_NUMA + bool + ++config OF_DMA_DEFAULT_COHERENT ++ # arches should select this if DMA is coherent by default for OF devices ++ bool ++ ++config OF_CONFIGFS ++ bool "Device Tree Overlay ConfigFS interface" ++ select CONFIGFS_FS ++ select OF_OVERLAY ++ help ++ Enable a simple user-space driven DT overlay interface. ++ + endif # OF +diff --git a/drivers/of/Makefile b/drivers/of/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/of/Makefile ++++ b/drivers/of/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-y = base.o cpu.o device.o module.o platform.o property.o + obj-$(CONFIG_OF_KOBJ) += kobj.o ++obj-$(CONFIG_OF_CONFIGFS) += configfs.o + obj-$(CONFIG_OF_DYNAMIC) += dynamic.o + obj-$(CONFIG_OF_FLATTREE) += fdt.o empty_root.dtb.o + obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o +diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/of/configfs.c +@@ -0,0 +1,277 @@ ++/* ++ * Configfs entries for device-tree ++ * ++ * Copyright (C) 2013 - Pantelis Antoniou ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "of_private.h" ++ ++struct cfs_overlay_item { ++ struct config_item item; ++ ++ char path[PATH_MAX]; ++ ++ const struct firmware *fw; ++ struct device_node *overlay; ++ int ov_id; ++ ++ void *dtbo; ++ int dtbo_size; ++}; ++ ++static inline struct cfs_overlay_item *to_cfs_overlay_item( ++ struct config_item *item) ++{ ++ return item ? container_of(item, struct cfs_overlay_item, item) : NULL; ++} ++ ++static ssize_t cfs_overlay_item_path_show(struct config_item *item, ++ char *page) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ return sprintf(page, "%s\n", overlay->path); ++} ++ ++static ssize_t cfs_overlay_item_path_store(struct config_item *item, ++ const char *page, size_t count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ const char *p = page; ++ char *s; ++ int err; ++ ++ /* if it's set do not allow changes */ ++ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) ++ return -EPERM; ++ ++ /* copy to path buffer (and make sure it's always zero terminated */ ++ count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p); ++ overlay->path[sizeof(overlay->path) - 1] = '\0'; ++ ++ /* strip trailing newlines */ ++ s = overlay->path + strlen(overlay->path); ++ while (s > overlay->path && *--s == '\n') ++ *s = '\0'; ++ ++ pr_debug("%s: path is '%s'\n", __func__, overlay->path); ++ ++ err = request_firmware(&overlay->fw, overlay->path, NULL); ++ if (err != 0) ++ goto out_err; ++ ++ err = of_overlay_fdt_apply((void *)overlay->fw->data, ++ (u32)overlay->fw->size, &overlay->ov_id, NULL); ++ if (err != 0) ++ goto out_err; ++ ++ return count; ++ ++out_err: ++ ++ release_firmware(overlay->fw); ++ overlay->fw = NULL; ++ ++ overlay->path[0] = '\0'; ++ return err; ++} ++ ++static ssize_t cfs_overlay_item_status_show(struct config_item *item, ++ char *page) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ return sprintf(page, "%s\n", ++ overlay->ov_id > 0 ? "applied" : "unapplied"); ++} ++ ++CONFIGFS_ATTR(cfs_overlay_item_, path); ++CONFIGFS_ATTR_RO(cfs_overlay_item_, status); ++ ++static struct configfs_attribute *cfs_overlay_attrs[] = { ++ &cfs_overlay_item_attr_path, ++ &cfs_overlay_item_attr_status, ++ NULL, ++}; ++ ++ssize_t cfs_overlay_item_dtbo_read(struct config_item *item, ++ void *buf, size_t max_count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ pr_debug("%s: buf=%p max_count=%zu\n", __func__, ++ buf, max_count); ++ ++ if (overlay->dtbo == NULL) ++ return 0; ++ ++ /* copy if buffer provided */ ++ if (buf != NULL) { ++ /* the buffer must be large enough */ ++ if (overlay->dtbo_size > max_count) ++ return -ENOSPC; ++ ++ memcpy(buf, overlay->dtbo, overlay->dtbo_size); ++ } ++ ++ return overlay->dtbo_size; ++} ++ ++ssize_t cfs_overlay_item_dtbo_write(struct config_item *item, ++ const void *buf, size_t count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ int err; ++ ++ /* if it's set do not allow changes */ ++ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) ++ return -EPERM; ++ ++ /* copy the contents */ ++ overlay->dtbo = kmemdup(buf, count, GFP_KERNEL); ++ if (overlay->dtbo == NULL) ++ return -ENOMEM; ++ ++ overlay->dtbo_size = count; ++ ++ err = of_overlay_fdt_apply(overlay->dtbo, overlay->dtbo_size, ++ &overlay->ov_id, NULL); ++ if (err != 0) ++ goto out_err; ++ ++ return count; ++ ++out_err: ++ kfree(overlay->dtbo); ++ overlay->dtbo = NULL; ++ overlay->dtbo_size = 0; ++ overlay->ov_id = 0; ++ ++ return err; ++} ++ ++CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M); ++ ++static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = { ++ &cfs_overlay_item_attr_dtbo, ++ NULL, ++}; ++ ++static void cfs_overlay_release(struct config_item *item) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ if (overlay->ov_id > 0) ++ of_overlay_remove(&overlay->ov_id); ++ if (overlay->fw) ++ release_firmware(overlay->fw); ++ /* kfree with NULL is safe */ ++ kfree(overlay->dtbo); ++ kfree(overlay); ++} ++ ++static struct configfs_item_operations cfs_overlay_item_ops = { ++ .release = cfs_overlay_release, ++}; ++ ++static struct config_item_type cfs_overlay_type = { ++ .ct_item_ops = &cfs_overlay_item_ops, ++ .ct_attrs = cfs_overlay_attrs, ++ .ct_bin_attrs = cfs_overlay_bin_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_item *cfs_overlay_group_make_item( ++ struct config_group *group, const char *name) ++{ ++ struct cfs_overlay_item *overlay; ++ ++ overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); ++ if (!overlay) ++ return ERR_PTR(-ENOMEM); ++ ++ config_item_init_type_name(&overlay->item, name, &cfs_overlay_type); ++ return &overlay->item; ++} ++ ++static void cfs_overlay_group_drop_item(struct config_group *group, ++ struct config_item *item) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ config_item_put(&overlay->item); ++} ++ ++static struct configfs_group_operations overlays_ops = { ++ .make_item = cfs_overlay_group_make_item, ++ .drop_item = cfs_overlay_group_drop_item, ++}; ++ ++static struct config_item_type overlays_type = { ++ .ct_group_ops = &overlays_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct configfs_group_operations of_cfs_ops = { ++ /* empty - we don't allow anything to be created */ ++}; ++ ++static struct config_item_type of_cfs_type = { ++ .ct_group_ops = &of_cfs_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++struct config_group of_cfs_overlay_group; ++ ++static struct configfs_subsystem of_cfs_subsys = { ++ .su_group = { ++ .cg_item = { ++ .ci_namebuf = "device-tree", ++ .ci_type = &of_cfs_type, ++ }, ++ }, ++ .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex), ++}; ++ ++static int __init of_cfs_init(void) ++{ ++ int ret; ++ ++ pr_info("%s\n", __func__); ++ ++ config_group_init(&of_cfs_subsys.su_group); ++ config_group_init_type_name(&of_cfs_overlay_group, "overlays", ++ &overlays_type); ++ configfs_add_default_group(&of_cfs_overlay_group, ++ &of_cfs_subsys.su_group); ++ ++ ret = configfs_register_subsystem(&of_cfs_subsys); ++ if (ret != 0) { ++ pr_err("%s: failed to register subsys\n", __func__); ++ goto out; ++ } ++ pr_info("%s: OK\n", __func__); ++out: ++ return ret; ++} ++late_initcall(of_cfs_init); +-- +Armbian + diff --git a/patch/kernel/rockchip64-6.14/general-add-panel-simple-dsi.patch b/patch/kernel/rockchip64-6.16/general-add-panel-simple-dsi.patch similarity index 99% rename from patch/kernel/rockchip64-6.14/general-add-panel-simple-dsi.patch rename to patch/kernel/rockchip64-6.16/general-add-panel-simple-dsi.patch index 480cc4f..c048e45 100644 --- a/patch/kernel/rockchip64-6.14/general-add-panel-simple-dsi.patch +++ b/patch/kernel/rockchip64-6.16/general-add-panel-simple-dsi.patch @@ -65,7 +65,7 @@ diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile -@@ -11,6 +11,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o +@@ -12,6 +12,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o diff --git a/patch/kernel/rockchip64-6.14/general-add-pll-hdmi-timings.patch b/patch/kernel/rockchip64-6.16/general-add-pll-hdmi-timings.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-add-pll-hdmi-timings.patch rename to patch/kernel/rockchip64-6.16/general-add-pll-hdmi-timings.patch diff --git a/patch/kernel/rockchip64-6.14/general-add-xtx-spi-nor-chips.patch b/patch/kernel/rockchip64-6.16/general-add-xtx-spi-nor-chips.patch similarity index 97% rename from patch/kernel/rockchip64-6.14/general-add-xtx-spi-nor-chips.patch rename to patch/kernel/rockchip64-6.16/general-add-xtx-spi-nor-chips.patch index 4513e8c..4a0b925 100644 --- a/patch/kernel/rockchip64-6.14/general-add-xtx-spi-nor-chips.patch +++ b/patch/kernel/rockchip64-6.16/general-add-xtx-spi-nor-chips.patch @@ -30,7 +30,7 @@ diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 111111111111..222222222222 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c -@@ -1981,6 +1981,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = { +@@ -1954,6 +1954,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = { &spi_nor_sst, &spi_nor_winbond, &spi_nor_xmc, diff --git a/patch/kernel/rockchip64-6.14/general-cryptov1-trng.patch b/patch/kernel/rockchip64-6.16/general-cryptov1-trng.patch similarity index 98% rename from patch/kernel/rockchip64-6.14/general-cryptov1-trng.patch rename to patch/kernel/rockchip64-6.16/general-cryptov1-trng.patch index 73fa8e2..2daa100 100644 --- a/patch/kernel/rockchip64-6.14/general-cryptov1-trng.patch +++ b/patch/kernel/rockchip64-6.16/general-cryptov1-trng.patch @@ -18,7 +18,7 @@ diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 111111111111..222222222222 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig -@@ -700,6 +700,14 @@ config CRYPTO_DEV_ROCKCHIP +@@ -694,6 +694,14 @@ config CRYPTO_DEV_ROCKCHIP This driver interfaces with the hardware crypto accelerator. Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode. @@ -163,7 +163,7 @@ diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rock index 111111111111..222222222222 100644 --- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c +++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c -@@ -296,6 +296,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) +@@ -298,6 +298,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) goto theend; } @@ -171,7 +171,7 @@ index 111111111111..222222222222 100644 rk_ahash_reg_init(areq, rkc); while (sg) { -@@ -330,6 +331,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) +@@ -332,6 +333,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) } theend: diff --git a/patch/kernel/rockchip64-6.14/general-disable-mtu-validation.patch b/patch/kernel/rockchip64-6.16/general-disable-mtu-validation.patch similarity index 96% rename from patch/kernel/rockchip64-6.14/general-disable-mtu-validation.patch rename to patch/kernel/rockchip64-6.16/general-disable-mtu-validation.patch index a350a44..4c3523c 100644 --- a/patch/kernel/rockchip64-6.14/general-disable-mtu-validation.patch +++ b/patch/kernel/rockchip64-6.16/general-disable-mtu-validation.patch @@ -18,7 +18,7 @@ diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/eth index 111111111111..222222222222 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -5878,27 +5878,15 @@ static void stmmac_set_rx_mode(struct net_device *dev) +@@ -5934,27 +5934,15 @@ static void stmmac_set_rx_mode(struct net_device *dev) static int stmmac_change_mtu(struct net_device *dev, int new_mtu) { struct stmmac_priv *priv = netdev_priv(dev); diff --git a/patch/kernel/rockchip64-6.14/general-driver-tm16xx-led-driver.patch b/patch/kernel/rockchip64-6.16/general-driver-tm16xx-led-driver.patch similarity index 65% rename from patch/kernel/rockchip64-6.14/general-driver-tm16xx-led-driver.patch rename to patch/kernel/rockchip64-6.16/general-driver-tm16xx-led-driver.patch index dc42841..3344b1e 100644 --- a/patch/kernel/rockchip64-6.14/general-driver-tm16xx-led-driver.patch +++ b/patch/kernel/rockchip64-6.16/general-driver-tm16xx-led-driver.patch @@ -1,14 +1,171 @@ From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Paolo Sabatino -Date: Sat, 5 Oct 2024 16:07:14 +0200 +Date: Sat, 21 Jun 2025 15:07:40 +0200 Subject: Add tm16xx led auxiliary display driver --- - drivers/auxdisplay/Kconfig | 10 + - drivers/auxdisplay/Makefile | 1 + - drivers/auxdisplay/tm16xx.c | 1167 ++++++++++ - 3 files changed, 1178 insertions(+) + Documentation/devicetree/bindings/auxdisplay/tm16xx.yaml | 150 ++ + drivers/auxdisplay/Kconfig | 10 + + drivers/auxdisplay/Makefile | 1 + + drivers/auxdisplay/tm16xx.c | 1187 ++++++++++ + 4 files changed, 1348 insertions(+) +diff --git a/Documentation/devicetree/bindings/auxdisplay/tm16xx.yaml b/Documentation/devicetree/bindings/auxdisplay/tm16xx.yaml +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/Documentation/devicetree/bindings/auxdisplay/tm16xx.yaml +@@ -0,0 +1,150 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/auxdisplay/tm16xx.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Auxiliary displays based on TM16xx and compatible LED controllers ++ ++maintainers: ++ - Jean-François Lessard ++ ++description: | ++ TM16xx controllers manage a matrix of LEDs organized in grids (rows) and segments (columns). ++ Each grid or segment can be wired to drive either a digit or individual icons, depending on the ++ board design. ++ ++ Typical display example: ++ ++         ---    ---       ---    --- ++ WIFI  |   |  |   |  -  |   |  |   |  USB  PLAY ++       ---    ---       ---    --- ++ LAN   |   |  |   |  -  |   |  |   |  BT   PAUSE ++         ---    ---       ---    --- ++ ++ The controller itself is agnostic of the display layout. The specific arrangement ++ (which grids and segments drive which digits or icons) is determined by the board-level ++ wiring. Therefore, these bindings describe hardware configuration at the PCB level ++ to enable support of multiple display implementations using these LED controllers. ++ ++properties: ++ compatible: ++ enum: ++ - titanmec,tm1618 ++ - titanmec,tm1620 ++ - titanmec,tm1628 ++ - titanmec,tm1650 ++ - fdhisi,fd620 ++ - fdhisi,fd628 ++ - fdhisi,fd650 ++ - fdhisi,fd6551 ++ - fdhisi,fd655 ++ - princeton,pt6964 ++ - hbs,hbs658 ++ ++ reg: ++ maxItems: 1 ++ ++ tm16xx,digits: ++ description: | ++ Array of grid (row) indexes corresponding to specific wiring of digits in the display matrix. ++ Defines which grid lines are connected to digit elements. ++ $ref: /schemas/types.yaml#/definitions/uint8-array ++ items: ++ minimum: 0 ++ maximum: 7 ++ minItems: 1 ++ maxItems: 8 ++ ++ tm16xx,segment-mapping: ++ description: | ++ Array of segment (column) indexes specifying the hardware layout mapping used for digit display. ++ Each entry gives the segment index corresponding to a standard 7-segment element (a-g). ++ $ref: /schemas/types.yaml#/definitions/uint8-array ++ items: ++ minimum: 0 ++ maximum: 7 ++ minItems: 7 ++ maxItems: 7 ++ ++ tm16xx,transposed: ++ description: | ++ Optional flag indicating if grids and segments are swapped compared to standard matrix orientation. ++ This accommodates devices where segments are wired to rows and grids to columns. ++ $ref: /schemas/types.yaml#/definitions/flag ++ ++ "#address-cells": ++ const: 2 ++ ++ "#size-cells": ++ const: 0 ++ ++patternProperties: ++ "^led@[0-7],[0-7]$": ++ $ref: /schemas/leds/common.yaml# ++ properties: ++ reg: ++ description: Grid (row) and segment (column) index in the matrix of this individual LED icon ++ required: ++ - reg ++ ++required: ++ - compatible ++ - reg ++ - tm16xx,digits ++ - tm16xx,segment-mapping ++ ++additionalProperties: true ++ ++examples: ++ - | ++ display_client: i2c { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ display@24 { ++ compatible = "titanmec,tm1650"; ++ reg = <0x24>; ++ tm16xx,digits = /bits/ 8 <0 1 2 3>; ++ tm16xx,segment-mapping = /bits/ 8 <0 1 2 3 4 5 6>; ++ ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ led@4,0 { ++ reg = <4 0>; ++ function = "lan"; ++ }; ++ ++ led@4,1 { ++ reg = <4 1>; ++ function = "wlan"; ++ }; ++ }; ++ }; ++ - | ++ display_client: spi { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ display@0 { ++ compatible = "titanmec,tm1628"; ++ reg = <0>; ++ tm16xx,transposed; ++ tm16xx,digits = /bits/ 8 <1 2 3 4>; ++ tm16xx,segment-mapping = /bits/ 8 <0 1 2 3 4 5 6>; ++ ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ led@0,2 { ++ reg = <0 2>; ++ function = "usb"; ++ }; ++ ++ led@0,3 { ++ reg = <0 3>; ++ function = "power"; ++ }; ++ }; ++ }; diff --git a/drivers/auxdisplay/Kconfig b/drivers/auxdisplay/Kconfig index 111111111111..222222222222 100644 --- a/drivers/auxdisplay/Kconfig @@ -47,7 +204,7 @@ new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/auxdisplay/tm16xx.c -@@ -0,0 +1,1167 @@ +@@ -0,0 +1,1187 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Auxiliary Display Driver for TM16XX and compatible LED controllers @@ -72,6 +229,13 @@ index 000000000000..111111111111 + +#define TM16XX_DRIVER_NAME "tm16xx" +#define TM16XX_DEVICE_NAME "display" ++#define DIGIT_SEGMENTS 7 ++#define MIN_SEGMENT 0 ++#define MAX_SEGMENT 7 /* data stored as 8 bits (u8) */ ++ ++static char *default_value = NULL; ++module_param(default_value, charp, 0644); ++MODULE_PARM_DESC(default_value, "Default display value to initialize"); + +/* Forward declarations */ +struct tm16xx_display; @@ -79,17 +243,15 @@ index 000000000000..111111111111 +/** + * struct tm16xx_controller - Controller-specific operations + * @max_brightness: Maximum brightness level supported by the controller -+ * @init: Initialize the controller -+ * @brightness: Set brightness level -+ * @data: Write display data ++ * @init: Configures the controller mode and brightness ++ * @data: Writes display data to the controller + * + * This structure holds function pointers for controller-specific operations. + */ +struct tm16xx_controller { -+ u8 max_brightness; -+ int (*init)(struct tm16xx_display *display, u8 **cmd); -+ int (*brightness)(struct tm16xx_display *display, u8 **cmd); -+ int (*data)(struct tm16xx_display *display, u8 **cmd, int data_index); ++ const u8 max_brightness; ++ const int (*init)(struct tm16xx_display *display); ++ const int (*data)(struct tm16xx_display *display, u8 index, u8 data); +}; + +/** @@ -125,13 +287,14 @@ index 000000000000..111111111111 + * @digits: Array of digits + * @num_digits: Number of digits + * @segment_mapping: Segment mapping array -+ * @num_segments: Number of segments ++ * @digit_bitmask: Bitmask for setting digit values + * @display_data: Display data buffer + * @display_data_len: Length of display data buffer + * @lock: Mutex for concurrent access protection -+ * @flush_brightness: Work structure for brightness update ++ * @flush_init: Work structure for brightness update + * @flush_display: Work structure for display update -+ * @client_write: Function pointer for client write operation ++ * @flush_status: Result of the last flush work ++ * @transpose_display_data: Flag indicating if segments and grids should be transposed when writing data + */ +struct tm16xx_display { + struct device *dev; @@ -145,268 +308,17 @@ index 000000000000..111111111111 + int num_leds; + struct tm16xx_digit *digits; + int num_digits; -+ u8 *segment_mapping; -+ int num_segments; ++ u8 segment_mapping[DIGIT_SEGMENTS]; ++ u8 digit_bitmask; + u8 *display_data; + size_t display_data_len; + struct mutex lock; -+ struct work_struct flush_brightness; ++ struct work_struct flush_init; + struct work_struct flush_display; -+ int (*client_write)(struct tm16xx_display *display, u8 *data, size_t len); ++ int flush_status; ++ bool transpose_display_data; +}; + -+/* Controller-specific functions */ -+static int tm1628_cmd_init(struct tm16xx_display *display, u8 **cmd) -+{ -+ // 01b mode is 5 grids with minimum of 7 segments -+ // tm1618 : 5 digits, 7 segments -+ // tm1620 : 5 digits, 9 segments -+ // tm1628 : 5 digits, 12 segments -+ static const u8 MODE_CMD = 0 << 7 | 0 << 6, MODE = 0 << 1 | 1 << 0; -+ static const u8 DATA_CMD = 0 << 7 | 1 << 6, DATA_ADDR_MODE = 0 << 2, DATA_WRITE_MODE = 0 << 1 | 0 << 0; -+ -+ static u8 cmds[] = { -+ MODE_CMD | MODE, -+ DATA_CMD | DATA_ADDR_MODE | DATA_WRITE_MODE, -+ }; -+ -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static int tm1628_cmd_brightness(struct tm16xx_display *display, u8 **cmd) { -+ static u8 cmds[1]; -+ static const u8 CTRL_CMD = 1 << 7 | 0 << 6, ON_FLAG = 1 << 3, BR_MASK = 7, BR_SHIFT = 0; -+ -+ int i = display->main_led.brightness; -+ cmds[0] = CTRL_CMD | ((i && 1) * (((i-1) & BR_MASK) << BR_SHIFT | ON_FLAG)); -+ -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static int tm1618_cmd_data(struct tm16xx_display *display, u8 **cmd, int i) { -+ static const u8 ADDR_CMD = 1 << 7 | 1 << 6; -+ static const u8 BYTE1_MASK = 0x1F, BYTE1_RSHIFT = 0; -+ static const u8 BYTE2_MASK = ~BYTE1_MASK, BYTE2_RSHIFT = 5-3; -+ static u8 cmds[3]; -+ -+ cmds[0] = ADDR_CMD + i * 2; -+ cmds[1] = (display->display_data[i] & BYTE1_MASK) >> BYTE1_RSHIFT; -+ cmds[2] = (display->display_data[i] & BYTE2_MASK) >> BYTE2_RSHIFT; -+ -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static int tm1628_cmd_data(struct tm16xx_display *display, u8 **cmd, int i) { -+ static const u8 ADDR_CMD = 1 << 7 | 1 << 6; -+ static u8 cmds[3]; -+ -+ cmds[0] = ADDR_CMD + i * 2; -+ cmds[1] = display->display_data[i]; // SEG 1 to 8 -+ cmds[2] = 0; // SEG 9 to 14 -+ -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static int tm1650_cmd_brightness(struct tm16xx_display *display, u8 **cmd) { -+ static u8 cmds[2]; -+ static const u8 ON_FLAG = 1, BR_MASK = 7, BR_SHIFT = 4, SEG7_MODE = 1 << 3; -+ -+ int i = display->main_led.brightness; -+ cmds[0] = 0x48; -+ cmds[1] = (i && 1) * ((i & BR_MASK) << BR_SHIFT | SEG7_MODE | ON_FLAG); -+ -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static int tm1650_cmd_data(struct tm16xx_display *display, u8 **cmd, int i) { -+ static const u8 BASE_ADDR = 0x68; -+ static u8 cmds[2]; -+ -+ cmds[0] = BASE_ADDR + i * 2; -+ cmds[1] = display->display_data[i]; // SEG 1 to 8 -+ -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static int fd655_cmd_brightness(struct tm16xx_display *display, u8 **cmd) { -+ static u8 cmds[2]; -+ static const u8 ON_FLAG = 1, BR_MASK = 3, BR_SHIFT = 5; -+ -+ int i = display->main_led.brightness; -+ cmds[0] = 0x48; -+ cmds[1] = (i && 1) * (((i%3) & BR_MASK) << BR_SHIFT | ON_FLAG); -+ -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static int fd655_cmd_data(struct tm16xx_display *display, u8 **cmd, int i) { -+ static const u8 BASE_ADDR = 0x66; -+ static u8 cmds[2]; -+ -+ cmds[0] = BASE_ADDR + i * 2; -+ cmds[1] = display->display_data[i]; // SEG 1 to 8 -+ -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static int fd6551_cmd_brightness(struct tm16xx_display *display, u8 **cmd) { -+ static u8 cmds[2]; -+ static const u8 ON_FLAG = 1, BR_MASK = 7, BR_SHIFT = 1; -+ -+ int i = display->main_led.brightness; -+ cmds[0] = 0x48; -+ cmds[1] = (i && 1) * ((~(i-1) & BR_MASK) << BR_SHIFT | ON_FLAG); -+ -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+void hbs658_msb_to_lsb(u8 *array, size_t length) { -+ for (size_t i = 0; i < length; i++) { -+ array[i] = (array[i] << 4) | (array[i] >> 4); -+ } -+} -+ -+static int hbs658_cmd_init(struct tm16xx_display *display, u8 **cmd) { -+ static const u8 DATA_CMD = 0 << 7 | 1 << 6, DATA_ADDR_MODE = 0 << 2, DATA_WRITE_MODE = 0 << 1 | 0 << 0; -+ -+ static u8 cmds[] = { -+ DATA_CMD | DATA_ADDR_MODE | DATA_WRITE_MODE, -+ }; -+ -+ hbs658_msb_to_lsb(cmds, ARRAY_SIZE(cmds)); -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static int hbs658_cmd_brightness(struct tm16xx_display *display, u8 **cmd) { -+ static u8 cmds[1]; -+ static const u8 CTRL_CMD = 1 << 7 | 0 << 6, ON_FLAG = 1 << 3, BR_MASK = 7, BR_SHIFT = 0; -+ -+ int i = display->main_led.brightness; -+ cmds[0] = CTRL_CMD | ((i && 1) * (((i-1) & BR_MASK) << BR_SHIFT | ON_FLAG)); -+ -+ hbs658_msb_to_lsb(cmds, ARRAY_SIZE(cmds)); -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static int hbs658_cmd_data(struct tm16xx_display *display, u8 **cmd, int i) { -+ static const u8 ADDR_CMD = 1 << 7 | 1 << 6; -+ static u8 cmds[2]; -+ -+ cmds[0] = ADDR_CMD + i * 2; -+ cmds[1] = display->display_data[i]; -+ -+ hbs658_msb_to_lsb(cmds, ARRAY_SIZE(cmds)); -+ *cmd = cmds; -+ return ARRAY_SIZE(cmds); -+} -+ -+static const struct tm16xx_controller tm1618_controller = { -+ .max_brightness = 8, -+ .init = tm1628_cmd_init, -+ .brightness = tm1628_cmd_brightness, -+ .data = tm1618_cmd_data, -+}; -+ -+static const struct tm16xx_controller tm1628_controller = { -+ .max_brightness = 8, -+ .init = tm1628_cmd_init, -+ .brightness = tm1628_cmd_brightness, -+ .data = tm1628_cmd_data, -+}; -+ -+static const struct tm16xx_controller tm1650_controller = { -+ .max_brightness = 8, -+ .init = NULL, -+ .brightness = tm1650_cmd_brightness, -+ .data = tm1650_cmd_data, -+}; -+ -+static const struct tm16xx_controller fd655_controller = { -+ .max_brightness = 3, -+ .init = NULL, -+ .brightness = fd655_cmd_brightness, -+ .data = fd655_cmd_data, -+}; -+ -+static const struct tm16xx_controller fd6551_controller = { -+ .max_brightness = 8, -+ .init = NULL, -+ .brightness = fd6551_cmd_brightness, -+ .data = fd655_cmd_data, -+}; -+ -+static const struct tm16xx_controller hbs658_controller = { -+ .max_brightness = 8, -+ .init = hbs658_cmd_init, -+ .brightness = hbs658_cmd_brightness, -+ .data = hbs658_cmd_data, -+}; -+ -+static int parse_int_array(const char *buf, int **array) -+{ -+ int *values, value, count = 0, len; -+ const char *ptr = buf; -+ -+ while (1 == sscanf(ptr, "%d %n", &value, &len)) { -+ count++; -+ ptr += len; -+ } -+ -+ if (count == 0) { -+ *array = NULL; -+ return 0; -+ } -+ -+ values = kmalloc(count * sizeof(*values), GFP_KERNEL); -+ if (!values) -+ return -ENOMEM; -+ -+ ptr = buf; -+ count = 0; -+ while (1 == sscanf(ptr, "%d %n", &value, &len)) { -+ values[count++] = value; -+ ptr += len; -+ } -+ -+ *array = values; -+ return count; -+} -+ -+static SEG7_CONVERSION_MAP(map_seg7, MAP_ASCII7SEG_ALPHANUM); -+ -+/** -+ * tm16xx_ascii_to_segments - Convert ASCII character to segment pattern -+ * @display: Pointer to tm16xx_display structure -+ * @c: ASCII character to convert -+ * -+ * Return: Segment pattern for the given ASCII character -+ */ -+static u8 tm16xx_ascii_to_segments(struct tm16xx_display *display, char c) -+{ -+ u8 standard_segments, mapped_segments = 0; -+ int i; -+ -+ standard_segments = map_to_seg7(&map_seg7, c); -+ -+ for (i = 0; i < 7; i++) { -+ if (standard_segments & BIT(i)) -+ mapped_segments |= BIT(display->segment_mapping[i]); -+ } -+ -+ return mapped_segments; -+} -+ +/** + * tm16xx_i2c_write - Write data to I2C client + * @display: Pointer to tm16xx_display structure @@ -451,23 +363,272 @@ index 000000000000..111111111111 + return spi_write(spi, data, len); +} + -+/** -+ * tm16xx_display_flush_brightness - Work function to update brightness -+ * @work: Pointer to work_struct -+ */ -+static void tm16xx_display_flush_brightness(struct work_struct *work) ++/* Controller-specific functions */ ++static int tm1628_init(struct tm16xx_display *display) +{ -+ struct tm16xx_display *display = container_of(work, struct tm16xx_display, flush_brightness); -+ u8 *cmd; -+ int len = -1, ret; ++ static const u8 MODE_CMD = 0 << 7 | 0 << 6; ++ static const u8 MODE_4GRIDS = 0 << 1 | 0 << 0; ++ static const u8 MODE_5GRIDS = 0 << 1 | 1 << 0; ++ static const u8 MODE_6GRIDS = 1 << 1 | 0 << 0; ++ static const u8 MODE_7GRIDS = 1 << 1 | 1 << 0; ++ static const u8 DATA_CMD = 0 << 7 | 1 << 6, DATA_ADDR_MODE = 0 << 2, DATA_WRITE_MODE = 0 << 1 | 0 << 0; ++ static const u8 CTRL_CMD = 1 << 7 | 0 << 6, ON_FLAG = 1 << 3, BR_MASK = 7, BR_SHIFT = 0; ++ const enum led_brightness brightness = display->main_led.brightness; ++ const u8 num_grids = display->transpose_display_data ? DIGIT_SEGMENTS : display->display_data_len; ++ u8 cmd; ++ int ret; + -+ if (display->controller->brightness) { -+ len = display->controller->brightness(display, &cmd); ++ cmd = MODE_CMD; ++ if (num_grids <= 4) { ++ cmd |= MODE_4GRIDS; ++ } else if (num_grids == 5) { ++ cmd |= MODE_5GRIDS; ++ } else if (num_grids == 6) { ++ cmd |= MODE_6GRIDS; ++ } else { ++ cmd |= MODE_7GRIDS; ++ } ++ ret = tm16xx_spi_write(display, &cmd, 1); ++ if (ret < 0) ++ return ret; ++ ++ cmd = DATA_CMD | DATA_ADDR_MODE | DATA_WRITE_MODE; ++ ret = tm16xx_spi_write(display, &cmd, 1); ++ if (ret < 0) ++ return ret; ++ ++ cmd = CTRL_CMD | ((brightness && 1) * (((brightness-1) & BR_MASK) << BR_SHIFT | ON_FLAG)); ++ ret = tm16xx_spi_write(display, &cmd, 1); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static int tm1618_data(struct tm16xx_display *display, u8 index, u8 data) { ++ static const u8 ADDR_CMD = 1 << 7 | 1 << 6; ++ static const u8 BYTE1_MASK = 0x1F, BYTE1_RSHIFT = 0; ++ static const u8 BYTE2_MASK = ~BYTE1_MASK, BYTE2_RSHIFT = 5-3; ++ u8 cmds[3]; ++ ++ cmds[0] = ADDR_CMD + index * 2; ++ cmds[1] = (data & BYTE1_MASK) >> BYTE1_RSHIFT; ++ cmds[2] = (data & BYTE2_MASK) >> BYTE2_RSHIFT; ++ ++ return tm16xx_spi_write(display, cmds, ARRAY_SIZE(cmds)); ++} ++ ++static int tm1628_data(struct tm16xx_display *display, u8 index, u8 data) { ++ static const u8 ADDR_CMD = 1 << 7 | 1 << 6; ++ u8 cmds[3]; ++ ++ cmds[0] = ADDR_CMD + index * 2; ++ cmds[1] = data; // SEG 1 to 8 ++ cmds[2] = 0; // SEG 9 to 14 ++ ++ return tm16xx_spi_write(display, cmds, ARRAY_SIZE(cmds)); ++} ++ ++static int tm1650_init(struct tm16xx_display *display) { ++ u8 cmds[2]; ++ static const u8 ON_FLAG = 1, BR_MASK = 7, BR_SHIFT = 4, SEG8_MODE = 0 << 3; ++ /* SEG7_MODE = 1 << 3 ++ * tm1650 and fd650 have only 4 digits and they ++ * use an 8th segment for the time separator ++ * */ ++ const enum led_brightness brightness = display->main_led.brightness; ++ ++ cmds[0] = 0x48; ++ cmds[1] = (brightness && 1) * ((brightness & BR_MASK) << BR_SHIFT | SEG8_MODE | ON_FLAG); ++ ++ return tm16xx_i2c_write(display, cmds, ARRAY_SIZE(cmds)); ++} ++ ++static int tm1650_data(struct tm16xx_display *display, u8 index, u8 data) { ++ static const u8 BASE_ADDR = 0x68; ++ u8 cmds[2]; ++ ++ cmds[0] = BASE_ADDR + index * 2; ++ cmds[1] = data; // SEG 1 to 8 ++ ++ return tm16xx_i2c_write(display, cmds, ARRAY_SIZE(cmds)); ++} ++ ++static int fd655_init(struct tm16xx_display *display) { ++ u8 cmds[2]; ++ static const u8 ON_FLAG = 1, BR_MASK = 3, BR_SHIFT = 5; ++ const enum led_brightness brightness = display->main_led.brightness; ++ ++ cmds[0] = 0x48; ++ cmds[1] = (brightness && 1) * (((brightness % 3) & BR_MASK) << BR_SHIFT | ON_FLAG); ++ ++ return tm16xx_i2c_write(display, cmds, ARRAY_SIZE(cmds)); ++} ++ ++static int fd655_data(struct tm16xx_display *display, u8 index, u8 data) { ++ static const u8 BASE_ADDR = 0x66; ++ u8 cmds[2]; ++ ++ cmds[0] = BASE_ADDR + index * 2; ++ cmds[1] = data; // SEG 1 to 8 ++ ++ return tm16xx_i2c_write(display, cmds, ARRAY_SIZE(cmds)); ++} ++ ++static int fd6551_init(struct tm16xx_display *display) { ++ u8 cmds[2]; ++ static const u8 ON_FLAG = 1, BR_MASK = 7, BR_SHIFT = 1; ++ const enum led_brightness brightness = display->main_led.brightness; ++ ++ cmds[0] = 0x48; ++ cmds[1] = (brightness && 1) * ((~(brightness - 1) & BR_MASK) << BR_SHIFT | ON_FLAG); ++ ++ return tm16xx_i2c_write(display, cmds, ARRAY_SIZE(cmds)); ++} ++ ++static void hbs658_swap_nibbles(u8 *data, size_t len) ++{ ++ for (size_t i = 0; i < len; i++) { ++ data[i] = (data[i] << 4) | (data[i] >> 4); ++ } ++} ++ ++static int hbs658_init(struct tm16xx_display *display) { ++ u8 cmd; ++ static const u8 DATA_CMD = 0 << 7 | 1 << 6, DATA_ADDR_MODE = 0 << 2, DATA_WRITE_MODE = 0 << 1 | 0 << 0; ++ static const u8 CTRL_CMD = 1 << 7 | 0 << 6, ON_FLAG = 1 << 3, BR_MASK = 7, BR_SHIFT = 0; ++ const enum led_brightness brightness = display->main_led.brightness; ++ int ret; ++ ++ cmd = DATA_CMD | DATA_ADDR_MODE | DATA_WRITE_MODE; ++ hbs658_swap_nibbles(&cmd, 1); ++ ret = tm16xx_spi_write(display, &cmd, 1); ++ if (ret < 0) ++ return ret; ++ ++ cmd = CTRL_CMD | ((brightness && 1) * (((brightness - 1) & BR_MASK) << BR_SHIFT | ON_FLAG)); ++ hbs658_swap_nibbles(&cmd, 1); ++ ret = tm16xx_spi_write(display, &cmd, 1); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static int hbs658_data(struct tm16xx_display *display, u8 index, u8 data) { ++ static const u8 ADDR_CMD = 1 << 7 | 1 << 6; ++ u8 cmds[2]; ++ ++ cmds[0] = ADDR_CMD + index * 2; ++ cmds[1] = data; ++ ++ hbs658_swap_nibbles(cmds, ARRAY_SIZE(cmds)); ++ return tm16xx_spi_write(display, cmds, ARRAY_SIZE(cmds)); ++} ++ ++static const struct tm16xx_controller tm1618_controller = { ++ .max_brightness = 8, ++ .init = tm1628_init, ++ .data = tm1618_data, ++}; ++ ++static const struct tm16xx_controller tm1628_controller = { ++ .max_brightness = 8, ++ .init = tm1628_init, ++ .data = tm1628_data, ++}; ++ ++static const struct tm16xx_controller tm1650_controller = { ++ .max_brightness = 8, ++ .init = tm1650_init, ++ .data = tm1650_data, ++}; ++ ++static const struct tm16xx_controller fd655_controller = { ++ .max_brightness = 3, ++ .init = fd655_init, ++ .data = fd655_data, ++}; ++ ++static const struct tm16xx_controller fd6551_controller = { ++ .max_brightness = 8, ++ .init = fd6551_init, ++ .data = fd655_data, ++}; ++ ++static const struct tm16xx_controller hbs658_controller = { ++ .max_brightness = 8, ++ .init = hbs658_init, ++ .data = hbs658_data, ++}; ++ ++static int tm16xx_parse_int_array(const char *buf, int **array) ++{ ++ int *values, value, count = 0, len; ++ const char *ptr = buf; ++ ++ while (1 == sscanf(ptr, "%d %n", &value, &len)) { ++ count++; ++ ptr += len; + } + -+ if (len > 0) { ++ if (count == 0) { ++ *array = NULL; ++ return 0; ++ } ++ ++ values = kmalloc(count * sizeof(*values), GFP_KERNEL); ++ if (!values) ++ return -ENOMEM; ++ ++ ptr = buf; ++ count = 0; ++ while (1 == sscanf(ptr, "%d %n", &value, &len)) { ++ values[count++] = value; ++ ptr += len; ++ } ++ ++ *array = values; ++ return count; ++} ++ ++static SEG7_CONVERSION_MAP(map_seg7, MAP_ASCII7SEG_ALPHANUM); ++ ++/** ++ * tm16xx_ascii_to_segments - Convert ASCII character to segment pattern ++ * @display: Pointer to tm16xx_display structure ++ * @c: ASCII character to convert ++ * ++ * Return: Segment pattern for the given ASCII character ++ */ ++static u8 tm16xx_ascii_to_segments(struct tm16xx_display *display, char c) ++{ ++ u8 standard_segments, mapped_segments = 0; ++ int i; ++ ++ standard_segments = map_to_seg7(&map_seg7, c); ++ ++ for (i = 0; i < DIGIT_SEGMENTS; i++) { ++ if (standard_segments & BIT(i)) ++ mapped_segments |= BIT(display->segment_mapping[i]); ++ } ++ ++ return mapped_segments; ++} ++ ++/** ++ * tm16xx_display_flush_init - Work function to update controller configuration (mode and brightness) ++ * @work: Pointer to work_struct ++ */ ++static void tm16xx_display_flush_init(struct work_struct *work) ++{ ++ struct tm16xx_display *display = container_of(work, struct tm16xx_display, flush_init); ++ int ret; ++ ++ if (display->controller->init) { + mutex_lock(&display->lock); -+ ret = display->client_write(display, cmd, len); ++ ret = display->controller->init(display); ++ display->flush_status = ret; + mutex_unlock(&display->lock); + if (ret < 0) + dev_err(display->dev, "Failed to set brightness: %d\n", ret); @@ -481,18 +642,13 @@ index 000000000000..111111111111 +static void tm16xx_display_flush_data(struct work_struct *work) +{ + struct tm16xx_display *display = container_of(work, struct tm16xx_display, flush_display); -+ u8 *cmd; -+ int i, len = -1, ret; ++ int i, ret = 0; + + mutex_lock(&display->lock); + -+ for (i = 0; i < display->display_data_len; i++) { -+ if (display->controller->data) { -+ len = display->controller->data(display, &cmd, i); -+ } -+ -+ if (len > 0) { -+ ret = display->client_write(display, cmd, len); ++ if (display->controller->data) { ++ for (i = 0; i < display->display_data_len; i++) { ++ ret = display->controller->data(display, i, display->display_data[i]); + if (ret < 0) { + dev_err(display->dev, "Failed to write display data: %d\n", ret); + break; @@ -500,41 +656,42 @@ index 000000000000..111111111111 + } + } + ++ display->flush_status = ret; + mutex_unlock(&display->lock); +} + +/** -+ * tm16xx_display_init - Initialize the display -+ * @display: Pointer to tm16xx_display structure -+ * -+ * Return: 0 on success, negative error code on failure ++ * tm16xx_display_flush_data_transposed - Transposed flush work function ++ * @work: Pointer to work_struct + */ -+static int tm16xx_display_init(struct tm16xx_display *display) ++static void tm16xx_display_flush_data_transposed(struct work_struct *work) +{ -+ u8 *cmd; -+ int len = -1, ret; ++ struct tm16xx_display *display = container_of(work, struct tm16xx_display, flush_display); ++ int i, j, ret = 0; ++ u8 transposed_data; + -+ if (display->controller->init) { -+ len = display->controller->init(display, &cmd); ++ mutex_lock(&display->lock); ++ ++ if (display->controller->data) { ++ /* Write operations based on number of segments */ ++ for (i = MIN_SEGMENT; i <= MAX_SEGMENT; i++) { ++ /* Gather bits from each grid for this segment */ ++ transposed_data = 0; ++ for (j = 0; j < display->display_data_len; j++) { ++ if (display->display_data[j] & BIT(i)) ++ transposed_data |= BIT(MAX_SEGMENT - j); ++ } ++ ++ ret = display->controller->data(display, i, transposed_data); ++ if (ret < 0) { ++ dev_err(display->dev, "Failed to write transposed data: %d\n", ret); ++ break; ++ } ++ } + } + -+ if (len > 0) { -+ mutex_lock(&display->lock); -+ ret = display->client_write(display, cmd, len); -+ mutex_unlock(&display->lock); -+ if (ret < 0) -+ return ret; -+ } -+ -+ schedule_work(&display->flush_brightness); -+ flush_work(&display->flush_brightness); -+ -+ memset(display->display_data, 0xFF, display->display_data_len); -+ schedule_work(&display->flush_display); -+ flush_work(&display->flush_display); -+ memset(display->display_data, 0x00, display->display_data_len); -+ -+ return 0; ++ display->flush_status = ret; ++ mutex_unlock(&display->lock); +} + +/** @@ -548,8 +705,8 @@ index 000000000000..111111111111 + flush_work(&display->flush_display); + + display->main_led.brightness = LED_OFF; -+ schedule_work(&display->flush_brightness); -+ flush_work(&display->flush_brightness); ++ schedule_work(&display->flush_init); ++ flush_work(&display->flush_init); + + dev_info(display->dev, "Display turned off\n"); +} @@ -565,7 +722,7 @@ index 000000000000..111111111111 + struct tm16xx_display *display = dev_get_drvdata(led_cdev->dev->parent); + + led_cdev->brightness = brightness; -+ schedule_work(&display->flush_brightness); ++ schedule_work(&display->flush_init); +} + +/** @@ -641,7 +798,9 @@ index 000000000000..111111111111 + data = 0; + } + -+ display->display_data[digit->grid] = data; ++ display->display_data[digit->grid] = ++ (display->display_data[digit->grid] & ~display->digit_bitmask) | ++ (data & display->digit_bitmask); + } + + schedule_work(&display->flush_display); @@ -668,24 +827,6 @@ index 000000000000..111111111111 +} + +/** -+ * tm16xx_num_segments_show - Show the number of segments per digit -+ * @dev: The device struct -+ * @attr: The device_attribute struct -+ * @buf: The output buffer -+ * -+ * This function returns the number of segments per digit in the display. -+ * -+ * Return: Number of bytes written to buf -+ */ -+static ssize_t tm16xx_num_segments_show(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ struct led_classdev *led_cdev = dev_get_drvdata(dev); -+ struct tm16xx_display *display = dev_get_drvdata(led_cdev->dev->parent); -+ -+ return sprintf(buf, "%d\n", display->num_segments); -+} -+ -+/** + * tm16xx_segment_mapping_show - Show the current segment mapping + * @dev: The device struct + * @attr: The device_attribute struct @@ -701,7 +842,7 @@ index 000000000000..111111111111 + struct tm16xx_display *display = dev_get_drvdata(led_cdev->dev->parent); + int i, count = 0; + -+ for (i = 0; i < display->num_segments; i++) { ++ for (i = 0; i < DIGIT_SEGMENTS; i++) { + count += sprintf(buf + count, "%d ", display->segment_mapping[i]); + } + count += sprintf(buf + count, "\n"); @@ -728,24 +869,27 @@ index 000000000000..111111111111 + struct tm16xx_display *display = dev_get_drvdata(led_cdev->dev->parent); + int *array, ret, i; + -+ ret = parse_int_array(buf, &array); ++ ret = tm16xx_parse_int_array(buf, &array); + if (ret < 0) + return ret; + -+ if (ret != display->num_segments) { ++ if (ret != DIGIT_SEGMENTS) { + kfree(array); + return -EINVAL; + } + -+ for (i = 0; i < display->num_segments; i++) { -+ if (array[i] < 0 || array[i] > 7) { ++ for (i = 0; i < DIGIT_SEGMENTS; i++) { ++ if (array[i] < MIN_SEGMENT || ++ array[i] > MAX_SEGMENT) { + kfree(array); + return -EINVAL; + } + } + -+ for (i = 0; i < display->num_segments; i++) { ++ display->digit_bitmask = 0; ++ for (i = 0; i < DIGIT_SEGMENTS; i++) { + display->segment_mapping[i] = (u8) array[i]; ++ display->digit_bitmask |= BIT(display->segment_mapping[i]); + } + + kfree(array); @@ -796,7 +940,7 @@ index 000000000000..111111111111 + int *array, ret, i, j; + bool found; + -+ ret = parse_int_array(buf, &array); ++ ret = tm16xx_parse_int_array(buf, &array); + if (ret < 0) + return ret; + @@ -866,7 +1010,6 @@ index 000000000000..111111111111 + +static DEVICE_ATTR(value, 0644, tm16xx_display_value_show, tm16xx_display_value_store); +static DEVICE_ATTR(num_digits, 0444, tm16xx_num_digits_show, NULL); -+static DEVICE_ATTR(num_segments, 0444, tm16xx_num_segments_show, NULL); +static DEVICE_ATTR(segments, 0644, tm16xx_segment_mapping_show, tm16xx_segment_mapping_store); +static DEVICE_ATTR(digits, 0644, tm16xx_digits_ordering_show, tm16xx_digits_ordering_store); +static DEVICE_ATTR(map_seg7, 0644, tm16xx_map_seg7_show, tm16xx_map_seg7_store); @@ -874,7 +1017,6 @@ index 000000000000..111111111111 +static struct attribute *tm16xx_main_led_attrs[] = { + &dev_attr_value.attr, + &dev_attr_num_digits.attr, -+ &dev_attr_num_segments.attr, + &dev_attr_segments.attr, + &dev_attr_digits.attr, + &dev_attr_map_seg7.attr, @@ -883,6 +1025,35 @@ index 000000000000..111111111111 +ATTRIBUTE_GROUPS(tm16xx_main_led); + +/** ++ * tm16xx_display_init - Initialize the display ++ * @display: Pointer to tm16xx_display structure ++ * ++ * Return: 0 on success, negative error code on failure ++ */ ++static int tm16xx_display_init(struct tm16xx_display *display) ++{ ++ schedule_work(&display->flush_init); ++ flush_work(&display->flush_init); ++ if (display->flush_status < 0) ++ return display->flush_status; ++ ++ if (default_value && strlen(default_value) > 0) { ++ tm16xx_display_value_store( ++ display->main_led.dev, NULL, ++ default_value, strlen(default_value)); ++ } else { ++ memset(display->display_data, 0xFF, display->display_data_len); ++ schedule_work(&display->flush_display); ++ flush_work(&display->flush_display); ++ memset(display->display_data, 0x00, display->display_data_len); ++ if (display->flush_status < 0) ++ return display->flush_status; ++ } ++ ++ return 0; ++} ++ ++/** + * tm16xx_parse_dt - Parse device tree data + * @dev: Pointer to device structure + * @display: Pointer to tm16xx_display structure @@ -895,6 +1066,8 @@ index 000000000000..111111111111 + int ret, i, max_grid = 0; + u8 *digits; + ++ display->transpose_display_data = device_property_read_bool(dev, "tm16xx,transposed"); ++ + ret = device_property_count_u8(dev, "tm16xx,digits"); + if (ret < 0) { + dev_err(dev, "Failed to count 'tm16xx,digits' property: %d\n", ret); @@ -925,24 +1098,23 @@ index 000000000000..111111111111 + + devm_kfree(dev, digits); + -+ display->num_segments = device_property_count_u8(dev, "tm16xx,segment-mapping"); -+ if (display->num_segments < 0) { -+ dev_err(dev, "Failed to count 'tm16xx,segment-mapping' property: %d\n", display->num_segments); -+ return display->num_segments; -+ } -+ -+ dev_dbg(dev, "Number of segments: %d\n", display->num_segments); -+ -+ display->segment_mapping = devm_kcalloc(dev, display->num_segments, sizeof(*display->segment_mapping), GFP_KERNEL); -+ if (!display->segment_mapping) -+ return -ENOMEM; -+ -+ ret = device_property_read_u8_array(dev, "tm16xx,segment-mapping", display->segment_mapping, display->num_segments); ++ ret = device_property_read_u8_array(dev, "tm16xx,segment-mapping", display->segment_mapping, DIGIT_SEGMENTS); + if (ret < 0) { + dev_err(dev, "Failed to read 'tm16xx,segment-mapping' property: %d\n", ret); + return ret; + } + ++ display->digit_bitmask = 0; ++ for (i = 0; i < DIGIT_SEGMENTS; i++) { ++ if (display->segment_mapping[i] < MIN_SEGMENT || ++ display->segment_mapping[i] > MAX_SEGMENT) { ++ dev_err(dev, "Invalid 'tm16xx,segment-mapping' value: %d (must be between %d and %d)\n", display->segment_mapping[i], MIN_SEGMENT, MAX_SEGMENT); ++ return -EINVAL; ++ } ++ ++ display->digit_bitmask |= BIT(display->segment_mapping[i]); ++ } ++ + display->num_leds = 0; + device_for_each_child_node(dev, child) { + u32 reg[2]; @@ -988,8 +1160,15 @@ index 000000000000..111111111111 + } + + mutex_init(&display->lock); -+ INIT_WORK(&display->flush_brightness, tm16xx_display_flush_brightness); -+ INIT_WORK(&display->flush_display, tm16xx_display_flush_data); ++ INIT_WORK(&display->flush_init, tm16xx_display_flush_init); ++ ++ /* Initialize work structure with appropriate flush function */ ++ if (display->transpose_display_data) { ++ INIT_WORK(&display->flush_display, tm16xx_display_flush_data_transposed); ++ dev_info(display->dev, "Operating in transposed mode\n"); ++ } else { ++ INIT_WORK(&display->flush_display, tm16xx_display_flush_data); ++ } + + display->main_led.name = TM16XX_DEVICE_NAME; + display->main_led.brightness = display->controller->max_brightness; @@ -1068,7 +1247,6 @@ index 000000000000..111111111111 + display->client.spi = spi; + display->dev = &spi->dev; + display->controller = controller; -+ display->client_write = tm16xx_spi_write; + + spi_set_drvdata(spi, display); + @@ -1138,7 +1316,6 @@ index 000000000000..111111111111 + display->client.i2c = client; + display->dev = &client->dev; + display->controller = controller; -+ display->client_write = tm16xx_i2c_write; + + i2c_set_clientdata(client, display); + diff --git a/patch/kernel/rockchip64-6.16/general-drm-panel-add-yixian-yx0345-panel.patch b/patch/kernel/rockchip64-6.16/general-drm-panel-add-yixian-yx0345-panel.patch new file mode 100644 index 0000000..5e3d342 --- /dev/null +++ b/patch/kernel/rockchip64-6.16/general-drm-panel-add-yixian-yx0345-panel.patch @@ -0,0 +1,378 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Sun, 17 Aug 2025 14:24:30 +0300 +Subject: drm/panel: Add Yixian YX0345 panel + +--- + drivers/gpu/drm/panel/Kconfig | 9 + + drivers/gpu/drm/panel/Makefile | 1 + + drivers/gpu/drm/panel/panel-yixian-yx0345wv00v2.c | 329 ++++++++++ + 3 files changed, 339 insertions(+) + +diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/panel/Kconfig ++++ b/drivers/gpu/drm/panel/Kconfig +@@ -1087,6 +1087,15 @@ config DRM_PANEL_WIDECHIPS_WS2401 + 480x800 display controller used in panels such as Samsung LMS380KF01. + This display is used in the Samsung Galaxy Ace 2 GT-I8160 (Codina). + ++config DRM_PANEL_YIXIAN_YX0345 ++ tristate "Yixian YX0345 DPI panel driver" ++ depends on OF ++ depends on DRM_MIPI_DSI ++ help ++ Say Y here if you want to enable support for the Yixian YX0345WV00V2 ++ 480x800 display controller used in SBCc such as NanoPi M6s. ++ ++ + config DRM_PANEL_XINPENG_XPP055C272 + tristate "Xinpeng XPP055C272 panel driver" + depends on OF +diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/panel/Makefile ++++ b/drivers/gpu/drm/panel/Makefile +@@ -112,3 +112,4 @@ obj-$(CONFIG_DRM_PANEL_VISIONOX_VTDR6130) += panel-visionox-vtdr6130.o + obj-$(CONFIG_DRM_PANEL_VISIONOX_R66451) += panel-visionox-r66451.o + obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o + obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o ++obj-$(CONFIG_DRM_PANEL_YIXIAN_YX0345) += panel-yixian-yx0345wv00v2.o +diff --git a/drivers/gpu/drm/panel/panel-yixian-yx0345wv00v2.c b/drivers/gpu/drm/panel/panel-yixian-yx0345wv00v2.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/gpu/drm/panel/panel-yixian-yx0345wv00v2.c +@@ -0,0 +1,329 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Copyright (c) 2025 Muhammed Efe Cetin ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++struct yixian_yx0345_panel_info { ++ struct drm_display_mode mode; ++ const struct regulator_bulk_data *regulators; ++ int num_regulators; ++ struct yixian_yx0345_panel_data *panel_data; ++}; ++ ++struct yixian_yx0345 { ++ struct drm_panel panel; ++ const struct yixian_yx0345_panel_info *panel_info; ++ struct mipi_dsi_device *dsi; ++ struct gpio_desc *reset_gpio; ++ struct regulator_bulk_data *supplies; ++ int num_supplies; ++}; ++ ++struct yixian_yx0345_cmd { ++ u8 delay; ++ u8 data[32]; ++ u8 len; ++}; ++ ++static const struct yixian_yx0345_cmd yixian_yx0345_init_code[] = { ++ { 0x0A, { 0x01, 0x00 }, 0x02 }, ++ { 0x7D, { 0x11, 0x00 }, 0x02 }, ++ { 0x00, { 0xFF, 0x77, 0x01, 0x00, 0x00, 0x13 }, 0x06 }, ++ { 0x00, { 0xEF, 0x08 }, 0x02 }, ++ { 0x00, { 0xFF, 0x77, 0x01, 0x00, 0x00, 0x10 }, 0x06 }, ++ { 0x00, { 0xC0, 0x63, 0x00 }, 0x03 }, ++ { 0x00, { 0xC1, 0x14, 0x14 }, 0x03 }, ++ { 0x00, { 0xC2, 0x37, 0x02 }, 0x03 }, ++ { 0x00, { 0xCC, 0x10 }, 0x02 }, ++ { 0x00, ++ { 0xB0, 0xC5, 0x11, 0x1B, 0x0D, 0x11, 0x07, 0x0A, 0x09, 0x08, 0x24, ++ 0x05, 0x12, 0x10, 0xA9, 0x32, 0xDF }, ++ 0x11 }, ++ { 0x00, ++ { 0xB1, 0xC5, 0x19, 0x21, 0x0B, 0x0E, 0x03, 0x0C, 0x07, 0x07, 0x26, ++ 0x04, 0x12, 0x11, 0xAA, 0x32, 0xDF }, ++ 0x11 }, ++ { 0x00, { 0xFF, 0x77, 0x01, 0x00, 0x00, 0x11 }, 0x06 }, ++ { 0x00, { 0xB0, 0x4D }, 0x02 }, ++ { 0x00, { 0xB1, 0x59 }, 0x02 }, ++ { 0x00, { 0xB2, 0x81 }, 0x02 }, ++ { 0x00, { 0xB3, 0x80 }, 0x02 }, ++ { 0x00, { 0xB5, 0x4E }, 0x02 }, ++ { 0x00, { 0xB7, 0x85 }, 0x02 }, ++ { 0x00, { 0xB8, 0x32 }, 0x02 }, ++ { 0x00, { 0xBB, 0x03 }, 0x02 }, ++ { 0x00, { 0xC1, 0x08 }, 0x02 }, ++ { 0x00, { 0xC2, 0x08 }, 0x02 }, ++ { 0x00, { 0xD0, 0x88 }, 0x02 }, ++ { 0x00, { 0xE0, 0x00, 0x00, 0x02 }, 0x04 }, ++ { 0x00, ++ { 0xE1, 0x06, 0x28, 0x08, 0x28, 0x05, 0x28, 0x07, 0x28, 0x0E, 0x33, ++ 0x33 }, ++ 0x0C }, ++ { 0x00, ++ { 0xE2, 0x30, 0x30, 0x33, 0x33, 0x34, 0x00, 0x00, 0x00, 0x34, 0x00, ++ 0x00, 0x00 }, ++ 0x0D }, ++ { 0x00, { 0xE3, 0x00, 0x00, 0x33, 0x33 }, 0x05 }, ++ { 0x00, { 0xE4, 0x44, 0x44 }, 0x03 }, ++ { 0x00, ++ { 0xE5, 0x09, 0x2F, 0x2C, 0x8C, 0x0B, 0x31, 0x2C, 0x8C, 0x0D, 0x33, ++ 0x2C, 0x8C, 0x0F, 0x35, 0x2C, 0x8C }, ++ 0x11 }, ++ { 0x00, { 0xE6, 0x00, 0x00, 0x33, 0x33 }, 0x05 }, ++ { 0x00, { 0xE7, 0x44, 0x44 }, 0x03 }, ++ { 0x00, ++ { 0xE8, 0x08, 0x2E, 0x2C, 0x8C, 0x0A, 0x30, 0x2C, 0x8C, 0x0C, 0x32, ++ 0x2C, 0x8C, 0x0E, 0x34, 0x2C, 0x8C }, ++ 0x11 }, ++ { 0x00, { 0xE9, 0x36, 0x00 }, 0x03 }, ++ { 0x00, { 0xEB, 0x00, 0x01, 0xE4, 0xE4, 0x44, 0x88, 0x40 }, 0x08 }, ++ { 0x00, ++ { 0xED, 0xFF, 0xFC, 0xB2, 0x45, 0x67, 0xFA, 0x01, 0xFF, 0xFF, 0x10, ++ 0xAF, 0x76, 0x54, 0x2B, 0xCF, 0xFF }, ++ 0x11 }, ++ { 0x00, { 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54 }, 0x07 }, ++ { 0x00, { 0xFF, 0x77, 0x01, 0x00, 0x00, 0x13 }, 0x06 }, ++ { 0x00, { 0xE8, 0x00, 0x0E }, 0x03 }, ++ { 0x78, { 0x11, 0x00 }, 0x02 }, ++ { 0x0A, { 0xE8, 0x00, 0x0C }, 0x03 }, ++ { 0x00, { 0xE8, 0x00, 0x00 }, 0x03 }, ++ { 0x00, { 0xFF, 0x77, 0x01, 0x00, 0x00, 0x00 }, 0x06 }, ++ { 0x00, { 0x36, 0x00 }, 0x02 }, ++ { 0x00, { 0x29, 0x00 }, 0x02 }, ++}; ++ ++struct yixian_yx0345_panel_data { ++ struct yixian_yx0345_cmd *init_code; ++ int len; ++}; ++ ++static struct yixian_yx0345_panel_data yx0345_panel_data = { ++ .init_code = (struct yixian_yx0345_cmd *)yixian_yx0345_init_code, ++ .len = ARRAY_SIZE(yixian_yx0345_init_code) ++}; ++ ++static inline struct yixian_yx0345 *to_yixian_yx0345(struct drm_panel *panel) ++{ ++ return container_of(panel, struct yixian_yx0345, panel); ++} ++ ++static void yixian_yx0345_reset(struct yixian_yx0345 *ctx) ++{ ++ if (ctx->reset_gpio) { ++ gpiod_set_value_cansleep(ctx->reset_gpio, 0); ++ msleep(60); ++ gpiod_set_value_cansleep(ctx->reset_gpio, 1); ++ msleep(60); ++ gpiod_set_value_cansleep(ctx->reset_gpio, 0); ++ msleep(60); ++ } ++} ++ ++static int yixian_yx0345_prepare(struct drm_panel *panel) ++{ ++ struct yixian_yx0345 *ctx = to_yixian_yx0345(panel); ++ struct mipi_dsi_multi_context mctx = { .dsi = ctx->dsi }; ++ int ret; ++ ++ ret = regulator_bulk_enable(ctx->num_supplies, ctx->supplies); ++ if (ret < 0) ++ return ret; ++ ++ yixian_yx0345_reset(ctx); ++ ++ msleep(60); ++ ++ struct yixian_yx0345_panel_data *panel_data = ++ ctx->panel_info->panel_data; ++ ++ for (int i = 0; i < panel_data->len; i++) { ++ struct yixian_yx0345_cmd code = panel_data->init_code[i]; ++ ++ mipi_dsi_dcs_write_buffer_multi(&mctx, &code.data, code.len); ++ ++ if (code.delay > 0) { ++ mipi_dsi_msleep(&mctx, code.delay); ++ } ++ } ++ ++ mipi_dsi_msleep(&mctx, 10); ++ ++ return 0; ++} ++ ++static int yixian_yx0345_unprepare(struct drm_panel *panel) ++{ ++ struct yixian_yx0345 *ctx = to_yixian_yx0345(panel); ++ ++ gpiod_set_value_cansleep(ctx->reset_gpio, 1); ++ regulator_bulk_disable(ctx->num_supplies, ctx->supplies); ++ ++ msleep(60); ++ ++ return 0; ++} ++ ++static int yixian_yx0345_disable(struct drm_panel *panel) ++{ ++ struct yixian_yx0345 *yx0345 = to_yixian_yx0345(panel); ++ struct mipi_dsi_multi_context ctx = { .dsi = yx0345->dsi }; ++ int ret; ++ ++ u8 data = 0x00; ++ ret = mipi_dsi_dcs_write(ctx.dsi, 0x28, &data, 1); ++ if (ret < 0) ++ return ret; ++ ++ ret = mipi_dsi_dcs_write(ctx.dsi, 0x10, &data, 1); ++ if (ret < 0) ++ return ret; ++ ++ mipi_dsi_msleep(&ctx, 70); ++ ++ return ctx.accum_err; ++} ++ ++static int yixian_yx0345_get_modes(struct drm_panel *panel, ++ struct drm_connector *connector) ++{ ++ struct yixian_yx0345 *ctx = to_yixian_yx0345(panel); ++ ++ return drm_connector_helper_get_modes_fixed(connector, ++ &ctx->panel_info->mode); ++} ++ ++static const struct drm_panel_funcs yixian_yx0345_funcs = { ++ .prepare = yixian_yx0345_prepare, ++ .unprepare = yixian_yx0345_unprepare, ++ .get_modes = yixian_yx0345_get_modes, ++ .disable = yixian_yx0345_disable, ++}; ++ ++static int yixian_yx0345_probe(struct mipi_dsi_device *dsi) ++{ ++ struct device *dev = &dsi->dev; ++ struct yixian_yx0345 *ctx; ++ int ret = 0; ++ ++ ctx = devm_drm_panel_alloc(dev, struct yixian_yx0345, panel, ++ &yixian_yx0345_funcs, ++ DRM_MODE_CONNECTOR_DSI); ++ if (IS_ERR(ctx)) ++ return PTR_ERR(ctx); ++ ++ ctx->panel_info = device_get_match_data(dev); ++ if (!ctx->panel_info) ++ return -EINVAL; ++ ++ ctx->num_supplies = ctx->panel_info->num_regulators; ++ ret = devm_regulator_bulk_get_const(&dsi->dev, ++ ctx->panel_info->num_regulators, ++ ctx->panel_info->regulators, ++ &ctx->supplies); ++ if (ret < 0) ++ return ret; ++ ++ ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); ++ if (IS_ERR(ctx->reset_gpio)) ++ return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), ++ "Failed to get reset-gpios\n"); ++ ++ ctx->dsi = dsi; ++ mipi_dsi_set_drvdata(dsi, ctx); ++ ++ dsi->lanes = 2; ++ dsi->format = MIPI_DSI_FMT_RGB888; ++ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | ++ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; ++ ctx->panel.prepare_prev_first = true; ++ ++ ret = drm_panel_of_backlight(&ctx->panel); ++ if (ret) ++ return ret; ++ ++ drm_panel_add(&ctx->panel); ++ ++ ret = mipi_dsi_attach(dsi); ++ if (ret < 0) { ++ dev_err(dev, "Failed to attach to DSI host: %d\n", ret); ++ drm_panel_remove(&ctx->panel); ++ } ++ ++ return ret; ++} ++ ++static void yixian_yx0345_remove(struct mipi_dsi_device *dsi) ++{ ++ struct yixian_yx0345 *ctx = mipi_dsi_get_drvdata(dsi); ++ int ret; ++ ++ ret = mipi_dsi_detach(dsi); ++ if (ret < 0) ++ dev_err(&dsi->dev, "Failed to detach DSI host: %d\n", ret); ++ ++ drm_panel_remove(&ctx->panel); ++} ++ ++static const struct regulator_bulk_data yx0345_regulators[] = { ++ { ++ .supply = "vcc2v8", ++ }, /* 2.8V */ ++ { ++ .supply = "vcc1v8", ++ }, /* 1.8V */ ++ { ++ .supply = "vcc3v3", ++ }, /* 3.3v */ ++}; ++ ++static const struct yixian_yx0345_panel_info yx0345_info = { ++ .mode = { ++ .clock = 29700, ++ .hdisplay = 480, ++ .hsync_start = 480 + 40, ++ .hsync_end = 480 + 40 + 30, ++ .htotal = 480 + 40 + 30 + 32, ++ .vdisplay = 800, ++ .vsync_start = 800 + 20, ++ .vsync_end = 800 + 20 + 20, ++ .vtotal = 800 + 20 + 20 + 10, ++ .width_mm = 45, ++ .height_mm = 75, ++ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, ++ .type = DRM_MODE_TYPE_DRIVER, ++ }, ++ .regulators = yx0345_regulators, ++ .num_regulators = ARRAY_SIZE(yx0345_regulators), ++ .panel_data = &yx0345_panel_data, ++}; ++ ++static const struct of_device_id yixian_yx0345_of_match[] = { ++ { .compatible = "yixian,yx0345wv00v2", .data = &yx0345_info }, ++ { /*sentinel*/ } ++}; ++MODULE_DEVICE_TABLE(of, yixian_yx0345_of_match); ++ ++static struct mipi_dsi_driver yixian_yx0345_driver = { ++ .probe = yixian_yx0345_probe, ++ .remove = yixian_yx0345_remove, ++ .driver = { ++ .name = "panel-yixian-yx0345wv00v2", ++ .of_match_table = yixian_yx0345_of_match, ++ }, ++}; ++module_mipi_dsi_driver(yixian_yx0345_driver); ++ ++MODULE_AUTHOR("Muhammed Efe Cetin "); ++MODULE_DESCRIPTION("DRM driver for Yixian YX0345WV00V2 DSI panels"); ++MODULE_LICENSE("GPL"); +-- +Armbian + diff --git a/patch/kernel/rockchip64-6.14/general-drm-rockchip-Set-dma-mask-to-64-bit.patch b/patch/kernel/rockchip64-6.16/general-drm-rockchip-Set-dma-mask-to-64-bit.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-drm-rockchip-Set-dma-mask-to-64-bit.patch rename to patch/kernel/rockchip64-6.16/general-drm-rockchip-Set-dma-mask-to-64-bit.patch diff --git a/patch/kernel/rockchip64-6.14/general-fix-es8316-kernel-panic.patch b/patch/kernel/rockchip64-6.16/general-fix-es8316-kernel-panic.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-fix-es8316-kernel-panic.patch rename to patch/kernel/rockchip64-6.16/general-fix-es8316-kernel-panic.patch diff --git a/patch/kernel/rockchip64-6.14/general-fix-mmc-signal-voltage-before-reboot.patch b/patch/kernel/rockchip64-6.16/general-fix-mmc-signal-voltage-before-reboot.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-fix-mmc-signal-voltage-before-reboot.patch rename to patch/kernel/rockchip64-6.16/general-fix-mmc-signal-voltage-before-reboot.patch diff --git a/patch/kernel/rockchip64-6.14/general-hdmi-clock-fixes.patch b/patch/kernel/rockchip64-6.16/general-hdmi-clock-fixes.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-hdmi-clock-fixes.patch rename to patch/kernel/rockchip64-6.16/general-hdmi-clock-fixes.patch diff --git a/patch/kernel/rockchip64-6.14/general-increase-spdif-dma-burst.patch b/patch/kernel/rockchip64-6.16/general-increase-spdif-dma-burst.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-increase-spdif-dma-burst.patch rename to patch/kernel/rockchip64-6.16/general-increase-spdif-dma-burst.patch diff --git a/patch/kernel/rockchip64-6.14/general-increasing_DMA_block_memory_allocation_to_2048.patch b/patch/kernel/rockchip64-6.16/general-increasing_DMA_block_memory_allocation_to_2048.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-increasing_DMA_block_memory_allocation_to_2048.patch rename to patch/kernel/rockchip64-6.16/general-increasing_DMA_block_memory_allocation_to_2048.patch diff --git a/patch/kernel/rockchip64-6.14/general-pl330-01-fix-periodic-transfers.patch b/patch/kernel/rockchip64-6.16/general-pl330-01-fix-periodic-transfers.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-pl330-01-fix-periodic-transfers.patch rename to patch/kernel/rockchip64-6.16/general-pl330-01-fix-periodic-transfers.patch diff --git a/patch/kernel/rockchip64-6.14/general-pl330-02-add-support-for-interleaved-transfers.patch b/patch/kernel/rockchip64-6.16/general-pl330-02-add-support-for-interleaved-transfers.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-pl330-02-add-support-for-interleaved-transfers.patch rename to patch/kernel/rockchip64-6.16/general-pl330-02-add-support-for-interleaved-transfers.patch diff --git a/patch/kernel/rockchip64-6.14/general-pl330-04-bigger-mcode-buffer.patch b/patch/kernel/rockchip64-6.16/general-pl330-04-bigger-mcode-buffer.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-pl330-04-bigger-mcode-buffer.patch rename to patch/kernel/rockchip64-6.16/general-pl330-04-bigger-mcode-buffer.patch diff --git a/patch/kernel/rockchip64-6.14/general-pl330-05-fix-unbalanced-power-down.patch b/patch/kernel/rockchip64-6.16/general-pl330-05-fix-unbalanced-power-down.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-pl330-05-fix-unbalanced-power-down.patch rename to patch/kernel/rockchip64-6.16/general-pl330-05-fix-unbalanced-power-down.patch diff --git a/patch/kernel/rockchip64-6.14/general-pl330-06-fix-buffer-underruns.patch b/patch/kernel/rockchip64-6.16/general-pl330-06-fix-buffer-underruns.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-pl330-06-fix-buffer-underruns.patch rename to patch/kernel/rockchip64-6.16/general-pl330-06-fix-buffer-underruns.patch diff --git a/patch/kernel/rockchip64-6.14/general-possibility-of-disabling-rk808-rtc.patch b/patch/kernel/rockchip64-6.16/general-possibility-of-disabling-rk808-rtc.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-possibility-of-disabling-rk808-rtc.patch rename to patch/kernel/rockchip64-6.16/general-possibility-of-disabling-rk808-rtc.patch diff --git a/patch/kernel/rockchip64-6.14/general-rk808-configurable-switch-voltage-steps.patch b/patch/kernel/rockchip64-6.16/general-rk808-configurable-switch-voltage-steps.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/general-rk808-configurable-switch-voltage-steps.patch rename to patch/kernel/rockchip64-6.16/general-rk808-configurable-switch-voltage-steps.patch diff --git a/patch/kernel/rockchip64-6.14/general-rockchip-overlays.patch b/patch/kernel/rockchip64-6.16/general-rockchip-overlays.patch similarity index 57% rename from patch/kernel/rockchip64-6.14/general-rockchip-overlays.patch rename to patch/kernel/rockchip64-6.16/general-rockchip-overlays.patch index a7fdef6..0353dad 100644 --- a/patch/kernel/rockchip64-6.14/general-rockchip-overlays.patch +++ b/patch/kernel/rockchip64-6.16/general-rockchip-overlays.patch @@ -1,24 +1,26 @@ From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Martin Ayotte Date: Wed, 5 Dec 2018 15:00:44 -0500 -Subject: add overlays framework for rockchip (scripts/Makefile.lib only) +Subject: add overlays framework for rockchip (scripts/Makefile.build only) - rpardini: real overlays are now bare in "overlay" directory and are handled directly by the patching scripts. No more null-patching of overlays. + +Signed-off-by: Werner --- - scripts/Makefile.lib | 3 +++ + scripts/Makefile.build | 3 +++ 1 file changed, 3 insertions(+) -diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 111111111111..222222222222 100644 ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -75,6 +75,9 @@ always-y += $(hostprogs-always-y) $(hostprogs-always-m) +--- a/scripts/Makefile.build ++++ b/scripts/Makefile.build +@@ -107,6 +107,9 @@ always-y += $(hostprogs-always-y) $(hostprogs-always-m) userprogs += $(userprogs-always-y) $(userprogs-always-m) always-y += $(userprogs-always-y) $(userprogs-always-m) +# Overlay targets -+extra-y += $(dtbo-y) $(scr-y) $(dtbotxt-y) ++extra-y += $(dtbo-y) $(scr-y) $(dtbotxt-y) + # Add subdir path diff --git a/patch/kernel/rockchip64-6.14/general-st7796-driver.patch b/patch/kernel/rockchip64-6.16/general-st7796-driver.patch similarity index 98% rename from patch/kernel/rockchip64-6.14/general-st7796-driver.patch rename to patch/kernel/rockchip64-6.16/general-st7796-driver.patch index c216a0c..8d1012c 100644 --- a/patch/kernel/rockchip64-6.14/general-st7796-driver.patch +++ b/patch/kernel/rockchip64-6.16/general-st7796-driver.patch @@ -13,7 +13,7 @@ diff --git a/drivers/staging/fbtft/Kconfig b/drivers/staging/fbtft/Kconfig index 111111111111..222222222222 100644 --- a/drivers/staging/fbtft/Kconfig +++ b/drivers/staging/fbtft/Kconfig -@@ -80,6 +80,12 @@ config FB_TFT_ILI9481 +@@ -70,6 +70,12 @@ config FB_TFT_ILI9481 help Generic Framebuffer support for ILI9481 @@ -25,7 +25,7 @@ index 111111111111..222222222222 100644 + config FB_TFT_ILI9486 tristate "FB driver for the ILI9486 LCD Controller" - depends on FB_TFT + help diff --git a/drivers/staging/fbtft/Makefile b/drivers/staging/fbtft/Makefile index 111111111111..222222222222 100644 --- a/drivers/staging/fbtft/Makefile diff --git a/patch/kernel/rockchip64-6.14/general-v4l2-iep-driver.patch b/patch/kernel/rockchip64-6.16/general-v4l2-iep-driver.patch similarity index 99% rename from patch/kernel/rockchip64-6.14/general-v4l2-iep-driver.patch rename to patch/kernel/rockchip64-6.16/general-v4l2-iep-driver.patch index 14c6700..53ff2d5 100644 --- a/patch/kernel/rockchip64-6.14/general-v4l2-iep-driver.patch +++ b/patch/kernel/rockchip64-6.16/general-v4l2-iep-driver.patch @@ -155,7 +155,7 @@ diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip index 111111111111..222222222222 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -993,14 +993,25 @@ crypto: crypto@ff8a0000 { +@@ -990,14 +990,25 @@ crypto: crypto@ff8a0000 { reset-names = "crypto-rst"; }; diff --git a/patch/kernel/rockchip64-6.14/general-v4l2-rkvdec-01-vp9.patch b/patch/kernel/rockchip64-6.16/general-v4l2-rkvdec-01-vp9.patch similarity index 96% rename from patch/kernel/rockchip64-6.14/general-v4l2-rkvdec-01-vp9.patch rename to patch/kernel/rockchip64-6.16/general-v4l2-rkvdec-01-vp9.patch index ef16e26..1e7b98f 100644 --- a/patch/kernel/rockchip64-6.14/general-v4l2-rkvdec-01-vp9.patch +++ b/patch/kernel/rockchip64-6.16/general-v4l2-rkvdec-01-vp9.patch @@ -13,7 +13,7 @@ diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvde index 111111111111..222222222222 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1128,9 +1128,9 @@ static void rkvdec_remove(struct platform_device *pdev) +@@ -1176,9 +1176,9 @@ static void rkvdec_remove(struct platform_device *pdev) cancel_delayed_work_sync(&rkvdec->watchdog_work); @@ -51,7 +51,7 @@ diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/ index 111111111111..222222222222 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c -@@ -392,6 +392,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, +@@ -417,6 +417,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, return 0; } @@ -221,7 +221,7 @@ index 111111111111..222222222222 100644 #include #include #include -@@ -718,6 +721,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, +@@ -766,6 +769,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, pm_runtime_mark_last_busy(rkvdec->dev); pm_runtime_put_autosuspend(rkvdec->dev); @@ -233,7 +233,7 @@ index 111111111111..222222222222 100644 rkvdec_job_finish_no_pm(ctx, result); } -@@ -755,6 +763,33 @@ static void rkvdec_device_run(void *priv) +@@ -803,6 +811,33 @@ static void rkvdec_device_run(void *priv) if (WARN_ON(!desc)) return; @@ -267,7 +267,7 @@ index 111111111111..222222222222 100644 ret = pm_runtime_resume_and_get(rkvdec->dev); if (ret < 0) { -@@ -1021,6 +1056,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) +@@ -1069,6 +1104,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) if (cancel_delayed_work(&rkvdec->watchdog_work)) { struct rkvdec_ctx *ctx; @@ -279,7 +279,7 @@ index 111111111111..222222222222 100644 ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); rkvdec_job_finish(ctx, state); } -@@ -1038,6 +1078,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1086,6 +1126,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); if (ctx) { dev_err(rkvdec->dev, "Frame processing timed out!\n"); @@ -287,7 +287,7 @@ index 111111111111..222222222222 100644 writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); -@@ -1106,6 +1147,18 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1154,6 +1195,18 @@ static int rkvdec_probe(struct platform_device *pdev) return ret; } @@ -336,7 +336,7 @@ index 111111111111..222222222222 100644 struct rkvdec_ctx; struct rkvdec_ctrl_desc { -@@ -96,6 +103,8 @@ struct rkvdec_dev { +@@ -110,6 +117,8 @@ struct rkvdec_dev { void __iomem *regs; struct mutex vdev_lock; /* serializes ioctls */ struct delayed_work watchdog_work; @@ -374,7 +374,7 @@ index 111111111111..222222222222 100644 #define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000) #define ROCKCHIP_VPU981_MIN_SIZE 64 -@@ -447,13 +448,20 @@ static int rk3588_vpu981_hw_init(struct hantro_dev *vpu) +@@ -461,13 +462,20 @@ static int rk3588_vpu981_hw_init(struct hantro_dev *vpu) return 0; } @@ -396,7 +396,7 @@ index 111111111111..222222222222 100644 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev; -@@ -709,7 +717,7 @@ const struct hantro_variant rk3288_vpu_variant = { +@@ -723,7 +731,7 @@ const struct hantro_variant rk3288_vpu_variant = { .codec_ops = rk3288_vpu_codec_ops, .irqs = rockchip_vpu1_irqs, .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), diff --git a/patch/kernel/rockchip64-6.14/media-0001-Add-rkvdec2-Support-v3.patch b/patch/kernel/rockchip64-6.16/media-0001-Add-rkvdec2-Support-v3.patch similarity index 99% rename from patch/kernel/rockchip64-6.14/media-0001-Add-rkvdec2-Support-v3.patch rename to patch/kernel/rockchip64-6.16/media-0001-Add-rkvdec2-Support-v3.patch index 0f0a2d7..a2c5141 100644 --- a/patch/kernel/rockchip64-6.14/media-0001-Add-rkvdec2-Support-v3.patch +++ b/patch/kernel/rockchip64-6.16/media-0001-Add-rkvdec2-Support-v3.patch @@ -3679,7 +3679,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -2883,6 +2883,16 @@ system_sram2: sram@ff001000 { +@@ -3093,6 +3093,16 @@ system_sram2: sram@ff001000 { ranges = <0x0 0x0 0xff001000 0xef000>; #address-cells = <1>; #size-cells = <1>; @@ -3696,7 +3696,7 @@ index 111111111111..222222222222 100644 }; pinctrl: pinctrl { -@@ -2952,6 +2962,46 @@ gpio4: gpio@fec50000 { +@@ -3162,6 +3172,46 @@ gpio4: gpio@fec50000 { #interrupt-cells = <2>; }; }; diff --git a/patch/kernel/rockchip64-6.14/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch b/patch/kernel/rockchip64-6.16/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch rename to patch/kernel/rockchip64-6.16/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch diff --git a/patch/kernel/rockchip64-6.14/media-0003-rk3568-disable-hantro-h264.patch b/patch/kernel/rockchip64-6.16/media-0003-rk3568-disable-hantro-h264.patch similarity index 96% rename from patch/kernel/rockchip64-6.14/media-0003-rk3568-disable-hantro-h264.patch rename to patch/kernel/rockchip64-6.16/media-0003-rk3568-disable-hantro-h264.patch index ca2a6c8..5cd53cb 100644 --- a/patch/kernel/rockchip64-6.14/media-0003-rk3568-disable-hantro-h264.patch +++ b/patch/kernel/rockchip64-6.16/media-0003-rk3568-disable-hantro-h264.patch @@ -20,7 +20,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1126,7 +1126,7 @@ power-domain@RK3588_PD_SDMMC { +@@ -1141,7 +1141,7 @@ power-domain@RK3588_PD_SDMMC { }; vpu121: video-codec@fdb50000 { @@ -57,7 +57,7 @@ diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/medi index 111111111111..222222222222 100644 --- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c +++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c -@@ -726,10 +726,9 @@ const struct hantro_variant rk3288_vpu_variant = { +@@ -740,10 +740,9 @@ const struct hantro_variant rk3288_vpu_variant = { const struct hantro_variant rk3328_vpu_variant = { .dec_offset = 0x400, @@ -71,7 +71,7 @@ index 111111111111..222222222222 100644 .codec_ops = rk3399_vpu_codec_ops, .irqs = rockchip_vdpu2_irqs, .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), -@@ -773,20 +772,6 @@ const struct hantro_variant rk3568_vepu_variant = { +@@ -787,20 +786,6 @@ const struct hantro_variant rk3568_vepu_variant = { .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) }; diff --git a/patch/kernel/rockchip64-6.16/net-usb-r8152-add-LED-configuration-from-OF._patch b/patch/kernel/rockchip64-6.16/net-usb-r8152-add-LED-configuration-from-OF._patch new file mode 100644 index 0000000..f3dfdc0 --- /dev/null +++ b/patch/kernel/rockchip64-6.16/net-usb-r8152-add-LED-configuration-from-OF._patch @@ -0,0 +1,79 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Sun, 26 Jul 2020 02:38:31 +0200 +Subject: net: usb: r8152: add LED configuration from OF + +This adds the ability to configure the LED configuration register using +OF. This way, the correct value for board specific LED configuration can +be determined. + +Signed-off-by: David Bauer +--- + drivers/net/usb/r8152.c | 23 ++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c +index 111111111111..222222222222 100644 +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -7017,6 +7018,22 @@ static void rtl_tally_reset(struct r8152 *tp) + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); + } + ++static int r8152_led_configuration(struct r8152 *tp) ++{ ++ u32 led_data; ++ int ret; ++ ++ ret = of_property_read_u32(tp->udev->dev.of_node, "realtek,led-data", ++ &led_data); ++ ++ if (ret) ++ return ret; ++ ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data); ++ ++ return 0; ++} ++ + static void r8152b_init(struct r8152 *tp) + { + u32 ocp_data; +@@ -7058,6 +7075,8 @@ static void r8152b_init(struct r8152 *tp) + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); ++ ++ r8152_led_configuration(tp); + } + + static void r8153_init(struct r8152 *tp) +@@ -7198,6 +7217,8 @@ static void r8153_init(struct r8152 *tp) + tp->coalesce = COALESCE_SLOW; + break; + } ++ ++ r8152_led_configuration(tp); + } + + static void r8153b_init(struct r8152 *tp) +@@ -7280,6 +7301,8 @@ static void r8153b_init(struct r8152 *tp) + rtl_tally_reset(tp); + + tp->coalesce = 15000; /* 15 us */ ++ ++ r8152_led_configuration(tp); + } + + static void r8153c_init(struct r8152 *tp) +-- +Armbian + diff --git a/patch/kernel/rockchip64-6.14/regulator-add-fan53200-driver.patch b/patch/kernel/rockchip64-6.16/regulator-add-fan53200-driver.patch similarity index 99% rename from patch/kernel/rockchip64-6.14/regulator-add-fan53200-driver.patch rename to patch/kernel/rockchip64-6.16/regulator-add-fan53200-driver.patch index d9aad0c..e1c116e 100644 --- a/patch/kernel/rockchip64-6.14/regulator-add-fan53200-driver.patch +++ b/patch/kernel/rockchip64-6.16/regulator-add-fan53200-driver.patch @@ -24,7 +24,7 @@ diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 111111111111..222222222222 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig -@@ -784,6 +784,7 @@ CONFIG_REGULATOR_BD9571MWV=y +@@ -792,6 +792,7 @@ CONFIG_REGULATOR_BD9571MWV=y CONFIG_REGULATOR_CROS_EC=y CONFIG_REGULATOR_DA9211=m CONFIG_REGULATOR_FAN53555=y @@ -36,7 +36,7 @@ diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 111111111111..222222222222 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig -@@ -421,6 +421,17 @@ config REGULATOR_FAN53880 +@@ -432,6 +432,17 @@ config REGULATOR_FAN53880 (PMIC), it is controlled by I2C and provides one BUCK, one BOOST and four LDO outputs. @@ -58,7 +58,7 @@ diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 111111111111..222222222222 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile -@@ -50,6 +50,7 @@ obj-$(CONFIG_REGULATOR_DBX500_PRCMU) += dbx500-prcmu.o +@@ -51,6 +51,7 @@ obj-$(CONFIG_REGULATOR_DBX500_PRCMU) += dbx500-prcmu.o obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o obj-$(CONFIG_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_REGULATOR_FAN53880) += fan53880.o diff --git a/patch/kernel/rockchip64-6.14/rk356x-add-rkvdec2-support.patch b/patch/kernel/rockchip64-6.16/rk356x-add-rkvdec2-support.patch similarity index 95% rename from patch/kernel/rockchip64-6.14/rk356x-add-rkvdec2-support.patch rename to patch/kernel/rockchip64-6.16/rk356x-add-rkvdec2-support.patch index b615aa9..d32a62f 100644 --- a/patch/kernel/rockchip64-6.14/rk356x-add-rkvdec2-support.patch +++ b/patch/kernel/rockchip64-6.16/rk356x-add-rkvdec2-support.patch @@ -16,7 +16,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi -@@ -369,6 +369,19 @@ usb2phy1_grf: syscon@fdca8000 { +@@ -380,6 +380,19 @@ usb2phy1_grf: syscon@fdca8000 { reg = <0x0 0xfdca8000 0x0 0x8000>; }; @@ -36,7 +36,7 @@ index 111111111111..222222222222 100644 pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; -@@ -554,7 +567,7 @@ gpu: gpu@fde60000 { +@@ -565,7 +578,7 @@ gpu: gpu@fde60000 { }; vpu: video-codec@fdea0400 { @@ -45,7 +45,7 @@ index 111111111111..222222222222 100644 reg = <0x0 0xfdea0000 0x0 0x800>; interrupts = ; interrupt-names = "vdpu"; -@@ -605,6 +618,26 @@ vepu_mmu: iommu@fdee0800 { +@@ -616,6 +629,26 @@ vepu_mmu: iommu@fdee0800 { #iommu-cells = <0>; }; diff --git a/patch/kernel/rockchip64-6.14/rk3588-0010-fix-clk-divisions.patch b/patch/kernel/rockchip64-6.16/rk3588-0010-fix-clk-divisions.patch similarity index 99% rename from patch/kernel/rockchip64-6.14/rk3588-0010-fix-clk-divisions.patch rename to patch/kernel/rockchip64-6.16/rk3588-0010-fix-clk-divisions.patch index 4a38b65..21d5f10 100644 --- a/patch/kernel/rockchip64-6.14/rk3588-0010-fix-clk-divisions.patch +++ b/patch/kernel/rockchip64-6.16/rk3588-0010-fix-clk-divisions.patch @@ -15,7 +15,7 @@ diff --git a/include/linux/math.h b/include/linux/math.h index 111111111111..222222222222 100644 --- a/include/linux/math.h +++ b/include/linux/math.h -@@ -36,6 +36,17 @@ +@@ -48,6 +48,17 @@ #define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP diff --git a/patch/kernel/rockchip64-6.14/rk35xx-montjoie-crypto-v2-rk35xx.patch b/patch/kernel/rockchip64-6.16/rk35xx-montjoie-crypto-v2-rk35xx.patch similarity index 99% rename from patch/kernel/rockchip64-6.14/rk35xx-montjoie-crypto-v2-rk35xx.patch rename to patch/kernel/rockchip64-6.16/rk35xx-montjoie-crypto-v2-rk35xx.patch index 6843ddf..eb3a47c 100644 --- a/patch/kernel/rockchip64-6.14/rk35xx-montjoie-crypto-v2-rk35xx.patch +++ b/patch/kernel/rockchip64-6.16/rk35xx-montjoie-crypto-v2-rk35xx.patch @@ -102,8 +102,8 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1948,6 +1948,18 @@ sdhci: mmc@fe2e0000 { - status = "disabled"; +@@ -2061,6 +2061,18 @@ rng@fe378000 { + resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; }; + crypto: crypto@fe370000 { @@ -142,7 +142,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi -@@ -1074,6 +1074,18 @@ rng: rng@fe388000 { +@@ -1090,6 +1090,18 @@ rng: rng@fe388000 { status = "disabled"; }; @@ -345,7 +345,7 @@ diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 111111111111..222222222222 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig -@@ -726,6 +726,35 @@ config CRYPTO_DEV_TEGRA +@@ -720,6 +720,35 @@ config CRYPTO_DEV_TEGRA Select this to enable Tegra Security Engine which accelerates various AES encryption/decryption and HASH algorithms. diff --git a/patch/kernel/rockchip64-6.16/temporary-workaround-dma-reset.patch b/patch/kernel/rockchip64-6.16/temporary-workaround-dma-reset.patch new file mode 100644 index 0000000..5a79587 --- /dev/null +++ b/patch/kernel/rockchip64-6.16/temporary-workaround-dma-reset.patch @@ -0,0 +1,21 @@ +Temporary patch to workaround a DMA reset issue with rockchip +devices experienced at least on rk3288 and rk3328 with a message +like this: + +rk_gmac-dwmac ff290000.ethernet end0: Failed to reset the dma + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +index e0fb06af1f94..156a5d25d1fd 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -3133,8 +3133,8 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) + + ret = stmmac_reset(priv, priv->ioaddr); + if (ret) { +- netdev_err(priv->dev, "Failed to reset the dma\n"); +- return ret; ++ netdev_warn(priv->dev, "Failed to reset the dma, device will work with reduced throughput\n"); ++ ret = 0; + } + + /* DMA Configuration */ diff --git a/patch/kernel/rockchip64-6.14/wifi-4003-add-bcm43342-chip.patch b/patch/kernel/rockchip64-6.16/wifi-4003-add-bcm43342-chip.patch similarity index 100% rename from patch/kernel/rockchip64-6.14/wifi-4003-add-bcm43342-chip.patch rename to patch/kernel/rockchip64-6.16/wifi-4003-add-bcm43342-chip.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Add-board-BananaPi-BPI-M4-Zero.patch b/patch/kernel/sunxi-6.14/patches.armbian/Add-board-BananaPi-BPI-M4-Zero.patch deleted file mode 100644 index 65bfb91..0000000 --- a/patch/kernel/sunxi-6.14/patches.armbian/Add-board-BananaPi-BPI-M4-Zero.patch +++ /dev/null @@ -1,407 +0,0 @@ -From 4c92bf1cdc05ee6b7426c2450e9dcd6ffebad533 Mon Sep 17 00:00:00 2001 -From: Patrick Yavitz -Date: Tue, 7 Jan 2025 06:58:55 -0500 -Subject: Add board BananaPi BPI-M4-Zero - -Signed-off-by: Patrick Yavitz ---- - arch/arm64/boot/dts/allwinner/Makefile | 1 + - .../sun50i-h618-bananapi-m4-zero.dts | 110 ++++++++ - .../allwinner/sun50i-h618-bananapi-m4.dtsi | 256 ++++++++++++++++++ - 3 files changed, 367 insertions(+) - create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts - create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4.dtsi - -diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile -index 67f738f9b513..a676c57aad1d 100644 ---- a/arch/arm64/boot/dts/allwinner/Makefile -+++ b/arch/arm64/boot/dts/allwinner/Makefile -@@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb -+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts -new file mode 100644 -index 000000000000..46e07893c653 ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts -@@ -0,0 +1,110 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2024 Patrick Yavitz -+ */ -+ -+/dts-v1/; -+ -+#include "sun50i-h618-bananapi-m4.dtsi" -+ -+/ { -+ model = "BananaPi BPI-M4-Zero"; -+ compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h618"; -+ -+ aliases { -+ ethernet0 = &emac1; -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c3 = &i2c3; -+ i2c4 = &i2c4; -+ serial4 = &uart4; -+ serial5 = &uart5; -+ spi1 = &spi1; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-0 { -+ color = ; -+ function = LED_FUNCTION_STATUS; -+ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+}; -+ -+/* Connected to an on-board RTL8821CU USB WiFi chip. */ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ehci2 { -+ status = "okay"; -+}; -+ -+&ehci3 { -+ status = "okay"; -+}; -+ -+&emac1 { -+ status = "disabled"; -+ pinctrl-0 = <&ext_rgmii_pins>; -+ pinctrl-names = "default"; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-supply = <®_dldo1>; -+ allwinner,rx-delay-ps = <3100>; -+ allwinner,tx-delay-ps = <700>; -+}; -+ -+&mdio1 { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ -+/* SDIO */ -+&mmc1 { -+ status = "disabled"; -+ bus-width = <4>; -+ max-frequency = <100000000>; -+ -+ non-removable; -+ disable-wp; -+ -+ /* WiFi firmware requires power to be kept while in suspend */ -+ keep-power-in-suspend; -+ -+ mmc-pwrseq = <&wifi_pwrseq>; -+ -+ cd-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */ -+ vmmc-supply = <®_vcc3v3>; -+ -+ sdio: wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ }; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&ohci2 { -+ status = "okay"; -+}; -+ -+&ohci3 { -+ status = "okay"; -+}; -+ -+&usbotg { -+ status = "okay"; -+ dr_mode = "peripheral"; -+}; -+ -+&usbphy { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4.dtsi -new file mode 100644 -index 000000000000..e9640439e02c ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4.dtsi -@@ -0,0 +1,256 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2024 Patrick Yavitz -+ */ -+ -+/dts-v1/; -+ -+#include "sun50i-h616.dtsi" -+#include "sun50i-h616-cpu-opp.dtsi" -+ -+#include -+#include -+#include -+#include -+ -+/ { -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ connector { -+ compatible = "hdmi-connector"; -+ type = "d"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ reg_usb_vbus: regulator-usb-vbus { -+ /* Separate discrete regulator for the USB ports */ -+ compatible = "regulator-fixed"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "usb-vbus"; -+ vin-supply = <®_vcc5v>; -+ }; -+ -+ reg_vcc5v: regulator-vcc5v { -+ /* Board wide 5V supply directly from the USB-C socket */ -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vcc-5v"; -+ }; -+ -+ reg_vcc3v3: regulator-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-3v3"; -+ vin-supply = <®_vcc5v>; -+ }; -+ -+ reg_vcc1v8: regulator-vcc1v8 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc-1v8"; -+ vin-supply = <®_vcc3v3>; -+ }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rtc CLK_OSC32K_FANOUT>; -+ clock-names = "ext_clock"; -+ pinctrl-0 = <&x32clk_fanout_pin>; -+ pinctrl-names = "default"; -+ post-power-on-delay-ms = <200>; -+ reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <®_dcdc2>; -+}; -+ -+&de { -+ status = "okay"; -+}; -+ -+&gpu { -+ status = "disabled"; -+ mali-supply = <®_dcdc1>; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&i2c0 { -+ status = "disabled"; -+ pinctrl-0 = <&i2c0_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&i2c1 { -+ status = "disabled"; -+ pinctrl-0 = <&i2c1_pi_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+ pinctrl-0 = <&i2c3_pg_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&i2c4 { -+ status = "disabled"; -+ pinctrl-0 = <&i2c4_pg_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&ir { -+ status = "disabled"; -+ pinctrl-0 = <&ir_rx_pin>; -+ pinctrl-names = "default"; -+}; -+ -+/* SD card */ -+&mmc0 { -+ status = "okay"; -+ bus-width = <4>; -+ max-frequency = <50000000>; -+ -+ disable-wp; -+ -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ -+ vmmc-supply = <®_vcc3v3>; -+}; -+ -+/* eMMC */ -+&mmc2 { -+ status = "okay"; -+ bus-width = <8>; -+ cap-mmc-hw-reset; -+ mmc-hs200-1_8v; -+ -+ non-removable; -+ disable-wp; -+ -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc1v8>; -+}; -+ -+&pio { -+ vcc-pc-supply = <®_aldo1>; -+ vcc-pf-supply = <®_dldo1>; -+ vcc-pg-supply = <®_dldo1>; -+ vcc-ph-supply = <®_dldo1>; -+ vcc-pi-supply = <®_dldo1>; -+}; -+ -+&r_i2c { -+ status = "okay"; -+ axp313: pmic@36 { -+ compatible = "x-powers,axp313a"; -+ reg = <0x36>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ interrupt-parent = <&pio>; -+ -+ vin1-supply = <®_vcc5v>; -+ vin2-supply = <®_vcc5v>; -+ vin3-supply = <®_vcc5v>; -+ -+ regulators { -+ reg_aldo1: aldo1 { -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc-1v8-pll"; -+ }; -+ -+ reg_dldo1: dldo1 { -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-3v3-io"; -+ }; -+ -+ reg_dcdc1: dcdc1 { -+ regulator-always-on; -+ regulator-min-microvolt = <810000>; -+ regulator-max-microvolt = <990000>; -+ regulator-name = "vdd-gpu-sys"; -+ }; -+ -+ reg_dcdc2: dcdc2 { -+ regulator-always-on; -+ regulator-min-microvolt = <810000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-name = "vdd-cpu"; -+ }; -+ -+ reg_dcdc3: dcdc3 { -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-name = "vdd-dram"; -+ }; -+ }; -+ }; -+}; -+ -+&spi1 { -+ status = "disabled"; -+ pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>; -+ pinctrl-names = "default"; -+ -+ spidev@1 { -+ compatible = "rohm,dh2228fv"; -+ reg = <1>; -+ spi-max-frequency = <1000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+ pinctrl-0 = <&uart0_ph_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&uart1 { -+ status = "disabled"; -+ pinctrl-0 = <&uart1_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&uart4 { -+ status = "disabled"; -+ pinctrl-0 = <&uart4_pi_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&uart5 { -+ status = "disabled"; -+ pinctrl-0 = <&uart5_pins>; -+ pinctrl-names = "default"; -+}; --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch b/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch deleted file mode 100644 index 5580614..0000000 --- a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 274fb3935e7d3c889a3ad70f765fb1f036b8d761 Mon Sep 17 00:00:00 2001 -From: The-going <48602507+The-going@users.noreply.github.com> -Date: Sun, 24 Jul 2022 13:56:50 +0300 -Subject: arm64: dts: sun50i-h6-orangepi.dtsi: Rollback r_rsb to r_i2c - -This fix affects two boards: -sun50i-h6-orangepi-lite2.dts -sun50i-h6-orangepi-one-plus.dts - -It also depends on the revision of the board. -If your board fails when working with this fix, just disable -it by adding (-) minus to the first position of the line -in which the patch is written in the series.conf file. ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -index 1c0e8288ebf6..947fb4636aaa 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -@@ -130,12 +130,12 @@ &r_pio { - vcc-pm-supply = <®_bldo3>; - }; - --&r_rsb { -+&r_i2c { - status = "okay"; - -- axp805: pmic@745 { -+ axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; -- reg = <0x745>; -+ reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = ; - interrupt-controller; --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch b/patch/kernel/sunxi-6.14/patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch deleted file mode 100644 index 73e24e0..0000000 --- a/patch/kernel/sunxi-6.14/patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 7f350d05012873c129458241792d005ef1344d9a Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Fri, 21 Feb 2025 00:58:00 +0000 -Subject: dt-bindings: gpu: mali-bifrost: Add Allwinner H616 compatible - -The Allwinner H616 SoC has a Mali-G31 MP2 GPU, which is of the Mali -Bifrost family. -Add the SoC specific compatible string and pair it with the bifrost -fallback compatible. - -Signed-off-by: Andre Przywara ---- - Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml -index 735c7f06c24e..439d5c59daa2 100644 ---- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml -+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml -@@ -17,6 +17,7 @@ properties: - oneOf: - - items: - - enum: -+ - allwinner,sun50i-h616-mali - - amlogic,meson-g12a-mali - - mediatek,mt8183-mali - - mediatek,mt8183b-mali --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch b/patch/kernel/sunxi-6.14/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch deleted file mode 100644 index 93010e4..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch +++ /dev/null @@ -1,45 +0,0 @@ -From c8ae813c02fca7c7c43317e894a6516e09012bd8 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Mon, 15 Aug 2022 02:23:37 +0200 -Subject: ASoC: rockchip: Fix doubling of playback speed after system sleep - -There is some issue with CRU on RK3399 that can be reproduced by: - -- playing some audio and stopping the playback (so that runtime PM suspends I2S) -- putting system to deep sleep and resuming it (using mainline TF-A) -- playing some audio (audio plays at 2x the normal speed) - -If the audio is kept playing during system sleep cycle, the issue -does not manifest. Relevant registers in CRU are identical in bug/ -no-bug scenarios, so this patch is just touching the CRU registers -without actually changing anything in the end. Touching the registers -fixes the playback speed, though. - -Inspired by: https://github.com/djselbeck/linux/commit/cb4be5dec3fa18c4b344c11fed3fc57aa3bea424 - -Signed-off-by: Ondrej Jirman ---- - sound/soc/rockchip/rockchip_i2s.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c -index 4315da4a47c1..b6602eaea194 100644 ---- a/sound/soc/rockchip/rockchip_i2s.c -+++ b/sound/soc/rockchip/rockchip_i2s.c -@@ -114,6 +114,13 @@ static int i2s_runtime_resume(struct device *dev) - if (ret) - clk_disable_unprepare(i2s->mclk); - -+ if (ret == 0) { -+ unsigned long rate = clk_get_rate(i2s->mclk); -+ -+ clk_set_rate(i2s->mclk, rate - 1); -+ clk_set_rate(i2s->mclk, rate); -+ } -+ - return ret; - } - --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch b/patch/kernel/sunxi-6.14/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch deleted file mode 100644 index cb947ec..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch +++ /dev/null @@ -1,215 +0,0 @@ -From 71cc8805841a3e8e908770977756c51c555ac801 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= -Date: Tue, 22 Nov 2016 01:01:49 +0100 -Subject: Add README.md with information and u-boot patches - -Signed-off-by: Ondrej Jirman ---- - ...Fix-PLL1-setup-to-never-use-dividers.patch | 33 ++++ - README.md | 154 ++++++++++++++++++ - 2 files changed, 187 insertions(+) - create mode 100644 0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch - create mode 100644 README.md - -diff --git a/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch b/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch -new file mode 100644 -index 000000000000..2b892e805a2b ---- /dev/null -+++ b/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch -@@ -0,0 +1,33 @@ -+From 7f5071f906f79bdc99d6b4b0ccf0cb280abe740b Mon Sep 17 00:00:00 2001 -+From: Ondrej Jirman -+Date: Tue, 20 Dec 2016 11:25:12 +0100 -+Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers -+ -+Kernel would lower the divider on first CLK change and cause the -+lock up. -+--- -+ arch/arm/mach-sunxi/clock_sun6i.c | 7 +++---- -+ 1 file changed, 3 insertions(+), 4 deletions(-) -+ -+diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c -+index 50fb302a19..91aa2a0478 100644 -+--- a/arch/arm/mach-sunxi/clock_sun6i.c -++++ b/arch/arm/mach-sunxi/clock_sun6i.c -+@@ -94,11 +94,10 @@ void clock_set_pll1(unsigned int clk) -+ int k = 1; -+ int m = 1; -+ -+- if (clk > 1152000000) { -+- k = 2; -+- } else if (clk > 768000000) { -++ if (clk >= 1368000000) { -+ k = 3; -+- m = 2; -++ } else if (clk >= 768000000) { -++ k = 2; -+ } -+ -+ /* Switch to 24MHz clock while changing PLL1 */ -+-- -+2.11.0 -+ -diff --git a/README.md b/README.md -new file mode 100644 -index 000000000000..74c4c16416d3 ---- /dev/null -+++ b/README.md -@@ -0,0 +1,154 @@ -+Mainline linux kernel for Orange Pi PC/PC2/PC3/One, TBS A711, PinePhone (Pro), PocketBook Touch Lux 3 -+------------------------------------------------------------------------------------------------------ -+ -+This kernel tree is meant for: -+ -+- Orange Pi One -+- Orange Pi PC -+- Orange Pi PC 2 -+- Orange Pi 3 -+- PinePhone 1.0, 1.1 and 1.2(a/b) -+- TBS A711 Tablet -+- PocketBook Touch Lux 3 -+- Pinebook Pro -+- Pinephone Pro -+ -+Features in addition to mainline: -+ -+- [Orange Pi One/PC/PC2] More aggressive OPPs for CPU -+- [All] Mark one of DRM planes as a cursor plane, speeding up Xorg based desktop with modesetting driver -+- [Orange Pi One/PC/PC2] Configure on-board micro-switches to perform system power off function -+- [Orange Pi One/PC/PC2/3] HDMI audio -+- [Orange Pi 3] Ethernet -+- [TBS A711] HM5065 (back camera) / GC2145 (front camera) -+- [PinePhone] WiFi, Bluetooth, Audio, Modem power, HDMI out over USB-C, USB-C support, cameras, PMIC improvements, power management, fixes here and there -+- [PocketBook Touch Lux 3] Display and Touchscreen support -+- [Pinephone Pro] Everything -+ -+Pre-built u-boot and kernels are available at https://xff.cz/kernels/ -+ -+You may need some firmware files for some part of the functionality. Those are -+available at: https://megous.com/git/linux-firmware -+ -+If you want to reproduce my pre-built kernels exactly, you'll need to uncomment -+CONFIG_EXTRA_FIRMWARE_DIR and CONFIG_EXTRA_FIRMWARE in the defconfigs, and -+point CONFIG_EXTRA_FIRMWARE_DIR to a directory on your computer where the -+clone of https://megous.com/git/linux-firmware resides. -+ -+You can also leave those two config options commented out, and copy the contents -+of https://megous.com/git/linux-firmware to /lib/firmware/ on the target device. -+ -+You can use this kernel to run a desktop environment on Orange Pi SBCs, -+Arch Linux on your Pinephone, or to have a completely opensource OS on -+a Pocketbook e-ink book reader. -+ -+Have fun! -+ -+ -+Build instructions -+------------------ -+ -+These are rudimentary instructions and you need to understand what you're doing. -+These are just core steps required to build the ATF/u-boot/kernel. Downloading, -+verifying, renaming to correct directories is not described or mentioned. You -+should be able to infer missing necessary steps yourself for your particular needs. -+ -+Get necessary toolchains from: -+ -+- https://releases.linaro.org/components/toolchain/binaries/latest/aarch64-linux-gnu/ for 64bit Orange Pi PC2 and Orange Pi 3, PinePhone -+- https://releases.linaro.org/components/toolchain/binaries/latest/arm-linux-gnueabihf/ for 32bit Orange Pis, Pocketbook, TBS tablet -+ -+Extract toolchains and prepare the environment: -+ -+ CWD=`pwd` -+ OUT=$CWD/builds -+ SRC=$CWD/u-boot -+ export PATH="$PATH:$CWD/Toolchains/arm/bin:$CWD/Toolchains/aarch64/bin" -+ -+For Orange Pi PC2, Orange Pi 3 or PinePhone: -+ -+ export CROSS_COMPILE=aarch64-linux-gnu- -+ export KBUILD_OUTPUT=$OUT/.tmp/uboot-pc2 -+ rm -rf "$KBUILD_OUTPUT" -+ mkdir -p $KBUILD_OUTPUT $OUT/pc2 -+ -+Get and build ATF from https://github.com/ARM-software/arm-trusted-firmware: -+ -+ make -C "$CWD/arm-trusted-firmware" PLAT=sun50i_a64 DEBUG=1 bl31 -+ cp "$CWD/arm-trusted-firmware/build/sun50i_a64/debug/bl31.bin" "$KBUILD_OUTPUT" -+ -+Use sun50i_a64 for Orange Pi PC2 or PinePhone and sun50i_h6 for Orange Pi 3. -+ -+Build u-boot from https://megous.com/git/u-boot/ (opi-v2020.04 branch) with appropriate -+defconfig (orangepi_one_defconfig, orangepi_pc2_defconfig, orangepi_pc_defconfig, orangepi_3_defconfig, tbs_a711_defconfig, pinephone_defconfig). -+ -+My u-boot branch already has all the necessary patches integrated and is configured for quick u-boot/kernel startup. -+ -+ make -C u-boot orangepi_pc2_defconfig -+ make -C u-boot -j5 -+ -+ cp $KBUILD_OUTPUT/.config $OUT/pc2/uboot.config -+ cat $KBUILD_OUTPUT/{spl/sunxi-spl.bin,u-boot.itb} > $OUT/pc2/uboot.bin -+ -+Get kernel from this repository and checkout the latest orange-pi-5.18 branch. -+ -+Build the kernel for 64-bit boards: -+ -+ export ARCH=arm64 -+ export CROSS_COMPILE=aarch64-linux-gnu- -+ export KBUILD_OUTPUT=$OUT/.tmp/linux-arm64 -+ mkdir -p $KBUILD_OUTPUT $OUT/pc2 -+ -+ make -C linux orangepi_defconfig -+ # or make -C linux pocketbook_touch_lux_3_defconfig -+ # or make -C linux tbs_a711_defconfig -+ make -C linux -j5 clean -+ make -C linux -j5 Image dtbs -+ -+ cp -f $KBUILD_OUTPUT/arch/arm64/boot/Image $OUT/pc2/ -+ cp -f $KBUILD_OUTPUT/.config $OUT/pc2/linux.config -+ cp -f $KBUILD_OUTPUT/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dtb $OUT/pc2/board.dtb -+ -+Build the kernel for 32-bit boards: -+ -+ export ARCH=arm -+ export CROSS_COMPILE=arm-linux-gnueabihf- -+ export KBUILD_OUTPUT=$OUT/.tmp/linux-arm -+ mkdir -p $KBUILD_OUTPUT $OUT/pc -+ -+ make orangepi_defconfig -+ # or make pinephone_defconfig -+ make -C linux orangepi_defconfig -+ make -C linux -j5 clean -+ make -C linux -j5 zImage dtbs -+ -+ cp -f $KBUILD_OUTPUT/arch/arm/boot/zImage $OUT/pc/ -+ cp -f $KBUILD_OUTPUT/.config $OUT/pc/linux.config -+ cp -f $KBUILD_OUTPUT/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb $OUT/pc/board.dtb -+ # Or use sun8i-h3-orangepi-one.dtb for Orange Pi One -+ -+ -+PinePhone -+--------- -+ -+I don't run u-boot on PinePhone, so my pre-built kernel packages don't come -+with u-boot built for PinePhone. -+ -+ -+Kernel lockup issues -+-------------------- -+ -+*If you're getting lockups on boot or later during thermal regulation, -+you're missing an u-boot patch.* -+ -+This patch is necessary to run this kernel! -+ -+These lockups are caused by improper NKMP clock factors selection -+in u-boot for PLL_CPUX. (M divider should not be used. P divider -+should be used only for frequencies below 240MHz.) -+ -+This patch for u-boot fixes it: -+ -+ 0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch -+ -+Kernel side is already fixed in this kernel tree. --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch b/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch deleted file mode 100644 index 686684e..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 90c0c047de85bdde3752b7556d4abf735df72242 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Fri, 22 Nov 2024 23:41:48 +0100 -Subject: arm64: dts: rk3399: Add dmc_opp_table - -This was removed in v6.12. Re-add it with original values. - -Signed-off-by: Ondrej Jirman ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 29 ++++++++++++++++++++++++ - 1 file changed, 29 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 6bc1249d99e6..bb9205bebf9f 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -104,6 +104,31 @@ opp05 { - opp-microvolt = <1100000 1100000 1150000>; - }; - }; -+ -+ dmc_opp_table: opp-table-3 { -+ compatible = "operating-points-v2"; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <328000000>; -+ opp-microvolt = <900000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <416000000>; -+ opp-microvolt = <900000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <666000000>; -+ opp-microvolt = <900000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <856000000>; -+ opp-microvolt = <900000>; -+ }; -+ opp04 { -+ opp-hz = /bits/ 64 <928000000>; -+ opp-microvolt = <925000>; -+ }; -+ }; - }; - - &cpu_l0 { -@@ -130,6 +155,10 @@ &cpu_b1 { - operating-points-v2 = <&cluster1_opp>; - }; - -+&dmc { -+ operating-points-v2 = <&dmc_opp_table>; -+}; -+ - &gpu { - operating-points-v2 = <&gpu_opp_table>; - }; --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch b/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch deleted file mode 100644 index 8bcf998..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch +++ /dev/null @@ -1,62 +0,0 @@ -From ea6833fd7294f14e4e84d6dde5fa11f82243f1a8 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Thu, 28 Nov 2024 11:16:31 +0100 -Subject: arm64: dts: rockchip: rk3399-s: Add DMC table - -This is used by Pinephone Pro. - -Signed-off-by: Ondrej Jirman ---- - arch/arm64/boot/dts/rockchip/rk3399-s.dtsi | 29 ++++++++++++++++++++++ - 1 file changed, 29 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-s.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-s.dtsi -index e54f451af9f3..82b941720294 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-s.dtsi -@@ -92,6 +92,31 @@ opp05 { - opp-microvolt = <1100000 1100000 1150000>; - }; - }; -+ -+ dmc_opp_table: opp-table-3 { -+ compatible = "operating-points-v2"; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <328000000>; -+ opp-microvolt = <900000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <416000000>; -+ opp-microvolt = <900000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <666000000>; -+ opp-microvolt = <900000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <856000000>; -+ opp-microvolt = <900000>; -+ }; -+ opp04 { -+ opp-hz = /bits/ 64 <928000000>; -+ opp-microvolt = <925000>; -+ }; -+ }; - }; - - &cpu_l0 { -@@ -118,6 +143,10 @@ &cpu_b1 { - operating-points-v2 = <&cluster1_opp>; - }; - -+&dmc { -+ operating-points-v2 = <&dmc_opp_table>; -+}; -+ - &gpu { - operating-points-v2 = <&gpu_opp_table>; - }; --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch b/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch deleted file mode 100644 index 4ba8d34..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch +++ /dev/null @@ -1,47 +0,0 @@ -From e35cba7b314073d85e8229ce603d291c0f720a68 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sat, 24 Sep 2022 21:59:07 +0200 -Subject: arm64: dts: rockchip: rk356x: Fix PCIe register map and ranges - -I have two Realtek PCIe wifi cards connected over the 4 port PCIe bridge -to Quartz64-A. The cards fail to work, when nvme SSD is connected at the -same time to the bridge. Without nvme connected, cards work fine. The -issue seems to be related to mixed use of devices which make use of I/O -ranges and memory ranges. - -This patch changes I/O, MEM and config mappings so that config and I/O -mappings use the 0xf4000000 outbound address space, and MEM range uses -the whole 0x300000000 outbound space. - -These values were suggested by pgwipeout: - - https://lore.kernel.org/lkml/875ygbsrf3.fsf@bloch.sibelius.xs4all.nl/T/#m84b5f6992cc26dffe0d3783c0d8c9c86e5e10c10 - -This is identical to how BSP does the mappings. - -This change to the regs/ranges makes the issue go away and both nvme and -wifi cards work when connected at the same time to the bridge. I tested -the nvme with large amount of reads/writes, both behind the PCIe bridge -and when directly connected to Quartz64-A board. - -Signed-off-by: Ondrej Jirman ---- - arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi -index 8421d4b8c771..3dd63161bbf1 100644 ---- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi -@@ -954,7 +954,7 @@ pcie2x1: pcie@fe260000 { - <0 0 0 4 &pcie_intc 3>; - linux,pci-domain = <0>; - num-ib-windows = <6>; -- num-ob-windows = <2>; -+ num-ob-windows = <8>; - max-link-speed = <2>; - msi-map = <0x0 &gic 0x0 0x1000>; - num-lanes = <1>; --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch b/patch/kernel/sunxi-6.14/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch deleted file mode 100644 index 8d819d9..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 38f3ba49d792cecd9b89602c16a74caa99d2eded Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sat, 24 Sep 2022 21:54:23 +0200 -Subject: drm: rockchip: Fix panic on reboot when DRM device fails to bind - -When DRM device is freed, we need to clear the drvdata pointer, because -it now points to invalid memory. - -Signed-off-by: Ondrej Jirman ---- - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index 439edc165ff6..44ba21037f50 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -206,6 +206,7 @@ static int rockchip_drm_bind(struct device *dev) - component_unbind_all(dev, drm_dev); - err_free: - drm_dev_put(drm_dev); -+ dev_set_drvdata(dev, NULL); - return ret; - } - -@@ -222,6 +223,7 @@ static void rockchip_drm_unbind(struct device *dev) - rockchip_iommu_cleanup(drm_dev); - - drm_dev_put(drm_dev); -+ dev_set_drvdata(dev, NULL); - } - - DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops); --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch b/patch/kernel/sunxi-6.14/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch deleted file mode 100644 index 36690c0..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 7b4684d211e12e8afabc94d545078e3ad070d1be Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sun, 9 Jun 2024 14:30:12 +0200 -Subject: drm: rockchip: dw-mipi-dsi-rockchip: Fix ISP1 PHY initialization - -After suspend/resume cycle, ISP1 would stop receiving data. -Re-initializing DPHY during PHY power on fixes the issue. - -Signed-off-by: Ondrej Jirman ---- - drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -index 3398160ad75e..471851879947 100644 ---- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -@@ -1245,6 +1245,14 @@ static int dw_mipi_dsi_dphy_power_on(struct phy *phy) - goto err_phy_cfg_clk; - } - -+ if (dsi->cdata->dphy_rx_init) { -+ ret = dsi->cdata->dphy_rx_init(phy); -+ if (ret < 0) { -+ DRM_DEV_ERROR(dsi->dev, "hardware-specific phy init failed: %d\n", ret); -+ goto err_pwr_on; -+ } -+ } -+ - /* do soc-variant specific init */ - if (dsi->cdata->dphy_rx_power_on) { - ret = dsi->cdata->dphy_rx_power_on(phy); --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-Implement-gamma-correction.patch b/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-Implement-gamma-correction.patch deleted file mode 100644 index 7dd2c26..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-Implement-gamma-correction.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 8521d1baa2940c22c9eede1517ee7ff85738f751 Mon Sep 17 00:00:00 2001 -From: Vasily Khoruzhick -Date: Wed, 13 Mar 2019 19:50:17 -0700 -Subject: drm/sun4i: Implement gamma correction - -Add support for gamma corretion to sun4i TCON driver. Its LUT has 256 -entries and can be updated only when gamma correction is disabled. - -Signed-off-by: Vasily Khoruzhick ---- - drivers/gpu/drm/sun4i/sun4i_crtc.c | 14 +++++++++++++ - drivers/gpu/drm/sun4i/sun4i_tcon.c | 33 ++++++++++++++++++++++++++++++ - drivers/gpu/drm/sun4i/sun4i_tcon.h | 12 ++++++++++- - 3 files changed, 58 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c -index 18e74047b0f5..a09944a49e89 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_crtc.c -+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c -@@ -103,6 +103,20 @@ static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc, - drm_crtc_send_vblank_event(crtc, event); - spin_unlock_irq(&crtc->dev->event_lock); - } -+ -+ if (crtc->state->color_mgmt_changed) { -+ if (crtc->state->gamma_lut) { -+ /* LUT can be only updated when gamma correction is -+ * disabled -+ */ -+ sun4i_tcon_enable_gamma(scrtc->tcon, false); -+ sun4i_tcon_load_gamma_lut(scrtc->tcon, -+ crtc->state->gamma_lut->data); -+ sun4i_tcon_enable_gamma(scrtc->tcon, true); -+ } else -+ sun4i_tcon_enable_gamma(scrtc->tcon, false); -+ } -+ - } - - static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc, -diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c -index fca95b76e258..ac6ad2ed1cc0 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c -@@ -240,6 +240,34 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) - } - EXPORT_SYMBOL(sun4i_tcon_enable_vblank); - -+void sun4i_tcon_load_gamma_lut(struct sun4i_tcon *tcon, -+ struct drm_color_lut *lut) -+{ -+ int i; -+ -+ for (i = 0; i < SUN4I_TCON_GAMMA_LUT_SIZE; i++) { -+ u32 r, g, b; -+ -+ r = drm_color_lut_extract(lut[i].red, 8); -+ g = drm_color_lut_extract(lut[i].green, 8); -+ b = drm_color_lut_extract(lut[i].blue, 8); -+ -+ regmap_write(tcon->regs, SUN4I_TCON_GAMMA_TABLE_REG + 4 * i, -+ SUN4I_TCON_GAMMA_TABLE_R(r) | -+ SUN4I_TCON_GAMMA_TABLE_G(g) | -+ SUN4I_TCON_GAMMA_TABLE_B(b)); -+ } -+} -+EXPORT_SYMBOL(sun4i_tcon_load_gamma_lut); -+ -+void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable) -+{ -+ regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, -+ SUN4I_TCON_GCTL_GAMMA_ENABLE, -+ enable ? SUN4I_TCON_GCTL_GAMMA_ENABLE : 0); -+} -+EXPORT_SYMBOL(sun4i_tcon_enable_gamma); -+ - /* - * This function is a helper for TCON output muxing. The TCON output - * muxing control register in earlier SoCs (without the TCON TOP block) -@@ -1288,6 +1316,11 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master, - - list_add_tail(&tcon->list, &drv->tcon_list); - -+ drm_mode_crtc_set_gamma_size(&tcon->crtc->crtc, -+ SUN4I_TCON_GAMMA_LUT_SIZE); -+ drm_crtc_enable_color_mgmt(&tcon->crtc->crtc, 0, false, -+ tcon->crtc->crtc.gamma_size); -+ - return 0; - - err_free_dclk: -diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h -index fa23aa23fe4a..97df39db2a31 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.h -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h -@@ -19,6 +19,7 @@ - - #define SUN4I_TCON_GCTL_REG 0x0 - #define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31) -+#define SUN4I_TCON_GCTL_GAMMA_ENABLE BIT(30) - #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0) - #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0) - #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0) -@@ -229,7 +230,13 @@ - #define SUN4I_TCON1_FILL_BEG2_REG 0x31c - #define SUN4I_TCON1_FILL_END2_REG 0x320 - #define SUN4I_TCON1_FILL_DATA2_REG 0x324 --#define SUN4I_TCON1_GAMMA_TABLE_REG 0x400 -+ -+#define SUN4I_TCON_GAMMA_TABLE_REG 0x400 -+#define SUN4I_TCON_GAMMA_TABLE_B(x) ((x) & 0xff) -+#define SUN4I_TCON_GAMMA_TABLE_G(x) (((x) & 0xff) << 8) -+#define SUN4I_TCON_GAMMA_TABLE_R(x) (((x) & 0xff) << 16) -+ -+#define SUN4I_TCON_GAMMA_LUT_SIZE 256 - - #define SUN4I_TCON_MAX_CHANNELS 2 - -@@ -297,6 +304,9 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, - const struct drm_display_mode *mode); - void sun4i_tcon_set_status(struct sun4i_tcon *crtc, - const struct drm_encoder *encoder, bool enable); -+void sun4i_tcon_load_gamma_lut(struct sun4i_tcon *tcon, -+ struct drm_color_lut *lut); -+void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable); - - extern const struct of_device_id sun4i_tcon_of_table[]; - --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch b/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch deleted file mode 100644 index e62940f..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 44014e4f2d9fa752d0b04d8322582aad7dcbf249 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Mon, 31 Oct 2022 03:23:11 +0100 -Subject: drm/sun4i: Mark one of the UI planes as a cursor one - -Signed-off-by: Ondrej Jirman ---- - drivers/gpu/drm/sun4i/sun8i_mixer.c | 7 ++++++- - drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 7 ++----- - drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 4 +++- - 3 files changed, 11 insertions(+), 7 deletions(-) - -diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index 8b41d33baa30..03dd180a4c31 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_mixer.c -+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c -@@ -349,8 +349,13 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm, - - for (i = 0; i < mixer->cfg->ui_num; i++) { - struct sun8i_layer *layer; -+ enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY; -+ if (i == 0) -+ type = DRM_PLANE_TYPE_PRIMARY; -+ else if (i == (mixer->cfg->ui_num - 1)) -+ type = DRM_PLANE_TYPE_CURSOR; - -- layer = sun8i_ui_layer_init_one(drm, mixer, i); -+ layer = sun8i_ui_layer_init_one(drm, mixer, i, type); - if (IS_ERR(layer)) { - dev_err(drm->dev, "Couldn't initialize %s plane\n", - i ? "overlay" : "primary"); -diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c -index b90e5edef4e8..0349e8bdffd6 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c -+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c -@@ -277,9 +277,9 @@ static const uint64_t sun8i_layer_modifiers[] = { - - struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, - struct sun8i_mixer *mixer, -- int index) -+ int index, -+ enum drm_plane_type type) - { -- enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY; - int channel = mixer->cfg->vi_num + index; - struct sun8i_layer *layer; - unsigned int plane_cnt; -@@ -289,9 +289,6 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, - if (!layer) - return ERR_PTR(-ENOMEM); - -- if (index == 0) -- type = DRM_PLANE_TYPE_PRIMARY; -- - /* possible crtcs are set later */ - ret = drm_universal_plane_init(drm, &layer->plane, 0, - &sun8i_ui_layer_funcs, -diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h -index 83892f6ff211..d4530e9f64e0 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h -+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h -@@ -51,5 +51,7 @@ struct sun8i_layer; - - struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, - struct sun8i_mixer *mixer, -- int index); -+ int index, -+ enum drm_plane_type type); -+ - #endif /* _SUN8I_UI_LAYER_H_ */ --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch b/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch deleted file mode 100644 index 54b9a2f..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch +++ /dev/null @@ -1,547 +0,0 @@ -From 0fcf6084c0e1482b81d3ee60db39b478fcd48798 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sun, 30 Apr 2023 18:19:16 +0200 -Subject: drm/sun4i: Support taking over display pipeline state from p-boot - -For perfect, flickerless and fast boot. - -Signed-off-by: Ondrej Jirman ---- - drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 4 +- - drivers/gpu/drm/drm_fbdev_ttm.c | 14 +++++ - drivers/gpu/drm/panel/panel-sitronix-st7703.c | 17 ++++++ - drivers/gpu/drm/sun4i/sun4i_tcon.c | 23 ++++++++ - drivers/gpu/drm/sun4i/sun4i_tcon.h | 2 + - drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 13 +++++ - drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 2 + - drivers/gpu/drm/sun4i/sun8i_mixer.c | 52 +++++++++++++++++++ - drivers/gpu/drm/sun4i/sun8i_mixer.h | 3 ++ - drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 14 +++++ - drivers/video/backlight/pwm_bl.c | 25 ++++++++- - 11 files changed, 167 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c -index 4b3068bdfdf2..c8cdb342b1a0 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c -@@ -980,7 +980,9 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) - /* Decrease the PLL AUDIO bias current to reduce noise. */ - writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG); - -- writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); -+ ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val); -+ if (ret) -+ writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); - - ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc); - if (ret) -diff --git a/drivers/gpu/drm/drm_fbdev_ttm.c b/drivers/gpu/drm/drm_fbdev_ttm.c -index 73d35d59590c..f9d71d285e2f 100644 ---- a/drivers/gpu/drm/drm_fbdev_ttm.c -+++ b/drivers/gpu/drm/drm_fbdev_ttm.c -@@ -179,6 +179,7 @@ int drm_fbdev_ttm_driver_fbdev_probe(struct drm_fb_helper *fb_helper, - struct fb_info *info; - size_t screen_size; - void *screen_buffer; -+ u32 fb_start; - u32 format; - int ret; - -@@ -228,6 +229,19 @@ int drm_fbdev_ttm_driver_fbdev_probe(struct drm_fb_helper *fb_helper, - if (ret) - goto err_drm_fb_helper_release_info; - -+ ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start); -+ if (ret == 0) { -+ // copy framebuffer contents from p-boot if reasonable -+ if (screen_size != 720 * 1440 * 4) { -+ drm_err(dev, "surface width(%d), height(%d) and bpp(%d) does not match p-boot requirements\n", -+ sizes->surface_width, sizes->surface_height, -+ sizes->surface_bpp); -+ return 0; -+ } -+ -+ memcpy(screen_buffer, __va(fb_start), screen_size); -+ } -+ - return 0; - - err_drm_fb_helper_release_info: -diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c -index 6d3ad83be141..8e359c9e0a09 100644 ---- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c -+++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c -@@ -62,6 +62,7 @@ struct st7703 { - struct dentry *debugfs; - const struct st7703_panel_desc *desc; - enum drm_panel_orientation orientation; -+ bool hw_preenabled; - }; - - struct st7703_panel_desc { -@@ -679,6 +680,11 @@ static int st7703_enable(struct drm_panel *panel) - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; - -+ if (ctx->hw_preenabled) { -+ ctx->hw_preenabled = false; -+ return 0; -+ } -+ - ctx->desc->init_sequence(&dsi_ctx); - - mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); -@@ -726,8 +732,10 @@ static int st7703_prepare(struct drm_panel *panel) - struct st7703 *ctx = panel_to_st7703(panel); - int ret; - -+ if (!ctx->hw_preenabled) { - dev_dbg(ctx->dev, "Resetting the panel\n"); - gpiod_set_value_cansleep(ctx->reset_gpio, 1); -+ } - - ret = regulator_enable(ctx->iovcc); - if (ret < 0) { -@@ -743,10 +751,12 @@ static int st7703_prepare(struct drm_panel *panel) - } - - /* Give power supplies time to stabilize before deasserting reset. */ -+ if (!ctx->hw_preenabled) { - usleep_range(10000, 20000); - - gpiod_set_value_cansleep(ctx->reset_gpio, 0); - usleep_range(15000, 20000); -+ } - - return 0; - } -@@ -844,12 +854,19 @@ static int st7703_probe(struct mipi_dsi_device *dsi) - { - struct device *dev = &dsi->dev; - struct st7703 *ctx; -+ u32 fb_start; - int ret; - - ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return -ENOMEM; - -+ ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start); -+ if (ret == 0) { -+ /* the display pipeline is already initialized by p-boot */ -+ ctx->hw_preenabled = true; -+ } -+ - ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); - if (IS_ERR(ctx->reset_gpio)) - return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "Failed to get reset gpio\n"); -diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c -index ac6ad2ed1cc0..b36c1ea0948c 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c -@@ -40,6 +40,8 @@ - #include "sun8i_tcon_top.h" - #include "sunxi_engine.h" - -+static bool hw_preconfigured; -+ - static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder) - { - struct drm_connector *connector; -@@ -743,6 +745,13 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, - const struct drm_encoder *encoder, - const struct drm_display_mode *mode) - { -+ if (tcon->hw_preconfigured) { -+ // avoid the first modeset -+ tcon->hw_preconfigured = false; -+ hw_preconfigured = false; -+ return; -+ } -+ - switch (encoder->encoder_type) { - case DRM_MODE_ENCODER_DSI: - /* DSI is tied to special case of CPU interface */ -@@ -883,6 +892,7 @@ static int sun4i_tcon_init_regmap(struct device *dev, - return PTR_ERR(tcon->regs); - } - -+ if (!tcon->hw_preconfigured) { - /* Make sure the TCON is disabled and all IRQs are off */ - regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); - regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); -@@ -891,6 +901,7 @@ static int sun4i_tcon_init_regmap(struct device *dev, - /* Disable IO lines and set them to tristate */ - regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); - regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); -+ } - - return 0; - } -@@ -1162,6 +1173,9 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master, - tcon->dev = dev; - tcon->id = engine->id; - tcon->quirks = of_device_get_match_data(dev); -+ -+ if (tcon->id == 0) -+ tcon->hw_preconfigured = hw_preconfigured; - - tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); - if (IS_ERR(tcon->lcd_rst)) { -@@ -1183,12 +1197,14 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master, - } - } - -+ if (!tcon->hw_preconfigured) { - /* Make sure our TCON is reset */ - ret = reset_control_reset(tcon->lcd_rst); - if (ret) { - dev_err(dev, "Couldn't deassert our reset line\n"); - return ret; - } -+ } - - if (tcon->quirks->supports_lvds) { - /* -@@ -1352,8 +1368,15 @@ static int sun4i_tcon_probe(struct platform_device *pdev) - const struct sun4i_tcon_quirks *quirks; - struct drm_bridge *bridge; - struct drm_panel *panel; -+ u32 fb_start; - int ret; - -+ ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start); -+ if (ret == 0) { -+ /* the display pipeline is already initialized by p-boot */ -+ hw_preconfigured = true; -+ } -+ - quirks = of_device_get_match_data(&pdev->dev); - - /* panels and bridges are present only on TCONs with channel 0 */ -diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h -index 97df39db2a31..864d70b9d242 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.h -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h -@@ -293,6 +293,8 @@ struct sun4i_tcon { - - /* TCON list management */ - struct list_head list; -+ -+ bool hw_preconfigured; - }; - - struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node); -diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c -index c35b70d83e53..3644db360a30 100644 ---- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c -+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c -@@ -732,6 +732,7 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder) - reset_control_deassert(dsi->reset); - clk_prepare_enable(dsi->mod_clk); - -+ if (!dsi->hw_preconfigured) { - /* - * Enable the DSI block. - */ -@@ -758,6 +759,7 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder) - sun6i_dsi_setup_inst_loop(dsi, mode); - sun6i_dsi_setup_format(dsi, mode); - sun6i_dsi_setup_timings(dsi, mode); -+ } - - phy_init(dsi->dphy); - -@@ -787,11 +789,15 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder) - if (dsi->panel) - drm_panel_enable(dsi->panel); - -+ if (!dsi->hw_preconfigured) { - sun6i_dsi_start(dsi, DSI_START_HSC); - - udelay(1000); - - sun6i_dsi_start(dsi, DSI_START_HSD); -+ } -+ -+ dsi->hw_preconfigured = false; - } - - static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder) -@@ -1105,6 +1111,7 @@ static int sun6i_dsi_probe(struct platform_device *pdev) - struct device *dev = &pdev->dev; - struct sun6i_dsi *dsi; - void __iomem *base; -+ u32 fb_start; - int ret; - - variant = device_get_match_data(dev); -@@ -1120,6 +1127,12 @@ static int sun6i_dsi_probe(struct platform_device *pdev) - dsi->host.dev = dev; - dsi->variant = variant; - -+ ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start); -+ if (ret == 0) { -+ /* the display pipeline is already initialized by p-boot */ -+ dsi->hw_preconfigured = true; -+ } -+ - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - dev_err(dev, "Couldn't map the DSI encoder registers\n"); -diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h -index f1ddefe0f554..958c2997ab43 100644 ---- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h -+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h -@@ -38,6 +38,8 @@ struct sun6i_dsi { - struct drm_panel *panel; - - const struct sun6i_dsi_variant *variant; -+ -+ bool hw_preconfigured; - }; - - static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host) -diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index 03dd180a4c31..913490acee53 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_mixer.c -+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c -@@ -24,6 +24,7 @@ - #include - - #include "sun4i_drv.h" -+#include "sun4i_tcon.h" - #include "sun8i_mixer.h" - #include "sun8i_ui_layer.h" - #include "sun8i_vi_layer.h" -@@ -34,6 +35,8 @@ struct de2_fmt_info { - u32 de2_fmt; - }; - -+static bool hw_preconfigured; -+ - static const struct de2_fmt_info de2_formats[] = { - { - .drm_fmt = DRM_FORMAT_ARGB8888, -@@ -278,6 +281,33 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, - struct drm_plane *plane; - u32 route = 0, pipe_en = 0; - -+ if (mixer->hw_preconfigured && engine->id == 0) { -+ struct sun4i_tcon* tcon; -+ u32 val, saved, ret; -+ -+ /* -+ * This is the first commit, wait for vblank on tcon0 before continuing. -+ */ -+ list_for_each_entry(tcon, &mixer->drv->tcon_list, list) { -+ if (tcon->id == 0) { -+ regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &saved); -+ saved &= 0xffff0000; -+ -+ regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); -+ -+ ret = regmap_read_poll_timeout(tcon->regs, SUN4I_TCON_GINT0_REG, val, -+ val & (SUN4I_TCON_GINT0_VBLANK_INT(0) | -+ SUN4I_TCON_GINT0_VBLANK_INT(1) | -+ SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT), -+ 100, 40000); -+ -+ regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, saved); -+ } -+ } -+ -+ mixer->hw_preconfigured = false; -+ } -+ - DRM_DEBUG_DRIVER("Committing changes\n"); - - drm_for_each_plane(plane, state->dev) { -@@ -461,6 +491,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, - dev_set_drvdata(dev, mixer); - mixer->engine.ops = &sun8i_engine_ops; - mixer->engine.node = dev->of_node; -+ mixer->drv = drv; - - if (of_property_present(dev->of_node, "iommus")) { - /* -@@ -485,6 +516,11 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, - */ - mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node); - -+ if (mixer->engine.id == 0) { -+ mixer->hw_preconfigured = hw_preconfigured; -+ hw_preconfigured = false; -+ } -+ - mixer->cfg = of_device_get_match_data(dev); - if (!mixer->cfg) - return -EINVAL; -@@ -532,8 +568,11 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, - * reason for the mixer to be functional. Make sure it's the - * case. - */ -+ -+ if (!mixer->hw_preconfigured) { - if (mixer->cfg->mod_rate) - clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate); -+ } - - clk_prepare_enable(mixer->mod_clk); - -@@ -541,6 +580,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, - - base = sun8i_blender_base(mixer); - -+ if (!mixer->hw_preconfigured) { - /* Reset registers and disable unused sub-engines */ - if (mixer->cfg->is_de3) { - for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4) -@@ -572,6 +612,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, - /* Enable the mixer */ - regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL, - SUN8I_MIXER_GLOBAL_CTL_RT_EN); -+ } /* hw_preconfigured */ - - /* Set background color to black */ - regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), -@@ -592,8 +633,10 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, - SUN8I_MIXER_BLEND_MODE(base, i), - SUN8I_MIXER_BLEND_MODE_DEF); - -+ if (!mixer->hw_preconfigured) { - regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), - SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); -+ } - - return 0; - -@@ -623,6 +666,15 @@ static const struct component_ops sun8i_mixer_ops = { - - static int sun8i_mixer_probe(struct platform_device *pdev) - { -+ int ret; -+ u32 fb_start; -+ -+ ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start); -+ if (ret == 0) { -+ /* the display pipeline is already initialized by p-boot */ -+ hw_preconfigured = true; -+ } -+ - return component_add(&pdev->dev, &sun8i_mixer_ops); - } - -diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h -index d7898c9c9cc0..68e2741b0962 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_mixer.h -+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h -@@ -184,6 +184,9 @@ struct sun8i_mixer { - - struct clk *bus_clk; - struct clk *mod_clk; -+ -+ struct sun4i_drv *drv; -+ bool hw_preconfigured; - }; - - enum { -diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c -index 36eab95271b2..a19a27cea860 100644 ---- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c -+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c -@@ -195,6 +195,8 @@ struct sun6i_dphy { - - const struct sun6i_dphy_variant *variant; - enum sun6i_dphy_direction direction; -+ -+ bool hw_preconfigured; - }; - - static int sun6i_dphy_init(struct phy *phy) -@@ -226,6 +228,11 @@ static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy) - { - u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); - -+ if (dphy->hw_preconfigured) { -+ dphy->hw_preconfigured = false; -+ return; -+ } -+ - regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, - SUN6I_DPHY_ANA0_REG_PWS | - SUN6I_DPHY_ANA0_REG_DMPC | -@@ -551,6 +558,7 @@ static int sun6i_dphy_probe(struct platform_device *pdev) - struct sun6i_dphy *dphy; - const char *direction; - void __iomem *regs; -+ u32 fb_start; - int ret; - - dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); -@@ -561,6 +569,12 @@ static int sun6i_dphy_probe(struct platform_device *pdev) - if (!dphy->variant) - return -EINVAL; - -+ ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start); -+ if (ret == 0) { -+ /* the display pipeline is already initialized by p-boot */ -+ dphy->hw_preconfigured = true; -+ } -+ - regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(regs)) { - dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n"); -diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c -index 237d3d3f3bb1..f7d9d8813d92 100644 ---- a/drivers/video/backlight/pwm_bl.c -+++ b/drivers/video/backlight/pwm_bl.c -@@ -444,7 +444,7 @@ static int pwm_backlight_probe(struct platform_device *pdev) - struct backlight_properties props; - struct backlight_device *bl; - struct pwm_bl_data *pb; -- struct pwm_state state; -+ struct pwm_state state, state_real; - unsigned int i; - int ret; - -@@ -509,6 +509,11 @@ static int pwm_backlight_probe(struct platform_device *pdev) - /* Sync up PWM state. */ - pwm_init_state(pb->pwm, &state); - -+ /* Read real state, but only if the PWM is enabled. */ -+ pwm_get_state(pb->pwm, &state_real); -+ if (state_real.enabled) -+ state = state_real; -+ - /* - * The DT case will set the pwm_period_ns field to 0 and store the - * period, parsed from the DT, in the PWM device. For the non-DT case, -@@ -601,6 +606,24 @@ static int pwm_backlight_probe(struct platform_device *pdev) - - bl->props.brightness = data->dft_brightness; - bl->props.power = pwm_backlight_initial_power_state(pb); -+ if (bl->props.power == FB_BLANK_UNBLANK && pb->levels) { -+ u64 level; -+ -+ /* If the backlight is already on, determine the default -+ * brightness from PWM duty cycle instead of forcing -+ * the brightness determined by the driver -+ */ -+ pwm_get_state(pb->pwm, &state); -+ level = (u64)state.duty_cycle * pb->scale; -+ do_div(level, (u64)state.period); -+ -+ for (i = 0; i <= data->max_brightness; i++) { -+ if (data->levels[i] > level) { -+ bl->props.brightness = i; -+ break; -+ } -+ } -+ } - backlight_update_status(bl); - - platform_set_drvdata(pdev, bl); --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch b/patch/kernel/sunxi-6.14/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch deleted file mode 100644 index 01b6d07..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch +++ /dev/null @@ -1,52 +0,0 @@ -From a276625b2b8b781c6e50fb66ddc747a8c761c076 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sat, 22 Jan 2022 20:35:39 +0000 -Subject: mmc: dw-mmc-rockchip: fix sdmmc after soft reboot - -During shutdown the dw-mmc driver shuts down the vqmmc regulator. -This leads to situations where the sdmmc is unavailable after a soft -reboot. -Fix this by ensuring the vqmmc regulator is powered up on kernel -shutdown. - -Signed-off-by: Peter Geis ---- - drivers/mmc/host/dw_mmc-rockchip.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c -index baa23b517731..42edf219623b 100644 ---- a/drivers/mmc/host/dw_mmc-rockchip.c -+++ b/drivers/mmc/host/dw_mmc-rockchip.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - - #include "dw_mmc.h" -@@ -575,9 +576,20 @@ static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = { - NULL) - }; - -+static void dw_mci_rockchip_shutdown(struct platform_device *pdev) -+{ -+ struct dw_mci *host = dev_get_drvdata(&pdev->dev); -+ struct mmc_host *mmc = host->slot->mmc; -+ -+ if (!IS_ERR(mmc->supply.vqmmc) && !(host->vqmmc_enabled)) -+ if(!regulator_enable(mmc->supply.vqmmc)) -+ host->vqmmc_enabled = true; -+} -+ - static struct platform_driver dw_mci_rockchip_pltfm_driver = { - .probe = dw_mci_rockchip_probe, - .remove = dw_mci_rockchip_remove, -+ .shutdown = dw_mci_rockchip_shutdown, - .driver = { - .name = "dwmmc_rockchip", - .probe_type = PROBE_PREFER_ASYNCHRONOUS, --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch b/patch/kernel/sunxi-6.14/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch deleted file mode 100644 index 2fb7a14..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch +++ /dev/null @@ -1,32 +0,0 @@ -From a624070758979300cfc1b684162a2fb881773cae Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Wed, 14 Jun 2023 00:48:21 +0200 -Subject: pci: Workaround ITS timeouts on poweroff/reboot on Orange Pi 5 Plus - -Call to pci_free_irq_vectors on PCIE2x ports causes ITS timeout messages -and delayed shutdown/reboot (by up to a minute). - -The root cause will be elsewhere. This is not for upstream. Anyway, -there should be no harm from this, since we're shutting down anyway. - -Signed-off-by: Ondrej Jirman ---- - drivers/pci/pcie/portdrv.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c -index e8318fd5f6ed..22d65c83396e 100644 ---- a/drivers/pci/pcie/portdrv.c -+++ b/drivers/pci/pcie/portdrv.c -@@ -743,7 +743,7 @@ static void pcie_portdrv_shutdown(struct pci_dev *dev) - pm_runtime_dont_use_autosuspend(&dev->dev); - } - -- pcie_port_device_remove(dev); -+ device_for_each_child(&dev->dev, NULL, remove_iter); - } - - static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev, --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch b/patch/kernel/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch deleted file mode 100644 index ee6d63e..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 2e0399dce5fedc6750458a4284bfb78db5d3f403 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Fri, 5 Jul 2024 23:25:25 +0200 -Subject: usb: typec: anx7688: Port to Linux 6.10 - -devm_* variant of device_add_groups was dropped. - -Signed-off-by: Ondrej Jirman ---- - drivers/usb/typec/anx7688.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c -index 77c154565340..448a6f48ab36 100644 ---- a/drivers/usb/typec/anx7688.c -+++ b/drivers/usb/typec/anx7688.c -@@ -1975,7 +1975,7 @@ static int anx7688_i2c_probe(struct i2c_client *client) - return irq_cabledet; - } - -- ret = devm_device_add_groups(&client->dev, anx7688_groups); -+ ret = device_add_groups(&client->dev, anx7688_groups); - if (ret) - return ret; - --- -2.35.3 - diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch b/patch/kernel/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch deleted file mode 100644 index 7785d8c..0000000 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 4e782d0f529ea1f1ae6a5c01f21cacc3903395c6 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Fri, 15 Mar 2024 23:05:10 +0100 -Subject: usb: typec: anx7688: Port to Linux 6.9 - -POWER_SUPPLY_PROP_USB_BC_ENABLED is no longer needed, nor supported -by axp20x driver. - -Signed-off-by: Ondrej Jirman ---- - drivers/usb/typec/anx7688.c | 51 ++++--------------------------------- - 1 file changed, 5 insertions(+), 46 deletions(-) - -diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c -index fa1d3496af73..77c154565340 100644 ---- a/drivers/usb/typec/anx7688.c -+++ b/drivers/usb/typec/anx7688.c -@@ -636,14 +636,6 @@ static void anx7688_disconnect(struct anx7688 *anx7688) - if (ret) - dev_err(dev, "failed to offline vbus_in\n"); - -- val.intval = 1; -- dev_dbg(dev, "enabling USB BC 1.2 detection\n"); -- ret = power_supply_set_property(anx7688->vbus_in_supply, -- POWER_SUPPLY_PROP_USB_BC_ENABLED, -- &val); -- if (ret) -- dev_err(dev, "failed to enabled USB BC1.2 detection\n"); -- - clear_bit(ANX7688_F_CONNECTED, anx7688->flags); - } - -@@ -1822,17 +1814,8 @@ static void anx7688_handle_current_update(struct anx7688* anx7688) - - if (current_limit) { - /* -- * Disable BC1.2 detection, because we'll be setting -- * a current limit determined by USB-PD -+ * Set a current limit determined by USB-PD - */ -- val.intval = 0; -- dev_dbg(dev, "disabling USB BC 1.2 detection\n"); -- ret = power_supply_set_property(anx7688->vbus_in_supply, -- POWER_SUPPLY_PROP_USB_BC_ENABLED, -- &val); -- if (ret) -- dev_err(dev, "failed to disable USB BC1.2 detection\n"); -- - val.intval = current_limit * 1000; - dev_dbg(dev, "setting vbus_in current limit to %d mA\n", current_limit); - ret = power_supply_set_property(anx7688->vbus_in_supply, -@@ -1846,27 +1829,13 @@ static void anx7688_handle_current_update(struct anx7688* anx7688) - * Use the result of BC1.2 detection performed by PMIC. - */ - ret = power_supply_get_property(anx7688->vbus_in_supply, -- POWER_SUPPLY_PROP_USB_BC_ENABLED, -+ POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, - &val); - if (ret) -- dev_err(dev, "failed to get USB BC1.2 detection status\n"); -- -- if (ret != 0 || val.intval == 0) { -- /* -- * If BC is disabled or we can't get its status, -- * set conservative 500mA limit. Otherwise leave -- * the limit to BC1.2. -- */ -- val.intval = 500 * 1000; -- dev_dbg(dev, "setting vbus_in current limit to %d mA\n", -+ dev_err(dev, "failed to get vbus_in current limit\n"); -+ if (ret == 0) -+ dev_dbg(dev, "vbus_in current limit is %d mA\n", - val.intval / 1000); -- ret = power_supply_set_property(anx7688->vbus_in_supply, -- POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, -- &val); -- if (ret) -- dev_err(dev, "failed to set vbus_in current to %d mA\n", -- val.intval / 1000); -- } - } - - /* Turn on VBUS power path inside PMIC. */ -@@ -1932,7 +1901,6 @@ static int anx7688_i2c_probe(struct i2c_client *client) - struct anx7688 *anx7688; - struct device *dev = &client->dev; - struct typec_capability typec_cap = { }; -- union power_supply_propval psy_val; - int i, vid_h, vid_l; - int irq_cabledet; - int ret = 0; -@@ -2087,15 +2055,6 @@ static int anx7688_i2c_probe(struct i2c_client *client) - - // make sure BC1.2 detection in PMIC is enabled - anx7688->last_bc_result = -1; -- psy_val.intval = 1; -- dev_dbg(dev, "enabling USB BC 1.2 detection\n"); -- ret = power_supply_set_property(anx7688->vbus_in_supply, -- POWER_SUPPLY_PROP_USB_BC_ENABLED, -- &psy_val); -- if (ret) { -- dev_err(anx7688->dev, "failed to enable BC1.2 detection\n"); -- goto err_cport; -- } - - ret = devm_request_irq(dev, irq_cabledet, anx7688_irq_plug_handler, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, --- -2.35.3 - diff --git a/patch/kernel/rockchip64-6.14/0000.patching_config.yaml b/patch/kernel/sunxi-6.16/0000.patching_config.yaml similarity index 60% rename from patch/kernel/rockchip64-6.14/0000.patching_config.yaml rename to patch/kernel/sunxi-6.16/0000.patching_config.yaml index d3eb1eb..38333df 100644 --- a/patch/kernel/rockchip64-6.14/0000.patching_config.yaml +++ b/patch/kernel/sunxi-6.16/0000.patching_config.yaml @@ -1,37 +1,38 @@ -config: # This is file 'patch/kernel/archive/rockchip64-6.13/0000.patching_config.yaml' +config: # Just some info stuff; not used by the patching scripts - name: rockchip64-6.14 + name: sunxi-6.15 kind: kernel - type: mainline # or: vendor - branch: linux-6.14.y - last-known-good-tag: v6.14-rc2 + type: mainline # or: mainline + branch: linux-6.15.y + last-known-good-tag: v6.7.0 maintainers: - - { github: rpardini, name: Ricardo Pardini, email: ricardo@pardini.net, armbian-forum: rpardini } - - { github: paolosabatino, name: Paolo Sabatino, email: paolo.sabatino@gmail.com, armbian-forum: jock } + - { github: pyavitz, name: Patrick Yavitz, email: pyavitz@gmail.com, armbian-forum: c0rnelius } # .dts files in these directories will be copied as-is to the build tree; later ones overwrite earlier ones. # This is meant to provide a way to "add a board DTS" without having to null-patch them in. dts-directories: - - { source: "dt", target: "arch/arm64/boot/dts/rockchip" } + # will copy patch/kernel/archive/meson64-MAJOR.MINOR/dt-boards/*.dts to arch/arm64/boot/dts/allwinner + - { source: "dt", target: "arch/arm64/boot/dts/allwinner" } # every file in these directories will be copied as-is to the build tree; later ones overwrite earlier ones # This is meant as a way to have overlays, bare, in a directory, without having to null-patch them in. # @TODO need a solution to auto-Makefile the overlays as well - overlay-directories: - - { source: "overlay", target: "arch/arm64/boot/dts/rockchip/overlay" } +# overlay-directories: + # will copy patch/kernel/archive/meson64-MAJOR.MINOR/overlay/**/* to arch/arm64/boot/dts/allwinner/overlay +# - { source: "overlay", target: "arch/arm64/boot/dts/allwinner/overlay" } # the Makefile in each of these directories will be magically patched to include the dts files copied # or patched-in; overlay subdir will be included "-y" if it exists. # No more Makefile patching needed, yay! auto-patch-dt-makefile: - - { directory: "arch/arm64/boot/dts/rockchip", config-var: "CONFIG_ARCH_ROCKCHIP" } + - { directory: "arch/arm64/boot/dts/allwinner", config-var: "CONFIG_ARCH_SUNXI" } # configuration for when applying patches to git / auto-rewriting patches (development cycle helpers) patches-to-git: do-not-commit-files: - "MAINTAINERS" # constant churn, drop them. sorry. - - "Documentation/devicetree/bindings/arm/rockchip.yaml" # constant churn, conflicts on every bump, drop it. sorry. + - "Documentation/devicetree/bindings/arm/allwinner.yaml" # constant churn, conflicts on every bump, drop it. sorry. do-not-commit-regexes: # Python-style regexes - "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9]+)/Makefile$" # ignore DT Makefile patches, we've an auto-patcher now diff --git a/patch/kernel/sunxi-6.16/dt/sun50i-h618-bananapi-m4-zero.dts b/patch/kernel/sunxi-6.16/dt/sun50i-h618-bananapi-m4-zero.dts new file mode 100644 index 0000000..933c133 --- /dev/null +++ b/patch/kernel/sunxi-6.16/dt/sun50i-h618-bananapi-m4-zero.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Patrick Yavitz + */ + +/dts-v1/; + +#include "sun50i-h618-bananapi-m4.dtsi" + +/ { + model = "BananaPi BPI-M4-Zero"; + compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h618"; + + aliases { + ethernet0 = &emac1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c3 = &i2c3; + i2c4 = &i2c4; + serial4 = &uart4; + serial5 = &uart5; + spi1 = &spi1; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* Connected to an on-board RTL8821CU USB WiFi chip. */ +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&emac1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + phy-mode = "rmii"; + phy-handle = <&rmii_phy>; + phy-supply = <®_dldo1>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; +}; + +&mdio1 { + rmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +/* SDIO */ +&mmc1 { + status = "disabled"; + bus-width = <4>; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + /* WiFi firmware requires power to be kept while in suspend */ + keep-power-in-suspend; + + mmc-pwrseq = <&wifi_pwrseq>; + + cd-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */ + vmmc-supply = <®_vcc3v3>; + + sdio: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&usbotg { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usbphy { + status = "okay"; + usb1_vbus-supply = <®_usb_vbus>; +}; diff --git a/patch/kernel/sunxi-6.16/dt/sun50i-h618-bananapi-m4.dtsi b/patch/kernel/sunxi-6.16/dt/sun50i-h618-bananapi-m4.dtsi new file mode 100644 index 0000000..4b34a89 --- /dev/null +++ b/patch/kernel/sunxi-6.16/dt/sun50i-h618-bananapi-m4.dtsi @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Patrick Yavitz + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" + +#include +#include +#include +#include + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + kaslr-seed = <0xfeedbeef 0xc0def00d>; + }; + + connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_usb_vbus: regulator-usb-vbus { + /* Separate discrete regulator for the USB ports */ + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "usb-vbus"; + vin-supply = <®_vcc5v>; + }; + + reg_vcc5v: regulator-vcc5v { + /* Board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc-5v"; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; + vin-supply = <®_vcc5v>; + }; + + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; + vin-supply = <®_vcc3v3>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; +}; + +&ahub_dam_plat { + status = "okay"; +}; + +&ahub1_plat { + status = "okay"; +}; + +&ahub1_mach { + status = "okay"; +}; + +&codec { + status = "disabled"; + allwinner,audio-routing = "Line Out", "LINEOUT"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&gpu { + status = "disabled"; + mali-supply = <®_dcdc1>; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "disabled"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "disabled"; + pinctrl-0 = <&i2c1_pi_pins>; + pinctrl-names = "default"; +}; + +&i2c3 { + status = "disabled"; + pinctrl-0 = <&i2c3_pg_pins>; + pinctrl-names = "default"; +}; + +&i2c4 { + status = "disabled"; + pinctrl-0 = <&i2c4_pg_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "disabled"; + pinctrl-0 = <&ir_rx_pin>; + pinctrl-names = "default"; +}; + +/* SD card */ +&mmc0 { + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + + disable-wp; + + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + vmmc-supply = <®_vcc3v3>; +}; + +/* eMMC */ +&mmc2 { + status = "okay"; + bus-width = <8>; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + + non-removable; + disable-wp; + + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; +}; + +&pio { + vcc-pc-supply = <®_aldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_dldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; + + /* PC0 required for spi0 */ + mmc2_pins: mmc2-pins { + pins = "PC1", "PC5", "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; +}; + +&r_i2c { + status = "okay"; + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&pio>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8-pll"; + }; + + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-io"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&spi0 { + status = "disabled"; + pinctrl-0 = <&spi0_pins>, <&spi1_cs0_pin>; + pinctrl-names = "default"; + + spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + spi-max-frequency = <1000000>; + }; +}; + +&spi1 { + status = "disabled"; + pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>; + pinctrl-names = "default"; + + spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + spi-max-frequency = <1000000>; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_ph_pins>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "disabled"; + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; +}; + +&uart4 { + status = "disabled"; + pinctrl-0 = <&uart4_pi_pins>; + pinctrl-names = "default"; +}; + +&uart5 { + status = "disabled"; + pinctrl-0 = <&uart5_pins>; + pinctrl-names = "default"; +}; diff --git a/patch/kernel/sunxi-6.16/dt/sun50i-h618-kickpi-k2b.dts b/patch/kernel/sunxi-6.16/dt/sun50i-h618-kickpi-k2b.dts new file mode 100644 index 0000000..3dc98ab --- /dev/null +++ b/patch/kernel/sunxi-6.16/dt/sun50i-h618-kickpi-k2b.dts @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Patrick Yavitz + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" + +#include +#include +#include +#include + +/ { + model = "KickPi K2B"; + compatible = "kickpi,k2b", "allwinner,sun50i-h618"; + + aliases { + ethernet0 = &emac0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + kaslr-seed = <0xfeedbeef 0xc0def00d>; + }; + + connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + button-power { + label = "power"; + linux,code = ; + gpios = <&pio 2 2 GPIO_ACTIVE_LOW>; /* PC2 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 8 16 GPIO_ACTIVE_HIGH>; /* PI16 */ + linux,default-trigger = "heartbeat"; + }; + }; + + reg_usb_vbus: regulator-usb-vbus { + /* Separate discrete regulator for the USB ports */ + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "usb-vbus"; + vin-supply = <®_vcc5v>; + }; + + reg_vcc5v: regulator-vcc5v { + /* Board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc-5v"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>, /* PG18 */ + <&pio 6 19 GPIO_ACTIVE_LOW>; /* PG19 */ + }; +}; + +&ahub_dam_plat { + status = "okay"; +}; + +&ahub1_plat { + status = "okay"; +}; + +&ahub1_mach { + status = "okay"; +}; + +&codec { + status = "okay"; + allwinner,audio-routing = "Line Out", "LINEOUT"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&emac0 { + status = "okay"; + pinctrl-0 = <&ext_rgmii_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + allwinner,tx-delay-ps = <700>; + allwinner,rx-delay-ps = <1700>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "disabled"; +}; + +&gpu { + status = "okay"; + mali-supply = <®_dcdc1>; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c1 { + status = "disabled"; + pinctrl-0 = <&i2c1_ph_pins>; + pinctrl-names = "default"; +}; + +&i2c2 { + status = "disabled"; + pinctrl-0 = <&i2c2_ph_pins>; + pinctrl-names = "default"; +}; + +&i2c3 { + status = "disabled"; + pinctrl-0 = <&i2c3_ph_pins>; + pinctrl-names = "default"; +}; + +&i2c4 { + status = "disabled"; + pinctrl-0 = <&i2c4_ph_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&ir_rx_pin>; + pinctrl-names = "default"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 8 6 GPIO_ACTIVE_LOW>; /* PI6 */ + }; +}; + +/* SD card */ +&mmc0 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + disable-wp; + max-frequency = <50000000>; + vmmc-supply = <®_dldo1>; +}; + +/* SDIO */ +&mmc1 { + status = "okay"; + bus-width = <4>; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + + sdio: wifi@1 { + reg = <1>; + }; +}; + +/* eMMC */ +&mmc2 { + status = "okay"; + bus-width = <8>; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "disabled"; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; + vcc-pl-supply = <®_aldo1>; + + /* PI16 required for sys_led */ + ext_rgmii_pins: rgmii-pins { + pins = "PI0", "PI1", "PI2", "PI3", "PI4", + "PI5", "PI7", "PI8", "PI9", "PI10", + "PI11", "PI12", "PI13", "PI14", "PI15"; + function = "emac0"; + drive-strength = <40>; + }; + + /* Add I2C PH Pins */ + i2c1_ph_pins: i2c1-ph-pins { + pins = "PH0", "PH1"; + function = "i2c1"; + }; + + i2c2_ph_pins: i2c2-ph-pins { + pins = "PH2", "PH3"; + function = "i2c2"; + }; + + i2c4_ph_pins: i2c4-ph-pins { + pins = "PH6", "PH7"; + function = "i2c4"; + }; + + /* PC0 required for spi0 */ + mmc2_pins: mmc2-pins { + pins = "PC1", "PC5", "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; +}; + +&r_i2c { + status = "okay"; + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&pio>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8-pll"; + }; + + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-io"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&spi1 { + status = "disabled"; + pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>; + pinctrl-names = "default"; + + spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + spi-max-frequency = <1000000>; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_ph_pins>; + pinctrl-names = "default"; +}; + +/* Bluetooth */ +&uart1 { + status = "okay"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&uart2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_ph_pins>; +}; + +&uart5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; +}; + +&usbotg { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usbphy { + status = "okay"; + usb1_vbus-supply = <®_usb_vbus>; +}; diff --git a/patch/kernel/sunxi-6.14/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch b/patch/kernel/sunxi-6.16/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch rename to patch/kernel/sunxi-6.16/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch b/patch/kernel/sunxi-6.16/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch rename to patch/kernel/sunxi-6.16/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-EMAC1.patch b/patch/kernel/sunxi-6.16/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-EMAC1.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-EMAC1.patch rename to patch/kernel/sunxi-6.16/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-EMAC1.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-HDMI.patch b/patch/kernel/sunxi-6.16/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-HDMI.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-HDMI.patch rename to patch/kernel/sunxi-6.16/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-HDMI.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/ASoC-AC200-Initial-driver.patch b/patch/kernel/sunxi-6.16/patches.armbian/ASoC-AC200-Initial-driver.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.armbian/ASoC-AC200-Initial-driver.patch rename to patch/kernel/sunxi-6.16/patches.armbian/ASoC-AC200-Initial-driver.patch index b634e51..14ba033 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/ASoC-AC200-Initial-driver.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/ASoC-AC200-Initial-driver.patch @@ -1,4 +1,4 @@ -From 2ace8ce7a3eb989f415186c74e6fbec9d2196c20 Mon Sep 17 00:00:00 2001 +From 054078aaba679a23051906fb1168e8201fe1ea7d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 1 Sep 2022 17:36:53 +0200 Subject: ASoC: AC200: Initial driver @@ -12,7 +12,7 @@ Signed-off-by: Jernej Skrabec create mode 100644 sound/soc/codecs/ac200.c diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig -index 45737cfc5966..1b7b38e3b5b9 100644 +index b1133b34efbd..b7b9788eb2a8 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -16,6 +16,7 @@ config SND_SOC_ALL_CODECS @@ -23,7 +23,7 @@ index 45737cfc5966..1b7b38e3b5b9 100644 imply SND_SOC_AC97_CODEC imply SND_SOC_AD1836 imply SND_SOC_AD193X_SPI -@@ -417,6 +418,15 @@ config SND_SOC_AB8500_CODEC +@@ -418,6 +419,15 @@ config SND_SOC_AB8500_CODEC tristate depends on ABX500_CORE @@ -40,7 +40,7 @@ index 45737cfc5966..1b7b38e3b5b9 100644 tristate "Build generic ASoC AC97 CODEC driver" select SND_AC97_CODEC diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile -index 7e12f3ae4f7d..eaae2fc19fbd 100644 +index 0f4d541fc619..d5a84598ee1b 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -1,6 +1,7 @@ @@ -51,7 +51,7 @@ index 7e12f3ae4f7d..eaae2fc19fbd 100644 snd-soc-ac97-y := ac97.o snd-soc-ad1836-y := ad1836.o snd-soc-ad193x-y := ad193x.o -@@ -418,6 +419,7 @@ snd-soc-simple-mux-y := simple-mux.o +@@ -419,6 +420,7 @@ snd-soc-simple-mux-y := simple-mux.o obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch b/patch/kernel/sunxi-6.16/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch b/patch/kernel/sunxi-6.16/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Add-FB_TFT-ST7796S-driver.patch b/patch/kernel/sunxi-6.16/patches.armbian/Add-FB_TFT-ST7796S-driver.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Add-FB_TFT-ST7796S-driver.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Add-FB_TFT-ST7796S-driver.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch b/patch/kernel/sunxi-6.16/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch b/patch/kernel/sunxi-6.16/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch index e0e8456..02208e7 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch @@ -1,4 +1,4 @@ -From a69f9a8b101b90606e01282a52262b129156f329 Mon Sep 17 00:00:00 2001 +From 836de5e4296b33c8145b3e6bbc09a7836f059212 Mon Sep 17 00:00:00 2001 From: afaulkner420 Date: Fri, 25 Mar 2022 20:18:18 +0000 Subject: Add sunxi-addr driver - Used to fix uwe5622 bluetooth MAC addresses @@ -17,20 +17,20 @@ Subject: Add sunxi-addr driver - Used to fix uwe5622 bluetooth MAC addresses create mode 100644 drivers/misc/sunxi-addr/sunxi-addr.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig -index c0efb3129661..7a7a8eaba0ef 100644 +index 3b866b34b5a3..b85a01bba452 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig -@@ -656,4 +656,5 @@ source "drivers/misc/uacce/Kconfig" +@@ -655,4 +655,5 @@ source "drivers/misc/uacce/Kconfig" source "drivers/misc/pvpanic/Kconfig" source "drivers/misc/mchp_pci1xxxx/Kconfig" source "drivers/misc/keba/Kconfig" +source "drivers/misc/sunxi-addr/Kconfig" endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile -index 9b20ffa44835..cd8ba3232581 100644 +index c5979bb01b86..70eb35c70842 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile -@@ -76,3 +76,4 @@ lan966x-pci-objs += lan966x_pci.dtbo.o +@@ -75,3 +75,4 @@ lan966x-pci-objs += lan966x_pci.dtbo.o obj-$(CONFIG_MCHP_LAN966X_PCI) += lan966x-pci.o obj-y += keba/ obj-$(CONFIG_MODEM_POWER) += modem-power.o diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch b/patch/kernel/sunxi-6.16/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch b/patch/kernel/sunxi-6.16/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch b/patch/kernel/sunxi-6.16/patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch rename to patch/kernel/sunxi-6.16/patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Compile-the-pwm-overlay.patch b/patch/kernel/sunxi-6.16/patches.armbian/Compile-the-pwm-overlay.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Compile-the-pwm-overlay.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Compile-the-pwm-overlay.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Correct-perf-interrupt-source-number-as-referenced-in-the-Allwi.patch b/patch/kernel/sunxi-6.16/patches.armbian/Correct-perf-interrupt-source-number-as-referenced-in-the-Allwi.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Correct-perf-interrupt-source-number-as-referenced-in-the-Allwi.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Correct-perf-interrupt-source-number-as-referenced-in-the-Allwi.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch b/patch/kernel/sunxi-6.16/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Enable-DMA-support-for-the-Allwinner-A10-EMAC-which-already-exi.patch b/patch/kernel/sunxi-6.16/patches.armbian/Enable-DMA-support-for-the-Allwinner-A10-EMAC-which-already-exi.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Enable-DMA-support-for-the-Allwinner-A10-EMAC-which-already-exi.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Enable-DMA-support-for-the-Allwinner-A10-EMAC-which-already-exi.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Enable-creation-of-__symbols__-node.patch b/patch/kernel/sunxi-6.16/patches.armbian/Enable-creation-of-__symbols__-node.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Enable-creation-of-__symbols__-node.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Enable-creation-of-__symbols__-node.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch b/patch/kernel/sunxi-6.16/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch similarity index 90% rename from patch/kernel/sunxi-6.14/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch index e3c7015..1e87799 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch @@ -1,4 +1,4 @@ -From 5607ccab3192a2cc9d70c6072f83d9b9060295c8 Mon Sep 17 00:00:00 2001 +From b75f5bf0d822ac325c205a489941f33256ed4b9a Mon Sep 17 00:00:00 2001 From: JohnTheCoolingFan Date: Sat, 25 Jan 2025 12:54:16 +0000 Subject: Fix ghost touches on tsc2007 tft screen @@ -24,11 +24,11 @@ index 2022990e4bc0..3b3a196eaa93 100644 ti,fuzzx = <32>; ti,fuzzy = <16>; diff --git a/drivers/input/touchscreen/tsc2007.h b/drivers/input/touchscreen/tsc2007.h -index 5252b6c6daeb..7411b8bce99c 100644 +index 46ae4e4183b8..c84b687b5399 100644 --- a/drivers/input/touchscreen/tsc2007.h +++ b/drivers/input/touchscreen/tsc2007.h -@@ -65,6 +65,7 @@ struct tsc2007 { - +@@ -67,6 +67,7 @@ struct tsc2007 { + struct touchscreen_properties prop; u16 model; u16 x_plate_ohms; + u16 y_plate_ohms; @@ -36,7 +36,7 @@ index 5252b6c6daeb..7411b8bce99c 100644 u16 rt_thr; u8 touched; diff --git a/drivers/input/touchscreen/tsc2007_core.c b/drivers/input/touchscreen/tsc2007_core.c -index 08bbbafbbae1..1ae1b1a3e367 100644 +index 2abcaff3fe0a..12e7b5cbcabf 100644 --- a/drivers/input/touchscreen/tsc2007_core.c +++ b/drivers/input/touchscreen/tsc2007_core.c @@ -70,22 +70,20 @@ static void tsc2007_read_values(struct tsc2007 *tsc, struct ts_event *tc) @@ -72,7 +72,7 @@ index 08bbbafbbae1..1ae1b1a3e367 100644 } bool tsc2007_is_pen_down(struct tsc2007 *ts) -@@ -180,6 +178,7 @@ static irqreturn_t tsc2007_soft_poll(int irq, void *handle) +@@ -179,6 +177,7 @@ static irqreturn_t tsc2007_soft_poll(int irq, void *handle) struct input_dev *input = ts->input; struct ts_event tc; u32 rt; @@ -80,7 +80,7 @@ index 08bbbafbbae1..1ae1b1a3e367 100644 if(!ts->stopped) { -@@ -189,45 +188,31 @@ static irqreturn_t tsc2007_soft_poll(int irq, void *handle) +@@ -188,45 +187,31 @@ static irqreturn_t tsc2007_soft_poll(int irq, void *handle) rt = tsc2007_calculate_resistance(ts, &tc); @@ -146,7 +146,7 @@ index 08bbbafbbae1..1ae1b1a3e367 100644 } return IRQ_HANDLED; -@@ -329,6 +314,13 @@ static int tsc2007_probe_properties(struct device *dev, struct tsc2007 *ts) +@@ -328,6 +313,13 @@ static int tsc2007_probe_properties(struct device *dev, struct tsc2007 *ts) return -EINVAL; } @@ -160,7 +160,7 @@ index 08bbbafbbae1..1ae1b1a3e367 100644 ts->gpiod = devm_gpiod_get_optional(dev, NULL, GPIOD_IN); if (IS_ERR(ts->gpiod)) return PTR_ERR(ts->gpiod); -@@ -347,6 +339,7 @@ static int tsc2007_probe_pdev(struct device *dev, struct tsc2007 *ts, +@@ -346,6 +338,7 @@ static int tsc2007_probe_pdev(struct device *dev, struct tsc2007 *ts, { ts->model = pdata->model; ts->x_plate_ohms = pdata->x_plate_ohms; @@ -168,7 +168,7 @@ index 08bbbafbbae1..1ae1b1a3e367 100644 ts->max_rt = pdata->max_rt ? : MAX_12BIT; ts->poll_period = msecs_to_jiffies(pdata->poll_period ? : 1); ts->get_pendown_state = pdata->get_pendown_state; -@@ -360,6 +353,11 @@ static int tsc2007_probe_pdev(struct device *dev, struct tsc2007 *ts, +@@ -359,6 +352,11 @@ static int tsc2007_probe_pdev(struct device *dev, struct tsc2007 *ts, return -EINVAL; } @@ -180,7 +180,7 @@ index 08bbbafbbae1..1ae1b1a3e367 100644 return 0; } -@@ -458,11 +456,9 @@ static int tsc2007_probe(struct i2c_client *client) +@@ -457,11 +455,9 @@ static int tsc2007_probe(struct i2c_client *client) return err; } } else { diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Fix-include-uapi-spi-spidev-module.patch b/patch/kernel/sunxi-6.16/patches.armbian/Fix-include-uapi-spi-spidev-module.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Fix-include-uapi-spi-spidev-module.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Fix-include-uapi-spi-spidev-module.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch b/patch/kernel/sunxi-6.16/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch b/patch/kernel/sunxi-6.16/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch rename to patch/kernel/sunxi-6.16/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch b/patch/kernel/sunxi-6.16/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch similarity index 81% rename from patch/kernel/sunxi-6.14/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch index c30677d..753b091 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch @@ -1,4 +1,4 @@ -From a0d572eb612278a969beebead69eeba250c8f74f Mon Sep 17 00:00:00 2001 +From 836e3c6dde4128b0c846e8baeffb6a8e8ea58e00 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Wed, 2 Feb 2022 11:28:14 +0300 Subject: Makefile: CONFIG_SHELL fix for builddeb packaging @@ -8,10 +8,10 @@ Subject: Makefile: CONFIG_SHELL fix for builddeb packaging 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile -index f49182f3bae1..b121106a8cef 100644 +index c1cd1b5fc269..d829884494af 100644 --- a/Makefile +++ b/Makefile -@@ -439,7 +439,9 @@ KCONFIG_CONFIG ?= .config +@@ -436,7 +436,9 @@ KCONFIG_CONFIG ?= .config export KCONFIG_CONFIG # SHELL used by kbuild diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch b/patch/kernel/sunxi-6.16/patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch b/patch/kernel/sunxi-6.16/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch similarity index 87% rename from patch/kernel/sunxi-6.14/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch index 7ab9da4..4b51dc9 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch @@ -1,18 +1,18 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From baabc51678faaf2020ee7791e2a52e39517cbc93 Mon Sep 17 00:00:00 2001 From: Alan Date: Sat, 20 May 2023 14:44:07 +0800 Subject: Optimize: TSC2007 touchscreen add polling method --- - drivers/input/touchscreen/tsc2007.h | 6 + - drivers/input/touchscreen/tsc2007_core.c | 110 +++++++++- + drivers/input/touchscreen/tsc2007.h | 6 ++ + drivers/input/touchscreen/tsc2007_core.c | 110 +++++++++++++++++++++-- 2 files changed, 108 insertions(+), 8 deletions(-) diff --git a/drivers/input/touchscreen/tsc2007.h b/drivers/input/touchscreen/tsc2007.h -index 111111111111..222222222222 100644 +index e346fb4f7552..46ae4e4183b8 100644 --- a/drivers/input/touchscreen/tsc2007.h +++ b/drivers/input/touchscreen/tsc2007.h -@@ -66,10 +66,13 @@ struct tsc2007 { +@@ -68,10 +68,13 @@ struct tsc2007 { u16 model; u16 x_plate_ohms; u16 max_rt; @@ -26,7 +26,7 @@ index 111111111111..222222222222 100644 struct gpio_desc *gpiod; int irq; -@@ -81,6 +84,9 @@ struct tsc2007 { +@@ -83,6 +86,9 @@ struct tsc2007 { void (*clear_penirq)(void); struct mutex mlock; @@ -37,7 +37,7 @@ index 111111111111..222222222222 100644 int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd); diff --git a/drivers/input/touchscreen/tsc2007_core.c b/drivers/input/touchscreen/tsc2007_core.c -index 111111111111..222222222222 100644 +index 5252301686ec..2abcaff3fe0a 100644 --- a/drivers/input/touchscreen/tsc2007_core.c +++ b/drivers/input/touchscreen/tsc2007_core.c @@ -28,6 +28,8 @@ @@ -49,7 +49,7 @@ index 111111111111..222222222222 100644 int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd) { s32 data; -@@ -172,6 +174,65 @@ static irqreturn_t tsc2007_soft_irq(int irq, void *handle) +@@ -171,6 +173,65 @@ static irqreturn_t tsc2007_soft_irq(int irq, void *handle) return IRQ_HANDLED; } @@ -115,7 +115,7 @@ index 111111111111..222222222222 100644 static void tsc2007_stop(struct tsc2007 *ts) { ts->stopped = true; -@@ -216,11 +277,32 @@ static int tsc2007_get_pendown_state_gpio(struct device *dev) +@@ -215,11 +276,32 @@ static int tsc2007_get_pendown_state_gpio(struct device *dev) return gpiod_get_value_cansleep(ts->gpiod); } @@ -148,7 +148,7 @@ index 111111111111..222222222222 100644 if (!device_property_read_u32(dev, "ti,max-rt", &val32)) ts->max_rt = val32; else -@@ -317,6 +399,9 @@ static int tsc2007_probe(struct i2c_client *client) +@@ -316,6 +398,9 @@ static int tsc2007_probe(struct i2c_client *client) if (!input_dev) return -ENOMEM; @@ -158,7 +158,7 @@ index 111111111111..222222222222 100644 i2c_set_clientdata(client, ts); ts->client = client; -@@ -362,14 +447,23 @@ static int tsc2007_probe(struct i2c_client *client) +@@ -361,14 +446,23 @@ static int tsc2007_probe(struct i2c_client *client) pdata->init_platform_hw(); } @@ -191,5 +191,5 @@ index 111111111111..222222222222 100644 tsc2007_stop(ts); -- -Armbian +2.35.3 diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Revert-drm-sun4i-hdmi-switch-to-struct-drm_edid.patch b/patch/kernel/sunxi-6.16/patches.armbian/Revert-drm-sun4i-hdmi-switch-to-struct-drm_edid.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Revert-drm-sun4i-hdmi-switch-to-struct-drm_edid.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Revert-drm-sun4i-hdmi-switch-to-struct-drm_edid.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch b/patch/kernel/sunxi-6.16/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch index 7dc1008..61d3cb7 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch @@ -1,4 +1,4 @@ -From 9b0e8a8239f334a40d1637204a0f58ab2efc0061 Mon Sep 17 00:00:00 2001 +From 096ce641f39e64987a038cfb18d9783d35d36a33 Mon Sep 17 00:00:00 2001 From: Stephen Graf Date: Wed, 26 Mar 2025 17:06:51 +0000 Subject: Sound for H616, H618 Allwinner SOCs @@ -158,10 +158,10 @@ index 307a8678e0eb..8de963bee2ac 100644 compatible = "allwinner,sun50i-h616-musb", "allwinner,sun8i-h3-musb"; diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h -index a11501752637..eb1eb56a4a6d 100644 +index d19ab5572d2b..15efde43c629 100644 --- a/include/sound/soc-dai.h +++ b/include/sound/soc-dai.h -@@ -413,6 +413,15 @@ struct snd_soc_dai_driver { +@@ -407,6 +407,15 @@ struct snd_soc_dai_driver { struct snd_soc_dobj dobj; const struct of_phandle_args *dai_args; @@ -177,7 +177,7 @@ index a11501752637..eb1eb56a4a6d 100644 /* ops */ const struct snd_soc_dai_ops *ops; const struct snd_soc_cdai_ops *cops; -@@ -423,6 +432,10 @@ struct snd_soc_dai_driver { +@@ -417,6 +426,10 @@ struct snd_soc_dai_driver { unsigned int symmetric_rate:1; unsigned int symmetric_channels:1; unsigned int symmetric_sample_bits:1; @@ -189,10 +189,10 @@ index a11501752637..eb1eb56a4a6d 100644 /* for Playback/Capture */ diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig -index 5efba76abb31..b1b4693ca49b 100644 +index 8b7d51266f81..3f3a9d0554fb 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig -@@ -117,6 +117,7 @@ source "sound/soc/starfive/Kconfig" +@@ -124,6 +124,7 @@ source "sound/soc/starfive/Kconfig" source "sound/soc/sti/Kconfig" source "sound/soc/stm/Kconfig" source "sound/soc/sunxi/Kconfig" @@ -201,10 +201,10 @@ index 5efba76abb31..b1b4693ca49b 100644 source "sound/soc/ti/Kconfig" source "sound/soc/uniphier/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile -index 08baaa11d813..ca53a0853e0f 100644 +index 358e227c5ab6..f919da58551b 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile -@@ -70,6 +70,7 @@ obj-$(CONFIG_SND_SOC) += starfive/ +@@ -74,6 +74,7 @@ obj-$(CONFIG_SND_SOC) += starfive/ obj-$(CONFIG_SND_SOC) += sti/ obj-$(CONFIG_SND_SOC) += stm/ obj-$(CONFIG_SND_SOC) += sunxi/ @@ -213,7 +213,7 @@ index 08baaa11d813..ca53a0853e0f 100644 obj-$(CONFIG_SND_SOC) += ti/ obj-$(CONFIG_SND_SOC) += uniphier/ diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c -index 3c6d8aef4130..e81e3b32569c 100644 +index 3f97d1f132c6..ade050657e5a 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -2632,6 +2632,7 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component, @@ -799,12 +799,12 @@ index 000000000000..6d4a847a928f + + /* set master/slave */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -+ case SND_SOC_DAIFMT_CBM_CFM: ++ case SND_SOC_DAIFMT_CBP_CFP: + /* lrck & bclk dir output */ + regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), + 0x1 << I2S_CTL_CLK_OUT, 0x0 << I2S_CTL_CLK_OUT); + break; -+ case SND_SOC_DAIFMT_CBS_CFS: ++ case SND_SOC_DAIFMT_CBC_CFC: + /* lrck & bclk dir input */ + regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), + 0x1 << I2S_CTL_CLK_OUT, 0x1 << I2S_CTL_CLK_OUT); diff --git a/patch/kernel/sunxi-6.14/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch b/patch/kernel/sunxi-6.16/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch rename to patch/kernel/sunxi-6.16/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/add-dtb-overlay-for-zero2w.patch b/patch/kernel/sunxi-6.16/patches.armbian/add-dtb-overlay-for-zero2w.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/add-dtb-overlay-for-zero2w.patch rename to patch/kernel/sunxi-6.16/patches.armbian/add-dtb-overlay-for-zero2w.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/add-initial-support-for-orangepi3-lts.patch b/patch/kernel/sunxi-6.16/patches.armbian/add-initial-support-for-orangepi3-lts.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/add-initial-support-for-orangepi3-lts.patch rename to patch/kernel/sunxi-6.16/patches.armbian/add-initial-support-for-orangepi3-lts.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch b/patch/kernel/sunxi-6.16/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch rename to patch/kernel/sunxi-6.16/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch index 3f86d15..c26346d 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch @@ -1,4 +1,4 @@ -From 165e8af0db38e2880c067355f5153ec6ca880b32 Mon Sep 17 00:00:00 2001 +From 379b3c9bf09db69afb31eb1f9f7f65e5a83b4308 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Mon, 24 Jan 2022 15:00:36 +0300 Subject: arm:dts: Add sun8i-h2-plus-nanopi-duo device @@ -10,10 +10,10 @@ Subject: arm:dts: Add sun8i-h2-plus-nanopi-duo device create mode 100644 arch/arm/boot/dts/allwinner/sun8i-h2-plus-nanopi-duo.dts diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile -index 1356e9553bd6..803bc88fccd6 100644 +index 326ff9c7de72..129d9e3d75a4 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile -@@ -222,6 +222,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ +@@ -223,6 +223,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-tbs-a711.dtb \ sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch index 820c80c..9d1c2ea 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch @@ -1,4 +1,4 @@ -From a0710275bb42a34ca0b8d2e62d1a39dfce4f00c7 Mon Sep 17 00:00:00 2001 +From 484b8abd16c1dd8ddaa0c9027b53de524d24809c Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Mon, 24 Jan 2022 15:23:33 +0300 Subject: arm:dts: Add sun8i-h2-plus-sunvell-r69 device @@ -10,10 +10,10 @@ Subject: arm:dts: Add sun8i-h2-plus-sunvell-r69 device create mode 100644 arch/arm/boot/dts/allwinner/sun8i-h2-plus-sunvell-r69.dts diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile -index 803bc88fccd6..2e8615538458 100644 +index 129d9e3d75a4..91fdb57d2c19 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile -@@ -225,6 +225,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ +@@ -226,6 +226,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h2-plus-nanopi-duo.dtb \ sun8i-h2-plus-orangepi-r1.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch index e381799..4e252fb 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch @@ -1,4 +1,4 @@ -From ab05f16488960a29e368534057af5aabea7cca78 Mon Sep 17 00:00:00 2001 +From 3110211a08b8a2d759a8c01170732fa5ffb0d850 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Wed, 2 Feb 2022 12:54:05 +0300 Subject: arm:dts:overlay Add Overlays for sunxi @@ -200,10 +200,10 @@ Subject: arm:dts:overlay Add Overlays for sunxi create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart7.dtso diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile -index 2e8615538458..ff32410674de 100644 +index 91fdb57d2c19..420454ae04dd 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile -@@ -272,3 +272,5 @@ dtb-$(CONFIG_MACH_SUNIV) += \ +@@ -274,3 +274,5 @@ dtb-$(CONFIG_MACH_SUNIV) += \ suniv-f1c100s-licheepi-nano.dtb \ suniv-f1c200s-lctech-pi.dtb \ suniv-f1c200s-popstick-v1.1.dtb diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch diff --git a/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun4i-pcduino2-add-hdmi.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun4i-pcduino2-add-hdmi.patch new file mode 100644 index 0000000..9f18ed9 --- /dev/null +++ b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun4i-pcduino2-add-hdmi.patch @@ -0,0 +1,64 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ryzer58 +Date: Mon, 24 Feb 2025 23:12:01 +0000 +Subject: Add HDMI support for pcDuino 1 and 2 by including HDMI and DE nodes + +Signed-off-by: Ryzer58 +--- + arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts | 25 ++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts +index a332d61fd561..b54f54ecc026 100644 +--- a/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts ++++ b/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts +@@ -72,10 +72,21 @@ led-1 { + label = "pcduino:green:rx"; + gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; + }; + }; + ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + gpio-keys { + compatible = "gpio-keys"; + + key-back { + label = "Key Back"; +@@ -125,10 +136,24 @@ axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; + }; + ++&de { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-bananapro-add-AXP209-regulators.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-bananapro-add-AXP209-regulators.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-bananapro-add-AXP209-regulators.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-bananapro-add-AXP209-regulators.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch diff --git a/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-pcduino3-add-hdmi.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-pcduino3-add-hdmi.patch new file mode 100644 index 0000000..8617296 --- /dev/null +++ b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun7i-pcduino3-add-hdmi.patch @@ -0,0 +1,64 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ryzer58 +Date: Mon, 2 Jun 2025 00:29:48 +0100 +Subject: Add HDMI support for pcDuino 3 by including HDMI and DE nodes + +Signed-off-by: Ryzer58 +--- + arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts | 25 ++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts +index 928b86a95f34..5086fb93f3b1 100644 +--- a/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts ++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts +@@ -73,10 +73,21 @@ led-1 { + label = "pcduino3:green:rx"; + gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; + }; + }; + ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + gpio-keys { + compatible = "gpio-keys"; + + key-back { + label = "Key Back"; +@@ -135,10 +146,24 @@ axp209: pmic@34 { + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + }; + ++&de { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + #include "axp209.dtsi" + + &ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pin>; +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch similarity index 89% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch index 34e94f0..76f3351 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch @@ -1,15 +1,15 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 404a4f5b185c2fa8946f4cdc45d5236f635ccf33 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Fri, 28 Jan 2022 12:58:57 +0300 Subject: arm:dts: sun8i-v3s/s3-pinecube enable sound codec --- - arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts | 14 ++++++++++ - arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 14 ++++++++++ + arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts | 14 ++++++++++++++ + arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts -index 111111111111..222222222222 100644 +index e0d4404b5957..46d6030e8ff6 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts @@ -58,6 +58,20 @@ wifi_pwrseq: pwrseq { @@ -34,10 +34,10 @@ index 111111111111..222222222222 100644 pinctrl-names = "default"; pinctrl-0 = <&csi1_8bit_pins>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi -index 111111111111..222222222222 100644 +index f909b1d4dbca..c08eb315dcf7 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi -@@ -506,6 +506,20 @@ codec_analog: codec-analog@1c23000 { +@@ -512,6 +512,20 @@ codec_analog: codec-analog@1c23000 { reg = <0x01c23000 0x4>; }; @@ -59,5 +59,5 @@ index 111111111111..222222222222 100644 compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- -Armbian +2.35.3 diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch index ff670c4..12e44e0 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch @@ -11,7 +11,7 @@ Subject: arm64: allwinner: Add sun50i-h618-bananapi-m4-berry support create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile -index a676c57aad1d..a34f2dbcc9b4 100644 +index 67f738f9b513..a676c57aad1d 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb @@ -19,9 +19,9 @@ index a676c57aad1d..a34f2dbcc9b4 100644 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-berry.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 004e824dfe0b..0f4587be1c0e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch index de32907..6034089 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch @@ -13,7 +13,7 @@ Signed-off-by: Jernej Skrabec 3 files changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index 5371662e52e7..74c9e4bac60d 100644 +index 452e72d9583f..c0162e2c4249 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -104,6 +104,19 @@ wifi_pwrseq: wifi-pwrseq { @@ -51,8 +51,8 @@ index 5371662e52e7..74c9e4bac60d 100644 &hdmi { status = "okay"; }; -@@ -220,6 +241,10 @@ &pio { - vcc-pg-supply = <®_vcc_wifi_io>; +@@ -337,6 +358,10 @@ sw { + }; }; +&pwm { diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch index 24b03ff..11148fa 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch @@ -107,10 +107,10 @@ diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwin index f80ea3d3ecec..80098fa014ac 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile -@@ -57,3 +57,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-sp.dtb +@@ -57,3 +57,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-sp.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun55i-a527-cubie-a5e.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun55i-h728-x96qpro+.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-avaota-a1.dtb + +subdir-y := $(dts-dirs) overlay diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-pwm-uart.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-pwm-uart.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-pwm-uart.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-pwm-uart.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch similarity index 84% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch index a573bed..733dc13 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch @@ -1,4 +1,4 @@ -From 7046bdcb478b36bc1886e3fca35a590e58c57201 Mon Sep 17 00:00:00 2001 +From ed7bdf184c5acfb1b82d8374615a05080794585b Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Wed, 2 Feb 2022 21:22:57 +0300 Subject: arm64:dts: sun50i-h6-orangepi enable higher clock @@ -9,10 +9,10 @@ Subject: arm64:dts: sun50i-h6-orangepi enable higher clock 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -index ca57044cfe57..1c0e8288ebf6 100644 +index e13d345f9abe..7d7dbb7973c6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -@@ -218,7 +218,7 @@ reg_cldo3: cldo3 { +@@ -210,7 +210,7 @@ reg_cldo3: cldo3 { reg_dcdca: dcdca { regulator-always-on; regulator-min-microvolt = <810000>; diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch b/patch/kernel/sunxi-6.16/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch rename to patch/kernel/sunxi-6.16/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/cb1-overlay.patch b/patch/kernel/sunxi-6.16/patches.armbian/cb1-overlay.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/cb1-overlay.patch rename to patch/kernel/sunxi-6.16/patches.armbian/cb1-overlay.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch b/patch/kernel/sunxi-6.16/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch rename to patch/kernel/sunxi-6.16/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/driver-allwinner-h618-emac.patch b/patch/kernel/sunxi-6.16/patches.armbian/driver-allwinner-h618-emac.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.armbian/driver-allwinner-h618-emac.patch rename to patch/kernel/sunxi-6.16/patches.armbian/driver-allwinner-h618-emac.patch index dee2b56..252a755 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/driver-allwinner-h618-emac.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/driver-allwinner-h618-emac.patch @@ -1,4 +1,4 @@ -From 73d5c27e53e0a2ee71cbd060f19029957fc551a5 Mon Sep 17 00:00:00 2001 +From 9d7527d6984ecab258affbf87a93f010e8329bbf Mon Sep 17 00:00:00 2001 From: chraac Date: Fri, 16 Aug 2024 16:44:41 +0800 Subject: driver: allwinner h618 emac @@ -27,7 +27,7 @@ Subject: driver: allwinner h618 emac create mode 100644 include/linux/mfd/ac200.h diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c -index 176e9142fd8f..b9f82442a985 100644 +index 65f6a7177b78..0154341c8aa6 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -25,21 +25,6 @@ @@ -52,7 +52,7 @@ index 176e9142fd8f..b9f82442a985 100644 /** * of_gpio_named_count() - Count GPIOs for a device * @np: device node to count GPIOs for -@@ -428,6 +413,20 @@ static struct gpio_desc *of_get_named_gpiod_flags(const struct device_node *np, +@@ -437,6 +422,20 @@ static struct gpio_desc *of_get_named_gpiod_flags(const struct device_node *np, return desc; } @@ -74,7 +74,7 @@ index 176e9142fd8f..b9f82442a985 100644 * of_get_named_gpio() - Get a GPIO number to use with GPIO API * @np: device node to get GPIO from diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig -index 77ab69463ae8..5ab57bf43741 100644 +index 1f36768c18f8..50225515fc81 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -215,6 +215,16 @@ config MFD_AC200 @@ -95,10 +95,10 @@ index 77ab69463ae8..5ab57bf43741 100644 tristate select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile -index 568ca7b227db..3ba1fcdbbbbd 100644 +index 63a5ba7b9f52..2cd12652286d 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile -@@ -147,6 +147,7 @@ obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o +@@ -146,6 +146,7 @@ obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o obj-$(CONFIG_MFD_AC100) += ac100.o obj-$(CONFIG_MFD_AC200) += ac200.o @@ -3702,7 +3702,7 @@ index 000000000000..926516835023 +} +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig -index 9e73ab1b2fbb..782fb4445e55 100644 +index 51eb1f599b02..06226a1b6e41 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -91,6 +91,14 @@ config AC200_PHY @@ -3721,10 +3721,10 @@ index 9e73ab1b2fbb..782fb4445e55 100644 tristate "AMD and Altima PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile -index 828de189d7ae..88597adfcebb 100644 +index c2bdd0daf459..7efdcc4ba8fe 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -34,6 +34,7 @@ sfp-obj-$(CONFIG_SFP) += sfp-bus.o +@@ -35,6 +35,7 @@ sfp-obj-$(CONFIG_SFP) += sfp-bus.o obj-y += $(sfp-obj-y) $(sfp-obj-m) obj-$(CONFIG_AC200_PHY) += ac200-phy.o diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch b/patch/kernel/sunxi-6.16/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch b/patch/kernel/sunxi-6.16/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch index 462611b..f2e400e 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch @@ -1,4 +1,4 @@ -From d09971d1f6971b3035599d77bfcf4374084bb3d9 Mon Sep 17 00:00:00 2001 +From e344416357eb02fa16ac438517efdb99cb272553 Mon Sep 17 00:00:00 2001 From: chraac Date: Thu, 15 Aug 2024 23:38:44 +0800 Subject: drivers: pwm: Add pwm-sunxi-enhance driver for h616 @@ -13,10 +13,10 @@ Subject: drivers: pwm: Add pwm-sunxi-enhance driver for h616 create mode 100644 drivers/pwm/pwm-sunxi-enhance.h diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig -index 0915c1e7df16..1f1ff7af5b5a 100644 +index 4731d5b90d7e..501ed6625ba1 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig -@@ -652,6 +652,15 @@ config PWM_SUN4I +@@ -662,6 +662,15 @@ config PWM_SUN4I To compile this driver as a module, choose M here: the module will be called pwm-sun4i. @@ -33,10 +33,10 @@ index 0915c1e7df16..1f1ff7af5b5a 100644 tristate "Sunplus PWM support" depends on ARCH_SUNPLUS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile -index 9081e0c0e9e0..b729ae59db56 100644 +index 539e0def3f82..5796264f77c1 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile -@@ -60,6 +60,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o +@@ -61,6 +61,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch index 393e43c..c51e1f9 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch @@ -1,4 +1,4 @@ -From 7209d2722c06641535136be81944a8f8304f344e Mon Sep 17 00:00:00 2001 +From eee7c362bf9f395eacfd8fd7f46890f178009a32 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Wed, 2 Feb 2022 19:34:55 +0300 Subject: drv:gpu:drm: panel-simple Add compability olinuxino lcd @@ -8,10 +8,10 @@ Subject: drv:gpu:drm: panel-simple Add compability olinuxino lcd 1 file changed, 121 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c -index cf9ab2d1f1d2..4ea9a1fe50de 100644 +index 33a37539de57..5e585fe5f553 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c -@@ -3551,6 +3551,42 @@ static const struct panel_desc okaya_rs800480t_7x0gp = { +@@ -3609,6 +3609,42 @@ static const struct panel_desc okaya_rs800480t_7x0gp = { .bus_format = MEDIA_BUS_FMT_RGB666_1X18, }; @@ -54,7 +54,7 @@ index cf9ab2d1f1d2..4ea9a1fe50de 100644 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { .clock = 9000, .hdisplay = 480, -@@ -3563,8 +3599,8 @@ static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { +@@ -3621,8 +3657,8 @@ static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { .vtotal = 272 + 8 + 5 + 3, }; @@ -65,7 +65,7 @@ index cf9ab2d1f1d2..4ea9a1fe50de 100644 .num_modes = 1, .size = { .width = 95, -@@ -3606,6 +3642,72 @@ static const struct panel_desc ontat_kd50g21_40nt_a1 = { +@@ -3664,6 +3700,72 @@ static const struct panel_desc ontat_kd50g21_40nt_a1 = { .connector_type = DRM_MODE_CONNECTOR_DPI, }; @@ -138,7 +138,7 @@ index cf9ab2d1f1d2..4ea9a1fe50de 100644 /* * 800x480 CVT. The panel appears to be quite accepting, at least as far as * pixel clocks, but this is the timing that was being used in the Adafruit -@@ -5067,8 +5169,23 @@ static const struct of_device_id platform_of_match[] = { +@@ -5131,8 +5233,23 @@ static const struct of_device_id platform_of_match[] = { .compatible = "okaya,rs800480t-7x0gp", .data = &okaya_rs800480t_7x0gp, }, { diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch index f9c3539..f4db710 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch @@ -1,4 +1,4 @@ -From e9c514407dd29d289792d6b84aa8da0b7a5cae8f Mon Sep 17 00:00:00 2001 +From 3fd0626269e403287f8697d223dd39e606f07c6b Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Tue, 1 Feb 2022 21:38:26 +0300 Subject: drv:mfd:axp20x add sysfs interface @@ -8,7 +8,7 @@ Subject: drv:mfd:axp20x add sysfs interface 1 file changed, 614 insertions(+) diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c -index 9be321c8aeae..3625cf1533c3 100644 +index f88a02913390..3eba9e152f1c 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -85,6 +85,7 @@ static const struct regmap_range axp20x_volatile_ranges[] = { @@ -19,7 +19,7 @@ index 9be321c8aeae..3625cf1533c3 100644 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L), }; -@@ -1300,6 +1301,611 @@ static int axp20x_power_off(struct sys_off_data *data) +@@ -1301,6 +1302,611 @@ static int axp20x_power_off(struct sys_off_data *data) return NOTIFY_DONE; } @@ -54,7 +54,7 @@ index 9be321c8aeae..3625cf1533c3 100644 + +static ssize_t axp20x_sysfs_read_bin_file(struct file *filp, + struct kobject *kobj, -+ struct bin_attribute *bin_attr, ++ const struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + int ret; @@ -73,7 +73,7 @@ index 9be321c8aeae..3625cf1533c3 100644 + +static ssize_t axp20x_sysfs_write_bin_file(struct file *filp, + struct kobject *kobj, -+ struct bin_attribute *bin_attr, ++ const struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + int ret; @@ -631,7 +631,7 @@ index 9be321c8aeae..3625cf1533c3 100644 int axp20x_match_device(struct axp20x_dev *axp20x) { struct device *dev = axp20x->dev; -@@ -1500,6 +2106,10 @@ int axp20x_device_probe(struct axp20x_dev *axp20x) +@@ -1501,6 +2107,10 @@ int axp20x_device_probe(struct axp20x_dev *axp20x) if (axp20x->variant != AXP288_ID) devm_register_power_off_handler(axp20x->dev, axp20x_power_off, axp20x); @@ -642,7 +642,7 @@ index 9be321c8aeae..3625cf1533c3 100644 dev_info(axp20x->dev, "AXP20X driver loaded\n"); return 0; -@@ -1508,6 +2118,10 @@ EXPORT_SYMBOL(axp20x_device_probe); +@@ -1509,6 +2119,10 @@ EXPORT_SYMBOL(axp20x_device_probe); void axp20x_device_remove(struct axp20x_dev *axp20x) { diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch similarity index 89% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch index a0c6418..3df37a7 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch @@ -18,24 +18,23 @@ Signed-off-by: Andre Przywara 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -index 111111111111..222222222222 100644 +index 699362e1a299..4b4c005cc39e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -1163,11 +1163,13 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) +@@ -1163,10 +1163,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) struct stmmac_resources stmmac_res; struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; + struct reg_field syscon_field; - phy_interface_t interface; - int ret; struct stmmac_priv *priv; struct net_device *ndev; struct regmap *regmap; + int ret; + u32 syscon_idx = 0; ret = stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) -@@ -1222,8 +1224,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) +@@ -1221,8 +1223,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) return ret; } @@ -50,7 +49,7 @@ index 111111111111..222222222222 100644 if (IS_ERR(gmac->regmap_field)) { ret = PTR_ERR(gmac->regmap_field); dev_err(dev, "Unable to map syscon register: %d\n", ret); -@@ -1348,6 +1354,8 @@ static const struct of_device_id sun8i_dwmac_match[] = { +@@ -1342,6 +1348,8 @@ static const struct of_device_id sun8i_dwmac_match[] = { .data = &emac_variant_a64 }, { .compatible = "allwinner,sun50i-h6-emac", .data = &emac_variant_h6 }, diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch similarity index 51% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch index 1635a39..cd39467 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch @@ -1,17 +1,17 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From f45c4632c0d5d25901f125ad80b245e5bdf50f7f Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Wed, 2 Feb 2022 14:16:31 +0300 Subject: drv:spi:spi-sun4i.c spi bug low on sck --- - drivers/spi/spi-sun4i.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) + drivers/spi/spi-sun4i.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c -index 111111111111..222222222222 100644 +index aa92fd5a35a9..9f3273256354 100644 --- a/drivers/spi/spi-sun4i.c +++ b/drivers/spi/spi-sun4i.c -@@ -390,6 +390,7 @@ static int sun4i_spi_runtime_resume(struct device *dev) +@@ -393,6 +393,7 @@ static int sun4i_spi_runtime_resume(struct device *dev) struct spi_controller *host = dev_get_drvdata(dev); struct sun4i_spi *sspi = spi_controller_get_devdata(host); int ret; @@ -19,18 +19,17 @@ index 111111111111..222222222222 100644 ret = clk_prepare_enable(sspi->hclk); if (ret) { -@@ -402,9 +403,10 @@ static int sun4i_spi_runtime_resume(struct device *dev) - dev_err(dev, "Couldn't enable module clock\n"); +@@ -406,8 +407,8 @@ static int sun4i_spi_runtime_resume(struct device *dev) goto err; } -+ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); - sun4i_spi_write(sspi, SUN4I_CTL_REG, -- SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP); -+ reg | SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP); +- sun4i_spi_write(sspi, SUN4I_CTL_REG, +- SUN4I_CTL_MASTER | SUN4I_CTL_TP); ++ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); ++ sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_MASTER | SUN4I_CTL_TP); return 0; -- -Armbian +2.35.3 diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch similarity index 87% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch index 2106cf3..e1cb91f 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch @@ -1,4 +1,4 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 36b50c879cbe1ac572e0c2c9dacc32f7405fd36e Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Wed, 2 Feb 2022 11:56:51 +0300 Subject: drv:spi:spidev Add armbian spi-dev compatible @@ -8,7 +8,7 @@ Subject: drv:spi:spidev Add armbian spi-dev compatible 1 file changed, 3 insertions(+) diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c -index 58ae4304fdab..c4c73a61a571 100644 +index 6108959c28d9..4f968069bd60 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -703,6 +703,7 @@ static const struct class spidev_class = { @@ -19,7 +19,7 @@ index 58ae4304fdab..c4c73a61a571 100644 { .name = /* cisco */ "spi-petra" }, { .name = /* dh */ "dhcom-board" }, { .name = /* elgin */ "jg10309-01" }, -@@ -730,10 +731,12 @@ static int spidev_of_check(struct device *dev) +@@ -731,10 +732,12 @@ static int spidev_of_check(struct device *dev) return 0; dev_err(dev, "spidev listed directly in DT is not supported\n"); @@ -33,5 +33,5 @@ index 58ae4304fdab..c4c73a61a571 100644 { .compatible = "dh,dhcom-board", .data = &spidev_of_check }, { .compatible = "elgin,jg10309-01", .data = &spidev_of_check }, -- -Armbian +2.35.3 diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch b/patch/kernel/sunxi-6.16/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch rename to patch/kernel/sunxi-6.16/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch b/patch/kernel/sunxi-6.16/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch rename to patch/kernel/sunxi-6.16/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch b/patch/kernel/sunxi-6.16/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch rename to patch/kernel/sunxi-6.16/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/h616-add-keys.patch b/patch/kernel/sunxi-6.16/patches.armbian/h616-add-keys.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/h616-add-keys.patch rename to patch/kernel/sunxi-6.16/patches.armbian/h616-add-keys.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch b/patch/kernel/sunxi-6.16/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch similarity index 83% rename from patch/kernel/sunxi-6.14/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch rename to patch/kernel/sunxi-6.16/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch index 6920a49..a641a65 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch @@ -1,4 +1,4 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 20c66d9e147b06cf8919c25582686ee2d70c6faf Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 19 Jun 2018 13:51:17 +0800 Subject: include:uapi:drm_fourcc: add ARM tiled format modifier @@ -11,10 +11,10 @@ Signed-off-by: The-going <48602507+The-going@users.noreply.github.com> 1 file changed, 9 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h -index 111111111111..222222222222 100644 +index e41a3cec6a9e..fcf65f89465d 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h -@@ -1349,6 +1349,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) +@@ -1350,6 +1350,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) */ #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) @@ -31,5 +31,5 @@ index 111111111111..222222222222 100644 * Arm 16x16 Block U-Interleaved modifier * -- -Armbian +2.35.3 diff --git a/patch/kernel/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch b/patch/kernel/sunxi-6.16/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch rename to patch/kernel/sunxi-6.16/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch b/patch/kernel/sunxi-6.16/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch rename to patch/kernel/sunxi-6.16/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch index 63b23ac..37b5b2e 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch @@ -1,4 +1,4 @@ -From 22de4391bc6b69c42ebf7c0a380e566d17810f0f Mon Sep 17 00:00:00 2001 +From 77b6d5f86a69c0e37612406ba6715c3040100271 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Fri, 16 Aug 2019 16:38:21 +0200 Subject: mfd: Add support for X-Powers AC200 @@ -31,7 +31,7 @@ Signed-off-by: Andre Przywara create mode 100644 drivers/mfd/ac200.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig -index ae23b317a64e..85f0eb5f764e 100644 +index 22b936310039..1f36768c18f8 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -203,6 +203,18 @@ config MFD_AC100 @@ -54,10 +54,10 @@ index ae23b317a64e..85f0eb5f764e 100644 tristate select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile -index e057d6d6faef..03244b2c7306 100644 +index 948cbdf42a18..63a5ba7b9f52 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile -@@ -146,6 +146,7 @@ obj-$(CONFIG_MFD_DA9052_SPI) += da9052-spi.o +@@ -145,6 +145,7 @@ obj-$(CONFIG_MFD_DA9052_SPI) += da9052-spi.o obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o obj-$(CONFIG_MFD_AC100) += ac100.o diff --git a/patch/kernel/sunxi-6.14/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch b/patch/kernel/sunxi-6.16/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch rename to patch/kernel/sunxi-6.16/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch b/patch/kernel/sunxi-6.16/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch rename to patch/kernel/sunxi-6.16/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch index 04d079c..3d98ab3 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch @@ -1,4 +1,4 @@ -From 9ea339d70cfa03d39fecfc3d980c758ed67c4639 Mon Sep 17 00:00:00 2001 +From 9918ef9dae0fce8d808c6583d50c37030afe6c85 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Fri, 16 Aug 2019 16:38:57 +0200 Subject: net: phy: Add support for AC200 EPHY @@ -21,7 +21,7 @@ Signed-off-by: Andre Przywara create mode 100644 drivers/net/phy/ac200-phy.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig -index 01b235b3bb7e..be4670e6b266 100644 +index d29f9f7fd2e1..51eb1f599b02 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -84,6 +84,13 @@ config AIR_EN8811H_PHY @@ -39,10 +39,10 @@ index 01b235b3bb7e..be4670e6b266 100644 tristate "AMD and Altima PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile -index 90f886844381..4bba8c64bcc9 100644 +index 23ce205ae91d..c2bdd0daf459 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -33,6 +33,7 @@ obj-$(CONFIG_SFP) += sfp.o +@@ -34,6 +34,7 @@ obj-$(CONFIG_SFP) += sfp.o sfp-obj-$(CONFIG_SFP) += sfp-bus.o obj-y += $(sfp-obj-y) $(sfp-obj-m) diff --git a/patch/kernel/sunxi-6.14/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch b/patch/kernel/sunxi-6.16/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch rename to patch/kernel/sunxi-6.16/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch b/patch/kernel/sunxi-6.16/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch rename to patch/kernel/sunxi-6.16/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/scripts-add-overlay-compilation-support.patch b/patch/kernel/sunxi-6.16/patches.armbian/scripts-add-overlay-compilation-support.patch similarity index 90% rename from patch/kernel/sunxi-6.14/patches.armbian/scripts-add-overlay-compilation-support.patch rename to patch/kernel/sunxi-6.16/patches.armbian/scripts-add-overlay-compilation-support.patch index 1d71a34..ad95c89 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/scripts-add-overlay-compilation-support.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/scripts-add-overlay-compilation-support.patch @@ -1,4 +1,4 @@ -From 2be34e5c09556a6c5304b36c03c5616856fdf73e Mon Sep 17 00:00:00 2001 +From f6bb6d63007c958316169fd47a34c4d7362bcd16 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Tue, 1 Feb 2022 21:04:08 +0300 Subject: scripts: add overlay compilation support @@ -10,7 +10,7 @@ Subject: scripts: add overlay compilation support 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore -index 5937c74d3dc1..3a2bea98567d 100644 +index f2f63e47fb88..3b0f8aab0d1d 100644 --- a/.gitignore +++ b/.gitignore @@ -44,6 +44,7 @@ @@ -52,10 +52,10 @@ index 9d920419a62c..dc0c8da28494 100644 endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib -index cad20f0e66ee..2d8b0b41d5f0 100644 +index 2fe73cda0bdd..cfb29d02030b 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib -@@ -75,6 +75,9 @@ always-y += $(hostprogs-always-y) $(hostprogs-always-m) +@@ -70,6 +70,9 @@ always-y += $(hostprogs-always-y) $(hostprogs-always-m) userprogs += $(userprogs-always-y) $(userprogs-always-m) always-y += $(userprogs-always-y) $(userprogs-always-m) @@ -65,7 +65,7 @@ index cad20f0e66ee..2d8b0b41d5f0 100644 # Add subdir path ifneq ($(obj),.) -@@ -436,6 +439,15 @@ quiet_cmd_lz4_with_size = LZ4 $@ +@@ -429,6 +432,15 @@ quiet_cmd_lz4_with_size = LZ4 $@ cmd_lz4_with_size = { cat $(real-prereqs) | $(LZ4) -l -9 - -; \ $(size_append); } > $@ diff --git a/patch/kernel/sunxi-6.14/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch b/patch/kernel/sunxi-6.16/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch rename to patch/kernel/sunxi-6.16/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch b/patch/kernel/sunxi-6.16/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch similarity index 90% rename from patch/kernel/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch rename to patch/kernel/sunxi-6.16/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch index 4d4a87b..954554a 100644 --- a/patch/kernel/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch +++ b/patch/kernel/sunxi-6.16/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch @@ -1,4 +1,4 @@ -From 98c6b31384477c771ba47a5f34384d0b8c7dcfc4 Mon Sep 17 00:00:00 2001 +From d15c101660339e266a7a3548aaea04a48f2fa108 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Wed, 2 Feb 2022 21:42:37 +0300 Subject: sound:soc:sunxi:sun4i-codec adcis select capture source @@ -8,7 +8,7 @@ Subject: sound:soc:sunxi:sun4i-codec adcis select capture source 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c -index 886b3fa537d2..5b67e2905a44 100644 +index 93733ff2e32a..3b90d54ab9f9 100644 --- a/sound/soc/sunxi/sun4i-codec.c +++ b/sound/soc/sunxi/sun4i-codec.c @@ -6,6 +6,7 @@ @@ -19,7 +19,7 @@ index 886b3fa537d2..5b67e2905a44 100644 * * Based on the Allwinner SDK driver, released under the GPL. */ -@@ -743,6 +744,16 @@ static struct snd_soc_dai_driver sun4i_codec_dai = { +@@ -745,6 +746,16 @@ static struct snd_soc_dai_driver sun4i_codec_dai = { }; /*** sun4i Codec ***/ @@ -36,7 +36,7 @@ index 886b3fa537d2..5b67e2905a44 100644 static const struct snd_kcontrol_new sun4i_codec_pa_mute = SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL, SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0); -@@ -756,6 +767,8 @@ static DECLARE_TLV_DB_SCALE(sun4i_codec_fmin_loopback_gain_scale, -450, 150, +@@ -758,6 +769,8 @@ static DECLARE_TLV_DB_SCALE(sun4i_codec_fmin_loopback_gain_scale, -450, 150, 0); static DECLARE_TLV_DB_SCALE(sun4i_codec_micin_loopback_gain_scale, -450, 150, 0); @@ -45,7 +45,7 @@ index 886b3fa537d2..5b67e2905a44 100644 static DECLARE_TLV_DB_RANGE(sun4i_codec_micin_preamp_gain_scale, 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 1, 7, TLV_DB_SCALE_ITEM(3500, 300, 0)); -@@ -809,6 +822,9 @@ static const struct snd_kcontrol_new sun7i_codec_controls[] = { +@@ -811,6 +824,9 @@ static const struct snd_kcontrol_new sun7i_codec_controls[] = { SOC_SINGLE_TLV("Mic2 Boost Volume", SUN7I_CODEC_AC_MIC_PHONE_CAL, SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG2, 7, 0, sun7i_codec_micin_preamp_gain_scale), @@ -55,7 +55,7 @@ index 886b3fa537d2..5b67e2905a44 100644 }; static const struct snd_kcontrol_new sun4i_codec_mixer_controls[] = { -@@ -887,6 +903,13 @@ static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = { +@@ -889,6 +905,13 @@ static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = { SND_SOC_DAPM_PGA("MIC2 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL, SUN4I_CODEC_ADC_ACTL_PREG2EN, 0, NULL, 0), @@ -69,7 +69,7 @@ index 886b3fa537d2..5b67e2905a44 100644 /* Power Amplifier */ SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL, SUN4I_CODEC_ADC_ACTL_PA_EN, 0, -@@ -915,6 +938,30 @@ static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = { +@@ -917,6 +940,30 @@ static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = { { "Right ADC", NULL, "ADC" }, { "Right DAC", NULL, "DAC" }, @@ -100,7 +100,7 @@ index 886b3fa537d2..5b67e2905a44 100644 /* Right Mixer Routes */ { "Right Mixer", NULL, "Mixer Enable" }, { "Right Mixer", "Right Mixer Left DAC Playback Switch", "Left DAC" }, -@@ -944,14 +991,10 @@ static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = { +@@ -946,14 +993,10 @@ static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = { { "HP Left", NULL, "Power Amplifier Mute" }, /* Mic1 Routes */ diff --git a/patch/kernel/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch b/patch/kernel/sunxi-6.16/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch rename to patch/kernel/sunxi-6.16/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch diff --git a/patch/kernel/sunxi-6.14/patches.armbian/sun50i-h616-Add-the-missing-digital-audio-node.patch b/patch/kernel/sunxi-6.16/patches.armbian/sun50i-h616-Add-the-missing-digital-audio-node.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.armbian/sun50i-h616-Add-the-missing-digital-audio-node.patch rename to patch/kernel/sunxi-6.16/patches.armbian/sun50i-h616-Add-the-missing-digital-audio-node.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch b/patch/kernel/sunxi-6.16/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch rename to patch/kernel/sunxi-6.16/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch b/patch/kernel/sunxi-6.16/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch rename to patch/kernel/sunxi-6.16/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/sunxi-6.16/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch rename to patch/kernel/sunxi-6.16/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-panfrost-add-h616-compatible-string.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-panfrost-add-h616-compatible-string.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-panfrost-add-h616-compatible-string.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-panfrost-add-h616-compatible-string.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch b/patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch rename to patch/kernel/sunxi-6.16/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch b/patch/kernel/sunxi-6.16/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch rename to patch/kernel/sunxi-6.16/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch b/patch/kernel/sunxi-6.16/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch rename to patch/kernel/sunxi-6.16/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch b/patch/kernel/sunxi-6.16/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch rename to patch/kernel/sunxi-6.16/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch b/patch/kernel/sunxi-6.16/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch rename to patch/kernel/sunxi-6.16/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch diff --git a/patch/kernel/sunxi-6.14/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch b/patch/kernel/sunxi-6.16/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch rename to patch/kernel/sunxi-6.16/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch diff --git a/patch/kernel/sunxi-6.14/patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch b/patch/kernel/sunxi-6.16/patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch similarity index 89% rename from patch/kernel/sunxi-6.14/patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch rename to patch/kernel/sunxi-6.16/patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch index ffedd6b..477a21f 100644 --- a/patch/kernel/sunxi-6.14/patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch +++ b/patch/kernel/sunxi-6.16/patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch @@ -1,4 +1,4 @@ -From f4671b6d4842701e71b6a1ba6a93fbfb9dabb188 Mon Sep 17 00:00:00 2001 +From 672717a70d3fa52c55aa222a011d27dff2756787 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Mon, 7 Apr 2025 21:32:25 +0300 Subject: dma: sun6i-dma: add sun50i-h616 support @@ -8,10 +8,10 @@ Subject: dma: sun6i-dma: add sun50i-h616 support 1 file changed, 23 insertions(+) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c -index 95ecb12caaa5..ae2b5509b5b4 100644 +index 2215ff877bf7..44b7b87ebea9 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c -@@ -1243,6 +1243,28 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { +@@ -1244,6 +1244,28 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { .has_mbus_clk = true, }; @@ -40,7 +40,7 @@ index 95ecb12caaa5..ae2b5509b5b4 100644 /* * The V3s have only 8 physical channels, a maximum DRQ port id of 23, * and a total of 24 usable source and destination endpoints. -@@ -1276,6 +1298,7 @@ static const struct of_device_id sun6i_dma_match[] = { +@@ -1277,6 +1299,7 @@ static const struct of_device_id sun6i_dma_match[] = { { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, { .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg }, { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg }, diff --git a/patch/kernel/sunxi-6.14/patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch b/patch/kernel/sunxi-6.16/patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch similarity index 91% rename from patch/kernel/sunxi-6.14/patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch rename to patch/kernel/sunxi-6.16/patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch index 113377c..294e63a 100644 --- a/patch/kernel/sunxi-6.14/patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch +++ b/patch/kernel/sunxi-6.16/patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch @@ -1,4 +1,4 @@ -From eae101ec576943cc34c4718b360bbe6091792e8b Mon Sep 17 00:00:00 2001 +From 0cd01ea9c529324c17a0fb4f3269c61385802fc2 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 7 Oct 2023 09:43:35 +0200 Subject: media: Add NV12 and P010 AFBC compressed formats @@ -13,10 +13,10 @@ Signed-off-by: Jernej Skrabec 2 files changed, 6 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 0304daa8471d..6c7f3abb4959 100644 +index a16fb44c7246..ef5d3f75c901 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1546,6 +1546,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) +@@ -1548,6 +1548,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_PISP_COMP2_GBRG: descr = "PiSP 8b GBGB/RGRG mode2 compr"; break; case V4L2_PIX_FMT_PISP_COMP2_BGGR: descr = "PiSP 8b BGBG/GRGR mode2 compr"; break; case V4L2_PIX_FMT_PISP_COMP2_MONO: descr = "PiSP 8b monochrome mode2 compr"; break; @@ -26,7 +26,7 @@ index 0304daa8471d..6c7f3abb4959 100644 if (fmt->description[0]) return; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index e7c4dce39007..8d423df66f61 100644 +index c8cb2796130f..810dbc73ff88 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -688,6 +688,10 @@ struct v4l2_pix_format { diff --git a/patch/kernel/sunxi-6.14/patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch b/patch/kernel/sunxi-6.16/patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch rename to patch/kernel/sunxi-6.16/patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch diff --git a/patch/kernel/sunxi-6.14/patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch b/patch/kernel/sunxi-6.16/patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch rename to patch/kernel/sunxi-6.16/patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch diff --git a/patch/kernel/sunxi-6.14/patches.media/media-cedrus-Increase-H6-clock-rate.patch b/patch/kernel/sunxi-6.16/patches.media/media-cedrus-Increase-H6-clock-rate.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.media/media-cedrus-Increase-H6-clock-rate.patch rename to patch/kernel/sunxi-6.16/patches.media/media-cedrus-Increase-H6-clock-rate.patch diff --git a/patch/kernel/sunxi-6.14/patches.media/media-cedrus-add-format-filtering-based-on-depth-and-src-format.patch b/patch/kernel/sunxi-6.16/patches.media/media-cedrus-add-format-filtering-based-on-depth-and-src-format.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.media/media-cedrus-add-format-filtering-based-on-depth-and-src-format.patch rename to patch/kernel/sunxi-6.16/patches.media/media-cedrus-add-format-filtering-based-on-depth-and-src-format.patch diff --git a/patch/kernel/sunxi-6.14/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch b/patch/kernel/sunxi-6.16/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch rename to patch/kernel/sunxi-6.16/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch index d66e295..2fc39de 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch @@ -1,4 +1,4 @@ -From 63ede72498fdb55584228f62a27c7564a9bd3289 Mon Sep 17 00:00:00 2001 +From 9ecee787050f6d98d07039ca5d5b1f5aa41492dc Mon Sep 17 00:00:00 2001 From: Arnav Singh Date: Mon, 6 May 2024 16:36:06 -0700 Subject: arm64: dts: sun50i: Define orientation and rotation for PinePhone diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-axp813-Add-charger-LED.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-axp813-Add-charger-LED.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-axp813-Add-charger-LED.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-axp813-Add-charger-LED.patch index c86157b..362da00 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-axp813-Add-charger-LED.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-axp813-Add-charger-LED.patch @@ -1,4 +1,4 @@ -From 6f7050f399283cdef2e0a1598a41279fb1d2ab01 Mon Sep 17 00:00:00 2001 +From d477668c4266ba1d4217b6c88561cae33b1fe3a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 14 Nov 2017 02:47:51 +0100 Subject: ARM: dts: axp813: Add charger LED diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch index 7738192..cf20d34 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch @@ -1,4 +1,4 @@ -From 1fdeabb9597a51122d1c07678c6dd94c15e40abf Mon Sep 17 00:00:00 2001 +From a1d3e85d015e5d6ab32048389c2d6bf0113d2bf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 23 Feb 2020 01:23:10 +0100 Subject: ARM: dts: sun5i: Add PocketBook Touch Lux 3 display/ctp support diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch similarity index 91% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch index 6476558..7c28e1c 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch @@ -1,4 +1,4 @@ -From 87c27d42818037b43a49d67edc1d2de68036d1af Mon Sep 17 00:00:00 2001 +From 71893478173cf32fa036959bd394153e061f9b79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 5 Oct 2019 15:04:43 +0200 Subject: ARM: dts: sun5i: Add soc handle diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch index 8dec8d9..1999de4 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch @@ -1,4 +1,4 @@ -From 7cd038980cc2a9a28a5d908f8c66a4a2c92ad36b Mon Sep 17 00:00:00 2001 +From 16cfba8cce4eacacf4bd1ad59c4ee99371590ce2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Thu, 25 Jun 2020 01:57:27 +0200 Subject: ARM: dts: sun5i-a13-pocketbook-touch-lux-3: Add RTC clock-cells diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch index c1428e0..5625be3 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch @@ -1,4 +1,4 @@ -From 671a2d6f20ba155cfcadf114e6d740936ee7088a Mon Sep 17 00:00:00 2001 +From 47c541391b7ecb5a63abeb30ef692461a43259fd Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 3 Apr 2021 20:53:26 -0500 Subject: ARM: dts: sun8i: a83t: Add MBUS node diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch index 6c111c2..939a15d 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch @@ -1,4 +1,4 @@ -From 01a3291530c88353c36fb80d55ce984363614c28 Mon Sep 17 00:00:00 2001 +From 4785f332e290fe61cb5b9325070a61f3ea5c5bf4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 9 Sep 2019 06:02:10 +0200 Subject: ARM: dts: sun8i-a83t: Add cedrus video codec support to A83T diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch index be6abc7..3f15769 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch @@ -1,4 +1,4 @@ -From bcee56858d98fe3523d52de0f6f1dd2750ee7c77 Mon Sep 17 00:00:00 2001 +From 06469f71a58b1be8a85e600a6096bb5470834beb Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 11:32:57 +0200 Subject: ARM: dts: sun8i: a83t: Add hdmi sound card diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch index 16e9783..a6dbb45 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch @@ -1,4 +1,4 @@ -From 79b5366ae1cedac8596a6188275c25db406c6f1f Mon Sep 17 00:00:00 2001 +From 7654f1f337bc35204b8e93569ec908c30a34bd78 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 13 Mar 2023 06:02:27 +0100 Subject: ARM: dts: sun8i-a83t: Add missing GPU trip point diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch index 8ae870f..0dfd9f7 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch @@ -1,4 +1,4 @@ -From e82fb342a69f47923f2e504b7e7e2fff952dac98 Mon Sep 17 00:00:00 2001 +From f925c47e6a482396f7532852d77f6a35c2cac8ef Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 11:34:43 +0200 Subject: ARM: dts: sun8i: a83t: Enable hdmi sound card on boards with hdmi diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch index aa6c75d..9a33454 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch @@ -1,4 +1,4 @@ -From 5968a3853998a21a9c2dd8aa2e4efc3a16e7ccfb Mon Sep 17 00:00:00 2001 +From b6156e61c002935057478c88a5d5d6d8b92a5444 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 1 Sep 2019 23:56:49 +0200 Subject: ARM: dts: sun8i-a83t: Improve CPU OPP tables (go up to 1.8GHz) diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch index 425121a..4c66e72 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch @@ -1,4 +1,4 @@ -From 1343ffd6e889e9f9ddfe35f87c6b9bd5006a9a49 Mon Sep 17 00:00:00 2001 +From 710b6e16f1c305c5ac59b1beb66ff5a079ad4772 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 1 Feb 2020 23:41:47 +0100 Subject: ARM: dts: sun8i-a83t: Set fifo-size for uarts diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch index 81ad7ed..019c44e 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch @@ -1,4 +1,4 @@ -From af628e240ad757d9fc0258f2d64165ade363cd86 Mon Sep 17 00:00:00 2001 +From 51f847df35b1bfee8665af1136c7cb6fb6858a7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Fri, 10 Nov 2017 14:33:28 +0100 Subject: ARM: dts: sun8i-a83t-tbs-a711: Add PN544 NFC support diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch index c004005..76dc180 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch @@ -1,4 +1,4 @@ -From 6b05b5d01cedf65ba4a82cd08ad552eb26817e9e Mon Sep 17 00:00:00 2001 +From 4dbc4506213f44456ff65336f5f7681aa0bfa6ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 23 Jun 2020 19:43:24 +0200 Subject: ARM: dts: sun8i-a83t-tbs-a711: Add camera sensors (HM5065, GC2145) diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch index a620e0b..9f5b0cf 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch @@ -1,4 +1,4 @@ -From f5ba77da4d5a3374ade9ce2c9a98697724e2f418 Mon Sep 17 00:00:00 2001 +From 625f242d2b7c3ddb7ccca4759ba6b756553b05e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 8 Nov 2017 21:57:45 +0100 Subject: ARM: dts: sun8i-a83t-tbs-a711: Add flash led support diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch index 79bd2f0..e6db9b5 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch @@ -1,4 +1,4 @@ -From 0da088ce86e596f4d2bdff7c255cc579579be341 Mon Sep 17 00:00:00 2001 +From 237bad66d7afb2e48e6edb32b83aa7642e9741af Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= Date: Thu, 6 Jul 2017 10:57:55 +0200 diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch index 7590fd5..0eb6488 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch @@ -1,4 +1,4 @@ -From 3388c7e4f1d60f11b0377cfe30d0bfaaa20183ba Mon Sep 17 00:00:00 2001 +From bec707061b0b6833cef484132c43d4a1247647a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 23 Jun 2020 19:15:37 +0200 Subject: ARM: dts: sun8i-a83t-tbs-a711: Add regulators to the accelerometer diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch index 4f8b75f..4668366 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch @@ -1,4 +1,4 @@ -From 06bc6b6ae01fd5e2e9cdc570581b5795cc7cd019 Mon Sep 17 00:00:00 2001 +From 5a64c0ebed2f55c83bd5b89f0b0a4252d887ff6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 22 Feb 2020 23:40:29 +0100 Subject: ARM: dts: sun8i-a83t-tbs-a711: Add sound support via AC100 codec diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch index 2edc3c8..9b86f6b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch @@ -1,4 +1,4 @@ -From 9b8f0e47429380b0d58597e2581abfe86d04f1e7 Mon Sep 17 00:00:00 2001 +From 2d3b3a3e3a5ba90a4667111bf37edd5cd28fe4ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 9 Nov 2019 23:55:48 +0100 Subject: ARM: dts: sun8i-a83t-tbs-a711: Add support for the vibrator motor diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch index b74a76c..f77f7b0 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch @@ -1,4 +1,4 @@ -From c099653062731dfb0f13e60373a890b7ba88c149 Mon Sep 17 00:00:00 2001 +From 7e323391c3eb86e861f8778d68fdc4e5cb917f99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 23 Feb 2020 13:21:58 +0100 Subject: ARM: dts: sun8i-a83t-tbs-a711: Enable charging LED diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch index 1b9c826..5a66223 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch @@ -1,4 +1,4 @@ -From fd7b0ea1f64ea844570ebcb802cb2a4934414fba Mon Sep 17 00:00:00 2001 +From 251853329b28a34715f833e07112fb07b28b03b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 23 Jun 2020 19:19:46 +0200 Subject: ARM: dts: sun8i-a83t-tbs-a711: Give Linux more privileges over SCPI diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch index 1be57b5..d4d6551 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch @@ -1,4 +1,4 @@ -From 7bf0e248c3dbd81edf1482bfebe5e99e0c8d30e2 Mon Sep 17 00:00:00 2001 +From 82f3e01b5525d8d97e8e9c437b0792b1cb4e116e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Fri, 8 Dec 2017 12:44:22 +0100 Subject: ARM: dts: sun8i-a83t-tbs-a711: Increase voltage on the vibrator diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch index e95ddef..d21b70f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch @@ -1,4 +1,4 @@ -From 4a04f862d0a85d8aac6e3bbd698c1a40bad66059 Mon Sep 17 00:00:00 2001 +From 298f7fd96e1cfea08de1215d985caef39b3eb884 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 11:14:51 +0200 Subject: ARM: dts: sun8i: h2-plus: bananapi-m2-zero: Enable HDMI audio diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch index 7f5c11d..9620075 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch @@ -1,4 +1,4 @@ -From e01f6a6ca5c4883ee5afbfa1eeaf9aa6c53e058b Mon Sep 17 00:00:00 2001 +From d84bf4adb0c0744ddbc7952a9cdab9b26650910d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 11:06:37 +0200 Subject: ARM: dts: sun8i: h3: Enable hdmi sound card on boards with hdmi diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch index 99f0ac9..c3041ec 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch @@ -1,4 +1,4 @@ -From 3b5ba528f3dee489d2a4d789c2e1dc83af43273e Mon Sep 17 00:00:00 2001 +From 022df214eb884c51a1e216d0a6efcfd144c243d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 17 Aug 2020 23:43:53 +0200 Subject: ARM: dts: sun8i-h3: Use my own more aggressive OPPs on H3 diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch index 3aec343..150de63 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch @@ -1,4 +1,4 @@ -From 230f694a6df3aad6214f652209d03b381999b4ac Mon Sep 17 00:00:00 2001 +From 2b22f37887782b93303499c51636d4c577f040b9 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 2 Apr 2022 02:24:26 +0200 Subject: ARM: dts: sun8i-h3-orange-pi-one: Enable all gpio header UARTs diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch index 0b8effe..6e3b30c 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch @@ -1,4 +1,4 @@ -From 6f11d654b5650b8563abeab166342c07899d4f39 Mon Sep 17 00:00:00 2001 +From 0c51a487e26615a4163a592d621e43798380e450 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 13 May 2018 21:00:43 +0200 Subject: ARM: dts: sun8i-h3-orange-pi-pc: Increase max CPUX voltage to 1.4V diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch index c86ced5..ee2d425 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch @@ -1,4 +1,4 @@ -From 453f3a74fadd774b213e9e99d7512f382f5ce2ca Mon Sep 17 00:00:00 2001 +From 9b64dc08bdd61c00b3fd45a905f5c573468818dc Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 11:50:56 +0200 Subject: ARM: dts: sun8i: r40: Add hdmi sound card diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch index c041094..55080c1 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch @@ -1,4 +1,4 @@ -From 9f7f66239ad389f9b77720ef467ba7d2225868b3 Mon Sep 17 00:00:00 2001 +From 618a27352b9f90f46de1f8a224ba4df915f7ce51 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 11:52:43 +0200 Subject: ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable HDMI audio diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch index e705752..360dbdb 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch @@ -1,4 +1,4 @@ -From c60e834e1aae8950464e736acaa2177b3497b307 Mon Sep 17 00:00:00 2001 +From 603832d7464d19cc29993b47f8a0684efedf1c86 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 12:00:46 +0200 Subject: ARM: dts: sun8i: v40: bananapi-m2-berry: Enable HDMI audio diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch index c7b5108..031b8a3 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch @@ -1,4 +1,4 @@ -From 95bfb93adb3ec8a52d09dc47bb16f5b0c6d74382 Mon Sep 17 00:00:00 2001 +From cff9d0cb6c3dd4ef8509c5f82bb4426e778e3e1e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 12 Nov 2017 19:03:39 +0100 Subject: ARM: dts: suni-a83t: Add i2s0 pins diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch index a3c58ae..e0ce708 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch @@ -1,4 +1,4 @@ -From 499d97a0f3f21070604d41562e7c376ccfb9c192 Mon Sep 17 00:00:00 2001 +From 0e04cf5c735f653e0ffe79b81df83f351e7ed0ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 25 Jan 2021 01:15:58 +0100 Subject: ARM: dts: sunxi: Add aliases for MMC diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch index 16e1599..1ff7b66 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch @@ -1,4 +1,4 @@ -From 2f243bf529a9e369b05118e64cd1553a0112f9d0 Mon Sep 17 00:00:00 2001 +From 1ba505b8d89073c8a669117e1d8edde1d1b77781 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 1 Jan 2020 16:14:29 -0600 Subject: ARM: dts: sunxi: a83t: Add SCPI protocol diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch index 594b982..150b416 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch @@ -1,4 +1,4 @@ -From f8e5ffe17a72e7fb942255154f5c9ff6f8b4a6bc Mon Sep 17 00:00:00 2001 +From 94fe8f725399e440902beef685698d208ea2db60 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 1 Jan 2020 16:12:36 -0600 Subject: ARM: dts: sunxi: h3/h5: Add SCPI protocol diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch index 23ce3e3..b9be967 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch @@ -1,4 +1,4 @@ -From 797e9a51924977c4a8ed90d9f4c5c2af75c97dda Mon Sep 17 00:00:00 2001 +From 8e4fd4e3d442940f48aefc15e045bac3fef49a58 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 11:04:58 +0200 Subject: ARM: dts: sunxi: h3/h5: Add hdmi sound card diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch index f3407c7..90f73b7 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch @@ -1,4 +1,4 @@ -From 64d4474e732197bc47adf374dd1dcf6bb24840e2 Mon Sep 17 00:00:00 2001 +From 88d7c5ca168472cfe5a832f6a4a26087a1c072ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 23 Oct 2019 05:06:29 +0200 Subject: ARM: sunxi: Add experimental suspend to memory implementation for diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch index f35af20..15b6329 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch @@ -1,4 +1,4 @@ -From 2c268237b942725705a5de8365c4142d45a346b5 Mon Sep 17 00:00:00 2001 +From 93027a00be9d72c542a88add7ddf4db67597a0cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 2 Nov 2019 15:21:04 +0100 Subject: ARM: sunxi: Use SCPI to send suspend message to SCP on A83T diff --git a/patch/kernel/sunxi-6.14/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch b/patch/kernel/sunxi-6.16/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch rename to patch/kernel/sunxi-6.16/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch index cd6627c..c191d89 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch @@ -1,4 +1,4 @@ -From 6410bf1e86927b02deae0fe3ddb51d41347f555b Mon Sep 17 00:00:00 2001 +From 5fe3f91dfdec69e6e4f287fa3240a8baf9dfbcbb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 23 Oct 2019 05:08:04 +0200 Subject: ARM: sunxi: sunxi_cpu0_hotplug_support_set is not supported on A83T diff --git a/patch/kernel/sunxi-6.14/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch b/patch/kernel/sunxi-6.16/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch rename to patch/kernel/sunxi-6.16/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch index d9898d8..80ca685 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch @@ -1,4 +1,4 @@ -From 0ab708fedde7fb0c6a3246c34cdc4490d7ce232a Mon Sep 17 00:00:00 2001 +From c996ffd1064a7e72b072b770e9b5709124ad5664 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 10 Nov 2020 20:42:44 +0100 Subject: ASOC: sun9i-hdmi-audio: Initial implementation @@ -46,7 +46,7 @@ index 6131aea97efa..19800277105c 100644 +obj-$(CONFIG_SND_SUN9I_HDMI_AUDIO) += sun9i-hdmi-audio.o diff --git a/sound/soc/sunxi/sun9i-hdmi-audio.c b/sound/soc/sunxi/sun9i-hdmi-audio.c new file mode 100644 -index 000000000000..32eb6d9decd3 +index 000000000000..d64b208d6f03 --- /dev/null +++ b/sound/soc/sunxi/sun9i-hdmi-audio.c @@ -0,0 +1,178 @@ @@ -177,7 +177,7 @@ index 000000000000..32eb6d9decd3 + link->name = "SUN9I-HDMI"; + link->stream_name = "SUN9I-HDMI PCM"; + -+ link->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_CBS_CFS; ++ link->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_CBC_CFC; + + link->ops = &sun9i_hdmi_audio_ops; + link->init = sun9i_hdmi_audio_dai_init; diff --git a/patch/kernel/sunxi-6.14/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch b/patch/kernel/sunxi-6.16/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch rename to patch/kernel/sunxi-6.16/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch index 33d8756..c486fef 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch @@ -1,4 +1,4 @@ -From c177a5ac1125f4c9a29db6884ac3f4d081cf1bbb Mon Sep 17 00:00:00 2001 +From 1e778ac5467969a21a0fc896ddf5ccf4603bb361 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 25 Sep 2020 21:42:52 -0500 Subject: ASoC: ec25: New codec driver for the EC25 modem @@ -16,10 +16,10 @@ Signed-off-by: Samuel Holland create mode 100644 sound/soc/codecs/ec25.c diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig -index 0138cfabbb03..211e77d7d64f 100644 +index 20f99cbee29b..b1133b34efbd 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig -@@ -1147,6 +1147,9 @@ config SND_SOC_HDMI_CODEC +@@ -1160,6 +1160,9 @@ config SND_SOC_HDMI_CODEC select SND_PCM_IEC958 select HDMI @@ -30,10 +30,10 @@ index 0138cfabbb03..211e77d7d64f 100644 tristate "Everest Semi ES7134 CODEC" diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile -index d7ad795603c1..7e12f3ae4f7d 100644 +index 10f726066b6c..0f4d541fc619 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile -@@ -122,6 +122,7 @@ snd-soc-da7219-y := da7219.o da7219-aad.o +@@ -123,6 +123,7 @@ snd-soc-da7219-y := da7219.o da7219-aad.o snd-soc-da732x-y := da732x.o snd-soc-da9055-y := da9055.o snd-soc-dmic-y := dmic.o @@ -41,7 +41,7 @@ index d7ad795603c1..7e12f3ae4f7d 100644 snd-soc-es7134-y := es7134.o snd-soc-es7241-y := es7241.o snd-soc-es83xx-dsm-common-y := es83xx-dsm-common.o -@@ -539,6 +540,7 @@ obj-$(CONFIG_SND_SOC_DA7219) += snd-soc-da7219.o +@@ -541,6 +542,7 @@ obj-$(CONFIG_SND_SOC_DA7219) += snd-soc-da7219.o obj-$(CONFIG_SND_SOC_DA732X) += snd-soc-da732x.o obj-$(CONFIG_SND_SOC_DA9055) += snd-soc-da9055.o obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o diff --git a/patch/kernel/sunxi-6.14/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch b/patch/kernel/sunxi-6.16/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch rename to patch/kernel/sunxi-6.16/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch index 415f1f5..ecbbda5 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch @@ -1,4 +1,4 @@ -From 60f86341890692981eed6c4c538b46d41788ce56 Mon Sep 17 00:00:00 2001 +From 9813b3e7ab2f35cdacb902a4776c420e3564dfae Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 14 May 2024 10:46:10 +0200 Subject: ASoC: simple-card: Allow to define pins for aux jack devices @@ -12,10 +12,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 40 insertions(+) diff --git a/sound/soc/generic/simple-card-utils.c b/sound/soc/generic/simple-card-utils.c -index 32efb30c55d6..7df92e045c5c 100644 +index 3ae2a212a2e3..e51e88b2ad62 100644 --- a/sound/soc/generic/simple-card-utils.c +++ b/sound/soc/generic/simple-card-utils.c -@@ -852,6 +852,46 @@ int simple_util_init_aux_jacks(struct simple_util_priv *priv, char *prefix) +@@ -879,6 +879,46 @@ int simple_util_init_aux_jacks(struct simple_util_priv *priv, char *prefix) continue; (void)snd_soc_component_set_jack(component, jack, NULL); diff --git a/patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch b/patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch rename to patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch index b5958b5..3d50d9a 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch @@ -1,4 +1,4 @@ -From 5ceac3477d9df0651a27ac60f88c8d67f516d60b Mon Sep 17 00:00:00 2001 +From 348696cd53ac362eb6bdd4e697852b006b324a80 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 17 Feb 2024 01:13:39 +0100 Subject: ASoC: sun8i-codec: Add debug output for jack detection @@ -9,7 +9,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c -index c5948b650777..6a9e147a6a1b 100644 +index 133165ca60f0..f96fc3bb4108 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -9,6 +9,8 @@ diff --git a/patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch b/patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch rename to patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch index c78992b..c9300aa 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch @@ -1,4 +1,4 @@ -From 6badb648bf732dd8480424ab5ddbeb0f1c9736a8 Mon Sep 17 00:00:00 2001 +From 710dfc2a31b54621aab6c56508b2c3a8a89d1871 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 2 Mar 2024 14:55:31 +0100 Subject: ASoC: sun8i-codec: Allow the jack type to be set via device tree @@ -12,7 +12,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 13 insertions(+) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c -index 8c645e04d571..838880cf5bd4 100644 +index 8b9eb1a202f7..4f44f35819e2 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -1563,6 +1563,18 @@ static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component) diff --git a/patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch b/patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch rename to patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch index 0890c58..b2d198e 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch @@ -1,4 +1,4 @@ -From bcd4fc8b4628893abdc7738afb815887ac8951d5 Mon Sep 17 00:00:00 2001 +From 2f91c9642f26aa4da3c1bfb967e2dee49f772f21 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 26 Mar 2024 17:38:38 +0100 Subject: ASoC: sun8i-codec: Set jack_type from DT in probe @@ -11,7 +11,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c -index 6a9e147a6a1b..b195ddc5d5cf 100644 +index f96fc3bb4108..9d28c675fb69 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -1602,14 +1602,9 @@ static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component) diff --git a/patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch b/patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch similarity index 89% rename from patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch rename to patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch index 0abda11..b07a020 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch @@ -1,4 +1,4 @@ -From 14100a8e3e83aeb304a3f136eb5aad44b7026feb Mon Sep 17 00:00:00 2001 +From 996eefe4372447c4622414c225833ad29b80a6ff Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 23 Feb 2024 01:58:40 +0100 Subject: ASoC: sun8i-codec: define button keycodes @@ -9,7 +9,7 @@ This is likely not upstreamable, but simple. :) 1 file changed, 7 insertions(+) diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c -index 838880cf5bd4..c5948b650777 100644 +index 4f44f35819e2..133165ca60f0 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -1541,6 +1541,13 @@ static int sun8i_codec_enable_jack_detect(struct snd_soc_component *component, diff --git a/patch/kernel/sunxi-6.14/patches.megous/Add-support-for-my-private-Sapomat-device.patch b/patch/kernel/sunxi-6.16/patches.megous/Add-support-for-my-private-Sapomat-device.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/Add-support-for-my-private-Sapomat-device.patch rename to patch/kernel/sunxi-6.16/patches.megous/Add-support-for-my-private-Sapomat-device.patch index ed1ab07..4db32de 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/Add-support-for-my-private-Sapomat-device.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/Add-support-for-my-private-Sapomat-device.patch @@ -1,4 +1,4 @@ -From 072caacd4e78332b3de5ed7621ded977eeb6c5e5 Mon Sep 17 00:00:00 2001 +From db5be9e788783971fdca17678e13eaddc7c7edfe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Fri, 18 Aug 2017 13:56:06 +0200 Subject: Add support for my private Sapomat device @@ -10,10 +10,10 @@ Subject: Add support for my private Sapomat device create mode 100644 arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile -index 48666f73e638..1356e9553bd6 100644 +index d799ad153b37..326ff9c7de72 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile -@@ -239,6 +239,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ +@@ -240,6 +240,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-lite.dtb \ sun8i-h3-orangepi-one.dtb \ sun8i-h3-orangepi-pc.dtb \ diff --git a/patch/kernel/sunxi-6.14/patches.megous/Defconfigs-for-all-my-devices.patch b/patch/kernel/sunxi-6.16/patches.megous/Defconfigs-for-all-my-devices.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/Defconfigs-for-all-my-devices.patch rename to patch/kernel/sunxi-6.16/patches.megous/Defconfigs-for-all-my-devices.patch index 4701a17..ef46253 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/Defconfigs-for-all-my-devices.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/Defconfigs-for-all-my-devices.patch @@ -1,17 +1,17 @@ -From b5cd928a177e0a489156d5634dc9b10b6d568ab6 Mon Sep 17 00:00:00 2001 +From ee9c7aa1c404fb5da0baa1032d4df07a5c034807 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 16 Sep 2019 00:35:50 +0200 Subject: Defconfigs for all my devices Signed-off-by: Ondrej Jirman --- - arch/arm/configs/orangepi_defconfig | 715 ++++++++++++ - .../configs/pocketbook_touch_lux_3_defconfig | 416 +++++++ - arch/arm/configs/tbs_a711_defconfig | 524 +++++++++ - arch/arm64/configs/orangepi_defconfig | 1037 +++++++++++++++++ - arch/arm64/configs/pinephone_defconfig | 650 +++++++++++ + arch/arm/configs/orangepi_defconfig | 715 +++++++++++ + .../configs/pocketbook_touch_lux_3_defconfig | 409 +++++++ + arch/arm/configs/tbs_a711_defconfig | 519 ++++++++ + arch/arm64/configs/orangepi_defconfig | 1046 +++++++++++++++++ + arch/arm64/configs/pinephone_defconfig | 650 ++++++++++ .../configs/pinephone_multidist_defconfig | 600 ++++++++++ - 6 files changed, 3942 insertions(+) + 6 files changed, 3939 insertions(+) create mode 100644 arch/arm/configs/orangepi_defconfig create mode 100644 arch/arm/configs/pocketbook_touch_lux_3_defconfig create mode 100644 arch/arm/configs/tbs_a711_defconfig @@ -21,7 +21,7 @@ Signed-off-by: Ondrej Jirman diff --git a/arch/arm/configs/orangepi_defconfig b/arch/arm/configs/orangepi_defconfig new file mode 100644 -index 000000000000..b76f1dc0eba9 +index 000000000000..a71973f41cdf --- /dev/null +++ b/arch/arm/configs/orangepi_defconfig @@ -0,0 +1,715 @@ @@ -43,7 +43,6 @@ index 000000000000..b76f1dc0eba9 +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CPUSETS=y -+# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_BPF=y +CONFIG_USER_NS=y @@ -517,7 +516,6 @@ index 000000000000..b76f1dc0eba9 +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_KENSINGTON is not set -+# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set @@ -692,7 +690,10 @@ index 000000000000..b76f1dc0eba9 +CONFIG_NLS_UTF8=y +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_ENCRYPTED_KEYS=y -+CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" ++CONFIG_SECURITY=y ++CONFIG_SECURITY_LANDLOCK=y ++# CONFIG_INTEGRITY is not set ++CONFIG_LSM="landlock" +CONFIG_INIT_STACK_NONE=y +CONFIG_CRYPTO_PCRYPT=y +CONFIG_CRYPTO_CURVE25519=y @@ -703,6 +704,8 @@ index 000000000000..b76f1dc0eba9 +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_CRC32C=y ++CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_LZ4=y @@ -719,8 +722,6 @@ index 000000000000..b76f1dc0eba9 +CONFIG_CRYPTO_SHA512_ARM=y +CONFIG_CRYPTO_AES_ARM_BS=y +CONFIG_CRYPTO_AES_ARM_CE=y -+CONFIG_CRYPTO_CRC32_ARM_CE=y -+CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y +CONFIG_CRYPTO_DEV_SUN4I_SS=y +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_CE=y @@ -736,16 +737,15 @@ index 000000000000..b76f1dc0eba9 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y +CONFIG_WQ_WATCHDOG=y -+# CONFIG_SCHED_DEBUG is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/pocketbook_touch_lux_3_defconfig b/arch/arm/configs/pocketbook_touch_lux_3_defconfig new file mode 100644 -index 000000000000..a86ca9662199 +index 000000000000..8132edcf6cf0 --- /dev/null +++ b/arch/arm/configs/pocketbook_touch_lux_3_defconfig -@@ -0,0 +1,416 @@ +@@ -0,0 +1,409 @@ +CONFIG_KERNEL_LZ4=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y @@ -1007,7 +1007,6 @@ index 000000000000..a86ca9662199 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_HID is not set -+# CONFIG_USB_HID is not set +CONFIG_USB_LED_TRIG=y +CONFIG_USB=m +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y @@ -1127,6 +1126,8 @@ index 000000000000..a86ca9662199 +CONFIG_CRYPTO_ESSIV=y +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_CRC32C=y ++CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_LZ4=y @@ -1136,26 +1137,18 @@ index 000000000000..a86ca9662199 +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_USER_API_RNG=y +CONFIG_CRYPTO_USER_API_AEAD=y -+CONFIG_CRYPTO_CURVE25519_NEON=y +CONFIG_CRYPTO_GHASH_ARM_CE=y -+CONFIG_CRYPTO_POLY1305_ARM=y +CONFIG_CRYPTO_SHA1_ARM_NEON=y +CONFIG_CRYPTO_SHA1_ARM_CE=y +CONFIG_CRYPTO_SHA2_ARM_CE=y +CONFIG_CRYPTO_SHA512_ARM=y +CONFIG_CRYPTO_AES_ARM_BS=y +CONFIG_CRYPTO_AES_ARM_CE=y -+CONFIG_CRYPTO_CHACHA20_NEON=y -+CONFIG_CRYPTO_CRC32_ARM_CE=y -+CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y +CONFIG_CRYPTO_DEV_SUN4I_SS=y +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=y -+CONFIG_CRYPTO_LIB_CURVE25519=y -+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y -+CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=128 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 @@ -1164,10 +1157,10 @@ index 000000000000..a86ca9662199 +# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/tbs_a711_defconfig b/arch/arm/configs/tbs_a711_defconfig new file mode 100644 -index 000000000000..e29e2c7db357 +index 000000000000..5406abbbb3ef --- /dev/null +++ b/arch/arm/configs/tbs_a711_defconfig -@@ -0,0 +1,524 @@ +@@ -0,0 +1,519 @@ +CONFIG_KERNEL_LZ4=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y @@ -1187,7 +1180,6 @@ index 000000000000..e29e2c7db357 +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CPUSETS=y -+# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_BPF=y +CONFIG_USER_NS=y @@ -1508,7 +1500,6 @@ index 000000000000..e29e2c7db357 +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_KENSINGTON is not set -+# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set @@ -1646,6 +1637,8 @@ index 000000000000..e29e2c7db357 +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y ++CONFIG_CRYPTO_CRC32C=y ++CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_LZ4=y @@ -1656,15 +1649,12 @@ index 000000000000..e29e2c7db357 +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m -+CONFIG_CRYPTO_CURVE25519_NEON=y -+CONFIG_CRYPTO_POLY1305_ARM=y +CONFIG_CRYPTO_SHA1_ARM_NEON=y +CONFIG_CRYPTO_SHA1_ARM_CE=y +CONFIG_CRYPTO_SHA2_ARM_CE=y +CONFIG_CRYPTO_SHA512_ARM=y +CONFIG_CRYPTO_AES_ARM_BS=y +CONFIG_CRYPTO_AES_ARM_CE=y -+CONFIG_CRYPTO_CRC32_ARM_CE=y +CONFIG_CRYPTO_DEV_SUN4I_SS=m +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_CE=m @@ -1672,7 +1662,6 @@ index 000000000000..e29e2c7db357 +CONFIG_PKCS8_PRIVATE_KEY_PARSER=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y -+CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=64 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 @@ -1683,7 +1672,6 @@ index 000000000000..e29e2c7db357 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y +CONFIG_WQ_WATCHDOG=y -+# CONFIG_SCHED_DEBUG is not set +# CONFIG_RCU_TRACE is not set +CONFIG_BOOTTIME_TRACING=y +CONFIG_FUNCTION_TRACER=y @@ -1694,10 +1682,10 @@ index 000000000000..e29e2c7db357 +# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm64/configs/orangepi_defconfig b/arch/arm64/configs/orangepi_defconfig new file mode 100644 -index 000000000000..19cfe9bb4c6e +index 000000000000..6ab0c419ebe2 --- /dev/null +++ b/arch/arm64/configs/orangepi_defconfig -@@ -0,0 +1,1037 @@ +@@ -0,0 +1,1046 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_WATCH_QUEUE=y @@ -1727,7 +1715,6 @@ index 000000000000..19cfe9bb4c6e +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y -+# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_BPF=y @@ -1825,7 +1812,6 @@ index 000000000000..19cfe9bb4c6e +CONFIG_ZSWAP=y +CONFIG_ZSWAP_DEFAULT_ON=y +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4=y -+CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +CONFIG_ZSMALLOC_STAT=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_CMA=y @@ -2036,15 +2022,13 @@ index 000000000000..19cfe9bb4c6e +CONFIG_PCIE_DPC=y +CONFIG_PCIE_PTM=y +CONFIG_PCI_DEBUG=y -+CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=y -+CONFIG_PCI_PF_STUB=y -+CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI=y +CONFIG_PCIE_ROCKCHIP_HOST=y +CONFIG_PCIE_ROCKCHIP_DW_HOST=y ++CONFIG_PCI_PWRCTL_SLOT=y +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y @@ -2064,7 +2048,16 @@ index 000000000000..19cfe9bb4c6e +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=y +CONFIG_BLK_DEV_NVME=y ++CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_HWMON=y ++CONFIG_NVME_TCP=y ++CONFIG_NVME_TCP_TLS=y ++CONFIG_NVME_HOST_AUTH=y ++CONFIG_NVME_TARGET=y ++CONFIG_NVME_TARGET_PASSTHRU=y ++CONFIG_NVME_TARGET_TCP=y ++CONFIG_NVME_TARGET_TCP_TLS=y ++CONFIG_NVME_TARGET_AUTH=y +CONFIG_SRAM=y +CONFIG_PPKB_POWER_MANAGER=y +CONFIG_MODEM_POWER=y @@ -2113,6 +2106,7 @@ index 000000000000..19cfe9bb4c6e +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +CONFIG_R8169=y ++CONFIG_R8169_LEDS=y +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set @@ -2128,6 +2122,7 @@ index 000000000000..19cfe9bb4c6e +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_LED_TRIGGER_PHY=y +CONFIG_MOTORCOMM_PHY=y ++CONFIG_REALTEK_PHY_HWMON=y +CONFIG_ROCKCHIP_PHY=y +CONFIG_MDIO_SUN4I=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y @@ -2303,6 +2298,8 @@ index 000000000000..19cfe9bb4c6e +CONFIG_VIDEO_SUN6I_CSI=y +CONFIG_VIDEO_SUN8I_DEINTERLACE=y +CONFIG_VIDEO_SUN8I_ROTATE=y ++CONFIG_VIDEO_SYNOPSYS_HDMIRX=y ++CONFIG_VIDEO_SYNOPSYS_HDMIRX_LOAD_DEFAULT_EDID=y +CONFIG_VIDEO_HANTRO=y +CONFIG_VIDEO_IMX258=y +CONFIG_VIDEO_OV5640=y @@ -2391,7 +2388,6 @@ index 000000000000..19cfe9bb4c6e +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KENSINGTON is not set -+# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set @@ -2531,6 +2527,7 @@ index 000000000000..19cfe9bb4c6e +CONFIG_SUN50I_IOMMU=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y ++CONFIG_ARM_SMMU_V3_SVA=y +CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_ROCKCHIP_PM_DOMAINS=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y @@ -2661,8 +2658,9 @@ index 000000000000..19cfe9bb4c6e +CONFIG_ENCRYPTED_KEYS=y +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_SECURITY=y ++CONFIG_SECURITY_LANDLOCK=y +# CONFIG_INTEGRITY is not set -+CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" ++CONFIG_LSM="landlock" +CONFIG_INIT_STACK_NONE=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_PCRYPT=y @@ -2674,6 +2672,7 @@ index 000000000000..19cfe9bb4c6e +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CRYPTO_ANSI_CPRNG=y @@ -2692,7 +2691,6 @@ index 000000000000..19cfe9bb4c6e +CONFIG_CRYPTO_AES_ARM64_BS=y +CONFIG_CRYPTO_SM4_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y +CONFIG_CRYPTO_DEV_SUN4I_SS=y +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y +CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG=y @@ -2722,7 +2720,6 @@ index 000000000000..19cfe9bb4c6e +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_KERNEL=y -+CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +CONFIG_PER_VMA_LOCK_STATS=y +CONFIG_PANIC_ON_OOPS=y @@ -2737,7 +2734,7 @@ index 000000000000..19cfe9bb4c6e +# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm64/configs/pinephone_defconfig b/arch/arm64/configs/pinephone_defconfig new file mode 100644 -index 000000000000..51c8740d56e7 +index 000000000000..54c4cb76aa91 --- /dev/null +++ b/arch/arm64/configs/pinephone_defconfig @@ -0,0 +1,650 @@ @@ -2765,7 +2762,6 @@ index 000000000000..51c8740d56e7 +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y -+# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_BPF=y @@ -2808,7 +2804,6 @@ index 000000000000..51c8740d56e7 +CONFIG_HZ_100=y +CONFIG_COMPAT=y +# CONFIG_ARM64_HW_AFDBM is not set -+# CONFIG_ARM64_PAN is not set +# CONFIG_ARM64_USE_LSE_ATOMICS is not set +# CONFIG_ARM64_RAS_EXTN is not set +# CONFIG_ARM64_CNP is not set @@ -3337,7 +3332,10 @@ index 000000000000..51c8740d56e7 +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_ENCRYPTED_KEYS=y +CONFIG_KEY_DH_OPERATIONS=y -+CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" ++CONFIG_SECURITY=y ++CONFIG_SECURITY_LANDLOCK=y ++# CONFIG_INTEGRITY is not set ++CONFIG_LSM="landlock" +CONFIG_INIT_STACK_NONE=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_PCRYPT=m @@ -3351,6 +3349,7 @@ index 000000000000..51c8740d56e7 +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA3=y ++CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_LZ4=y @@ -3370,7 +3369,6 @@ index 000000000000..51c8740d56e7 +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_SM4_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=m -+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +CONFIG_CRYPTO_DEV_SUN8I_CE=m +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +# CONFIG_RAID6_PQ_BENCHMARK is not set @@ -3379,7 +3377,6 @@ index 000000000000..51c8740d56e7 +CONFIG_CMA_SIZE_MBYTES=64 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_DYNAMIC_DEBUG=y -+CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_PER_VMA_LOCK_STATS=y @@ -3393,7 +3390,7 @@ index 000000000000..51c8740d56e7 +# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm64/configs/pinephone_multidist_defconfig b/arch/arm64/configs/pinephone_multidist_defconfig new file mode 100644 -index 000000000000..633924e11882 +index 000000000000..5806a7f7c659 --- /dev/null +++ b/arch/arm64/configs/pinephone_multidist_defconfig @@ -0,0 +1,600 @@ @@ -3419,7 +3416,6 @@ index 000000000000..633924e11882 +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y -+# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_BPF=y @@ -3463,7 +3459,6 @@ index 000000000000..633924e11882 +CONFIG_NR_CPUS=4 +CONFIG_COMPAT=y +# CONFIG_ARM64_HW_AFDBM is not set -+# CONFIG_ARM64_PAN is not set +# CONFIG_ARM64_USE_LSE_ATOMICS is not set +# CONFIG_ARM64_RAS_EXTN is not set +# CONFIG_ARM64_CNP is not set @@ -3946,7 +3941,10 @@ index 000000000000..633924e11882 +CONFIG_BIG_KEYS=y +CONFIG_ENCRYPTED_KEYS=y +CONFIG_KEY_DH_OPERATIONS=y -+CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" ++CONFIG_SECURITY=y ++CONFIG_SECURITY_LANDLOCK=y ++# CONFIG_INTEGRITY is not set ++CONFIG_LSM="landlock" +CONFIG_INIT_STACK_NONE=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_PCRYPT=y @@ -3957,6 +3955,7 @@ index 000000000000..633924e11882 +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_LZ4=y @@ -3976,7 +3975,6 @@ index 000000000000..633924e11882 +CONFIG_CRYPTO_AES_ARM64_BS=y +CONFIG_CRYPTO_SM4_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y +CONFIG_CRYPTO_DEV_SUN8I_CE=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=y +# CONFIG_RAID6_PQ_BENCHMARK is not set @@ -3985,7 +3983,6 @@ index 000000000000..633924e11882 +CONFIG_CMA_SIZE_MBYTES=64 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_DYNAMIC_DEBUG=y -+CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_SLUB_DEBUG is not set diff --git a/patch/kernel/sunxi-6.14/patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch b/patch/kernel/sunxi-6.16/patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch similarity index 91% rename from patch/kernel/sunxi-6.14/patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch rename to patch/kernel/sunxi-6.16/patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch index 02c47fe..9457571 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch @@ -1,4 +1,4 @@ -From c9248297e040af7071212003c78140c1e383535d Mon Sep 17 00:00:00 2001 +From db50ddfc31f95785afe1d795342ebbaab9ab9484 Mon Sep 17 00:00:00 2001 From: "Steinar H. Gunderson" Date: Mon, 4 Nov 2024 15:35:38 +0000 Subject: Fix broken allwinner,sram dependency on h616, h618 @@ -33,10 +33,10 @@ Signed-off-by: Steinar H. Gunderson 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/of/property.c b/drivers/of/property.c -index 8c9f3ea663a6..074fbf9d27f8 100644 +index 934468f306d2..632520524453 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c -@@ -1470,8 +1470,9 @@ static struct device_node *parse_allwinner_sram(struct device_node *np, +@@ -1503,8 +1503,9 @@ static struct device_node *parse_allwinner_sram(struct device_node *np, return NULL; sram_node = of_parse_phandle(np, prop_name, 0); diff --git a/patch/kernel/sunxi-6.14/patches.megous/Fix-intptr_t-typedef.patch b/patch/kernel/sunxi-6.16/patches.megous/Fix-intptr_t-typedef.patch similarity index 88% rename from patch/kernel/sunxi-6.14/patches.megous/Fix-intptr_t-typedef.patch rename to patch/kernel/sunxi-6.16/patches.megous/Fix-intptr_t-typedef.patch index e17baeb..5f48aa8 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/Fix-intptr_t-typedef.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/Fix-intptr_t-typedef.patch @@ -1,4 +1,4 @@ -From fb28d52e3bbfa61ae3a900d5a42972628c2e9ea2 Mon Sep 17 00:00:00 2001 +From 433ece293225ddb3579d8daae858a99c91ab6345 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 26 Aug 2023 10:55:24 +0200 Subject: Fix intptr_t typedef @@ -12,7 +12,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 4 insertions(+) diff --git a/include/linux/types.h b/include/linux/types.h -index 1c509ce8f7f6..46f7b982a7ec 100644 +index 49b79c8bb1a9..2ba4098c118f 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -40,7 +40,11 @@ typedef __kernel_uid16_t uid16_t; diff --git a/patch/kernel/sunxi-6.14/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch b/patch/kernel/sunxi-6.16/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch similarity index 79% rename from patch/kernel/sunxi-6.14/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch rename to patch/kernel/sunxi-6.16/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch index 8b378ab..80f83fa 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch @@ -1,4 +1,4 @@ -From 8b84ffb671ccc349736193252b38ecedb32503dd Mon Sep 17 00:00:00 2001 +From adf296d2885139e4d707f2ddcda67119cde20459 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 30 Sep 2017 21:31:35 +0200 Subject: MAINTAINERS: Add entry for Himax HM5065 @@ -9,10 +9,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS -index 00e94bec401e..7d07a2608cb2 100644 +index dd844ac8d910..5e3f6101fef6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -10375,6 +10375,12 @@ L: linux-kernel@vger.kernel.org +@@ -10642,6 +10642,12 @@ L: linux-kernel@vger.kernel.org S: Maintained F: drivers/misc/hisi_hikey_usb.c diff --git a/patch/kernel/sunxi-6.14/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch b/patch/kernel/sunxi-6.16/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch rename to patch/kernel/sunxi-6.16/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch index 14982ac..c569cef 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch @@ -1,4 +1,4 @@ -From 6d2930ee9c0b2c64a42d5559a91858b9b8e6926c Mon Sep 17 00:00:00 2001 +From 80c12c413892885dce6c7a162c4f3fad729bf19e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Fri, 18 Aug 2017 13:55:48 +0200 Subject: Make microbuttons on Orange Pi PC and PC 2 work as power off buttons diff --git a/patch/kernel/sunxi-6.14/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch b/patch/kernel/sunxi-6.16/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch similarity index 87% rename from patch/kernel/sunxi-6.14/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch rename to patch/kernel/sunxi-6.16/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch index 95bc4a9..4780d6f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch @@ -1,4 +1,4 @@ -From 3bcea65acc9d9f6227d539e7db848caa149e8ed6 Mon Sep 17 00:00:00 2001 +From 9d4e9084103a2d5317f981d19f1e4f25cce82e56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 10 Feb 2020 01:00:12 +0100 Subject: Mark some slow drivers for async probe with PROBE_PREFER_ASYNCHRONOUS @@ -12,10 +12,10 @@ Signed-off-by: Ondrej Jirman 2 files changed, 2 insertions(+) diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c -index 128db14ba726..9881cb1de9ef 100644 +index aa664a923f91..f232c309639c 100644 --- a/drivers/iio/accel/bma180.c +++ b/drivers/iio/accel/bma180.c -@@ -1127,6 +1127,7 @@ static struct i2c_driver bma180_driver = { +@@ -1126,6 +1126,7 @@ static struct i2c_driver bma180_driver = { .name = "bma180", .pm = pm_sleep_ptr(&bma180_pm_ops), .of_match_table = bma180_of_match, diff --git a/patch/kernel/sunxi-6.14/patches.megous/Move-a-node-to-avoid-merge-conflict.patch b/patch/kernel/sunxi-6.16/patches.megous/Move-a-node-to-avoid-merge-conflict.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/Move-a-node-to-avoid-merge-conflict.patch rename to patch/kernel/sunxi-6.16/patches.megous/Move-a-node-to-avoid-merge-conflict.patch index 02cab02..74a283c 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/Move-a-node-to-avoid-merge-conflict.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/Move-a-node-to-avoid-merge-conflict.patch @@ -1,4 +1,4 @@ -From 275a68cd0bf4414c886f9f4a5e39f7f166fe4286 Mon Sep 17 00:00:00 2001 +From 52698af01860c97aa37a5f939822e5e373d750e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 9 May 2021 23:43:21 +0200 Subject: Move a node to avoid merge conflict @@ -40,7 +40,7 @@ index 0f19e7c00c50..a872fc586ab6 100644 compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index 7e11286bf6d1..d1f5daf63484 100644 +index 4e435010d3e7..e0c2b097cf46 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -128,6 +128,10 @@ &gpu { diff --git a/patch/kernel/sunxi-6.14/patches.megous/Revert-Input-cyttsp4-remove-driver.patch b/patch/kernel/sunxi-6.16/patches.megous/Revert-Input-cyttsp4-remove-driver.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/Revert-Input-cyttsp4-remove-driver.patch rename to patch/kernel/sunxi-6.16/patches.megous/Revert-Input-cyttsp4-remove-driver.patch index 40050fc..4b0dc1c 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/Revert-Input-cyttsp4-remove-driver.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/Revert-Input-cyttsp4-remove-driver.patch @@ -1,4 +1,4 @@ -From afe7cc88dc1c603d849bfac407867231ce8ccdff Mon Sep 17 00:00:00 2001 +From 381c22e7230b5ef2b5b417ce70407d7033657341 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 26 Sep 2024 23:00:02 +0200 Subject: Revert "Input: cyttsp4 - remove driver" @@ -24,10 +24,10 @@ This reverts commit 25162a4f64f8ba0065f300977589fe1f6af332f0. create mode 100644 include/linux/platform_data/cyttsp4.h diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig -index 1a03de7fcfa6..3a8a3ad64cdc 100644 +index 91a2b584dab1..588c43247b5a 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig -@@ -254,6 +254,36 @@ config TOUCHSCREEN_CYTTSP_SPI +@@ -267,6 +267,36 @@ config TOUCHSCREEN_CYTTSP_SPI To compile this driver as a module, choose M here: the module will be called cyttsp_spi. @@ -65,10 +65,10 @@ index 1a03de7fcfa6..3a8a3ad64cdc 100644 tristate "Cypress TrueTouch Gen5 Touchscreen Driver" depends on I2C diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile -index 82bc837ca01e..04dc8039341b 100644 +index 97a025c6a377..4f57a36a565c 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile -@@ -25,8 +25,11 @@ obj-$(CONFIG_TOUCHSCREEN_CHIPONE_ICN8505) += chipone_icn8505.o +@@ -26,8 +26,11 @@ obj-$(CONFIG_TOUCHSCREEN_CHIPONE_ICN8505) += chipone_icn8505.o obj-$(CONFIG_TOUCHSCREEN_CY8CTMA140) += cy8ctma140.o obj-$(CONFIG_TOUCHSCREEN_CY8CTMG110) += cy8ctmg110_ts.o obj-$(CONFIG_TOUCHSCREEN_CYTTSP_CORE) += cyttsp_core.o diff --git a/patch/kernel/sunxi-6.14/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch b/patch/kernel/sunxi-6.16/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch rename to patch/kernel/sunxi-6.16/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch index 4c49a15..1938fc9 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch @@ -1,4 +1,4 @@ -From 150ddcb209012261b0a63d80ae9481134105e04a Mon Sep 17 00:00:00 2001 +From 92403437786449872aeeb6f754c46e0491d7237b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 1 Nov 2020 02:57:38 +0100 Subject: Revert "drm/sun4i: lvds: Invert the LVDS polarity" diff --git a/patch/kernel/sunxi-6.14/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch b/patch/kernel/sunxi-6.16/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch rename to patch/kernel/sunxi-6.16/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch index cfbff1c..508a268 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch @@ -1,4 +1,4 @@ -From 4328071664e452dc5ceff356343a04b4f399c118 Mon Sep 17 00:00:00 2001 +From ebdcbc962461edbec4202e2838cdc8b7bc71e2de Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 7 May 2024 18:39:12 +0200 Subject: Revert "usb: typec: tcpm: unregister existing source caps before @@ -10,7 +10,7 @@ This reverts commit 230ecdf71a644c9c73e0e6735b33173074ae3f94. 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c -index 62ca4a0ec55b..2c92996954b2 100644 +index 8adf6f954633..3dc8e89d4349 100644 --- a/drivers/usb/typec/tcpm/tcpm.c +++ b/drivers/usb/typec/tcpm/tcpm.c @@ -3053,7 +3053,7 @@ static int tcpm_register_source_caps(struct tcpm_port *port) diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch index 7c22387..08fe391 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch @@ -1,4 +1,4 @@ -From eff7988fc46688c551cb1d18bef171cf3243905d Mon Sep 17 00:00:00 2001 +From 2e0c841787533394064770f05807d550041e25ce Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 20 Jul 2020 01:11:34 +0800 Subject: arm64: allwinner: dts: a64: enable K101-IM2BYL02 panel for PineTab diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch index e15c1e4..99b84cf 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch @@ -1,4 +1,4 @@ -From add1775ff68e073feb7cc5e3ada49826633c256c Mon Sep 17 00:00:00 2001 +From cb04a2e9798702acfada5ebae6eaeb8666a94d97 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 6 Dec 2020 11:15:34 -0600 Subject: arm64: dts: allwinner: Enforce consistent MMC numbering diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch index a26e4b2..2542323 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch @@ -1,4 +1,4 @@ -From 6129debfdc7530a3ac08ad6486d4008b7aa7c3ab Mon Sep 17 00:00:00 2001 +From 36a8032951af0c3cc2c611e3eb9e029284ab20e4 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 10:39:56 +0200 Subject: arm64: dts: allwinner: a64: Add hdmi sound card diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch index 3cd1913..3e75eb7 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch @@ -1,4 +1,4 @@ -From 12b313d4d8ec2709665fd56a97d28fee9dbd5207 Mon Sep 17 00:00:00 2001 +From 7a5d60656d86649a9d75691e0627e7b6ac4425c4 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 10:42:16 +0200 Subject: arm64: dts: allwinner: a64: Enable hdmi sound card on boards with diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch index dbc1ee3..8441241 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch @@ -1,4 +1,4 @@ -From c675093587794fbf1de91fa2de45aea0c117b901 Mon Sep 17 00:00:00 2001 +From 31cb5e39bc2c1e82535deb7e8a3caa22b92cceeb Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 30 Jun 2019 22:45:34 +0800 Subject: arm64: dts: allwinner: a64: Fix LRADC compatible diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch index fc01a5a..0c1bca6 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch @@ -1,4 +1,4 @@ -From 572548e1235cc21b5be242b267fdc66984d6d3f8 Mon Sep 17 00:00:00 2001 +From f39cebebca731d2532487e25b0abb922ff1b73d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 17 Nov 2020 01:06:30 +0100 Subject: arm64: dts: allwinner: a64: pinetab: add front camera diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch index b085458..f67de87 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch @@ -1,4 +1,4 @@ -From 7835fbd016daedfa548cdb6b9c4b9d663bc67c73 Mon Sep 17 00:00:00 2001 +From 311d32459db5a436223e8ae214ce3924f052346e Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 9 May 2021 12:40:31 +0200 Subject: arm64: dts: allwinner: h5: Enable hdmi sound card on boards with hdmi diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch index 2589bd6..e2952bc 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch @@ -1,4 +1,4 @@ -From eedcdc30e7c22e62ce01296f6fefc63b1143e810 Mon Sep 17 00:00:00 2001 +From 49109dd5b54b7d1005023c4267c1430c1851f803 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 10 Nov 2020 20:43:28 +0100 Subject: arm64: dts: allwinner: h6: Add hdmi sound card diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch index 109c6a2..bff0ca8 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch @@ -1,4 +1,4 @@ -From dead2c32ebf5c0c69df98a4b72e35e11753991b2 Mon Sep 17 00:00:00 2001 +From 2d299372345e7b811416c38bb8cbb7a0f533bbd5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 11 Jan 2022 13:08:47 +0100 Subject: arm64: dts: allwinner: h6: Enable hdmi sound card on boards with hdmi @@ -15,7 +15,7 @@ Signed-off-by: Jernej Skrabec 4 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -index 13a0e63afeaf..4044c33c92f2 100644 +index 2c64d834a2c4..bf1e98ded8f5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -119,6 +119,10 @@ hdmi_out_con: endpoint { @@ -29,8 +29,8 @@ index 13a0e63afeaf..4044c33c92f2 100644 &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; -@@ -291,6 +295,10 @@ sw { - }; +@@ -291,6 +295,10 @@ &r_pio { + vcc-pm-supply = <®_aldo1>; }; +&sound_hdmi { @@ -41,7 +41,7 @@ index 13a0e63afeaf..4044c33c92f2 100644 pinctrl-names = "default"; pinctrl-0 = <&spdif_tx_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index 48d720e20334..7e11286bf6d1 100644 +index da322cb97935..4e435010d3e7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -167,6 +167,10 @@ ext_rgmii_phy: ethernet-phy@1 { @@ -67,7 +67,7 @@ index 48d720e20334..7e11286bf6d1 100644 pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -index d05dc5d6e6b9..ed4d4672f4c9 100644 +index e34dbb992021..283ccedf61ad 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi @@ -91,6 +91,10 @@ hdmi_out_con: endpoint { diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch index 89e454e..62167ed 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch @@ -1,4 +1,4 @@ -From 4e0844ed190a4de7091fac2fcb3f1cfb7b6893dd Mon Sep 17 00:00:00 2001 +From d9a843250fcc438da3dd001affeb7cf4633f1353 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 20 Aug 2019 14:54:48 +0200 Subject: arm64: dts: allwinner: orange-pi-3: Enable ethernet @@ -29,7 +29,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index ab87c3447cd7..48d720e20334 100644 +index f005072c68a1..da322cb97935 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -15,6 +15,7 @@ / { @@ -92,7 +92,7 @@ index ab87c3447cd7..48d720e20334 100644 &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -@@ -212,6 +251,7 @@ reg_aldo2: aldo2 { +@@ -208,6 +247,7 @@ reg_aldo2: aldo2 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc33-audio-tv-ephy-mac"; diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch index 48a2b34..59c6b64 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch @@ -1,4 +1,4 @@ -From ed8e79073bb141a1f5a5b5f2b891e3c9be8079c8 Mon Sep 17 00:00:00 2001 +From bbabbba649fd3fb0c0b0891097d19b674786c49a Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 14 May 2024 10:47:05 +0200 Subject: arm64: dts: sun50-a64-pinephone: Define jack pins in DT diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch index 2e608e0..b28af14 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch @@ -1,4 +1,4 @@ -From b0ce326666eaf6803bcc5723af14c513eff895d5 Mon Sep 17 00:00:00 2001 +From 9fc8d272956ff94de190cfd4db043b2de160fe91 Mon Sep 17 00:00:00 2001 From: Arnav Singh Date: Mon, 6 May 2024 16:36:04 -0700 Subject: arm64: dts: sun50i: Define orientation and rotation for PinePhone diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch index 5c5658d..2defb1b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch @@ -1,4 +1,4 @@ -From d742191977aca3b6ba39e760ff7c307728e10eb2 Mon Sep 17 00:00:00 2001 +From c20ec491bd4e9ff660e61f5a0a6742b5030b53c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 1 Feb 2020 23:41:18 +0100 Subject: arm64: dts: sun50i-a64: Set fifo-size for uarts diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch index 54ebfbf..d14799b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch @@ -1,4 +1,4 @@ -From dbf95776199d6ae835f22bcb28af833821d3e2b2 Mon Sep 17 00:00:00 2001 +From 1b9223af22e8cc89dfafd8fde0927b198a0096cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 8 Jul 2020 00:58:16 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Add Type-C support for all PP diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch index 69258e2..32a0ccb 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch @@ -1,4 +1,4 @@ -From 382fca153620b6d38d36f13d093e524d301f8c44 Mon Sep 17 00:00:00 2001 +From 0b69e3c30ca0642ec4aeb432682ba091eff25fc4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 28 Sep 2020 04:35:13 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Add detailed OCV to capactiy diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch index b03ae63..48ac89b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch @@ -1,4 +1,4 @@ -From 46c60d4ce1900101897221b32794922bee23855f Mon Sep 17 00:00:00 2001 +From eb1bd7fb76019a6f26fb91df777427bffd0a2a64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 8 Apr 2020 14:13:08 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Add front/back cameras diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch index df18e76..2ee9403 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch @@ -1,4 +1,4 @@ -From dd36dd39913b0dcbcd99b4d41492a5c436a056e3 Mon Sep 17 00:00:00 2001 +From 7d013de674b78eb3c9aaf2525fe3ff1c4c534110 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 17 Jan 2021 23:06:03 +0100 Subject: arm64: dts: sun50i-a64-pinephone: Add interrupt pin for WiFi diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch index d188548..a2624d5 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch @@ -1,4 +1,4 @@ -From 079113ffb649556d044400aa3d4ab176948c461a Mon Sep 17 00:00:00 2001 +From 87c069f463b5254f2a9eb8897f5518e0447ffeba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 8 Jul 2020 01:00:48 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Add modem power manager diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch index cdf579e..8795216 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch @@ -1,4 +1,4 @@ -From 3aa8258da2bda4c6e5b18e223c6025fc77fd4bc5 Mon Sep 17 00:00:00 2001 +From fd3a8795bb4bf5da2d3e53734304275bf9bc3b33 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 20 May 2023 16:58:11 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Add power supply to stk3311 diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch index a476322..db1cd4b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch @@ -1,4 +1,4 @@ -From 8cedae67577d6f1d1350e65571d6bfc6a5be9ffa Mon Sep 17 00:00:00 2001 +From 26bd71ea18a5d67fe7786ae7ac3718fc3a151ad6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 15 Feb 2021 17:45:13 +0100 Subject: arm64: dts: sun50i-a64-pinephone: Add reboot mode driver diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch index 040b4b6..c41fe45 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch @@ -1,4 +1,4 @@ -From 1e444bc655527644b0420e0da7a3b2b41b460f6e Mon Sep 17 00:00:00 2001 +From 7669f421470053b340536075c4e32a295fc6d41f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 18 Oct 2021 17:41:25 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Add supply for i2c bus to anx7688 diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch index 609274b..16876ec 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch @@ -1,4 +1,4 @@ -From 34e327e91d7aafc189e2be3c701ceeb9b2dbaacd Mon Sep 17 00:00:00 2001 +From c8e8b1a46867903e0416442d11b04fe76f92764d Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 6 Feb 2020 23:49:27 -0600 Subject: arm64: dts: sun50i-a64-pinephone: Add support for Bluetooth audio diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch index 15cdb66..046a462 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch @@ -1,4 +1,4 @@ -From c2c2f67a5e65027ed1f142ad564fa0e170df47ca Mon Sep 17 00:00:00 2001 +From b7354df594ca1f5c018d9a6226c5e75e9b103a92 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 10 Nov 2022 20:11:10 +0100 Subject: arm64: dts: sun50i-a64-pinephone: Add support for Pinephone 1.2 beta diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch index de5ffb1..c8f93de 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch @@ -1,4 +1,4 @@ -From 671ab9b320585350524ef5f6fdf3e1d3a47b2b15 Mon Sep 17 00:00:00 2001 +From 87ab5e0886a0900ef9e7aaac7db023a452a38acc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Fri, 21 Jan 2022 23:28:48 +0100 Subject: arm64: dts: sun50i-a64-pinephone: Add support for Pinephone keyboard diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch index dd64937..251ad26 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch @@ -1,4 +1,4 @@ -From 2cf576727cd3f9434c1a9921d69ca2eb04273f3c Mon Sep 17 00:00:00 2001 +From ec5a6dcc040fdd8fd25a04c069aa347af2a2f0bc Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 5 Feb 2020 23:14:27 -0600 Subject: arm64: dts: sun50i-a64-pinephone: Add support for modem audio diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch index 99992b0..0a271b6 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch @@ -1,4 +1,4 @@ -From 429717d518e8ab162336302782b040755e6f3d9f Mon Sep 17 00:00:00 2001 +From b7a6048f256191e77603b184100ada3d55d71482 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 30 Nov 2020 06:14:07 +0100 Subject: arm64: dts: sun50i-a64-pinephone: Bump I2C frequency to 400kHz diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch index e9171c2..ba482f0 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch @@ -1,4 +1,4 @@ -From c5f3ddccace279a6885d01b7919e7dd5cdf21b3c Mon Sep 17 00:00:00 2001 +From a3bfb36655db6b2b391834286308d27446f5aad2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 26 Apr 2021 01:31:27 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Don't make lradc keys a wakeup diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch index ab4aab7..ad80a2e 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch @@ -1,4 +1,4 @@ -From 88b3c983bfedc0ccceede32e6055320772a8c146 Mon Sep 17 00:00:00 2001 +From 9080ccefb9c9248b5883fca436cca525325ee9ab Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 16 Apr 2022 02:12:06 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Enable Pinephone Keyboard power diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch index 3892e49..a971e18 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch @@ -1,4 +1,4 @@ -From b4a237d25b94da596769bf1669e8e8017a0d2145 Mon Sep 17 00:00:00 2001 +From d0a9f2f8c0fb354e2f13c21a6233307e5f7d1762 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 23 Sep 2020 00:13:54 -0500 Subject: arm64: dts: sun50i-a64-pinephone: Enable internal HMIC bias diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch index 5be69fc..95f91c6 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch @@ -1,4 +1,4 @@ -From 60ededfd0381c8c76a587daff8ca5dfe47195149 Mon Sep 17 00:00:00 2001 +From 91abb8ec1b9d1934f30bce18754beaaa3c876a3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 5 Aug 2020 11:19:01 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Fix BH modem manager behavior diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch index 230dd5c..68e9aa7 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch @@ -1,4 +1,4 @@ -From f495e5bfb6f5967b34cf61a8e9a0dfb91c0c726d Mon Sep 17 00:00:00 2001 +From d3683b90a432c887c58a9ebc1aa9c9b0a2cb28d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 25 Apr 2021 03:17:39 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Power off the touch controller in diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch index cfcbee7..f30bbbf 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch @@ -1,4 +1,4 @@ -From d7c78e25c6b1f65cbf3fdef64401a804f62392e1 Mon Sep 17 00:00:00 2001 +From a45320985e7d7014bbf626c99a7a13f3bb5b37c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 7 Jun 2021 20:23:52 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Set minimum backlight duty cycle to diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch index 59e3d65..645add9 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch @@ -1,4 +1,4 @@ -From 02f9ee2c698d1d2debe17d60569ebb7366280942 Mon Sep 17 00:00:00 2001 +From 68e6a5f5eb0d80c8848148d6b28b9a70dde13d85 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Thu, 6 Feb 2020 04:58:32 +0100 Subject: arm64: dts: sun50i-a64-pinephone: Shorten post-power-on-delay on mmcs diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch index 3a9127f..fa1c827 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch @@ -1,4 +1,4 @@ -From 3eaa6aabbb8758f9309a73287cfaaf9005a6979e Mon Sep 17 00:00:00 2001 +From 0a1d2105089307fe586728da81ffe9ff72a7c1c1 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 23 Feb 2024 01:53:14 +0100 Subject: arm64: dts: sun50i-a64-pinephone: Use newer jack detection diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch index bd24677..a59b3b8 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch @@ -1,4 +1,4 @@ -From 5547207e11f604491659e71791488f00b010d3c9 Mon Sep 17 00:00:00 2001 +From 859ef16fde3273363d1f96aa5102ffd989839ba0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 26 Oct 2021 01:25:46 +0200 Subject: arm64: dts: sun50i-a64-pinephone: Workaround broken HDMI HPD signal diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch index 910f707..a506fc1 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch @@ -1,4 +1,4 @@ -From b76c601b4f0f85265c2d33adf1c4642c6e050e2a Mon Sep 17 00:00:00 2001 +From 02c1983611509ffa7c23a7d179b9938d91ce3605 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sun, 18 Feb 2024 17:39:58 +0100 Subject: arm64: dts: sun50i-a64-pinetab: Add accelerometer diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch index 4d98add..e4353ab 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch @@ -1,4 +1,4 @@ -From c530886e537d311c5c8833f1c685ca457155e5fb Mon Sep 17 00:00:00 2001 +From 151137acdd83736e3d861c9741bf9c6a15a941fc Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sun, 18 Feb 2024 17:38:00 +0100 Subject: arm64: dts: sun50i-a64-pinetab: Name sound card PineTab diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch index 8070192..86a417d 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch @@ -1,4 +1,4 @@ -From ad81b4fe119c8d10e47fc7aa721f5505103176ea Mon Sep 17 00:00:00 2001 +From 9ff7270eb4cce26a5f9273ff517c5e33160bebcd Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 14 Apr 2019 23:46:47 +0800 Subject: arm64: dts: sun50i-a64-pinetab: enable RTL8723CS bluetooth diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch index a362ef8..f9e4246 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch @@ -1,4 +1,4 @@ -From c83ffe6aa547f78dc811a570dd78baf0c482a41f Mon Sep 17 00:00:00 2001 +From 9aa4049d40809f2660a84ef5de4e12a6796e008d Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 13 Mar 2023 06:02:46 +0100 Subject: arm64: dts: sun50i-h5: Add missing GPU trip point diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch index 5a85ded..77074c6 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch @@ -1,4 +1,4 @@ -From a926b916c845808bcbfc976427be67d28c980a4c Mon Sep 17 00:00:00 2001 +From c0e0b352c9fa4e4cf0c0cfefc91fb7f29c7a1499 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 17 Aug 2020 23:43:53 +0200 Subject: arm64: dts: sun50i-h5: Use my own more aggressive OPPs on H5 diff --git a/patch/kernel/sunxi-6.14/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch b/patch/kernel/sunxi-6.16/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch rename to patch/kernel/sunxi-6.16/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch index 463464f..c4782ee 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch @@ -1,4 +1,4 @@ -From b8f9f4c5427c44cc2c23c51687424d2dc5c25fcf Mon Sep 17 00:00:00 2001 +From 5dbdd7357937051a2dea9365c458d37c380f1f54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Thu, 10 Sep 2020 21:38:28 +0200 Subject: arm64: xor: Select 32regs without benchmark to speed up boot diff --git a/patch/kernel/sunxi-6.14/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch b/patch/kernel/sunxi-6.16/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch rename to patch/kernel/sunxi-6.16/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch index b458c52..92e3109 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch @@ -1,4 +1,4 @@ -From 23fcf552af5ba182cd53d5af326a73c86a351eae Mon Sep 17 00:00:00 2001 +From c5dbbc316c5cac012f24ea37b8edd816689771a9 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sun, 7 Aug 2022 14:28:16 +0200 Subject: bluetooth: bcm: Restore drive_rts_on_open = true behavior on diff --git a/patch/kernel/sunxi-6.14/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch b/patch/kernel/sunxi-6.16/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch similarity index 89% rename from patch/kernel/sunxi-6.14/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch rename to patch/kernel/sunxi-6.16/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch index b880bf8..88033f7 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch @@ -1,4 +1,4 @@ -From dcd320fc4e24521978144b482cb01814b4f80c5e Mon Sep 17 00:00:00 2001 +From 05a88f4a1f6a5458c8f26b463e0edbf1f7184061 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sun, 30 Apr 2023 18:12:17 +0200 Subject: bluetooth: h5: Don't re-initialize rtl8723cs on resume @@ -11,7 +11,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c -index c0436881a533..3f6955ce9b7c 100644 +index edafa228bf83..3788f2e30827 100644 --- a/drivers/bluetooth/hci_h5.c +++ b/drivers/bluetooth/hci_h5.c @@ -1108,7 +1108,7 @@ static const struct of_device_id rtl_bluetooth_of_match[] = { diff --git a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch rename to patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch index 0317431..2c8f4cf 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch @@ -1,4 +1,4 @@ -From c654921edfdbeca309621420e64ee5b014fc306b Mon Sep 17 00:00:00 2001 +From 0a4e8bd6b447700ce0f19a40923dea454568612b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 10 Mar 2020 06:04:32 +0100 Subject: clk: sunxi-ng: Don't use CPU PLL gating and CPUX reparenting to HOSC diff --git a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch rename to patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch index 434a324..a8f459d 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch @@ -1,4 +1,4 @@ -From c55cb745c5ad2b343487227c24d2961cc2aa7ec2 Mon Sep 17 00:00:00 2001 +From 0f50c9a070925687c775a7d49ae8f1e00d4b37a7 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 3 Apr 2021 17:14:49 -0500 Subject: clk: sunxi-ng: Export CLK_DRAM for devfreq diff --git a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch rename to patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch index 460c133..05d87ff 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch @@ -1,4 +1,4 @@ -From 9ba880cc4a8d1fcd989cb000c1679e9e596dba9b Mon Sep 17 00:00:00 2001 +From 7100e0e8a9e4ee57a7a98902ec75ca6b6e39f540 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 28 May 2022 18:01:42 -0500 Subject: clk: sunxi-ng: Mark TWD clocks as critical diff --git a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch rename to patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch index babc35e..55f4a16 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch @@ -1,4 +1,4 @@ -From 68e7e97e96211e3df8cc02638fcfe7081166ebbf Mon Sep 17 00:00:00 2001 +From 935080b966eaeacab0d252f43c6889df1e1978ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Thu, 12 Jan 2017 16:34:57 +0100 Subject: clk: sunxi-ng: Set maximum P and M factors to 1 for H3 pll-cpux clock diff --git a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch rename to patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch index 917d49a..e605af4 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch @@ -1,4 +1,4 @@ -From 6817daf7af44eaf118c68c12b617b62b9ecc510f Mon Sep 17 00:00:00 2001 +From af8b7fb8734c40d59add9eba0afae4135ab3ab5d Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 19 Jul 2020 17:10:15 -0500 Subject: clk: sunxi-ng: a64: Increase PLL_AUDIO base frequency diff --git a/patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch b/patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch rename to patch/kernel/sunxi-6.16/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch diff --git a/patch/kernel/sunxi-6.16/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch b/patch/kernel/sunxi-6.16/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch new file mode 100644 index 0000000..e790bc7 --- /dev/null +++ b/patch/kernel/sunxi-6.16/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch @@ -0,0 +1,29 @@ +From c796eb62c525763361ff0749c648738b23ffa5d2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= +Date: Thu, 31 Oct 2019 18:31:32 +0100 +Subject: cpufreq: sun50i: Show detected CPU bin, for easier debugging + +Useful for people running into crashes during boot, due to issues +with OPP voltages. + +Signed-off-by: Ondrej Jirman +--- + drivers/cpufreq/sun50i-cpufreq-nvmem.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c +index 744312a44279..d8c1be2b30fb 100644 +--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c ++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c +@@ -268,6 +268,8 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev) + snprintf(name, sizeof(name), "speed%d", speed); + config.prop_name = name; + ++ pr_info("Using CPU speed bin %s\n", name); ++ + for_each_present_cpu(cpu) { + struct device *cpu_dev = get_cpu_device(cpu); + +-- +2.35.3 + diff --git a/patch/kernel/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch b/patch/kernel/sunxi-6.16/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch similarity index 91% rename from patch/kernel/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch rename to patch/kernel/sunxi-6.16/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch index 9296558..e7194e5 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch @@ -1,4 +1,4 @@ -From 023860ddb7a0feb4e634ebcbdd53a1721663f512 Mon Sep 17 00:00:00 2001 +From f51bbed2c8816215dc541a759744ede320046e11 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 1 Sep 2023 00:57:04 +0200 Subject: drm: bridge: dw-hdmi: Allow to accept HPD status from other drivers @@ -11,7 +11,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 996733ed2c00..57b2ea9225ca 100644 +index 0890add5f707..8d100b964947 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -9,6 +9,7 @@ @@ -53,7 +53,7 @@ index 996733ed2c00..57b2ea9225ca 100644 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; else hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; -@@ -3128,7 +3137,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) +@@ -3127,7 +3136,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) status = connector_status_disconnected; } @@ -62,7 +62,7 @@ index 996733ed2c00..57b2ea9225ca 100644 dev_dbg(hdmi->dev, "EVENT=%s\n", status == connector_status_connected ? "plugin" : "plugout"); -@@ -3314,6 +3323,25 @@ bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi) +@@ -3313,6 +3322,25 @@ bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi) } EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420); @@ -88,7 +88,7 @@ index 996733ed2c00..57b2ea9225ca 100644 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, const struct dw_hdmi_plat_data *plat_data) { -@@ -3356,15 +3384,38 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, +@@ -3355,15 +3383,38 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, if (ret < 0) return ERR_PTR(ret); @@ -129,7 +129,7 @@ index 996733ed2c00..57b2ea9225ca 100644 } else { dev_dbg(hdmi->dev, "no ddc property found\n"); } -@@ -3583,6 +3634,8 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, +@@ -3582,6 +3633,8 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, err_res: i2c_put_adapter(hdmi->ddc); @@ -138,7 +138,7 @@ index 996733ed2c00..57b2ea9225ca 100644 return ERR_PTR(ret); } -@@ -3590,6 +3643,8 @@ EXPORT_SYMBOL_GPL(dw_hdmi_probe); +@@ -3589,6 +3642,8 @@ EXPORT_SYMBOL_GPL(dw_hdmi_probe); void dw_hdmi_remove(struct dw_hdmi *hdmi) { diff --git a/patch/kernel/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch b/patch/kernel/sunxi-6.16/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch similarity index 87% rename from patch/kernel/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch rename to patch/kernel/sunxi-6.16/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch index 1726442..2cfaf75 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch @@ -1,4 +1,4 @@ -From d21528bf852f57845123c8d64bbd5dd5eba17e32 Mon Sep 17 00:00:00 2001 +From 568e67eba02daecce03d3264e8a2eef088d99a7e Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 1 Sep 2023 00:59:08 +0200 Subject: drm: bridge: dw-hdmi: Report HDMI hotplug events @@ -9,7 +9,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 57b2ea9225ca..0f1582318119 100644 +index 8d100b964947..ca6ef7c7a4f6 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2455,7 +2455,13 @@ static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi) @@ -27,7 +27,7 @@ index 57b2ea9225ca..0f1582318119 100644 return result; } -@@ -3138,7 +3144,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) +@@ -3137,7 +3143,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) } if (status != connector_status_unknown && !hdmi->extcon) { diff --git a/patch/kernel/sunxi-6.14/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch b/patch/kernel/sunxi-6.16/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch rename to patch/kernel/sunxi-6.16/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch index 19f4533..449ea31 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch @@ -1,4 +1,4 @@ -From 82f1ded9bc2c9cf4f9f3b541cdc8f2d6d42a6775 Mon Sep 17 00:00:00 2001 +From e7e694ceab4d3e5b1733a275600ee7610a156eb6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Thu, 29 Oct 2020 04:55:40 +0100 Subject: drm/panel: st7703: Fix xbd599 timings to make refresh rate exactly diff --git a/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch b/patch/kernel/sunxi-6.16/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch rename to patch/kernel/sunxi-6.16/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch index 7330797..28a0291 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch @@ -1,4 +1,4 @@ -From acc83b9c1798eb38d27e8bb273d5fd1f79f8c33a Mon Sep 17 00:00:00 2001 +From 9a81dc42297b8d3afe929ea9dac2e500ce323ed5 Mon Sep 17 00:00:00 2001 From: Frank Oltmanns Date: Sun, 10 Mar 2024 14:32:29 +0100 Subject: drm/sun4i: tcon: Support keeping dclk rate upon ancestor clock diff --git a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch rename to patch/kernel/sunxi-6.16/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch index d464378..e636809 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch @@ -1,4 +1,4 @@ -From 9d267992ddf49ed7c35fec49416bea500dd7efdf Mon Sep 17 00:00:00 2001 +From da5fbba99d1384b9a439632e5eb57c50d2d52f50 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 10 Sep 2019 12:02:23 +0800 Subject: dt-bindings: axp20x-adc: allow to use TS pin as GPADC diff --git a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch rename to patch/kernel/sunxi-6.16/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch index f66383c..7d189bb 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch @@ -1,4 +1,4 @@ -From 02cd44cdcb83d7b3b4adb5908fa184cfb60a67e1 Mon Sep 17 00:00:00 2001 +From 79b28fcefa71e73bed54bee943e9fe7ee0c320af Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 23 Feb 2020 00:00:00 +0100 Subject: dt-bindings: input: gpio-vibrator: Don't require enable-gpios diff --git a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch rename to patch/kernel/sunxi-6.16/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch index 6e92a41..90dbf13 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch @@ -1,4 +1,4 @@ -From 881c70e2d4624f2af93a7464c0b7471896b2cb9a Mon Sep 17 00:00:00 2001 +From 5cd5beae0f142c506a821f000f01715f384d3f36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 23 Feb 2020 13:40:15 +0100 Subject: dt-bindings: leds: Add a binding for AXP813 charger led diff --git a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch rename to patch/kernel/sunxi-6.16/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch index 3062996..30603c4 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch @@ -1,4 +1,4 @@ -From 3680411d51a3657965cf6226c91dca9e7b0140fc Mon Sep 17 00:00:00 2001 +From a7ff54b904bb070b4fe162639fe573e38be39b10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 30 Sep 2017 02:30:39 +0200 Subject: dt-bindings: media: Add bindings for Himax HM5065 camera sensor diff --git a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch rename to patch/kernel/sunxi-6.16/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch index 9c7b9fb..f611ace 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch @@ -1,4 +1,4 @@ -From b1949039cf1e2d3d460e0ae3da77e6f51e3df3f0 Mon Sep 17 00:00:00 2001 +From 6eb32c97bee48006c6eaf138ed1a74953b32bcc3 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 17 Feb 2024 02:01:49 +0100 Subject: dt: bindings: mfd: Add codec related properties to AC100 PMIC diff --git a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch rename to patch/kernel/sunxi-6.16/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch index 62246f6..625e19d 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch @@ -1,4 +1,4 @@ -From f20f5106e8f16311a5a99f9de7ef1049d9e8bbd7 Mon Sep 17 00:00:00 2001 +From 0430c4df441ae442ee384a64e6e644d7a665e4fe Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 23 Feb 2024 00:47:12 +0100 Subject: dt-bindings: sound: Add jack-type property to sun8i-a33-codec diff --git a/patch/kernel/sunxi-6.14/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch b/patch/kernel/sunxi-6.16/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch rename to patch/kernel/sunxi-6.16/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch index e6ccb92..e2463bc 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch @@ -1,4 +1,4 @@ -From 7ccfcf014f1793ab9388a98cdabe65e0a336259a Mon Sep 17 00:00:00 2001 +From e77804e8367c2482dcc0720e3a0e671b0e1cf9a7 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 5 Mar 2019 22:02:41 -0600 Subject: firmware: arm_scpi: Support unidirectional mailbox channels diff --git a/patch/kernel/sunxi-6.14/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch b/patch/kernel/sunxi-6.16/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch rename to patch/kernel/sunxi-6.16/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch index 6b0932f..4210af5 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch @@ -1,4 +1,4 @@ -From 0cfb0b5ca768b2516a5aa7b0f88be0daeea31692 Mon Sep 17 00:00:00 2001 +From fd7032e0146307b9a5908510a0b7d15bef0f1e12 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 2 Nov 2019 15:14:10 +0100 Subject: firmware: scpi: Add support for sending a SCPI_CMD_SET_SYS_PWR_STATE diff --git a/patch/kernel/sunxi-6.14/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch b/patch/kernel/sunxi-6.16/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch rename to patch/kernel/sunxi-6.16/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch index ed98593..ef0c210 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch @@ -1,4 +1,4 @@ -From 21307662463898619177f8290f24007d38d3810e Mon Sep 17 00:00:00 2001 +From 938a58ff90b57bbdcf4c5f3dbf263943a34242d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 23 Oct 2019 05:08:35 +0200 Subject: gnss: ubx: Send soft powerdown message on suspend diff --git a/patch/kernel/sunxi-6.14/patches.megous/hm5065-yaml-bindings-wip.patch b/patch/kernel/sunxi-6.16/patches.megous/hm5065-yaml-bindings-wip.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/hm5065-yaml-bindings-wip.patch rename to patch/kernel/sunxi-6.16/patches.megous/hm5065-yaml-bindings-wip.patch index 95462e0..681fc1b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/hm5065-yaml-bindings-wip.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/hm5065-yaml-bindings-wip.patch @@ -1,4 +1,4 @@ -From 95c2f6cf0f9b2c0f358946ebd92947e817bb2ba1 Mon Sep 17 00:00:00 2001 +From 3d8fccc589301485fdc68d36ae2f4ead37cf20b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 20 May 2019 17:58:05 +0200 Subject: hm5065: yaml bindings (wip) diff --git a/patch/kernel/sunxi-6.14/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch b/patch/kernel/sunxi-6.16/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch similarity index 84% rename from patch/kernel/sunxi-6.14/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch rename to patch/kernel/sunxi-6.16/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch index b8f1eab..dbc5f3b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch @@ -1,4 +1,4 @@ -From 329092d43e60dd4c8f1308330231a77c7cb00bd9 Mon Sep 17 00:00:00 2001 +From bf093191436d019c33ede873d5a2bec444cf60c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 17 Jan 2021 23:19:52 +0100 Subject: i2c: mv64xxx: Don't make a fuss when pinctrl recovery state is not @@ -12,10 +12,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 8 insertions(+) diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c -index 874309580c33..d7cac1434126 100644 +index 8fc26a511320..03447ef74845 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c -@@ -950,6 +950,14 @@ static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data, +@@ -944,6 +944,14 @@ static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data, return -ENODEV; } diff --git a/patch/kernel/sunxi-6.14/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch b/patch/kernel/sunxi-6.16/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch rename to patch/kernel/sunxi-6.16/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch index ba33f25..265ca5e 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch @@ -1,4 +1,4 @@ -From 5617049aa26b140a13a7eb7c3e38ab940c6cbca0 Mon Sep 17 00:00:00 2001 +From 093d6a0d3bd6ce22417d9a1edfc2eb6327b33251 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 10 Sep 2019 12:03:32 +0800 Subject: iio: adc: axp20x_adc: allow to set TS pin to GPADC mode diff --git a/patch/kernel/sunxi-6.14/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch b/patch/kernel/sunxi-6.16/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch rename to patch/kernel/sunxi-6.16/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch index 0bfb840..19c913a 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch @@ -1,4 +1,4 @@ -From 0ff022dc3b2674f575bcf30a2a988002845eb698 Mon Sep 17 00:00:00 2001 +From a005a12a6903c17751b70d576d4f735136d9fe37 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 7 Oct 2019 02:12:34 +0200 Subject: iio: adc: sun4i-gpadc-iio: Allow to use sun5i-a13-gpadc-iio from DT diff --git a/patch/kernel/sunxi-6.14/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch b/patch/kernel/sunxi-6.16/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch rename to patch/kernel/sunxi-6.16/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch index e24bffa..fb3aa3f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch @@ -1,4 +1,4 @@ -From db9ba37a021ab7935acc6d7b7ff4e40756314229 Mon Sep 17 00:00:00 2001 +From 5d65602a483243db2d1e342e663d615ffaeeb3d8 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 29 Oct 2022 23:12:49 +0200 Subject: iio: st_sensors: Don't report error when the device is not present on diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch index e6a8c25..59ec835 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch @@ -1,4 +1,4 @@ -From eeddb82ccb6cc3d77349fc5eb465b3636383017f Mon Sep 17 00:00:00 2001 +From 325eb4b9e594a5319de6a4eabe6551c74bf32f8a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 28 Sep 2019 18:00:33 +0200 Subject: input: cyttsp4: Clear the ids buffer in a saner way diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch index e202ca0..93b2676 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch @@ -1,4 +1,4 @@ -From 3b73c055dddefa34abf2bc744b607c23411e3099 Mon Sep 17 00:00:00 2001 +From 278ce12ef3cd9b45214e97eaca762fb3d7171369 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 28 Sep 2019 16:01:06 +0200 Subject: input: cyttsp4: De-obfuscate MT signals setup/platform data diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch index 3f201fb..39d63b5 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch @@ -1,4 +1,4 @@ -From 942e10d26c88fc22ffb1a520d4441b31912cc5fd Mon Sep 17 00:00:00 2001 +From 0f6085b577de00361be85a9174abf50406a79f0d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 28 Sep 2019 14:46:11 +0200 Subject: input: cyttsp4: De-obfuscate platform data for keys diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch index 23785ca..bc16d8b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch @@ -1,4 +1,4 @@ -From fc58479f81ed2a3d2eaf37030addf1534fcf10d0 Mon Sep 17 00:00:00 2001 +From c7b389914f6bfb6cdb77aa8d7d8860e659525aee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 28 Sep 2019 18:01:49 +0200 Subject: input: cyttsp4: ENOSYS error is ok when powering up diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch index 7ff2799..57f5e30 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch @@ -1,4 +1,4 @@ -From d360ec7955abbb6da5b01a392a0192cb561a54c3 Mon Sep 17 00:00:00 2001 +From cb57244359cccc2351137f99e35efc58c449d903 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 28 Sep 2019 18:03:41 +0200 Subject: input: cyttsp4: Faster recovery from failed wakeup (HACK) diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Fix-compile-issue.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Fix-compile-issue.patch similarity index 83% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Fix-compile-issue.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Fix-compile-issue.patch index dde9442..260abc2 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Fix-compile-issue.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Fix-compile-issue.patch @@ -1,4 +1,4 @@ -From 224d61a728afdbd5131719f99e33b6be432ea25c Mon Sep 17 00:00:00 2001 +From 83687378bf8c8bb19ea59e6b4e91379e64856661 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 22 Nov 2024 23:42:03 +0100 Subject: input: cyttsp4: Fix compile issue @@ -11,7 +11,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c -index 67cb72ad6620..97264bfbfca4 100644 +index 67cb72ad6620..b2a294cce19e 100644 --- a/drivers/input/touchscreen/cyttsp4_core.c +++ b/drivers/input/touchscreen/cyttsp4_core.c @@ -851,7 +851,7 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch) @@ -19,7 +19,7 @@ index 67cb72ad6620..97264bfbfca4 100644 struct cyttsp4_touch tch; int i, j, t = 0; - int ids[max(CY_TMA1036_MAX_TCH, CY_TMA4XX_MAX_TCH)] = {0}; -+ int ids[max(CY_TMA1036_MAX_TCH, CY_TMA4XX_MAX_TCH)] = {}; ++ int ids[CY_TMA4XX_MAX_TCH] = {}; struct cyttsp4_signal_def* sig; for (i = 0; i < num_cur_tch; i++) { diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Fix-probe-oops.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Fix-probe-oops.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Fix-probe-oops.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Fix-probe-oops.patch index aef98e6..8b7cdf9 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Fix-probe-oops.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Fix-probe-oops.patch @@ -1,4 +1,4 @@ -From 4909c2986e0c930ce9ee49e30f53eae3a1fd5abd Mon Sep 17 00:00:00 2001 +From 007fbfc30bc53cb0ea6ec6787a0a55939b79aaa3 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 11 Mar 2022 22:01:10 +0100 Subject: input: cyttsp4: Fix probe oops diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Fix-warnings.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Fix-warnings.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Fix-warnings.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Fix-warnings.patch index d32a0d2..e99df80 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Fix-warnings.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Fix-warnings.patch @@ -1,4 +1,4 @@ -From 46db61d367d9b20e72bb4660be54a418672262ec Mon Sep 17 00:00:00 2001 +From d028d8705f55b0503a3af7683883e7ea872dd212 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 7 Oct 2019 06:22:56 +0200 Subject: input: cyttsp4: Fix warnings diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch index 919a604..92549d4 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch @@ -1,4 +1,4 @@ -From 1445518f66b5f3d00bee5a10cf66fda0d0adae18 Mon Sep 17 00:00:00 2001 +From 6073f0dc79fd6d96a8d947ef7d99cfb6e6224bd1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 14 Oct 2019 18:00:32 +0200 Subject: input: cyttsp4: Make the driver not hog the system's workqueue diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch index da130be..75ae97f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch @@ -1,4 +1,4 @@ -From 7fd7b9301fa4d426d48cc017cd1920cec28be8a0 Mon Sep 17 00:00:00 2001 +From b34db1af691712bbec6f7691d13bb85d163f0b8e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 1 Oct 2019 00:31:06 +0200 Subject: input: cyttsp4: Port the driver to use device properties diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch similarity index 91% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch index bd63188..8a89a36 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch @@ -1,4 +1,4 @@ -From 20f3eaeeca3ca518b9f5d566ea206afc70569569 Mon Sep 17 00:00:00 2001 +From 9ddbbad78c1517f14a55b441e26198883adfb1a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 28 Sep 2019 15:06:16 +0200 Subject: input: cyttsp4: Remove unused enable_vkeys diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch index 30fc8a6..fc0fc57 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch @@ -1,4 +1,4 @@ -From c384e31b371b8cd94b47ed60fc35c0f72247b71a Mon Sep 17 00:00:00 2001 +From b6b725e62058c3a130ae6b1f2e9fe1f58ab2079f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 28 Sep 2019 15:05:39 +0200 Subject: input: cyttsp4: Remove useless indirection with driver/platform data diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch index 5c8550d..21247bb 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch @@ -1,4 +1,4 @@ -From 722dc128c2cfef58b8ed8737f6c76224be25cd28 Mon Sep 17 00:00:00 2001 +From 80d62b28d911162c42e2e4ecc1e97509aea92d17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 1 Oct 2019 02:21:43 +0200 Subject: input: cyttsp4: Restart on wakeup (wakeup by I2C read doesn't work) diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch index b6f968e..af9cbd9 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch @@ -1,4 +1,4 @@ -From 08cc518ba716985004d51794be20d684e18bdd45 Mon Sep 17 00:00:00 2001 +From 35529ed0b3185a534b4d6a155316aed8a8c9b943 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 6 Mar 2023 01:17:09 +0100 Subject: input: cyttsp4: Use i2c/spi names directly in the driver diff --git a/patch/kernel/sunxi-6.14/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch b/patch/kernel/sunxi-6.16/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch rename to patch/kernel/sunxi-6.16/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch index 8abb01a..ff42a60 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch @@ -1,4 +1,4 @@ -From 2ff865418f446773e58aacf75a2af9a9327abedb Mon Sep 17 00:00:00 2001 +From 82acca74c4809c57b7e7a808b41050a992ea7ccf Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 8 Sep 2023 01:07:30 +0200 Subject: input: gpio-vibra: Allow to use vcc-supply alone to control the diff --git a/patch/kernel/sunxi-6.14/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch b/patch/kernel/sunxi-6.16/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch rename to patch/kernel/sunxi-6.16/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch index 0311559..9bc7a76 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch @@ -1,4 +1,4 @@ -From aa883f0bc0aa293a2e1dc1e1f1514a9f75aa2eb2 Mon Sep 17 00:00:00 2001 +From 2829adc58e91d03b47b7e921cc061b3f851e7f5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Thu, 4 Feb 2021 00:55:20 +0100 Subject: leds: axp20x: Support charger LED on AXP20x like PMICs @@ -23,10 +23,10 @@ Signed-off-by: Ondrej Jirman create mode 100644 drivers/leds/leds-axp20x.c diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig -index 2b27d043921c..6ee7b96aa3d2 100644 +index a104cbb0a001..2cdd55033c54 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -996,6 +996,14 @@ config LEDS_IP30 +@@ -1006,6 +1006,14 @@ config LEDS_IP30 To compile this driver as a module, choose M here: the module will be called leds-ip30. @@ -41,7 +41,7 @@ index 2b27d043921c..6ee7b96aa3d2 100644 config LEDS_ACER_A500 tristate "Power button LED support for Acer Iconia Tab A500" depends on LEDS_CLASS && MFD_ACER_A500_EC -@@ -1003,6 +1011,13 @@ config LEDS_ACER_A500 +@@ -1013,6 +1021,13 @@ config LEDS_ACER_A500 This option enables support for the Power Button LED of Acer Iconia Tab A500. @@ -56,10 +56,10 @@ index 2b27d043921c..6ee7b96aa3d2 100644 comment "Flash and Torch LED drivers" diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile -index 6ad52e219ec6..b8626ca58a6f 100644 +index 2f170d69dcbf..c9d62a7b166b 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile -@@ -96,6 +96,7 @@ obj-$(CONFIG_LEDS_UPBOARD) += leds-upboard.o +@@ -97,6 +97,7 @@ obj-$(CONFIG_LEDS_UPBOARD) += leds-upboard.o obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o @@ -327,10 +327,10 @@ index 000000000000..e2877af1032a +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:leds-axp20x"); diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c -index cff56deba24f..4e52c79f8f50 100644 +index e9914e8a29a3..6d3ac1ac3bc0 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c -@@ -1214,6 +1214,9 @@ static const struct mfd_cell axp813_cells[] = { +@@ -1215,6 +1215,9 @@ static const struct mfd_cell axp813_cells[] = { .num_resources = ARRAY_SIZE(axp803_usb_power_supply_resources), .resources = axp803_usb_power_supply_resources, .of_compatible = "x-powers,axp813-usb-power-supply", diff --git a/patch/kernel/sunxi-6.14/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch b/patch/kernel/sunxi-6.16/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch similarity index 87% rename from patch/kernel/sunxi-6.14/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch rename to patch/kernel/sunxi-6.16/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch index 7aab58a..b347669 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch @@ -1,4 +1,4 @@ -From 18fbe636256b55efe55c17b1a9d039ee1fc8c538 Mon Sep 17 00:00:00 2001 +From 7d40d465a2d0dc0673eecb34fe8ad4b284f82740 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 2 Nov 2019 15:09:01 +0100 Subject: mailbox: Allow to run mailbox while timekeeping is suspended @@ -14,10 +14,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c -index d3d26a2c9895..01f918ae71b6 100644 +index 0593b4d03685..2926ffac3df1 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c -@@ -84,10 +84,12 @@ static void msg_submit(struct mbox_chan *chan) +@@ -81,10 +81,12 @@ static void msg_submit(struct mbox_chan *chan) spin_unlock_irqrestore(&chan->lock, flags); if (!err && (chan->txdone_method & TXDONE_BY_POLL)) { @@ -34,7 +34,7 @@ index d3d26a2c9895..01f918ae71b6 100644 } } -@@ -269,6 +271,24 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg) +@@ -266,6 +268,24 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg) msg_submit(chan); diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch b/patch/kernel/sunxi-6.16/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch index 039bb68..b9ed9de 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch @@ -1,4 +1,4 @@ -From d7e104605f90e71fd43fa8a8579b6082c6ffdd76 Mon Sep 17 00:00:00 2001 +From 626ac094d7bc8c340ca5e76f47cadcf63a78fd99 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 26 Apr 2020 14:38:15 -0500 Subject: media: cedrus: Fix failure to clean up hardware on probe failure diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch index d91063a..a3c5fe6 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch @@ -1,4 +1,4 @@ -From b909ea0af9550a47ce455f0bac451bf8ed37e916 Mon Sep 17 00:00:00 2001 +From 921cab004fc9c32299287534cccaf6411a289f51 Mon Sep 17 00:00:00 2001 From: Benjamin Schaaf Date: Mon, 22 Nov 2021 23:38:26 +1100 Subject: media: gc2145: Add PIXEL_RATE, HBLANK and VBLANK controls diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch index 54eb5e2..72e2483 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch @@ -1,4 +1,4 @@ -From c39a8e59c4abd741e172f47ec80b08ad12b85f39 Mon Sep 17 00:00:00 2001 +From ca2aeac0efd626c422a0ccf0162c97b77dcb32c7 Mon Sep 17 00:00:00 2001 From: Martijn Braam Date: Fri, 4 Sep 2020 17:35:39 +0200 Subject: media: gc2145: Added BGGR bayer mode diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Disable-debug-output.patch b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Disable-debug-output.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Disable-debug-output.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Disable-debug-output.patch index 1822318..ab93fea 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Disable-debug-output.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Disable-debug-output.patch @@ -1,4 +1,4 @@ -From 420354a4c5c188185fcc37270e4c41bdbb608e60 Mon Sep 17 00:00:00 2001 +From 9bbfe7211cdb4889fa26845d3615f7365707534a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 27 Oct 2021 17:22:51 +0200 Subject: media: gc2145: Disable debug output diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch index 3ea449e..1b68613 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch @@ -1,4 +1,4 @@ -From 57c06d951021ac23bc4850ca6bbf1513848a6a06 Mon Sep 17 00:00:00 2001 +From 916c5ebcec96ed092f84c0ba8174fa2d7b0e8a6f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 23 Jun 2020 19:51:18 +0200 Subject: media: gc2145: Galaxycore camera module driver @@ -14,7 +14,7 @@ Signed-off-by: Ondrej Jirman create mode 100644 drivers/media/i2c/gc2145.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig -index 0cc793fc7910..017d993a8c49 100644 +index 85f8315014fd..9648fb08614d 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -712,6 +712,16 @@ config VIDEO_HM5065 @@ -35,10 +35,10 @@ index 0cc793fc7910..017d993a8c49 100644 menu "Camera ISPs" diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile -index 08bd346db54e..8d79cbb0f29c 100644 +index af8ffebd936a..6d65938bf13b 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile -@@ -158,3 +158,4 @@ obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o +@@ -159,3 +159,4 @@ obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o obj-$(CONFIG_VIDEO_WM8739) += wm8739.o obj-$(CONFIG_VIDEO_WM8775) += wm8775.o obj-$(CONFIG_VIDEO_HM5065) += hm5065.o diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-fix-white-balance-colors.patch b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-fix-white-balance-colors.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/media-gc2145-fix-white-balance-colors.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-gc2145-fix-white-balance-colors.patch index 4249b78..b898bfa 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-fix-white-balance-colors.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-fix-white-balance-colors.patch @@ -1,4 +1,4 @@ -From 7499b88dc111f8367eb0f8a807e4603627ee2e4e Mon Sep 17 00:00:00 2001 +From 4500a0c03eeaf344403eae481fc459196a6046b7 Mon Sep 17 00:00:00 2001 From: Andrey Skvortsov Date: Sat, 26 Aug 2023 12:10:49 +0300 Subject: media: gc2145: fix white-balance colors diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-implement-system-suspend.patch b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-implement-system-suspend.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/media-gc2145-implement-system-suspend.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-gc2145-implement-system-suspend.patch index c3396c6..72953dc 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-gc2145-implement-system-suspend.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-gc2145-implement-system-suspend.patch @@ -1,4 +1,4 @@ -From db757ea5f058b665f3435c42810ff35838f4a28d Mon Sep 17 00:00:00 2001 +From 0ffac4f697e56f9853250674f09bd28c2a43083a Mon Sep 17 00:00:00 2001 From: Andrey Skvortsov Date: Mon, 14 Aug 2023 13:27:08 +0300 Subject: media: gc2145: implement system suspend diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch b/patch/kernel/sunxi-6.16/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch index a9b0d8c..673078f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch @@ -1,4 +1,4 @@ -From 198b881fede9a9acae6cf9dc4e100735985e2785 Mon Sep 17 00:00:00 2001 +From e7e994d0635f53037864802477adcd9779b47639 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 30 Sep 2017 02:39:48 +0200 Subject: media: hm5065: Add subdev driver for Himax HM5065 camera sensor @@ -21,7 +21,7 @@ Signed-off-by: Ondrej Jirman create mode 100644 drivers/media/i2c/hm5065.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig -index 85ecb2aeefdb..2be73870045c 100644 +index e45ba127069f..f4737e952402 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -702,6 +702,16 @@ config VIDEO_VGXY61 @@ -42,10 +42,10 @@ index 85ecb2aeefdb..2be73870045c 100644 menu "Camera ISPs" diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile -index fbb988bd067a..b429d9f2e982 100644 +index 6c23a4463527..4604119022dd 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile -@@ -157,3 +157,4 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o +@@ -158,3 +158,4 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o obj-$(CONFIG_VIDEO_WM8739) += wm8739.o obj-$(CONFIG_VIDEO_WM8775) += wm8775.o diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch b/patch/kernel/sunxi-6.16/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch index c808ad0..afe2527 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch @@ -1,4 +1,4 @@ -From 430f13bc72248989cdf797c828aff616164e4ebf Mon Sep 17 00:00:00 2001 +From 74cec6ad97f5515089149372ae45d01fe352228a Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 13 Jan 2024 21:00:27 +0100 Subject: media: i2c: gc2145: Move upstream driver out of the way @@ -15,7 +15,7 @@ Signed-off-by: Ondrej Jirman rename drivers/media/i2c/{gc2145.c => gc2145-mipi.c} (100%) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig -index e7da18f3da3c..43be07cc5b37 100644 +index f4737e952402..85f8315014fd 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -90,9 +90,9 @@ config VIDEO_GC08A3 @@ -31,7 +31,7 @@ index e7da18f3da3c..43be07cc5b37 100644 This is a V4L2 sensor-level driver for GalaxyCore GC2145 2 Mpixel camera. diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile -index b429d9f2e982..08bd346db54e 100644 +index 4604119022dd..af8ffebd936a 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -40,7 +40,7 @@ obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/ diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch b/patch/kernel/sunxi-6.16/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch index 3c2e227..0474b26 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch @@ -1,4 +1,4 @@ -From 4e13c92260d7cce43f7278488993cf4ed4b4c591 Mon Sep 17 00:00:00 2001 +From 9f481d156324d320094a23c554e2c75a5dc070ec Mon Sep 17 00:00:00 2001 From: Robert Mader Date: Mon, 6 May 2024 16:36:05 -0700 Subject: media: i2c: gc2145: Parse and register properties diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch index c0c4296..0878382 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch @@ -1,4 +1,4 @@ -From 8f82ed74e5a0e9bc121429492cc09ff99b12aa9b Mon Sep 17 00:00:00 2001 +From 571e03699f1d966341d521234d8634901d7344d9 Mon Sep 17 00:00:00 2001 From: Adam Pigg Date: Thu, 29 Dec 2022 11:10:41 +0000 Subject: media: ov5640: Add read-only property for vblank diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch index 3eda71e..6471115 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch @@ -1,4 +1,4 @@ -From 699b30b9278830c2ad7ae7331b3e6ee5016199da Mon Sep 17 00:00:00 2001 +From 86218a28682b1b5953f17a9704aa2d0f6d1f737b Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 8 Nov 2023 19:13:37 +0100 Subject: media: ov5640: Don't powerup the sensor during driver probe diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch index 05abfd3..2c8c196 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch @@ -1,4 +1,4 @@ -From 3fcdfc009b409cd64bb7926fecab2633486caf3b Mon Sep 17 00:00:00 2001 +From 4fe83630124f10631b59efa447f469ee978f354e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Fri, 24 Jan 2020 18:25:59 +0100 Subject: media: ov5640: [Experiment] Try to disable denoising/sharpening diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch index e92f0af..aa55f06 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch @@ -1,4 +1,4 @@ -From eb9964740528f9aa25ee2c7591e92d3ed8f296a3 Mon Sep 17 00:00:00 2001 +From 70588635615f5d4a6c8074b7d3d9908d6ad95352 Mon Sep 17 00:00:00 2001 From: Benjamin Schaaf Date: Mon, 22 Nov 2021 23:38:26 +1100 Subject: media: ov5640: Fix focus commands blocking until complete diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Implement-autofocus.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Implement-autofocus.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Implement-autofocus.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Implement-autofocus.patch index ddfb542..1b61836 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Implement-autofocus.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Implement-autofocus.patch @@ -1,4 +1,4 @@ -From e4f5aafa6a9584e382e62fe88386a58efc19ac29 Mon Sep 17 00:00:00 2001 +From 3d30babbea4d5e01f95446cf434816adb9e2b275 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sun, 7 Aug 2022 15:17:09 +0200 Subject: media: ov5640: Implement autofocus diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Improve-error-reporting.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Improve-error-reporting.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Improve-error-reporting.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Improve-error-reporting.patch index 3cd68e2..5d9e1f3 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Improve-error-reporting.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Improve-error-reporting.patch @@ -1,4 +1,4 @@ -From bba2d0b661c0d2e89df60ea31e93307367407e75 Mon Sep 17 00:00:00 2001 +From 46691e9e3d27f941c858425cce057b9debf704c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Fri, 22 Oct 2021 19:52:49 +0200 Subject: media: ov5640: Improve error reporting diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Improve-firmware-load-time.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Improve-firmware-load-time.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Improve-firmware-load-time.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Improve-firmware-load-time.patch index d35a05c..79114ac 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Improve-firmware-load-time.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Improve-firmware-load-time.patch @@ -1,4 +1,4 @@ -From 20eee5b2d15278056cfddaddebbe2870b368ea1e Mon Sep 17 00:00:00 2001 +From 6abe0f00f6f10238a86138273eb20ac1f5c3c391 Mon Sep 17 00:00:00 2001 From: Benjamin Schaaf Date: Mon, 22 Nov 2021 23:38:26 +1100 Subject: media: ov5640: Improve firmware load time diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch index 98c89d2..05626a9 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch @@ -1,4 +1,4 @@ -From 8649c6af904ecf4098b858e6d622b5cee6ffd1cf Mon Sep 17 00:00:00 2001 +From cb549cb4cb6561599f15d0e105128cebdfcf074f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 26 Jan 2020 00:19:40 +0100 Subject: media: ov5640: Sleep after poweroff to ensure next poweron is not too diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-set-default-ae-target-lower.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-set-default-ae-target-lower.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5640-set-default-ae-target-lower.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5640-set-default-ae-target-lower.patch index ab30ecb..ddffa6b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-set-default-ae-target-lower.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-set-default-ae-target-lower.patch @@ -1,4 +1,4 @@ -From 098ea461478192bdce1c8daf9dced8b2edba861b Mon Sep 17 00:00:00 2001 +From e04cd072725047a968181aa31138f17ff3560c63 Mon Sep 17 00:00:00 2001 From: Martijn Braam Date: Wed, 7 Oct 2020 17:33:43 +0200 Subject: media: ov5640: set default ae target lower diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch index edf72ed..234d37f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch @@ -1,4 +1,4 @@ -From b05dfe5ce59ad5c2bae740af6d2b44518a7754fd Mon Sep 17 00:00:00 2001 +From 6968b9a6cbd6679054184da7d924494a9c3d5803 Mon Sep 17 00:00:00 2001 From: Andrey Skvortsov Date: Mon, 14 Aug 2023 13:25:07 +0300 Subject: media: ov5640: use pm_runtime_force_suspend/resume for system suspend diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch b/patch/kernel/sunxi-6.16/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch index fe435c8..84cd1c5 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch @@ -1,4 +1,4 @@ -From 2f64c8745d4217a3375648c0e3af0f3ab0765a5d Mon Sep 17 00:00:00 2001 +From e2831e8bd14ee5e31bfda88837b48dc0e4f01b1e Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 24 Apr 2024 00:00:31 +0200 Subject: media: ov5648: Fix call to pm_runtime_set_suspended diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch index 62222bc..859e7fb 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch @@ -1,4 +1,4 @@ -From 9bdb57f474095a3e7ab25410a24d4b7dbf8028aa Mon Sep 17 00:00:00 2001 +From a32cdeeedfa4d7d6b5ad4fbce611dff54aadeec6 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 6 Jan 2023 11:25:09 +0100 Subject: media: sun6i-csi: Add multicamera support for parallel bus diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch index c686004..aa7a01c 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch @@ -1,4 +1,4 @@ -From 8f97c0cb4b2e06ba17b6c6d020ff22af2f9ed265 Mon Sep 17 00:00:00 2001 +From 27e548baf66f29354ecc92048d9ecabd200cf255 Mon Sep 17 00:00:00 2001 From: Adam Pigg Date: Tue, 3 Jan 2023 18:52:04 +0000 Subject: media: sun6i-csi: add V4L2_CAP_IO_MC capability diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch index c3995fc..d20b1d8 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch @@ -1,4 +1,4 @@ -From 92fb79b20a3d74951ac19b53d684d6b5f9a284de Mon Sep 17 00:00:00 2001 +From 55d4b1a0847850f4a5cb27a979c3b52ad2e09291 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 4 Jan 2023 12:29:56 +0200 Subject: media: sun6i-csi: capture: Use subdev operation to access bridge diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch index ecfc5c5..a3e0272 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch @@ -1,4 +1,4 @@ -From 5d32b5ed1d4592469ac598972ed467486a9c3641 Mon Sep 17 00:00:00 2001 +From b49b58d79ff3ec88dcd5d2cca003932126e7334b Mon Sep 17 00:00:00 2001 From: Adam Pigg Date: Wed, 4 Jan 2023 21:18:51 +0000 Subject: media: sun6i-csi: implement vidioc_enum_framesizes diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch index 3c35ff6..ea2a8b1 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch @@ -1,4 +1,4 @@ -From 4a94459f3c9f24e22331bb5e100ca885faa6a3bb Mon Sep 17 00:00:00 2001 +From 20ba5b2794f226a6068df460dc8996e9145fcfec Mon Sep 17 00:00:00 2001 From: Adam Pigg Date: Tue, 3 Jan 2023 18:20:21 +0000 Subject: media: sun6i-csi: merge sun6i_csi_formats and sun6i_csi_formats_match diff --git a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch rename to patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch index 60b5267..dd3919f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch @@ -1,4 +1,4 @@ -From 7ca3f841e2a66d2145bedc06dbcce5044725f622 Mon Sep 17 00:00:00 2001 +From d363452af206db99c991de89f7c20a46bde318ae Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 13 Jan 2024 21:24:24 +0100 Subject: media: sun6i-csi: subdev: Use subdev active state to store active diff --git a/patch/kernel/sunxi-6.14/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch b/patch/kernel/sunxi-6.16/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch similarity index 88% rename from patch/kernel/sunxi-6.14/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch rename to patch/kernel/sunxi-6.16/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch index 0321218..35b91ec 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch @@ -1,4 +1,4 @@ -From 183f5386ee44033042a23dcb7051572cb5a229a9 Mon Sep 17 00:00:00 2001 +From f065ee70cbba46f1f31aea8cfb8b745c4c3a72f3 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 29 Feb 2020 01:01:58 -0600 Subject: mfd: axp20x: Add battery IRQ resources @@ -9,10 +9,10 @@ Signed-off-by: Samuel Holland 1 file changed, 36 insertions(+) diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c -index 4e52c79f8f50..8ff8bc4a22b2 100644 +index 6d3ac1ac3bc0..3584121faef8 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c -@@ -311,6 +311,15 @@ static const struct resource axp20x_ac_power_supply_resources[] = { +@@ -312,6 +312,15 @@ static const struct resource axp20x_ac_power_supply_resources[] = { DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"), }; @@ -28,7 +28,7 @@ index 4e52c79f8f50..8ff8bc4a22b2 100644 static const struct resource axp20x_pek_resources[] = { DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_RIS_EDGE, "PEK_DBR"), DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_FAL_EDGE, "PEK_DBF"), -@@ -369,6 +378,23 @@ static const struct resource axp717_pek_resources[] = { +@@ -370,6 +379,23 @@ static const struct resource axp717_pek_resources[] = { DEFINE_RES_IRQ_NAMED(AXP717_IRQ_PEK_FAL_EDGE, "PEK_DBF"), }; @@ -52,7 +52,7 @@ index 4e52c79f8f50..8ff8bc4a22b2 100644 static const struct resource axp803_pek_resources[] = { DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"), DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"), -@@ -972,6 +998,8 @@ static const struct mfd_cell axp20x_cells[] = { +@@ -973,6 +999,8 @@ static const struct mfd_cell axp20x_cells[] = { }, { .name = "axp20x-battery-power-supply", .of_compatible = "x-powers,axp209-battery-power-supply", @@ -61,7 +61,7 @@ index 4e52c79f8f50..8ff8bc4a22b2 100644 }, { .name = "axp20x-ac-power-supply", .of_compatible = "x-powers,axp202-ac-power-supply", -@@ -1006,6 +1034,8 @@ static const struct mfd_cell axp221_cells[] = { +@@ -1007,6 +1035,8 @@ static const struct mfd_cell axp221_cells[] = { }, { .name = "axp20x-battery-power-supply", .of_compatible = "x-powers,axp221-battery-power-supply", @@ -70,7 +70,7 @@ index 4e52c79f8f50..8ff8bc4a22b2 100644 }, { .name = "axp20x-usb-power-supply", .of_compatible = "x-powers,axp221-usb-power-supply", -@@ -1028,6 +1058,8 @@ static const struct mfd_cell axp223_cells[] = { +@@ -1029,6 +1059,8 @@ static const struct mfd_cell axp223_cells[] = { }, { .name = "axp20x-battery-power-supply", .of_compatible = "x-powers,axp221-battery-power-supply", @@ -79,7 +79,7 @@ index 4e52c79f8f50..8ff8bc4a22b2 100644 }, { .name = "axp20x-regulator", }, { -@@ -1144,6 +1176,8 @@ static const struct mfd_cell axp803_cells[] = { +@@ -1145,6 +1177,8 @@ static const struct mfd_cell axp803_cells[] = { }, { .name = "axp20x-battery-power-supply", .of_compatible = "x-powers,axp813-battery-power-supply", @@ -88,7 +88,7 @@ index 4e52c79f8f50..8ff8bc4a22b2 100644 }, { .name = "axp20x-ac-power-supply", .of_compatible = "x-powers,axp813-ac-power-supply", -@@ -1204,6 +1238,8 @@ static const struct mfd_cell axp813_cells[] = { +@@ -1205,6 +1239,8 @@ static const struct mfd_cell axp813_cells[] = { }, { .name = "axp20x-battery-power-supply", .of_compatible = "x-powers,axp813-battery-power-supply", diff --git a/patch/kernel/sunxi-6.14/patches.megous/misc-modem-power-Power-manager-for-modems.patch b/patch/kernel/sunxi-6.16/patches.megous/misc-modem-power-Power-manager-for-modems.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/misc-modem-power-Power-manager-for-modems.patch rename to patch/kernel/sunxi-6.16/patches.megous/misc-modem-power-Power-manager-for-modems.patch index ca2f317..a0f3f15 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/misc-modem-power-Power-manager-for-modems.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/misc-modem-power-Power-manager-for-modems.patch @@ -1,4 +1,4 @@ -From ec41719fff6c6b38703993687e10ee49d795092e Mon Sep 17 00:00:00 2001 +From 28912983986d99ae9bb3d9db95ba639b9ddea4a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 12 Nov 2017 02:10:15 +0100 Subject: misc: modem-power: Power manager for modems @@ -21,7 +21,7 @@ Signed-off-by: Ondrej Jirman create mode 100644 drivers/misc/modem-power.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig -index 56bc72c7ce4a..c0efb3129661 100644 +index 6b37d61150ee..3b866b34b5a3 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -632,6 +632,13 @@ config MCHP_LAN966X_PCI @@ -39,17 +39,17 @@ index 56bc72c7ce4a..c0efb3129661 100644 source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile -index 545aad06d088..9b20ffa44835 100644 +index d6c917229c45..c5979bb01b86 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile -@@ -75,3 +75,4 @@ lan966x-pci-objs := lan966x_pci.o +@@ -74,3 +74,4 @@ lan966x-pci-objs := lan966x_pci.o lan966x-pci-objs += lan966x_pci.dtbo.o obj-$(CONFIG_MCHP_LAN966X_PCI) += lan966x-pci.o obj-y += keba/ +obj-$(CONFIG_MODEM_POWER) += modem-power.o diff --git a/drivers/misc/modem-power.c b/drivers/misc/modem-power.c new file mode 100644 -index 000000000000..069790db953d +index 000000000000..44fb2dec74ef --- /dev/null +++ b/drivers/misc/modem-power.c @@ -0,0 +1,1990 @@ @@ -1655,7 +1655,7 @@ index 000000000000..069790db953d + if (mpwr->wakeup_irq > 0) + device_init_wakeup(mpwr->dev, false); + -+ del_timer_sync(&mpwr->wd_timer); ++ timer_delete_sync(&mpwr->wd_timer); + cancel_delayed_work_sync(&mpwr->host_ready_work); + + cancel_work_sync(&mpwr->power_work); diff --git a/patch/kernel/sunxi-6.14/patches.megous/mmc-add-delay-after-power-class-selection.patch b/patch/kernel/sunxi-6.16/patches.megous/mmc-add-delay-after-power-class-selection.patch similarity index 78% rename from patch/kernel/sunxi-6.14/patches.megous/mmc-add-delay-after-power-class-selection.patch rename to patch/kernel/sunxi-6.16/patches.megous/mmc-add-delay-after-power-class-selection.patch index cfb8029..25f3bd8 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/mmc-add-delay-after-power-class-selection.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/mmc-add-delay-after-power-class-selection.patch @@ -1,4 +1,4 @@ -From e943000632398ac560d05492d23665c8ea0113cf Mon Sep 17 00:00:00 2001 +From ca85d84df824967ad00111ff14fa9b36189df44a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Fri, 16 Mar 2018 20:31:55 +0100 Subject: mmc: add delay after power class selection @@ -12,10 +12,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c -index 6a23be214543..8ef20ffc9828 100644 +index 1522fd2b517d..917c164426d4 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c -@@ -1840,6 +1840,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, +@@ -1844,6 +1844,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, */ mmc_select_powerclass(card); @@ -24,7 +24,7 @@ index 6a23be214543..8ef20ffc9828 100644 /* * Enable HPI feature (if supported) */ -@@ -1858,6 +1860,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, +@@ -1862,6 +1864,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, } } diff --git a/patch/kernel/sunxi-6.14/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch b/patch/kernel/sunxi-6.16/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch rename to patch/kernel/sunxi-6.16/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch index 808b333..dadc032 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch @@ -1,4 +1,4 @@ -From 2cdaf7e64d4df7a1f4cc2be5f04d0831cc87b0a6 Mon Sep 17 00:00:00 2001 +From 705722410514044ede22de0b7218280cf1b34d59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 15 Feb 2021 09:11:16 +0100 Subject: mmc: sunxi-mmc: Remove runtime-PM diff --git a/patch/kernel/sunxi-6.14/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch b/patch/kernel/sunxi-6.16/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch rename to patch/kernel/sunxi-6.16/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch index 2030dbb..bb8dc64 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch @@ -1,4 +1,4 @@ -From 3b39764173b1cd726267af2c4510f1ac145c1def Mon Sep 17 00:00:00 2001 +From 45da957a46efc19ff40a9acf6fc381dfa42d9acc Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 1 Aug 2023 14:56:33 +0200 Subject: mtd: spi-nor: Add Alliance memory support @@ -57,10 +57,10 @@ index 000000000000..f3f03d458a5c + .nparts = ARRAY_SIZE(alliance_nor_parts), +}; diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c -index 7bb44fabe093..12c3b844e135 100644 +index a41f6a725092..80a121cbb07f 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c -@@ -1967,6 +1967,7 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) +@@ -1940,6 +1940,7 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) } static const struct spi_nor_manufacturer *manufacturers[] = { diff --git a/patch/kernel/sunxi-6.14/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch b/patch/kernel/sunxi-6.16/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch similarity index 81% rename from patch/kernel/sunxi-6.14/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch rename to patch/kernel/sunxi-6.16/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch index 851e4b3..fb8be51 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch @@ -1,4 +1,4 @@ -From 397be32cffa8fe179989e754f15cdfd42d32d325 Mon Sep 17 00:00:00 2001 +From 4b817e9c8cd15ec2c363f8c158930486cdef9d1a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 30 Sep 2019 11:49:54 +0200 Subject: mtd: spi-nor: Add vdd regulator support @@ -11,10 +11,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c -index 19eb98bd6821..7bb44fabe093 100644 +index ac4b960101cc..a41f6a725092 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c -@@ -3596,6 +3596,13 @@ static int spi_nor_probe(struct spi_mem *spimem) +@@ -3569,6 +3569,13 @@ static int spi_nor_probe(struct spi_mem *spimem) if (!nor) return -ENOMEM; diff --git a/patch/kernel/sunxi-6.14/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch b/patch/kernel/sunxi-6.16/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch rename to patch/kernel/sunxi-6.16/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch index 90ae368..a588817 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch @@ -1,4 +1,4 @@ -From 7b4eda27c79bedf2ce5ed68df717b53e84bf15e2 Mon Sep 17 00:00:00 2001 +From 00c9630d3319bbba479a3a58ffd5a528f5108d55 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 20 Aug 2019 14:31:38 +0200 Subject: net: stmmac: sun8i: Add support for enabling a regulator for PHY I/O @@ -16,7 +16,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -index 9c2685cb72d2..6e82638d314a 100644 +index c0985dd48eab..699362e1a299 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -61,6 +61,8 @@ struct emac_variant { @@ -71,7 +71,7 @@ index 9c2685cb72d2..6e82638d314a 100644 } static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) -@@ -1177,6 +1189,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) +@@ -1176,6 +1188,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy), "Failed to get PHY regulator\n"); diff --git a/patch/kernel/sunxi-6.14/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch b/patch/kernel/sunxi-6.16/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch rename to patch/kernel/sunxi-6.16/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch index 21f3ba8..a70f04a 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch @@ -1,4 +1,4 @@ -From e75d0648a45ace112ac64688f87b05b23b8bb1c5 Mon Sep 17 00:00:00 2001 +From 05a950dd52f36a1f6d978103f5c0afd727059f54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 20 Aug 2019 14:29:29 +0200 Subject: net: stmmac: sun8i: Rename PHY regulator variable to regulator_phy @@ -12,7 +12,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -index 7983df0d0eaa..9c2685cb72d2 100644 +index a9f705fd9a22..c0985dd48eab 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -60,7 +60,7 @@ struct emac_variant { @@ -63,7 +63,7 @@ index 7983df0d0eaa..9c2685cb72d2 100644 } static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) -@@ -1172,9 +1172,9 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) +@@ -1171,9 +1171,9 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } /* Optional regulator for PHY */ diff --git a/patch/kernel/sunxi-6.14/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch b/patch/kernel/sunxi-6.16/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch rename to patch/kernel/sunxi-6.16/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch index f7b3898..056d864 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch @@ -1,4 +1,4 @@ -From e79f7a9f2ca1b767b63f924b43ee363e850a911c Mon Sep 17 00:00:00 2001 +From a34a99447dab13e673b4e41d85e417b10696e88f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 27 Mar 2019 13:21:06 +0100 Subject: net: stmmac: sun8i: Use devm_regulator_get for PHY regulator @@ -21,7 +21,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -index 4b7b2582a120..7983df0d0eaa 100644 +index 6c7e8655a7eb..a9f705fd9a22 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -588,12 +588,10 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) @@ -61,7 +61,7 @@ index 4b7b2582a120..7983df0d0eaa 100644 } static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) -@@ -1176,13 +1172,10 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) +@@ -1175,13 +1171,10 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } /* Optional regulator for PHY */ diff --git a/patch/kernel/sunxi-6.14/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch b/patch/kernel/sunxi-6.16/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch rename to patch/kernel/sunxi-6.16/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch index dc481d7..389a913 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch @@ -1,4 +1,4 @@ -From 1734c610a0f7ac87fbbad98ffc8fc13b5b84d066 Mon Sep 17 00:00:00 2001 +From 02cfdd37f75e46936c6882006e5b5bdf669e68ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Fri, 10 Nov 2017 14:29:26 +0100 Subject: nfc: pn544: Add support for VBAT/PVDD regulators diff --git a/patch/kernel/sunxi-6.14/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch b/patch/kernel/sunxi-6.16/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch similarity index 86% rename from patch/kernel/sunxi-6.14/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch rename to patch/kernel/sunxi-6.16/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch index 228851a..31554e6 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch @@ -1,4 +1,4 @@ -From ffba28a2260e995a9170bea3a008d84a130fa583 Mon Sep 17 00:00:00 2001 +From 1f28aefc539c63c3dc6e53986a34ce8e0e4665b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 15 May 2021 21:43:44 +0200 Subject: of: property: fw_devlink: Support allwinner,sram links @@ -14,10 +14,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 22 insertions(+) diff --git a/drivers/of/property.c b/drivers/of/property.c -index 208d922cc24c..8c9f3ea663a6 100644 +index c1feb631e383..934468f306d2 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c -@@ -1455,6 +1455,27 @@ static struct device_node *parse_remote_endpoint(struct device_node *np, +@@ -1488,6 +1488,27 @@ static struct device_node *parse_remote_endpoint(struct device_node *np, return of_graph_get_remote_port_parent(np); } @@ -45,7 +45,7 @@ index 208d922cc24c..8c9f3ea663a6 100644 static const struct supplier_bindings of_supplier_bindings[] = { { .parse_prop = parse_clocks, }, { .parse_prop = parse_interconnects, }, -@@ -1502,6 +1523,7 @@ static const struct supplier_bindings of_supplier_bindings[] = { +@@ -1535,6 +1556,7 @@ static const struct supplier_bindings of_supplier_bindings[] = { .parse_prop = parse_post_init_providers, .fwlink_flags = FWLINK_FLAG_IGNORE, }, diff --git a/patch/kernel/sunxi-6.14/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch b/patch/kernel/sunxi-6.16/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch rename to patch/kernel/sunxi-6.16/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch index bf907bf..5dbdc6f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch @@ -1,4 +1,4 @@ -From c0d7f75b2beb43824f91642088643e90e5eeb19e Mon Sep 17 00:00:00 2001 +From 89b3ba84edbb94bd85ca8e0620e64c160783fec5 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 29 Oct 2022 23:16:51 +0200 Subject: opp: core: Avoid confusing error when no regulator is defined in DT diff --git a/patch/kernel/sunxi-6.14/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch b/patch/kernel/sunxi-6.16/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch rename to patch/kernel/sunxi-6.16/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch index bb0c22c..9e6ef05 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch @@ -1,4 +1,4 @@ -From 0179ed04b8454eca07abc91a41c213423f4d1b1d Mon Sep 17 00:00:00 2001 +From 389a8f337f2a5a931008ea770eb38fcf4ef3b8ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 8 Jun 2020 00:11:06 +0200 Subject: phy: allwinner: sun4i-usb: Add support for usb_role_switch diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch b/patch/kernel/sunxi-6.16/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch similarity index 82% rename from patch/kernel/sunxi-6.14/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch index 173af00..ce6d30b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch @@ -1,4 +1,4 @@ -From aa242f8de59b3c71dd8541e635ddcb3fbe319ff2 Mon Sep 17 00:00:00 2001 +From 6af9316d099683a02dbc2b23e3559e1b3070ace8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Thu, 27 Feb 2020 00:53:17 +0100 Subject: power: axp20x_battery: Allow to set target voltage to 4.35V @@ -11,10 +11,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 5 insertions(+) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index 3c3158f31a48..96d2856ef318 100644 +index 50ca8e110085..a72a4afd43db 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c -@@ -629,6 +629,11 @@ static int axp20x_battery_set_max_voltage(struct axp20x_batt_ps *axp20x_batt, +@@ -632,6 +632,11 @@ static int axp20x_battery_set_max_voltage(struct axp20x_batt_ps *axp20x_batt, val = AXP20X_CHRG_CTRL1_TGT_4_2V; break; diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch b/patch/kernel/sunxi-6.16/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch similarity index 86% rename from patch/kernel/sunxi-6.14/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch index b5db132..cc19699 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch @@ -1,4 +1,4 @@ -From 3128559dbbdafac2ca2b68bf52d1472b349dd330 Mon Sep 17 00:00:00 2001 +From 15eded6ac1440432109ce2337903f0e179078b01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 14 Mar 2021 15:49:34 +0100 Subject: power: axp803: Add interrupts for low battery power condition @@ -13,10 +13,10 @@ Signed-off-by: Ondrej Jirman 2 files changed, 4 insertions(+) diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c -index 8ff8bc4a22b2..5da865469679 100644 +index 3584121faef8..a735c66e0cb6 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c -@@ -393,6 +393,8 @@ static const struct resource axp803_battery_resources[] = { +@@ -394,6 +394,8 @@ static const struct resource axp803_battery_resources[] = { DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_HIGH_END, "BATT_ACT_TEMP_HIGH_END"), DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW, "BATT_ACT_TEMP_LOW"), DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW_END, "BATT_ACT_TEMP_LOW_END"), @@ -26,10 +26,10 @@ index 8ff8bc4a22b2..5da865469679 100644 static const struct resource axp803_pek_resources[] = { diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index 3a5f77219d83..988741b7d3be 100644 +index 81a2d15942b0..1eca1ad48c46 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c -@@ -1098,6 +1098,8 @@ static const struct axp_irq_data axp813_irqs[] = { +@@ -1119,6 +1119,8 @@ static const struct axp_irq_data axp813_irqs[] = { { "BATT_HEALTH_GOOD", axp20x_battery_changed_irq }, { "BATT_CHARGING", axp20x_battery_changed_irq }, { "BATT_CHARGING_DONE", axp20x_battery_changed_irq }, diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch similarity index 92% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch index ed33902..519edc9 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch @@ -1,4 +1,4 @@ -From d997e3a57c6e83fa651b6f9daa80ac308b17c51f Mon Sep 17 00:00:00 2001 +From afb2df35a90d945a1a46e3e848927ef3f9ee2118 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 22 Jun 2020 02:28:01 +0200 Subject: power: supply: Add support for USB_BC_ENABLED and @@ -15,7 +15,7 @@ Signed-off-by: Ondrej Jirman 2 files changed, 4 insertions(+) diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c -index edb058c19c9c..430d64b974c0 100644 +index 439dd0bf8644..16777e88b27a 100644 --- a/drivers/power/supply/power_supply_sysfs.c +++ b/drivers/power/supply/power_supply_sysfs.c @@ -213,6 +213,8 @@ static struct power_supply_attr power_supply_attrs[] __ro_after_init = { @@ -28,7 +28,7 @@ index edb058c19c9c..430d64b974c0 100644 POWER_SUPPLY_ATTR(PRECHARGE_CURRENT), POWER_SUPPLY_ATTR(CHARGE_TERM_CURRENT), diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h -index 6ed53b292162..dec890d882c2 100644 +index 888824592953..4775455b0a46 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -166,6 +166,8 @@ enum power_supply_property { diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch similarity index 85% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch index f33ff73..a6e8f08 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch @@ -1,4 +1,4 @@ -From fcfd714cac86026d77c397e3f52740ab2eb76566 Mon Sep 17 00:00:00 2001 +From 926e070078720fbd916193e2c656d543c9463a96 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 10 Nov 2022 20:05:58 +0100 Subject: power: supply: axp20x-battery: Add support for @@ -12,18 +12,18 @@ Signed-off-by: Ondrej Jirman 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index ba7c45e4bf10..9b4b1b8d09b1 100644 +index b3c493b01bda..26ee5629faff 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c -@@ -127,6 +127,7 @@ struct axp20x_batt_ps { - /* Maximum constant charge current */ +@@ -130,6 +130,7 @@ struct axp20x_batt_ps { unsigned int max_ccc; const struct axp_data *data; + bool ts_disable; + struct power_supply_battery_info *info; }; static int axp20x_battery_get_max_voltage(struct axp20x_batt_ps *axp20x_batt, -@@ -460,6 +461,16 @@ static int axp20x_battery_get_prop(struct power_supply *psy, +@@ -463,6 +464,16 @@ static int axp20x_battery_get_prop(struct power_supply *psy, break; @@ -40,7 +40,7 @@ index ba7c45e4bf10..9b4b1b8d09b1 100644 default: return -EINVAL; } -@@ -914,6 +925,8 @@ static enum power_supply_property axp20x_battery_props[] = { +@@ -917,6 +928,8 @@ static enum power_supply_property axp20x_battery_props[] = { POWER_SUPPLY_PROP_VOLTAGE_MIN, POWER_SUPPLY_PROP_VOLTAGE_OCV, POWER_SUPPLY_PROP_CAPACITY, @@ -49,7 +49,7 @@ index ba7c45e4bf10..9b4b1b8d09b1 100644 }; static enum power_supply_property axp717_battery_props[] = { -@@ -1213,12 +1226,18 @@ static const struct of_device_id axp20x_battery_ps_id[] = { +@@ -1234,12 +1247,18 @@ static const struct of_device_id axp20x_battery_ps_id[] = { }; MODULE_DEVICE_TABLE(of, axp20x_battery_ps_id); @@ -69,7 +69,7 @@ index ba7c45e4bf10..9b4b1b8d09b1 100644 struct device *dev = &pdev->dev; const struct axp_irq_data *irq_data; int irq, ret; -@@ -1256,9 +1275,12 @@ static int axp20x_power_probe(struct platform_device *pdev) +@@ -1277,9 +1296,12 @@ static int axp20x_power_probe(struct platform_device *pdev) axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD; diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch similarity index 85% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch index 82a1d06..04785ac 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch @@ -1,4 +1,4 @@ -From 1f7bdbc2a3c8d4b6deb77a4ef6b7bf5dada6a662 Mon Sep 17 00:00:00 2001 +From 1642baafe656e04566a271195ab49c50bc4f7996 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 27 Aug 2022 20:50:43 +0200 Subject: power: supply: axp20x-battery: Enable poweron by RTC alarm @@ -15,10 +15,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 5 insertions(+) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index 1899af1810fd..ba7c45e4bf10 100644 +index d2c153ee0d88..b3c493b01bda 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c -@@ -1333,6 +1333,11 @@ static int axp20x_power_probe(struct platform_device *pdev) +@@ -1354,6 +1354,11 @@ static int axp20x_power_probe(struct platform_device *pdev) ret = regmap_update_bits(axp20x_batt->regmap, 0x84, 0x37, 0x31); if (ret) goto warn_bat; diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch similarity index 90% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch index 8da1d25..9cb5496 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch @@ -1,4 +1,4 @@ -From e452c5a4a3d43d07132fcd9eaf2b041bddafc3fb Mon Sep 17 00:00:00 2001 +From 21633fc4e1deb07b154781c076d1b8ebf57e6633 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 7 Jan 2025 18:53:23 +0100 Subject: power: supply: axp20x-battery: Improve probe error reporting @@ -11,10 +11,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index 9b4b1b8d09b1..bab9b4a8f623 100644 +index 26ee5629faff..d16ef16f2c61 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c -@@ -1262,16 +1262,15 @@ static int axp20x_power_probe(struct platform_device *pdev) +@@ -1283,16 +1283,15 @@ static int axp20x_power_probe(struct platform_device *pdev) ret = axp20x_batt->data->cfg_iio_chan(pdev, axp20x_batt); if (ret) @@ -36,7 +36,7 @@ index 9b4b1b8d09b1..bab9b4a8f623 100644 axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD; -@@ -1286,20 +1285,17 @@ static int axp20x_power_probe(struct platform_device *pdev) +@@ -1307,20 +1306,17 @@ static int axp20x_power_probe(struct platform_device *pdev) /* Request irqs after registering, as irqs may trigger immediately */ for (irq_data = axp20x_batt->data->irqs; irq_data->name; irq_data++) { irq = platform_get_irq_byname(pdev, irq_data->name); diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch similarity index 86% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch index c5cd63b..ddd02a1 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch @@ -1,4 +1,4 @@ -From 69e253126549eb8af47a0145651f4fc575b1332c Mon Sep 17 00:00:00 2001 +From 17de502af8b957bdd5e09b51410d765a81265f5c Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 2 Apr 2022 02:50:14 +0200 Subject: power: supply: axp20x-battery: Support @@ -12,10 +12,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 31 insertions(+) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index 988741b7d3be..1899af1810fd 100644 +index 1eca1ad48c46..d2c153ee0d88 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c -@@ -317,6 +317,19 @@ static int axp20x_battery_get_prop(struct power_supply *psy, +@@ -320,6 +320,19 @@ static int axp20x_battery_get_prop(struct power_supply *psy, val->intval = !!(reg & AXP20X_PWR_OP_BATT_PRESENT); break; @@ -35,7 +35,7 @@ index 988741b7d3be..1899af1810fd 100644 case POWER_SUPPLY_PROP_STATUS: ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE, ®); -@@ -819,6 +832,21 @@ static int axp20x_battery_set_prop(struct power_supply *psy, +@@ -822,6 +835,21 @@ static int axp20x_battery_set_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: return axp20x_set_max_constant_charge_current(axp20x_batt, val->intval); @@ -57,7 +57,7 @@ index 988741b7d3be..1899af1810fd 100644 case POWER_SUPPLY_PROP_STATUS: switch (val->intval) { case POWER_SUPPLY_STATUS_CHARGING: -@@ -876,6 +904,7 @@ static enum power_supply_property axp20x_battery_props[] = { +@@ -879,6 +907,7 @@ static enum power_supply_property axp20x_battery_props[] = { POWER_SUPPLY_PROP_PRESENT, POWER_SUPPLY_PROP_ONLINE, POWER_SUPPLY_PROP_STATUS, @@ -65,7 +65,7 @@ index 988741b7d3be..1899af1810fd 100644 POWER_SUPPLY_PROP_VOLTAGE_NOW, POWER_SUPPLY_PROP_CURRENT_NOW, POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT, -@@ -907,6 +936,7 @@ static int axp20x_battery_prop_writeable(struct power_supply *psy, +@@ -910,6 +939,7 @@ static int axp20x_battery_prop_writeable(struct power_supply *psy, return psp == POWER_SUPPLY_PROP_STATUS || psp == POWER_SUPPLY_PROP_VOLTAGE_MIN || psp == POWER_SUPPLY_PROP_VOLTAGE_MAX || @@ -73,7 +73,7 @@ index 988741b7d3be..1899af1810fd 100644 psp == POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT || psp == POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX; } -@@ -928,6 +958,7 @@ static const struct power_supply_desc axp209_batt_ps_desc = { +@@ -931,6 +961,7 @@ static const struct power_supply_desc axp209_batt_ps_desc = { .property_is_writeable = axp20x_battery_prop_writeable, .get_property = axp20x_battery_get_prop, .set_property = axp20x_battery_set_prop, diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch similarity index 90% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch index a7196f1..b55a9db 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch @@ -1,4 +1,4 @@ -From c5a7633f0da393dd7ba0d1ea7e7c205470c3c72d Mon Sep 17 00:00:00 2001 +From 026f5b08f9171ca338c2c04376a3b790bb624a60 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 15 Mar 2024 21:48:34 +0100 Subject: power: supply: axp20x-usb-power: Add missing interrupts @@ -13,10 +13,10 @@ Signed-off-by: Ondrej Jirman 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c -index 5da865469679..94651380ecdb 100644 +index a735c66e0cb6..f88a02913390 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c -@@ -347,6 +347,8 @@ static const struct resource axp717_usb_power_supply_resources[] = { +@@ -348,6 +348,8 @@ static const struct resource axp717_usb_power_supply_resources[] = { static const struct resource axp803_usb_power_supply_resources[] = { DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"), DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"), @@ -26,7 +26,7 @@ index 5da865469679..94651380ecdb 100644 static const struct resource axp22x_pek_resources[] = { diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c -index b555ba9bf6ad..44cbd429cb91 100644 +index 0b655274dadb..20c9c0474e75 100644 --- a/drivers/power/supply/axp20x_usb_power.c +++ b/drivers/power/supply/axp20x_usb_power.c @@ -728,6 +728,13 @@ static const char * const axp717_irq_names[] = { diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch similarity index 88% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch index 7ab6ac6..8055ac8 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch @@ -1,4 +1,4 @@ -From 66616b654c38ff3cb0b34b6b676fa13425c40d4e Mon Sep 17 00:00:00 2001 +From d347953a2f22987f457b483eabd0a017981802f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 14 Dec 2020 07:42:08 +0100 Subject: power: supply: axp20x-usb-power: Change Vbus hold voltage to 4.5V @@ -11,7 +11,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 12 insertions(+) diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c -index 9722912268fe..b555ba9bf6ad 100644 +index e75d1e377ac1..0b655274dadb 100644 --- a/drivers/power/supply/axp20x_usb_power.c +++ b/drivers/power/supply/axp20x_usb_power.c @@ -1011,6 +1011,18 @@ static int axp20x_usb_power_probe(struct platform_device *pdev) @@ -30,7 +30,7 @@ index 9722912268fe..b555ba9bf6ad 100644 + return ret; + } + - psy_cfg.of_node = pdev->dev.of_node; + psy_cfg.fwnode = dev_fwnode(&pdev->dev); psy_cfg.drv_data = power; -- diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch similarity index 84% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch index b90a739..945d6c2 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch @@ -1,4 +1,4 @@ -From 008e3cc97745fbba5e3273a5d9395d1791ff8df7 Mon Sep 17 00:00:00 2001 +From 3b5256829d82e7d6c5701c35a2071f5ee1a35763 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Fri, 28 Feb 2020 19:16:46 +0100 Subject: power: supply: axp20x_battery: Add support for reporting OCV @@ -11,10 +11,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 23 insertions(+) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index 96d2856ef318..f19ab493245b 100644 +index a72a4afd43db..551cbe0b0f97 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c -@@ -270,6 +270,25 @@ static int axp717_get_constant_charge_current(struct axp20x_batt_ps *axp, +@@ -273,6 +273,25 @@ static int axp717_get_constant_charge_current(struct axp20x_batt_ps *axp, return 0; } @@ -40,7 +40,7 @@ index 96d2856ef318..f19ab493245b 100644 static int axp20x_battery_get_prop(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) -@@ -368,6 +387,9 @@ static int axp20x_battery_get_prop(struct power_supply *psy, +@@ -371,6 +390,9 @@ static int axp20x_battery_get_prop(struct power_supply *psy, break; @@ -50,7 +50,7 @@ index 96d2856ef318..f19ab493245b 100644 case POWER_SUPPLY_PROP_CAPACITY: /* When no battery is present, return capacity is 100% */ ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE, -@@ -851,6 +873,7 @@ static enum power_supply_property axp20x_battery_props[] = { +@@ -854,6 +876,7 @@ static enum power_supply_property axp20x_battery_props[] = { POWER_SUPPLY_PROP_HEALTH, POWER_SUPPLY_PROP_VOLTAGE_MAX, POWER_SUPPLY_PROP_VOLTAGE_MIN, diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch similarity index 87% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch index b55a095..11b667b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch @@ -1,4 +1,4 @@ -From 1159cc7534f19ea3fad016e3651cce77df029e6f Mon Sep 17 00:00:00 2001 +From be93a3ac7bdf43e7be535abadb38848f5dcc3a8a Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 29 Feb 2020 00:55:09 -0600 Subject: power: supply: axp20x_battery: Fix charging done detection @@ -9,7 +9,7 @@ Signed-off-by: Samuel Holland 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index 1bac1a934614..74a5d53d7cf2 100644 +index 132c0d8f9175..3d64d7c8c47b 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c @@ -38,6 +38,7 @@ @@ -20,7 +20,7 @@ index 1bac1a934614..74a5d53d7cf2 100644 #define AXP20X_PWR_OP_BATT_PRESENT BIT(5) #define AXP20X_PWR_OP_BATT_ACTIVATED BIT(3) #define AXP717_PWR_OP_BATT_PRESENT BIT(3) -@@ -308,12 +309,12 @@ static int axp20x_battery_get_prop(struct power_supply *psy, +@@ -311,12 +312,12 @@ static int axp20x_battery_get_prop(struct power_supply *psy, break; case POWER_SUPPLY_PROP_STATUS: diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch similarity index 87% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch index f063c5e..699a4e2 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch @@ -1,4 +1,4 @@ -From fad659e393bcf094adcd4cd5661a8c19bcb1bdfd Mon Sep 17 00:00:00 2001 +From e52201b57362ee042ea803ce6dfb94e7ad96af1c Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 29 Feb 2020 01:04:33 -0600 Subject: power: supply: axp20x_battery: Monitor battery health @@ -9,10 +9,10 @@ Signed-off-by: Samuel Holland 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index 1c4d5f2eac62..3a5f77219d83 100644 +index ee94d9527153..81a2d15942b0 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c -@@ -123,6 +123,7 @@ struct axp20x_batt_ps { +@@ -125,6 +125,7 @@ struct axp20x_batt_ps { struct iio_channel *batt_chrg_i; struct iio_channel *batt_dischrg_i; struct iio_channel *batt_v; @@ -20,7 +20,7 @@ index 1c4d5f2eac62..3a5f77219d83 100644 /* Maximum constant charge current */ unsigned int max_ccc; const struct axp_data *data; -@@ -362,7 +363,7 @@ static int axp20x_battery_get_prop(struct power_supply *psy, +@@ -365,7 +366,7 @@ static int axp20x_battery_get_prop(struct power_supply *psy, return 0; } @@ -29,7 +29,7 @@ index 1c4d5f2eac62..3a5f77219d83 100644 break; case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT: -@@ -1047,6 +1048,39 @@ static irqreturn_t axp20x_battery_changed_irq(int irq, void *devid) +@@ -1068,6 +1069,39 @@ static irqreturn_t axp20x_battery_changed_irq(int irq, void *devid) return IRQ_HANDLED; } @@ -69,7 +69,7 @@ index 1c4d5f2eac62..3a5f77219d83 100644 static const struct axp_irq_data axp20x_irqs[] = { { "BATT_PLUGIN", axp20x_battery_changed_irq }, { "BATT_REMOVAL", axp20x_battery_changed_irq }, -@@ -1057,6 +1091,24 @@ static const struct axp_irq_data axp20x_irqs[] = { +@@ -1078,6 +1112,24 @@ static const struct axp_irq_data axp20x_irqs[] = { {} }; @@ -94,7 +94,7 @@ index 1c4d5f2eac62..3a5f77219d83 100644 static const struct axp_data axp209_data = { .ccc_scale = 100000, .ccc_offset = 300000, -@@ -1108,7 +1160,7 @@ static const struct axp_data axp813_data = { +@@ -1129,7 +1181,7 @@ static const struct axp_data axp813_data = { .set_max_voltage = axp20x_battery_set_max_voltage, .cfg_iio_chan = axp209_bat_cfg_iio_channels, .set_bat_info = axp209_set_battery_info, @@ -103,7 +103,7 @@ index 1c4d5f2eac62..3a5f77219d83 100644 }; static const struct of_device_id axp20x_battery_ps_id[] = { -@@ -1169,6 +1221,8 @@ static int axp20x_power_probe(struct platform_device *pdev) +@@ -1190,6 +1242,8 @@ static int axp20x_power_probe(struct platform_device *pdev) return PTR_ERR(axp20x_batt->batt); } diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch similarity index 82% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch index 12f0738..e34006f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch @@ -1,6 +1,6 @@ -From 3370f271bac47c366689c2372d201bc48cb99b15 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 29 Feb 2020 01:04:17 -0600 +From 8c7dd5717bd52b20181f230987e1799953e4becc Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sat, 5 Apr 2025 18:14:35 +0200 Subject: power: supply: axp20x_battery: Send uevents for status changes Signed-off-by: Samuel Holland @@ -9,12 +9,12 @@ Signed-off-by: Samuel Holland 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index 74a5d53d7cf2..1c4d5f2eac62 100644 +index 3d64d7c8c47b..ee94d9527153 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c -@@ -90,8 +90,15 @@ - #define AXP717_BAT_CC_MIN_UA 0 - #define AXP717_BAT_CC_MAX_UA 3008000 +@@ -92,8 +92,15 @@ + + #define AXP717_TS_PIN_DISABLE BIT(4) +#define DRVNAME "axp20x-battery-power-supply" + @@ -28,7 +28,7 @@ index 74a5d53d7cf2..1c4d5f2eac62 100644 struct axp_data { int ccc_scale; int ccc_offset; -@@ -106,6 +113,7 @@ struct axp_data { +@@ -108,6 +115,7 @@ struct axp_data { void (*set_bat_info)(struct platform_device *pdev, struct axp20x_batt_ps *axp_batt, struct power_supply_battery_info *info); @@ -36,7 +36,7 @@ index 74a5d53d7cf2..1c4d5f2eac62 100644 }; struct axp20x_batt_ps { -@@ -1030,6 +1038,25 @@ static void axp717_set_battery_info(struct platform_device *pdev, +@@ -1051,6 +1059,25 @@ static void axp717_set_battery_info(struct platform_device *pdev, } } @@ -62,7 +62,7 @@ index 74a5d53d7cf2..1c4d5f2eac62 100644 static const struct axp_data axp209_data = { .ccc_scale = 100000, .ccc_offset = 300000, -@@ -1040,6 +1067,7 @@ static const struct axp_data axp209_data = { +@@ -1061,6 +1088,7 @@ static const struct axp_data axp209_data = { .set_max_voltage = axp20x_battery_set_max_voltage, .cfg_iio_chan = axp209_bat_cfg_iio_channels, .set_bat_info = axp209_set_battery_info, @@ -70,7 +70,7 @@ index 74a5d53d7cf2..1c4d5f2eac62 100644 }; static const struct axp_data axp221_data = { -@@ -1053,6 +1081,7 @@ static const struct axp_data axp221_data = { +@@ -1074,6 +1102,7 @@ static const struct axp_data axp221_data = { .set_max_voltage = axp22x_battery_set_max_voltage, .cfg_iio_chan = axp209_bat_cfg_iio_channels, .set_bat_info = axp209_set_battery_info, @@ -78,7 +78,7 @@ index 74a5d53d7cf2..1c4d5f2eac62 100644 }; static const struct axp_data axp717_data = { -@@ -1065,6 +1094,7 @@ static const struct axp_data axp717_data = { +@@ -1086,6 +1115,7 @@ static const struct axp_data axp717_data = { .set_max_voltage = axp717_battery_set_max_voltage, .cfg_iio_chan = axp717_bat_cfg_iio_channels, .set_bat_info = axp717_set_battery_info, @@ -86,7 +86,7 @@ index 74a5d53d7cf2..1c4d5f2eac62 100644 }; static const struct axp_data axp813_data = { -@@ -1078,6 +1108,7 @@ static const struct axp_data axp813_data = { +@@ -1099,6 +1129,7 @@ static const struct axp_data axp813_data = { .set_max_voltage = axp20x_battery_set_max_voltage, .cfg_iio_chan = axp209_bat_cfg_iio_channels, .set_bat_info = axp209_set_battery_info, @@ -94,7 +94,7 @@ index 74a5d53d7cf2..1c4d5f2eac62 100644 }; static const struct of_device_id axp20x_battery_ps_id[] = { -@@ -1099,11 +1130,13 @@ MODULE_DEVICE_TABLE(of, axp20x_battery_ps_id); +@@ -1120,11 +1151,13 @@ MODULE_DEVICE_TABLE(of, axp20x_battery_ps_id); static int axp20x_power_probe(struct platform_device *pdev) { @@ -109,7 +109,7 @@ index 74a5d53d7cf2..1c4d5f2eac62 100644 if (!of_device_is_available(pdev->dev.of_node)) return -ENODEV; -@@ -1141,6 +1174,25 @@ static int axp20x_power_probe(struct platform_device *pdev) +@@ -1162,6 +1195,25 @@ static int axp20x_power_probe(struct platform_device *pdev) power_supply_put_battery_info(axp20x_batt->batt, info); } @@ -135,7 +135,7 @@ index 74a5d53d7cf2..1c4d5f2eac62 100644 /* * Update max CCC to a valid value if battery info is present or set it * to current register value by default. -@@ -1206,7 +1258,7 @@ static int axp20x_power_probe(struct platform_device *pdev) +@@ -1227,7 +1279,7 @@ static int axp20x_power_probe(struct platform_device *pdev) static struct platform_driver axp20x_batt_driver = { .probe = axp20x_power_probe, .driver = { diff --git a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch similarity index 93% rename from patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch rename to patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch index 6886f02..59b0d3b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch @@ -1,4 +1,4 @@ -From c402714c643950ffe020804c98bb8e23e31ae050 Mon Sep 17 00:00:00 2001 +From feac05e823e4620f60fe4590fd1f0592ec849b0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 23 Sep 2020 14:59:41 +0200 Subject: power: supply: axp20x_battery: Setup thermal regulation @@ -14,10 +14,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 53 insertions(+) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c -index f19ab493245b..1bac1a934614 100644 +index 551cbe0b0f97..132c0d8f9175 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c -@@ -1146,6 +1146,59 @@ static int axp20x_power_probe(struct platform_device *pdev) +@@ -1167,6 +1167,59 @@ static int axp20x_power_probe(struct platform_device *pdev) */ axp20x_get_constant_charge_current(axp20x_batt, &axp20x_batt->max_ccc); diff --git a/patch/kernel/sunxi-6.14/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch b/patch/kernel/sunxi-6.16/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch rename to patch/kernel/sunxi-6.16/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch index 35711ff..1090572 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch @@ -1,4 +1,4 @@ -From b6d9a904952e90d848cb7dc88a4f1e2a9ae8b438 Mon Sep 17 00:00:00 2001 +From 54fa0ad6e8f828ce63c8ec1518b350d2dc46cece Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 5 Oct 2019 15:10:11 +0200 Subject: regulator: Add simple driver for enabling a regulator from userspace @@ -15,7 +15,7 @@ Signed-off-by: Ondrej Jirman create mode 100644 drivers/regulator/userspace-consumer-of.c diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig -index 39297f7d8177..db7f70e9a015 100644 +index 05e32d764028..e34b9140c2d5 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -66,6 +66,15 @@ config REGULATOR_NETLINK_EVENTS @@ -35,7 +35,7 @@ index 39297f7d8177..db7f70e9a015 100644 tristate "Marvell 88PG86X voltage regulators" depends on I2C diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile -index 3d5a803dce8a..267a09e14295 100644 +index 524e026c0273..a11bc8ff1c78 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_OF) += of_regulator.o diff --git a/patch/kernel/sunxi-6.14/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch b/patch/kernel/sunxi-6.16/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch similarity index 91% rename from patch/kernel/sunxi-6.14/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch rename to patch/kernel/sunxi-6.16/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch index 968e1a5..066983f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch @@ -1,4 +1,4 @@ -From 8a7a8e2c300da9d317bc12cad53e4f495978b476 Mon Sep 17 00:00:00 2001 +From d538a4de6626fb50b3c0783a3757390bd37a731c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 8 Jun 2020 00:15:04 +0200 Subject: regulator: axp20x: Add support for vin-supply for drivevbus @@ -13,10 +13,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c -index dca99cfb7cbb..0f2480316d5a 100644 +index da891415efc0..2c2a0b38f969 100644 --- a/drivers/regulator/axp20x-regulator.c +++ b/drivers/regulator/axp20x-regulator.c -@@ -1734,12 +1734,36 @@ static int axp20x_regulator_probe(struct platform_device *pdev) +@@ -1728,12 +1728,36 @@ static int axp20x_regulator_probe(struct platform_device *pdev) } if (drivevbus) { diff --git a/patch/kernel/sunxi-6.14/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch b/patch/kernel/sunxi-6.16/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch similarity index 86% rename from patch/kernel/sunxi-6.14/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch rename to patch/kernel/sunxi-6.16/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch index 6a74bb5..3f6ac1b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch @@ -1,4 +1,4 @@ -From 3071728a895acee0ad98869a26eac2d25376718d Mon Sep 17 00:00:00 2001 +From 04548a9110db778a99c5a27fe657fa6f6dae72e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 18 Feb 2020 23:57:20 +0100 Subject: regulator: axp20x: Enable over-temperature protection and 16s reset @@ -12,7 +12,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 7 insertions(+) diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c -index f304d393f5e0..95bb3ffd76b9 100644 +index f48d03be42f8..43dba61ca59b 100644 --- a/drivers/regulator/axp20x-regulator.c +++ b/drivers/regulator/axp20x-regulator.c @@ -92,6 +92,8 @@ @@ -24,7 +24,7 @@ index f304d393f5e0..95bb3ffd76b9 100644 #define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0) #define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0) -@@ -1778,6 +1780,11 @@ static int axp20x_regulator_probe(struct platform_device *pdev) +@@ -1772,6 +1774,11 @@ static int axp20x_regulator_probe(struct platform_device *pdev) } } diff --git a/patch/kernel/sunxi-6.14/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch b/patch/kernel/sunxi-6.16/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch similarity index 91% rename from patch/kernel/sunxi-6.14/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch rename to patch/kernel/sunxi-6.16/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch index 64cc3bc..2ebc10a 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch @@ -1,4 +1,4 @@ -From 161f933ab81767414c88de145df9220a8a66ae2e Mon Sep 17 00:00:00 2001 +From 23d656fa1e7f3d985b84ae9c946e4b7cda091c4e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 9 Jun 2020 22:00:36 +0200 Subject: regulator: axp20x: Turn N_VBUSEN to input on x-powers,sense-vbus-en @@ -30,10 +30,10 @@ index c4e3547e02e9..ec4927dfe9dc 100644 power-supply = <®_ldo_io0>; lth-brightness = <10>; diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c -index 0f2480316d5a..f304d393f5e0 100644 +index 2c2a0b38f969..f48d03be42f8 100644 --- a/drivers/regulator/axp20x-regulator.c +++ b/drivers/regulator/axp20x-regulator.c -@@ -1733,6 +1733,14 @@ static int axp20x_regulator_probe(struct platform_device *pdev) +@@ -1727,6 +1727,14 @@ static int axp20x_regulator_probe(struct platform_device *pdev) &aldo1_name); } diff --git a/patch/kernel/sunxi-6.14/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch b/patch/kernel/sunxi-6.16/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch rename to patch/kernel/sunxi-6.16/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch index 11e8579..44938f4 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch @@ -1,4 +1,4 @@ -From 6a9067668d70903cdeb7420f6e759c0f175390bb Mon Sep 17 00:00:00 2001 +From df411c05c3a63394a9d316b077aa315010028128 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Thu, 17 Oct 2019 23:23:17 +0200 Subject: regulator: tp65185: Add hwmon device for reading temperature diff --git a/patch/kernel/sunxi-6.14/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch b/patch/kernel/sunxi-6.16/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch rename to patch/kernel/sunxi-6.16/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch index 6a69fc0..3f7ee94 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch @@ -1,4 +1,4 @@ -From 654021b95149522cd06ce47f7378a5ca0025aef4 Mon Sep 17 00:00:00 2001 +From 2f3a3e1cafddcf030243c64795ef125d82796fe6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 5 Oct 2019 15:12:51 +0200 Subject: regulator: tp65185x: Add tp65185x eInk panel regulator driver @@ -21,7 +21,7 @@ Signed-off-by: Ondrej Jirman create mode 100644 drivers/regulator/tp65185x.c diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig -index db7f70e9a015..887d8a78a1ba 100644 +index e34b9140c2d5..f11d74e41bf4 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1729,4 +1729,12 @@ config REGULATOR_QCOM_LABIBB @@ -38,7 +38,7 @@ index db7f70e9a015..887d8a78a1ba 100644 + endif diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile -index 267a09e14295..c0266414e3e4 100644 +index a11bc8ff1c78..76e18cbfd63f 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -202,5 +202,6 @@ obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o diff --git a/patch/kernel/sunxi-6.14/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch b/patch/kernel/sunxi-6.16/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch similarity index 88% rename from patch/kernel/sunxi-6.14/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch rename to patch/kernel/sunxi-6.16/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch index 59e01a9..2fbb945 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch @@ -1,4 +1,4 @@ -From 8952f8ddf5ac1e61907aed9d5ec6f061175efd36 Mon Sep 17 00:00:00 2001 +From 42dea1676c644552b72e4723f2c004f33d89cf31 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 2 Mar 2024 15:08:57 +0100 Subject: rtc: Print which error caused RTC read failure @@ -13,7 +13,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c -index e31fa0ad127e..2f14aecf0e24 100644 +index b88cd4fb295b..47d1c9d835a8 100644 --- a/drivers/rtc/class.c +++ b/drivers/rtc/class.c @@ -66,7 +66,8 @@ static void rtc_hctosys(struct rtc_device *rtc) diff --git a/patch/kernel/sunxi-6.14/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch b/patch/kernel/sunxi-6.16/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch rename to patch/kernel/sunxi-6.16/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch index 1327813..e6551d5 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch @@ -1,4 +1,4 @@ -From 78d0c26df5a45af3c229534210c1a73b91a7f2fd Mon Sep 17 00:00:00 2001 +From 8e97daae69f2398f5da25a772f73972d7a3aedf4 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 2 Jan 2021 15:52:27 -0600 Subject: rtc: sun6i: Allow RTC wakeup after shutdown diff --git a/patch/kernel/sunxi-6.14/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch b/patch/kernel/sunxi-6.16/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch rename to patch/kernel/sunxi-6.16/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch index e2cd38c..867f704 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch @@ -1,4 +1,4 @@ -From d0f048c22adc859780fb354f0f229ef524306066 Mon Sep 17 00:00:00 2001 +From 46e3509bf3833f9da3d9cbcb9a35da9b274bf66f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 12 Nov 2017 23:09:14 +0100 Subject: sound: soc: ac100-codec: Support analog part of X-Powers AC100 codec diff --git a/patch/kernel/sunxi-6.14/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch b/patch/kernel/sunxi-6.16/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch rename to patch/kernel/sunxi-6.16/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch index e305ebd..2ab210b 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch @@ -1,4 +1,4 @@ -From 098efa67e28d6ed17911b54030337059db3ff7a9 Mon Sep 17 00:00:00 2001 +From bff7f6b41a9006e82ece2052f168aaa368b00eec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 9 Feb 2020 17:58:59 +0100 Subject: sound: soc: sun8i-codec: Add support for digital part of the AC100 @@ -39,7 +39,7 @@ index 7b2b3bcb062e..f87b061f59b2 100644 Say Y or M if you want to add sun8i digital audio codec support. diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c -index b195ddc5d5cf..d6408c7af76c 100644 +index 9d28c675fb69..57ae3ea2dbff 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -21,7 +21,9 @@ diff --git a/patch/kernel/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch b/patch/kernel/sunxi-6.16/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch rename to patch/kernel/sunxi-6.16/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch index 34bc969..3eb4012 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch @@ -1,4 +1,4 @@ -From a30a50421a3d54842e8f42974617c24aa7512fe6 Mon Sep 17 00:00:00 2001 +From ce8b984be644b942b6462e4e76fd42fa0a672724 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 2 Sep 2019 14:51:17 +0200 Subject: sunxi: Use dev_err_probe to handle EPROBE_DEFER errors diff --git a/patch/kernel/sunxi-6.14/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch b/patch/kernel/sunxi-6.16/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch rename to patch/kernel/sunxi-6.16/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch index 8826a4a..81a67fd 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch @@ -1,4 +1,4 @@ -From a1a6076e6a12342802c48ab522e841b8386ab0fc Mon Sep 17 00:00:00 2001 +From bdd2bbf85958c82988e12d961d8638f9a35c6480 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Wed, 8 Jul 2020 12:21:14 +0200 Subject: thermal: sun8i: Be loud when probe fails diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch index ab7a192..298e99d 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch @@ -1,4 +1,4 @@ -From b5e1f014248677c77d0ba5a410b27a215fa067ac Mon Sep 17 00:00:00 2001 +From c911506dcbf05dfd6d47832369b20c295f72d543 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 7 Sep 2023 14:07:26 +0200 Subject: usb: gadget: Fix dangling pointer in netdev private data @@ -120,7 +120,7 @@ index 6de81ea17274..b1e1a26808dd 100644 static struct usb_function *eem_alloc(struct usb_function_instance *fi) diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c -index f60576a65ca6..454a451491b1 100644 +index 58b0dd575af3..a27fd479030c 100644 --- a/drivers/usb/gadget/function/f_ncm.c +++ b/drivers/usb/gadget/function/f_ncm.c @@ -1455,14 +1455,13 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) @@ -140,7 +140,7 @@ index f60576a65ca6..454a451491b1 100644 us = usb_gstrings_attach(cdev, ncm_strings, ARRAY_SIZE(ncm_string_defs)); if (IS_ERR(us)) { -@@ -1729,6 +1728,8 @@ static void ncm_free(struct usb_function *f) +@@ -1728,6 +1727,8 @@ static void ncm_free(struct usb_function *f) static void ncm_unbind(struct usb_configuration *c, struct usb_function *f) { struct f_ncm *ncm = func_to_ncm(f); @@ -149,7 +149,7 @@ index f60576a65ca6..454a451491b1 100644 DBG(c->cdev, "ncm unbind\n"); -@@ -1747,6 +1748,8 @@ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f) +@@ -1746,6 +1747,8 @@ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f) kfree(ncm->notify_req->buf); usb_ep_free_request(ncm->notify, ncm->notify_req); diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch index 501c5fb..6a8e506 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch @@ -1,4 +1,4 @@ -From 0766c518fb42f94f9ae7c24dcdaf79423eaa3b43 Mon Sep 17 00:00:00 2001 +From 6e1d44fb6e46cdccb0b11f619e7074331d82069a Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 6 Mar 2023 01:19:52 +0100 Subject: usb: musb: sunxi: Avoid enabling host side code on SoCs where it's @@ -21,7 +21,7 @@ Signed-off-by: Ondrej Jirman 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c -index 7f349f5e781d..521074d68c3b 100644 +index cbbb27178024..8075fa45eb85 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -976,6 +976,16 @@ static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl) @@ -42,7 +42,7 @@ index 7f349f5e781d..521074d68c3b 100644 WARNING("unhandled DISCONNECT transition (%s)\n", musb_otg_state_string(musb)); diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c -index eac1cde86be3..e7b9c9bd56aa 100644 +index a6bd3e968cc7..70caed0fffc5 100644 --- a/drivers/usb/musb/sunxi.c +++ b/drivers/usb/musb/sunxi.c @@ -350,12 +350,6 @@ static int sunxi_musb_set_mode(struct musb *musb, u8 mode) diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch index 6bba1f6..5f44d62 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch @@ -1,4 +1,4 @@ -From cf701dfb5650ddb3cd4b83baa0715c6cb7c3fc5e Mon Sep 17 00:00:00 2001 +From 60910eef7307569a6c87c9f0b25becd2f316720d Mon Sep 17 00:00:00 2001 From: Thomas Thorne Date: Tue, 20 Sep 2022 20:34:57 -0400 Subject: usb: serial: option: add 'reset_resume' callback for WWAN devices diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch index 753bdb8..904c7e4 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch @@ -1,4 +1,4 @@ -From d7895c7ef2ffbb7c8ad7e949a4427e82c77150e6 Mon Sep 17 00:00:00 2001 +From 1a52324dc072ea44c67c46b88dd8bb84502a50c7 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 5 Sep 2022 00:56:07 +0200 Subject: usb: typec: altmodes: displayport: Respect DP_CAP_RECEPTACLE bit diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch index f9f8fa1..c58f955 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch @@ -1,4 +1,4 @@ -From 08c64a2d7b390c78dccd932d6c8f53127bbc18e3 Mon Sep 17 00:00:00 2001 +From 7b487bc5dca0224aa0720ebf4e2dc9a2b244bf62 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Thu, 13 Feb 2020 15:37:25 +0100 Subject: usb: typec: anx7688: Add driver for ANX7688 USB-C HDMI bridge @@ -39,8 +39,8 @@ Signed-off-by: Ondrej Jirman --- drivers/usb/typec/Kconfig | 12 + drivers/usb/typec/Makefile | 1 + - drivers/usb/typec/anx7688.c | 2237 +++++++++++++++++++++++++++++++++++ - 3 files changed, 2250 insertions(+) + drivers/usb/typec/anx7688.c | 2196 +++++++++++++++++++++++++++++++++++ + 3 files changed, 2209 insertions(+) create mode 100644 drivers/usb/typec/anx7688.c diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig @@ -87,10 +87,10 @@ index 7a368fea61bc..3f8ff94ad294 100644 obj-$(CONFIG_TYPEC_RT1719) += rt1719.o diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c new file mode 100644 -index 000000000000..fa1d3496af73 +index 000000000000..e2ac4ae4a7cd --- /dev/null +++ b/drivers/usb/typec/anx7688.c -@@ -0,0 +1,2237 @@ +@@ -0,0 +1,2196 @@ +/* + * ANX7688 USB-C HDMI bridge/PD driver + * @@ -729,14 +729,6 @@ index 000000000000..fa1d3496af73 + if (ret) + dev_err(dev, "failed to offline vbus_in\n"); + -+ val.intval = 1; -+ dev_dbg(dev, "enabling USB BC 1.2 detection\n"); -+ ret = power_supply_set_property(anx7688->vbus_in_supply, -+ POWER_SUPPLY_PROP_USB_BC_ENABLED, -+ &val); -+ if (ret) -+ dev_err(dev, "failed to enabled USB BC1.2 detection\n"); -+ + clear_bit(ANX7688_F_CONNECTED, anx7688->flags); +} + @@ -1915,17 +1907,8 @@ index 000000000000..fa1d3496af73 + + if (current_limit) { + /* -+ * Disable BC1.2 detection, because we'll be setting -+ * a current limit determined by USB-PD ++ * Set a current limit determined by USB-PD + */ -+ val.intval = 0; -+ dev_dbg(dev, "disabling USB BC 1.2 detection\n"); -+ ret = power_supply_set_property(anx7688->vbus_in_supply, -+ POWER_SUPPLY_PROP_USB_BC_ENABLED, -+ &val); -+ if (ret) -+ dev_err(dev, "failed to disable USB BC1.2 detection\n"); -+ + val.intval = current_limit * 1000; + dev_dbg(dev, "setting vbus_in current limit to %d mA\n", current_limit); + ret = power_supply_set_property(anx7688->vbus_in_supply, @@ -1939,27 +1922,13 @@ index 000000000000..fa1d3496af73 + * Use the result of BC1.2 detection performed by PMIC. + */ + ret = power_supply_get_property(anx7688->vbus_in_supply, -+ POWER_SUPPLY_PROP_USB_BC_ENABLED, ++ POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, + &val); + if (ret) -+ dev_err(dev, "failed to get USB BC1.2 detection status\n"); -+ -+ if (ret != 0 || val.intval == 0) { -+ /* -+ * If BC is disabled or we can't get its status, -+ * set conservative 500mA limit. Otherwise leave -+ * the limit to BC1.2. -+ */ -+ val.intval = 500 * 1000; -+ dev_dbg(dev, "setting vbus_in current limit to %d mA\n", ++ dev_err(dev, "failed to get vbus_in current limit\n"); ++ if (ret == 0) ++ dev_dbg(dev, "vbus_in current limit is %d mA\n", + val.intval / 1000); -+ ret = power_supply_set_property(anx7688->vbus_in_supply, -+ POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, -+ &val); -+ if (ret) -+ dev_err(dev, "failed to set vbus_in current to %d mA\n", -+ val.intval / 1000); -+ } + } + + /* Turn on VBUS power path inside PMIC. */ @@ -2025,7 +1994,6 @@ index 000000000000..fa1d3496af73 + struct anx7688 *anx7688; + struct device *dev = &client->dev; + struct typec_capability typec_cap = { }; -+ union power_supply_propval psy_val; + int i, vid_h, vid_l; + int irq_cabledet; + int ret = 0; @@ -2100,7 +2068,7 @@ index 000000000000..fa1d3496af73 + return irq_cabledet; + } + -+ ret = devm_device_add_groups(&client->dev, anx7688_groups); ++ ret = device_add_groups(&client->dev, anx7688_groups); + if (ret) + return ret; + @@ -2180,15 +2148,6 @@ index 000000000000..fa1d3496af73 + + // make sure BC1.2 detection in PMIC is enabled + anx7688->last_bc_result = -1; -+ psy_val.intval = 1; -+ dev_dbg(dev, "enabling USB BC 1.2 detection\n"); -+ ret = power_supply_set_property(anx7688->vbus_in_supply, -+ POWER_SUPPLY_PROP_USB_BC_ENABLED, -+ &psy_val); -+ if (ret) { -+ dev_err(anx7688->dev, "failed to enable BC1.2 detection\n"); -+ goto err_cport; -+ } + + ret = devm_request_irq(dev, irq_cabledet, anx7688_irq_plug_handler, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, @@ -2246,7 +2205,7 @@ index 000000000000..fa1d3496af73 + + power_supply_unreg_notifier(&anx7688->vbus_in_nb); + -+ del_timer_sync(&anx7688->work_timer); ++ timer_delete_sync(&anx7688->work_timer); + + cancel_delayed_work_sync(&anx7688->work); + @@ -2269,7 +2228,7 @@ index 000000000000..fa1d3496af73 +{ + struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev)); + -+ del_timer_sync(&anx7688->work_timer); ++ timer_delete_sync(&anx7688->work_timer); + cancel_delayed_work_sync(&anx7688->work); + + regulator_disable(anx7688->supplies[ANX7688_I2C_INDEX].consumer); diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch index 0e3fd9f..28b9f6f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch @@ -1,4 +1,4 @@ -From 709e2922a1a3df25257575a268c61d76821ca1bc Mon Sep 17 00:00:00 2001 +From 7f9b97367d67bca15ee4f8b401d21932e42a4953 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 14 Nov 2021 01:14:25 +0100 Subject: usb: typec: fusb302: Add OF extcon support diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch index 2595cd2..670de10 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch @@ -1,4 +1,4 @@ -From 4f7d79c40e49fd119dbd6ee104c1c881528ce595 Mon Sep 17 00:00:00 2001 +From 510ed83d8f8db0ce0ed226befaf675eaf1e31c48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 20 Nov 2021 14:35:10 +0100 Subject: usb: typec: fusb302: Clear interrupts before we start toggling diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch index 8ba6789..01777d5 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch @@ -1,4 +1,4 @@ -From e1b00df124f5b8feb982559b0cd5c31d18ebebae Mon Sep 17 00:00:00 2001 +From d8abc08100197b4d60fcae9cd26d0fe8072a9c4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 7 Nov 2021 19:29:06 +0100 Subject: usb: typec: fusb302: Extend debugging interface with driver state diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch index 8330ea2..12fb6f0 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch @@ -1,4 +1,4 @@ -From 147bad79f8711565de8231fb6763cadeac0e7eed Mon Sep 17 00:00:00 2001 +From faab445a4650b84a873d16624accfa85baf528c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sat, 20 Nov 2021 14:33:58 +0100 Subject: usb: typec: fusb302: Fix register definitions diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch similarity index 98% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch index 375cbc7..0e8f470 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch @@ -1,4 +1,4 @@ -From e678c93a59c3442d081762fcaaad8e5af760a5e5 Mon Sep 17 00:00:00 2001 +From 2a0910be8800f26893e93ac39b65055255a23d37 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 23 Nov 2021 17:55:34 +0100 Subject: usb: typec: fusb302: More useful of logging status on interrupt diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch index 0fcc83b..200c8dd 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch @@ -1,4 +1,4 @@ -From b4c45356612f9188c1cdd64419c60f262921410b Mon Sep 17 00:00:00 2001 +From 6095566e63825a57b55331c3e3efe8e802176ed7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 23 Nov 2021 17:53:27 +0100 Subject: usb: typec: fusb302: Retry reading of CC pins status if activity is diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch index 7fcb873..14bd42f 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch @@ -1,4 +1,4 @@ -From 9e2282a1cf5c500f3805b1cbfbedc550ea74f921 Mon Sep 17 00:00:00 2001 +From 4001ec5db264f20b12bee2b12c35508f3681a48f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 7 Nov 2021 19:28:27 +0100 Subject: usb: typec: fusb302: Set the current before enabling pullups diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch index 9d28fb2..6edd372 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch @@ -1,4 +1,4 @@ -From edb5ad67b7842d4fc9758e2cdb010a7835089d50 Mon Sep 17 00:00:00 2001 +From 2ac85ef0a079e9cab6169eec529eee3f8887a783 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 30 Jan 2022 23:46:37 +0100 Subject: usb: typec: fusb302: Slightly increase wait time for BC1.2 result diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch index b040b79..6529dd4 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch @@ -1,4 +1,4 @@ -From 190f76e5c4c74c2cff9dc8cec5158712638f68eb Mon Sep 17 00:00:00 2001 +From 8aa4a83137634252a2116022d2d532d9b93b4bd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 23 Nov 2021 17:57:06 +0100 Subject: usb: typec: fusb302: Update VBUS state even if VBUS interrupt is not diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch similarity index 96% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch index 958cd0d..f7eb187 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch @@ -1,4 +1,4 @@ -From 6330c7bba3992991c37f3204828293a3cda064a9 Mon Sep 17 00:00:00 2001 +From bc1f4f90872ff70b4dbfb0ad3c0804d533aad023 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 18 Feb 2023 00:38:44 +0100 Subject: usb: typec: tcpm: Fix PD devices/capabilities registration @@ -15,7 +15,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c -index 01e1a2c066c7..9f2e376aafd6 100644 +index 3b59bea56f8e..ce96f3d58e02 100644 --- a/drivers/usb/typec/tcpm/tcpm.c +++ b/drivers/usb/typec/tcpm/tcpm.c @@ -3057,15 +3057,22 @@ static int tcpm_register_source_caps(struct tcpm_port *port) diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-tcpm-Improve-logs.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-tcpm-Improve-logs.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-tcpm-Improve-logs.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-tcpm-Improve-logs.patch index d85ac5d..e5ba023 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-tcpm-Improve-logs.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-tcpm-Improve-logs.patch @@ -1,4 +1,4 @@ -From aa7b2907c1dd687c07d1a8245d7c01d1b05f4aa2 Mon Sep 17 00:00:00 2001 +From ec3c952ba0a79a119796f67dad5f6831cf57e6d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 23 Nov 2021 17:58:05 +0100 Subject: usb: typec: tcpm: Improve logs @@ -11,7 +11,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c -index 9f2e376aafd6..d44e12fb2a53 100644 +index ce96f3d58e02..b6008a2b3efa 100644 --- a/drivers/usb/typec/tcpm/tcpm.c +++ b/drivers/usb/typec/tcpm/tcpm.c @@ -986,10 +986,13 @@ static int tcpm_pd_transmit(struct tcpm_port *port, diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch similarity index 94% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch index c7ace71..7f82a8e 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch @@ -1,4 +1,4 @@ -From c02b2e7f1fc2126867ea3500684704c3a7006fd1 Mon Sep 17 00:00:00 2001 +From 8be54495513b6fc2dc15e1131f1798084410c20d Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sun, 14 Aug 2022 16:23:28 +0200 Subject: usb: typec: tcpm: Unregister altmodes before registering new ones @@ -34,7 +34,7 @@ Signed-off-by: Ondrej Jirman 1 file changed, 3 insertions(+) diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c -index 2c92996954b2..01e1a2c066c7 100644 +index 3dc8e89d4349..3b59bea56f8e 100644 --- a/drivers/usb/typec/tcpm/tcpm.c +++ b/drivers/usb/typec/tcpm/tcpm.c @@ -1798,6 +1798,9 @@ static void tcpm_register_partner_altmodes(struct tcpm_port *port) diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch similarity index 99% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch index 9a3d19f..5a78cd8 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch @@ -1,4 +1,4 @@ -From c51b4cd25c8224ea7667def456cb55f18d8e5d5a Mon Sep 17 00:00:00 2001 +From 0dd8089753a3726cf180a5b521b75295e67bd44d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Sun, 7 Nov 2021 19:24:40 +0100 Subject: usb: typec: typec-extcon: Add typec -> extcon bridge driver diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch similarity index 95% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch index d6fb880..041cf26 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch @@ -1,4 +1,4 @@ -From 0ef3b1cee239d5a9ae7bc7e8ad075ac1fef5ed84 Mon Sep 17 00:00:00 2001 +From 95d89a8fc260eaa3a9675178b4571d3f03823258 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 9 Feb 2023 20:33:50 +0100 Subject: usb: typec: typec-extcon: Allow to force reset on each mux change diff --git a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch similarity index 91% rename from patch/kernel/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch rename to patch/kernel/sunxi-6.16/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch index 2faaec7..8b76bcd 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch @@ -1,4 +1,4 @@ -From 169c2c30b74c8ecb334823420b30da6030e48247 Mon Sep 17 00:00:00 2001 +From 79cf7afe5b1cce9ff77f6c4f8b58f0fdf47a013f Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 23 Mar 2022 14:21:34 +0100 Subject: usb: typec: typec-extcon: Enable debugging for now diff --git a/patch/kernel/sunxi-6.14/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch b/patch/kernel/sunxi-6.16/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch similarity index 97% rename from patch/kernel/sunxi-6.14/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch rename to patch/kernel/sunxi-6.16/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch index 7f94064..c5f9243 100644 --- a/patch/kernel/sunxi-6.14/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch +++ b/patch/kernel/sunxi-6.16/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch @@ -1,4 +1,4 @@ -From 1a8de735c0b99b2d9aa538603431e63bf121bf0a Mon Sep 17 00:00:00 2001 +From 51064d247051fb8032a0ea42f26a9996d7634364 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Tue, 24 Sep 2019 17:53:02 +0200 Subject: video: fbdev: eInk display driver for A13 based PocketBooks @@ -11,11 +11,13 @@ Signed-off-by: Ondrej Jirman --- drivers/video/fbdev/Kconfig | 12 + drivers/video/fbdev/Makefile | 4 + - drivers/video/fbdev/sun5i-eink-neon.c | 49 ++ - drivers/video/fbdev/sun5i-eink.c | 1156 +++++++++++++++++++++++++ - 4 files changed, 1221 insertions(+) + drivers/video/fbdev/sun5i-eink-neon.c | 51 ++ + drivers/video/fbdev/sun5i-eink.c | 1155 +++++++++++++++++++++++++ + drivers/video/fbdev/sun5i-eink.h | 7 + + 5 files changed, 1229 insertions(+) create mode 100644 drivers/video/fbdev/sun5i-eink-neon.c create mode 100644 drivers/video/fbdev/sun5i-eink.c + create mode 100644 drivers/video/fbdev/sun5i-eink.h diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index 55c6686f091e..5685c65da340 100644 @@ -54,15 +56,17 @@ index b3d12f977c06..36026f5adf6e 100644 +CFLAGS_sun5i-eink-neon.o += -march=armv7-a -mfloat-abi=softfp -mfpu=neon -ffreestanding -isystem $(shell $(CC) -print-file-name=include) diff --git a/drivers/video/fbdev/sun5i-eink-neon.c b/drivers/video/fbdev/sun5i-eink-neon.c new file mode 100644 -index 000000000000..9e2386fd91ea +index 000000000000..e1eca7be81c1 --- /dev/null +++ b/drivers/video/fbdev/sun5i-eink-neon.c -@@ -0,0 +1,49 @@ +@@ -0,0 +1,51 @@ +#include +#include +#include +#include + ++#include "sun5i-eink.h" ++ +void eink_ctlstream_fill_data_neon(u32* cmd, u8* fb, int stride, + int sources, int gates, u32 masks[4]) +{ @@ -109,10 +113,10 @@ index 000000000000..9e2386fd91ea +EXPORT_SYMBOL_GPL(eink_ctlstream_fill_data_neon); diff --git a/drivers/video/fbdev/sun5i-eink.c b/drivers/video/fbdev/sun5i-eink.c new file mode 100644 -index 000000000000..fbc2cbaedb22 +index 000000000000..e8c45e628cc7 --- /dev/null +++ b/drivers/video/fbdev/sun5i-eink.c -@@ -0,0 +1,1156 @@ +@@ -0,0 +1,1155 @@ +/* + * Copyright Ondrej Jirman + */ @@ -141,6 +145,8 @@ index 000000000000..fbc2cbaedb22 +#include +#include + ++#include "sun5i-eink.h" ++ +// {{{ Registry defines + +#define SUN4I_TCON_GCTL_REG 0x0 @@ -488,9 +494,6 @@ index 000000000000..fbc2cbaedb22 + SET_PINS(r, G_SP | S_SP ); +} + -+void eink_ctlstream_fill_data_neon(u32* cmd, u8* fb, int stride, -+ int sources, int gates, u32 masks[4]); -+ +static void eink_ctlstream_fill_data(struct eink_dev* eink, u8* fb) +{ + const struct eink_panel_config* pc = eink->panel; @@ -531,7 +534,7 @@ index 000000000000..fbc2cbaedb22 + mod_timer(&eink->powerdown_timer, + jiffies + msecs_to_jiffies(5000)); + else -+ del_timer_sync(&eink->powerdown_timer); ++ timer_delete_sync(&eink->powerdown_timer); + + eink->powered = en; + return 0; @@ -1213,7 +1216,7 @@ index 000000000000..fbc2cbaedb22 + + eink_set_power(eink, 0); + -+ del_timer_sync(&eink->powerdown_timer); ++ timer_delete_sync(&eink->powerdown_timer); + cancel_work_sync(&eink->work); + destroy_workqueue(eink->wq); + @@ -1269,6 +1272,19 @@ index 000000000000..fbc2cbaedb22 +MODULE_DESCRIPTION("eInk display Allwinner TCON0 based bit-banging driver"); +MODULE_AUTHOR("Ondrej Jirman "); +MODULE_LICENSE("GPL v2"); +diff --git a/drivers/video/fbdev/sun5i-eink.h b/drivers/video/fbdev/sun5i-eink.h +new file mode 100644 +index 000000000000..bf6b2688a470 +--- /dev/null ++++ b/drivers/video/fbdev/sun5i-eink.h +@@ -0,0 +1,7 @@ ++#ifndef SUN5I_EINK_H ++#define SUN5I_EINK_H ++ ++void eink_ctlstream_fill_data_neon(u32* cmd, u8* fb, int stride, ++ int sources, int gates, u32 masks[4]); ++ ++#endif -- 2.35.3 diff --git a/patch/kernel/sunxi-6.14/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch b/patch/kernel/sunxi-6.16/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch similarity index 100% rename from patch/kernel/sunxi-6.14/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch rename to patch/kernel/sunxi-6.16/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch diff --git a/patch/kernel/sunxi-6.16/patches.megous/wifi-rtw89-Fix-inadverent-sharing-of-struct-ieee80211_supported.patch b/patch/kernel/sunxi-6.16/patches.megous/wifi-rtw89-Fix-inadverent-sharing-of-struct-ieee80211_supported.patch new file mode 100644 index 0000000..0e2088a --- /dev/null +++ b/patch/kernel/sunxi-6.16/patches.megous/wifi-rtw89-Fix-inadverent-sharing-of-struct-ieee80211_supported.patch @@ -0,0 +1,120 @@ +From d1df57a3a54fe840db56edd130991be84752957d Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sun, 27 Apr 2025 02:20:36 +0200 +Subject: wifi: rtw89: Fix inadverent sharing of struct + ieee80211_supported_band data + +Internally wiphy writes to individual channels in this structure, +so we must not share one static definition of channel list between +multiple device instances, because that causes hard to debug +breakage. + +For example, with two rtw89 driven devices in the system, channel +information may get incoherent, preventing channel use. + +Signed-off-by: Ondrej Jirman +--- + drivers/net/wireless/realtek/rtw89/core.c | 51 ++++++++++++++++++----- + 1 file changed, 41 insertions(+), 10 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c +index cc9b014457ac..3455082f5e21 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.c ++++ b/drivers/net/wireless/realtek/rtw89/core.c +@@ -4398,16 +4398,47 @@ static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, + _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); + } + ++static struct ieee80211_supported_band *rtw89_copy_sband(const struct ieee80211_supported_band *sband) ++{ ++ struct ieee80211_supported_band *copy = kmemdup(sband, sizeof(*sband), GFP_KERNEL); ++ ++ if (!copy) ++ return NULL; ++ ++ copy->channels = kmemdup(sband->channels, sizeof(struct ieee80211_channel) * sband->n_channels, GFP_KERNEL); ++ if (!copy->channels) { ++ kfree(copy); ++ return NULL; ++ } ++ ++ copy->bitrates = kmemdup(sband->bitrates, sizeof(struct ieee80211_rate) * sband->n_bitrates, GFP_KERNEL); ++ if (!copy->bitrates) { ++ kfree(copy->channels); ++ kfree(copy); ++ return NULL; ++ } ++ ++ return copy; ++} ++ ++static void rtw89_free_sband(const struct ieee80211_supported_band *sband) ++{ ++ if (sband) { ++ kfree(sband->bitrates); ++ kfree(sband->channels); ++ kfree(sband); ++ } ++} ++ + static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) + { + struct ieee80211_hw *hw = rtwdev->hw; + struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; + struct ieee80211_supported_band *sband_6ghz = NULL; +- u32 size = sizeof(struct ieee80211_supported_band); + u8 support_bands = rtwdev->chip->support_bands; + + if (support_bands & BIT(NL80211_BAND_2GHZ)) { +- sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); ++ sband_2ghz = rtw89_copy_sband(&rtw89_sband_2ghz); + if (!sband_2ghz) + goto err; + rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); +@@ -4416,7 +4447,7 @@ static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) + } + + if (support_bands & BIT(NL80211_BAND_5GHZ)) { +- sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); ++ sband_5ghz = rtw89_copy_sband(&rtw89_sband_5ghz); + if (!sband_5ghz) + goto err; + rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); +@@ -4426,7 +4457,7 @@ static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) + } + + if (support_bands & BIT(NL80211_BAND_6GHZ)) { +- sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); ++ sband_6ghz = rtw89_copy_sband(&rtw89_sband_6ghz); + if (!sband_6ghz) + goto err; + rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); +@@ -4445,9 +4476,9 @@ static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) + kfree((__force void *)sband_5ghz->iftype_data); + if (sband_6ghz) + kfree((__force void *)sband_6ghz->iftype_data); +- kfree(sband_2ghz); +- kfree(sband_5ghz); +- kfree(sband_6ghz); ++ rtw89_free_sband(sband_2ghz); ++ rtw89_free_sband(sband_5ghz); ++ rtw89_free_sband(sband_6ghz); + return -ENOMEM; + } + +@@ -4461,9 +4492,9 @@ static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) + kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); + if (hw->wiphy->bands[NL80211_BAND_6GHZ]) + kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); +- kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); +- kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); +- kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); ++ rtw89_free_sband(hw->wiphy->bands[NL80211_BAND_2GHZ]); ++ rtw89_free_sband(hw->wiphy->bands[NL80211_BAND_5GHZ]); ++ rtw89_free_sband(hw->wiphy->bands[NL80211_BAND_6GHZ]); + hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; + hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; + hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; +-- +2.35.3 + diff --git a/patch/kernel/sunxi-6.14/series.armbian b/patch/kernel/sunxi-6.16/series.armbian similarity index 99% rename from patch/kernel/sunxi-6.14/series.armbian rename to patch/kernel/sunxi-6.16/series.armbian index cf79327..fa855e8 100644 --- a/patch/kernel/sunxi-6.14/series.armbian +++ b/patch/kernel/sunxi-6.16/series.armbian @@ -147,7 +147,6 @@ patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch - patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch diff --git a/patch/kernel/sunxi-6.14/series.conf b/patch/kernel/sunxi-6.16/series.conf similarity index 92% rename from patch/kernel/sunxi-6.14/series.conf rename to patch/kernel/sunxi-6.16/series.conf index c844954..00d13fe 100644 --- a/patch/kernel/sunxi-6.14/series.conf +++ b/patch/kernel/sunxi-6.16/series.conf @@ -51,7 +51,7 @@ patches.megous/media-gc2145-implement-system-suspend.patch patches.megous/media-gc2145-fix-white-balance-colors.patch patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch - patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch +- patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch @@ -155,35 +155,25 @@ patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch - patches.megous/misc-modem-power-Power-manager-for-modems.patch +- patches.megous/misc-modem-power-Power-manager-for-modems.patch patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch - patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch - patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch - patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch - patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch patches.megous/Fix-intptr_t-typedef.patch patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch - patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch - patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch - patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch - patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch +- patches.megous/wifi-rtw89-Fix-inadverent-sharing-of-struct-ieee80211_supported.patch patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch -- patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch -- patches.megous/drm-sun4i-Implement-gamma-correction.patch patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch -- patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch @@ -193,8 +183,6 @@ patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch - patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch - patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch @@ -245,7 +233,6 @@ patches.megous/Add-support-for-my-private-Sapomat-device.patch patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch -- patches.megous/Add-README.md-with-information-and-u-boot-patches.patch patches.megous/Defconfigs-for-all-my-devices.patch ################################################################################ @@ -272,26 +259,25 @@ patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch - patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch +- patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch - patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch +- patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch patches.drm/add-TCON-global-control-reg-for-pad-selection.patch - patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch - patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch - patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch - patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch - patches.drm/drm-panfrost-Add-PM-runtime-flags.patch - patches.drm/drm-panfrost-add-h616-compatible-string.patch - patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch +- patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch +- patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch +- patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch +- patches.drm/drm-panfrost-Add-PM-runtime-flags.patch +- patches.drm/drm-panfrost-add-h616-compatible-string.patch +- patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch ################################################################################ # -# media patches +# media # ################################################################################ patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch @@ -308,7 +294,7 @@ ################################################################################ patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch - patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch +- patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch patches.armbian/Revert-drm-sun4i-hdmi-switch-to-struct-drm_edid.patch @@ -330,7 +316,7 @@ patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch - patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch +- patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch @@ -343,7 +329,7 @@ patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch patches.armbian/Fix-include-uapi-spi-spidev-module.patch patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch - patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch +- patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch @@ -391,7 +377,7 @@ patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch - patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch +- patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch @@ -413,7 +399,7 @@ patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch - patches.armbian/scripts-add-overlay-compilation-support.patch +- patches.armbian/scripts-add-overlay-compilation-support.patch patches.armbian/Enable-creation-of-__symbols__-node.patch patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch @@ -426,6 +412,8 @@ patches.armbian/cb1-overlay.patch patches.armbian/Correct-perf-interrupt-source-number-as-referenced-in-the-Allwi.patch patches.armbian/Enable-DMA-support-for-the-Allwinner-A10-EMAC-which-already-exi.patch + patches.armbian/arm-dts-sun4i-pcduino2-add-hdmi.patch + patches.armbian/arm-dts-sun7i-pcduino3-add-hdmi.patch patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch @@ -433,7 +421,7 @@ patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch - patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch +- patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch @@ -442,7 +430,7 @@ patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch - patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch +- patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch @@ -450,7 +438,6 @@ patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch - patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch @@ -470,13 +457,12 @@ patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-pwm-uart.patch - patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch +- patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch patches.armbian/add-dtb-overlay-for-zero2w.patch patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-HDMI.patch patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-EMAC1.patch patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch - patches.armbian/Add-board-BananaPi-BPI-M4-Zero.patch patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch diff --git a/patch/kernel/sunxi-6.14/series.drm b/patch/kernel/sunxi-6.16/series.drm similarity index 96% rename from patch/kernel/sunxi-6.14/series.drm rename to patch/kernel/sunxi-6.16/series.drm index f6693de..0710965 100644 --- a/patch/kernel/sunxi-6.14/series.drm +++ b/patch/kernel/sunxi-6.16/series.drm @@ -33,7 +33,6 @@ patches.drm/add-TCON-global-control-reg-for-pad-selection.patch patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch - patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch patches.drm/drm-panfrost-Add-PM-runtime-flags.patch patches.drm/drm-panfrost-add-h616-compatible-string.patch diff --git a/patch/kernel/sunxi-6.14/series.media b/patch/kernel/sunxi-6.16/series.media similarity index 100% rename from patch/kernel/sunxi-6.14/series.media rename to patch/kernel/sunxi-6.16/series.media diff --git a/patch/kernel/sunxi-6.14/series.megous b/patch/kernel/sunxi-6.16/series.megous similarity index 94% rename from patch/kernel/sunxi-6.14/series.megous rename to patch/kernel/sunxi-6.16/series.megous index 1773cf5..3a270da 100644 --- a/patch/kernel/sunxi-6.14/series.megous +++ b/patch/kernel/sunxi-6.16/series.megous @@ -159,30 +159,20 @@ patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch - patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch - patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch - patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch - patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch patches.megous/Fix-intptr_t-typedef.patch patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch - patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch - patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch - patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch - patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch + patches.megous/wifi-rtw89-Fix-inadverent-sharing-of-struct-ieee80211_supported.patch patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch - patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch - patches.megous/drm-sun4i-Implement-gamma-correction.patch patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch - patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch @@ -192,8 +182,6 @@ patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch - patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch - patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch @@ -244,5 +232,4 @@ patches.megous/Add-support-for-my-private-Sapomat-device.patch patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch - patches.megous/Add-README.md-with-information-and-u-boot-patches.patch patches.megous/Defconfigs-for-all-my-devices.patch diff --git a/patch/kernel/x_rk3566_clock_fixes.patch b/patch/kernel/x_rk3566_clock_fixes.patch deleted file mode 100644 index 60a8d7b..0000000 --- a/patch/kernel/x_rk3566_clock_fixes.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- kernel/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi.old 2025-07-06 20:36:43.730388402 +0200 -+++ kernel/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi 2025-07-06 20:34:36.687531470 +0200 -@@ -336,6 +336,7 @@ - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; -+ clock-output-names = "rk808-clkout1", "rk808-clkout2"; - pinctrl-names = "default", "pmic-sleep", - "pmic-power-off", "pmic-reset"; - pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; diff --git a/patch/uboot/btt/btt_pi2_support.patch b/patch/uboot/btt/btt_pi2_support.patch index dbe74ad..dab5045 100644 --- a/patch/uboot/btt/btt_pi2_support.patch +++ b/patch/uboot/btt/btt_pi2_support.patch @@ -1,28 +1,3 @@ -diff '--color=auto' -Naur uboot_btt_pi2_or/arch/arm/dts/rk3566-btt-pi2.dts uboot_btt_pi2/arch/arm/dts/rk3566-btt-pi2.dts ---- uboot_btt_pi2_or/arch/arm/dts/rk3566-btt-pi2.dts 1970-01-01 01:00:00.000000000 +0100 -+++ uboot_btt_pi2/arch/arm/dts/rk3566-btt-pi2.dts 2024-12-25 14:33:13.750360443 +0100 -@@ -0,0 +1,3 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include -diff '--color=auto' -Naur uboot_btt_pi2_or/arch/arm/dts/rk3566-btt-pi2.dtsi uboot_btt_pi2/arch/arm/dts/rk3566-btt-pi2.dtsi ---- uboot_btt_pi2_or/arch/arm/dts/rk3566-btt-pi2.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ uboot_btt_pi2/arch/arm/dts/rk3566-btt-pi2.dtsi 2024-12-25 14:33:00.070527818 +0100 -@@ -0,0 +1,14 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include "rk356x-u-boot.dtsi" -+ -+&gpio4 { -+ bootph-pre-ram; -+}; -+ -+&sfc { -+ flash@0 { -+ bootph-pre-ram; -+ bootph-some-ram; -+ }; -+}; diff '--color=auto' -Naur uboot_btt_pi2_or/arch/arm/mach-rockchip/rk3568/Kconfig uboot_btt_pi2/arch/arm/mach-rockchip/rk3568/Kconfig --- uboot_btt_pi2_or/arch/arm/mach-rockchip/rk3568/Kconfig 2025-06-27 23:33:08.241020412 +0200 +++ uboot_btt_pi2/arch/arm/mach-rockchip/rk3568/Kconfig 2025-06-27 23:43:47.734346143 +0200 @@ -83,7 +58,7 @@ diff '--color=auto' -Naur uboot_btt_pi2_or/board/btt/btt_pi2/btt_pi2.c uboot_btt +}; + +static const struct board_model board_models[] = { -+ { 0, "btt/rk3566-btt-pi2-v1.0.1.dtb", "rk3566-btt-pi2-v1.0.1.dtb" }, ++ { 0, "rk3566-bigtreetech-pi2.dtb" }, +}; + +static int get_board_value(void) @@ -177,7 +152,7 @@ diff '--color=auto' -Naur uboot_btt_pi2_or/configs/btt-pi2_defconfig uboot_btt_p +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-btt-pi2.dtb" ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-bigtreetech-pi2.dts" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 @@ -249,77 +224,4 @@ diff '--color=auto' -Naur uboot_btt_pi2_or/configs/btt-pi2_defconfig uboot_btt_p +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y -diff '--color=auto' -Naur uboot_btt_pi2_or/dts/upstream/src/arm64/rockchip/rk3566-btt-pi2.dts uboot_btt_pi2/dts/upstream/src/arm64/rockchip/rk3566-btt-pi2.dts ---- uboot_btt_pi2_or/dts/upstream/src/arm64/rockchip/rk3566-btt-pi2.dts 1970-01-01 01:00:00.000000000 +0100 -+++ uboot_btt_pi2/dts/upstream/src/arm64/rockchip/rk3566-btt-pi2.dts 2024-12-25 14:03:08.870311329 +0100 -@@ -0,0 +1,70 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include "rk3566-btt-pi2.dtsi" -+ -+/ { -+ model = "BigTreeTech Pi2 RK3566"; -+ compatible = "btt,pi2", "rockchip,rk3566"; -+ -+ vccio_phy1: regulator-1v8-vccio-phy { -+ compatible = "regulator-fixed"; -+ regulator-name = "vccio_phy1"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <1800000>; -+ }; -+}; -+ -+&pmu_io_domains { -+ vccio5-supply = <&vccio_phy1>; -+}; -+ -+&gmac1 { -+ phy-handle = <&rgmii_phy1>; -+ status = "okay"; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&sdmmc1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ brcmf: wifi@1 { -+ compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; -+ reg = <1>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ interrupt-names = "host-wake"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_wake_host_h>; -+ }; -+}; -+ -+&uart1 { -+ bluetooth { -+ compatible = "brcm,bcm4345c5"; -+ clocks = <&rk809 1>; -+ clock-names = "lpo"; -+ interrupt-parent = <&gpio2>; -+ interrupts = ; -+ interrupt-names = "host-wakeup"; -+ device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_reg_on_h &bt_wake_host_h &host_wake_bt_h>; -+ vbat-supply = <&vcc_3v3>; -+ vddio-supply = <&vcc_1v8>; -+ }; +}; diff --git a/scripts/os.py b/scripts/os.py index 5615a9b..2f0dabd 100644 --- a/scripts/os.py +++ b/scripts/os.py @@ -14,12 +14,13 @@ class OS: self.root_dir = f"{ROOT_DIR}/root" self.mount_dir = f"{ROOT_DIR}/build/mnt_tmp" self.actions = [ - [ "chroot", self.chroot ], - [ "sync", self.sync_repo ], - [ "update", self.update_all ], - [ "reinstall", self.rebuild_all ], - [ "pack", self.pack ], - [ "sqh", self.sqh ] + [ "chroot", self.chroot ], + [ "sync", self.sync_repo ], + [ "update", self.update_all ], + [ "reinstall", self.rebuild_all ], + [ "pack", self.pack ], + [ "sqh", self.sqh ], + [ "sqh_kmod", self.make_sqh_kmod ] ] def __relaunch_as_sudo(self): @@ -81,17 +82,20 @@ class OS: if (dir == ""): dir = self.root_dir Logger.os(text) - self.__sudo(["cp", "/etc/resolv.conf", f"{self.root_dir}/etc/resolv.conf"]) + self.__sudo(["cp", "/etc/resolv.conf", f"{dir}/etc/resolv.conf"]) for step in info["steps"]: if ("file" in step): is_append = "-a" if step["append"] else "" lines = "\n".join(step["lines"]) path = step["file"] directory = Path(path).parent - cmd = f"mkdir -p {self.root_dir}{directory} && echo '{lines}'" - cmd += f" | sudo tee {is_append} {self.root_dir}{path} > /dev/null" + cmd = f"mkdir -p {dir}{directory} && echo '{lines}'" + cmd += f" | sudo tee {is_append} {dir}{path} > /dev/null" Logger.os(f"\tCreate file {path}...") self.__sudo(cmd, shell=True, cwd=dir) + if ("chmod" in step): + mode = step["chmod"] + self.__sudo(f"chmod {mode} {dir}{path}", shell=True, cwd=dir) if ("chroot" in step): cmd = self.board.parse_variables(step["chroot"]) self.__chroot(cmd, dir=dir) @@ -152,6 +156,8 @@ class OS: else: args.insert(0, "sudo") err_n = args[1] + else: + err_n = args p = subprocess.Popen(args, cwd=cwd, env=env, stdout=stdout, stderr=stdout, shell=shell) p.wait() if (p.returncode != 0): @@ -239,8 +245,20 @@ class OS: def __finalize(self, dir): self.__stage3_steps(self.finalize, "Finalize system installation...", dir=dir) - def sqh(self): + def make_sqh_kmod(self): self.__relaunch_as_sudo() + mod_path = f"{ROOT_DIR}/out/modules" + os.makedirs(mod_path, exist_ok=True) + kmod_fn = self.board.parse_variables("%{out_dir}%/kmods/usr/lib/modules") + kmod = Path(kmod_fn) + for f in kmod.iterdir(): + sqh_name = f.name + self.__make_sqh(f"{kmod_fn}/../../..", f"{mod_path}/{sqh_name}.lzm") + break + + def sqh(self): + #self.__relaunch_as_sudo() + self.make_sqh_kmod() date = datetime.datetime.today().strftime('%Y_%m_%d') temp_dir = f"{ROOT_DIR}/build/tmp" # pack full system via tar @@ -255,6 +273,7 @@ class OS: # remove temp directory self.__tmp_clean(temp_dir) self.__extract_tar(arch_path, temp_dir) + self.__sudo(f"rm {temp_dir}/usr/bin/qemu-{self.arch}", shell=True) sqh_fn = f"{ROOT_DIR}/out/root_{date}.sqh" self.__make_sqh(temp_dir, sqh_fn) os.symlink(sqh_fn, f"{ROOT_DIR}/out/root.sqh.tmp") @@ -359,9 +378,8 @@ class OS: if (part_size > (90 * 1024 * 1024)) and (i == idx): # required partition #print(f"\tIdx:{i} Size:{part_size}") - self.__sudo(["losetup", "-o", str(offset), "--sizelimit", - str(part_size), "/dev/loop0", img_or_blk], - cwd=ROOT_DIR)#, stdout=subprocess.DEVNULL) + self.__sudo(f"losetup -o {offset} --sizelimit {part_size} /dev/loop0 {img_or_blk}", + cwd=ROOT_DIR, shell=True)#, stdout=subprocess.DEVNULL) return True i += 1 offset += part_size @@ -388,8 +406,12 @@ class OS: def __copy_file(self, src, dst): Logger.install(f"\tCopy {src}") + dir_ch = Path(src) self.__sudo(["mkdir", "-p", dst], stdout=subprocess.DEVNULL) - self.__sudo(["cp", src, dst], stdout=subprocess.DEVNULL) + if (dir_ch.is_dir()): + self.__sudo(["cp", "-Hr", src, dst], stdout=subprocess.DEVNULL) + else: + self.__sudo(["cp", src, dst], stdout=subprocess.DEVNULL) def __dd_bin(self, src, block_size, offset): blk_sz = self.__parse_size(block_size) @@ -401,15 +423,28 @@ class OS: extl_dir = f"{out_dir}/extlinux" extl_fn = f"{extl_dir}/extlinux.conf" dtb_file = self.board.parse_variables("%{DTB_FILE}%") + dto_dir = self.board.parse_variables("%{DTO_DIR}%") cmd = f"mkdir -p {extl_dir} && touch {out_dir}/livecd && " - cmd += f"echo 'menu title Boot Options.\n\ntimeout 20\ndefault Kernel_def\n\n" - cmd += f"label Kernel_def\n\tkernel /Image\n\tfdtdir /dtb/\n\tdevicetree /dtb/{dtb_file}\n\tinitrd /uInitrd\n' >> {extl_fn}" + cmd += f"echo 'menu title Boot Options.\n\n" + cmd += f"timeout 20\ndefault Kernel_def\n\n" + cmd += f"label Kernel_def\n" + cmd += f"\tkernel /Image\n" + cmd += f"\tfdtdir /dtb/\n" + cmd += f"\tdevicetree /dtb/{dtb_file}\n" + cmd += f"\tinitrd /uInitrd\n" + if ("overlays" in self.board.installs): + overlays = self.board.installs["overlays"] + overlays = " ".join(overlays) + overlays = self.board.parse_variables(overlays) + cmd += f"\tfdtoverlays {overlays}\n" + cmd += f"' >> {extl_fn}" self.__sudo(["sh", "-c", f"{cmd}"], stdout=subprocess.DEVNULL) for target in self.board.targets: target.install_files(out_dir, self.board.out_dir, "boot", self.__copy_file, self.__dd_bin) self.__copy_file(f"{self.board.out_sh}/uInitrd", f"{out_dir}/") Logger.install(f"\tCopy root.sqh") self.__sudo(["cp", "-H", f"{self.board.out_sh}/root.sqh", f"{out_dir}/"]) + self.__sudo(["cp", "-Hr", f"{self.board.out_sh}/modules", f"{out_dir}/"]) def __install_rw(self, out_dir): self.__sudo(["touch", f"{out_dir}/rw_part"], stdout=subprocess.DEVNULL) diff --git a/scripts/sources.py b/scripts/sources.py index 04fbbf8..ffcf3be 100644 --- a/scripts/sources.py +++ b/scripts/sources.py @@ -264,11 +264,19 @@ class Sources: # copy new configurtion, if exists shutil.copyfile(work_cfg_name, cfg_name) + def prepare_artifacts(self, artifacts, out_dir): + for art in artifacts: + if ("kmods" in art): + shutil.rmtree(f"{out_dir}/kmods", ignore_errors=True) + def copy_artifacts(self, artifacts, out_dir): for art in artifacts: + if ("kmods" in art): + continue file_name = self.work_dir + "/" + art["file"] if ("subdir" in art): - dir_o = out_dir + "/" + art["subdir"] + "/" + subdir = art["subdir"] + dir_o = out_dir + "/" + subdir + "/" else: dir_o = out_dir + "/" os.makedirs(dir_o, exist_ok=True) diff --git a/scripts/target.py b/scripts/target.py index 049f811..85bdc3f 100644 --- a/scripts/target.py +++ b/scripts/target.py @@ -72,6 +72,7 @@ class Target: def build(self, sub_target, out_dir): self.source_sync() + self.sources.prepare_artifacts(self.artifacts, out_dir) if (not self.no_build): opts = self.makeopts.split(" ") config = "" @@ -96,9 +97,11 @@ class Target: for art in self.artifacts: art_fn = os.path.basename(art["file"]) if (art["store_type"] == part_name): - subdir = "" if "subdir" in art: subdir = art["subdir"] + "/" - on_file(f"{tmp_dir}/{subdir}{art_fn}", f"{dir}/{subdir}") + destdir = art["destdir"] + "/" + on_file(f"{tmp_dir}/{subdir}", f"{dir}/{destdir}") + else: + on_file(f"{tmp_dir}/{art_fn}", f"{dir}/") if (art["store_type"] == "dd"): on_dd(f"{tmp_dir}/{art_fn}", art["block_size"], int(art["img_offset"]))