From c5b7968c7a8250669ecf04a0b0804f8d79984925 Mon Sep 17 00:00:00 2001
From: The-going <48602507+The-going@users.noreply.github.com>
Date: Wed, 2 Feb 2022 21:01:10 +0300
Subject: arm64:dts:overlay sun50i-h5 add gpio regulator overclock

---
 .../arm64/boot/dts/allwinner/overlay/Makefile |  4 ++
 .../sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso      | 31 ++++++++++
 .../sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso      | 31 ++++++++++
 .../sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso      | 61 +++++++++++++++++++
 .../sun50i-h5-gpio-regulator-1.3v.dtso        | 38 ++++++++++++
 5 files changed, 165 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso
 create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso
 create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso
 create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso

diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
index 8d5ae3e3beb8..9e3def41669e 100644
--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
+++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
@@ -14,6 +14,10 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
 	sun50i-a64-w1-gpio.dtbo \
 	sun50i-h5-analog-codec.dtbo \
 	sun50i-h5-cir.dtbo \
+	sun50i-h5-cpu-clock-1.0GHz-1.1v.dtbo \
+	sun50i-h5-cpu-clock-1.2GHz-1.3v.dtbo \
+	sun50i-h5-cpu-clock-1.3GHz-1.3v.dtbo \
+	sun50i-h5-gpio-regulator-1.3v.dtbo \
 	sun50i-h5-i2c0.dtbo \
 	sun50i-h5-i2c1.dtbo \
 	sun50i-h5-i2c2.dtbo \
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso
new file mode 100644
index 000000000000..674ec1dcbfe4
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso
@@ -0,0 +1,31 @@
+// DT overlay for CPU frequency operating points to up to 1.0GHz at a maximum CPU voltage of 1.1v
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&cpu_opp_table>;
+
+		__overlay__ {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			// in order to match the H5 DT cooling-maps, update the existing OP table in-place
+			// with the new voltages
+
+			opp-960000000 {
+				opp-hz = /bits/ 64 <960000000>;
+				opp-microvolt = <1100000 1100000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+
+			opp-1008000000 {
+				opp-hz = /bits/ 64 <1008000000>;
+				opp-microvolt = <1100000 1100000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+		};
+	};
+};
+
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso
new file mode 100644
index 000000000000..4fb5c81d31d5
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso
@@ -0,0 +1,31 @@
+// DT overlay for CPU frequency operating points to up to 1.2GHz at a maximum CPU voltage of 1.3v
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&cpu_opp_table>;
+
+		__overlay__ {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			// in order to match the H5 DT cooling-maps, update the existing OP table in-place
+			// with the new voltages
+
+			opp-1104000000 {
+				opp-hz = /bits/ 64 <1104000000>;
+				opp-microvolt = <1300000 1300000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+
+			opp-1200000000 {
+				opp-hz = /bits/ 64 <1200000000>;
+				opp-microvolt = <1300000 1300000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+		};
+	};
+};
+
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso
new file mode 100644
index 000000000000..9c633973df8b
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso
@@ -0,0 +1,61 @@
+// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&cpu_opp_table>;
+
+		__overlay__ {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			// in order to match the H5 DT cooling-maps, update the existing OP table in-place
+			// with the new voltages
+
+			opp-1056000000 {
+				opp-hz = /bits/ 64 <1056000000>;
+				opp-microvolt = <1300000 1300000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+
+			opp-1104000000 {
+				opp-hz = /bits/ 64 <1104000000>;
+				opp-microvolt = <1300000 1300000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+
+			opp-1152000000 {
+				opp-hz = /bits/ 64 <1152000000>;
+				opp-microvolt = <1300000 1300000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+
+			opp-1200000000 {
+				opp-hz = /bits/ 64 <1200000000>;
+				opp-microvolt = <1300000 1300000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+
+			opp-1224000000 {
+				opp-hz = /bits/ 64 <1224000000>;
+				opp-microvolt = <1300000 1300000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+
+			opp-1248000000 {
+				opp-hz = /bits/ 64 <1248000000>;
+				opp-microvolt = <1300000 1300000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+
+			opp-1296000000 {
+				opp-hz = /bits/ 64 <1296000000>;
+				opp-microvolt = <1300000 1300000 1300000>;
+				clock-latency-ns = <244144>; /* 8 32k periods */
+			};
+		};
+	};
+};
+
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso
new file mode 100644
index 000000000000..8d2755c3d76f
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso
@@ -0,0 +1,38 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun50i-h5";
+
+	fragment@0 {
+		target-path = "/";
+
+		__overlay__ {
+			reg_vdd_cpux: gpio-regulator {
+				compatible = "regulator-gpio";
+				regulator-name = "vdd-cpux";
+				regulator-type = "voltage";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-ramp-delay = <50>; /* 4ms */
+
+				gpios = <&r_pio 0 6 0>; /* PL6 */
+				enable-active-high;
+				gpios-states = <0x1>;
+				states = <1100000 0x0
+					  1300000 0x1>;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&cpu0>;
+
+		__overlay__ {
+			cpu-supply = <&reg_vdd_cpux>;
+		};
+	};
+};
+
-- 
2.35.3

