From 671801e0eeeedda435cbebf42db4957f59a511ec Mon Sep 17 00:00:00 2001
From: Gunjan Gupta <viraniac@gmail.com>
Date: Fri, 29 Sep 2023 08:26:47 +0000
Subject: [PATCH] Allwinner: Fix incorrect ram size detection for H6 boards

---
 arch/arm/mach-sunxi/dram_helpers.c   | 1 +
 arch/arm/mach-sunxi/dram_sun50i_h6.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index cdf2750f1c5..5758c58e070 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -32,6 +32,7 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val)
 #ifndef CONFIG_MACH_SUNIV
 bool mctl_mem_matches(u32 offset)
 {
+	dsb();
 	/* Try to write different values to RAM at two addresses */
 	writel(0, CFG_SYS_SDRAM_BASE);
 	writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index b332f3a3e4a..4675ec932e3 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -611,6 +611,8 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
 	para->rows = 18;
 	mctl_core_init(para);
 
+	udelay(50);
+
 	for (para->rows = 13; para->rows < 18; para->rows++) {
 		/* 8 banks, 8 bit per byte and 16/32 bit width */
 		if (mctl_mem_matches((1 << (para->rows + para->cols +
@@ -622,6 +624,8 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
 	para->cols = 11;
 	mctl_core_init(para);
 
+	udelay(50);
+
 	for (para->cols = 8; para->cols < 11; para->cols++) {
 		/* 8 bits per byte and 16/32 bit width */
 		if (mctl_mem_matches(1 << (para->cols + 1 +
-- 
2.34.1

