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28 lines
649 B
Systemverilog
28 lines
649 B
Systemverilog
`timescale 1ps/1ps
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module clk_sel
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(
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input wire i_clk1,
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input wire i_clk2,
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input wire i_sel,
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output wire o_clk
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);
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logic and11, and12, and21, and22;
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logic[1:0] sync1, sync2;
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assign and11 = (!i_sel) & (!sync2[1]);
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assign and12 = (!sync1[1]) & i_sel;
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always_ff @(posedge i_clk1)
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sync1 <= { sync1[0], and11 };
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always_ff @(posedge i_clk2)
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sync2 <= { sync2[0], and12 };
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assign and21 = sync1[1] & i_clk1;
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assign and22 = sync2[1] & i_clk2;
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assign o_clk = and21 | and22;
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endmodule
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