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43 lines
1.3 KiB
Systemverilog
43 lines
1.3 KiB
Systemverilog
`timescale 1ps/1ps
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module emulate
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(
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input wire i_clk,
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input wire i_reset_n
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);
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// interfaces to emulator
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logic[31:0] rom1_addr /* verilator public */;
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logic[31:0] rom2_addr /* verilator public */;
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logic[31:0] rom_disk_addr /* verilator public */;
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logic[31:0] rom1_rdata /* verilator public */;
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logic[31:0] rom2_rdata /* verilator public */;
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logic[31:0] rom_disk_rdata /* verilator public */;
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logic[31:0] cfg_sw /* verilator public */;
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orion_pro_top
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#(
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.TURBO_CLK_10 (1'b1)
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)
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u_orion_core
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(
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.i_clk (i_clk),
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.i_reset_n (i_reset_n),
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.i_cfg_sw (cfg_sw[7:0]),
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.o_rom1_addr (rom1_addr[12:0]),
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.o_rom2_addr (rom2_addr[19:0]),
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.o_rom_dsk_addr (rom_disk_addr[19:0]),
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.i_rom1_rdata (rom1_rdata[7:0]),
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.i_rom2_rdata (rom2_rdata[7:0]),
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.i_rom_dsk_rdata (rom_disk_rdata[7:0])
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);
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initial
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begin
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rom1_addr = '0;
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rom2_addr = '0;
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rom_disk_addr = '0;
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end
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endmodule
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