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21 lines
413 B
Systemverilog
21 lines
413 B
Systemverilog
`timescale 1ps/1ps
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module tb_top
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(
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input wire i_clk,
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input wire i_reset_n
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);
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orion_pro_top
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#(
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.TURBO_CLK_10 (1'b1)
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)
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u_orion_core
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(
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.i_clk (i_clk),
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.i_reset_n (i_reset_n),
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.i_cfg_sw (8'b0000_1111)
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);
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endmodule
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